MC68HC05E5P [FREESCALE]
General Release Specification; 常规版本规格
| 型号： | MC68HC05E5P |
| 厂家： | 
Freescale |
| 描述： | General Release Specification |
| 文件： | 总140页 (文件大小：3399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
HC05E5GRS/D
REV. 1.0
MC68HC05E5
Ge ne ra l Re le a se Sp e c ific a tion
Fe b rua ry 3, 1997
CSIC MCU De sig n Ce nte r
Austin, Te xa s
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Ge ne ra l Re le a se Sp e c ifia tion
MC68HC05E5 — Rev. 1.0
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05E5
List of Se c tions
Se c tion 1. Ge ne ra l De sc rip tion . . . . . . . . . . . . . . . . . . . 15
Se c tion 2. Me m ory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Se c tion 3. Ce ntra l Proc e ssing Unit (CPU) . . . . . . . . . . . 27
Se c tion 4. Inte rrup ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Se c tion 5. Re se ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Se c tion 6. Op e ra ting Mod e s . . . . . . . . . . . . . . . . . . . . . 45
Se c tion 7. Inp ut/ Outp ut (I/ O) Ports . . . . . . . . . . . . . . . . 49
Se c tion 8. Tim e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Se c tion 9. Pha se -Loc ke d Loop (PLL) Synthe sis . . . . . . 59
Se c tion 10. Com p ute r Op e ra ting
Prop e rly (COP) Wa tc hd og . . . . . . . . . . 65
Se c tion 11. Motorola Bus (M Bus) Inte rfa c e . . . . . . . . . 69
Se c tion 12. Sync hronous Se ria l Inte rfa c e (SSI) . . . . . . 93
Se c tion 13. Instruc tion Se t . . . . . . . . . . . . . . . . . . . . . . 105
Se c tion 14. Ele c tric a l Sp e c ific a tions . . . . . . . . . . . . . . 123
Se c tion 15. Me c ha nic a l Da ta . . . . . . . . . . . . . . . . . . . 133
Se c tion 16. Ord e ring Inform a tion . . . . . . . . . . . . . . . . 135
MC68HC05E5 — Rev. 1.0
General Release Specification
List of Sections
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
List of Se c tions
General Release Specification
MC68HC05E5 — Rev. 1.0
List of Sections
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05E5
Ta b le of Conte nts
Se c tion 1. Ge ne ra l De sc rip tion
1.1
1.2
1.3
1.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
V
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DD SS
IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PB0–PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PC0–PC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DDSYN
Se c tion 2. Me m ory
2.1
2.2
2.3
2.4
2.5
2.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Se c tion 3. Ce ntra l Proc e ssing Unit (CPU)
3.1
3.2
3.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MC68HC05E5 — Rev. 1.0
General Release Specification
Table of Contents
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Ta b le of Conte nts
3.4
Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.5
3.6
3.7
Se c tion 4. Inte rrup ts
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . .33
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Custom Periodic Interrupt (CPI) . . . . . . . . . . . . . . . . . . . . . . . .37
Synchronous Serial Interface Interrupt (SSI) . . . . . . . . . . . . . .38
2
M-Bus (I C) Interrupt (M Bus). . . . . . . . . . . . . . . . . . . . . . . . . .38
4.10 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.11 Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .38
Se c tion 5. Re se ts
5.1
5.2
5.3
5.4
5.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
5.6
Computer Operating Properly Reset (COPR). . . . . . . . . . . . . .43
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
COP During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .43
COP During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .43
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . .44
5.6.1
5.6.2
5.6.3
5.6.4
5.7
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Se c tion 6. Op e ra ting Mod e s
6.1
6.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
General Release Specification
MC68HC05E5 — Rev. 1.0
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Table of Contents
6.3
6.4
Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.5.1
6.5.2
6.5.3
Se c tion 7. Inp ut/ Outp ut (I/ O) Ports
7.1
7.2
7.3
7.4
7.5
7.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Se c tion 8. Tim e r
8.1
8.2
8.3
8.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Timer Control and Status Register . . . . . . . . . . . . . . . . . . . . . .55
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Se c tion 9. Pha se -Loc ke d Loop (PLL) Synthe sis
9.1
9.2
9.3
9.4
9.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Phase-Locked Loop Control Register. . . . . . . . . . . . . . . . . . . .61
Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .63
Noise Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Se c tion 10. Com p ute r Op e ra ting
Prop e rly (COP) Wa tc hd og
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
10.3 System Control and Status Register. . . . . . . . . . . . . . . . . . . . .66
10.4 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
10.5 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
MC68HC05E5 — Rev. 1.0
General Release Specification
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Ta b le of Conte nts
Se c tion 11. Motorola Bus (M Bus) Inte rfa c e
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
11.3 M-Bus Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
11.4 M-Bus System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .71
11.5 M-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.5.8
Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Slave Address Transmission. . . . . . . . . . . . . . . . . . . . . . . .73
Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Repeated Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Stop Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Clock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
11.6 M-Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
M-Bus Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .76
M-Bus Frequency Divider Register . . . . . . . . . . . . . . . . . . .78
M-Bus Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .80
M-Bus Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
M-Bus Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . .84
11.7 M-Bus Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.8 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.8.1
11.8.2
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Generation of a Start Signal and the First Byte
of Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Software Responses after Transmission or Reception
of a Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Generation of the Stop Signal . . . . . . . . . . . . . . . . . . . . . . .89
Generation of a Repeated Start Signal . . . . . . . . . . . . . . . .90
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
11.8.3
11.8.4
11.8.5
11.8.6
11.8.7
11.9 Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .91
11.10 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .91
General Release Specification
MC68HC05E5 — Rev. 1.0
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Se c tion 12. Sync hronous Se ria l Inte rfa c e (SSI)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
12.3 SSI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.3.1
12.3.2
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Serial Data Input/Output (SDIO) . . . . . . . . . . . . . . . . . . . . .96
12.4 SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
12.4.1
12.4.2
12.4.3
SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
SSI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
SSI Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . .102
12.5 SSI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
12.6 SSI During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.7 SSI Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Se c tion 13. Instruc tion Se t
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
13.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
13.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .110
Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . .111
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .112
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .114
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
13.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
MC68HC05E5 — Rev. 1.0
General Release Specification
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Se c tion 14. Ele c tric a l Sp e c ific a tions
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
14.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
14.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .125
14.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
14.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .126
14.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
14.8 M-Bus Interface Input Signal Timing. . . . . . . . . . . . . . . . . . . .130
14.9 M-Bus Interface Output Signal Timing . . . . . . . . . . . . . . . . . .130
Se c tion 15. Me c ha nic a l Da ta
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
15.3 28-Pin Plastic Dual-in-Line Package
(Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
15.4 28-Pin Small Outline Integrated Circuit Package
(Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Se c tion 16. Ord e ring Inform a tion
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
16.3 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
16.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .136
16.5 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .137
16.6 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .138
16.7 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
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List of Fig ure s
Figure
Title
Page
1-1
1-2
1-3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Single-Chip Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3-1
3-2
3-3
3-4
3-5
3-6
3-7
Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . .29
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4-1
4-2
4-3
Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .35
STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Custom Periodic Interrupt Control
and Status Register (CPICSR) . . . . . . . . . . . . . . . . . . . .37
5-1
5-2
Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
RESET and POR Timing Diagram . . . . . . . . . . . . . . . . . . . .41
7-1
Port I/O Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
8-1
8-2
8-3
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Timer Control and Status Register (TCSR) . . . . . . . . . . . . .55
Timer Counter Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .57
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List of Fig ure s
Figure
Title
Page
9-1
9-2
PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Phase-Locked Loop Control Register (PLLCR) . . . . . . . . . .61
10-1
System Control and Status Register (SCSR). . . . . . . . . . . .66
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
M-Bus Transmission Signal Diagram. . . . . . . . . . . . . . . . . .72
Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
M-Bus Address Register (MADR) . . . . . . . . . . . . . . . . . . . .76
M-Bus Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . .77
M-Bus Frequency Divider Register (MFDR). . . . . . . . . . . . .78
M-Bus Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . .80
M-Bus Status Register (MSR) . . . . . . . . . . . . . . . . . . . . . . .82
M-Bus Data I/O Register (MDR). . . . . . . . . . . . . . . . . . . . . .84
Flowchart of M-Bus Interrupt Routine. . . . . . . . . . . . . . . . . .85
12-1
12-2
12-3
12-4
12-5
12-6
SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Synchronous Serial Interface Timing (CPOL = 1) . . . . . . . .97
Synchronous Serial Interface Timing (CPOL = 0) . . . . . . . .97
SSI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . .98
SSI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . .101
SSI Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . .102
14-1
14-2
14-3
14-4
14-5
Maximum Supply Current versus Operating Frequency . .127
Typical Supply Current versus Operating Frequency. . . . .127
External Interrupt Mode Diagram . . . . . . . . . . . . . . . . . . . .128
Power-On Reset and RESET. . . . . . . . . . . . . . . . . . . . . . .129
M-Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .131
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List of Ta b le s
Table
4-1
Title
Page
Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . .32
COP Watchdog Timer Recommendations . . . . . . . . . . . . . . .44
Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .45
I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
RTI Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
PS1 and PS0 Speed Selects with 32.768-kHz Crystal. . . . . .62
5-1
6-1
7-1
8-1
9-1
10-1
11-1
12-1
COP Rates at f
= 32.768 kHz. . . . . . . . . . . . . . . . . . . . . . .67
osc
M-Bus Clock Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Master Mode SCK Frequency Select . . . . . . . . . . . . . . . . . .100
13-1
13-2
13-3
13-4
13-5
13-6
13-7
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .110
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .111
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .113
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .114
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
16-1
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05E5
Se c tion 1. Ge ne ra l De sc rip tion
1.1 Conte nts
1.2
1.3
1.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
V
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DD SS
IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PB0–PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PC0–PC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DDSYN
1.2 Introd uc tion
The MC68HC05E5 is a low-cost introduction to the M68HC05 Family of
microcontrollers (MCUs). The HC05 central processing unit (CPU) core
has been enhanced with a 15-stage multifunctional timer and
programmable phase-locked loop (PLL). The MCU is available in a
28-pin package and has two 8-bit input/output (I/O) ports and one 4-bit
I/O port. The 8-Kbyte memory map includes 384 bytes of random access
memory (RAM) and 5120 bytes of user read-only memory (ROM). The
MC68HC705E5 serves as an erasable, programmable ROM (EPROM)
based emulation device for the MC68HC05E5.
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Ge ne ra l De sc rip tion
1.3 Fe a ture s
Features of the MC68HC05E5 include:
• Low Cost
• HC05 Core
• 28-Pin Package
• On-Chip Oscillator (Crystal or Ceramic Resonator)
• Phase-Locked Loop (PLL) Synthesizer with Programmable Speed
• Synchronous Serial Interface (SSI) with Interrupts and Most
Significant Bit (MSB) or Least Significant Bit (LSB) First
2
• M-Bus (I C) Communication Port
• 5120 Bytes of User ROM (Including 16 Bytes of User Vectors)
• 384 Bytes of On-Chip RAM
• 15-Stage Multifunctional Timer with Programmable Input
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog Timer Mask
Option
• Custom Periodic Interrupt Circuit
• 20 Bidirectional I/O Lines
• Single-Chip Mode
• Self-Check Mode
• Power-Saving Stop and Wait Modes
• Edge-Only Sensitive or Edge- and Level-Sensitive Interrupt
Trigger Mask Option
• STOP Instruction Disable Mask Option
• System Control and Status Register
• Illegal Address Reset
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General Description
Features
V
DD
V
COP
SYSTEM
SS
CUSTOM
PERIODIC
INTERRUPT
OSC2
OSC1
OSCILLATOR
OSCOUT
I2C
SYSTEM
V
PLL
SYNTHESIS
DDSYN
CLOCK
SELECT
÷ 2
XFC
TPLL
SSI
SYSTEM
TIMER
SYSTEM
C
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RESET
IRQ
CPU
ALU
CONTROL
M68HC05 CPU
CPU REGISTERS
ACCUMULATOR
INDEX REGISTER
STACK POINTER
PB0
PB1
PROGRAM COUNTER
CONDITION CODE REGISTER
PB2
PB3/TIPL
PB4/SCK
PB5/SDI/SDO
PB6/SDA
PB7/SCL
SRAM — 384 BYTES
ROM — 4608 BYTES
PC0
PC1
PC2
PC3
SELF-CHECK ROM — 240 BYTES
Figure 1-1. Block Diagram
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Ge ne ra l De sc rip tion
1.4 Ma sk Op tions
The M68HC05E5 has four mask options:
1. STOP instruction (enable/disable)
2. IRQ (edge-sensitive only or edge- and level-sensitive)
3. COP watchdog timer (enable/disable)
4. CPI Rate (1 second, 0.5 second, or 0.25 second)
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active low.
1.5 Func tiona l Pin De sc rip tion
Figure 1-2 shows the single-chip mode pinout for the MC68HC05E5.
Refer to the following subsections for a description of the pins.
IRQ
RESET
OSC1
XFC
V
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
DDSYN
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
3
OSC2
4
PB7/SCL
PB6/SDA
PB5/SDIO
PB4/SCK
PB3/TIPL
PB2
5
6
7
8
9
10
11
12
13
14
PB1
PB0
V
DD
V
SS
Figure 1-2. Single-Chip Mode Pinout
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General Description
Functional Pin Description
1.5.1 V a nd V
DD
SS
Power is supplied to the microcontroller using these two pins. V is the
DD
positive supply and V is ground.
SS
1.5.2 IRQ
The maskable interrupt request (IRQ) has a programmable option that
provides two different choices of interrupt triggering sensitivity. The
options are:
1. Negative edge-sensitive triggering only
2. Both negative edge-sensitive and level-sensitive triggering
The MCU completes the current instruction before it responds to the
interrupt request. When IRQ goes low for at least one t , a logic 1 is
ILIH
latched internally to signify an interrupt has been requested. When the
MCU completes its current instruction, the interrupt latch is tested. If the
interrupt latch contains a logic 1, and the interrupt mask bit (I bit) in the
condition code register is clear, the MCU then begins the interrupt
sequence.
If the option is selected to include level-sensitive triggering, the IRQ input
requires an external resistor to V for wired-OR operation.
DD
The IRQ pin contains an internal Schmitt trigger as part of its input to
improve noise immunity. Refer to Section 4. Interrupts for more detail.
NOTE: The voltage on the IRQ pin affects the mode of operation. For additional
information, see Section 6. Operating Modes.
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1.5.3 OSC1 a nd OSC2
These pins provide control input for an on-chip clock oscillator circuit
which can optionally drive a PLL clock. A crystal, a ceramic resonator, or
an external signal connects to these pins providing a system clock. The
oscillator frequency is two times the internal bus rate if the PLL is not
used.
Crystal
Figure 1-3 (a) shows the recommended circuit for using a crystal. The
crystal and components should be mounted as close as possible to
the input pins to minimize output distortion and startup stabilization
time.
Ceramic Resonator
A ceramic resonator may be used in place of the crystal in
cost-sensitive applications. Figure 1-3 (a) shows the recommended
circuit for using a ceramic resonator. The manufacturer of the
particular ceramic resonator being considered should be consulted
for specific information.
External Clock
An external clock should be applied to the OSC1 input with the OSC2
pin not connected (refer to Figure 1-3 (b)). This setup can be used if
the user does not wish to run the CPU with a 32.768-kHz crystal or
the PLL frequencies are not suitable for the application.
MCU
MCU
OSC2
OSC1
OSC2
OSC1
330 kΩ
20 MΩ
UNCONNECTED
<
EXTERNAL CLOCK
32.768 kHz
10 pF
33 pF
(a) Crystal/Ceramic Resonator
Oscillator Connections
(b) External Clock Source
Connections
Figure 1-3. Oscillator Connections
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Functional Pin Description
1.5.4 RESET
This active low pin is used to reset the MCU to a known startup state by
pulling RESET low. The RESET pin contains an internal Schmitt trigger
as part of its input to improve noise immunity. See Section 5. Resets for
additional information.
1.5.5 PA0–PA7
These eight I/O lines comprise port A. The state of any pin is software
programmable and all port A lines are configured as input during
power-on or reset. See 7.6 Input/Output Programming for additional
information.
1.5.6 PB0–PB7
These eight I/O lines comprise port B. The state of any pin is software
programmable and all port B lines are configured as input during
power-on or reset. PB7 (SCL) and PB6 (SDA) can be configured as an
M-bus interface. (Refer to Section 11. Motorola Bus (M Bus) Interface
for M-bus pin configurations). PB3–PB5 (TIPL, SCK, and SDIO) can be
configured as a synchronous serial interface (SSI). Refer to Section 12.
Synchronous Serial Interface (SSI) and to 7.6 Input/Output
Programming for additional information.
1.5.7 PC0–PC3
These four I/O lines comprise port C. The state of any pin is software
programmable and all port C lines are configured as input during
power-on or reset. 7.6 Input/Output Programming for additional
information.
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1.5.8 XFC
This pin provides a means for connecting an external filter capacitor to
the synthesizer PLL filter. For additional information concerning this
capacitor, see Section 9. Phase-Locked Loop (PLL) Synthesis.
1.5.9 V
DDSYN
This pin provides a separate power connection to the PLL synthesizer
which should be at the same potential as V .
DD
NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic
level (either V or V ). Although the I/O ports of the MC68HC05E5 do
DD
SS
not require termination, it is recommended to reduce the possibility of
static damage.
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Se c tion 2. Me m ory
2.1 Conte nts
2.2
2.3
2.4
2.5
2.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2 Introd uc tion
The MC68HC05E5 has an 8-Kbyte memory map, consisting of user
read-only memory (ROM), user random access memory (RAM),
self-check ROM, control registers, and input/output (I/O). Refer to
Figure 2-1 for the memory map and Figure 2-2 for the register map.
2.3 ROM
2.4 RAM
The user ROM consists of 5120 bytes located from $0B00 to $1EFF,
with 16 additional bytes of user vectors from $1FF0 to $1FFF. The
self-check ROM and vectors are located from $1F00 to $1FEF.
The user RAM, including the stack area, consists of 384 bytes located
from $0080 to $01FF. The stack begins at address $00FF. The stack
pointer can access 64 bytes of RAM from $00FF to $00C0. Using the
stack area for data storage or temporary work locations requires care to
prevent it from being overwritten due to stacking from an interrupt or
subroutine call.
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Me m ory
2.5 Me m ory Ma p
$0000
0000
PORT A DATA REGISTER
$00
$01
$02
$03
$04
$05
$06
$07
I/O
32 BYTES
PORT B DATA REGISTER
PORT C DATA REGISTER
$001F
$0020
0031
0032
UNUSED
96 BYTES
UNUSED
$007F
$0080
0127
0128
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
PLL CONTROL REGISTER
RAM
128 BYTES
$00BF
$00C0
0191
0192
STACK
64 BYTES
$00FF
$0100
0255
0256
RAM
256 BYTES
TIMER CONTROL & STATUS REGISTER $08
$01FF
$0200
0511
0512
TIMER COUNTER REGISTER
$09
SSI REGISTERS
UNUSED
$0A-$0C
$0D-$11
UNUSED
2304 BYTES
$0AFF
$0B00
2815
2816
CPI CONTROL & STATUS REGISTER
$12
SCSR REGISTER
I2C (M -BUS)
REGISTERS
$13
$18
USER ROM
5120 BYTES
$1EFF
$1F00
7935
7936
$1C
$1D
SELF-CHECK ROM
& VECTORS
UNUSED
240 BYTES
$1E
$1F
$1FEF
$1FF0
8175
8176
RESERVED
UNUSED
USER VECTORS
16 BYTES
$1FFF
8191
$1FF0
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
UNUSED
M BUS VECTOR (HIGH BYTE)
M BUS VECTOR (LOW BYTE)
SSI VECTOR (HIGH BYTE)
SSI VECTOR (LOW BYTE)
CPI VECTOR (HIGH BYTE)
CPI VECTOR (LOW BYTE)
TIMER VECTOR (HIGH BYTE)
TIMER VECTOR (LOW BYTE)
IRQ VECTOR (HIGH BYTE)
IRQ VECTOR (LOW BYTE)
SWI VECTOR (HIGH BYTE)
SWI VECTOR (LOW BYTE)
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
Figure 2-1. Memory Map
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Memory
Register Summary
2.6 Re g iste r Sum m a ry
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
Register
Port A Data Register
Bit 7
6
5
4
3
2
1
Bit 0
Port B Data Register
Port C Data Register
Unimplemented
0
0
0
0
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
PLL Control Register
Timer Control and Status Register.
Timer Counter Register
SSI Control Register
SSI Status Register
0
BCS
RTIF
0
BWC
RTIE
PLLON VCOTST
PS1
RT1
PS0
RT0
TOF
TOFE
TOFA
RTIFA
SIE
SF
D7
SE
DCOL
D6
LSBF
0
MSTR
0
CPOL
0
SDIR
0
SR1
0
SR0
TIPL
D0
SSI Data Register
D5
D4
D3
D2
D1
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
CPI Control and Status Register.
System Control and Status Register
Unimplemented
—
0
CPIF
0
—
0
CPIE
—
—
—
—
STOPR ILADR
COPR
CRS1
CRS0
Unimplemented
Unimplemented
Unimplemented
= Unimplemented
Figure 2-2. I/O Registers
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Me m ory
Addr.
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Register
M-Bus Address Register MAD7
M Bus Frequency Divider Register
Bit 7
6
5
4
3
2
1
Bit 0
MAD6
MAD5
MAD4
FD4
MAD3
FD3
MAD2
FD2
MAD1
FD1
FD0
M Bus Control Register MEN
M Bus Status Register MCF
M Bus Data I/O Register MD7
Unimplemented
MIEN
MAAS
MD6
MSTA
MBB
MD5
MTX
MAL
MD4
TXAK
MMUX
SRW
MD2
MIF
MXAK
MD0
MD3
MD1
Unimplemented
Reserved
R
R
R
R
R
R
R
R
R
= Unimplemented
= Reserved
Figure 2-2. I/O Registers (Continued)
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Se c tion 3. Ce ntra l Proc e ssing Unit (CPU)
3.1 Conte nts
3.2
3.3
3.4
3.5
3.6
3.7
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.2 Introd uc tion
The MCU contains five registers as shown in Figure 3-1. The interrupt
stacking order is shown in Figure 3-2.
7
7
0
A
X
ACCUMULATOR
0
0
0
INDEX REGISTER
12
PC
1
PROGRAM COUNTER
STACK POINTER
12
7
1
0
0
0
0
0
SP
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
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Ce ntra l Proc e ssing Unit (CPU)
7
0
CONDITION CODE REGISTER
ACCUMULATOR
STACK
1
1
1
I
N
T
E
R
R
U
P
R
E
T
U
R
N
INCREASING
MEMORY
ADDRESSES
DECREASING
MEMORY
ADDRESSES
INDEX REGISTER
PCH
T
PCL
UNSTACK
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked
first, followed by PCH, etc. Pulling from the stack is in the reverse
order.
Figure 3-2. Stacking Order
3.3 Ac c um ula tor
The accumulator is a general-purpose 8-bit register used to hold
operands and results of arithmetic calculations or data manipulations.
Bit 7
6
5
4
3
2
1
Bit 0
A
Figure 3-3. Accumulator (A)
3.4 Ind e x Re g iste r
The index register is an 8-bit register used for the indexed addressing
value to create an effective address. The index register may also be
used as a temporary storage area.
Bit 7
6
5
4
3
2
1
Bit 0
X
Figure 3-4. Index Register (X)
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Central Processing Unit (CPU)
Condition Code Register
3.5 Cond ition Cod e Re g iste r
The CCR is a 5-bit register in which the H, N, Z, and C bits are used to
indicate the results of the instruction just executed, and the I bit is used
to enable interrupts. These bits can be tested individually by a program,
and specific actions can be taken as a result of their state. Each bit is
explained in the following paragraphs.
Bit 4
H
3
I
2
1
Z
Bit 0
C
N
Figure 3-5. Condition Code Register (CCR)
Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
Interrupt (I)
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the I bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was zero.
Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit also is affected during bit test and branch instructions and during
shifts and rotates.
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Ce ntra l Proc e ssing Unit (CPU)
3.6 Sta c k Pointe r
The stack pointer contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to location $00FF. The stack pointer then is
decremented as data is pushed onto the stack and incremented as data
is pulled from the stack.
When accessing memory, the seven most significant bits (MSB) are
permanently set to 0000011. These seven bits are appended to the six
least significant register bits to produce an address within the range of
$00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer wraps around
and loses the previously stored information. A subroutine call occupies
two locations on the stack; an interrupt uses five locations.
Bit
12
Bit
0
11
0
10
0
9
0
8
0
7
1
6
5
4
3
2
1
0
SP
Figure 3-6. Stack Pointer (SP)
3.7 Prog ra m Counte r
The program counter is a 13-bit register that contains the address of the
next byte to be fetched.
Bit
12
Bit
0
11
10
9
8
7
6
5
4
3
2
1
PC
Figure 3-7. Program Counter (PC)
NOTE: The HC05 CPU core is capable of addressing 16-bit locations. For this
implementation, however, the addressing registers are limited to an
8-Kbyte memory map.
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Se c tion 4. Inte rrup ts
4.1 Conte nts
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . .33
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Custom Periodic Interrupt (CPI) . . . . . . . . . . . . . . . . . . . . . . . .37
Synchronous Serial Interface Interrupt (SSI) . . . . . . . . . . . . . .38
2
M-Bus (I C) Interrupt (M Bus). . . . . . . . . . . . . . . . . . . . . . . . . .38
4.10 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.11 Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.2 Introd uc tion
The MCU can be interrupted six different ways: the five maskable
hardware interrupts (IRQ, timer, CPI, SSI, and M bus) and the
nonmaskable software interrupt instruction (SWI).
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. The
RTI instruction causes the register contents to be recovered from the
stack and normal processing to resume.
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Inte rrup ts
Unlike RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete. The current instruction is the one already fetched
and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the I-bit
state.
Table 4-1. Vector Address for Interrupts and Reset
Flag
Name
CPU
Interrupt
Vector
Address
Register
Interrupts
N/A
N/A
N/A
N/A
Reset
RESET
SWI
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF8–$1FF9
$1FF6–$1FF7
$1FF4–$1FF5
$1FF2–$1FF3
Software
N/A
N/A
External Interrupt
IRQ
TCSR
N/A
TOF
RTIF
CPIF
SF
Timer Overflow
TIMER
TIMER
CPI
Real-Time Interrupt
Custom Periodic Interrupt
Synchronous Serial Interrupt
M-Bus Interrupt
CPICSR
SSR
SSI
MSR
MIF
M Bus
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Interrupts
Hardware Controlled Interrupt Sequence
4.3 Ha rd wa re Controlle d Inte rrup t Se q ue nc e
The following three functions (RESET, STOP, and WAIT) are not in the
strictest sense an interrupt; however, they are acted upon in a similar
manner. See Figure 4-1 and Figure 4-2. A discussion is provided below.
1. RESET — A low input on the RESET input pin causes the program
to vector to its starting address which is specified by the contents
of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a
known state during this type of reset as described in Section 5.
Resets.
2. STOP — The STOP instruction causes the oscillator to be turned
off and the processor to “sleep” until an external interrupt (IRQ) or
reset occurs.
3. WAIT — The WAIT instruction causes all processor clocks to stop,
but leaves the timer clock running. This “rest” state of the
processor can be cleared by reset, an external interrupt (IRQ), or
timer interrupt. There are no special wait vectors for these
individual interrupts.
4.4 Softwa re Inte rrup t (SWI)
The SWI is an executable instruction and a nonmaskable interrupt. It is
executed regardless of the state of the I bit in the CCR. If the I bit is zero
(interrupts enabled), SWI executes after interrupts which were pending
when the SWI was fetched but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the
contents of memory locations $1FFC and $1FFD.
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Inte rrup ts
4.5 Exte rna l Inte rrup t
If the I bit of the condition code reister (CCR) is set, all maskable
interrupts (internal and external) are disabled. Clearing the I bit enables
interrupts. The interrupt request is latched immediately following the
falling edge of IRQ. It is then synchronized internally and serviced by the
interrupt service routine located at the address specified by the contents
of $1FFA and $1FFB.
Either a level-sensitive and edge-sensitive trigger or an
edge-sensitive-only trigger is available as a mask option.
NOTE: The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I bit is cleared.
4.6 Tim e r Inte rrup t
Two different timer interrupt flags cause a timer interrupt whenever they
are set and enabled. The interrupt flags and enable bits are located in
the timer control and status register (TCSR). Either of these interrupts
will vector to the same interrupt service routine, located at the address
specified by the contents of memory location $1FF8 and $1FF9. For
additional information, refer to 8.3 Timer Control and Status Register.
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Interrupts
Timer Interrupt
FROM
RESET
IS
I BIT
SET?
Y
N
IRQ
CLEAR IRQ
Y
EXTERNAL
INTERRUPT?
REQUEST
LATCH.
N
TIMER
INTERNAL
Y
INTERRUPT?
STACK
PC, X, A, CC.
N
CPI
INTERNAL
Y
SET
INTERRUPT?
I BIT.
N
LOAD PC FROM:
SWI: $1FFC–$1FFD
FETCH NEXT
INSTRUCTION.
IRQ:
$1FFA–$1FFB
TIMER: $1FF8–$1FF9
CPI:
SSI:
$1FF6–$1FF7
$1FF4–$1FF5
N
M BUS: $1FF2–$1FF3
SWI
INSTRUCTION
?
Y
Y
N
RTI
RESTORE RESISTERS
FROM STACK
INSTRUCTION
?
CC, A, X, PC
N
EXECUTE
INSTRUCTION.
Figure 4-1. Interrupt Processing Flowchart
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Inte rrup ts
WAIT
STOP
OSCILLATOR ACTIVE.
TIMER CLOCK ACTIVE.
PROCESSOR CLOCKS
STOPPED.
STOP OSCILLATOR
AND ALL CLOCKS.
CLEAR I BIT.
N
N
RESET?
Y
RESET?
Y
EXTERNAL
INTERRUPT
(IRQ)?
EXTERNAL
INTERRUPT
(IRQ)?
N
N
Y
Y
TIMER
N
INTERNAL
INTERRUPT?
Y
TURN ON OSCILLATOR.
WAIT FOR TIME
DELAY TO STABILIZE.
RESTART
PROCESSOR CLOCK.
CPI, SSI, OR M-BUS
INTERNAL
N
INTERRUPT?
Y
1. FETCH RESET
VECTOR OR
2. SERVICE
INTERRUPT
A. STACK
1. FETCH RESET
VECTOR OR
2. SERVICE
INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
Figure 4-2. STOP/WAIT Flowcharts
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Interrupts
Custom Periodic Interrupt (CPI)
4.7 Custom Pe riod ic Inte rrup t (CPI)
The CPI flag and enable bits are located in the CPI control and status
register (CPICSR). A CPI interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
location $1FF6 and $1FF7.
The custom periodic interrupt is mask programmable to a 0.25 second,
0.5 second, or 1 second interrupt. The interrupt is generated from the
32-kHz OSC1 input by a 15-bit counter. This interrupt is under the
control of the custom periodic interrupt control and status register
located at $12.
Address $0012
Bit 7
6
CPIF
0
5
0
0
4
CPIE
0
3
0
0
2
0
0
1
0
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
Figure 4-3. Custom Periodic Interrupt Control
and Status Register (CPICSR)
CPIF — Custom Periodic Interrupt Flag
CPIF is a clearable, read-only status bit and is set when the 15-bit
counter changes from $7FFF to $0000. A CPU interrupt request will
be generated if CPIE is set. Clearing the CPIF is done by writing a
zero to it. Writing a one to CPIF has no effect on the bit’s value. Reset
clears CPIF.
CPIE — Custom Periodic Interrupt Enable
When this bit is cleared, the CPI interrupts are disabled. When this bit
is set, the CPU interrupt request is generated when the CPIF bit is set.
Reset clears this bit.
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Inte rrup ts
4.8 Sync hronous Se ria l Inte rfa c e Inte rrup t (SSI)
The SSI flag and enable bits are located in the SSI control (SCR) and
status (SSR) registers. An SSI interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
locations $1FF4 and $1FF5. For additional information, refer to 12.4 SSI
Registers.
4.9 M-Bus (I2C) Inte rrup t (M Bus)
The MIF flag and enable bits are located in the M-bus status (MSR) and
control (MCR) registers. An M-bus interrupt will vector to the interrupt
service routine located at the address specified by the contents of
memory locations $1FF2 and $1FF3. For further information, refer to
11.6 M-Bus Registers.
4.10 Op e ra tion During Stop Mod e
The timer system is cleared and the CPI counter is halted when going
into stop mode. When stop mode is exited by an external interrupt or an
external RESET, the internal oscillator will resume, followed by a
4064-cycle internal processor oscillator stabilization delay. The timer
system counter is then cleared and operation resumes. The CPI will
continue counting once the oscillator resumes and does not wait for the
oscillator to stabilize.
4.11 Op e ra tion During Wa it Mod e
The CPU clock halts during wait mode, but the timer and CPI remain
active. A timer interrupt or custom periodic interrupt, SSI, and M bus will
cause the processor to exit wait mode if the interrupts are enabled.
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Se c tion 5. Re se ts
5.1 Conte nts
5.2
5.3
5.4
5.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
5.6
Computer Operating Properly Reset (COPR). . . . . . . . . . . . . .43
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
COP During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .43
COP During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .43
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . .44
5.6.1
5.6.2
5.6.3
5.6.4
5.7
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.2 Introd uc tion
The MCU can be reset from five sources: one external input and four
internal restart conditions. The RESET pin is an input with a Schmitt
trigger as shown in Figure 5-1. All the internal peripheral modules will be
reset by the internal reset signal (RST). Refer to Figure 5-2 for reset
timing detail.
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Re se ts
5.3 Exte rna l Re se t (RESET)
The RESET pin is the only external source of a reset. This pin is
connected to a Schmitt trigger input gate to provide an upper and lower
threshold voltage separated by a minimum amount of hysteresis. This
external reset occurs whenever the RESET pin is pulled below the lower
threshold and remains in reset until the RESET pin rises above the
upper threshold. This active-low input will generate the RST signal and
reset the CPU and peripherals. The only reset sources that can alter the
MCU’s operating mode are termination of the external reset input or the
internal computer operating properly (COP) watchdog reset.
NOTE: Activation of the RST signal is generally referred to as a reset of the
device, unless otherwise specified.
TO IRQ
LOGIC
IRQ/VTST
RESET
D
MODE
LATCH
SELECT
R
(PULSE WIDTH = 3 x E-CLK)
CLOCKED
ONE-SHOT
PH2
OSC
DATA
ADDRESS
COP WATCHDOG
(COPR)
CPU
RST
S
D
TO OTHER
PERIPHERALS
POWER-ON RESET
(POR)
VDD
ADDRESS
STOPEN
LATCH
PH2
ILLEGAL ADDRESS
(ILLADDR)
DISABLED STOP
INSTRUCTION
Figure 5-1. Reset Block Diagram
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Resets
External Reset (RESET)
P
C
N
N
P
1
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Re se ts
The RESET pin can also act as an open-drain output. It will be pulled to
a low state by an internal pulldown that is activated by any reset source.
This RESET pulldown device will be asserted only by three to four cycles
of the internal clock, PH2 (PH2 period = E clock period), or as long as an
internal reset source is asserted. When the external RESET pin is
asserted, the pulldown device will be turned on for the three to four
internal clock cycles only.
5.4 Inte rna l Re se ts
The four internally generated resets are the initial power-on reset
function, the COP watchdog timer reset, the illegal address detector, and
the disabled STOP instruction. The only reset sources that can alter the
MCU’s operating mode are termination of the external RESET input or
the internal COP watchdog timer. The other internal resets will not have
any effect on the mode of operation when their reset state ends. All
internal resets will also assert (pull to logic 0) the external RESET pin for
the duration of the reset or three to four internal clock cycles, whichever
is longer.
5.5 Powe r-On Re se t (POR)
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out). There is
an oscillator stabilization delay of 4064 internal processor clock cycles
after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any
other reset function is active at the end of the 4064-cycle delay, the RST
signal will remain in the reset condition until the other reset condition(s)
end.
POR will activate the RESET pin pulldown device connected to the pin.
V
must drop below V
for the internal POR circuit to detect the next
DD
POR
rise of V .
DD
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Resets
Computer Operating Properly Reset (COPR)
5.6 Com p ute r Op e ra ting Prop e rly Re se t (COPR)
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to timeout, an internal reset is generated
to reset the MCU. Regardless of an internal or external reset, the MCU
comes out of a COP reset according to the standard rules of mode
selection.
The COP reset function is enabled or disabled by a mask option and is
verified during production testing.
The COP watchdog reset will activate the internal pulldown device
connected to the RESET pin.
5.6.1 Re se tting the COP
Preventing a COP reset is done by writing a logic 0 to the COPF bit. This
action will reset the counter and begin the timeout period again. The
COPF bit is bit 0 of address $1FF0. A read of address $1FF0 will return
user data programmed at that location.
5.6.2 COP During Wa it Mod e
The COP will continue to operate normally during wait mode. The
software should pull the device out of wait mode periodically and reset
the COP by writing to the COPF bit to prevent a COP reset.
5.6.3 COP During Stop Mod e
When the stop enable mask option is selected, stop mode disables the
oscillator circuit and thereby turns the clock off for the entire device. The
COP counter will be reset when stop mode is entered. If a reset is used
to exit stop mode, the COP counter will be held in reset during the 4064
cycles of startup delay. If any operable interrupt is used to exit stop
mode, the COP counter will not be reset during the 4064-cycle startup
delay and will have that many cycles already counted when control is
returned to the program.
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Re se ts
5.6.4 COP Wa tc hd og Tim e r Consid e ra tions
If enabled by a mask option, the COP watchdog timer is active in all
modes of operation (disabled in test and self-check modes). If the COP
watchdog timer is selected by a mask option, any execution of the STOP
instruction (either intentional or inadvertent due to the CPU being
disturbed) will cause the oscillator to halt and prevent the COP watchdog
timer from timing out. Therefore, it is recommended that the STOP
instruction should be disabled if the COP watchdog timer is enabled.
If the COP watchdog timer is selected by a mask option, the COP will
reset the MCU when it times out. Therefore, it is recommended that the
COP watchdog should be disabled for a system that must have
intentional uses of the wait mode for periods longer than the COP
timeout period.
The recommended interactions and considerations for the COP
watchdog timer, STOP instruction, and WAIT instruction are
summarized in Figure 5-1.
Table 5-1. COP Watchdog Timer Recommendations
IF the Following Conditions Exist:
THEN the COP Watchdog
Timer Should Be:
STOP Instruction
Wait Time
WAIT Time
Less Than
COP Timeout
Enable or Disable COP
by Mask Option
Converted to Reset
WAIT Time
More Than
COP Timeout
Converted to Reset
Acts as STOP
Disable COP by Mask Option
Disable COP by Mask Option
Any Length
WAIT Time
5.7 Ille g a l Ad d re ss Re se t
When an opcode fetch occurs from an address which is not implemented
in the RAM ($0080–$01FF) or ROM ($0F00–$1FFF), the part is reset
automatically.
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Se c tion 6. Op e ra ting Mod e s
6.1 Conte nts
6.2
6.3
6.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.5.1
6.5.2
6.5.3
6.2 Introd uc tion
The MCU has two modes of operation: single-chip mode and self-check
mode. This section describes these modes as well as the two low-power
modes: stop mode and wait mode.
Refer to Table 6-1 for the conditions required to go into each of the
operating modes.
Table 6-1. Operating Mode Conditions
RESET
IRQ
PB1
Mode
VSS – VDD
VSS – VDD
Single-Chip
VTST
VDD
Self-Check
VTST = 2 x VDD
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Op e ra ting Mod e s
6.3 Sing le -Chip Mod e
In single-chip mode, the address and data buses are not available
externally, but there are two 8-bit input/output (I/O) ports and one 4-bit
I/O port. This mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU.
Single-chip mode is entered on the rising edge of RESET if the IRQ pin
is within normal operating range.
Refer to Figure 1-2 for the single-chip user mode pinout diagram.
6.4 Se lf-Che c k Mod e
The self-check mode provides an internal check to determine if the
device is functional.
6.5 Low-Powe r Mod e s
The following subsections provide a description of the low-power modes.
6.5.1 Stop Mod e
The STOP instruction places the MCU in its lowest power-consumption
mode. In stop mode, the internal oscillator is turned off, halting all
internal processing, including timer (and COP watchdog timer)
operation.
During stop mode, the I bit in the CCR is cleared to enable external
interrupts. All other registers, including the bits in the TCSR, and
memory remain unaltered. All input/output lines remain unchanged. The
processor can be brought out of stop mode only by an external interrupt
or RESET.
The STOP instruction can be disabled by a mask option. When disabled,
the STOP instruction causes a chip reset.
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Operating Modes
Low-Power Modes
Refer to Figure 4-2 and to 4.10 Operation During Stop Mode for
additional information.
6.5.2 Wa it Mod e
The WAIT instruction places the MCU in a low power-consumption
mode, but the wait mode consumes more power than the stop mode. All
CPU action is suspended, but the timer, CPI, COP, SSI, and M bus
remain active. An interrupt from the timer, SSI, or M bus can cause the
MCU to exit the wait mode.
During the wait mode, the I bit in the CCR is cleared to enable interrupts.
All other registers, memory, and input/output lines remain in their
previous state. The timer, SSI, and/or IIC modules may be enabled to
allow a periodic exit from the wait mode.
Refer to Figure 4-2 and to 4.11 Operation During Wait Mode for
additional information.
6.5.3 Da ta -Re te ntion Mod e
The contents of RAM and CPU registers are retained at supply voltages
as low as 2.0 Vdc. This is called the data-retention mode where the data
is held, but the device is not guaranteed to operate. RESET must be held
low during data-retention mode.
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Op e ra ting Mod e s
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Se c tion 7. Inp ut/ Outp ut (I/ O) Ports
7.1 Conte nts
7.2
7.3
7.4
7.5
7.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
7.2 Introd uc tion
In single-chip mode, 20 lines are arranged as two 8-bit input/output (I/O)
ports and one 4-bit I/O port. These ports are programmable as either
inputs or outputs under software control of the data direction registers.
To avoid a glitch on the output pins, write data to the I/O port data
register before writing a one to the corresponding data direction register
(DDR).
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The port A data register is at $0000 and the DDR
is at $0004. Reset does not affect the data registers, but clears the data
direction registers, thereby returning the ports to inputs. Writing a one to
a DDR bit sets the corresponding port bit to output mode.
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Inp ut/ Outp ut (I/ O) Ports
7.4 Port B
Port B is an 8-bit bidirectional port which does share some of its pins with
other subsystems. The address of the port B data register is $0001 and
the DDR is at address $0005. Reset does not affect the data registers,
but clears the data direction registers, thereby returning the ports to
inputs. Writing a one to a DDR bit sets the corresponding port bit to
output mode. Refer to Section 11. Motorola Bus (M Bus) Interface and
Section 12. Synchronous Serial Interface (SSI) for descriptions of
port B behavior while either module is enabled.
7.5 Port C
Port C is a 4-bit bidirectional port which does not share any of its pins
with other subsystems. The port C data register is at $0002 and the DDR
is at $0006. Reset does not affect the data registers, but clears the data
direction registers, thereby returning the ports to inputs. Writing a one to
a DDR bit sets the corresponding port bit to output mode.
7.6 Inp ut/ Outp ut Prog ra m m ing
Ports A, B, and C may be programmed as inputs or outputs under
software control. The direction of the pins is determined by the state of
the corresponding bit in the port DDR with each port having an
associated DDR. Any port A, port B, or port C pin is configured as an
output if its corresponding DDR bit is set to a logic 1. A pin is configured
as an input if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all port A,
B, and C pins as inputs. The data direction registers are capable of being
written to or read from by the processor. During the programmed output
state, a read of the data register actually reads the value of the output
data latch and not the I/O pin. See Table 7-1 and Figure 7-1.
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Input/Output (I/O) Ports
Input/Output Programming
Table 7-1. I/O Pin Functions
R/W
DDR
I/O Pin Function
The I/O pin is in input mode. Data is written into the output
data latch.
0
0
Data is written into the output data latch and output of
the I/O pin.
0
1
1
1
0
1
The state of the I/O pin is read.
The I/O pin is in an output mode. The output data latch
is read.
DATA DIRECTION
REGISTER BIT
INTERNAL
HC05
I/O
LATCHED OUTPUT
DATA BIT
OUTPUT
PIN
CONNECTIONS
INPUT
REGISTER
BIT
INPUT
I/O
Figure 7-1. Port I/O Circuitry
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Inp ut/ Outp ut (I/ O) Ports
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Input/Output (I/O) Ports
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Se c tion 8. Tim e r
8.1 Conte nts
8.2
8.3
8.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Timer Control and Status Register . . . . . . . . . . . . . . . . . . . . . .55
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
8.2 Introd uc tion
The timer for this device is a 15-stage multifunctional ripple counter. The
features include timer overflow, power-on reset (POR), and real-time
interrupt.
As seen in Figure 8-1, the timer is driven by the output of the clock select
circuit (as determined by the value of BCS in the PLLCR) and then a
fixed divide-by-four prescaler. This signal drives an 8-bit ripple counter.
The value of this 8-bit ripple counter can be read by the CPU at any time
by accessing the timer counter register (TCR) at address $09. A timer
overflow function is implemented on the last stage of this counter, giving
a possible interrupt at the rate of f /1024. Two additional stages
op
produce the POR function at f /4064.
op
This circuit is followed by two more stages, with the resulting clock
(f /16,384) driving the real-time interrupt circuit. The RTI circuit consists
op
of three divider stages with a one-of-four selector. The RTI rate selector
bit and the RTI and TOF enable bits and flags are located in the timer
control and status register at location $0008.
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Tim e r
MC68HC05E4 INTERNAL BUS
8
8
INTERNAL
PROCESSOR
CLOCK
$09 TCR
f
op
TIMER COUNTER REGISTER (TCR)
f /22
TCR
op
÷4
f /210
op
7-BIT COUNTER
POR
TCBP
RTI SELECT CIRCUIT
OVERFLOW
DETECT
CIRCUIT
$08 TCSR
TIMER CONTROL & STATUS REGISTER
TCSR
TOF RTIF TOFE RTIE TOFA RTIFA RT1
RT0
INTERRUPT CIRCUIT
TO INTERRUPT
LOGIC
Figure 8-1. Timer Block Diagram
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Timer
Timer Control and Status Register
8.3 Tim e r Control a nd Sta tus Re g iste r
The timer control and status register (TCSR) contains the timer interrupt
flag, the timer interrupt enable bits, and the real-time interrupt rate select
bits. Figure 8-2 shows the value of each bit in the TCSR when coming
out of reset.
Address: $0008
Bit 7
TOF
0
6
RTIF
0
5
TOFE
0
4
RTIE
0
3
TOFA
0
2
RTIFA
0
1
RT1
1
Bit 0
RT0
1
Read:
Write:
Reset:
Figure 8-2. Timer Control and Status Register (TCSR)
TOF — Timer Over Flow
TOF is a clearable, read-only status bit and is set when the 8-bit ripple
counter rolls over from $FF to $00. A CPU interrupt request will be
generated if TOFE is set. Clearing the TOF is done by writing a logic 1
to TOFA. This is a read-only bit. Reset also clears TOF.
RTIF — Real-Time Interrupt Flag
The real-time interrupt circuit consists of a 3-stage divider and a
one-of-four selector. The clock frequency that drives the RTI circuit is
13
f /2 (or f /8192) with three additional divider stages giving a
op
op
maximum interrupt period of four seconds at a crystal frequency of
32.768 kHz. RTIF is a clearable, read-only status bit and is set when
the output of the chosen (one-of-four selection) stage goes active. A
CPU interrupt request will be generated if RTIE is set. Clearing the
RTIF is done by writing a logic 1 to RTIFA. Reset also clears RTIF.
TOFE — Timer Overflow Enable
When this bit is set, a CPU interrupt request is generated when the
TOF bit is set. Reset clears this bit.
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Tim e r
RTIE — Real-Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the
RTIF bit is set. Reset clears this bit.
TOFA — Timer Over Flow Flag Acknowledge
When a one is written to this bit location, the TOF flag bit is cleared.
This bit always reads as a zero.
RTIFA — Real-Time Interrupt Flag Acknowledge
When a one is written to this bit location, the RTIF flag bit is cleared.
This bit always reads as a zero.
RT1–RT0 — Real-Time Interrupt Rate Select
These two bits select one of four taps from the real-time interrupt
circuit.Table 8-1 shows the available interrupt rates with several f
op
values. Reset sets RT0 and RT1, selecting the lowest periodic rate
and therefore the maximum time in which to alter these bits if
necessary. Care should be taken when altering RT0 and RT1 if the
time-out period is imminent or uncertain. If the selected tap is
modified during a cycle in which the counter is switching, an RTIF
could be missed or an additional one could be generated.
Table 8-1. RTI Rates
RT1 Rates at f Frequency Specified:
op
RT1flRT0
f
16.384 kHz
524 kHz
31.3 ms
62.5 ms
125 ms
250 ms
1.049 MHz
15.6 ms
2.097 MHz
7.8 ms
4.194 MHz
3.9 ms
op
÷ f
÷ f
÷ f
÷ f
14
00
01
10
11
1 s
2 s
4 s
8 s
2
2
2
2
op
op
op
op
15
16
17
31.3 ms
15.6 ms
31.3 ms
62.5 ms
7.8 ms
62.5 ms
15.6 ms
31.3 ms
125.1 ms
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Timer
Timer Counter Register
8.4 Tim e r Counte r Re g iste r
The timer counter register (TCR) is a read-only register which contains
the current value of the 8-bit ripple counter at the beginning of the timer
chain. This counter is clocked at f divided by four and can be used for
op
various functions including a software input capture. Extended time
periods can be attained using the TOF function to increment a temporary
RAM storage location, thereby simulating a 16-bit (or more) counter.
Address: $0009
Bit 7
0
6
5
4
0
3
0
2
0
1
1
Bit 0
1
Read:
Write:
Reset:
0
0
= Unimplemented
Figure 8-3. Timer Counter Register (TCR)
The power-on cycle clears the entire counter chain and begins clocking
the counter. After 4064 cycles, the power-on reset circuit is released
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer will start
counting up from zero and normal device operation will begin. When
RESET is asserted any time during operation other than POR, the
counter chain will be cleared.
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Tim e r
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Se c tion 9. Pha se -Loc ke d Loop (PLL) Synthe sis
9.1 Conte nts
9.2
9.3
9.4
9.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Phase-Locked Loop Control Register. . . . . . . . . . . . . . . . . . . .61
Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .63
Noise Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
9.2 Introd uc tion
The PLL consists of a variable bandwidth loop filter, a voltage-controlled
oscillator (VCO), a feedback frequency divider, and a digital phase
detector. The PLL requires an external loop filter capacitor (typically
0.1 µF) connected between XFC and V
. This capacitor should be
DDSYN
located as close to the chip as possible to minimize noise. V
is the
DDSYN
supply source for the PLL and should be bypassed to minimize noise.
The V bypass cap should be as close as possible to the chip.
DDSYN
The phase detector compares the frequency and phase of the feedback
frequency (t ) and the crystal oscillator reference frequency (t ) and
REF
FB
generates the output, PCOMP, as shown in Figure 9-1. The output
waveform is then integrated and amplified. The resultant DC voltage is
applied to the voltage controlled oscillator. The output of the VCO is
divided by a variable frequency divider of 256, 128, 64, or 32 to provide
the feedback frequency for the phase detector.
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Pha se -Loc ke d Loop (PLL) Synthe sis
V
DDSYN
0.1 µF
0.1 µF
XFC
OSC1
CLOCK
tREF
OSC1
PCOMP
PLLOUT
PHASE
DETECT
VCO
LOOP FILTER
÷ 2
SELECT
TO CLOCK
GENERATION
CIRCUITRY
CRYSTAL
OSCILLATOR
BCS
tFB
FREQUENCY
DIVIDER
PS1
PS0
Figure 9-1. PLL Circuit
To change PLL frequencies, follow the procedure outlined here:
1. Clear BCS to enable the low-frequency bus rate.
2. Clear PLLON to disable the PLL and select high bandwidth.
3. Select the speed using PS1 and PS0.
4. Set PLLON to enable the PLL.
5. Wait a time of 90% t
for the PLL frequency to stabilize and
PLLS
select manual low bandwidth, wait another 10% t
.
PLLS
6. Set BCS to switch to the high-frequency bus rate
The user cannot switch among the high speeds with the BCS bit set.
Following the procedure above will prevent possible bursts of high
frequency operation during the re-configuration of the PLL.
Whenever the PLL is first enabled, the wide bandwidth mode should be
used. This enables the PLL frequency to ramp up quickly. When the
output frequency is near the desired frequency, the filter is switched to
the narrow bandwidth mode to make the final frequency more stable.
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Phase-Locked Loop (PLL) Synthesis
Phase-Locked Loop Control Register
9.3 Pha se -Loc ke d Loop Control Re g iste r
This read/write register contains the control bits which select the PLL
frequency and enable/disable the synthesizer.
Address: $0007
Bit 7
6
BCS
0
5
0
0
4
BWC
0
3
2
1
PS1
0
Bit 0
PS0
1
Read:
Write:
Reset:
0
PLLON VCOTST
0
1
1
Figure 9-2. Phase-Locked Loop Control Register (PLLCR)
BCS — Bus Clock Select
When this bit is set, the output of the PLL is used to generate the
internal processor clock. When clear, the internal bus clock is driven
by the crystal (OSC1 ÷ 2). Once BCS has been changed, it may take
up to 1.5 OSC1 cycles + 1.5 PLLOUT cycles to make the transition.
During the transition, the clock select output will be held low and all
CPU and timer activity will cease until the transition is complete.
Before setting BCS, allow at least a time of t
after PLLON is set.
PLLS
This bit cannot be set unless the PLLON bit is already set on a
previous instruction. Reset clears this bit.
BWC — Bandwidth Control
This bit selects high bandwidth control when set and low bandwidth
control when clear. The low bandwidth driver is always enabled, so
this bit determines whether the high bandwidth driver is on or off.
When the PLL is turned on, the BWC bit should be set to a logic 1 for
a time of 90% t
to allow the PLL time to acquire a frequency close
PLLS
to the desired frequency. The BWC bit should then be cleared and
software should delay for a time 10% t to allow the PLL time to
PLLS
make the final adjustments. The PLL clock cannot be used (BCS bit
set). Although it is NOT prohibited in hardware, the BCS bit should not
be set unless the BWC bit is cleared and the proper delay times have
been followed. The PLL will generate a lower jitter clock when the
BWC bit is cleared. Reset clears this bit.
MC68HC05E5 — Rev. 1.0
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Pha se -Loc ke d Loop (PLL) Synthe sis
PLLON — PLL On
This bit activates the synthesizer circuit without connecting it to the
control circuit. This allows the synthesizer to stabilize before it can
drive the CPU clocks. When this bit is cleared, the PLL is shut off and
the BCS bit cannot be set. (Setting the BCS bit would engage the
disabled PLL onto the bus.) Reset sets this bit.
NOTE: PLLON cannot be cleared unless the BCS bit has been cleared on a
previous write to the register.
VCOTST — VCO Test
This bit is used to isolate the loop filter from the VCO to facilitate
testing. When cleared only in test or self-check modes, the low
bandwidth mode of the PLL filter is disabled. When set, the loop filter
operates as indicated by the value of the BWC bit. Reset sets this bit.
NOTE: This bit is intended for use by Motorola to test and characterize the PLL.
This bit cannot be cleared in user mode.
PS1–PS0 — PLL Synthesizer Speed Select
These two bits select one-of-four taps from the PLL to drive the CPU
clocks. These bits are used in conjunction with PLLON and BCS bits
in the PLL control register. These bits should not be written if BCS in
the PLLCR is at a logic high. Reset clears PS1 and sets PS0,
choosing a bus clock frequency of 1.049 MHz.
Table 9-1. PS1 and PS0 Speed Selects with 32.768-kHz Crystal
CPU Bus Clock Frequency (f
)
PS1–PS0
0 0
op
524 kHz
0 1
1.049 MHz Reset Condition
2.097 MHz See Note Below
4.194 MHz See Note Below
1 0
1 1
NOTE:
For the standard MC68HC05E5, the 4.194-MHz bus clock frequency should never
be selected, and the 2.097-MHz bus clock frequency should not be selected when
running the part below V
= 4.5 V.
DD
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MC68HC05E5 — Rev. 1.0
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Phase-Locked Loop (PLL) Synthesis
Operation During Stop Mode
9.4 Op e ra tion During Stop Mod e
The PLL is switched to low-frequency bus rate and is temporarily turned
off when STOP is executed. Coming out of stop mode with an external
IRQ, the PLL is turned on with the same configuration it had before going
into STOP, with the exception of BCS which is reset. Otherwise, the PLL
control register is in the reset condition.
9.5 Noise Im m unity
The MCU should be insulated as much as possible from noise in the
system. We recommend the following steps be taken to help prevent
problems due to noise injection.
1. The application environment should be designed so that the MCU
is not near signal traces which switch often, such as a clock signal.
2. The oscillator circuit for the MCU should be placed as close as
possible to the OSC1 and OSC2 pins on the MCU.
3. All power pins should be filtered (to minimize noise on these
signals) by using bypass capacitors placed as close as possible to
the MCU.
See the application note Designing for Electromagnetic Compatibility
(EMC) with HCMOS Microcontrollers, available through the Motorola
Literature Distribution Center, Motorola document number AN1050/D.
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05E5
Se c tion 10. Com p ute r Op e ra ting Prop e rly (COP)
Wa tc hd og
10.1 Conte nts
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
10.3 System Control and Status Register. . . . . . . . . . . . . . . . . . . . .66
10.4 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
10.5 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
10.2 Introd uc tion
The COP watchdog system is a mask-programmable feature which will
generate a system reset if not serviced within the specified COP timeout
period. The COP counter chain is derived from an output of the CPI
circuit. This input signal is divided to give the COP reset rate selected by
the first write to the system control and status register (SCSR) located at
address $13.
A COP reset is done by writing a logic zero to bit 0 of address $1FF0.
This will reset the COP counter chain and begin the timeout countdown
again. The COP counter chain is also cleared when the MCU is in reset
or stop mode.
MC68HC05E5 — Rev. 1.0
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Com p ute r Op e ra ting Prop e rly (COP) Wa tc hd og
10.3 Syste m Control a nd Sta tus Re g iste r
The SCSR is a read/write register containing the control flags for the
COP rate, COP inhibit, and IRQ level and status flags indicating the
cause of the last reset. Figure 10-1 shows the value of each bit in the
SCSR when coming out of reset.
Address: $0013
Bit 7
6
0
0
5
0
0
4
STOPR
R
3
ILADR
R
2
COPR
R
1
CRS1
0
Bit 0
CRS0
0
Read:
Write:
Reset:
0
0
R = Determined by cause of previous reset
Figure 10-1. System Control and Status Register (SCSR)
NOTE: The debounce time for the IRQ input must be shorter than the COP
timeout period.
STOPR — Illegal STOP Instruction Reset
STOPR is a read-only status bit. This bit is set by the execution of a
STOP instruction when the STOP instruction option is disabled. This
bit is cleared by POR, external reset, or COP reset.
1 = Last reset was the execution of a disabled STOP instruction.
0 = Last reset was not the execution of a disabled STOP
instruction.
ILADR — Illegal Address Reset
ILADR is a read-only status bit. This bit is set by an ILADR reset, but
is cleared by POR, external reset, or COP reset.
1 = Last reset was an ILADR reset.
0 = Last reset was not an ILADR reset.
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Computer Operating Properly (COP) Watchdog
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Computer Operating Properly (COP) Watchdog
System Control and Status Register
COPR — COP Reset
COPR is a read-only status bit. This bit is set by a COP reset, but is
cleared by POR, external reset, or illegal address reset.
1 = Last reset was a COP reset.
0 = Last reset was not a COP reset.
NOTE: The COP watchdog reset is a mask option. Therefore, a COP reset will
only occur when this option is enabled. This option cannot be disabled
by software.
CRS1 and CRS0 — COP Rate Select
The value of these two bits determines the COP timeout rate. These
bits can be written only on the first write to this register after reset. If
these bits are never written to, the COP reset rate will be set at one
second. The COP counter chain is cleared when these bits are
written.
NOTE: Although these bits default to zero, the user should write to these bits to
prevent subsequent writes from changing the COP rate.
A bit set/clear for any bit in this register is executed as a
read-modify-write of this register. If used as the first write to this register,
further writes to CRS1 and CRS0 would not be valid, and the default
value would be set.
Table 10-1. COP Rates at f
= 32.768 kHz
osc
CRS1
CRS0
Minimum COP Rate
1 second
0
0
1
1
0
1
0
1
2 seconds
4 seconds
8 seconds
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Com p ute r Op e ra ting Prop e rly (COP) Wa tc hd og
10.4 COP During Wa it Mod e
The CPU clock halts during wait mode, but the oscillator and the COP
system are still active. The software should exit wait mode to service the
COP system before the COP timeout period.
10.5 COP During Stop Mod e
Prior to entry into stop mode, the COP should be cleared. This allows for
proper stop recovery and eliminates a possible COP time out during stop
mode recovery, if the COP was about to time out prior to the STOP
instruction. If enabled, stop mode turns off the oscillator and, therefore,
will stop the COP.
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05E5
Se c tion 11. Motorola Bus (M Bus) Inte rfa c e
11.1 Conte nts
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
11.3 M-Bus Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
11.4 M-Bus System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .71
11.5 M-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.5.8
Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Slave Address Transmission. . . . . . . . . . . . . . . . . . . . . . . .73
Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Repeated Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Stop Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Clock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
11.6 M-Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
M-Bus Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .76
M-Bus Frequency Divider Register . . . . . . . . . . . . . . . . . . .78
M-Bus Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .80
M-Bus Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
M-Bus Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . .84
11.7 M-Bus Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.8 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.8.1
11.8.2
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Generation of a Start Signal and the
First Byte of Data Transfer . . . . . . . . . . . . . . . . . . . . . . .87
Software Responses after Transmission
11.8.3
or Reception of a Byte . . . . . . . . . . . . . . . . . . . . . . . . . .88
Generation of the Stop Signal . . . . . . . . . . . . . . . . . . . . . . .89
Generation of a Repeated Start Signal . . . . . . . . . . . . . . . .90
11.8.4
11.8.5
MC68HC05E5 — Rev. 1.0
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Motorola Bus (M Bus) Inte rfa c e
11.8.6
11.8.7
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
11.9 Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .91
11.10 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .91
11.2 Introd uc tion
Motorola bus (M bus) is a 2-wire, bidirectional serial bus which provides
a simple, efficient way for data exchange between devices. It is fully
compatible to I2C bus standards and is similar to the MC68HC05T10.
This bus is suitable for applications that require frequent
communications over a short distance between a number of devices. It
also provides a flexibility that allows additional devices to be connected
to the bus. The maximum data rate is limited to 100 Kbits and the
maximum communication distance and number of devices that can be
connected is limited by the maximum bus capacitance of 400 pF.
The M-bus system is a true multimaster bus including collision detection
and arbitration to prevent data corruption if two or more masters intend
to control the bus simultaneously. This feature provides the capability for
complex applications with multiprocessor control. It may also be used for
rapid testing and alignment of end products by way of external
connections to an assembly-line computer.
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Motorola Bus (M Bus) Interface
M-Bus Interface Features
11.3 M-Bus Inte rfa c e Fe a ture s
Features of the M-bus interface include:
• Fully Compatible with I2C Bus Standard
• Multimaster Operation
• Software Programmable for 1of 32 Different Serial Clock
Frequencies
• Software Selectable Acknowledge Bit
• Interrupt Driven Byte-by-Byte Data Transfer
• Arbitration Lost Driven Interrupt with Automatic Mode Switching
from Master to Slave
• Calling Address Identification Interrupt
• Generate/Detect the Start or Stop Signal
• Repeated Start Signal Generation
• Generate/Recognize the Acknowledge Bit
• Bus Busy Detection
11.4 M-Bus Syste m Config ura tion
The M-bus system uses a serial data line (SDA) and a serial clock line
(SCL) for data transfer. All devices connected to it must have open-drain
or open-collector outputs and the logical AND function is performed on
both lines by two pullup resistors.
11.5 M-Bus Protoc ol
Normally, a standard communication is composed of four parts: start
signal, slave address transmission, data transfer, and stop signal. These
are described briefly in the following subsections and illustrated in
Figure 11-1.
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11.5.1 Sta rt Sig na l
When the bus is free (for example, no master device is engaging the bus
and both SCL and SDA lines are at logical high), a master may initiate
communication by sending a start signal. As shown in Figure 11-1, a
start signal is defined as a high-to-low transition of SDA while SCL is
high. This signal denotes the beginning of new data transfer (each data
transfer may contain several bytes of data) and wakes up all slaves.
MSB
LSB
MSB
1
LSB
1
SCL
SDA
1
1
0
0
0
0
1
1
1
0
0
0
0
1
ACKNOWLEDGE BIT
NO ACKNOWLEDGE
START SIGNAL
STOP SIGNAL
MSB
LSB
MSB
1
LSB
SCL
SDA
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
ACKNOWLEDGE BIT
NO ACKNOWLEDGE
START SIGNAL
REPEATED START SIGNAL
STOP SIGNAL
Figure 11-1. M-Bus Transmission Signal Diagram
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M-Bus Protocol
11.5.2 Sla ve Ad d re ss Tra nsm ission
Immediately after the start signal, the first byte of data transfer is the
slave address transmitted by the master. This data is a 7-bit calling
address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
Only the slave with a matched address will respond by sending back an
acknowledge bit. This acknowledge bit is accomplished by pulling SDA
low on the ninth clock cycle. (See Figure 11-1.)
11.5.3 Da ta Tra nsfe r
Once a successful slave addressing is achieved, the data transfer can
proceed byte by byte in the direction specified by the R/W bit sent by the
calling master.
Each data byte is eight bits long. Data can be changed only when SCL
is low and must be held stable while SCL is high as shown in Figure
11-1. The MSB is transmitted first and each byte has to be followed by
an acknowledge bit. The acknowledge bit is signalled by the receiving
device by pulling the SDA low on the ninth clock cycle. Therefore, one
complete data byte transfer needs nine clock cycles.
If the slave receiver does not acknowledge the master, the SDA line
should be left high by the slave. The master can then generate a stop
signal to abort the data transfer or a start signal (repeated start) to
commence a new transfer.
If the master receiver does not acknowledge the slave transmitter after
a byte has been transmitted, it means an “end of data” to the slave. The
slave should now release the SDA line for the master to generate a stop
or start signal.
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11.5.4 Re p e a te d Sta rt Sig na l
As shown in Figure 11-1, a repeated start signal is used to generate a
start signal without first generating a stop signal to terminate the
communication. This is used by the master to communicate with another
slave or with the same slave in a different mode (transmit/receive mode)
without releasing the bus.
11.5.5 Stop Sig na l
The master can terminate the communication by generating a stop
signal to free the bus. However, the master may generate a start signal
followed by a calling command without first generating a stop signal.
This is called repeat start. A stop signal is defined as a low-to-high
transition of SDA while SCL is at logical high. (See Figure 11-1.)
11.5.6 Arb itra tion Proc e d ure
This interface circuit is a true multimaster system which allows more
than one master to be connected to it. If two or more masters try to
control the bus at the same time, a clock synchronization procedure
determines the bus clock, for which the low period is equal to the longest
clock low period and the high is equal to the shortest one among the
masters. A data arbitration procedure determines the priority. The
masters will lose arbitration if they transmit a logic 1 while another
transmits logic 0. The losing masters will immediately switch over to
slave receive mode and stop its data and clock outputs. In this case, the
transition from master to slave mode will not generate a stop condition;
however, a software bit will be set by hardware to indicate loss of
arbitration.
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Motorola Bus (M Bus) Interface
M-Bus Protocol
11.5.7 Cloc k Sync hroniza tion
Since wired-AND logic is performed on the SCL line, a high-to-low
transition will affect the devices connected to the bus. The devices start
counting their low period and once a device's clock has gone low, it will
hold the SCL line low until the clock high state is reached. However, the
change of low to high in this device clock may not change the state of
the SCL line if another device clock is still within its low period.
Therefore, the synchronized clock SCL will be held low by the device
with the longest low period. Devices with shorter low periods enter a high
wait state during this time. (See Figure 11-2.) When all devices
concerned have counted off their low period, the synchronized SCL line
will be released and go high. There will then be no difference between
the device clocks and the state of the SCL line and all devices will start
counting their high periods. The first device to complete its high period
will again pull the SCL line low.
11.5.8 Ha nd sha king
The clock synchronization mechanism can be used as a handshake in
data transfer. Slave devices may hold the SCL low after completion of
one byte. In such cases, the device will halt the bus clock and force the
master clock into a wait state until the slave releases the SCL line.
START COUNTING HIGH PERIOD
WAIT
SCL1
SCL2
SCL
INTERNAL COUNTER RESET
Figure 11-2. Clock Synchronization
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11.6 M-Bus Re g iste rs
Five different registers are used in the M-bus interface. The internal
configuration of these registers is discussed in the following paragraphs.
NOTE: The register addresses show only the low-order address bits (for
example ABL3–ABL0). The registers can be placed anywhere in the
device memory map by generating an appropriate module select signal
in the map logic.
A block diagram of the M-bus system is shown in Figure 11-3.
11.6.1 M-Bus Ad d re ss Re g iste r
Address: $0018
Bit 7
6
MAD6
0
5
MAD5
0
4
MAD4
0
3
MAD3
0
2
MAD2
0
1
MAD1
0
Bit 0
—
Read:
MAD7
Write:
Reset:
0
= Unimplemented
Figure 11-3. M-Bus Address Register (MADR)
Bit 1–Bit 7
Each of these bits contains its own specific slave address. This
register is cleared upon reset.
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Motorola Bus (M Bus) Interface
M-Bus Registers
L
R
A DD R E S
A DD R E S
R
C
R
C O M PA R TA O R
S
L
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11.6.2 M-Bus Fre q ue nc y Divid e r Re g iste r
Address: $0019
Bit 7
6
5
4
FD4
0
3
FD3
0
2
FD2
0
1
FD1
0
Bit 0
FD0
0
Read:
Write:
Reset:
—
—
—
= Unimplemented
Figure 11-5. M-Bus Frequency Divider Register (MFDR)
Bit 0–Bit 4
These bits are used for clock rate selection. The serial bit clock
frequency is equal to the CPU clock divided by the divider shown in
Table 11-1. This register is cleared upon reset.
For a 4-MHz external crystal operation (2-MHz internal operating
frequency), the serial bit clock frequency of the M-bus ranges from
460 Hz to 90,909 Hz.
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M-Bus Registers
Table 11-1. M-Bus Clock Prescaler
FD4, FD3, FD2, FD1, FD0
Divider
22
FD4, FD3, FD2, FD1, FD0
Divider
352
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
24
384
28
448
34
544
44
704
48
768
56
896
68
1088
1408
1536
1792
2176
2816
3072
3584
4352
88
96
112
136
176
192
224
272
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11.6.3 M-Bus Control Re g iste r
The M-bus control register (MCR) provides five control bits and is
cleared upon reset.
Address: $001A
Bit 7
MEN
0
6
MIEN
0
5
MSTA
0
4
MTX
0
3
TXAK
0
2
MMUX
0
1
Bit 0
—
Read:
Write:
Reset:
—
= Unimplemented
Figure 11-6. M-Bus Control Register (MCR)
MEN — M-Bus Enable Bit
If MEN is set, the M-bus interface system is enabled. If MEN is
cleared, the interface is reset and disabled. The MEN bit must be set
first before any bits of MCR are set.
MIEN — M-Bus Interrupt Enable Bit
If MIEN is set, an interrupt occurs provided the MIF flag in the status
register is set and the I bit in the condition code register is cleared. If
MIEN is cleared, the M-bus interrupt is disabled.
MSTA — Master/Slave Mode Select Bit
Upon reset, this bit is cleared. When this bit is changed from a logic 0
to a logic 1, a start signal is generated on the bus, and master mode
is selected. When this bit is changed from a logic 1 to a logic 0, a stop
signal is generated and the operating mode changes from master to
slave.
In master mode, a bit clear immediately followed by a bit set
generates a repeated start signal (see Figure 11-1) without
generating a stop signal.
1 = Master
0 = Slave
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M-Bus Registers
MTX — Transmit/Receiver Mode Select Bit
This bit selects the direction of master and slave transfers. When
addressed as a slave, this bit should be set by software according to
the SRW bit in the status register. In master mode, this bit should be
set according to the type of transfer required. Hence, for address
cycles this bit will always be high.
1 = Transmit
0 = Receive
TXAK — Transmit Acknowledge Enable Bit
If TXAK is cleared, an acknowledge signal will be sent out to the bus
at the ninth clock bit after receiving one byte of data. When TXAK is
set, there will be no acknowledge signal response (for example,
acknowledge bit = 1).
MMUX — M-Bus Multiplexer
This bit is used to enable PB7 and PB6 to be under the control of the
M-bus circuit. When set, both PB7 and PB6 become open-collector
outputs or inputs when enabled by the M-bus control. When cleared
PB7 and PB6 are under control of the port DDR logic. This bit can be
set or cleared independent of the MEN bit. Caution should be used if
PB7 and PB6 are used as general-purpose I/O.
1 = M-bus control
0 = POR condition, port B DDR control
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11.6.4 M-Bus Sta tus Re g iste r
This status register is software readable only with exception of bit 1
(MIF) and bit 4 (MAL) which are software clearable. All bits are cleared
upon reset except bit 7 (MCF) and bit 0 (RXAK).
Address: $001B
Bit 7
MCF
6
5
4
MAL
MAL CLR
0
3
2
1
MIF
Bit 0
Read:
Write:
Reset:
MAAS
MBB
SRW
RXAK
MIF CLR
0
1
0
0
—
0
1
= Unimplemented
Figure 11-7. M-Bus Status Register (MSR)
MCF — Data Transferring Bit
While one byte of data is being transferred, this bit is cleared. It is set
by the falling edge of the ninth clock of a byte transfer.
1 = Transfer complete
0 = Transfer in progress
MAAS — Addressed as a Slave Bit
When its own specific address (MADR) is matched with the calling
address, this bit is set. The CPU is interrupted provided MIEN is set.
Then CPU needs to check the SRW bit and set its TX/RX mode
accordingly.
1 = Addressed as a slave
0 = Not addressed
Writing to the M-bus control register clears this bit.
MBB — Bus Busy Bit
This bit indicates the status of the bus. When a start signal is
detected, the MBB is set. If a stop signal is detected, it is cleared.
1 = Bus busy
0 = Bus idle
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M-Bus Registers
MAL — Arbitration Lost Bit
MAL is set by hardware when the arbitration procedure is lost during
a master transmission. This bit must be cleared by software.
SRW — R/W Command Bit
When MAAS is set, the R/W command bit of the calling address (sent
from master) is latched into the R/W command bit (SRW). Checking
this bit, the CPU can select the slave transmit/receive mode
according to the command of master.
1 = Slave transmit, master reading from slave
0 = Slave receive, master writing to slave
MIF — M-Bus Interrupt Bit
MIF is set when an interrupt is pending. This will cause an M-bus
interrupt request provided MIEN is set. This bit is set when one of the
following events occurs:
– Transmission of one byte is completed. The bit is set at the
falling edge of the ninth clock.
– Reception of a calling address which matches its own specific
address in slave receive mode.
– Arbitration is lost.
This bit must be cleared by writing a logic 0 to it.
RXAK — Receive Acknowledge Bit
If RXAK is low, it indicates an acknowledge signal has been received
after the completion of an 8-bit data transmission on the bus. If RXAK
is high, it means no acknowledge signal is detected at the ninth clock.
1 = No acknowledge received
0 = Acknowledge received
RXAK is set upon reset.
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11.6.5 M-Bus Da ta I/ O Re g iste r
Address: $001C
Bit 7
6
5
4
3
2
1
Bit 0
MD0
Read:
MD7
Write:
MD6
MD5
MD4
MD3
MD2
MD1
Reset:
Unaffected by Reset
Figure 11-8. M-Bus Data I/O Register (MDR)
In master transmit mode, data written to this register is sent (MSB first)
to the bus automatically. In master receive mode, reading from this
register initiates reception of the next byte of data. This is accomplished
by holding the SCL clock line low until a read of this register occurs.
Once the data is read, the device releases the SCL line to allow the
transmitting device to transmit the next byte. In slave mode, the same
function is available after it is addressed.
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M-Bus Registers
CLEAR MIF
Y
N
MASTER
MODE
TX
RX
Y
Y
ARBITRATION
TX/RX
LOST
N
CLEAR MAL
Y
LAST BYTE
TO BE READ
LAST BYTE
Y
TRANSMITTED
MAAS = 1
N
N
N
N
MAAS = 1
Y
RX
LAST 2nd BYTE
TO BE READ
RXAK=0
TX/RX
TX
N
Y
Y (READ)
N
SRW = 1
WRITE NEXT
BYTE TO MDR
GENERATE
STOP SIGNAL
SET TXAK = 1
READ MDR
AND STORE
N (WRITE)
SET
TX MODE
GENERATE
STOP SIGNAL
Y
ACK FROM
RECEIVER
WRITE
TO MDR
N
TX NEXT
BYTE
SET
RX MODE
SWITCH TO
RX MODE
READ DATA FROM
MDR AND STORE
DUMMY READ
FROM MDR
DUMMY READ
FROM MDR
RTI
Figure 11-9. Flowchart of M-Bus Interrupt Routine
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11.7 M-Bus Pin Config ura tion
When the M-bus interface is enabled with the MEN bit and the MMUX bit
in the M-bus control register (MCR), the port B data direction register bits
6 and 7 relinquish control to the M-bus control register bits. Enabling the
M-bus does not alter the state of the port B DDR bits.
11.8 Prog ra m m ing Consid e ra tions
Programming considerations are discussed in the following subsections.
11.8.1 Initia liza tion
Initialization is accomplished using the following steps:
1. Update frequency divider register (MFDR) to select an SCL
frequency.
2. Update M-bus address register (MADR) to define its own slave
address.
3. Set MEN bit of the M-bus control register (MCR) to enable the
M-bus interface system and set the MMUX bit to allow M-bus
control of the PB7 and PB6 pins.
4. Modify the M-bus control register (MCR) bits to select
master/slave mode, transmit/receive mode, interrupt enable, or
not.
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Programming Considerations
11.8.2 Ge ne ra tion of a Sta rt Sig na l a nd the First Byte of Da ta Tra nsfe r
After completion of the initialization procedure, serial data can be
transmitted by selecting the master transmitter mode. If the device is
connected to a multimaster bus system, the state of the M-bus busy bit
(MBB) must be tested to check whether the serial bus is free. If the bus
is free (MBB = 0), the start condition and the first byte (the slave address)
can be sent.
An example of a program which generates the start signal and transmits
the first byte of data (slave address) is shown here. (The MMUX bit must
be set to allow control of PB7 and PB6 pins.)
SEI
BRSET
; DISABLE INTERRUPT
5,MSR,CHFLAG; CHECK THE MBB BIT OF THE
; STATUS REGISTER. IF IT IS
CHFALG
; SET, WAIT UNTIL IT IS CLEAR
TXSTART BSET
BSET
4,MCR
5,MCR
; SET TRANSMIT MODE
; SET MASTER MODE
; i.e., GENERATE START CONDITION
; GET THE CALLING ADDRESS
; TRANSMIT THE CALLING
; ADDRESS
LDA
STA
#CALLING
MDR
CLI
; ENABLE INTERRUPT
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11.8.3 Softwa re Re sp onse s a fte r Tra nsm ission or Re c e p tion of a Byte
Transmission or reception of a byte will set the data transferring bit
(MCF) to a logic 1, which indicates one byte of communication is
finished. Also, the M-bus interrupt bit (MIF) is set to generate an M-bus
interrupt if the interrupt function is enabled during initialization. Software
must clear the MIF bit in the interrupt routine first. The MCF bit will be
cleared by reading from the M-bus data I/O register (MDR) in receive
mode or writing to MDR in transmit mode. Software may serve the M-bus
I/O in the main program by monitoring the MIF bit if the interrupt function
is disabled.
The following is an example of a software response by a master
transmitter in the interrupt routine. See Figure 11-9.
ISR
BCLR
BRCLR
1,MSR
5,MCR,SLAVE
; CLEAR THE MIF FLAG
; CHECK THE MSTA FLAG,
; BRANCH IF SLAVE MODE
BRCLR
BRSET
4,MCR,RECEIVE ; CHECK THE MODE FLAG,
; BRANCH IF IN RECEIVE MODE
0,MSR,END
; CHECK ACK FROM RECEIVER
; IF NO ACK, END OF
; TRANSMISSION
TRANSMIT LDA
STA
DATABUF
MDR
; GET THE NEXT BYTE OF DATA
; TRANSMIT THE DATA
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Programming Considerations
11.8.4 Ge ne ra tion of the Stop Sig na l
A data transfer ends with a stop signal generated by the master device.
A master transmitter can simply generate a stop signal after all the data
has been transmitted.
The following is an example showing how a stop condition is generated
by a master transmitter.
MASTX
BRSET
LDA
0,MSR,END
TXCNT
; IF NO ACK, BRANCH TO END
; GET VALUE FROM THE
; TRANSMITTING COUNTER
; IF NO MORE DATA, BRANCH TO
; END
BEQ
END
LDA
STA
DEC
BRA
BCLR
RTI
DATABUF
MDR
TXCNT
EMASTX
5,MCR
; GET NEXT BYTE OF DATA
; TRANSMIT THE DATA
; DECREASE THE TXCNT
; EXIT
; GENERATE A STOP CONDITION
; RETURN FROM INTERRUPT
END
EMASTX
If a master receiver wants to terminate a data transfer, it must inform the
slave transmitter by not acknowledging the last byte of data. This can be
done by setting the transmit acknowledge bit (TXAK) before reading the
second to the last byte of data. Before reading the last byte of data, a
stop signal must be generated first.
The following is an example showing how a stop signal is generated by
a master receiver.
MASR
DEC
BEQ
LDA
RXCNT
ENMASR
RXCNT
; LAST BYTE TO BE READ
DECA
BNE
BSET
; CHECK LAST 2ND BYTE TO BE READ
; NOT LAST ONE OR LAST SECOND
; LAST SECOND, DISABLE ACK
; TRANSMITTING
NXMAR
3,MCR
LAMAR
BRA
BCLR
NXMAR
5,MCR
ENMASR
NXMAR
; LAST ONE, GENERATE 'STOP'
; SIGNAL
; READ DATA AND STORE
LDA
STA
RTI
MDR
RXBUF
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11.8.5 Ge ne ra tion of a Re p e a te d Sta rt Sig na l
If at the end of data transfer the master still wants to communicate on the
bus, it can generate another start signal followed by another slave
address without first generating a stop signal. A program example is
shown here.
RESTART BCLR
BSET
5,MCR
5,MCR
; ANOTHER START (RESTART) IS
; GENERATED BY THESE TWO
; CONSEQUENCE INSTRUCTION
; GET THE CALLING ADDRESS
; TRANSMIT THE CALLING
; ADDRESS
LDA
STA
#CALLING
MDR
11.8.6 Sla ve Mod e
In the slave service routine, the master addressed as slave bit (MAAS)
should be tested to see if a calling of its own address has just been
received. If MAAS is set, software should set the transmit/receive mode
select bit (MTX bit of MCR) according to the R/W command bit (SRW).
Writing to the MCR clears the MAAS automatically. A data transfer may
then be initiated by writing information to MDR or dummy reading from
MDR.
In the slave transmitter routine, the received acknowledge bit (RXAK)
must be tested before transmitting the next byte of data. If RXAK is set,
indicating an end of the data signal from the master receiver, then RXAK
must switch from transmitter mode to receiver mode by software. A
dummy read must follow to release the SCL line so that the master can
generate a stop signal.
11.8.7 Arb itra tion Lost
If more than one master wants to engage the bus simultaneously, only
one master wins and the others lose arbitration. The arbitration loss
devices immediately switch to slave receive mode by hardware. Their
data output to the SDA line is stopped, but the internal transmitting clock
still runs until the end of the current byte transmission. An interrupt
occurs when this dummy byte transmission is accomplished with
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Operation During Wait Mode
MAL = 1 and MSTA = 0. If one master attempts to start transmission
while the bus is being engaged by another master:
1. The hardware will inhibit the transmission.
2. The MSTA bit will switch from one to zero without generating a
stop condition.
3. Interrupt to CPU will be generated.
4. MAL will be set to indicate that the attempt to engage the bus has
failed.
In consideration of these cases, the slave service routine should test the
MAL first, and software should clear the MAL bit if it is set.
11.9 Op e ra tion During Wa it Mod e
During wait mode the M-bus block is idle. If in slave mode, the M-bus
block will wake up on receiving a valid start condition. If the interrupt is
enabled, the CPU will come out of wait mode after the end of a byte
transmission.
11.10 Op e ra tion During Stop Mod e
In stop mode, the whole block is disabled.
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05E5
Se c tion 12. Sync hronous Se ria l Inte rfa c e (SSI)
12.1 Conte nts
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
12.3 SSI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.3.1
12.3.2
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Serial Data Input/Output (SDIO) . . . . . . . . . . . . . . . . . . . . .96
12.4 SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
12.4.1
12.4.2
12.4.3
SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
SSI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
SSI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
12.5 SSI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
12.6 SSI During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.7 SSI Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
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Sync hronous Se ria l Inte rfa c e (SSI)
12.2 Introd uc tion
This synchronous serial I/O module is also used on the MC68HC05X1.
The module is similar to the SIOP used on the MC68HC05P7 and the
MC68HC705P9 and the SPI used on the MC68HC05L5.
The SSI is a 2-wire master/slave system including serial clock (SCK) and
serial data input output (SDIO). Data is transferred eight bits at a time.
An interrupt may be generated at the completion of each transfer, and a
software programmable option determines whether the SSI transfers
data most significant bit (MSB) or least significant bit (LSB) first. When
operating as a master device, the serial clock speed is selectable
between four rates; as a slave device, the clock speed may be chosen
over a wide range. Refer to Figure 12-1.
In master mode, transmission is initiated by a write to the SSI data
register (SDR). A transfer cannot be initiated in slave mode; however,
the external master will initiate the transfer. The programmer must
choose between master or slave mode before the SSI is enabled. It is up
to the programmer to ensure that only one master exists in the system
at any one time. All devices in the system must operate with the same
clock polarity and data rates. Slaves should always be disabled before
the master is disabled. Likewise, the master should always be enabled
before the slaves are enabled.
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Synchronous Serial Interface (SSI)
Introduction
INTERNAL BUS
DATA BUS
CONTROLS/ADDRESS BUS
CONTROL LOGIC
INTERRUPT CIRCUIT
TO INTERRUPT LOGIC
HFF
0 0 0 0 0
SDIO
SCK
SSI STATUS REGISTER
SSI CONTROL REGISTER
SSI DATA REGISTER
LSBF
SE
PB3/TIPL
CLOCK GENERATOR
&
MSTR
Figure 12-1. SSI Block Diagram
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12.3 SSI Sig na ls
The following sections describe the SSI signals.
12.3.1 Se ria l Cloc k (SCK)
In master mode (MSTR = 1), the SCK pin is an output with a selectable
frequency of:
f
divided by 16 (SR1–SR0 = 00),
op
f divided by 8 (SR1–SR0 = 01),
op
f
f
divided by 4 (SR1–SR0 = 10), or
divided by 2 (SR1–SR0 = 11).
op
op
This pin will be high (CPOL = 1) or low (CPOL = 0) between
transmissions.
In slave mode (MSTR = 0), the SCK pin is an input and the clock must
be supplied by an external master with a maximum frequency of f
op
divided by 2. There is no minimum SCK frequency. This pin should be
driven high (CPOL = 1) or low (CPOL = 0) between transmissions by the
external master and must be stable before the SSI is first enabled
(SE = 1).
NOTE: Data is always captured with the SDIO pin on the rising edge of SCK.
Data is always shifted out and presented at the SDIO pin on the falling
edge of SCK.
12.3.2 Se ria l Da ta Inp ut/ Outp ut (SDIO)
This pin receives and transmits data to or from the SSI module as
described in the following paragraphs.
SDIO as an Output Pin
Prior to enabling the SSI (SE = 0), the SDIO pin will be three-stated.
The SDIO pin will be active when the SSI is enabled (SE = 1), the
serial direction (SDIR = 1) bit is set, and MSTR = 1. The state of the
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SSI Signals
pin will depend on the value of the CPOL bit. Data can be sent or
received in either MSB first format (LSBF = 0) or LSB first format
(LSBF = 1).
If (CPOL = 1), the first falling edge of SCK will shift the first data bit
out to the SDIO pin. Subsequent falling edges of SCK will shift the
remaining data bits out.
If (CPOL = 0), the first data bit will be driven out to the SDIO pin before
the first rising edge of SCK. Subsequent falling edges of SCK will shift
the remaining data bits out.
SDIO as an Input Pin
The SDIO pin will accept data once the SSI is enabled and the SDIR
bit = 0. Valid data must be present at least 100 ns before the rising
edge of the clock and remain valid for 100 ns after the edge. See
Figure 12-2 and Figure 12-3.
SCK
SDIO
SE
BIT 1
BIT 2
BIT 3
BIT 7
BIT 8
Figure 12-2. Synchronous Serial Interface Timing (CPOL = 1)
SCK
BIT 1
BIT 2
BIT 3
BIT 7
BIT 8
SDIO
SE
Figure 12-3. Synchronous Serial Interface Timing (CPOL = 0)
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12.4 SSI Re g iste rs
The SSI registers are described in the following subsections.
12.4.1 SSI Control Re g iste r
This register is located at address $000A. A reset clears all of these bits,
except bit 3 which is set. Writes to this register during a transfer should
be avoided, with the exception of clearing the SE bit to disable the SSI.
In addition, the clock polarity, rate, data format, and master/slave
selection should not be changed while the SSI is enabled (SE = 1) or
being enabled. Always disable the SSI, by clearing the SE bit, before
altering control bits within the SCR.
Address: $000A
Bit 7
SIE
0
6
SE
0
5
LSBF
0
4
MSTR
0
3
CPOL
1
2
SDIR
0
1
SR1
0
Bit 0
SR0
0
Read:
Write:
Reset:
Figure 12-4. SSI Control Register (SCR)
SIE — SSI Interrupt Enable
This bit determines whether an interrupt request should be generated
when a transfer is complete. Reset clears this bit.
1 = An interrupt request will be made if the CPU is in the run or wait
mode of operation and the status flag bit SF is set.
0 = No interrupt requests will be made by the SSI.
SE — SSI Enable
When this bit is set, it enables the SSI and SCK pins. When this bit is
cleared, any transmission in progress is aborted and the SCK and
SDIO are three-stated. The SE bit is readable and writable any time.
Clearing SE while a data transfer is occurring will abort the
transmission and reset the bit counter. Reset clears this bit.
1 = Enable the SSI module.
0 = Disable the SSI module.
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SSI Registers
LSBF — Least Significant Bit First
The LSBF bit determines the format of the data transfer. The two
formats are least significant bit (LSB) or most significant bit (MSB)
transferred or received first. Reset clears this bit, initializing the SSI to
MSB first order.
1 = Data will be sent and received in an LSB first format.
0 = Data will be sent and received in an MSB first format.
MSTR — Master Mode
Reset clears this bit and configures the SSI for slave operation. MSTR
may be set at any time regardless of the state of SE.
1 = SSI is configured for master mode. The transmission is initiated
by a write to the data register and the SCK pin becomes an
output providing a synchronous data clock at a rate determined
by the SR bit.
0 = SSI is configured to slave mode. Any transmission in progress
is aborted. Transfers are initiated by an external master which
should supply the clock signal to the SCK pin.
CPOL — Clock Polarity
The clock polarity bit controls the state of the SCK pin between
transmissions.
1 = SCK will be high between transmissions.
0 = SCK will be low between transmissions.
In both cases, the data is latched on the rising edge of SCK for serial
input and is valid on the rising edge of SCK for serial output. Reset
sets this bit.
SDIR — Serial Data Direction
When the SE bit = 1, SDIR functions as the output driver enable bit
for the SDIO pin with SSI in master or in slave mode. This bit has no
effect on the SDIO pin when the SSI is disabled (SE = 0). This bit is
cleared by reset.
1 = Enable the output driver of the SDIO pin.
0 = Disable the output driver of the SDIO pin.
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SR1 and SR0 — SSI Clock Rate Select
These bits determine the frequency of SCK when in master mode
(MSTR = 1). They have no effect in slave mode (MSTR = 0).
Table 12-1. Master Mode SCK Frequency Select
SR1
SR0
SCK Frequency
0
0
1
1
0
1
0
1
f
÷ 16
÷ 8
op
f
f
f
op
op
op
÷ 4
÷ 2
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SSI Registers
12.4.2 SSI Sta tus Re g iste r
The SSI status register (SSR) is located at address $000B and contains
three bits.
Address: $000B
Bit 7
SF
0
6
5
0
0
4
0
0
3
0
1
2
0
0
1
0
0
Bit 0
TIPL
0
Read:
Write:
Reset:
DCOL
0
= Unimplemented
Figure 12-5. SSI Status Register (SSR)
SF — SSI Flag
This bit is set upon occurrence of the last rising clock edge and
indicates that a data transfer has taken place. It has no effect on any
further transmissions and can be ignored without problem. However,
SF must be cleared before a master can initiate a transfer. SF is
cleared by reading the SSR with SF set followed by a read or write of
the serial data register. If it is cleared before the last edge of the next
byte, it will be set again. Reset clears this bit.
DCOL — Data Collision
This is a read-only status bit which indicates that an invalid access to
the data register has been made. This can occur any time after the
first falling edge of SCK and before SF is set. DCOL is cleared by
reading the status register with SF set followed by a read or write of
the data register. If the last part of the clearing sequence is done after
another transmission has been started, DCOL will be set again. Reset
also clears this bit.
TIPL
The state of the PB3 pin is latched and placed into this bit on the
eighth rising SCK clock during a shift operation. This is the case
regardless of the state of MSTR and CPOL in the SSI control register.
Reset clears this bit.
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12.4.3 SSI Da ta Re g iste r
This register is located at address $000C and is both the transmit and
receive data register. This system is not double buffered but writes to
this register during transfers are masked and will not destroy the
previous contents. The SDR can be read at any time, but, if a transfer is
in progress the results may be ambiguous. This register should only be
written to when the SSI is enabled (SE = 1).
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Reset Results Unknown
Figure 12-6. SSI Data Register (SDR)
12.5 SSI During Stop Mod e
In stop mode, the SSI halts operation. The SDIO and SCK pins will
maintain their states.
If the SSI was nearing completion of a transfer when the stop mode is
entered, it might be possible for the SSI to generate an interrupt request
and cause the processor to immediately exit stop mode. To prevent this
occurrence, the programmer should ensure that all transfers are
complete before entering stop mode.
If the SSI is configured to slave mode, then further care should be taken
in entering stop mode. In slave mode, the SCK pin will still accept a clock
from an external master, allowing potentially unwanted transfers to take
place and power consumption to be increased. Note that the SSI will not
generate interrupt requests in this situation. However, on exiting stop
mode through some other means, the SF flag may be found to be set. If,
at this point, SIE is also set, an interrupt request will be generated.
NOTE: To avoid these potential problems, it is safer to disable the SSI
completely (SE = 0) before entering stop mode.
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SSI During Wait Mode
12.6 SSI During Wa it Mod e
The CPU clock halts during wait mode, but the SSI remains active. If
interrupts are enabled, an SSI interrupt will cause the processor to exit
wait mode.
12.7 SSI Pin Config ura tion
When the SSI is enabled via the SE bit of the SCR ($0A), the port B data
direction register bits 3–5 relinquish control to the SSI as directed by the
combination of the SE, MSTR, and SDIR bits. The states of the port B
DDR bits are not altered by the SSI.
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05E5
Se c tion 13. Instruc tion Se t
13.1 Conte nts
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .110
Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . .111
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .112
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .114
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
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13.2 Introd uc tion
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
13.3 Ad d re ssing Mod e s
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
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13.3.1 Inhe re nt
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
13.3.2 Im m e d ia te
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
13.3.3 Dire c t
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
13.3.4 Exte nd e d
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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13.3.5 Ind e xe d , No Offse t
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
13.3.6 Ind e xe d , 8-Bit Offse t
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
13.3.7 Ind e xe d ,16-Bit Offse t
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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13.3.8 Re la tive
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
13.4 Instruc tion Typ e s
The MCU instructions fall into the following five categories:
• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions
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13.4.1 Re g iste r/ Me m ory Instruc tions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 13-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Add Memory Byte to Accumulator
AND Memory Byte with Accumulator
Bit Test Accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare Accumulator
CMP
CPX
EOR
LDA
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Multiply
LDX
MUL
ORA
SBC
STA
OR Accumulator with Memory Byte
Subtract Memory Byte and Carry Bit from Accumulator
Store Accumulator in Memory
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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13.4.2 Re a d -Mod ify-Write Instruc tions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE: Do not use read-modify-write operations on write-only registers.
Table 13-2. Read-Modify-Write Instructions
Instruction
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
Bit Clear
Mnemonic
ASL
ASR
(1)
BCLR
(1)
Bit Set
BSET
Clear Register
CLR
COM
DEC
INC
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left (Same as ASL)
Logical Shift Right
LSL
LSR
NEG
ROL
ROR
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
(2)
TST
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence be-
cause it does not write a replacement value.
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13.4.3 Jum p / Bra nc h Instruc tions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Table 13-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Branch if Lower
BHS
BIH
BIL
BLO
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
BLS
BMC
BMI
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
BMS
BNE
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
BRN
BRSET
BSR
Branch Never
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
JMP
JSR
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13.4.4 Bit Ma nip ula tion Instruc tions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 13-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit Clear
Branch if Bit Clear
Branch if Bit Set
Bit Set
BRCLR
BRSET
BSET
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13.4.5 Control Instruc tions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 13-5. Control Instructions
Instruction
Clear Carry Bit
Mnemonic
CLC
CLI
Clear Interrupt Mask
No Operation
NOP
RSP
RTI
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
RTS
SEC
SEI
Set Interrupt Mask
Stop Oscillator and Enable IRQ Pin
Software Interrupt
STOP
SWI
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
TAX
TXA
WAIT
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13.5 Instruc tion Se t Sum m a ry
Table 13-6. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
M oed
H I N Z C
C
O
A
O
ii
ADC #opr
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
2
3
4
5
4
3
dd
hh ll
ee ff
ff
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
2
3
4
5
4
3
Add without Carry
A ← (A) + (M)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
2
3
4
5
4
3
Logical AND
A ← (A) (M)
— — ↕ ↕ —
dd
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
Arithmetic Shift Left (Same as LSL)
— — ↕ ↕ ↕
C
0
ff
b7
b7
b0
b0
dd
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
INH
IX1
IX
37
47
57
67
77
5
3
3
6
5
C
Arithmetic Shift Right
— — ↕ ↕ ↕
ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
BCS rel
BEQ rel
BHCC rel
BHCS rel
BHI rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
25 rr
27 rr
28 rr
29 rr
22 rr
24 rr
3
3
3
3
3
3
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? C Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
BHS rel
Branch if Higher or Same
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Table 13-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL
2F rr
2E rr
3
3
BIL rel
Branch if IRQ Pin Low
ii
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
2
3
4
5
4
3
dd
hh ll
ee ff
ff
Bit Test Accumulator with Memory Byte
(A) (M)
— — ↕ ↕ —
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? C Z = 1 — — — — — REL
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
PC ← (PC) + 2 + rel ? Mn = 1
— — — — ↕
BRN rel
Branch Never
— — — — — REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
— — — — ↕
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
— — — — — REL
AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
9A
2
2
Clear Interrupt Mask
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Table 13-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
dd
ff
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
5
3
3
6
5
Clear Byte
— — 0 1 —
ii
dd
hh ll
ee ff
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
2
3
4
5
4
3
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
Decrement Byte
(A) – (M)
— — ↕ ↕ ↕
dd
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
5
3
3
6
5
— — ↕ ↕
1
ii
dd
hh ll
ee ff
ff
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
2
3
4
5
4
3
(X) – (M)
— — ↕ ↕ ↕
— — ↕ ↕ —
— — ↕ ↕ —
dd
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
5
3
3
6
5
ii
dd
hh ll
ee ff
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
2
3
4
5
4
3
EXCLUSIVE OR Accumulator with Memory
Byte
A ← (A) (M)
dd
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
5
3
3
6
5
Increment Byte
— — ↕ ↕ —
dd
hh ll
ee ff
ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
2
3
4
3
2
Unconditional Jump
PC ← Jump Address
— — — — —
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Instruction Set Summary
Table 13-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
dd
hh ll
ee ff
ff
JSR opr
DIR
BD
CD
DD
ED
FD
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
EXT
IX2
IX1
IX
Jump to Subroutine
— — — — —
ii
dd
hh ll
ee ff
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
2
3
4
5
4
3
Load Accumulator with Memory Byte
A ← (M)
X ← (M)
— — ↕ ↕ —
ii
dd
hh ll
ee ff
ff
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
2
3
4
5
4
3
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
— — ↕ ↕ —
dd
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
C
0
— — ↕ ↕ ↕
b7
b0
ff
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
— — 0 ↕ ↕
0 — — — 0
— — ↕ ↕ ↕
— — — — —
b7
b0
ff
MUL
Unsigned Multiply
X : A ← (X) × (A)
INH
42
11
dd
ff
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
IX1
IX
30
40
50
60
70
5
3
3
6
5
Negate Byte (Two’s Complement)
No Operation
NOP
INH
9D
2
ii
dd
hh ll
ee ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
2
3
4
5
4
3
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
A ← (A) (M)
— — ↕ ↕ —
dd
ff
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
INH
IX1
IX
39
49
59
69
79
5
3
3
6
5
C
— — ↕ ↕ ↕
b7
b0
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Table 13-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
dd
ff
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
INH
IX1
IX
36
46
56
66
76
5
3
3
6
5
C
Rotate Byte Right through Carry Bit
— — ↕ ↕ ↕
b7
b0
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $00FF
— — — — —
INH
9C
2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕ ↕ ↕ ↕ ↕
INH
80
9
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
— — — — —
INH
81
6
ii
dd
hh ll
ee ff
ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
2
3
4
5
4
3
Subtract Memory Byte and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
— — ↕ ↕ ↕
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
9B
2
2
Set Interrupt Mask
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
4
5
6
5
4
Store Accumulator in Memory
Stop Oscillator and Enable IRQ Pin
Store Index Register In Memory
M ← (A)
— — ↕ ↕ —
— 0 — — —
— — ↕ ↕ —
STOP
INH
8E
2
dd
hh ll
ee ff
ff
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
4
5
6
5
4
M ← (X)
ii
dd
hh ll
ee ff
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
2
3
4
5
4
3
Subtract Memory Byte from Accumulator
A ← (A) – (M)
— — ↕ ↕ ↕
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
TAX
Software Interrupt
— 1 — — —
— — — — —
INH
INH
83
97
10
2
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Transfer Accumulator to Index Register
X ← (A)
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Instruction Set
Instruction Set Summary
Table 13-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
M oed
H I N Z C
C
O
A
O
dd
ff
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
4
3
3
5
4
Test Memory Byte for Negative or Zero
(M) – $00
— — ↕ ↕ —
TXA
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
A ← (X)
— — — — —
— 0 — — —
INH
INH
9F
8F
2
2
WAIT
A
C
Accumulator
Carry/borrow flag
opr
PC
Operand (one or two bytes)
Program counter
CCR
dd
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
PCH Program counter high byte
PCL
REL
rel
rr
SP
X
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
dd rr
DIR
ee ff
EXT
ff
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
Index register
H
Z
Zero flag
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
#
Immediate value
Logical AND
ii
Immediate operand byte
Logical OR
IMM
INH
IX
IX1
IX2
M
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
( )
–( )
←
?
:
↕
—
If
Concatenated with
Set or cleared
Not affected
N
n
Negative flag
Any bit
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L
0
1
2
3
4
5
6
7
8
9
F
E
A
B
C
D
MS B
3
3
3
3
3
3
3
4
3
3
3
3
2
5
3
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
A
F
I
B TI
T
L
S
D
S
MJ P
S
S
CP X
A
D
AD
O
O RA
CMP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
5
4
4
4
4
3
6
4
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
I
A
A
E
B TI
I
T
L
S
D
S
MJ P
S
S
CP X
A
D
AD
O
O RA
CMP
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
5
5
5
5
5
5
5
6
5
5
5
5
4
7
5
6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
I
A
A
B TI
I
T
L
J
D
S
MJ P
S
S
CP X
A
D
AD
O
O RA
CMP
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
5
4
4
4
4
3
6
4
5
E
E
E
E
E
E
X
X
X
X
X
X
X
X
X
E
A
A
B TI
T
L
J
D
S
MJ P
S
S
CP X
A
D
AD
E
O
O RA
CMP
M
m
c
N
R
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
3
3
3
3
2
5
3
4
5
General Release Specification
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05E5
Se c tion 14. Ele c tric a l Sp e c ific a tions
14.1 Conte nts
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
14.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
14.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .125
14.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
14.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .126
14.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
14.8 M-Bus Interface Input Signal Timing. . . . . . . . . . . . . . . . . . . .130
14.9 M-Bus Interface Output Signal Timing . . . . . . . . . . . . . . . . . .130
14.2 Introd uc tion
This section contains the electrical and timing specifications.
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Ele c tric a l Sp e c ific a tions
14.3 Ma xim um Ra ting s
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
VSS –0.3 to
VDD +0.3
Input Voltage
VIN
VIN
V
V
VSS –0.3 to
2 x VDD +0.3
Self-Check Mode (IRQ Pin Only)
Current Drain Per Pin Excluding VDD and VSS
Storage Temperature Range
I
25
mA
TSTG
–65 to +150
°C
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 14.6 DC Electrical Characteristics for guaranteed
operating conditions.
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Electrical Specifications
Operating Temperature Range
14.4 Op e ra ting Te m p e ra ture Ra ng e
Characteristic
Symbol
Value
Unit
Operating Temperature Range
MC68HC(7)05E5DW (Standard)
MC68HC(7)05E5P
TL to TH
0 to +70
0 to +70
TA
°C
14.5 The rm a l Cha ra c te ristic s
Characteristic
Symbol
Value
Unit
Thermal Resistance
Plastic DIP
SOIC
θ
60
60
°C/W
JA
I/O Pin Power Dissipation
P
User Determined
W
W
I/O
P = (I x V ) + P =
I/O
(1)
D
DD
DD
Power Dissipation
P
D
K/(T + 273 °C)
J
P x (T + 273 °C)
(2)
D
A
Constant
K
W/°C
2
+ P x θ
D
JA
Average Junction Temperature
Maximum Junction Temperature
NOTES:
T
T + (P x θ )
°C
°C
J
A
D
JA
T
125
JM
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined for a known TA and
measured PD. With this value of K, PD and TJ can be determined for any value of TA.
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Ele c tric a l Sp e c ific a tions
14.6 DC Ele c tric a l Cha ra c te ristic s
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
ILOAD = 10.0 µA
ILOAD = –10.0 µA
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
Output High Voltage
(ILOAD –0.8 mA) PA0–PA7, PB0–PB7, PC0–PC3
VOH
VOL
VIH
VIL
VDD –0.8
—
—
—
—
—
—
0.4
V
V
V
V
Output Low Voltage
(ILOAD = 1.6 mA) PA0–PA7, PB0–PB7, PC0–PC3
Input High Voltage
PA0–PA7, PB0–PB7, PC0–PC3, IRQ, RESET, OSC1
0.7 x VDD
VSS
VDD
Input Low Voltage
PA0–PA7, PB0–PB7, PC0–PC3, IRQ, RESET, OSC1
0.3 x VDD
XFC Wide Bandwidth
Source
Sink
I
I
–50
50
–100
100
—
—
µA
µA
OH
OL
XFC Narrow Bandwidth
Source
Sink
I
I
–1
1
–2
2
—
—
OH
OL
Supply Current (see Notes)
Run
(f = 32.768 kHz, f = 16.384 kHz)
—
—
120
2.5
400
3.5
µA
mA
osc
op
(f = 4.2 MHz, f = 2.1 MHz)
osc
op
Wait
(f = 32.768 kHz, f = 16.384 kHz)
IDD
—
—
50
0.7
150
1
µA
mA
osc
op
(f = 4.2 MHz, f = 2.1 MHz)
osc
op
Stop (PLL Off)
o
25 C
—
—
10
—
50
10
µA
µA
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB0–PB7, PC0–PC3
IOZ
IIN
Input Current
RESET, IRQ, OSC1
—
—
1
µA
Capacitance
Ports as Input or Output
RESET, IRQ
COUT
CINT
—
—
—
—
12
8
pF
NOTES:
1. V = 5.0 Vdc ± 10%, V = 0 Vdc, T = 0 °C to +70 °C, unless otherwise noted
DD
SS
A
2. Typical values at midpoint of voltage range, 25 °C only
3. Wait IDD: Only timer and CPI systems active
4. Run (Operating) IDD, wait IDD: Measured using external square wave clock source; all inputs 0.2 V from rail;
no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2
5. Wait, stop IDD: All ports configured as inputs; VIL = 0.2; VIH = VDD –0.2 V
6. Stop IDD measured with OSC1 = VSS
7. Wait IDD affected linearly by the OSC2 capacitance
General Release Specification
MC68HC05E5 — Rev. 1.0
Electrical Specifications
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Electrical Specifications
DC Electrical Characteristics
3.5
VDD = 5.0 V
TA = –0 °C to 70 °C
3.0
2.5
2.0
1.5
Y C U RR E N T (m A )
1.0
0.5
0
S
0.016 0.277
0.537 0.798 1.058 1.319 1.579 1.840 2.100
OPERATING FREQUENCY (MHz)
Figure 14-1. Maximum Supply Current
versus Operating Frequency
2.5
2.0
V
DD = 5.0 V
TA = –0 °C to 70 °C
1.5
1.0
0.5
0
0.016 0.277
0.537 0.798 1.058 1.319 1.579 1.840 2.100
OPERATING FREQUENCY (MHz)
Figure 14-2. Typical Supply Current
versus Operating Frequency
MC68HC05E5 — Rev. 1.0
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Electrical Specifications
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Ele c tric a l Sp e c ific a tions
14.7 Control Tim ing
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
Crystal Option
External Clock Option
fOSC
—
dc
32.768
4.2
kHz
MHz
Internal Operating Frequency
Crystal (fOSC ÷ 2)
External Clock (fOSC ÷ 2)
fOP
—
dc
16.384
2.1
kHz
MHz
Cycle Time
tCYC
tRL
480
1.5
—
—
—
—
—
—
ns
tCYC
ns
RESET Pulse Width
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
OSC1 Pulse Width
tILIH
125
tILIL
see Note 2
90
tCYC
ns
tOH, tOL
PLL Startup Stabilization Time
NOTES:
t
50
ms
PLLS
o
o
1. V = 5.0 Vdc ± 10%, V = 0 Vdc, T = 0 C to +70 C, unless otherwise noted
DD
SS
A
2. The minimum period, t
should not be less than the number of cycle times it takes to execute the
ILIL,
interrupt service routine plus 19 t
.
cyc
IRQ
tILIH
tILIH
IRQ1
tILIH
.
.
.
NORMALLY USED
WITH WIRE-ORed
CONNECTION
IRQn
IRQ
(MCU)
Figure 14-3. External Interrupt Mode Diagram
General Release Specification
MC68HC05E5 — Rev. 1.0
Electrical Specifications
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Electrical Specifications
Control Timing
P
C
N
N
P
1
MC68HC05E5 — Rev. 1.0
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Electrical Specifications
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Ele c tric a l Sp e c ific a tions
14.8 M-Bus Inte rfa c e Inp ut Sig na l Tim ing
Characteristic
Start Condition Hold Time
Clock Low Period
Symbol
Min
2
Max
—
Unit
t
t
t
t
HD.STA
cyc
cyc
cyc
t
4.7
4
—
LOW
Clock High Period
t
—
HIGH
SDA/SCL Rise Time
tR
—
—
250
0
1.0
300
—
ms
ns
ns
SDA/SCL Fall Time
t
F
Data Setup Time
t
t
SU.DAT
HD.DAT
Data Hold Time
—
t
cyc
cyc
cyc
Start Condition Setup Time (For Repeated Start Condition Only)
Stop Condition Setup Time
t
2
—
t
t
SU.STA
t
2
—
SU.STO
o
o
NOTE: V = 5.0 Vdc ± 10%, V = 0 Vdc, T = –40 C to +85 C, unless otherwise noted
DD
SS
A
14.9 M-Bus Inte rfa c e Outp ut Sig na l Tim ing
Characteristic
Start Condition Hold Time
Clock Low Period
Symbol
Min
12
11
11
—
Max
—
Unit
t
t
t
t
HD.STA
cyc
cyc
cyc
t
—
LOW
Clock High Period
t
—
HIGH
SDA/SCL Rise Time
tR
1.0
300
—
ms
ns
ns
SDA/SCL Fall Time
t
—
F
Data Setup Time
t
t
t
–t
SU.DAT
HD.DAT
Low cyc
Data Hold Time
0
—
t
cyc
cyc
cyc
Start Condition Setup Time (For Repeated Start Condition Only)
Stop Condition Setup Time
t
10
12
—
t
t
SU.STA
t
—
SU.STO
o
o
NOTE: V = 5.0 Vdc ± 10%, V = 0 Vdc, T = –40 C to +85 C, unless otherwise noted
DD
SS
A
General Release Specification
MC68HC05E5 — Rev. 1.0
Electrical Specifications
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Electrical Specifications
M-Bus Interface Output Signal Timing
SDA
SCL
t
t
t
t
HIGH
HD.DAT
SU.STO
HD.STA
t
t
SU.DAT
LOW
Figure 14-5. M-Bus Interface Timing
MC68HC05E5 — Rev. 1.0
General Release Specification
Electrical Specifications
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Ele c tric a l Sp e c ific a tions
General Release Specification
MC68HC05E5 — Rev. 1.0
Electrical Specifications
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05E5
Se c tion 15. Me c ha nic a l Da ta
15.1 Conte nts
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
15.3 28-Pin Plastic Dual-in-Line Package (Case 710-02) . . . . . . .133
15.4 28-Pin Small Outline Integrated
Circuit Package (Case 751F-04) . . . . . . . . . . . . . . . . . . . .134
15.2 Introd uc tion
This section describes the dimensions of the plastic dual in-line package
(PDIP) and small outline integrated circuit (SOIC) MCU packages.
15.3 28-Pin Pla stic Dua l-in-Line Pa c ka g e (Ca se 710-02)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
28
1
15
14
2. DIMENSION
WHEN FORMED PARALLEL.
3. DIMENSION DOES NOT INCLUDE
MOLD FLASH.
L
TO CENTER OF LEADS
B
B
MILLIMETERS
MIN MAX
INCHES
MIN MAX
DIM
A
B
C
D
F
36.45 37.21
13.72 14.22
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
L
A
C
3.94
0.36
1.02
5.08
0.56
1.52
N
G
H
J
2.54 BSC
0.100 BSC
0.065 0.085
0.008 0.015
0.115 0.135
1.65
0.20
2.92
2.16
0.38
3.43
J
H
G
K
L
M
K
SEATING
PLANE
15.24 BSC
0.600 BSC
F
D
0°
0.51
15°
1.02
0°
0.020 0.040
15°
M
N
MC68HC05E5 — Rev. 1.0
General Release Specification
Mechanical Data
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Me c ha nic a l Da ta
15.4 28-Pin Sm a ll Outline Inte g ra te d Circ uit Pa c ka g e (Ca se 751F-04)
-A-
NOTES:
28
1
15
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION
PROTRUSION.
14X P
M
-B-
0.010 (0.25M)
B
A
AND
B
DO NOT INCLUDE MOLD
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
14
5. DIMENSION
D
DOES NOT INCLUDE
DAMBAR PROTRUSIONA. LLOWABLE
28X D
DAMBAR PROTRUSION SHALL BE 0.13
D
(0.005) TOTAL IN EXCESS OF
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
0.010 (0.25M)
T
S
A
S
B
R X 45°
MILLIMETERS
MIN MAX
17.80 18.05
INCHES
MIN MAX
C
DIM
A
-T-
0.701 0.711
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
-T-
SEATING
PLANE
B
7.40
2.35
0.35
0.41
7.60
2.65
0.49
0.90
26X G
C
D
K
F
F
G
J
1.27 BSC
0.23
0.13
0.32
0.29
8°
0.009 0.013
0.005 0.011
J
K
M
P
0°
0°
0.395 0.415
8°
10.05 10.55
0.25 0.75
R
0.010 0.029
General Release Specification
MC68HC05E5 — Rev. 1.0
Mechanical Data
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC05E5
Se c tion 16. Ord e ring Inform a tion
16.1 Conte nts
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
16.3 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
16.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .136
16.5 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .137
16.6 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .138
16.7 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
16.2 Introd uc tion
This section contains instructions for ordering custom-masked ROM
MCUs.
16.3 MCU Ord e ring Form s
To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Motorola representative. Submit the
following items when ordering MCUs:
• A current MCU ordering form that is completely filled out
(Contact your Motorola sales office for assistance.)
• A copy of the customer specification if the customer specification
deviates from the Motorola specification for the MCU
• Customer’s application program on one of the media listed in 16.4
Application Program Media
MC68HC05E5 — Rev. 1.0
General Release Specification
Ordering Information
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Ord e ring Inform a tion
The current MCU ordering form is also available through the Motorola
Freeware Bulletin Board Service (BBS). The telephone number is (512)
891-FREE. After making the connection, type bbsin lowercase letters.
Then press the return key to start the BBS software.
16.4 Ap p lic a tion Prog ra m Me d ia
Please deliver the application program to Motorola in one of the following
media:
®1
• Macintosh 3 1/2-inch diskette (double-sided 800 K or
double-sided high-density 1.4 M)
®2
• MS-DOS or PC-DOSTM3 3 1/2-inch diskette (double-sided 720
K or double-sided high-density 1.44 M)
®
• MS-DOS or PC-DOSTM 5 1/4-inch diskette (double-sided
double-density 360 K or double-sided high-density 1.2 M)
Use positive logic for data and addresses.
When submitting the application program on a diskette, clearly label the
diskette with the following information:
• Customer name
• Customer part number
• Project or product name
• File name of object code
• Date
• Name of operating system that formatted diskette
• Formatted capacity of diskette
On diskettes, the application program must be in Motorola’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation.
3. PC-DOS is a trademark of International Business Machines Corporation.
General Release Specification
MC68HC05E5 — Rev. 1.0
Ordering Information
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Ordering Information
ROM Program Verification
NOTE: Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all nonuser ROM
locations or leave all nonuser ROM locations blank. Refer to the current
MCU ordering form for additional requirements. Motorola may request
pattern re-submission if nonuser areas contain any nonzero code.
If the memory map has two user ROM areas with the same addresses,
then write the two areas in separate files on the diskette. Label the
diskette with both filenames.
In addition to the object code, a file containing the source code can be
included. Motorola keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the filename of the source code.
16.5 ROM Prog ra m Ve rific a tion
The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
Motorola inputs the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain nonuser ROM code, such as
self-check code. Motorola sends the customer a computer printout of the
listing verify file along with a listing verify form.
To aid the customer in checking the listing verify file, Motorola will
program the listing verify file into customer-supplied blank preformatted
Macintosh or DOS disks. All original pattern media are filed for
contractual purposes and are not returned.
Check the listing verify file thoroughly, then complete and sign the listing
verify form and return the listing verify form to Motorola. The signed
listing verify form constitutes the contractual agreement for the creation
of the custom mask.
MC68HC05E5 — Rev. 1.0
General Release Specification
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Ord e ring Inform a tion
16.6 ROM Ve rific a tion Units (RVUs)
After receiving the signed listing verify form, Motorola manufactures a
custom photographic mask. The mask contains the customer’s
application program and is used to process silicon wafers. The
application program cannot be changed after the manufacture of the
mask begins. Motorola then produces 10 MCUs, called RVUs, and
sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are
not tested to environmental extremes because their sole purpose is to
demonstrate that the customer’s user ROM pattern was properly
implemented. The 10 RVUs are free of charge with the minimum order
quantity. These units are not to be used for qualification or production.
RVUs are not guaranteed by Motorola Quality Assurance.
16.7 MC Ord e r Num b e rs
Table 16-1 shows the MC order numbers for the available package
types.
Table 16-1. MC Order Numbers
Operating
MC Order
Package Type
Temperature
Range
Number
28-Pin Plastic Dual In-Line Package (PDIP)
0 °C to 70°C
0 °C to 70°C
MC68HC05E5P
MC68HC05E5DW
28-Pin Small Outline Integrated Circuit
Package (SOIC)
General Release Specification
MC68HC05E5 — Rev. 1.0
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相关型号：
MC68HC05E6CDW
Microcontroller, 8-Bit, MROM, 6805 CPU, 2.1MHz, HCMOS, PDSO28, PLASTIC, SOIC-28
MOTOROLA
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