MC68HC08TV24CFB_技术文档

Advance Information — MC68HC908TV24

List of Sections

Section 1. General Description . . . . . . . . . . . . . . . . . . . 29

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 41

Section 3. Low-Power Modes . . . . . . . . . . . . . . . . . . . . . 57

Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 67

Section 5. Analog-to-Digital Converter (ADC4) . . . . . . 81

Section 6. Break Module (BRK). . . . . . . . . . . . . . . . . . . . 87

Section 7. Clock Generator Module (CGMC) . . . . . . . 97

Section 8. Closed-Caption Data Slicer (DSL) . . . . . . . 127

Section 9. Configuration Register (CONFIG). . . . . . . . 143

Section 10. Computer Operating Properly (COP) . . . 147

Section 11. Central Processor Unit (CPU) . . . . . . . . . . 153

Section 12. User FLASH Memory. . . . . . . . . . . . . . . . . . 171

Section 13. On-Screen Display (OSD)

FLASH Memory . . . . . . . . . . . . . . . . . . . . 185

Section 14. External Interrupt (IRQ) . . . . . . . . . . . . . . . 195

Section 15. Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . 201

Section 16. Monitor ROM (MON) . . . . . . . . . . . . . . . . . 207

Section 17. On-Screen Display Module (OSD) . . . . . . 221

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List of Sections

Section 18. Input/Output (I/O) Ports . . . . . . . . . . . . . . 267

Section 19. Random-Access Memory (RAM). . . . . . . 277

Section 20. System Integration Module (SIM). . . . . . . 279

Section 21. Serial Synchronous Interface

Module (SSI) . . . . . . . . . . . . . . . . . . . . . . . 305

Section 22. Timebase Module (TBM) . . . . . . . . . . . . . . 319

Section 23. Timer Interface Module (TIM) . . . . . . . . . . 325

Section 24. ROM Version Overview (ROM) . . . . . . . . . 349

Section 25. Preliminary Electrical Specifications . . . . 353

Section 26. Mechanical Specifications. . . . . . . . . . . . 363

Section 27. Ordering Information. . . . . . . . . . . . . . . . . 365

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MC68HC908TV24 — Rev. 2.1

List of Sections

Freescale Semiconductor

Advance Information — MC68HC908TV24

Table of Contents

Section 1. General Description

1.1

1.2

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

1.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Television Application-Specific Features . . . . . . . . . . . . . . .32

CPU08 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

1.3.1

1.3.2

1.3.3

1.4

1.5

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

1.6

1.6.1

1.6.2

1.6.3

1.6.4

1.6.5

1.6.6

1.6.7

Power Supply Pins (V and V ). . . . . . . . . . . . . . . . . . . .36

DD SS

Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .37

External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .37

External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .37

CGM Power Supply Pins (V

and V

) . . . . . . . .37

DDCGM

SSCGM

External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .37

Power Supply Pins for On-Screen Display

(V

and V

). . . . . . . . . . . . . . . . . . . . . . . . . . .37

SSOSD

DDOSD

1.6.8

1.6.9

External Filter Pins for On-Screen Display

(OSDVCO and OSDPMP). . . . . . . . . . . . . . . . . . . . . . . .38

Synchronism Signals (HSYNC and VSYNC) . . . . . . . . . . . .38

1.6.10 Color Encoded Pixel Signals (R, G, B, and I). . . . . . . . . . . .38

1.6.11 Fast Blanking Signal (FBKG) . . . . . . . . . . . . . . . . . . . . . . . .38

1.6.12 Serial Synchronous Interface Clocks

(SCL1 and SCL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

1.6.13 Serial Synchronous Interface Data Lines

(SDA1 and SDA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

1.6.14 Video Input (VIDEO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

1.6.15 A/D Converter Input (ADCIN). . . . . . . . . . . . . . . . . . . . . . . .39

1.6.16 Timer I/O Pins (TCH1 and TCH0) . . . . . . . . . . . . . . . . . . . .39

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1.6.17 Timer External Clock Input (TCLK) . . . . . . . . . . . . . . . . . . .39

1.6.18 Port A I/O Pins (PTA7–PTA0) . . . . . . . . . . . . . . . . . . . . . . .39

1.6.19 Port B I/O Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . .39

1.6.20 Port C I/O Pins (PTC4–PTC0) . . . . . . . . . . . . . . . . . . . . . . .40

1.6.21 Scan Enable (SCANEN). . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Section 2. Memory Map

2.1

2.2

2.3

2.4

2.5

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . .41

Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .42

Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Section 3. Low-Power Modes

3.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

3.2

3.2.1

3.2.2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

3.3

A/D Converter (ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.4

3.4.1

3.4.2

Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.5

3.5.1

3.5.2

Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . .59

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.6

3.6.1

3.6.2

Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . .60

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.7

Closed-Caption Data Slicer Module (DSL) . . . . . . . . . . . . . . . .61

3.8

3.8.1

3.8.2

Computer Operating Properly Module (COP). . . . . . . . . . . . . .61

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

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3.9

3.9.1

3.9.2

External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .61

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . .62

3.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.11 On-Screen Display Module (OSD) . . . . . . . . . . . . . . . . . . . . . .62

3.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.12 Serial Synchronous Interface Module (SSI) . . . . . . . . . . . . . . .63

3.13 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.14 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.14.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.14.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.16 Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Section 4. Resets and Interrupts

4.1

4.2

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

4.3

Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

System Integration Module (SIM) Reset Status Register. . .71

4.3.1

4.3.2

4.3.3

4.3.4

4.4

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .79

4.4.1

4.4.2

4.4.3

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Section 5. Analog-to-Digital Converter (ADC4)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

5.1

5.2

5.3

5.4

5.5

Programming Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

5.5.1

5.5.2

5.5.3

5.6

5.7

5.8

ADC Control and Status Register. . . . . . . . . . . . . . . . . . . . . . .84

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Interrupts and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Section 6. Break Module (BRK)

6.1

6.2

6.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

6.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Flag Protection During Break Interrupts. . . . . . . . . . . . . . . .90

CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . .90

TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .90

COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . .90

6.4.1

6.4.2

6.4.3

6.4.4

6.5

6.5.1

6.5.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

6.6

Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Break Status and Control Register. . . . . . . . . . . . . . . . . . . .92

Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .93

SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . .94

SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . .95

6.6.1

6.6.2

6.6.3

6.6.4

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Section 7. Clock Generator Module (CGMC)

7.1

7.2

7.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

7.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .101

PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . .102

Manual and Automatic PLL Bandwidth Modes. . . . . . . . . .103

Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Special Programming Exceptions . . . . . . . . . . . . . . . . . . .108

Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . .108

CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . .109

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

7.4.6

7.4.7

7.4.8

7.4.9

7.5

Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .110

Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .110

External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . .111

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

7.5.6

7.5.7

7.5.8

PLL Analog Power Pin (V

). . . . . . . . . . . . . . . . . . . .111

DDCGM

PLL Analog Ground Pin (V

) . . . . . . . . . . . . . . . . . . .111

SSCGM

Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .111

CGMC Base Clock Output (CGMOUT) . . . . . . . . . . . . . . .112

CGMC CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . .112

7.6

CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .117

PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . .118

PLL Multiplier Select Register Low. . . . . . . . . . . . . . . . . . .119

PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .120

PLL Reference Divider Select Register . . . . . . . . . . . . . . .121

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.6

7.7

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

7.8

Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

CGMC During Break Interrupts . . . . . . . . . . . . . . . . . . . . .123

7.8.1

7.8.2

7.8.3

7.9

Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .123

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7.9.1

7.9.2

7.9.3

Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .124

Parametric Influences on Reaction Time . . . . . . . . . . . . . .124

Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Section 8. Closed-Caption Data Slicer (DSL)

8.1

8.2

8.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

8.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Line and Field Detection. . . . . . . . . . . . . . . . . . . . . . . . . . .129

Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

8.4.1

8.4.2

8.4.3

8.5

Programming Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

8.5.1

8.5.2

8.5.3

8.6

8.6.1

8.6.2

Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

VSYNC, HSYNC, and Video Input Requirements . . . . . . .132

8.7

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

DSL Character Registers . . . . . . . . . . . . . . . . . . . . . . . . . .135

8.7.1

8.7.2

8.7.3

8.7.4

DSL Control Register 1

DSL Control Register 2

. . . . . . . . . . . . . . . . . . . . . . . . .136

. . . . . . . . . . . . . . . . . . . . . . . . .138

DSL Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Interrupts and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

8.8

8.9

Section 9. Configuration Register (CONFIG)

9.1

9.2

9.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

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Section 10. Computer Operating Properly (COP)

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

10.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.4.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .150

10.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .152

Section 11. Central Processor Unit (CPU)

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

11.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

11.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

11.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

11.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

11.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

11.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . .159

11.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . .161

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11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

11.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .162

11.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

11.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Section 12. User FLASH Memory

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

12.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

12.5 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

12.5.1 FLASH Charge Pump Frequency Control . . . . . . . . . . . . .175

12.6 FLASH Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

12.7 FLASH Program/Margin Read Operation. . . . . . . . . . . . . . . .178

12.8 User FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . .181

12.9 User FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . .182

12.10 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

12.11 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Section 13. On-Screen Display (OSD)

FLASH Memory

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

13.4 OSD FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . .187

13.5 Charge Pump Frequency Control. . . . . . . . . . . . . . . . . . . . . .189

13.6 FLASH Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

13.7 FLASH Program/Margin Read Operation. . . . . . . . . . . . . . . .192

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13.8 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

13.9 OSD FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . .193

Section 14. External Interrupt (IRQ)

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

14.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

14.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .199

14.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .199

Section 15. Low-Voltage Inhibit (LVI)

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

15.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .204

15.4.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .204

15.4.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

15.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

15.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

15.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

15.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

15.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

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Section 16. Monitor ROM (MON)

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

16.4.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .210

16.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

16.4.3 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

16.4.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

16.4.5 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

16.4.6 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Section 17. On-Screen Display Module (OSD)

17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

17.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

17.4.1 Single-Row Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . .225

17.4.2 Display Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

17.4.3 Registers and Pixel Memory . . . . . . . . . . . . . . . . . . . . . . .226

17.4.4 OSD Output Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

17.5 Display Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

17.5.1 Closed-Caption Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

17.5.2 On-Screen Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . .230

17.6 FLASH Programming Guidelines . . . . . . . . . . . . . . . . . . . . . .234

17.7 Programming Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

17.7.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

17.7.2 Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

17.7.3 Software Controlled Features. . . . . . . . . . . . . . . . . . . . . . .242

17.8 Input and Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

17.8.1 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

17.8.2 Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

17.8.3 PLL Filter Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

17.8.4 Output Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

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17.9 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

17.9.1 OSD Character Registers. . . . . . . . . . . . . . . . . . . . . . . . . .245

17.9.2 OSD Vertical Delay Register . . . . . . . . . . . . . . . . . . . . . . .251

17.9.3 OSD Horizontal Delay Register . . . . . . . . . . . . . . . . . . . . .252

17.9.4 OSD Foreground Control Register. . . . . . . . . . . . . . . . . . .252

17.9.5 OSD Background Control Register . . . . . . . . . . . . . . . . . .254

17.9.6 OSD Border Control Register. . . . . . . . . . . . . . . . . . . . . . .255

17.9.7 OSD Enable Control Register . . . . . . . . . . . . . . . . . . . . . .257

17.9.8 OSD Event Line Register . . . . . . . . . . . . . . . . . . . . . . . . . .259

17.9.9 OSD Event Count Register . . . . . . . . . . . . . . . . . . . . . . . .260

17.9.10 OSD Output Control Register. . . . . . . . . . . . . . . . . . . . . . .260

17.9.11 OSD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

17.9.12 OSD Matrix Start Register . . . . . . . . . . . . . . . . . . . . . . . . .263

17.9.13 OSD Matrix End Register. . . . . . . . . . . . . . . . . . . . . . . . . .265

17.10 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

17.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

17.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

17.11 Interrupts and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

Section 18. Input/Output (I/O) Ports

18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267

18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267

18.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269

18.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269

18.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .270

18.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

18.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

18.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .273

18.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

18.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

18.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .275

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Section 19. Random-Access Memory (RAM)

19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

Section 20. System Integration Module (SIM)

20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279

20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

20.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .283

20.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

20.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . .284

20.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . .284

20.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .284

20.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

20.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . .286

20.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

20.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .289

20.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . .290

20.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .290

20.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

20.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

20.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

20.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

20.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . .296

20.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297

20.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297

20.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298

20.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300

20.8.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .300

20.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .301

20.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .303

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Section 21. Serial Synchronous Interface

Module (SSI)

21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306

21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306

21.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307

21.4.1 START Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308

21.4.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . .309

21.4.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

21.4.4 STOP Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310

21.4.5 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . .310

21.4.6 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310

21.4.7 Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311

21.5 Programming Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . .311

21.5.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311

21.5.2 Interrupt Serving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312

21.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313

21.6.1 SSI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313

21.6.2 SSI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

21.6.3 SSI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

21.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

21.8 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

Section 22. Timebase Module (TBM)

22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319

22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319

22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319

22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

22.5 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . .321

22.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

22.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

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Section 23. Timer Interface Module (TIM)

23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325

23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

23.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

23.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .329

23.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329

23.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329

23.4.4 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .330

23.4.5 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . .330

23.4.6 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .331

23.4.7 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . .332

23.4.8 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . .333

23.4.9 PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334

23.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

23.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

23.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336

23.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336

23.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .336

23.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337

23.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337

23.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .337

23.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .340

23.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .341

23.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . .342

23.9.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .346

Section 24. ROM Version Overview (ROM)

24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

24.3 FLASH for ROM Substitution . . . . . . . . . . . . . . . . . . . . . . . . .349

24.4 Configuration Register Programming . . . . . . . . . . . . . . . . . . .351

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Section 25. Preliminary Electrical Specifications

25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

25.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .354

25.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .355

25.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

25.6 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .356

25.7 5.0-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358

25.8 ADC4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359

25.9 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .359

25.10 Clock Generation Module Characteristics . . . . . . . . . . . . . . .359

25.10.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . .359

25.10.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .360

25.11 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361

25.12 5.0-V SSI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .362

Section 26. Mechanical Specifications

26.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363

26.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363

26.3 52-Pin Plastic Quad Flat Pack (PQFP). . . . . . . . . . . . . . . . . .364

Section 27. Ordering Information

27.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

27.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

27.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

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Title

Page

1-1

1-2

1-3

MC68HC908TV24 Block Diagram . . . . . . . . . . . . . . . . . . . .34

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . .36

2-1

2-2

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . .45

4-1

4-2

4-3

4-4

4-5

4-6

4-7

4-8

Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Power-On Reset Recovery. . . . . . . . . . . . . . . . . . . . . . . . . .70

SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . .72

Interrupt Stacking Order. . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . . .74

Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Interrupt Status Register 1 (INT1) . . . . . . . . . . . . . . . . . . . .80

Interrupt Status Register 2 (INT2) . . . . . . . . . . . . . . . . . . . .80

5-1

5-2

5-3

ADC4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

ADC Conversion Code Example . . . . . . . . . . . . . . . . . . . . .83

ADC Control and Status Register (ADCCSR) . . . . . . . . . . .84

6-1

6-2

6-3

6-4

6-5

6-7

6-6

6-8

Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . .89

I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Break Status and Control Register (BRKSCR) . . . . . . . . . .92

Break Address Register High (BRKH) . . . . . . . . . . . . . . . . .93

Break Address Register Low (BRKL). . . . . . . . . . . . . . . . . .93

Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . .94

SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . .95

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Page

7-1

7-2

7-3

7-4

7-5

7-6

7-7

7-8

7-9

7-10

CGMC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

CGMC Exernal Connections . . . . . . . . . . . . . . . . . . . . . . .110

CGMC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . .113

PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . .114

PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . .117

PLL Multiplier Select Register High (PMSH) . . . . . . . . . . .118

PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . .119

PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . .120

PLL Reference Divider Select Register (PMDS) . . . . . . . .121

PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

8-1

8-2

8-3

8-4

8-5

8-6

8-7

8-8

8-9

8-10

Data Slicer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .129

Slicer Input and Output. . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Video Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

DSL Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

DSL Character Registers (DSLCH1 and DSLCH2) . . . . . .135

DSL Control Register 1 (DSLCR1). . . . . . . . . . . . . . . . . . .136

DSL Control Register 2 (DSLCR2). . . . . . . . . . . . . . . . . . .138

Data and Sync Slicing . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Conditions for Setting Vertical Pulse Delay . . . . . . . . . . . .140

DSL Status Register (DSLSR) . . . . . . . . . . . . . . . . . . . . . .141

9-1

Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . .144

10-1

10-2

COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . .150

11-1

11-2

11-3

11-4

11-5

11-6

CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . .159

12-1

12-2

User FLASH Control Register (FL1CR) . . . . . . . . . . . . . . .173

Smart Programming Algorithm Flowchart . . . . . . . . . . . . .180

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12-3

User FLASH Block Protect Register (FL1BPR) . . . . . . . . .182

13-1

13-2

13-3

Connection of the OSD FLASH Memory . . . . . . . . . . . . . .186

FLASH Control Register (FL2CR) . . . . . . . . . . . . . . . . . . .187

OSD FLASH Block Protect Register (FL2BPR) . . . . . . . . .193

14-1

14-2

14-3

IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .197

IRQ I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .197

IRQ Status and Control Register (INTSCR). . . . . . . . . . . .200

15-1

15-2

15-3

LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .203

LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .203

LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . .205

16-1

16-2

16-3

16-4

16-5

16-6

16-7

16-8

16-9

16-10

16-11

16-12

Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Monitor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

Sample Monitor Waveforms. . . . . . . . . . . . . . . . . . . . . . . .212

Break Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Read Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

READ (Read Memory) Command . . . . . . . . . . . . . . . . . . .215

WRITE (Write Memory) Command . . . . . . . . . . . . . . . . . .215

IREAD (Indexed Read) Command. . . . . . . . . . . . . . . . . . .216

IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . .216

READSP (Read Stack Pointer) Command. . . . . . . . . . . . .217

RUN (Run User Program) Command. . . . . . . . . . . . . . . . .217

Monitor Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . .218

17-1

17-2

17-3

17-4

17-5

17-6

17-7

17-8

17-9

OSD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

Active Display Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

CC-ROM Pixel Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

Boundary Conditions with Italics . . . . . . . . . . . . . . . . . . . .230

OSD-ROM Pixel Matrix with Northwest Shadow . . . . . . . .231

Example of 3D Shadow . . . . . . . . . . . . . . . . . . . . . . . . . . .231

Behavior of Control Characters in OSD Mode . . . . . . . . . .232

Overlaying Characters to Get Two Foreground Colors . . .233

OSD FLASH Memory Map. . . . . . . . . . . . . . . . . . . . . . . . .234

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Page

17-10

17-11

17-12

17-13

17-14

17-15

17-16

17-17

17-18

17-19

17-20

17-21

17-22

17-23

17-24

17-25

17-26

17-27

17-28

17-29

17-30

17-31

17-32

17-33

OSD Pixel Matrix in FLASH Memory . . . . . . . . . . . . . . . . .235

CC Pixel Matrix in FLASH Memory . . . . . . . . . . . . . . . . . .236

Spaces and Box-Making Characters in CC Mode . . . . . . .237

Pixel Matrices Organization in FLASH . . . . . . . . . . . . . . . .238

PLL Filter Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

OSD Character Registers (OSDCHAR1–OSDCHAR34) . .245

CC Mode Control Character — Format A . . . . . . . . . . . . .246

CC Mode Control Character — Format B . . . . . . . . . . . . .246

CC Mode Control Character — Format C . . . . . . . . . . . . .246

OSD Mode Control Character — Format A . . . . . . . . . . . .248

OSD Mode Control Character — Format B . . . . . . . . . . . .248

OSD Mode Control Character — Format C . . . . . . . . . . . .248

OSD Vertical Delay Register (OSDVDR) . . . . . . . . . . . . . .251

OSD Horizontal Delay Register (OSDHDR). . . . . . . . . . . .252

OSD Foreground Control Register (OSDFCR) . . . . . . . . .253

OSD Background Control Register (OSDBKCR) . . . . . . . .254

OSD Border Control Register (OSDBCR) . . . . . . . . . . . . .255

OSD Enable Control Register (OSDECTR) . . . . . . . . . . . .257

OSD Event Line Register (OSDELR). . . . . . . . . . . . . . . . .259

OSD Event Count Register (OSDECR) . . . . . . . . . . . . . . .260

OSD Output Control Register (OSDOCR) . . . . . . . . . . . . .260

OSD Status Register (OSDSR) . . . . . . . . . . . . . . . . . . . . .262

OSD Matrix Start Register (OSDMSR). . . . . . . . . . . . . . . .264

OSD Matrix End Register (OSDMER) . . . . . . . . . . . . . . . .265

18-1

18-2

18-3

18-4

18-5

18-6

18-7

18-8

18-9

18-10

I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . .268

Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .269

Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .270

Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .272

Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .273

Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .274

Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . .275

Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276

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20-1

20-2

20-3

20-4

20-5

20-6

20-7

20-8

SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

SIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .282

CGM Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . .286

POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

Interrupt Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . .291

Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . .293

Interrupt Status Register 1 (INT1) . . . . . . . . . . . . . . . . . . .295

Interrupt Status Register 2 (INT2) . . . . . . . . . . . . . . . . . . .295

Wait Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .297

Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . .298

Wait Recovery from Internal Reset . . . . . . . . . . . . . . . . . .298

Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .299

Stop Mode Recovery from Interrupt or Break. . . . . . . . . . .299

SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . .300

SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . .301

SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .303

20-9

20-10

20-11

20-12

20-13

20-14

20-15

20-16

20-17

20-18

20-19

20-20

20-21

21-1

21-2

21-3

21-4

21-5

SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307

Transmission Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308

SSI Control Register (SSICR) . . . . . . . . . . . . . . . . . . . . . .313

SSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . .315

SSI Data Register (SSIDR) . . . . . . . . . . . . . . . . . . . . . . . .316

22-1

22-2

Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .320

Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . .321

23-1

23-2

23-3

23-4

23-5

TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327

TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .328

PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .332

TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .338

TIM Counter Register High (TCNTH). . . . . . . . . . . . . . . . .340

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

Advance Information

List of Figures

25

List of Figures

Figure

Title

Page

23-6

23-7

23-8

23-9

23-10

23-11

23-12

23-13

23-14

23-15

TIM Counter Register Low (TCNTL) . . . . . . . . . . . . . . . . .340

TIM Counter Modulo Register High (TMODH) . . . . . . . . . .341

TIM Counter Modulo Register Low (TMODL). . . . . . . . . . .341

TIM Channel 0 Status and Control Register (TSC0) . . . . .342

TIM Channel 1 Status and Control Register (TSC1) . . . . .342

CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345

TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . .346

TIM Channel 0 Register Low (TCH0L). . . . . . . . . . . . . . . .346

TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . .347

TIM Channel 1 Register Low (TCH1L). . . . . . . . . . . . . . . .347

24-1

25-1

MC68HC08TV24 Block Diagram . . . . . . . . . . . . . . . . . . . .350

SSI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362

Advance Information

26

MC68HC908TV24 — Rev. 2.1

List of Figures

Freescale Semiconductor

Advance Information — MC68HC908TV24

List of Tables

Table

Title

Page

2-1

Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

4-1

4-2

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Interrupt Source Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

7-1

7-2

7-3

Numeric Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

PRE 1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . .116

VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . .116

8-1

8-2

8-3

Line Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Data Slicer Bias Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Minimum Vertical Pulse Width . . . . . . . . . . . . . . . . . . . . . . .139

11-1

11-2

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

12-1

12-2

Charge Pump Clock Frequency . . . . . . . . . . . . . . . . . . . . . .175

Erase Block Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

13-1

13-2

Charge Pump Clock Frequency . . . . . . . . . . . . . . . . . . . . . .189

Erase Block Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

15-1

LVIOUT Bit Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

16-1

16-2

Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

17-1

17-2

SHAD1 and SHAD0 Meaning. . . . . . . . . . . . . . . . . . . . . . . .250

Memory Test Mode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

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List of Tables

27

List of Tables

Table

Title

Page

18-1

18-2

18-3

Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276

20-1

20-2

20-3

20-4

Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . .281

PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300

21-1

22-1

SCL Rates (Hz) at Bus Frequency . . . . . . . . . . . . . . . . . . . .315

Timebase Rate Selection for OSC1 = 32.768 kHz. . . . . . . .321

23-1

23-2

Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . .344

27-1

MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

Advance Information

28

MC68HC908TV24 — Rev. 2.1

List of Tables

Freescale Semiconductor

Advance Information — MC68HC908TV24

Section 1. General Description

1.1 Contents

1.2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

1.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Television Application Specific Features . . . . . . . . . . . . . . .32

CPU08 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

1.3.1

1.3.2

1.3.3

1.4

1.5

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

1.6

1.6.1

1.6.2

1.6.3

1.6.4

1.6.5

1.6.6

1.6.7

Power Supply Pins (V and V ). . . . . . . . . . . . . . . . . . . .36

DD SS

Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .37

External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .37

External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .37

CGM Power Supply Pins (V

and V

) . . . . . . . .37

DDCGM

SSCGM

External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .37

Power Supply Pins for On-Screen Display

(V

and V

). . . . . . . . . . . . . . . . . . . . . . . . . . .37

DDOSD

SSOSD

1.6.8

1.6.9

External Filter Pins for On-Screen Display

(OSDVCO and OSDPMP). . . . . . . . . . . . . . . . . . . . . . . .38

Synchronism Signals (HSYNC and VSYNC) . . . . . . . . . . . .38

1.6.10 Color Encoded Pixel Signals (R, G, B, and I). . . . . . . . . . . .38

1.6.11 Fast Blanking Signal (FBKG) . . . . . . . . . . . . . . . . . . . . . . . .38

1.6.12 Serial Synchronous Interface Clocks (SCL1 and SCL2) . . .38

1.6.13 Serial Synchronous Interface Data Lines

(SDA1 and SDA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

1.6.14 Video Input (VIDEO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

1.6.15 A/D Converter Input (ADCIN). . . . . . . . . . . . . . . . . . . . . . . .39

1.6.16 Timer I/O Pins (TCH1 and TCH0) . . . . . . . . . . . . . . . . . . . .39

1.6.17 Timer External Clock Input (TCLK) . . . . . . . . . . . . . . . . . . .39

1.6.18 Port A I/O Pins (PTA7–PTA0) . . . . . . . . . . . . . . . . . . . . . . .39

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

Advance Information

29

General Description

1.2 Introduction

1.6.19 Port B I/O Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . .39

1.6.20 Port C I/O Pins (PTC4–PTC0) . . . . . . . . . . . . . . . . . . . . . . .40

1.6.21 Scan Enable (SCANEN). . . . . . . . . . . . . . . . . . . . . . . . . . . .40

The MC68HC908TV24 is a member of the low-cost, high-performance

M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the

family use the enhanced M68HC08 central processor unit (CPU08) and

are available with a variety of modules, memory sizes and types, and

package types.

This part contains an embedded on-screen display module and a

closed-caption controller, making it highly suitable for use as a low-cost

TV or VCR microcontroller.

1.3 Features

For convenience, features of the MC68HC908TV24 have been

organized to reflect:

•

Standard features

Television application-specific features

CPU08 features

1.3.1 Standard Features

•

High-performance M68HC08 architecture

Fully upward-compatible object code with M6805, M146805, and

M68HC05 Families

•

8-MHz internal bus frequency

24 Kbytes of on-chip FLASH memory

608 bytes of on-chip random-access memory (RAM)

21 general-purpose input/output (I/O) pins

Advance Information

30

MC68HC908TV24 — Rev. 2.1

General Description

Freescale Semiconductor

General Description

Features

1

•

FLASH program memory security

System protection features:

– Optional computer operating properly (COP) reset

– Low-voltage detection with optional reset and selectable trip

points for 3.0-V and 5.0-V operation

– Illegal opcode detection with reset

– Illegal address detection with reset

Low-power design; fully static with stop and wait modes

Standard low-power modes of operation:

– Wait mode

•

– Stop mode

•

16-bit, 2-channel timer interface module (TIM) with selectable

input capture, output compare, and pulse-width modulation

(PWM) capability on each channel

•

BREAK module (BRK) to allow single breakpoint setting during

in-circuit debugging

Clock generator module with on-chip 32-kHz crystal compatible

PLL (phase-lock loop)

Timebase module with clock prescaler circuitry for eight user

selectable periodic real-time interrupts with active clock source

during stop mode for periodic wakeup from stop using an external

32-kHz crystal

•

Master reset pin and power-on reset (POR)

52-pin plastic quad flat pack (PQFP)

1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or

copying the FLASH difficult for unauthorized users.

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

31

General Description

1.3.2 Television Application-Specific Features

•

On-screen display (OSD) controller

– Works with either 525- or 625-line systems

– Pixel matrix FLASH memory capable of storing 192 9 x 13

closed-caption characters and 128 12 x 18 on-screen display

characters

– 16 rows by 34 columns in closed-caption mode

– 12 rows by 24 columns in on-screen display mode

– Software selectable attributes: 16 foreground and background

colors, black outline, 3D-shadow, underline, and italics

– Two foreground colors are possible in one character by the use

of backspace overlaying of two characters

– Three on-screen display (OSD) character sizes selectable on

a row by row basis:

(1 x 1), (1.5 x 2), and (2 x 2)

– Programmable vertical and horizontal position

– Software controlled features: soft scrolling and blinking

– Support for video muting

– Outputs: R, G, B, I, and FBKG, all with software programmable

polarities

•

Closed-caption data slicer (DSL):

– FCC/EIA-744 V-chip compatible

– FCC/EIA-608 line 21 format data extraction on both field 1 and

field 2

– Software programmable line selection (lines 14 to 29)

– Hardware parity checking

– Software programmable data slicing level

Serial synchronous interface (SSI) — Two independent data ports

with single master I C compatibility (both ports cannot be used

simultaneously)

•

2

Analog-to-digital converter (ADC) — 4-bits resolution

Advance Information

32

MC68HC908TV24 — Rev. 2.1

General Description

Freescale Semiconductor

General Description

MCU Block Diagram

1.3.3 CPU08 Features

Features of the CPU08 include:

•

Enhanced HC05 programming model

Extensive loop control functions

16 addressing modes (eight more than the HC05)

16-bit index register and stack pointer

Memory-to-memory data transfers

Fast 8 × 8 multiply instruction

Fast 16/8 divide instruction

Binary-coded decimal (BCD) instructions

Optimization for controller applications

Efficient C language support

1.4 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908TV24.

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

33

General Description

Pin Assignments

1.5 Pin Assignments

OSDPMP

V_SSCGM

V_DDCGM

CGMXFC

OSC1

OSC2

IRQ

1

39

OSDVCO

2

38

37

36

35

34

33

32

31

30

29

28

VIDEO

3

ADCIN

4

HSYNC

5

VSYNC

6

SCANEN

PTB7

7

R

PTB6

8

G

PTB5

9

B

PTB4

10

I

PTB3

11

FBKG

PTB2

12

SCL1

PTB1

13

27

Figure 1-2. Pin Assignments

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

35

General Description

1.6 Pin Functions

Descriptions of the pin functions are provided here.

1.6.1 Power Supply Pins (V and V )

DD

SS

V

and V are the power supply and ground pins. The MCU operates

SS

DD

from a single power supply.

Fast signal transitions on MCU pins place high, short-duration current

demands on the power supply. To prevent noise problems, take special

care to provide power supply bypassing at the MCU as Figure 1-3

shows. Place the C1 bypass capacitor as close to the MCU as possible.

Use a high-frequency-response ceramic capacitor for C1. C2 is an

optional bulk current bypass capacitor for use in applications that require

the port pins to source high current levels.

MCU

V_DD

V_SS

C1

0.1 µF

+

C2

V_DD

Note: Component values shown represent typical applications.

Figure 1-3. Power Supply Bypassing

Advance Information

36

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

General Description

Pin Functions

1.6.2 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator

circuit. See Section 7. Clock Generator Module (CGMC).

1.6.3 External Reset Pin (RST)

A logic 0 on the RST pin forces the MCU to a known startup state. RST

is bidirectional, allowing a reset of the entire system. It is driven low when

any internal reset source is asserted. See Section 20. System

Integration Module (SIM).

1.6.4 External Interrupt Pin (IRQ)

IRQ is an asynchronous external interrupt pin. See Section 14. External

Interrupt (IRQ).

1.6.5 CGM Power Supply Pins (V

and V

)

SSCGM

DDCGM

V

and V

are the power supply pins for the analog portion of

DDCGM

SSCGM

the clock generator module (CGM). Decoupling of these pins should be

as per the digital supply. See Section 7. Clock Generator Module

(CGMC).

1.6.6 External Filter Capacitor Pin (CGMXFC)

CGMXFC is an external filter capacitor connection for the CGM. See

Section 7. Clock Generator Module (CGMC).

1.6.7 Power Supply Pins for On-Screen Display (V

and V

)

DDOSD

SSOSD

V

and V

are the power supply and ground pins for the

SSOSD

DDOSD

analog part of the on-screen display module (OSD). Decoupling of these

pins should be as per the digital supply. See Section 17. On-Screen

Display Module (OSD).

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

37

General Description

1.6.8 External Filter Pins for On-Screen Display (OSDVCO and OSDPMP)

OSDVCO and OSDPMP are two external filter pins used by the PLL that

extracts the OSD clock from the horizontal sync signal. See Section 17.

On-Screen Display Module (OSD).

1.6.9 Synchronism Signals (HSYNC and VSYNC)

These are two input-only pins used by the on-screen display module to

synchronize to the television signal. These pins contain internal Schmitt

triggers to improve noise immunity. See Section 17. On-Screen

Display Module (OSD).

1.6.10 Color Encoded Pixel Signals (R, G, B, and I)

These are the red, green, blue and intensity output signals from the

on-screen display module. See Section 17. On-Screen Display

Module (OSD).

1.6.11 Fast Blanking Signal (FBKG)

FBKG is an output pin of the on-screen display module. It is used to

blank the TV video when a pixel is being outputted on the R, G, B, and I

pins. See Section 17. On-Screen Display Module (OSD).

1.6.12 Serial Synchronous Interface Clocks (SCL1 and SCL2)

SCL1 and SCL2 are open-drain I/O pins. They are the bidirectional clock

lines of the serial synchronous interface module. See Section 21. Serial

Synchronous Interface Module (SSI).

1.6.13 Serial Synchronous Interface Data Lines (SDA1 and SDA2)

SDA1 and SDA2 are open-drain I/O pins. They are the bidirectional data

lines of the serial synchronous interface module. See Section 21. Serial

Synchronous Interface Module (SSI).

Advance Information

38

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

General Description

Pin Functions

1.6.14 Video Input (VIDEO)

This input-only analog pin is the composite base-band video input signal

for the data slicer module. See Section 8. Closed-Caption Data Slicer

(DSL).

1.6.15 A/D Converter Input (ADCIN)

This is the analog input to the analog-to-digital converter module. See

Section 5. Analog-to-Digital Converter (ADC4).

1.6.16 Timer I/O Pins (TCH1 and TCH0)

These pins are used by the timer interface module. They can be

programmed independently as input capture or output compare pins.

See Section 23. Timer Interface Module (TIM).

1.6.17 Timer External Clock Input (TCLK)

This is an external clock input for the timer module that can be used

instead of the prescaled internal bus clock. See Section 23. Timer

Interface Module (TIM).

1.6.18 Port A I/O Pins (PTA7–PTA0)

PTA7–PTA0 are general-purpose, bidirectional I/O port pins. See

Section 18. Input/Output (I/O) Ports.

1.6.19 Port B I/O Pins (PTB7–PTB0)

PTB7–PTB0 are general-purpose, bidirectional I/O port pins. See

Section 18. Input/Output (I/O) Ports.

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

39

General Description

1.6.20 Port C I/O Pins (PTC4–PTC0)

PTC4–PTC0 are general-purpose, bidirectional I/O port pins. See

Section 18. Input/Output (I/O) Ports.

1.6.21 Scan Enable (SCANEN)

This pin is used only during production test and should be connected to

V

in all user applications.

SS

NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic

level (either V or V ). Although the I/O ports of the

DD

SS

MC68HC908TV24 do not require termination, termination is

recommended to reduce the possibility of static damage.

Advance Information

40

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

General Description

Advance Information — MC68HC908TV24

Section 2. Memory Map

2.1 Contents

2.2

2.3

2.4

2.5

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .41

Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .42

Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

2.2 Introduction

The CPU08 can address 64 Kbytes of memory space. The memory

map, shown in Figure 2-1, includes:

•

24,064 bytes of user FLASH memory

8 Kbytes of on-screen display (OSD) FLASH memory

608 bytes of random-access memory (RAM)

22 bytes of user-defined vectors

240 bytes of monitor read-only memory (ROM)

2.3 Unimplemented Memory Locations

Accessing an unimplemented location can cause an illegal address

reset if illegal address resets are enabled. In the memory map

(Figure 2-1) and in register figures in this document, unimplemented

locations are shaded.

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

Advance Information

41

Memory Map

2.4 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU

operation. In Figure 2-1 and in register figures in this document,

reserved locations are marked with the word Reserved or with the

letter R.

2.5 Input/Output (I/O) Section

Addresses $0000–$004F, shown in Figure 2-2, contain most of the

control, status, and data registers. Additional input/output (I/O) registers

have these addresses:

•

$FE00; SIM break status register, SBSR

$FE01; SIM reset status register, SRSR

$FE02; reserved, SUBAR

$FE03; SIM break flag control register, SBFCR

$FE04; interrupt status register 1, INT1

$FE05; interrupt status register 2, INT2

$FE06; reserved, FL1TCR

$FE07; user FLASH control register, FL1CR

$FE08; reserved, FL2TCR

$FE09; OSD FLASH control register, FL2CR

$FE0A; OSD output control register, OSDOCR

$FE0B; OSD enable control register, OSDECTR

$FE0C; break address register high, BRKH

$FE0D; break address register low, BRKL

$FE0E; break status and control register, BRKSCR

$FE0F; LVI status register, LVISR

$FF80; user FLASH block protect register, FL1BPR

$FF81; OSD FLASH block protect register, FL2BPR

$FFFF; COP control register, COPCTL

Table 2-1 is a list of vector locations.

Advance Information

42

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

Memory Map

Input/Output (I/O) Section

$0000

↓

I/O Registers

80 Bytes

$004F

$0050

↓

RAM

608 Bytes

$02AF

$02B0

↓

Unimplemented

32,080 Bytes

$7FFF

$8000

↓

OSD FLASH Memory

8,192 Bytes

$9FFF

$A000

↓

User FLASH Memory

24,064 Bytes

$FDFF

$FE00

$FE01

$FE02

$FE03

$FE04

$FE05

$FE06

$FE07

$FE08

$FE09

$FE0A

$FE0B

$FE0C

$FE0D

SIM Break Status Register (SBSR)

SIM Reset Status Register (SRSR)

Reserved (SUBAR)

SIM Break Flag Control Register (SBFCR)

Interrupt Status Register 1 (INT1)

Interrupt Status Register 2 (INT2)

Reserved (FL1TCR)

User FLASH Control Register (FL1CR)

Reserved (FL2TCR)

OSD FLASH Control Register (FL2CR)

OSD Output Control Register (OSDOCR)

OSD Enable Control Register (OSDECTR)

Break Address Register High (BRKH)

Break Address Register Low (BRKL)

Figure 2-1. Memory Map

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

43

Memory Map

$FE0E

$FE0F

$FE10

↓

Break Status and Control Register (BRKSCR)

LVI Status Register (LVISR)

Monitor ROM

240 Bytes

$FEFF

$FF00

↓

Unimplemented

128 Bytes

$FF7F

$FF80

$FF81

$FF82

↓

User FLASH Block Protect Register (FL1BPR)

OSD FLASH Block Protect Register (FL2BPR)

Reserved

104 Bytes

$FFE9

$FFEA

↓

FLASH Vectors

22 Bytes

$FFFF

Figure 2-1. Memory Map (Continued)

Advance Information

44

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

Memory Map

Input/Output (I/O) Section

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Port A Data Register

PTA7

PTA6

PTA5

PTA4

PTA3

PTA2

PTA1

PTA0

$0000

(PTA) Write:

See page 269.

Reset:

Read:

Unaffected by reset

PTB4 PTB3

Unaffected by reset

PTC4 PTC3

Port B Data Register

PTB7

0

PTB6

0

PTB5

0

PTB2

PTC2

PTB1

PTC1

PTB0

PTC0

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

(PTB) Write:

See page 272.

Reset:

Read:

Port C Data Register

(PTC) Write:

See page 274.

Reset:

Read:

Unaffected by reset

Unimplemented Write:

Reset:

Unaffected by reset

Read:

Data Direction Register A

DDRA7

0

DDRA6

0

DDRA5

0

DDRA4

0

DDRA3

0

DDRA2

0

DDRA1

DDRA0

(DDRA) Write:

See page 270.

Reset:

Read:

0

DDRB1

0

Data Direction Register B

DDRB7

DDRB6

DDRB5

DDRB4

0

DDRB3

0

DDRB2

0

DDRB0

(DDRB) Write:

See page 273.

Reset:

Read:

0

Data Direction Register C

DDRC4

DDRC3

DDRC2

DDRC1

0

DDRC0

(DDRC) Write:

See page 275.

Reset:

Read:

0

IRQF

IRQ Status and Control

IMASK

0

MODE

Register (INTSCR) Write:

ACK

0

See page 199.

Reset:

0

PLLIE

0

PLLON

1

0

Read:

PLLF

PLL Control Register

BCS

PRE1

PRE0

VPR1

VPR0

(PCTL) Write:

See page 114.

Reset:

0

R

0

Read:

LOCK

PLL Bandwidth Control

AUTO

0

ACQ

Register (PBWC) Write:

See page 117.

Reset:

0

= Unimplemented

R = Reserved U = Unaffected X = Indeterminate

Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 10)

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

45

Memory Map

Addr.

Register Name

Bit 7

6

5

4

3

MUL11

0

2

MUL10

0

1

MUL9

0

Bit 0

MUL8

0

Read:

0

PLL Multiplier Select High

$000A

Register (PMSH) Write:

See page 118.

Reset:

0

Read:

PLL Multiplier Select Low

MUL7

0

MUL6

1

MUL5

0

MUL4

0

MUL3

0

MUL2

0

MUL1

0

MUL0

0

$000B

$000C

Register (PMSL) Write:

See page 119.

Reset:

Read:

PLL VCO Select Range

VRS7

VRS6

VRS5

VRS4

VRS3

0

VRS2

0

VRS1

0

VRS0

0

Register (PMRS) Write:

See page 120.

Reset:

0

1

0

Read:

PLL Reference Divider

RDS3

0

RDS2

0

RDS1

0

RDS0

1

$000D Select Register (PMDS) Write:

See page 121.

Reset:

0

Read:

†

Configuration Register

(CONFIG) Write:

LVISTOP LVI5OR3 LVIRSTD LVIPWRD SSREC COPRS

STOP

0

COPD

0

$000E

$000F

$0010

$0011

See page 144.

Reset:

Read:

0

TOF

0

Timer Status and Control

TOIE

TSTOP

PS2

PS1

PS0

Register (TSC) Write:

TRST

0

See page 337.

Reset:

0

1

0

9

0

Read: Bit 15

14

13

12

11

10

Bit 8

Timer Counter Register

High (TCNTH) Write:

See page 340.

Reset:

Read:

0

6

0

5

0

4

0

3

0

2

0

1

0

Bit 7

Bit 0

Timer Counter Register

Low (TCNTL) Write:

See page 340.

Reset:

0

Bit 15

1

0

14

1

0

13

1

0

12

1

0

11

1

0

10

1

0

9

1

0

Bit 8

1

Read:

Timer Counter Modulo

$0012 Register High (TMODH) Write:

See page 341.

Reset:

Read:

Timer Counter Modulo

Bit 7

1

6

5

4

3

2

Bit 0

1

$0013

Register Low (TMODL) Write:

See page 341.

Reset:

1

† One-time writable register after each reset, except LVI5OR3 bit. The LVI5OR3 bit is only reset via POR (power-on reset).

= Unimplemented R = Reserved U = Unaffected X = Indeterminate

Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 10)

Advance Information

46

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

Memory Map

Input/Output (I/O) Section

Addr.

Register Name

Bit 7

6

CH0IE

0

5

MS0B

0

4

MS0A

0

3

ELS0B

0

2

ELS0A

0

1

TOV0

0

Bit 0

CH0MAX

0

Read: CH0F

Timer Channel 0 Status

$0014

and Control Register Write:

0

(TSC0) See page 342.

Reset:

Read:

Timer Channel 0

Bit 15

14

13

12

11

10

9

Bit 8

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

Register High (TCH0H) Write:

See page 346.

Reset:

Indeterminate after reset

Read:

Timer Channel 0

Bit 7

6

5

0

4

3

2

1

Bit 0

Register Low (TCH0L) Write:

See page 346.

Reset:

Indeterminate after reset

Read: CH1F

Timer Channel 1 Status

CH1IE

MS1A

0

ELS1B

ELS1A

TOV1

CH1MAX

and Control Register Write:

0

(TSC1) See page 342.

Reset:

0

9

0

Read:

Timer Channel 1

Bit 15

14

13

12

11

10

Bit 8

Register High (TCH1H) Write:

See page 346.

Reset:

Indeterminate after reset

Read:

Timer Channel 1

Bit 7

6

5

4

3

2

1

Bit 0

Register Low (TCH1L) Write:

See page 346.

Reset:

Indeterminate after reset

Read: TBIF

0

TBR0

Timebase Control

TBR2

TBR1

TBIE

0

TBON

0

R

0

Register (TBCR) Write:

TACK

See page 321.

Reset:

0

HD4

0

HD3

0

Read:

OSD Horizontal Delay

HD2

0

HD1

0

HD0

0

Register (OSDHDR) Write:

See page 252.

Reset:

0

CHHS

0

CHWS

0

RNDEN

0

Read:

OSD Foreground Control

BOEN

0

FGI

0

FGR

0

FGB

0

FGG

0

Register (OSDFCR) Write:

See page 252.

Reset:

Read:

OSD Background Control

BKHT

0

SHAD1

0

SHAD0

0

BKS

0

BKI

0

BKR

0

BKB

0

BKG

0

Register (OSDBKCR) Write:

See page 254.

Reset:

= Unimplemented

R = Reserved U = Unaffected X = Indeterminate

Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 10)

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

47

Memory Map

Addr.

Register Name

Bit 7

6

5

4

MS4

0

3

MS3

0

2

MS2

0

1

MS1

0

Bit 0

MS0

0

Read:

0

OSD Matrix Start Register

DMODE

BLINK

$001E

(OSDMSR) Write:

See page 263.

Reset:

0

Read:

OSD Matrix End Register

ME4

0

ME3

0

ME2

0

ME1

0

ME0

0

$001F

$0020

$0021

$0022

$0023

$0024

$0025

$0026

$0027

(OSDMER) Write:

See page 265.

Reset:

0

Read:

OSD Character 1

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

(OSDCHAR1) Write:

See page 245.

Reset:

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Read:

OSD Character 2

CH7

CH6

CH5

CH2

CH1

CH0

(OSDCHAR2) Write:

See page 245.

Reset:

Read:

OSD Character 3

(OSDCHAR3) Write:

See page 245.

Reset:

Read:

OSD Character 4

(OSDCHAR4) Write:

See page 245.

Reset:

Read:

OSD Character 5

(OSDCHAR5) Write:

See page 245.

Reset:

Read:

OSD Character 6

(OSDCHAR6) Write:

See page 245.

Reset:

Read:

OSD Character 7

(OSDCHAR7) Write:

See page 245.

Reset:

Read:

OSD Character 8

(OSDCHAR8) Write:

See page 245.

Reset:

Unaffected by reset

R = Reserved U = Unaffected X = Indeterminate

= Unimplemented

Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 10)

Advance Information

48

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

Memory Map

Input/Output (I/O) Section

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

OSD Character 9

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

$0028

(OSDCHAR9) Write:

See page 245.

Reset:

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Read:

OSD Character 10

CH7

CH6

CH5

CH2

CH1

CH0

$0029

$002A

$002B

$002C

$002D

$002E

$002F

$0030

$0031

(OSDCHAR10) Write:

See page 245.

Reset:

Read:

OSD Character 11

(OSDCHAR11) Write:

See page 245.

Reset:

Read:

OSD Character 12

(OSDCHAR12) Write:

See page 245.

Reset:

Read:

OSD Character 13

(OSDCHAR13) Write:

See page 245.

Reset:

Read:

OSD Character 14

(OSDCHAR14) Write:

See page 245.

Reset:

Read:

OSD Character 15

(OSDCHAR15) Write:

See page 245.

Reset:

Read:

OSD Character 16

(OSDCHAR16) Write:

See page 245.

Reset:

Read:

OSD Character 17

(OSDCHAR17) Write:

See page 245.

Reset:

Read:

OSD Character 18

(OSDCHAR18) Write:

See page 245.

Reset:

Unaffected by reset

R = Reserved U = Unaffected X = Indeterminate

= Unimplemented

Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 10)

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

49

Memory Map

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

OSD Character 19

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

$0032

(OSDCHAR19) Write:

See page 245.

Reset:

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Read:

OSD Character 20

CH7

CH6

CH5

CH2

CH1

CH0

$0033

$0034

$0035

$0036

$0037

$0038

$0039

$003A

$003B

(OSDCHAR20) Write:

See page 245.

Reset:

Read:

OSD Character 21

(OSDCHAR21) Write:

See page 245.

Reset:

Read:

OSD Character 22

(OSDCHAR22) Write:

See page 245.

Reset:

Read:

OSD Character 23

(OSDCHAR23) Write:

See page 245.

Reset:

Read:

OSD Character 24

(OSDCHAR24) Write:

See page 245.

Reset:

Read:

OSD Character 25

(OSDCHAR25) Write:

See page 245.

Reset:

Read:

OSD Character 26

(OSDCHAR26) Write:

See page 245.

Reset:

Read:

OSD Character 27

(OSDCHAR27) Write:

See page 245.

Reset:

Read:

OSD Character 28

(OSDCHAR28) Write:

See page 245.

Reset:

Unaffected by reset

R = Reserved U = Unaffected X = Indeterminate

= Unimplemented

Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 10)

Advance Information

50

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

Memory Map

Input/Output (I/O) Section

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

OSD Character 29

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

$003C

(OSDCHAR29) Write:

See page 245.

Reset:

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

CH4 CH3

Unaffected by reset

Read:

OSD Character 30

CH7

CH6

CH5

CH2

CH1

CH0

$003D

$003E

$003F

$0040

$0041

$0042

$0043

$0044

$0045

(OSDCHAR30) Write:

See page 245.

Reset:

Read:

OSD Character 31

(OSDCHAR31) Write:

See page 245.

Reset:

Read:

OSD Character 32

(OSDCHAR32) Write:

See page 245.

Reset:

Read:

OSD Character 33

(OSDCHAR33) Write:

See page 245.

Reset:

Read:

OSD Character 34

(OSDCHAR34) Write:

See page 245.

Reset:

Read:

0

OSD Vertical Delay

VD5

0

VD4

0

VD3

0

VD2

0

VD1

0

VD0

0

Register (OSDVDR) Write:

See page 251.

Reset:

Read:

OSD Border Control

BLINKEN BOHT

VMUTE

0

BOS

0

BOI

0

BOR

0

BOB

0

BOG

0

Register (OSDBCR) Write:

See page 255.

Reset:

0

Read:

OSD Event Line Register

EL7

EL6

EL5

EL4

EL3

EL2

EL1

EL0

(OSDELR) Write:

See page 259.

Reset:

0

Read:

EV7

EV6

EV5

EV4

EV3

EV2

EV1

EV0

OSD Event Count

Register (OSDECR) Write:

See page 260.

Reset:

Indeterminate after reset

R = Reserved U = Unaffected X = Indeterminate

= Unimplemented

Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 10)

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

51

Memory Map

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read: ELMF

VSINF

HSYN

VSYN

0

OSD Status Register

VCOTST DSLTST PLLTST

$0046

(OSDSR) Write:

See page 262.

Reset:

1

0

X

0

DSL Character Register 1 Read:

PE

DA6

DA5

DA4

DA3

DA2

DA1

DA0

(DSLCH1)

Write:

$0047

$0048

$0049

$004A

$004B

$004C

$004D

$004E

$004F

See page 135.

Reset:

0

X

Read:

PE

DA6

DA5

DA4

DA3

DA2

DA1

DA0

DSL Character Register 2

(DSLCH2) Write:

See page 135.

Reset:

0

DSIEN

0

X

DSEN

0

X

VVEN

0

X

LINE4

0

X

LINE3

0

X

LINE2

0

X

LINE1

0

X

DISCLP

0

Read:

DSL Control Register 1

(DSLCR1) Write:

See page 136.

Reset:

Read:

SYNCMP DATCMP BLKCMP

DSL Control Register 2

VR1

VR0

PW1

PW0

VPD

(DSLCR2) Write:

See page 138.

Reset:

0

Read: DSFL

OVFL

FIELD1

CSYNC

VPDET

RIC1

RIC0

DSL Status Register

(DSLSR) Write:

See page 141.

Reset:

Read:

0

X

0

SSI Control Register

SIE

SE

START

STOP

ACK

SCHS

SR1

SR0

(SSICR) Write:

See page 313.

Reset:

Read:

0

SF

DCOL

SSI Status Register

(SSISR) Write:

See page 315.

Reset:

Read:

0

DA7

0

DA6

0

DA3

0

DA2

0

DA1

0

DA0

0

SSI Data Register

DA5

DA4

(SSIDR) Write:

See page 316.

Reset:

0

Read: RESULT

ADC Control and Status

ADON

AD3

AD2

AD1

AD0

Register (ADCCSR) Write:

See page 84.

Reset:

0

= Unimplemented

R = Reserved U = Unaffected X = Indeterminate

Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 10)

Advance Information

52

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

Memory Map

Input/Output (I/O) Section

Addr.

Register Name

Bit 7

6

0

5

0

4

1

3

0

2

0

1

BW

Note

0

Bit 0

Read:

0

R

0

R

0

SIM Break Status Register

$FE00

(SBSR) Write:

See page 300.

R

0

R

0

R

1

R

0

R

0

Reset:

Note: Writing a logic 0 clears SBSW.

Read: POR

COP

ILOP

ILAD

0

LVI

0

SIM Reset Status Register

$FE01

$FE02

$FE03

$FE04

$FE05

$FE06

$FE07

$FE08

$FE09

(SRSR) Write:

See page 301.

POR:

Read:

Write:

Reset:

Read:

1

0

R

SIM Upper Byte Address

Register (SUBAR)

SIM Break Flag Control

BCFE

R

Register (SBFCR) Write:

See page 303.

Reset:

0

IF6

R

Read:

IF5

R

0

IF4

R

0

IF3

R

0

IF2

R

0

IF1

R

0

R

0

R

Interrupt Status Register 1

(INT1) Write:

See page 199.

Reset:

Read:

0

IF9

R

IF8

R

IF7

R

Interrupt Status Register 2

(INT2) Write:

R

0

R

0

R

0

R

0

See page 199.

Reset:

Read:

Write:

Reset:

Read:

0

R

0

R

0

R

0

User FLASH Test Control

Register (FL1TCR)

0

BLK1

0

BLK0

0

User FLASH Control

FDIV1

FDIV0

HVEN

MARGIN ERASE

PGM

0

Register (FL1CR) Write:

See page 173.

Reset:

0

R

0

R

0

Read:

R

OSD FLASH Test Control

Write:

Register (FL2TCR)

Reset:

0

FDIV1

0

FDIV0

0

HVEN

0

OSD FLASH Control Read:

BLK1

BLK0

MARGIN ERASE

PGM

Register (FL2CR)

Write:

See page 187.

Reset:

0

= Unimplemented

R = Reserved U = Unaffected X = Indeterminate

Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 10)

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

53

Memory Map

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

0

OSD Output Control

HINV

VINV

FDINV

CINV

FBINV

IINV

$FE0A

Register (OSDOCR) Write:

See page 260.

Reset:

0

OSDEN

0

SCAN

0

Read:

OSD Enable Control

ELIEN

VSIEN

XFER

PLLEN

MEM1

MEM0

$FE0B

$FE0C

$FE0D

$FE0E

$FE0F

$FF80

$FF81

Register (OSDECTR) Write:

See page 257.

Reset:

0

13

0

12

0

11

0

10

0

9

0

1

Read:

Break Address Register

Bit 15

0

14

Bit 8

0

High (BRKH) Write:

See page 93.

Reset:

0

Read:

Break Address Register

Bit 7

0

6

0

5

4

3

2

Bit 0

Low (BRKL) Write:

See page 93.

Reset:

0

Read:

Break Status and Control

BRKE

0

BRKA

Register (BRKSCR) Write:

See page 92.

Reset:

0

Read: LVIOUT

LVI Status Register

(LVISR) Write:

See page 205.

Reset:

Read:

0

BPR3

U

0

BPR2

U

0

BPR1

U

0

BPR0

U

User FLASH Block Protect

†

R

U

R

U

R

U

R

U

R

U

R

U

R

U

R

U

Register (FL1BPR) Write:

See page 182.

Reset:

Read:

OSD FLASH Block Protect

BPR3

U

BPR2

U

BPR1

U

BPR0

U

†

Register (FL2BPR) Write:

See page 193.

Reset:

Read:

Low byte of reset vector

COP Control Register

$FFFF

(COPCTL) Write:

Writing clears COP counter, any value

Unaffected by reset

See page 150.

Reset:

† Non-volatile FLASH register

= Unimplemented

R = Reserved U = Unaffected X = Indeterminate

Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 10)

Advance Information

54

MC68HC908TV24 — Rev. 2.1

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Input/Output (I/O) Section

Table 2-1. Vector Addresses

Vector Priority Vector Address

Lowest

Vector

SSI Vector (High)

$FFEA

$FFEB

$FFEC

$FFED

$FFEE

$FFEF

$FFF0

$FFF1

$FFF2

$FFF3

$FFF4

$FFF5

$FFF6

$FFF7

$FFF8

$FFF9

$FFFA

$FFFB

$FFFC

$FFFD

$FFFE

$FFFF

IF9

IF8

IF7

IF6

IF5

IF4

IF3

IF2

IF1

—

SSI Vector (Low)

DSL Vector (High)

DSL Vector (Low)

OSD Vector (High)

OSD Vector (Low)

TIM Overflow Vector (High)

TIM Overflow Vector (Low)

TIM Channel 1 Vector (High)

TIM Channel 1 Vector (Low)

TIM Channel 0 Vector (High)

TIM Channel 0 Vector (Low)

Timebase Vector (High)

Timebase Vector (Low)

PLL Vector (High)

PLL Vector (Low)

IRQ Vector (High)

IRQ Vector (Low)

SWI Vector (High)

SWI Vector (Low)

Reset Vector (High)

Reset Vector (Low)

—

Highest

MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

AdvanceInformation

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Memory Map

Advance Information

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MC68HC908TV24 — Rev. 2.1

Freescale Semiconductor

Memory Map

Advance Information — MC68HC908TV24

Section 3. Low-Power Modes

3.1 Contents