MC68HC705P6ACDW [FREESCALE]
Microcontrollers; 微控制器
| 型号： | MC68HC705P6ACDW |
| 厂家： | 
Freescale |
| 描述： | Microcontrollers |
| 文件： | 总98页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC705P6A
Advance Information Data Sheet
M68HC05
Microcontrollers
MC68HC705P6A
Rev. 2.1
9/2005
freescale.com
This document contains certain information on a new product.Specifications and information herein are subject to change without notice.
Blank
MC68HC705P6A
Advance Information Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com/
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Revision
Level
Page
Number(s)
Date
Description
Format update to current publication standards
N/A
November,
2001
2.0
2.1
Figure 11-1. Mask Option Register (MOR) — Definition of bit 6
corrected.
92
September,
2005
Updated to meet Freescale identity guidelines.
Throughout
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
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Revision History
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
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List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Chapter 3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Chapter 4 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Chapter 5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Chapter 6 Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Chapter 7 Serial Input/Output Port (SIOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Chapter 8 Capture/Compare Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Chapter 9 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Chapter 10 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Chapter 11 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Chapter 12 Central Processor Unit (CPU) Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Chapter 13 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Chapter 14 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Chapter 15 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Chapter 16 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
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List of Chapters
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Table of Contents
Chapter 1
General Description
1.1
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.1
1.3.2
1.3.2.1
1.3.2.2
1.3.2.3
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.3.9
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ceramic Resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PB5/SDO, PB6/SDI, and PB7/SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH. . . . . . . . . . . . . . . . 16
PD5 and PD7/TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TCMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IRQ/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2
Memory
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bootloader Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Computer Operating Properly (COP) Clear Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 3
Operating Modes
3.1
3.2
3.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
WAIT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.1
3.4.1.1
3.4.1.2
3.4.2
3.5
COP Watchdog Timer Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Table of Contents
Chapter 4
Resets
4.1
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
External Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3
4.3.1
4.3.2
Internal Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chapter 5
Interrupts
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2
5.2.1
5.2.2
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3
5.2.3.4
Interrupt Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Output Compare Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Timer Overflow Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Chapter 6
Input/Output Ports
6.1
6.2
6.3
6.4
6.5
6.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I/O Port Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 7
Serial Input/Output Port (SIOP)
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2
SIOP Signal Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Serial Data Input (SDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.1
7.2.2
7.2.3
7.3
SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SIOP Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SIOP Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.1
7.3.2
7.3.3
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Table of Contents
Chapter 8
Capture/Compare Timer
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2
8.2.1
8.2.2
Timer Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.3
Timer I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Timer Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Alternate Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.4
8.5
Timer During Wait/Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Timer During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 9
Analog Subsystem
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2
Analog Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Reference Voltage (VREFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2.1
9.2.2
9.2.3
9.3
Conversion Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.4
Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4.1
9.4.2
9.4.3
9.5
9.6
9.7
9.8
A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
A/D Conversion Data Register (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A/D Subsystem Operation during Halt/Wait Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
A/D Subsystem Operation during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Chapter 10
EPROM
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.2 EPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3 EPROM Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.4 EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.5 EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.6 EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.7 Programming from an External Memory Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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Table of Contents
Chapter 11
Mask Option Register (MOR)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.2 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.3 MOR Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 12
Central Processor Unit (CPU) Core
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Chapter 13
Instruction Set
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.2.8
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.3 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
13.4 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
13.5 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Chapter 14
Electrical Specifications
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.3 Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.5 5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.6 3.3-Volt DC Electrical Charactertistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
14.7 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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Table of Contents
14.8 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14.9 SIOP Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.10 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Chapter 15
Mechanical Specifications
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
15.2 Plastic Dual In-Line Package (Case 710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
15.3 Small Outline Integrated Circuit Package (Case 751F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Chapter 16
Ordering Information
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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Table of Contents
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
12
Freescale Semiconductor
Chapter 1
General Description
1.1 Introduction
The MC68HC705P6A is an EPROM version of the MC68HC05P6 microcontroller. It is a low-cost
combination of an M68HC05 Family microprocessor with a 4-channel, 8-bit analog-to-digital (A/D)
converter, a 16-bit timer with output compare and input capture, a serial communications port (SIOP), and
a computer operating properly (COP) watchdog timer. The M68HC05 CPU core contains 176 bytes of
RAM, 4672 bytes of user EPROM, 239 bytes of bootloader ROM, and 21 input/output (I/O) pins (20
bidirectional, 1 input-only). This device is available in either a 28-pin plastic dual in-line (PDIP) or a 28-pin
small outline integrated circuit (SOIC) package.
A functional block diagram of the MC68HC705P6A is shown in Figure 1-1.
1.2 Features
Features of the MC68HC705P6A include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low cost
M68HC05 core
28-pin SOIC, PDIP, or windowed DIP package
4672 bytes of user EPROM (including 48 bytes of page zero EPROM and 16 bytes of user vectors)
239 bytes of bootloader ROM
176 bytes of on-chip RAM
4-channel 8-bit A/D converter
SIOP serial communications port
16-bit timer with output compare and input capture
20 bidirectional I/O lines and 1 input-only line
PC0 and PC1 high-current outputs
Single-chip, bootloader, and test modes
Power-saving stop, halt, and wait modes
Static EPROM mask option register (MOR) selectable options:
–
–
–
–
–
–
–
COP watchdog timer enable or disable
Edge-sensitive or edge- and level-sensitive external interrupt
SIOP most significant bit (MSB) or least significant bit (LSB) first
SIOP clock rates: OSC divided by 8, 16, 32, or 64
Stop instruction mode, STOP or HALT
EPROM security external lockout
Programmable keyscan (pullups/interrupts) on PA0–PA7
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
13
General Description
INTERNAL
CPU CLOCK
COP
OSC 1
OSC 2
÷2
OSC
16-BIT TIMER
PD7/TCAP
TCMP
÷4
CPU CONTROL
M68HC05 CPU
ALU
1 INPUT CAPTURE
1 OUTPUT COMPARE
PORT D LOGIC
RESET
PD5
IRQ/VPP
ACCUM
CPU REGISTERS
PC7/VREFH
PC6/AD0
PC5/AD1
PC4/AD2
PC3/AD3
PC2
INDEX REG
0 0 0 0 0 0 0 0 1 1 STK PNTR
PROGRAM COUNTER
COND CODE REG
1 1 1 H I N Z C
PC1
PC0
SRAM — 176 BYTES
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
USER EPROM — 4672 BYTES
BOOTLOADER ROM — 239 BYTES
PORT B AND
SIOP
PB5/SDO
PB6/SDI
PB7/SCK
REGISTERS
AND LOGIC
VDD
VSS
Figure 1-1. MC68HC705P6A Block Diagram
NOTE
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
Any reference to voltage, current, or frequency specified in the following
sections will refer to the nominal values. The exact values and their
tolerances or limits are specified in Chapter 14 Electrical Specifications.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
14
Freescale Semiconductor
Functional Pin Description
1.3 Functional Pin Description
The following paragraphs describe the functionality of each pin on the MC68HC705P6A package. Pins
connected to subsystems described in other chapters provide a reference to the chapter instead of a
detailed functional description.
1.3.1 V and V
DD
SS
Power is supplied to the MCU through VDD and VSS. VDD is connected to a regulated +5 volt supply and
VSS is connected to ground.
Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high
short-duration current demands on the power supply. To prevent noise problems, take special care to
provide good power supply bypassing at the MCU. Use bypass capacitors with good high-frequency
characteristics and position them as close to the MCU as possible. Bypassing requirements vary,
depending on how heavily the MCU pins are loaded.
1.3.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the on-chip oscillator. The OSC1 and OSC2
pins can accept the following:
1. A crystal as shown in Figure 1-2(a)
2. A ceramic resonator as shown in Figure 1-2(a)
3. An external clock signal as shown in Figure 1-2(b)
The frequency, fosc, of the oscillator or external clock source is divided by two to produce the internal bus
clock operating frequency, fop. The oscillator cannot be turned off by software unless the MOR bit, SWAIT,
is clear when a STOP instruction is executed.
To VDD (or STOP)
MCU
To VDD (or STOP)
MCU
OSC1
OSC2
OSC1
OSC2
4.7 MΩ
UNCONNECTED
EXTERNAL CLOCK
37 pF
37 pF
(a) Crystal or Ceramic
Resonator Connections
(b) External Clock Source
Connections
Figure 1-2. Oscillator Connections
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
15
General Description
1.3.2.1 Crystal
The circuit in Figure 1-2(a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. Follow
the crystal manufacturer’s recommendations, as the crystal parameters determine the external
component values required to provide maximum stability and reliable startup. The load capacitance
values used in the oscillator circuit design should include all stray capacitances. Mount the crystal and
components as close as possible to the pins for startup stabilization and to minimize output distortion.
1.3.2.2 Ceramic Resonator
In cost-sensitive applications, use a ceramic resonator in place of a crystal. Use the circuit in Figure 1-2(a)
for a ceramic resonator and follow the resonator manufacturer’s recommendations, as the resonator
parameters determine the external component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as close as possible to the pins for startup stabilization and to
minimize output distortion.
1.3.2.3 External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the
OSC2 input not connected, as shown in Figure 1-2(b).
1.3.3 RESET
Driving this input low will reset the MCU to a known startup state. The RESET pin contains an internal
Schmitt trigger to improve its noise immunity. Refer to Chapter 4 Resets.
1.3.4 PA0–PA7
These eight I/O pins comprise port A. The state of any pin is software programmable and all port A lines
are configured as inputs during power-on or reset. Port A has mask-option register enabled interrupt
capability with internal pullup devices selectable for any pin. Refer to Chapter 6 Input/Output Ports.
1.3.5 PB5/SDO, PB6/SDI, and PB7/SCK
These three I/O pins comprise port B and are shared with the SIOP communications subsystem. The
state of any pin is software programmable, and all port B lines are configured as inputs during power-on
or reset. Refer to Chapter 6 Input/Output Ports and Chapter 7 Serial Input/Output Port (SIOP).
1.3.6 PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/V
REFH
These eight I/O pins comprise port C and are shared with the A/D converter subsystem. The state of any
pin is software programmable and all port C lines are configured as inputs during power-on or reset. Refer
to Chapter 6 Input/Output Ports and Chapter 9 Analog Subsystem.
1.3.7 PD5 and PD7/TCAP
These two I/O pins comprise port D and one of them is shared with the 16-bit timer subsystem. The state
of PD5 is software programmable and is configured as an input during power-on or reset. PD7 is always
an input. It may be read at any time, regardless of which mode of operation the 16-bit timer is in. Refer to
Chapter 6 Input/Output Ports and Chapter 8 Capture/Compare Timer.
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Freescale Semiconductor
Functional Pin Description
1.3.8 TCMP
This pin is the output from the 16-bit timer’s output compare function. It is low after reset. Refer to
Chapter 8 Capture/Compare Timer.
1.3.9 IRQ/V (Maskable Interrupt Request)
PP
This input pin drives the asynchronous interrupt function of the MCU in user mode and provides the VPP
programming voltage in bootloader mode. The MCU will complete the current instruction being executed
before it responds to the IRQ interrupt request. When the IRQ/VPP pin is driven low, the event is latched
internally to signify an interrupt has been requested. When the MCU completes its current instruction, the
interrupt latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU will begin the interrupt sequence.
Depending on the MOR LEVEL bit, the IRQ/VPP pin will trigger an interrupt on either a negative edge at
the IRQ/VPP pin and/or while the IRQ/VPP pin is held in the low state. In either case, the IRQ/VPP pin must
be held low for at least one tILIH time period. If the edge- and level-sensitive mode is selected (LEVEL bit
set), the IRQ/VPP input pin requires an external resistor connected to VDD for wired-OR operation. If the
IRQ/VPP pin is not used, it must be tied to the VDD supply. The IRQ/VPP pin input circuitry contains an
internal Schmitt trigger to improve noise immunity. Refer to Chapter 5 Interrupts.
NOTE
If the voltage level applied to the IRQ/VPP pin exceeds VDD, it may affect
the MCU’s mode of operation. See Chapter 3 Operating Modes.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
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General Description
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
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Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
The MC68HC705P6A utilizes 13 address lines to access an internal memory space covering 8 Kbytes.
This memory space is divided into I/O, RAM, ROM, and EPROM areas.
2.2 User Mode Memory Map
When the MC68HC705P6A is in the user mode, the 32 bytes of I/O, 176 bytes of RAM, 4608 bytes of user
EPROM, 48 bytes of user page zero EPROM, 239 bytes of bootloader ROM, and 16 bytes of user vectors
EPROM are all active as shown in Figure 2-1.
2.3 Bootloader Mode Memory Map
Memory space is identical to the user mode. See Figure 2-1.
2.4 Input/Output and Control Registers
Figure 2-2 and Figure 2-3 briefly describe the I/O and control registers at locations $0000–$001F.
Reading unimplemented bits will return unknown states, and writing unimplemented bits will be ignored.
2.5 RAM
The user RAM consists of 176 bytes (including the stack) at locations $0050 through $00FF. The stack
begins at address $00FF. The stack pointer can access 64 bytes of RAM from $00FF to $00C0.
NOTE
Using the stack area for data storage or temporary work locations requires
care to prevent it from being overwritten due to stacking from an interrupt
or subroutine call.
2.6 EPROM/ROM
There are 4608 bytes of user EPROM at locations $0100 through $12FF, plus 48 bytes in user page zero
locations $0020 through $004F, and 16 additional bytes for user vectors at locations $1FF0 through
$1FFF. The bootloader ROM and vectors are at locations $1F01 through $1FEF.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
19
Memory
$0000
0000
$0000
I/O
32 BYTES
$001F
$0020
0031
0032
USER EPROM
48 BYTES
I/O REGISTERS
SEE Figure 2-2
$004F
$0050
0079
0080
INTERNAL RAM
176 BYTES
$00BF
$00C0
0191
0192
$001F
STACK
64 BYTES
$00FF
$0100
0255
0256
USER EPROM
COP CLEAR REGISTER(1)
UNUSED
$1FF0
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
4608 BYTES
UNUSED
UNUSED
$12FF
$1300
4863
4864
UNUSED
UNIMPLEMENTED
3071 BYTES
UNUSED
UNUSED
$1EFE
$1EFF
$1F00
$1F01
7934
7935
7936
7937
UNUSED
MASK OPTION REGISTERS
TIMER VECTOR (HIGH BYTE)
TIMER VECTOR (LOW BYTE)
IRQ VECTOR (HIGH BYTE)
IRQ VECTOR (LOW BYTE)
SWI VECTOR (HIGH BYTE)
SWI VECTOR (LOW BYTE)
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
BOOTLOADER ROM
AND VECTORS 239 BYTES
$1FEF
$1FF0
8175
8176
USER VECTORS EPROM
16 BYTES
$1FFF
8191
Note 1. Writing zero to bit 0 of $1FF0 clears the COP watchdog timer. Reading $1FF0 returns user EPROM data.
Figure 2-1. MC68HC705P6A User Mode Memory Map
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
20
Freescale Semiconductor
EPROM/ROM
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
PORT D DATA REGISTER
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
PORT D DATA DIRECTION REGISTER
UNIMPLEMENTED
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0015
$0016
$0017
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
UMIMPLEMENTED
SIOP CONTROL REGISTER
SIOP STATUS REGISTER
SIOP DATA REGISTER
RESERVED
UNIMPLEMENTED
UNIMPLEMENTED
UNIMPLEMENTED
UNIMPLEMENTED
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE MSB
INPUT CAPTURE LSB
OUTPUT COMPARE MSB
OUTPUT COMPARE LSB
TIMER MSB
TIMER LSB
ALTERNATE COUNTER MSB
ALTERNATE COUNTER LSB
EPROM PROGRAMMING REGISTER
A/D CONVERTER DATA REGISTER
A/D CONVERTER CONTROL AND STATUS REGISTER
RESERVED
Figure 2-2. MC68HC705P6A I/O and Control
Registers Memory Map
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
21
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Port A Data Register
(PORTA)
See page 37.
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
$0000
Unaffected by reset
0
0
0
0
0
Port B Data Register
(PORTB)
See page 38.
PB7
PB6
PB5
PC5
PD5
$0001
$0002
$0003
$0004
$0005
$0006
Unaffected by reset
PC4 PC3
Unaffected by reset
Port C Data Register
(PORTC)
See page 38.
PC7
PD7
PC6
0
PC2
0
PC1
0
PC0
0
1
0
Port D Data Register
(PORTD)
See page 39.
Unaffected by reset
Port A Data Direction
Register (DDRA)
See page 37.
DDRA7
0
DDRA6
0
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
1
0
1
0
1
0
1
0
1
Port B Data Direction
Register (DDRB)
See page 38.
DDRB7
0
DDRB6
0
DDRB5
0
DDRC5
0
0
0
0
0
0
Port C Data Direction
DDRC7
DDRC6
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
Register (DDRC) Write:
See page 38.
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Port D Data Direction
Register (DDRD) Write:
DDRD5
0
$0007
$0008
$0009
See page 39.
Reset:
0
0
0
0
0
0
0
Unimplemented
Unimplemented
Read:
0
0
0
0
0
0
SIOP Control Register
(SCR)
See page 43.
SPE
MSTR
$000A
$000B
$000C
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPIF
DCOL
SIOP Status Register
(SSR)
See page 44.
0
0
0
0
0
0
0
0
SIOP Data Register
(SDR)
See page 44.
SDR7
SDR6
SDR5
SDR4
SDR3
SSDR2
SDR1
SDR0
Unaffected by reset
= Reserved
= Unimplemented
R
U = Undetermined
Figure 2-3. I/O and Control Register Summary (Sheet 1 of 3)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
22
Freescale Semiconductor
EPROM/ROM
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$000D
Reserved for Test
R
R
R
R
R
R
R
R
$000E
$000F
$0010
$0011
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
Timer Control Register
(TCR)
See page 47.
ICIE
OCIE
TOIE
IEDG
OLVL
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
0
0
0
0
0
0
0
0
0
U
0
0
0
ICF
OCF
TOF
Timer Status Register
(TSR)
See page 48.
U
U
U
0
0
0
0
0
Read: ICRH7
Write:
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
Input Capture Register
MSB (ICRH)
See page 50.
Reset:
Unaffected by reset
ICRL4 ICRL3
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
ICRL7
ICRL6
ICRL5
ICRL2
ICRL1
ICRL0
Input Capture Register
LSB (ICRL)
See page 50.
Unaffected by reset
OCRH4 OCRH3
Unaffected by reset
OCRL4 OCRL3
Unaffected by reset
Output Compare
Register MSB (OCRH)
See page 50.
OCRH7
OCRH6
OCRH5
OCRH2
OCRH1
OCRH0
Output Compare
Register LSB (OCRL)
See page 50.
OCRL7
TRH7
OCRL6
TRH6
OCRL5
TRH5
OCRL2
TRH2
OCRL1
TRH1
OCRL0
TRH0
TRH4
TRH3
Timer Register MSB
(TRH)
See page 49.
1
1
1
1
1
1
1
1
TRL7
TRL6
TRL5
TRL4
TRL3
TRL2
TRL1
TRL0
Timer Register LSB (TRL)
See page 49.
1
1
1
1
1
1
0
0
Read: ACRH7
Write:
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
Alternate Timer
Register MSB (ATRH)
See page 49.
Reset:
1
1
1
1
1
1
1
1
= Unimplemented
R
= Reserved
U = Undetermined
Figure 2-3. I/O and Control Register Summary (Sheet 2 of 3)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
23
Memory
Addr.
Register Name
Bit 7
Read: ACRL7
Write:
6
5
4
3
2
1
Bit 0
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
Alternate Timer
Register LSB (ATRL)
See page 49.
$001B
$001C
$001D
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
1
0
1
0
1
0
1
0
1
0
1
0
0
0
EPROM Programming
Register (EPROG)
See page 58.
ELAT
EPGM
0
0
0
0
0
0
0
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
A/D Conversion Value
Data Register (ADC)
See page 55.
Unaffected by reset
CC
0
0
A/D Status and Control
Register (ADSC)
See page 54.
ADRC
ADON
CH2
CH1
CH0
$001E
$001F
0
0
0
0
0
0
0
0
Reserved for Test
R
R
R
R
R
R
R
R
= Unimplemented
R
= Reserved
U = Undetermined
Figure 2-3. I/O and Control Register Summary (Sheet 3 of 3)
2.7 Mask Option Register
The mask option register (MOR) is a pair of EPROM bytes located at $1EFF and $1F00. It controls the
programmable options on the MC68HC705P6A. See Chapter 11 Mask Option Register (MOR) for
additional information.
$1EFF
Read:
Bit 7
PA7PU
0
6
PA6PU
0
5
PA5PU
0
4
PA4PU
0
3
PA3PU
0
2
PA2PU
0
1
PA1PU
0
Bit 0
PA0PU
0
Write:
Erased State:
$1F00
Read:
Bit 7
SECURE
0
6
5
SWAIT
0
4
SPR1
0
3
SPR0
0
2
LSBF
0
1
LEVEL
0
Bit 0
COP
0
Write:
Erased State:
0
= Unimplemented
Figure 2-4. Mask Option Register (MOR)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
24
Freescale Semiconductor
Computer Operating Properly (COP) Clear Register
2.8 Computer Operating Properly (COP) Clear Register
The computer operating properly (COP) watchdog timer is located at address $1FF0. Writing a logical 0
to bit zero of this location will clear the COP watchdog counter as described in 4.3.2 Computer Operating
Properly (COP) Reset.
$1FF0
Read:
Write:
Reset:
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
COPR
0
0
0
0
0
0
0
0
= Unimplemented
Figure 2-5. COP Watchdog Timer Location
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
25
Memory
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
26
Freescale Semiconductor
Chapter 3
Operating Modes
3.1 Introduction
The MC68HC705P6A has two modes of operation that affect the pinout and architecture of the MCU:
user mode and bootloader mode. The user mode is normally used for the application and the bootloader
mode is used for programming the EPROM. The conditions required to enter each mode are shown in
Table 3-1. The mode of operation is determined by the voltages on the IRQ/VPP and PD7/TCAP pins on
the rising edge of the external RESET pin.
Table 3-1. Operating Mode Conditions After Reset
IRQ/VPP
RESET Pin
PD7/TCAP
Mode
VSS to VDD
VSS to VDD
Single chip
VPP
VDD
Bootloader
The mode of operation is also determined whenever the internal computer operating properly (COP)
watchdog timer resets the MCU. When the COP timer expires, the voltage applied to the IRQ/VPP pin
controls the mode of operation while the voltage applied to PD7/TCAP is ignored. The voltage applied to
PD7/TCAP during the last rising edge on RESET is stored in a latch and used to determine the mode of
operation when the COP watchdog timer resets the MCU.
3.2 User Mode
The user mode allows the MCU to function as a self-contained microcontroller, with maximum use of the
pins for on-chip peripheral functions. All address and data activity occurs within the MCU and are not
available externally. User mode is entered on the rising edge of RESET if the IRQ/VPP pin is within the
normal operating voltage range. The pinout for the user mode is shown in Figure 3-1.
In the user mode, there is an 8-bit I/O port, a second 8-bit I/O port shared with the analog-to-digital (A/D)
subsystem, one 3-bit I/O port shared with the serial input/output port (SIOP), and a 3-bit port shared with
the 16-bit timer subsystem, which includes one general-purpose I/O pin.
3.3 Bootloader Mode
The bootloader mode provides a means to program the user EPROM from an external memory device or
host computer. This mode is entered on the rising edge of RESET if VPP is applied to the IRQ/VPP pin and
VDD is applied to the PD7/TCAP pin. The user code in the external memory device must have data located
in the same address space it will occupy in the internal MCU EPROM, including the mask option register
(MOR) at $1EFF and $1F00.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
27
Operating Modes
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RESET
IRQ/VPP
PA7
1
VDD
2
OSC1
3
OSC2
PA6
4
PD7/TCAP
TCMP
PA5
5
PA4
6
PD5
PA3
7
PC0
PA2
8
PC1
PA1
9
PC2
PA0
10
11
12
13
14
PC3/AD3
PC4/AD2
PC5/AD1
PC6/AD0
PC7/VREFH
SDO/PB5
SDI/PB6
SCK/PB7
VSS
Figure 3-1. User Mode Pinout
3.4 Low-Power Modes
The MC68HC705P6A is capable of running in a low-power mode in each of its configurations. The WAIT
and STOP instructions provide three modes that reduce the power required for the MCU by stopping
various internal clocks and/or the on-chip oscillator. The SWAIT bit in the MOR is used to modify the
behavior of the STOP instruction from stop mode to halt mode. The flow of the stop, halt, and wait modes
is shown in Figure 3-2.
3.4.1 STOP Instruction
The STOP instruction can result in one of two modes of operation depending on the state of the SWAIT
bit in the MOR. If the SWAIT bit is clear, the STOP instruction will behave like a normal STOP instruction
in the M68HC05 Family and place the MCU in stop mode. If the SWAIT bit in the MOR is set, the STOP
instruction will behave like a WAIT instruction (with the exception of a brief delay at startup) and place the
MCU in halt mode.
3.4.1.1 Stop Mode
Execution of the STOP instruction when the SWAIT bit in the MOR is clear places the MCU in its lowest
power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing,
including the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the
condition code register so that the IRQ external interrupt is enabled. All other registers and memory
remain unaltered. All input/output lines remain unchanged.
The MCU can be brought out of stop mode only by an IRQ external interrupt or an externally generated
RESET. When exiting stop mode, the internal oscillator will resume after a 4064 internal clock cycle
oscillator stabilization delay.
NOTE
Execution of the STOP instruction when the SWAIT bit in the MOR is clear
will cause the oscillator to stop, and, therefore, disable the COP watchdog
timer. To avoid turning off the COP watchdog timer, stop mode should be
changed to halt mode by setting the SWAIT bit in the MOR. See 3.5 COP
Watchdog Timer Considerations for additional information.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
28
Freescale Semiconductor
Low-Power Modes
STOP
HALT
WAIT
EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
MOR
SWAIT
Y
BIT SET?
N
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET STARTUP DELAY
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
EXTERNAL
RESET?
Y
Y
Y
Y
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
N
IRQ
EXTERNAL
INTERRUPT?
Y
EXTERNAL
RESET?
Y
EXTERNAL
RESET?
N
N
N
IRQ
IRQ
EXTERNAL
Y
TIMER
EXTERNAL
INTERRUPT?
Y
INTERNAL
INTERRUPT?
INTERRUPT?
N
RESTART EXTERNAL OSCILLATOR,
N
N
START STABILIZATION DELAY
TIMER
Y
COP
INTERNAL
INTERRUPT?
INTERNAL
RESET?
N
END
N
Y
OF STABILIZATION
DELAY?
COP
Y
INTERNAL
RESET?
N
RESTART
N
INTERNAL PROCESSOR CLOCK
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT ROUTINE
Figure 3-2. STOP/WAIT Flowcharts
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
29
Operating Modes
3.4.1.2 Halt Mode
NOTE
Halt mode is NOT designed for intentional use. Halt mode is only provided
to keep the COP watchdog timer active in the event a STOP instruction is
executed inadvertently. This mode of operation is usually achieved by
invoking wait mode.
Execution of the STOP instruction when the SWAIT bit in the MOR is set places the MCU in this low-power
mode. Halt mode consumes the same amount of power as wait mode (both halt and wait modes consume
more power than stop mode).
In halt mode, the internal clock is halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-bit timer or a reset to be generated
from the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other registers, memory, and input/output
lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit the halt mode and resume normal
operation. The halt mode also can be exited when an IRQ external interrupt or external RESET occurs.
When exiting the halt mode, the internal clock will resume after a delay of one to 4064 internal clock
cycles. This varied delay time is the result of the halt mode exit circuitry testing the oscillator stabilization
delay timer (a feature of the stop mode), which has been free-running (a feature of the wait mode).
3.4.2 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode which consumes more power than stop mode.
In wait mode, the internal clock is halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-bit timer and reset to be generated
from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other registers, memory, and input/output
lines remain in their previous state.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit wait mode and resume normal
operation. The 16-bit timer may be used to generate a periodic exit from wait mode. Wait mode may also
be exited when an IRQ external interrupt or RESET occurs.
3.5 COP Watchdog Timer Considerations
The COP watchdog timer is active in user mode of operation when the COP bit in the MOR is set.
Executing the STOP instruction when the SWAIT bit in the MOR is clear will cause the COP to be
disabled. Therefore, it is recommended that the STOP instruction be modified to produce halt mode (set
bit SWAIT in the MOR) if the COP watchdog timer is required to function at all times.
Furthermore, it is recommended that the COP watchdog timer be disabled for applications that will use
the wait mode for time periods that will exceed the COP timeout period.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
30
Freescale Semiconductor
Chapter 4
Resets
4.1 Introduction
The MCU can be reset from three sources: one external input and two internal reset conditions. The
RESET pin is a Schmitt trigger input as shown in Figure 4-1. The CPU and all peripheral modules will be
reset by the RST signal which is the logical OR of internal reset functions and is clocked by PH1.
RESET
POWER-ON
RESET
(POR)
D
VDD
RST
TO CPU AND
RES
PERIPHERALS
DFF
OSC
DATA
COP
WATCHDOG
(COPR)
PH1
ADDRESS
Figure 4-1. Reset Block Diagram
4.2 External Reset (RESET)
The RESET input is the only external reset and is connected to an internal Schmitt trigger. The external
reset occurs whenever the RESET input is driven below the lower threshold and remains in reset until the
RESET pin rises above the upper threshold. The upper and lower thresholds are given in Chapter 14
Electrical Specifications.
4.3 Internal Resets
The two internally generated resets are the initial power-on reset (POR) function and the computer
operating properly (COP) watchdog timer function.
4.3.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator to stabilize. The POR is strictly for
power turn-on conditions and should not be used to detect a drop in the power supply voltage. There is a
4064 internal clock cycle oscillator stabilization delay after the oscillator becomes active.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
31
Resets
The POR will generate the RST signal and reset the MCU. If any other reset function is active at the end
of this 4064 internal clock cycle delay, the RST signal will remain active until the other reset condition(s)
end.
4.3.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (COP bit in the MOR is set), the internal COP reset is
generated automatically by a timeout of the COP watchdog timer. This timer is implemented with an
18-stage ripple counter that provides a timeout period of 65.5 ms when a 4-MHz oscillator is used. The
COP watchdog counter is cleared by writing a logical 0 to bit zero at location $1FF0.
The COP watchdog timer can be disabled by clearing the COP bit in the MOR or by applying 2 x VDD to
the IRQ/VPP pin (for example, during bootloader). When the IRQ/VPP pin is returned to its normal
operating voltage range (between VSS–VDD), the COP watchdog timer’s output will be restored if the COP
bit in the mask option register (MOR) is set.
The COP register is shared with the least significant byte (LSB) of an unused vector address as shown
in Figure 4-2. Reading this location will return the programmed value of the unused user interrupt vector,
usually 0. Writing to this location will clear the COP watchdog timer.
Address:
$1FF0
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
COPR
= Unimplemented
Figure 4-2. Unused Vector and COP Watchdog Timer
When the COP watchdog timer expires, it will generate the RST signal and reset the MCU. If any other
reset function is active at the end of the COP reset signal, the RST signal will remain in the reset condition
until the other reset condition(s) end. When the reset condition ends, the MCU’s operating mode will be
selected (see Table 3-1. Operating Mode Conditions After Reset).
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
32
Freescale Semiconductor
Chapter 5
Interrupts
5.1 Introduction
The MCU can be interrupted six different ways:
1. Non-maskable software interrupt instruction (SWI)
2. External asynchronous interrupt (IRQ)
3. Input capture interrupt (TIMER)
4. Output compare interrupt (TIMER)
5. Timer overflow interrupt (TIMER)
6. Port A interrupt (if selected via mask option register)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I
bit) to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current instruction is completed.
When the current instruction is completed, the processor checks all pending hardware interrupts. If
interrupts are not masked (I bit in the condition code register is clear) and the corresponding interrupt
enable bit is set, the processor proceeds with interrupt processing. Otherwise, the next instruction is
fetched and executed. The SWI is executed the same as any other instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU puts the register contents on the stack, sets the I bit in the
CCR, and fetches the address of the corresponding interrupt service routine from the vector table at
locations $1FF8 through $1FFF. If more than one interrupt is pending when the interrupt vector is fetched,
the interrupt with the highest vector location shown in Table 5-1 will be serviced first.
Table 5-1. Vector Addresses for Interrupts and Reset
Flag
Name
CPU
Interrupt
Vector
Address
Register
Interrupts
N/A
N/A
N/A
N/A
N/A
ICF
Reset
RESET
SWI
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF8–$1FF9
$1FF8–$1FF9
Software
N/A
External Interrupt
Timer Input Capture
Timer Output Compare
Timer Overflow
IRQ
TSR
TSR
TSR
TIMER
TIMER
TIMER
OCF
TOF
An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI
instruction causes the CPU state to be recovered from the stack and normal processing to resume at the
next instruction that was to be executed when the interrupt took place. Figure 5-1 shows the sequence of
events that occurs during interrupt processing.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
33
Interrupts
FROM RESET
IS I BIT
SET?
Y
N
CLEAR IRQ
REQUEST
LATCH
IRQ
Y
Y
INTERRUPT?
N
TIMER
INTERRUPT?
N
STACK
PC, X, A, CC
SET
I BIT IN CCR
LOAD PC FROM:
SWI: $1FFC, $1FFD
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9
FETCH NEXT
INSTRUCTION
SWI
Y
Y
INSTRUCTION?
N
RESTORE RESISTERS
FROM STACK
RTI
INSTRUCTION?
CC, A, X, PC
N
EXECUTE INSTRUCTION
Figure 5-1. Interrupt Processing Flowchart
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
34
Freescale Semiconductor
Interrupt Types
5.2 Interrupt Types
The interrupts fall into three categories: reset, software, and hardware.
5.2.1 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner
as shown in Figure 5-1. A low-level input on the RESET pin or internally generated RST signal causes
the program to vector to its starting address which is specified by the contents of memory locations $1FFE
and $1FFF. The I bit in the condition code register is also set. The MCU is configured to a known state
during this type of reset as previously described in Chapter 4 Resets.
5.2.2 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt since it is executed regardless
of the state of the I bit in the CCR. As with any instruction, interrupts pending during the previous
instruction will be serviced before the SWI opcode is fetched. The interrupt service routine address for the
SWI instruction is specified by the contents of memory locations $1FFC and $1FFD.
5.2.3 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts
(internal and external) are disabled. Clearing the I bit enables the hardware interrupts. Four hardware
interrupts are explained in the following subsections.
5.2.3.1 External Interrupt (IRQ)
The IRQ/VPP pin drives an asynchronous interrupt to the CPU. An edge detector flip-flop is latched on the
falling edge of IRQ/VPP. If either the output from the internal edge detector flip-flop or the level on the
IRQ/VPP pin is low, a request is synchronized to the CPU to generate the IRQ interrupt. If the LEVEL bit
in the mask option register is clear (edge-sensitive only), the output of the internal edge detector flip-flop
is sampled and the input level on the IRQ/VPP pin is ignored. The interrupt service routine address is
specified by the contents of memory locations $1FFA and $1FFB. If the port A interrupts are enabled by
the MOR, they generate external interrupts identically to the IRQ/VPP pin.
NOTE
The internal interrupt latch is cleared nine internal clock cycles after the
interrupt is recognized (immediately after location $1FFA is read).
Therefore, another external interrupt pulse could be latched during the IRQ
service routine.
Another interrupt will be serviced if the IRQ pin is still in a low state when
the RTI in the service routine is executed.
5.2.3.2 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described in Chapter 8 Capture/Compare
Timer. The input capture interrupt flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear for the input capture interrupt to be enabled. The
interrupt service routine address is specified by the contents of memory locations $1FF8 and $1FF9.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
35
Interrupts
5.2.3.3 Output Compare Interrupt
The output compare interrupt is generated by a 16-bit timer as described in Chapter 8 Capture/Compare
Timer. The output compare interrupt flag is located in register TSR and its corresponding enable bit can
be found in register TCR. The I bit in the CCR must be clear for the output compare interrupt to be
enabled. The interrupt service routine address is specified by the contents of memory locations $1FF8
and $1FF9.
5.2.3.4 Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described in Chapter 8 Capture/Compare
Timer. The timer overflow interrupt flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear for the timer overflow interrupt to be enabled.
This internal interrupt will vector to the interrupt service routine located at the address specified by the
contents of memory locations $1FF8 and $1FF9.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
36
Freescale Semiconductor
Chapter 6
Input/Output Ports
6.1 Introduction
In the user mode, 20 bidirectional I/O lines are arranged as two 8-bit I/O ports (ports A and C), one 3-bit
I/O port (port B), and one 1-bit I/O port (port D). These ports are programmable as either inputs or outputs
under software control of the data direction registers (DDRs). Port D also contains one input-only pin.
6.2 Port A
Port A is an 8-bit bidirectional port, which does not share any of its pins with other subsystems (see
Figure 6-1). The port A data register is located at address $0000 and its data direction register (DDR) is
located at address $0004. The contents of the port A data register are indeterminate at initial power up
and must be initialized by user software. Reset does not affect the data registers, but does clear the
DDRs, thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the corresponding
port pin to output mode. Port A has mask option register enabled interrupt capability with an internal pullup
device
NOTE
The keyscan (pullup/interrupt) feature available on port A is NOT available
in the ROM device, MC68HC05P6.
VDD
PULLUP MASK
OPTION REGISTER
READ $0004
WRITE $0004
DATA DIRECTION
RESET
REGISTER BIT
(RST)
I/O
PIN
WRITE $0000
READ $0000
OUTPUT
DATA
REGISTER BIT
INTERNAL HC05
TO IRQ
INTERRUPT SYSTEM
DATA BUS
Figure 6-1. Port A I/O and Interrupt Circuitry
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
37
Input/Output Ports
6.3 Port B
Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with the SIOP communications
subsystem. The port B data register is located at address $0001 and its data direction register (DDR) is
located at address $0005. The contents of the port B data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data registers, but clears the DDRs,
thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the corresponding port pin
to output mode (see Figure 6-2).
Port B may be used for general I/O applications when the SIOP subsystem is disabled. The SPE bit in
register SPCR is used to enable/disable the SIOP subsystem. When the SIOP subsystem is enabled, port
B registers are still accessible to software. Writing to either of the port B registers while a data transfer is
under way could corrupt the data. See Chapter 7 Serial Input/Output Port (SIOP) for a discussion of the
SIOP subsystem.
READ $0005
WRITE $0005
DATA DIRECTION
RESET
REGISTER BIT
(RST)
I/O
PIN
WRITE $0001
READ $0001
OUTPUT
DATA
REGISTER BIT
INTERNAL HC05
DATA BUS
Figure 6-2. Port B I/O Circuitry
6.4 Port C
Port C is an 8-bit bidirectional port which can share pins PC3–PC7 with the A/D subsystem. The port C
data register is located at address $0002 and its data direction register (DDR) is located at address
$0006. The contents of the port C data register are indeterminate at initial powerup and must be initialized
by user software. Reset does not affect the data registers, but clears the DDRs, thereby setting all of the
port pins to input mode. Writing a 1 to a DDR bit sets the corresponding port pin to output mode (see
Figure 6-3).
Port C may be used for general I/O applications when the A/D subsystem is disabled. The ADON bit in
register ADSC is used to enable/disable the A/D subsystem. Care must be exercised when using pins
PC0–PC2 while the A/D subsystem is enabled. Accidental changes to bits that affect pins PC3–PC7 in
the data or DDR registers will produce unpredictable results in the A/D subsystem. See Chapter 9 Analog
Subsystem.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
38
Freescale Semiconductor
Port D
READ $0006
WRITE $0006
DATA DIRECTION
REGISTER BIT
RESET
(RST)
I/O
PIN
WRITE $0002
READ $0002
OUTPUT
DATA
REGISTER BIT
INTERNAL HC05
DATA BUS
Figure 6-3. Port C I/O Circuitry
6.5 Port D
Port D is a 2-bit port with one bidirectional pin (PD5) and one input-only pin (PD7). Pin PD7 is shared with
the 16-bit timer. The port D data register is located at address $0003 and its data direction register (DDR)
is located at address $0007. The contents of the port D data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data registers, but clears the DDRs,
thereby setting PD5 to input mode. Writing a 1 to DDR bit 5 sets PD5 to output mode (see Figure 6-4).
Port D may be used for general I/O applications regardless of the state of the 16-bit timer. Since PD7 is
an input-only line, its state can be read from the port D data register at any time.
READ $0007
WRITE $0007
DATA DIRECTION
REGISTER BIT
RESET
(RST)
WRITE $0003
READ $0003
I/O
PIN
OUTPUT
DATA
REGISTER BIT
INTERNAL HC05
DATA BUS
Figure 6-4. Port D I/O Circuitry
6.6 I/O Port Programming
Each pin on port A through port D (except pin 7 of port D) can be programmed as an input or an output
under software control as shown in Table 6-1, Table 6-2, Table 6-3, and Table 6-4. The direction of a pin
is determined by the state of its corresponding bit in the associated port data direction register (DDR). A
pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an
input if its corresponding DDR bit is cleared to a logic 0.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
39
Input/Output Ports
Table 6-1. Port A I/O Functions
Accesses to
DDRA @ $0004
Accesses to Data
Register @ $0000
DDRA
I/O Pin Mode
Read/Write
Read
I/O Pin
Write
0
1
IN, Hi-Z
OUT
DDRA0–DDRA7
DDRA0–DDRA7
See Note
PA0–PA7
PA0–PA7
Note: Does not affect input, but stored to data register
Table 6-2. Port B I/O Functions
Accesses to
DDRB @ $0005
Accesses to Data
Register @ $0001
DDRB
I/O Pin Mode
Read/Write
Read
I/O Pin
Write
0
1
IN, Hi-Z
OUT
DDRB5–DDRB7
DDRB5–DDRB7
See Note
PB5–PB7
PB5–PB7
Note: Does not affect input, but stored to data register
Table 6-3. Port C I/O Functions
Accesses to
DDRC @ $0006
Accesses to Data
Register @ $0002
DDRC
I/O Pin Mode
Read/Write
Read
I/O Pin
Write
0
1
IN, Hi-Z
OUT
DDRC0–DDRC7
DDRC0–DDRC7
See Note
PC0–PC7
PC0–PC7
Note: Does not affect input, but stored to data register
Table 6-4. Port D I/O Functions
Accesses to
DDRD @ $0007
Accesses to Data
Register @ $0003
DDRD
I/O Pin Mode
Read/Write
DDRD5
Read
I/O Pin
PD5
Write
See Note 1
PD5
0
IN, Hi-Z
OUT
1
DDRD5
Notes:
1. Does not affect input, but stored to data register
2. PD7 is input only
NOTE
To avoid generating a glitch on an I/O port pin, data should be written to the
I/O port data register before writing a logic 1 to the corresponding data
direction register.
At power-on or reset, all DDRs are cleared, which configures all port pins as inputs. The DDRs are
capable of being written to or read by the processor. During the programmed output state, a read of the
data register will actually read the value of the output data latch and not the level on the I/O port pin.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
40
Freescale Semiconductor
Chapter 7
Serial Input/Output Port (SIOP)
7.1 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to provide efficient serial
communications between peripheral devices or other MCUs. The SIOP is implemented as a 3-wire
master/slave system with serial clock (SCK), serial data input (SDI), and serial data output (SDO). A block
diagram of the SIOP is shown in Figure 7-1. A mask programmable option determines whether the SIOP
is MSB or LSB first.
The SIOP subsystem shares its input/output pins with port B. When the SIOP is enabled (SPE bit set in
register SCR), port B DDR and data registers are modified by the SIOP. Although port B DDR and data
registers can be altered by application software, these actions could affect the transmitted or received
data.
HCO5 INTERNAL BUS
SPE
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
BAUD
SDO/PB5
SDI/PB6
8-BIT
SDO
SDI
I/O
STATUS
CONTROL
REGISTER
RATE
SHIFT
REGISTER
$0C
CONTROL
LOGIC
REGISTER
$0B
GENERATOR
$0A
SCK
SCK/PB7
INTERNAL
CPU CLOCK
Figure 7-1. SIOP Block Diagram
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
41
Serial Input/Output Port (SIOP)
7.2 SIOP Signal Format
The SIOP subsystem is software configurable for master or slave operation. No external mode selection
inputs are available (for instance, slave select pin).
7.2.1 Serial Clock (SCK)
The state of the SCK output normally remains a logic 1 during idle periods between data transfers. The
first falling edge of SCK signals the beginning of a data transfer. At this time, the first bit of received data
may be presented at the SDI pin and the first bit of transmitted data is presented at the SDO pin (see
Figure 7-2). Data is captured at the SDI pin on the rising edge of SCK. The transfer is terminated upon
the eighth rising edge of SCK.
The master and slave modes of operation differ only by the sourcing of SCK. In master mode, SCK is
driven from an internal source within the MCU. In slave mode, SCK is driven from a source external to the
MCU. The SCK frequency is dependent upon the SPR0 and SPR1 bits located in the mask option
register. Refer to 11.2 Mask Option Register for a description of available SCK frequencies.
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
SDO
SCK
SDI
100 ns
100 ns
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 7-2. SIOP Timing Diagram
7.2.2 Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is enabled. New data may be presented
to the SDI pin on the falling edge of SCK.However, valid data must be present at least 100 nanoseconds
before the rising edge of SCK and remain valid for 100 nanoseconds after the rising edge of SCK. See
Figure 7-2.
7.2.3 Serial Data Output (SDO)
The SDO pin becomes an output as soon as the SIOP subsystem is enabled. Prior to enabling the SIOP,
PB5 can be initialized to determine the beginning state. While the SIOP is enabled, PB5 cannot be used
as a standard output since that pin is connected to the last stage of the SIOP serial shift register. Mask
option register bit LSBF permits data to be transmitted in either the MSB first format or the LSB first format.
Refer to 11.2 Mask Option Register for MOR LSBF programming information.
On the first falling edge of SCK, the first data bit will be shifted out to the SDO pin. The remaining data
bits will be shifted out to the SDO pin on subsequent falling edges of SCK. The SDO pin will present valid
data at least 100 nanoseconds before the rising edge of the SCK and remain valid for 100 nanoseconds
after the rising edge of SCK. See Figure 7-2.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
42
Freescale Semiconductor
SIOP Registers
7.3 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register (SCR) located at address $000A,
the SIOP status register (SSR) located at address $000B, and the SIOP data register (SDR) located at
address $000C.
7.3.1 SIOP Control Register (SCR)
This register is located at address $000A and contains two bits. Figure 7-3 shows the position of each bit
in the register and indicates the value of each bit after reset.
Address:
$000A
Bit 7
0
6
5
0
4
MSTR
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
SPE
0
0
0
0
0
0
0
= Unimplemented
Figure 7-3. SIOP Control Register (SCR)
SPE — Serial Peripheral Enable
When set, the SPE bit enables the SIOP subsystem such that SDO/PB5 is the serial data output,
SDI/PB6 is the serial data input, and SCK/PB7 is a serial clock input in the slave mode or a serial clock
output in the master mode. Port B DDR and data registers can be manipulated as usual (except for
PB5); however, these actions could affect the transmitted or received data.
The SPE bit is readable at any time. However, writing to the SIOP control register while a transmission
is in progress will cause the SPIF and DCOL bits in the SIOP status register (see below) to operate
incorrectly. Therefore, the SIOP control register should be written once to enable the SIOP and then
not written to until the SIOP is to be disabled. Clearing the SPE bit while a transmission is in progress
will 1) abort the transmission, 2) reset the serial bit counter, and 3) convert the port B/SIOP port to a
general-purpose I/O port. Reset clears the SPE bit.
MSTR — Master Mode Select
When set, the MSTR bit configures the serial I/O port for master mode. A transfer is initiated by writing
to the SDR. Also, the SCK pin becomes an output providing a synchronous data clock dependent upon
the oscillator frequency. When the device is in slave mode, the SDO and SDI pins do not change
function. These pins behave exactly the same in both the master and slave modes.
The MSTR bit is readable and writeable at any time regardless of the state of the SPE bit. Clearing the
MSTR bit will abort any transfers that may have been in progress. Reset clears the MSTR bit as well
as the SPE bit, disabling the SIOP subsystem.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
43
Serial Input/Output Port (SIOP)
7.3.2 SIOP Status Register (SSR)
This register is located at address $000B and contains two bits. Figure 7-4 shows the position of each bit
in the register and indicates the value of each bit after reset.
Address:
$000B
Bit 7
6
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
SPIF
DCOL
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-4. SIOP Status Register (SSR)
SPIF — Serial Port Interface Flag
SPIF is a read-only status bit that is set on the last rising edge of SCK and indicates that a data transfer
has been completed. It has no effect on any future data transfers and can be ignored. The SPIF bit is
cleared by reading the SSR followed by a read or write of the SDR. If the SPIF is cleared before the
last rising edge of SCK, it will be set again on the last rising edge of SCK. Reset clears the SPIF bit.
DCOL — Data Collision
DCOL is a read-only status bit which indicates that an illegal access of the SDR has occurred. The
DCOL bit will be set when reading or writing the SDR after the first falling edge of SCK and before SPIF
is set. Reading or writing the SDR during this time will result in invalid data being transmitted or
received.
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed by a read or write of
the SDR. If the last part of the clearing sequence is done after another transfer has started, the DCOL
bit will be set again. Reset clears the DCOL bit.
7.3.3 SIOP Data Register (SDR)
This register is located at address $000C and serves as both the transmit and receive data register.
Writing to this register will initiate a message transmission if the SIOP is in master mode. The SIOP
subsystem is not double buffered and any write to this register will destroy the previous contents. The
SDR can be read at any time; however, if a transfer is in progress, the results may be ambiguous and the
DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause invalid data to be
transmitted and/or received. Figure 7-5 shows the position of each bit in the register. This register is not
affected by reset.
Address:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
SD0
Read:
Write:
Reset:
SD7
SD6
SD5
SD4
SD3
SD2
SD1
Unaffected by reset
Figure 7-5. Serial Port Data Register (SDR)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
44
Freescale Semiconductor
Chapter 8
Capture/Compare Timer
8.1 Introduction
This section describes the operation of the 16-bit capture/compare timer. Figure 8-1 shows the structure
of the capture/compare subsystem.
INTERNAL BUS
INTERNAL
PROCESSOR
CLOCK
HIGH LOW
BYTE BYTE
8-BIT
BUFFER
³³³
÷4
HIGH LOW
BYTE BYTE
$16
$17
OUTPUT
COMPARE
REGISTER
HIGH
BYTE
LOW
BYTE
INPUT
CAPTURE
REGISTER
16-BIT FREE
RUNNING
COUNTER
$14
$15
$18
$19
COUNTER
ALTERNATE
REGISTER
$1A
$1B
EDGE
DETECT
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
OUTPUT
COMPARE
CIRCUIT
D
CLK
Q
OUTPUT
LEVEL
REG.
TIMER
STATUS
REG.
$13
ICF OCF TOF
C
TIMER
CONTROLRESET
REG.
$12
ICIE OCIE TOIE IEDG OLVL
OUTPUT EDGE
LEVEL INPUT
(TCMP) (TCAP)
INTERRUPT CIRCUIT
Figure 8-1. Capture/Compare Timer Block Diagram
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
45
Capture/Compare Timer
8.2 Timer Operation
The core of the capture/compare timer is a 16-bit free-running counter. The counter provides the timing
reference for the input capture and output compare functions. The input capture and output compare
functions provide a means to latch the times at which external events occur, to measure input waveforms,
and to generate output waveforms and timing delays. Software can read the value in the 16-bit
free-running counter at any time without affecting the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input capture and output compare
functions are pairs of 8-bit registers.
Because the counter is 16 bits long and preceded by a fixed divide-by-4 prescaler, the counter rolls over
every 262,144 internal clock cycles. Timer resolution with a 4-MHz crystal is 2 µs.
8.2.1 Input Capture
The input capture function is a means to record the time at which an external event occurs. When the
input capture circuitry detects an active edge on the TCAP pin, it latches the contents of the timer registers
into the input capture registers. The polarity of the active edge is programmable.
Latching values into the input capture registers at successive edges of the same polarity measures the
period of the input signal on the TCAP pin. Latching values into the input capture registers at successive
edges of opposite polarity measures the pulse width of the signal.
8.2.2 Output Compare
The output compare function is a means of generating an output signal when the 16-bit counter reaches
a selected value. Software writes the selected value into the output compare registers. On every fourth
internal clock cycle the output compare circuitry compares the value of the counter to the value written in
the output compare registers. When a match occurs, the timer transfers the programmable output level
bit (OLVL) from the timer control register to the TCMP pin.
The programmer can use the output compare register to measure time periods, to generate timing delays,
or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the
TCMP pin.
8.3 Timer I/O Registers
The following I/O registers control and monitor timer operation:
•
•
•
•
•
•
Timer control register (TCR)
Timer status register (TSR)
Timer registers (TRH and TRL)
Alternate timer registers (ATRH and ATRL)
Input capture registers (ICRH and ICRL)
Output compare registers (OCRH and OCRL)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
46
Freescale Semiconductor
Timer I/O Registers
8.3.1 Timer Control Register
The timer control register (TCR), shown in Figure 8-2, performs these functions:
•
•
•
•
•
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Controls the active edge polarity of the TCAP signal
Controls the active level of the TCMP output
Address:
$0012
Bit 7
6
OCIE
0
5
TOIE
0
4
0
3
0
2
0
1
IEDG
U
Bit 0
OLVL
0
Read:
Write:
Reset:
ICIE
0
0
0
0
= Unimplemented
U = Undetermined
Figure 8-2. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable
This read/write bit enables interrupts caused by an active signal on the TCAP pin. Resets clear the
ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable
This read/write bit enables interrupts caused by an active signal on the TCMP pin. Resets clear the
OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow. Reset clear the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Edge
The state of this read/write bit determines whether a positive or negative transition on the TCAP pin
triggers a transfer of the contents of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture
OLVL — Output Level
The state of this read/write bit determines whether a logic 1 or logic 0 appears on the TCMP pin when
a successful output compare occurs. Resets clear the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
47
Capture/Compare Timer
8.3.2 Timer Status Register
The timer status register (TSR), shown in Figure 8-3, contains flags to signal the following conditions:
•
•
•
An active signal on the TCAP pin, transferring the contents of the timer registers to the input
capture registers
A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to
the TCMP pin
A timer roll over from $FFFF to $0000
Address:
$0013
Bit 7
ICF
6
5
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
OCF
TOF
U
U
U
0
0
0
0
0
= Unimplemented
U = Undetermined
Figure 8-3. Timer Status Register (TSR)
ICF — Input Capture Flag
The ICF bit is set automatically when an edge of the selected polarity occurs on the TCAP pin. Clear
the ICF bit by reading the timer status register with ICF set and then reading the low byte ($0015) of
the input capture registers. Resets have no effect on ICF.
OCF — Output Compare Flag
The OCF bit is set automatically when the value of the timer registers matches the contents of the
output compare registers. Clear the OCF bit by reading the timer status register with OCF set and then
reading the low byte ($0017) of the output compare registers. Resets have no effect on OCF.
TOF — Timer Overflow Flag
The TOF bit is set automatically when the 16-bit counter rolls over from $FFFF to $0000. Clear the
TOF bit by reading the timer status register with TOF set, and then reading the low byte ($0019) of the
timer registers. Resets have no effect on TOF.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
48
Freescale Semiconductor
Timer I/O Registers
8.3.3 Timer Registers
The timer registers (TRH and TRL), shown in Figure 8-4, contains the current high and low bytes of the
16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading
TRL after reading the timer status register clears the timer overflow flag (TOF). Writing to the timer
registers has no effect.
Address: TRH — $0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write
TRH7
TRH6
TRH5
TRH4
TRH3
TRH2
TRH1
TRH0
Reset:
1
1
1
1
1
1
1
1
Address: TRL — $0019
Bit 7
6
1
5
1
4
1
3
1
2
1
1
0
Bit 0
0
Write:
Reset:
1
= Unimplemented
Figure 8-4. Timer Registers (TRH and TRL)
8.3.4 Alternate Timer Registers
The alternate timer registers (ATRH and ATRL), shown in Figure 8-5, contain the current high and low
bytes of the 16-bit counter. Reading ATRH before reading ATRL causes ATRL to be latched until ATRL
is read. Reading ATRL has no effect on the timer overflow flag (TOF). Writing to the alternate timer
registers has no effect.
Address: ATRH — $001A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
1
1
1
1
1
1
1
1
Address: ATRL — $001B
Bit 7
6
1
5
1
4
1
3
1
2
1
1
0
Bit 0
0
Write:
Reset:
1
= Unimplemented
Figure 8-5. Alternate Timer Registers (ATRH and ATRL)
NOTE
To prevent interrupts from occurring between readings of ATRH and ATRL,
set the interrupt flag in the condition code register before reading ATRH,
and clear the flag after reading ATRL.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
49
Capture/Compare Timer
8.3.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are
latched into the input capture registers. Reading ICRH before reading ICRL inhibits further capture until
ICRL is read. Reading ICRL after reading the status register clears the input capture flag (ICF). Writing to
the input capture registers has no effect.
Address: ICRH — $0014
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
Unaffected by reset
Address: ICRL — $0015
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Unaffected by reset
= Unimplemented
Figure 8-6. Input Capture Registers (ICRH and ICRL)
NOTE
To prevent interrupts from occurring between readings of ICRH and ICRL,
set the interrupt flag in the condition code register before reading ICRH, and
clear the flag after reading ICRL.
8.3.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the output compare registers, the planned
TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer compares until OCRL
is written. Reading or writing to OCRL after the timer status register clears the output compare flag (OCF).
Address: OCRH — $0016
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Read:
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
Unaffected by reset
Address: OCRL — $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Unaffected by reset
Figure 8-7. Output Compare Registers (OCRH and OCRL)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
50
Freescale Semiconductor
Timer During Wait/Halt Mode
To prevent OCF from being set between the time it is read and the time the output compare registers are
updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
8.4 Timer During Wait/Halt Mode
The CPU clock halts during the wait (or halt) mode, but the timer remains active. If interrupts are enabled,
a timer interrupt will cause the processor to exit the wait mode.
8.5 Timer During Stop Mode
In the stop mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt.
If STOP is exited by RESET, the counters are forced to $FFFC. During STOP, if at least one valid input
capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any
timer flags or wake up the MCU, but if an interrupt is used to exit stop mode, there is an active input
capture flag and data from the first valid edge that occurred during the stop mode. If reset is used to exit
stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
51
Capture/Compare Timer
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
52
Freescale Semiconductor
Chapter 9
Analog Subsystem
9.1 Introduction
The MC68HC705P6A includes a 4-channel, multiplexed input, 8-bit, successive approximation
analog-to-digital (A/D) converter. The A/D subsystem shares its inputs with port C pins PC3–PC7.
9.2 Analog Section
The following paragraphs describe the operation and performance of analog modules within the analog
subsystem.
9.2.1 Ratiometric Conversion
The A/D converter is ratiometric, with pin VREFH supplying the high reference voltage. Applying an input
voltage equal to VREFH produces a conversion result of $FF (full scale). Applying an input voltage equal
to VSS produces a conversion result of $00. An input voltage greater than VREFH will convert to $FF with
no overflow indication. For ratiometric conversions, VREFH should be at the same potential as the supply
voltage being used by the analog signal being measured and referenced to VSS.
9.2.2 Reference Voltage (V
)
REFH
The reference supply for the A/D converter shares pin PC7 with port C. The low reference is tied to the
VSS pin internally. VREFH can be any voltage between VSS and VDD; however, the accuracy of
conversions is tested and guaranteed only for VREFH = VDD
.
9.2.3 Accuracy and Precision
The 8-bit conversion result is accurate to within 1 1/2 LSB, including quantization; however, the accuracy
of conversions is tested and guaranteed only with external oscillator operation.
9.3 Conversion Process
The A/D reference inputs are applied to a precision digital-to-analog converter. Control logic drives the
D/A and the analog output is successively compared to the selected analog input which was sampled at
the beginning of the conversion cycle. The conversion process is monotonic and has no missing codes.
9.4 Digital Section
The following paragraphs describe the operation and performance of digital modules within the analog
subsystem.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
53
Analog Subsystem
9.4.1 Conversion Times
Each input conversion requires 32 internal clock cycles, which must be at a frequency equal to or greater
than 1 MHz.
9.4.2 Internal versus External Oscillator
If the internal clock is 1 MHz or greater (i.e., external oscillator 2 MHz or greater), the internal RC oscillator
must be turned off and the external oscillator used as the conversion clock.
If the MCU internal clock frequency is less than 1 MHz (2 MHz external oscillator), the internal RC
oscillator (approximately 1.5 MHz) must be used for the A/D converter clock. The internal RC clock is
selected by setting the ADRC bit in the ADSC register.
When the internal RC oscillator is being used, these limitations apply:
1. Since the internal RC oscillator is running asynchronously with respect to the internal clock, the
conversion complete bit (CC) in register ADSC must be used to determine when a conversion
sequence has been completed.
2. Electrical noise will slightly degrade the accuracy of the A/D converter. The A/D converter is
synchronized to read voltages during the quiet period of the clock driving it. Since the internal and
external clocks are not synchronized, the A/D converter will occasionally measure an input when
the external clock is making a transition.
9.4.3 Multi-Channel Operation
An input multiplexer allows the A/D converter to select from one of four external analog signals. Port C
pins PC3 through PC6 are shared with the inputs to the multiplexer.
9.5 A/D Status and Control Register (ADSC)
The ADSC register reports the completion of A/D conversion and provides control over oscillator
selection, analog subsystem power, and input channel selection. See Figure 9-1.
Address: $001E
Bit 7
CC
6
ADRC
0
5
ADON
0
4
0
3
0
2
CH2
0
1
CH1
0
Bit 0
CH0
0
Read:
Write:
Reset:
0
0
0
= Unimplemented
Figure 9-1. A/D Status and Control Register (ADSC)
CC — Conversion Complete
This read-only status bit is set when a conversion sequence has completed and data is ready to be
read from the ADC register. CC is cleared when the ADSC is written to or when data is read from the
ADC register. Once a conversion has been started, conversions of the selected channel will continue
every 32 internal clock cycles until the ADSC register is written to again. During continuous conversion
operation, the ADC register will be updated with new data, and the CC bit set every 32 internal clock
cycles. Also, data from the previous conversion will be overwritten regardless of the state of the CC bit.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
54
Freescale Semiconductor
A/D Conversion Data Register (ADC)
ADRC — RC Oscillator Control
When ADRC is set, the A/D subsystem operates from the internal RC oscillator instead of the internal
clock. The RC oscillator requires a time, tRCON, to stabilize before accurate conversion results can be
obtained. See 9.2.2 Reference Voltage (VREFH) for more information.
ADON — A/D Subsystem On
When the A/D subsystem is turned on (ADON = 1), it requires a time, tADON, to stabilize before
accurate conversion results can be attained.
CH2–CH0 — Channel Select Bits
CH2, CH1, and CH0 form a 3-bit field which is used to select an input to the A/D converter. Channels
0–3 correspond to port C input pins PC6–PC3. Channels 4–6 are used for reference measurements.
Channel 7 is reserved. If a conversion is attempted with channel 7 selected, the result will be $00.
Table 9-1 lists the inputs selected by bits CH0-CH3.
If the ADON bit is set and an input from channels 0–4 is selected, the corresponding port C pin’s DDR
bit will be cleared (making that port C pin an input). If the port C data register is read while the A/D is
on and one of the shared input channels is selected using bit CH0–CH2, the corresponding port C pin
will read as a logic 0. The remaining port C pins will read normally. To digitally read a port C pin, the
A/D subsystem must be disabled (ADON = 0), or input channels 5–7 must be selected.
Table 9-1. A/D Multiplexer Input Channel Assignments
Channel
Signal
0
1
2
3
4
AD0 — port C, bit 6
AD1 — port C, bit 5
AD2 — port C, bit 4
AD3 — port C, bit 3
VREFH — port C, bit 7
(VREFH + VSS)/2
VSS
5
6
7
Reserved for factory test
9.6 A/D Conversion Data Register (ADC)
This register contains the output of the A/D converter. See Figure 9-2.
Address: $001D
Bit 7
AD7
6
5
4
3
2
1
Bit 0
AD0
Read:
Write:
Reset:
AD6
AD5
AD4
AD3
AD2
AD1
Unaffected by reset
= Unimplemented
Figure 9-2. A/D Conversion Value Data Register (ADC)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
55
Analog Subsystem
9.7 A/D Subsystem Operation during Halt/Wait Modes
The A/D subsystem continues normal operation during wait and halt modes. To decrease power
consumption during wait or halt mode, the ADON and ADRC bits in the A/D status and control register
should be cleared if the A/D subsystem is not being used.
9.8 A/D Subsystem Operation during Stop Mode
When stop mode is enabled, execution of the STOP instruction will terminate all A/D subsystem functions.
Any pending conversion is aborted. When the oscillator resumes operation upon leaving stop mode, a
finite amount of time passes before the A/D subsystem stabilizes sufficiently to provide conversions at its
rated accuracy. The delays built into the MC68HC705P6A when coming out of stop mode are sufficient
for this purpose. No explicit delays need to be added to the application software.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
56
Freescale Semiconductor
Chapter 10
EPROM
10.1 Introduction
The user EPROM consists of 48 bytes of user page zero EPROM from $0020 to $004F, 4608 bytes of
user EPROM from $0100 to $12FF, the two MOR reset values located at $1EFF and $1F00, and 16 bytes
of user vectors EPROM from $1FF0 to $1FFF. The bootloader ROM and vectors are located from $1F01
to $1FEF.
10.2 EPROM Erasing
NOTE
Only parts packaged in a windowed package may be erased. Others are
one-time programmable and may not be erased by UV exposure.
The MC68HC705P6A can be erased by exposure to a high-intensity ultraviolet (UV) light with a
wavelength of 2537 angstroms. The recommended dose (UV intensity multiplied by exposure time) is
15 Ws/cm2. UV lamps without shortwave filters should be used, and the EPROM device should be
positioned about one inch from the UV lamp. An erased EPROM byte will read as $00.
10.3 EPROM Programming Sequence
The bootloader software goes through a complete write cycle of the EPROM including the MOR. This is
followed by a verify cycle which continually branches in a loop if an error is found. A sample routine to
program a byte of EPROM is shown in Table 10-1.
NOTE
To avoid damage to the MCU, VDD must be applied to the MCU before VPP
.
10.4 EPROM Registers
Three registers are associated with the EPROM: the EPROM programming register (EPROG) and the
two mask option registers (MOR). The EPROG register controls the actual programming of the EPROM
bytes and the MOR. The MOR registers control the six mask options found on the ROM version of this
MCU (MC68HC05P6), the EPROM security feature, and eight additional port A interrupt options.
10.5 EPROM Programming Register (EPROG)
This register is used to program the EPROM array. Only the ELAT and EPGM bits are available.
Table 10-1 shows the location of each bit in the EPROG register and the state of these bits coming out of
reset. All the bits in the EPROG register are cleared by reset.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
57
EPROM
Address $001C
Bit 7
6
0
5
0
4
0
3
0
2
ELAT
0
1
0
Bit 0
EPGM
0
Read:
Write:
Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 10-1. EPROM Programming Register (EPROG)
EPGM — EPROM Program Control
If the EPGM bit is set, programming power is applied to the EPROM array. If the EPGM bit is cleared,
programming power is removed from the EPROM array. The EPGM bit cannot be set unless the ELAT
bit is set already.
Whenever the ELAT bit is cleared, the EPGM bit is cleared also. Both the EPGM and the ELAT bit
cannot be set using the same write instruction. Any attempt to set both the EPGM and ELAT bit on the
same write instruction cycle will result in the ELAT bit being set and the EPGM bit being cleared. The
EPGM bit is a read-write bit and can be read at any time. The EPGM bit is cleared by reset.
ELAT— EPROM Latch Control
If the ELAT bit is set, the EPROM address and data bus are configured for programming to the array.
If the ELAT bit is cleared, the EPROM address and data bus are configured for normal reading of data
from the array. When the ELAT bit is set, the address and data bus are latched in the EPROM array
when a subsequent write to the array is made. Data in the EPROM array cannot be read if the ELAT
bit is set.
Whenever the ELAT bit is cleared, the EPGM bit is cleared also. Both the EPGM and the ELAT bit
cannot be set using the same write instruction. Any attempt to set both the EPGM and ELAT bit on the
same write instruction cycle will result in the ELAT bit being set and the EPGM bit being cleared. The
ELAT bit is a read-write bit and can be read at any time. The ELAT bit is cleared by reset.
To program a byte of EPROM, manipulate the EPROG register as follows:
1. Set the ELAT bit in the EPROG register.
2. Write the desired data to the desired EPROM address.
3. Set the EPGM bit in the EPROG register for the specified programming time, t
4. Clear the ELAT and EPGM bits in the EPROG register.
.
EPGM
This sequence is also shown in the sample program listing in Table 10-1.
Table 10-1. EPROM Programming Routine
001C
0055
0700
0000
EPROG
DATA
EPROM
EPGM
EQU $1C
EQU $55
EQU $700
EQU $00
PROGRAMMING REG
DATA VALUE
A SAMPLE EPROM ADX
EPGM BIT IN EPROG REG
00D0
ORG
$D0
00D0
00D2
00D4
00D6
00D9
00DB
00DD
00DF
A6 02
B7 1C
A6 55
C7 07 00
10 1C
AD 03
3F 1C
81
LDA #$04
STA EPROG
LDA #DATA
SET LAT BIT IN EPROG
DATA BYTE
STA EPROM
BSET EPGM, EPROG
BSR DELAY
CLR EPROG
RTS
WRITE IT TO EPROM LOC
TURN ON PGM VOLTAGE
WAIT 4 ms MINIMUM
CLR LAT AND PGM BITS
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
58
Freescale Semiconductor
EPROM Bootloader
10.6 EPROM Bootloader
Three port pins are associated with bootloader control functions: PC3, PC4, and PC6. Table 10-2
summarizes their functionality.
Table 10-2. Bootloader Control Pins
PC6
PC4
PC3
Mode
Program/verify
1
1
1
1
1
0
1
0
0
Verify only
Dump MCU EPROM to port A
10.7 Programming from an External Memory Device
In this programming mode, PC5 must be connected to VSS. PC4 and PC3 are used to select the
programming mode. The programming circuit shown in Figure 10-2 uses an external 12-bit counter to
address the memory device containing the code to be copied. This counter requires a clock and a reset
function. The 12-bit counter can address up to 4 Kbytes of memory, which means that a port pin has to
be used to address the remaining 4 K of the 8-K memory space.
The following procedure explains how to use the programming circuit shown in Figure 10-2 to copy a user
program from an external memory device into the MCU’s EPROM:
1. Program a 2764-type EPROM device with the desired instructions and data. Code programmed
into the 2764 must appear at the same addresses desired in the MC68HC705P6A. Therefore, the
page zero code must start at $0020 and end at $004F, the main body of code must start at $0100
and end at $12FF, and the user vectors must start at $1FF0 and end at $1FFF.
NOTE
The MOR data must appear at $1EFF and $1F00.
2. Install the programmed 2764 device into the programming circuit.
3. Install the MC68HC705P6A to be programmed into the programming circuit.
4. Set the PROGRAM and/or VERIFY switches for the desired operation (an open switch is the active
state) and close the RESET switch to hold the MCU in reset.
5. Make sure that the VPP source is OFF.
6. Apply the VDD source to the programming circuit.
7. Apply the VPP source to the programming circuit.
8. Open the RESET switch to allow the MCU to come out of reset and begin execution of the software
in its internal bootloader ROM.
9. Wait for programming and/or verification to complete (about 40 seconds). The PROGRAM LED will
light during programming and the VERIFY LED will light if verification was requested and was
successful.
10. When complete, close the RESET switch to force the MCU into the reset state.
11. Turn off the VPP source.
12. Turn off the VDD source.
13. Remove device(s).
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
59
EPROM
PROGRAM 2764 TYPE EPROM
INSTALL EPROM INTO PROGRAMMER
N
PROGRAMMING?
Y
INSTALL MC68HC705P6A INTO PROGRAMMER
WAIT FOR PROGRAMMING LED TO
TURN ON AND OFF.
N
PROGRAMMING?
Y
OPEN PROGRAM SWITCH
CLOSE PROGRAM SWITCH
N
VERIFYING?
Y
WAIT FOR 30 SECONDS
N
VERIFYING?
Y
OPEN VERIFY SWITCH
CLOSE VERIFY SWITCH
N
IS VERIFY
LED LIT?
CLOSE RESET SWITCH
MAKE SURE VPP IS OFF
TURN VDD ON
Y
VERIFICATION FAILED
VERIFICATION COMPLETE
CLOSE RESET SWITCH
TURN OFF VPP
TURN VPP ON
OPEN RESET SWITCH
TURN OFF VDD
REMOVE DEVICES
Figure 10-2. MC68HC705P6A EPROM Programming Flowchart
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
60
Freescale Semiconductor
Programming from an External Memory Device
V
DD
MC68HC705P6A
10 kΩ
V
IRQ/VPP
PP
2764
MC74HC4040
PD7/TCAP
PB5
V
DD
OSC1
OSC2
PGM
2 MHz
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Q12
A12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
10 MΩ
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
D7
D6
D5
D4
D3
D2
D1
D0
20 pF
20 pF
V
DD
10 kΩ
1 µF
RESET
RESET
V
CE
OE
DD
RST
CLK
V
DD
10 kΩ
PC6
PB7
PC1
PC2
PROG
330 Ω
330 Ω
V
V
DD
10 kΩ
DD
10 kΩ
VERF
PGM
VFY
PB6
PC5
PC3
PC4
V
V
= 5.0 V
DD
= 16.5 V
PP
Figure 10-3. MC68HC705P6A EPROM Programming Schematic Diagram
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
61
EPROM
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
62
Freescale Semiconductor
Chapter 11
Mask Option Register (MOR)
11.1 Introduction
The mask option register (MOR) contains two bytes of EPROM used to enable or disable each of the
features controlled by mask options on the MC68HC05P6 (a ROM version of the MC68HC705P6A).
The seven programmable options on the MC68HC705P6A are:
1. COP watchdog timer (enable or disable)
2. IRQ triggering (edge- or edge- and level-sensitive)
3. SIOP data bit order (most significant bit or least significant bit first)
4. SIOP clock rate (OSC divided by 8, 16, 32, or 64)
5. Stop instruction mode (stop mode or halt mode)
6. Secure EPROM from external reading
7. Keyscan interrupt/pullups on PA0–PA7
11.2 Mask Option Register
Mask options are programmed into the mask option register (MOR) by the firmware in the bootloader
ROM. See Figure 11-1.
Address: $1EFF
Bit 7
PA7PU
0
6
PA6PU
0
5
PA5PU
0
4
PA4PU
0
3
PA3PU
0
2
PA2PU
0
1
PA1PU
0
Bit 0
PA0PU
0
Read:
Write:
Erased State:
Address: $1F00
Bit 7
SECURE
0
6
0
5
SWAIT
0
4
SPR1
0
3
SPR0
0
2
LSBF
0
1
LEVEL
0
Bit 0
COP
0
Read:
Write:
Erased State:
= Unimplemented
Figure 11-1. Mask Option Register (MOR)
COP — COP Watchdog Enable
Setting the COP bit will enable the COP watchdog timer. The COP will reset the MCU if the timeout
period is reached before the COP watchdog timer is cleared by the application software and the
voltage applied to the IRQ/VPP pin is between VSS and VDD. Clearing the COP bit will disable the COP
watchdog timer regardless of the voltage applied to the IRQ/VPP pin.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
63
Mask Option Register (MOR)
LEVEL — IRQ Edge Sensitivity
If the LEVEL bit is clear, the IRQ/VPP pin will only be sensitive to the falling edge of the signal applied
to the IRQ/VPP pin. If the LEVEL bit is set, the IRQ/VPP pin will be sensitive to both the falling edge of
the input signal and the logic low level of the input signal on the IRQ/VPP pin.
LSBF — SIOP Least Significant Bit First
If the LSBF bit is set, the serial data to and from the SIOP will be transferred least significant bit first.
If the LSBF bit is clear, the serial data to and from the SIOP will be transferred most significant bit first.
SPR0 and SPR1 — SIOP Clock Rate
The SPR0 and SPR1 bits determine the clock rate used to transfer the serial data to and from the
SIOP. The various clock rates available are given in Table 11-1.
Table 11-1. SIOP Clock Rate
SPR1
SPR0
SIOP Master Clock
fosc ÷ 64
0
0
1
1
0
1
0
1
fosc ÷ 32
fosc ÷ 16
fosc ÷ 8
SWAIT — STOP Instruction Mode
Setting the SWAIT bit will prevent the STOP instruction from stopping the on-board oscillator. Clearing
the SWAIT bit will permit the STOP instruction to stop the on-board oscillator and place the MCU in
stop mode. Executing the STOP instruction when SWAIT is set will place the MCU in halt mode. See
3.4.1 STOP Instruction for additional information.
SECURE — Security State(1)
If SECURE bit is set, the EPROM is locked.
PA(0:7)PU — Port A Pullups/Interrupt Enable/Disable
If any PA(0:7)PU is selected, that pullup/interrupt is enabled. The interrupt sensitivity will be selected
via the LEVEL bit in the same way as the IRQ pin.
NOTE
The port A pullup/interrupt function is NOT available on the ROM device,
MC68HC05P6.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
64
Freescale Semiconductor
MOR Programming
11.3 MOR Programming
The contents of the MOR should be programmed in bootloader mode using the hardware shown in
Figure 10-2. MC68HC705P6A EPROM Programming Flowchart. In order to allow programming, all the
implemented bits in the MOR are essentially read-write bits in bootloader mode as shown in Figure 11-1.
The programming of the MOR is the same as user EPROM.
1. Set the ELAT bit in the EPROG register.
2. Write the desired data to the desired MOR address.
3. Set the EPGM bit in the EPROG.
4. Wait for the programming time (tEPGM).
5. Clear the ELAT and EPGM bits in the EPROG.
6. Remove the programming voltage from the IRQ/VPP pin.
A sample routine to program a byte of EPROM is shown in Table 11-2.
Once the MOR bits have been programmed, the options are not loaded into the MOR registers until the
part is reset.
Table 11-2. MOR Programming Routine
001C
00FF
0023
1EFF
1F00
0000
EPROG
DATA2
DATA1
MOR2
MOR1
EPGM
EQU $1C
EQU $FF
EQU #23
EQU $1EFF
EQU $1F00
EQU $00
PROGRAMMING REG
SAMPLE MOR VALUES
MOPR ADDRESSES
EPGM BIT IN EPROG REG
00E0
ORG $E0
00E0
00E2
00E4
00E6
00E9
00EB
00ED
00EF
A6 04
B7 1C
A6 FF
C7 1E FF
12 1C
AD 03
3F 1C
81
LDA #$04
STA EPROG
LDA #DATA2
STA MOR2
BSET EPGM,EPROG
BSR DELAY
CLR EPROG
RTS
SET ELAT BIT
IN EPGM REG AT $1C
DATA BYTE
WRITE IT TO MOR LOC
TURN ON PGM VOLTAGE
WAIT 4 ms MINIMUM
CLR EPGM REGISTER
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
65
Mask Option Register (MOR)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
66
Freescale Semiconductor
Chapter 12
Central Processor Unit (CPU) Core
12.1 Introduction
The MC68HC705P6A has an 8-K memory map. Therefore, it uses only the lower 13 bits of the address
bus. In the following discussion, the upper three bits of the address bus can be ignored. Also, the STOP
instruction can be modified to place the MCU in either the normal stop mode or the halt mode by means
of a MOR bit. All other instructions and registers behave as described in this section.
12.2 Registers
The MCU contains five registers which are hard-wired within the CPU and are not part of the memory
map. These five registers are shown in Figure 12-1 and are described in the following paragraphs.
7
6
5
4
3
2
1
0
ACCUMULATOR
INDEX REGISTER
A
X
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
1
1
STACK POINTER
SP
PC
CC
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
1
H
I
N
Z
C
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
Figure 12-1. MC68HC05 Programming Model
12.2.1 Accumulator
The accumulator is a general-purpose 8-bit register as shown in Figure 12-1. The CPU uses the
accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The
accumulator is unaffected by a reset of the device.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
67
Central Processor Unit (CPU) Core
12.2.2 Index Register
The index register shown in Figure 12-1 is an 8-bit register that can perform two functions:
•
•
Indexed addressing
Temporary storage
In indexed addressing with no offset, the index register contains the low byte of the operand address, and
the high byte is assumed to be $00. In indexed addressing with an 8-bit offset, the CPU finds the operand
address by adding the index register contents to an 8-bit immediate value. In indexed addressing with a
16-bit offset, the CPU finds the operand address by adding the index register contents to a 16-bit
immediate value.
The index register can also serve as an auxiliary accumulator for temporary storage. The index register
is unaffected by a reset of the device.
12.2.3 Stack Pointer
The stack pointer shown in Figure 12-1 is a 16-bit register internally. In devices with memory maps less
than 64 Kbytes, the unimplemented upper address lines are ignored. The stack pointer contains the
address of the next free location on the stack. During a reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to $00FF. The stack pointer is then decremented as data is pushed onto the stack
and incremented as data is pulled from the stack.
When accessing memory, the 10 most significant bits are permanently set to 0000000011. The six least
significant register bits are appended to these 10 fixed bits to produce an address within the range of
$00FF to $00C0. Subroutines and interrupts may use up to 64 ($40) locations. If 64 locations are
exceeded, the stack pointer wraps around and writes over the previously stored information. A subroutine
call occupies two locations on the stack and an interrupt uses five locations.
12.2.4 Program Counter
The program counter shown in Figure 12-1 is a 16-bit register internally. In devices with memory maps
less than 64 Kbytes, the unimplemented upper address lines are ignored. The program counter contains
the address of the next instruction or operand to be fetched.
Normally, the address in the program counter increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
12.2.5 Condition Code Register
The CCR shown in Figure 12-1 is a 5-bit register in which four bits are used to indicate the results of the
instruction just executed. The fifth bit is the interrupt mask. These bits can be individually tested by a
program, and specific actions can be taken as a result of their state. The condition code register should
be thought of as having three additional upper bits that are always ones. Only the interrupt mask is
affected by a reset of the device. The following paragraphs explain the functions of the lower five bits of
the condition code register.
H — Half Carry Bit
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator
during the last ADD or ADC (add with carry) operation. The half-carry bit is required for binary-coded
decimal (BCD) arithmetic operations.
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Registers
I — Interrupt Mask Bit
When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts are enabled
when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is automatically set
after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt
request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt
is processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt
mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and
can only be cleared by the clear I bit (CLI), STOP, or WAIT instructions.
N — Negative Bit
The negative bit is set when the result of the last arithmetic operation, logical operation, or data
manipulation was negative. (Bit 7 of the result was a logic one.)
The negative bit can also be used to check an often-tested flag by assigning the flag to bit 7 of a
register or memory location. Loading the accumulator with the contents of that register or location then
sets or clears the negative bit according to the state of the flag.
Z — Zero Bit
The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation,
or data load operation was zero.
C — Carry/Borrow Bit
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last
arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared
during bit test and branch instructions and during shifts and rotates. This bit is not set by an INC or
DEC instruction.
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Central Processor Unit (CPU) Core
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Chapter 13
Instruction Set
13.1 Introduction
The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include
all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X).
The high-order product is stored in the index register, and the low-order product is stored in the
accumulator.
13.2 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide
eight different ways for the CPU to find the data required to execute an instruction. The eight addressing
modes are:
•
•
•
•
•
•
•
•
Inherent
Immediate
Direct
Extended
Indexed, no offset
Indexed, 8-bit offset
Indexed, 16-bit offset
Relative
13.2.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP).
Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
13.2.2 Immediate
Immediate instructions are those that contain a value to be used in an operation with the value in the
accumulator or index register. Immediate instructions require no operand address and are two bytes long.
The opcode is the first byte, and the immediate data value is the second byte.
13.2.3 Direct
Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the
opcode, and the second is the low byte of the operand address. In direct addressing, the CPU
automatically uses $00 as the high byte of the operand address.
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Instruction Set
13.2.4 Extended
Extended instructions use three bytes and can access any address in memory. The first byte is the
opcode; the second and third bytes are the high and low bytes of the operand address.
When using the Freescale assembler, the programmer does not need to specify whether an instruction is
direct or extended. The assembler automatically selects the shortest form of the instruction.
13.2.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses
within the first 256 memory locations. The index register contains the low byte of the effective address of
the operand. The CPU automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of
a frequently used RAM or I/O location.
13.2.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses
within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the
unsigned byte following the opcode. The sum is the effective address of the operand. These instructions
can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table
can begin anywhere within the first 256 memory locations and could extend as far as location 510
($01FE). The k value is typically in the index register, and the address of the beginning of the table is in
the byte following the opcode.
13.2.7 Indexed,16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at
any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand. The first byte after the opcode is
the high byte of the 16-bit offset; the second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere
in memory.
As with direct and extended addressing, the Freescale assembler determines the shortest form of
indexed addressing.
13.2.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the
effective branch destination by adding the signed byte following the opcode to the contents of the program
counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed,
two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Freescale assembler, the programmer does not need to calculate the offset, because the
assembler determines the proper offset and verifies that it is within the span of the branch.
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Instruction Types
13.3 Instruction Types
The MCU instructions fall into the following five categories:
•
•
•
•
•
Register/memory instructions
Read-modify-write instructions
Jump/branch instructions
Bit manipulation instructions
Control instructions
13.3.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations. Most of them use two operands. One
operand is in either the accumulator or the index register. The CPU finds the other operand in memory.
Table 13-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Add Memory Byte to Accumulator
AND Memory Byte with Accumulator
Bit Test Accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare Accumulator
CMP
CPX
EOR
LDA
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Multiply
LDX
MUL
ORA
SBC
STA
OR Accumulator with Memory Byte
Subtract Memory Byte and Carry Bit from Accumulator
Store Accumulator in Memory
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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Instruction Set
13.3.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and write the modified value
back to the memory location or to the register.
NOTE
Do not use read modify-write operations on write-only registers.
Table 13-2. Read-Modify-Write Instructions
Instruction
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
Mnemonic
ASL
ASR
BCLR(1)
Bit Clear
BSET(1)
CLR
COM
DEC
INC
Bit Set
Clear Register
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left (Same as ASL)
Logical Shift Right
LSL
LSR
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
NEG
ROL
ROR
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
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Instruction Types
13.3.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The
unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register
operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter
when a test condition is met. If the test condition is not met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first
256 memory locations. These 3-byte instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte
is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of
the opcode. The span of branching is from –128 to +127 from the address of the next location after the
branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code
register.
Table 13-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Branch if Lower
BHS
BIH
BIL
BLO
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
BLS
BMC
BMI
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
BMS
BNE
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
BRN
BRSET
BSR
Branch Never
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
JMP
JSR
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Instruction Set
13.3.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers
and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 13-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit Clear
Branch if Bit Clear
Branch if Bit Set
Bit Set
BRCLR
BRSET
BSET
13.3.5 Control Instructions
These instructions act on CPU registers and control CPU operation during program execution.
Table 13-5. Control Instructions
Instruction
Mnemonic
CLC
CLI
Clear Carry Bit
Clear Interrupt Mask
No Operation
NOP
RSP
RTI
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
RTS
SEC
SEI
Set Interrupt Mask
Stop Oscillator and Enable IRQ Pin
Software Interrupt
STOP
SWI
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
TAX
TXA
WAIT
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Instruction Set Summary
13.4 Instruction Set Summary
Table 13-6 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on
the condition code register.
Table 13-6. Instruction Set Summary (Sheet 1 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
ii
dd
hh ll
ee ff
ff
ADC #opr
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
2
3
4
5
4
3
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
Add without Carry
Logical AND
A ← (A) + (M) + (C)
ꢀ —
ꢀ —
— —
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM
DIR
EXT CB
IX2
IX1
IX
AB
BB
2
3
4
5
4
3
A ← (A) + (M)
A ← (A) ∧ (M)
ꢀ
DB
EB
FB
ii
dd
hh ll
ee ff
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
2
3
4
5
4
3
ꢀ —
dd
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
C
0
Arithmetic Shift Left (Same as LSL)
— —
— —
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
b7
b7
b0
b0
ff
dd
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
INH
IX1
IX
37
47
57
67
77
5
3
3
6
5
C
Arithmetic Shift Right
ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
BCS rel
BEQ rel
BHCC rel
BHCS rel
BHI rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
25 rr
27 rr
28 rr
29 rr
22 rr
24 rr
3
3
3
3
3
3
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
BHS rel
Branch if Higher or Same
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Instruction Set
Table 13-6. Instruction Set Summary (Sheet 2 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
BIH rel
BIL rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL
2F rr
2E rr
3
3
Branch if IRQ Pin Low
ii
dd
hh ll
ee ff
ff
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
2
3
4
5
4
3
Bit Test Accumulator with Memory Byte
(A) ∧ (M)
— — ꢀ ꢀ —
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — — REL
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
PC ← (PC) + 2 + rel ? Mn = 0 — — — — ꢀ
BRN rel
Branch Never
PC ← (PC) + 2 + rel ? 1 = 0
— — — — — REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
PC ← (PC) + 2 + rel ? Mn = 1 — — — — ꢀ
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
— — — — — REL AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
2
2
Clear Interrupt Mask
9A
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Instruction Set Summary
Table 13-6. Instruction Set Summary (Sheet 3 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
dd
ff
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
5
3
3
6
5
Clear Byte
— — 0 1 —
ii
dd
hh ll
ee ff
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
2
3
4
5
4
3
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
Decrement Byte
(A) – (M)
— —
— —
— —
— —
— —
— —
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
ꢀ
dd
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
5
3
3
6
5
ii
dd
hh ll
ee ff
ff
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
2
3
4
5
4
3
(X) – (M)
dd
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
5
3
3
6
5
ꢀ —
ꢀ —
ꢀ —
ii
dd
hh ll
ee ff
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
2
3
4
5
4
3
EXCLUSIVE OR Accumulator with Memory
Byte
A ← (A) ⊕ (M)
dd
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
5
3
3
6
5
Increment Byte
dd
hh ll
ee ff
ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT CC
IX2
IX1
IX
BC
2
3
4
3
2
Unconditional Jump
Jump to Subroutine
PC ← Jump Address
— — — — —
— — — — —
DC
EC
FC
dd
hh ll
ee ff
ff
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT CD
IX2
IX1
IX
BD
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
DD
ED
FD
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Instruction Set
Table 13-6. Instruction Set Summary (Sheet 4 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
ii
dd
hh ll
ee ff
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
2
3
4
5
4
3
Load Accumulator with Memory Byte
A ← (M)
— —
ꢀ
ꢀ
ꢀ —
ii
dd
hh ll
ee ff
ff
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT CE
IX2
IX1
IX
AE
BE
2
3
4
5
4
3
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
X ← (M)
— —
ꢀ —
DE
EE
FE
dd
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
C
0
— — ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
b7
b0
ff
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
Unsigned Multiply
— — 0
b7
b0
ff
1
1
MUL
X : A ← (X) × (A)
0 — — — 0
INH
42
dd
ff
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
IX1
IX
30
40
50
60
70
5
3
3
6
5
Negate Byte (Two’s Complement)
No Operation
— — ꢀ ꢀ ꢀ
NOP
— — — — —
INH
9D
2
ii
dd
hh ll
ee ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT CA
IX2
IX1
IX
AA
BA
2
3
4
5
4
3
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
A ← (A) ∨ (M)
— —
ꢀ
ꢀ —
DA
EA
FA
dd
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
INH
IX1
IX
39
49
59
69
79
5
3
3
6
5
C
— —
— —
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
b7
b0
ff
dd
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
INH
IX1
IX
36
46
56
66
76
5
3
3
6
5
C
Rotate Byte Right through Carry Bit
Reset Stack Pointer
b7
b0
ff
RSP
SP ← $00FF
— — — — —
INH
9C
2
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
80
Freescale Semiconductor
Instruction Set Summary
Table 13-6. Instruction Set Summary (Sheet 5 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
Return from Interrupt
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
INH
INH
80
81
9
6
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
— — — — —
ii
dd
hh ll
ee ff
ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
2
3
4
5
4
3
Subtract Memory Byte and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
— — ꢀ ꢀ ꢀ
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
2
2
Set Interrupt Mask
9B
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
4
5
6
5
4
Store Accumulator in Memory
Stop Oscillator and Enable IRQ Pin
Store Index Register In Memory
M ← (A)
— — ꢀ ꢀ —
STOP
— 0 — — —
INH
8E
2
dd
hh ll
ee ff
ff
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
4
5
6
5
4
M ← (X)
— —
— —
ꢀ
ꢀ
ꢀ —
ii
dd
hh ll
ee ff
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
2
3
4
5
4
3
Subtract Memory Byte from Accumulator
A ← (A) – (M)
ꢀ ꢀ
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
1
0
SWI
TAX
Software Interrupt
— 1 — — —
— — — — —
INH
83
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Transfer Accumulator to Index Register
Test Memory Byte for Negative or Zero
X ← (A)
INH
97
2
dd
ff
TST opr
TSTA
TSTX
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
4
3
3
5
4
(M) – $00
— — ꢀ ꢀ —
TST opr,X
TST ,X
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
81
Instruction Set
Table 13-6. Instruction Set Summary (Sheet 6 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
TXA
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
A ← (X)
— — — — —
— 0 — — —
INH
INH
9F
8F
2
2
WAIT
A
C
Accumulator
Carry/borrow flag
opr
PC
Operand (one or two bytes)
Program counter
CCR Condition code register
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
dd
Direct address of operand
dd rr
DIR
ee ff
EXT
ff
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
rel
rr
SP
X
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
H
Z
Zero flag
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
#
∧
Immediate value
Logical AND
ii
Immediate operand byte
∨
Logical OR
IMM
INH
IX
IX1
IX2
M
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
⊕
( )
–( )
←
?
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
:
ꢀ
Concatenated with
Set or cleared
N
Negative flag
n
Any bit
—
Not affected
13.5 Opcode Map
See Table 13-7.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
82
Freescale Semiconductor
Table 13-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
INH
IX1
IX
7
INH
INH
IMM
A
DIR
B
EXT
IX2
IX1
E
IX
F
MSB
LSB
MSB
LSB
0
1
2
4
5
6
8
9
C
D
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
SUB
SUB
SUB
SUB
SUB
CMP
SBC
CPX
AND
BIT
0
1
0
3
DIR 2
5
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
6
2
2
2
2
2
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BRCLR0
BCLR0
BRN
RTS
CMP
CMP
CMP
CMP
CMP
1
2
3
DIR 2
5
DIR 2
5
REL
3
1
INH
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
11
BRSET1
BSET1
BHI
MUL
SBC
SBC
SBC
SBC
CPX
AND
BIT
SBC
CPX
AND
BIT
2
3
DIR 2
5
DIR 2
5
REL
3
1
5
INH
3
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
3
6
5
10
SWI
INH
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
LSR
CPX
CPX
CPX
3
3
3
DIR 2
5
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX 1
5
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
AND
AND
4
4
3
DIR 2
5
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BRCLR2
BCLR2 BCS/BLO
BIT
BIT
BIT
5
5
3
DIR 2
5
DIR 2
5
REL
3
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
3
3
6
5
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
ASR
LDA
LDA
LDA
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
6
6
3
DIR 2
5
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
IMM 2
DIR 3
4
EXT 3
5
IX2 2
6
IX1 1
5
IX
4
2
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
STA
7
7
3
DIR 2
5
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
1
1
1
1
1
1
1
INH
2
2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BRSET4
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
CLC
EOR
EOR
EOR
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
8
8
3
DIR 2
5
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
DEC
SEC
ADC
ADC
ADC
9
9
3
DIR 2
5
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
ORA
ORA
ORA
A
B
C
D
E
F
A
B
C
D
E
F
3
DIR 2
5
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BRCLR5
BCLR5
BMI
SEI
ADD
ADD
ADD
3
DIR 2
5
DIR 2
5
REL
3
INH 2
2
IMM 2
DIR 3
2
EXT 3
3
IX2 2
4
IX1 1
3
IX
2
5
3
3
6
5
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
TST
INC
TST
RSP
INH
JMP
JMP
3
DIR 2
5
DIR 2
5
REL 2
3
DIR 1
4
INH 1
3
INH 2
3
IX1 1
5
IX
4
2
6
DIR 3
5
EXT 3
6
IX2 2
7
IX1 1
6
IX
5
2
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
NOP
BSR
JSR
JSR
3
DIR 2
5
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
REL 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
2
BRSET7
BSET7
BIL
STOP
LDX
LDX
LDX
3
DIR 2
5
DIR 2
5
REL
3
1
INH
2
2
2
IMM 2
DIR 3
4
EXT 3
5
IX2 2
6
IX1 1
5
IX
4
5
3
3
6
5
BRCLR7
BCLR7
BIH
CLR
DIR 1
CLRA
INH 1
CLRX
INH 2
CLR
CLR
WAIT
TXA
INH
STX
STX
3
DIR 2
DIR 2
REL 2
IX1 1
IX 1
INH 1
2
DIR 3
EXT 3
IX2 2
IX1 1
IX
MSB
INH = Inherent
IMM = Immediate
DIR = Direct
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
0
MSB of Opcode in Hexadecimal
LSB
5
Number of Cycles
BRSET0 Opcode Mnemonic
LSB of Opcode in Hexadecimal
0
EXT = Extended
3
DIR Number of Bytes/Addressing Mode
Instruction Set
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
84
Freescale Semiconductor
Chapter 14
Electrical Specifications
14.1 Introduction
This section contains the electrical and timing specifications.
14.2 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging
it.
The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do
not apply voltages higher than those shown in the table below. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating(1)
Symbol
VDD
Value
Unit
V
Supply voltage
Input voltage
–0.3 to +7.0
VIn
VSS –0.3 to VDD +0.3
VSS –0.3 to 2 x VDD +0.3
V
Bootloader mode (IRQ/VPP pin only)
Current drain per pin excluding VDD and VSS
Storage temperature range
VIn
V
I
25
mA
°C
Tstg
–65 to +150
1. Voltages are referenced to VSS
.
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 14.5 5.0-Volt DC Electrical Characteristics and
14.6 3.3-Volt DC Electrical Charactertistics for guaranteed operating
conditions.
14.3 Operating Temperature Range
Characteristic
Symbol
Value
Unit
TL to TH
0 to +70
–40 to +85
Operating temperature range
MC68HC705P6A (standard)
MC68HC705P6AC (extended)
TA
°C
14.4 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
PDIP
SOIC
θJA
60
60
°C/W
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
85
Electrical Specifications
14.5 5.0-Volt DC Electrical Characteristics
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
Output voltage
I
= 10.0 µA
VOL
VOH
—
DD –0.1
Load
Load
—
—
0.1
—
V
V
I
= –10.0 µA
Output high voltage
(I
= –0.8 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
VDD –0.8
VDD –0.8
VOH
Load
Load
—
—
—
—
V
V
(I
= –5.0 mA) PC0:1
Output low voltage
(I
= 1.6 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
VOL
Load
Load
—
—
—
—
0.4
0.4
(I
= 10 mA) PC0:1
Input high voltage
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP, RESET,
OSC1
VIH
0.7 x VDD
VDD
—
—
V
V
Input low voltage
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP, RESET,
VIL
VSS
0.2 x VDD
OSC1
Supply current(3), (4)
Run
Wait(5) (A/D converter on)
Wait(5) (A/D converter off)
Stop(6)
25°C
—
—
—
4.0
2.0
1.3
7.0
4.0
2.0
mA
mA
mA
IDD
—
—
—
2
—
—
30
50
100
µA
µA
µA
0°C to +70°C (standard)
–40°C to +85°C (extended)
I/O ports high-z leakage current
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7
IIL
IOZ
IIn
—
—
—
—
10.0
1.0
µA
µA
µA
µA
A/D ports hi-z leakage current
PC3:7
Input current
RESET, IRQ/VPP, OSC1, PD7/TCAP
—
—
1.0
Input pullup current
PA0:7 (with pullup enabled)
IIn
175
385
750
Capaitance
Ports (as input or output)
RESET, IRQ/VPP
COut
CIn
—
—
—
—
12
8
pF
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted. All values shown refelect pre-silicon
estimates.
2. Typical values at midpoint of voltage range, 25°C only.
3. Run (Operating) IDD, Wait IDD: To be measured using external square wave clock source (fosc = 4.2 MHz), all inputs 0.2 V
from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V.
5. Wait IDD will be affected linearly by the OSC2 capacitance.
6. Stop IDD to be measured with OSC1 = VSS
.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
86
Freescale Semiconductor
3.3-Volt DC Electrical Charactertistics
14.6 3.3-Volt DC Electrical Charactertistics
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
Output voltage
I
= 10.0 µA
VOL
VOH
—
DD –0.1
Load
Load
—
—
0.1
—
V
V
I
= –10.0 µA
Output high voltage
(I
= –0.2 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
VDD –0.3
VDD –0.3
VOH
Load
Load
—
—
—
—
V
V
(I
= –1.2 mA) PC0:1
Output low voltage
(I
= 0.4 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
VOL
Load
Load
—
—
—
—
0.3
0.3
(I
= 2.5 mA) PC0:1
Input high voltage
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP, RESET,
OSC1
VIH
0.7 x VDD
VDD
—
—
V
V
Input low voltage
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP, RESET,
VIL
VSS
0.2 x VDD
OSC1
Supply current(3), (4)
Run
Wait(5) (A/D converter on)
Wait(5) (A/D converter off)
Stop(6)
25°C
—
—
—
1.8
1.0
0.6
2.5
1.4
1.0
mA
mA
mA
IDD
—
—
—
2
—
—
20
40
50
µA
µA
µA
0°C to +70°C (standard)
–40°C to +85°C (extended)
I/O ports high-z leakage current
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7
IIL
IOZ
IIn
—
—
—
75
—
—
10.0
1.0
µA
µA
µA
µA
A/D ports hi-z leakage current
PC3:7
Input current
RESET, IRQ/VPP, OSC1, PD7/TCAP
—
1.0
Input pullup current
PA0:7 (with pullup enabled)
IIn
175
350
Capaitance
Ports (as input or output)
RESET, IRQ/VPP
COut
CIn
—
—
—
—
12
8
pF
1. VDD = 3.3 Vdc 0.3 Vdc, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted. All values shown reflect pre-silicon
estimates.
2. Typical values at midpoint of voltage range, 25°C only.
3. Run (Operating) IDD, Wait IDD: To be measured using external square wave clock source (fosc = 4.2 MHz), all inputs 0.2 V
from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V.
5. Wait IDD will be affected linearly by the OSC2 capacitance.
6. Stop IDD to be measured with OSC1 = VSS
.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
87
Electrical Specifications
14.7 A/D Converter Characteristics
Characteristic(1)
Min
Max
Unit
Comments
Resolution
8
8
Bits
Absolute accuacy
(VDD ≥ VREFH > 4.0)
—
1 1/2
LSB
V
Including quanitization
A/D accuracy may decrease
proportionately as VREFH is
reduced below 4.0
VSS
VSS
VREFH
VDD
Conversion range
VREFH
Input leakage
AD0, AD1, AD2, AD3
VREFH
—
—
1
1
µA
Conversion time
MCU external oscillator
Internal RC oscillator
tcyc
µs
—
—
32
32
Includes sampling time
Monotonicity
Inherent (within total error)
Vin = 0 V
Zero input reading
Full-scale reading
00
01
FF
Hex
Hex
Vin = VREFH
FE
Sample time
MCU external oscillator
Internal RC oscillator
tcyc
µs
—
—
12
12
Input capacitance
—
12
pF
V
VSS
VREFH
Analog input voltage
tADON
IOZ
A/D on current stabilization time
A/D ports hi-z leakage current (PC3:7)
—
—
100
1
µs
µA
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
14.8 EPROM Programming Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Programming voltage
IRQ/VPP
VPP
16.25
16.5
16.75
V
Programming current
IRQ/VPP
IPP
—
4
5.0
—
10
—
mA
ms
tEPGM
Programming time per byte
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
88
Freescale Semiconductor
SIOP Timing
14.9 SIOP Timing
Number
Characteristic
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fop(m)
fop(s)
fop
0.25
dc
0.25
0.25
Cycle time
Master
Slave
tcyc(m)
tcyc(s)
tcyc
1
4.0
—
4.0
4.0
tcyc
tv
tho
ts
2
3
4
5
6
SCK low time
932
—
—
200
—
ns
ns
ns
ns
ns
SDO data valid time
SDO hold time
SDI setup time
SDI hold time
0
100
100
—
th
—
t1
t2
SCK
t5
t6
SDI
BIT 0
BIT 1 ... 6
BIT 7
t3
t4
SDO
BIT 0
BIT 1 ... 6
BIT 7
Figure 14-1. SIOP Timing Diagram
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
89
Electrical Specifications
14.10 Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
External clock option
fOSC
—
DC
4.2
4.2
MHz
Internal operating frequency
Crystal (fOSC ÷ 2)
External clock (fOSC ÷ 2)
fOP
—
DC
2.1
2.1
MHz
tCYC
tOXOV
tILCH
tRL
Cycle time
476
—
—
100
100
—
ns
ms
Crystal oscillator startup time
Stop mode recovery startup time (crystal oscillator)
RESET pulse width
—
ms
tCYC
1.5
tILIH
Interrupt pulse width low (edge-triggered)
125
Note 2
200
Q
—
ns
Interrupt pulse period(2)
OSC1 pulse width
tILIL
tCYC
—
tOH, tOL
tADON
—
ns
A/D On current stabilization time
100
µs
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted
2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tCYC
.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
90
Freescale Semiconductor
t
VDDR
V
THRESHOLD (1-2 V TYPICAL)
DD
V
DD
(2)
OSC1
4064 t
cyc
t
cyc
INTERNAL
PROCESSOR
(1)
CLOCK
INTERNAL
ADDRESS
(1)
1FFE
1FFF
NEW PC
NEW PC
1FFE
1FFE
1FFE
1FFE
PCH
1FFF
PCL
NEW PC
NEW PC
BUS
INTERNAL
DATA
(1)
NEW
PCH
NEW
PCL
OP
CODE
OP
CODE
BUS
tRL
NOTE 3
RESET
Notes:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal clock following the rising edge of RESET initiates the reset sequence.
Figure 14-2. Power-On Reset and External Reset Timing Diagram
Electrical Specifications
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
92
Freescale Semiconductor
Chapter 15
Mechanical Specifications
15.1 Introduction
The MC68HC705P6A is available in either a 28-pin plastic dual in-line (PDIP) or a 28-pin small outline
integrated circuit (SOIC) package.
15.2 Plastic Dual In-Line Package (Case 710)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
28
1
15
14
B
MILLIMETERS
MIN MAX
INCHES
MIN MAX
DIM
A
B
C
D
F
36.45 37.21
13.72 14.22
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
L
A
C
3.94
0.36
1.02
5.08
0.56
1.52
N
G
H
J
2.54 BSC
0.100 BSC
1.65
0.20
2.92
2.16
0.38
3.43
0.065 0.085
0.008 0.015
0.115 0.135
J
H
G
K
L
M
K
SEATING
PLANE
15.24 BSC
0.600 BSC
F
D
0°
0.51
15°
1.02
0°
0.020 0.040
15°
M
N
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
93
Mechanical Specifications
15.3 Small Outline Integrated Circuit Package (Case 751F)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
28
1
15
14X P
M
M
-B-
0.010 (0.25)
B
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
14
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
28X D
M
M
S
S
B
0.010 (0.25)
T
A
R X 45°
MILLIMETERS
MIN MAX
17.80 18.05
INCHES
MIN MAX
C
DIM
A
-T-
0.701 0.711
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
-T-
SEATING
PLANE
B
7.40
2.35
0.35
0.41
7.60
2.65
0.49
0.90
26X G
C
D
K
F
F
G
J
1.27 BSC
0.23
0.13
0°
0.32
0.29
8°
0.009 0.013
0.005 0.011
J
K
M
P
0° 8°
0.395 0.415
10.05 10.55
R
0.25 0.75
0.010 0.029
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
94
Freescale Semiconductor
Chapter 16
Ordering Information
16.1 Introduction
This section contains ordering information for the available package types.
16.2 MC Order Numbers
The following table shows the MC order numbers for the available package types.
Operating
MC Order Number
Temperature Range
MC68HC705P6ACP(1) (extended)
MC68HC705P6ACDW(2) (extended)
–40°C to 85°C
–40°C to 85°C
1. P = Plastic dual in-line package
2. DW = Small outline integrated circuit (SOIC) package
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
95
Ordering Information
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
96
Freescale Semiconductor
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MC68HC705P6A
Rev. 2.1, 9/2005
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