MC68HC708XL36 [FREESCALE]
HCMOS Microcontroller Unit; HCMOS微控制器单元
| 型号： | MC68HC708XL36 |
| 厂家： | 
Freescale |
| 描述： | HCMOS Microcontroller Unit |
| 文件： | 总376页 (文件大小：2207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MC68HC708XL36/D
HC 8
MC68HC708XL36
HCMOS Mic roc ontrolle r Unit
TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
\
List of Se c tions
List of Se c tions
Ta b le of Conte nts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introd uc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Me m ory Ma p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ra nd om Ac c e ss Me m ory (RAM) . . . . . . . . . . . . . . . . . . 33
Nonvola tile Me m ory (EPROM) . . . . . . . . . . . . . . . . . . . . 35
Config ura tion Re g iste r (CONFIG). . . . . . . . . . . . . . . . . . 39
Ce ntra l Proc e ssor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . 41
Re se ts a nd Inte rrup ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Low-Powe r Mod e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Cloc k Ge ne ra tor Mod ule (CGM). . . . . . . . . . . . . . . . . . 83
Dire c t Me m ory Ac c e ss Mod ule (DMA) . . . . . . . . . . . . 111
Bre a k Mod ule (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Tim e r Inte rfa c e Mod ule (TIM) . . . . . . . . . . . . . . . . . . . . 171
Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI) . . . . . . . . . . . 201
Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI). . . . . 235
Inp ut/ Outp ut Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
© Motorola, Inc., 1996
MOTOROLA
MC68HC708XL36
List of Sections
3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
List of Se c tions
Com p ute r Op e ra ting Prop e rly Mod ule (COP) . . . . . . 305
Exte rna l Inte rrup t Mod ule (IRQ) . . . . . . . . . . . . . . . . . . 311
Ke yb oa rd Inte rrup t Mod ule (KB) . . . . . . . . . . . . . . . . . 321
Low-Volta g e Inhib it Mod ule (LVI) . . . . . . . . . . . . . . . . 329
Sp e c ific a tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Glossa ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Ind e x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Lite ra ture Up d a te s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
MC68HC708XL36
4
List of Sections
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Ta b le of Conte nts
Ta b le of Conte nts
Introduction
Memory Map
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Reserved Memory Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
RAM
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
EPROM
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
EPROM Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
CONFIG Register
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
MC68HC708XL36
MOTOROLA
Table of Contents
5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Ta b le of Conte nts
CPU
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Resets
and Interrupts
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Low-Power Modes
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Computer Operating Properly Module (COP) . . . . . . . . . . . . . . . . . . .76
Direct Memory Access Module (DMA) . . . . . . . . . . . . . . . . . . . . . . . .76
External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Keyboard Interrupt Module (KB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . .78
Serial Peripheral Interface Module (SPI). . . . . . . . . . . . . . . . . . . . . . .79
Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
CGM
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
MC68HC708XL36
6
Table of Contents
MOTOROLA
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table of Contents
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . .106
DMA
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
DMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
BRK
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
MON
TIM
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
MC68HC708XL36
MOTOROLA
Table of Contents
7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Ta b le of Conte nts
SPI
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Transmission Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
Error Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
Resetting the SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
SPI During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
SCI
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .262
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
I/O Ports
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
Port F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
MC68HC708XL36
8
Table of Contents
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table of Contents
COP
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . .310
IRQ
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .318
IRQ Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .318
KBI
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . . . . . .326
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
LVI
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
LVI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
MC68HC708XL36
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Ta b le of Conte nts
Specifications
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
Preliminary Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .333
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
Glossary
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
Index
Literature Updates
Literature Distribution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
Mfax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
Motorola SPS World Marketing World Wide Web Server . . . . . . . . .372
CSIC Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . .372
MC68HC708XL36
10
Table of Contents
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Introd uc tion
Introd uc tion
Conte nts
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . . . . .17
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . .18
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
External Interrupt Pins (IRQ1/VPP and IRQ2) . . . . . . . . . . . . . . . .18
Clock Ground Pin (CGND/EVSS) . . . . . . . . . . . . . . . . . . . . . . . . . .18
CGM Power Supply Pin (VDDA). . . . . . . . . . . . . . . . . . . . . . . . . . .18
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . .18
Port A Input/Output (I/O) Pins (PA7–PA0) . . . . . . . . . . . . . . . . . . .19
Port B I/O Pins (PB7–PB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Port C I/O Pins (PC7–PC0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Port D I/O Pins (PD7/KBD7–PD0/KBD0) . . . . . . . . . . . . . . . . . . . .19
Port E I/O Pins (PE7/TCH3–PE0). . . . . . . . . . . . . . . . . . . . . . . . . .19
Port F I/O Pins (PF5–PF0/SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Port G I/O Pins (PG3–PG0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Port H I/O Pins (PH3–PH0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1-intro_a
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Introd uc tion
Fe a ture s
Features of the MC68HC708XL36 include the following:
•
•
High-Performance M68HC08 Architecture
Fully Upward-Compatible Object Code with M6805, M146805,
and M68HC05 Families
•
•
8-MHz Internal Bus Frequency
36 Kbytes of On-Chip Erasable Programmable Read-Only
Memory (EPROM) or One-Time Programmable Read-Only
Memory (OTPROM)
•
On-Chip Programming Firmware for Use with Host Personal
Computer
•
•
•
•
•
•
•
•
EPROM/OTPROM Data Security
One Kbyte of On-Chip Random-Access Memory (RAM)
Serial Peripheral Interface Module (SPI)
Serial Communications Interface Module (SCI)
16-Bit, 4-Channel Timer Interface Module (TIM)
Three-Channel Direct Memory Access Module (DMA)
Clock Generator Module (CGM)
System Protection Features
– Optional Computer Operating Properly (COP) Reset
– Low-Voltage Detection with Optional Reset
– Illegal Opcode Detection with Optional Reset
– Illegal Address Detection with Optional Reset
•
56-Pin Plastic Shrink Dual-In-Line Package (SDIP) or 64-Pin
Plastic Quad Flat Pack (QFP)
•
•
•
Low-Power Design (Fully Static with Stop and Wait Modes)
Master Reset Pin and Power-On Reset
8-Bit Keyboard Wakeup Port
2-intro_a
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Introduction
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Introduction
MCU Block Diagram
Features of the CPU08 include the following:
•
•
•
•
•
•
•
•
•
•
Enhanced HC05 Programming Model
Extensive Loop Control Functions
16 Addressing Modes (Eight More Than the HC05)
16-Bit Index Register and Stack Pointer
Memory-to-Memory Data Transfers
Fast 8 × 8 Multiply Instruction
Fast 16/8 Divide Instruction
Binary-Coded Decimal (BCD) Instructions
Optimization for Controller Applications
Third Party C Language Support
MCU Bloc k Dia g ra m
Figure 1 shows the structure of the MC68HC708XL36.
3-intro_a
MC68HC708XL36
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Introd uc tion
P O R T A
D D R A
P O R T B
D D R B
P O R T C
D D R C
P O R T D
D D R D
P O R T G
D D R G
P O R T H
D D R H
P O R T E
D D R E
P O R T F
D D R F
4-intro_a
MC68HC708XL36
14
Introduction
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Introduction
Pin Assignments
Pin Assig nm e nts
RST
PF5
PF4
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
IRQ1/V
2
PP
IRQ2
PF3/MISO
PF2/MOSI
CGND/EV
3
V
4
DDA
CGMXFC
OSC1
5
SS
PF1/SPSCK
PF0/SS
6
OSC2
7
V
PE7/TCH3
PE6/TCH2
PE5/TCH1
PE4/TCH0
PE3/TCLK
PE2/TxD
PE1/RxD
PE0
8
SS
V
9
DD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD7/KBD7
PD6/KBD6
PD5/KBD5
PD4/KBD4
PD3/KBD3
PD2/KBD2
PD1/KBD1
PD0/KBD0
PC7
PC6
PC5
PC4
PC3
Figure 2. SDIP Pin Assignments
5-intro_a
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Introd uc tion
OSC1
OSC2
PE7/TCH3
PE6/TCH2
PE5/TCH1
PE4/TCH0
PE3/TCLK
PE2/TxD
1
48
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
3
SS
V
4
DD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
5
6
PE1/RxD
PE0
7
8
PD7/KBD7
PD6/KBD6
PD5/KBD5
PD4/KBD4
PD3/KBD3
PD2/KBD2
PD1/KBD1
PD0/KBD0
9
10
11
12
13
14
15
16
33
NOTE: Ports G and H are available only with the QFP.
Figure 3. QFP Pin Assignments
6-intro_a
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Introduction
Pin Functions
Pin Func tions
Powe r Sup p ly Pins
V
and V are the power supply and ground pins. The MCU operates
DD SS
(V a nd V )
from a single power supply.
DD
SS
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 4 shows.
Place the C1 bypass capacitor as close to the MCU as possible. Use a
high-frequency-response ceramic capacitor for C1. C2 is an optional
bulk current bypass capacitor for use in applications that require the port
pins to source high current levels.
MCU
V
V
SS
DD
C1
0.1 µF
+
C2
V
DD
NOTE: Component values shown
represent typical applications.
Figure 4. Power Supply Bypassing
7-intro_a
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Introd uc tion
Osc illa tor Pins
(OSC1 a nd OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. (See Clock Generator Module on page 83.)
Exte rna l Re se t Pin
(RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted.
Exte rna l Inte rrup t
IRQ1/V and IRQ2 are asynchronous external interrupt pins. (See
PP
Pins (IRQ1/ V
a nd IRQ2)
External Interrupt Module on page 311.) IRQ1/V is also the
EPROM/OTPROM programming power pin. (See Memory Map on page
21.)
PP
PP
Cloc k Ground Pin
(CGND/ EV )
CGND/EV is the ground for the port output buffers and the ground
return for the serial clock in the serial peripheral interface module (SPI).
(See Serial Peripheral Interface Module on page 201.)
SS
SS
NOTE: CGND/EV must be grounded for proper MCU operation.
SS
CGM Powe r
Sup p ly Pin (V
V
is the power supply pin for the analog portion of the clock
DDA
)
generator module (CGM). (See Clock Generator Module on page 83.)
DDA
Exte rna l Filte r
Ca p a c itor Pin
(CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. (See
Clock Generator Module on page 83.)
8-intro_a
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Introduction
Pin Functions
Port A
Inp ut/ Outp ut (I/ O)
Pins (PA7–PA0)
PA7–PA0 are general-purpose bidirectional I/O port pins. (See
Input/Output Ports on page 283.)
Port B I/ O Pins
(PB7–PB0)
PB7–PB0 are general-purpose bidirectional I/O port pins. (See
Input/Output Ports on page 283.)
Port C I/ O Pins
(PC7–PC0)
PC7–PC0 are general-purpose bidirectional I/O port pins. (See
Input/Output Ports on page 283.)
Port D I/ O Pins
(PD7/ KBD7–
PD0/ KBD0)
PD7/KBD7–PD0/KBD0 are general-purpose bidirectional I/O port pins.
Any or all of the port D pins can be programmed to serve as external
interrupt pins. (See Input/Output Ports on page 283.)
Port E I/ O Pins
(PE7/ TCH3–PE0)
Port E is an 8-bit special function port that shares five of its pins with the
timer interface module (TIM) and two of its pins with the serial
communications interface (SCI) module. (See Timer Interface Module,
Serial Communications Interface Module, and Input/Output Ports.)
Port F I/ O Pins
(PF5–PF0/ SS)
Port F is a 6-bit special function port that shares four of its pins with the
serial peripheral interface module (SPI). (See Serial Peripheral Interface
Module and Input/Output Ports.)
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Introd uc tion
Port G I/ O Pins
(PG3–PG0)
PG3–PG0 are general-purpose bidirectional I/O pins. (See Input/Output
Ports on page 283.) Port G is available only with the 64-pin package.
Port H I/ O Pins
(PH3–PH0)
PH3–PH0 are general-purpose bidirectional I/O pins. (See Input/Output
Ports on page 283.) Port H is available only with the 64-pin package.
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Me m ory Ma p
Me m ory Ma p
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Unimplemented Memory Locations. . . . . . . . . . . . . . . . . . . . . . . . . . .22
Reserved Memory Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1-mem_a
MC68HC708XL36
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Memory Map
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Me m ory Ma p
Introd uc tion
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 1, includes:
•
36 Kbytes of erasable programmable read-only memory
(EPROM)
•
•
•
One Kbyte of random-access memory (RAM)
34 bytes of user-defined vectors
240 bytes of monitor ROM
Unimplemented Me m ory Loc a tions
Accessing an unimplemented location can cause an illegal address
reset if illegal address resets are enabled. In the memory map figure and
in register figures in this document, unimplemented locations are
shaded.
Re se rve d Me m ory Loc a tions
Accessing a reserved location can have unpredictable effects on MCU
operation. In the memory map figure and in register figures in this
document, reserved locations are marked with the word Reserved or
with the letter R.
2-mem_a
MC68HC708XL36
22
Memory Map
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Memory Map
Reserved Memory Locations
$0000
I/O Registers
80 Bytes
↓
$004F
$0050
↓
RAM
1024 Bytes
$044F
$0450
↓
Unimplemented
27,056 Bytes
$6DFF
$6E00
↓
EPROM
36,864 BYTES
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
↓
Break Status Register (BSR)
Reset Status Register (RSR)
Reserved
Break Flag Control Register (BFCR)
Interrupt Status Register 1 (INT1)
Interrupt Status Register 2 (INT2)
Interrupt Status Register 3 (INT3)
EPROM Control Register (EPMCR)
Unimplemented
4 Bytes
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
$FE10
↓
Break Address Register High (BRKH)
Break Address Register Low (BRKL)
Break Status and Control Register (BSCR)
LVI Status Register (LVISR)
Monitor ROM
240 Bytes
$FEFF
$FF00
↓
Unimplemented
222 Bytes
$FFDD
$FFDE
↓
Vectors
34 Bytes
$FFFF
Figure 1. Memory Map
3-mem_a
MC68HC708XL36
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Memory Map
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Me m ory Ma p
Inp ut/ Outp ut (I/ O) Se c tion
Addresses $0000–$004F contain most of the control, status, and data
registers. Additional I/O registers have the following addresses:
•
•
•
•
•
•
•
•
•
•
•
$FE00 (break status register, BSR)
$FE01 (reset status register, RSR)
$FE03 (break flag control register, BFCR)
$FE04 (interrupt status register 1, INT1)
$FE05 (interrupt status register 2, INT2)
$FE06 (interrupt status register 3, INT3)
$FE07 (EPROM control register, EPMCR)
$FE0C and $FE0D (break address registers, BRKH and BRKL)
$FE0E (break status and control register, BSCR)
$FE0F (LVI status register, LVISR)
$FFFF (COP control register, COPCTL)
4-mem_a
MC68HC708XL36
24
Memory Map
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Memory Map
Input/Output (I/O) Section
Register Name
Addr.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Port A Data Register
(PORTA)
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
$0000
Unaffected by Reset
PB4 PB3
Unaffected by Reset
PC4 PC3
Unaffected by Reset
PD4 PD3
Unaffected by Reset
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Port B Data Register
(PORTB)
PB7
PC7
PD7
PB6
PC6
PD6
PB5
PC5
PD5
PB2
PC2
PD2
PB1
PC1
PD1
PB0
PC0
PD0
$0001
$0002
$0003
$0004
$0005
Port C Data Register
(PORTC)
Port D Data Register
(PORTD)
Data Direction Register A
(DDRA)
0
0
0
0
0
0
0
0
Data Direction Register B
(DDRB)
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0
0
0
0
0
0
0
0
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Data Direction Register C
(DDRC)
$0006 Write:
Reset:
0
0
0
0
0
0
0
0
Read:
Data Direction Register D
(DDRD)
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
$0007
$0008
$0009
$000A
$000B
$000C
$000D
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
Port E Data Register
(PORTE)
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Unaffected by Reset
PF4 PF3
0
0
0
0
0
0
Port F Data Register
(PORTF)
PF5
0
PF2
PG2
PH2
PF1
PG1
PH1
PF0
PG0
PH0
Unaffected by Reset
0
Port G Data Register
(PORTG)
PG3
Unaffected by Reset
0
0
Port H Data Register
(PORTH)
PH3
Unaffected by Reset
Data Direction Register E
(DDRE)
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
0
0
0
0
0
DDRF5
0
0
DDRF4
0
0
DDRF3
0
0
DDRF2
0
0
DDRF1
0
0
DDRF0
0
Data Direction Register F
(DDRF)
0
0
= Unimplemented
R = Reserved
Figure 2. I/O Register Summary
5-mem_a
MC68HC708XL36
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Memory Map
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Me m ory Ma p
Register Name
Addr.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
Data Direction Register G
(DDRG)
DDRG3 DDRG2 DDRG1 DDRG0
$000E
0
0
0
0
0
0
0
0
0
0
0
0
Data Direction Register H
(DDRH)
DDRH3 DDRH2 DDRH1 DDRH0
$000F
$0010
$0011
0
SPRIE
0
0
0
0
0
0
0
SPE
0
0
SPI Control Register
(SPCR)
DMAS SPMSTR CPOL
CPHA SPWOM
SPTIE
0
0
1
0
0
0
Read: SPRF
Write:
OVRF
MODF
SPTE
SPI Status and Control
Register (SPSCR)
ERRIE
MODFEN SPR1
SPR0
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
1
0
0
0
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register (SPDR) $0012
Unaffected by Reset
SCI Control Register 1
$0013
LOOPS
0
ENSCI
0
TXINV
M
0
WAKE
0
ILTY
0
PEN
0
PTY
0
(SCC1)
0
SCRIE
0
SCI Control Register 2
$0014
SCTIE
TCIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
(SCC2)
0
R8
0
SCI Control Register 3
$0015
T8
DMARE DMATE
ORIE
NEIE
FEIE
PEIE
(SCC3)
U
U
0
0
0
0
0
0
Read: SCTE
Write:
TC
SCRF
IDLE
OR
NF
FE
PE
SCI Status Register 1
$0016
(SCS1)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
1
1
0
0
0
0
0
BKF
0
RPF
SCI Status Register 2
$0017
(SCS2)
0
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
0
R3
T3
0
R2
T2
0
R1
T1
0
R0
T0
SCI Data Register
$0018
(SCDR)
Unaffected by Reset
SCP1
SCP0
R
SCR2
SCR1
0
SCR0
0
SCI Baud Rate Register
$0019 Write:
Reset:
(SCBR)
0
0
0
0
0
0
0
0
0
0
Read:
KEYF
0
ACKK
0
Keyboard Status and
Control Register (KBSCR)
IMASKK MODEK
$001A
$001B
Write:
Reset:
Read:
Write:
Reset:
0
KBIE7
0
0
KBIE6
0
0
KBIE5
0
0
KBIE4
0
0
KBIE3
0
0
KBIE1
0
0
KBIE0
0
Keyboard Interrupt
Enable Register (KBIER)
KBIE2
0
= Unimplemented
R = Reserved
Figure 2. I/O Register Summary (Continued)
6-mem_a
MC68HC708XL36
26
Memory Map
MOTOROLA
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Memory Map
Input/Output (I/O) Section
Register Name
Addr.
Bit 7
PLLIE
0
6
PLLF
5
PLLON
1
4
BCS
0
3
1
2
1
1
1
Bit 0
1
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PLL Control Register
(PCTL)
$001C
0
1
0
1
0
1
0
1
0
LOCK
PLL Bandwidth Control
Register (PBWC)
AUTO
0
ACQ
0
XLD
0
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
0
MUL6
1
0
VRS7
0
0
0
VRS5
1
0
VRS4
0
PLL Programming
Register (PPG)
MUL7
0
MUL5
1
MUL4
0
VRS6
1
0
Configuration Register
(CONFIG)
COPRS LVISTOP LVIRSTD LVIPWRD SSREC
STOP
0
COPD
0
0
TOF
0
0
0
0
0
0
0
0
0
PS2
0
0
TRST
0
TIM Status and Control
Register (TSC)
TOIE
TSTOP
PS1
0
PS0
0
0
0
1
0
0
0
TIM DMA Select Register
(TDMA)
DMA3S DMA2S DMA1S DMA0S
0
0
14
0
13
0
12
0
11
0
10
0
9
0
Bit 8
Read: Bit 15
Write:
TIM Counter Register
High (TCNTH)
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
Read: Bit 7
Write:
TIM Counter Register Low
(TCNTL
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
Bit 15
1
0
0
13
1
0
12
1
0
0
0
0
Bit 8
1
TIM Counter Modulo Reg.
High (TMODH)
14
11
10
9
1
1
1
1
TIM Counter Modulo Reg.
Low (TMODL)
Bit 7
1
6
1
5
4
3
2
1
Bit 0
1
1
1
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
Read: CH0F
TIM Channel 0 Status and
Control Register (TSC0)
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
TIM Channel 0 Register
High (TCH0H)
Bit 15
14
13
12
11
10
9
Bit 8
Indeterminate after Reset
TIM Channel 0 Register
Low (TCH0L)
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after Reset
Read: CH1F
0
0
TIM Channel 1 Status and
Control Register (TSC1)
CH1IE
0
MS1A
0
ELS1B
0
ELS1A
0
TOV1
0
CH1MAX
0
Write:
Reset:
0
0
= Unimplemented
R = Reserved
Figure 2. I/O Register Summary (Continued)
7-mem_a
MC68HC708XL36
27
MOTOROLA
Memory Map
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Me m ory Ma p
Register Name
Addr.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
TIM Channel 1 Register
High (TCH1H)
Bit 15
14
13
12
11
10
9
Bit 8
$002A
Indeterminate after Reset
TIM Channel 1 Register
Low (TCH1L)
Bit 7
6
5
4
3
2
1
Bit 0
$002B
$002C
$002D
$002E
$002F
$0030
$0031
Indeterminate after Reset
Read: CH2F
TIM Channel 2 Status and
Control Register (TSC2)
CH2IE
0
MS2B
0
MS2A
0
ELS2B
ELS2A
TOV2
CH2MAX
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
0
9
0
TIM Channel 2 Register
High (TCH2H)
Bit 15
14
13
12
11
10
Bit 8
Indeterminate after Reset
TIM Channel 2 Register
Low (TCH2L)
Bit 7
6
5
0
4
3
2
1
Bit 0
Indeterminate after Reset
Read: CH3F
TIM Channel 3 Status and
Control Register (TSC3)
CH3IE
0
MS3A
0
ELS3B
ELS3A
TOV3
CH3MAX
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
0
0
9
0
TIM Channel 3 Register
High (TCH3H)
Bit 15
14
13
12
11
10
Bit 8
Indeterminate after Reset
TIM Channel 3 Register
Low (TCH3L)
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after Reset
IRQF1
Read: IRQF2
Write:
Reset:
0
ACK2
0
0
ACK1
0
IRQ Status and Control
Register (ISCR)
IMASK2 MODE2
IMASK1 MODE1
$0032
$0033
0
0
0
0
0
0
Reserved
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
DMA Channel 0 Source
Address Register High) $0034
(D0SH)
AD15
AD7
AD14
AD6
AD13
AD5
AD12
AD11
AD10
AD2
AD9
AD1
AD9
AD1
AD8
AD0
AD8
AD0
Indeterminate after Reset
AD4 AD3
Indeterminate after Reset
AD12 AD11
Indeterminate after Reset
AD4 AD3
DMA Channel 0 Source
Address Register Low $0035
(D0SL)
DMA Channel 0
Destination Address $0036
Register High (D0DH)
AD15
AD7
AD14
AD6
AD13
AD5
AD10
AD2
DMA Channel 0
Destination Address $0037
Register Low (D0DL)
Indeterminate after Reset
R = Reserved
= Unimplemented
Figure 2. I/O Register Summary (Continued)
8-mem_a
MC68HC708XL36
28
Memory Map
MOTOROLA
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Memory Map
Input/Output (I/O) Section
Register Name
Addr.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
DMA Channel 0 Control
Register (D0C)
SDC3
SDC2
SDC1
SDC0
BWC
DTS2
DTS1
DTS0
$0038
Indeterminate after Reset
BL4 BL3
DMA Channel 0 Block
Length Register (D0BL)
BL7
BL6
BL5
BL2
BL1
BL0
$0039
$003A
Indeterminate after Reset
Reserved
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
DMA Channel 0 Byte
Count Register (D0BC)
BC7
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
0
BC1
0
BC0
0
$003B
DMA Channel 1 Source
Address Register High) $003C
(D1SH)
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
Indeterminate after Reset
AD4 AD3
Indeterminate after Reset
AD12 AD11
Indeterminate after Reset
AD4 AD3
Indeterminate after Reset
SDC0 BWC
Indeterminate after Reset
BL4 BL3
DMA Channel 1 Source
Address Register Low $003D
(D1SL)
AD7
AD15
AD7
AD6
AD14
AD6
AD5
AD13
AD5
AD2
AD10
AD2
AD1
AD9
AD1
DTS1
BL1
AD0
AD8
AD0
DTS0
BL0
DMA Channel 1
Destination Address $003E
Register High (D1DH)
DMA Channel 1
Destination Address $003F
Register Low (D1DL)
DMA Channel 1 Control
$0040
SDC3
BL7
SDC2
BL6
SDC1
BL5
DTS2
BL2
Register (D1C)
DMA Channel 1 Block
$0041
Length Register (D1BL)
Indeterminate after Reset
Reserved
$0042
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
DMA Channel 1 Byte
$0043
BC7
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
0
BC1
0
BC0
0
Count Register (D1BC)
DMA Channel 2 Source
Address Register High) $0044
(D2SH)
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
Indeterminate after Reset
AD4 AD3
DMA Channel 2 Source
Address Register Low $0045
(D2SL)
AD7
AD6
AD5
AD2
AD1
AD0
Indeterminate after Reset
R = Reserved
= Unimplemented
Figure 2. I/O Register Summary (Continued)
9-mem_a
MC68HC708XL36
29
MOTOROLA
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Me m ory Ma p
Register Name
Addr.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
DMA Channel 2
Destination Address $0046
Register High (D2DH)
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
Indeterminate after Reset
AD4 AD3
Indeterminate after Reset
SDC0 BWC
Indeterminate after Reset
BL4 BL3
DMA Channel 2
Destination Address $0047
Register Low (D2DL)
AD7
SDC3
BL7
AD6
SDC2
BL6
AD5
SDC1
BL5
AD2
DTS2
BL2
AD1
DTS1
BL1
AD0
DTS0
BL0
DMA Channel 2 Control
$0048
Register (D2C)
DMA Channel 2 Block
$0049
Length Register (D2BL)
Indeterminate after Reset
Reserved
$004A
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
DMA Channel 2 Byte
$004B
BC7
0
BC6
0
BC5
0
BC4
0
BC3
BC2
0
BC1
0
BC0
0
Count Register (D2BC)
0
TEC1
0
DMA Control Register 1
BB1
0
BB0
0
TEC2
0
IEC2
0
IEC1
0
TEC0
0
IEC0
0
$004C
(DC1)
DMAP
0
L2
L1
L0
DMAWE
0
IFC2
0
IFC1
0
IFC0
0
DMA Status and Control
$004D
Register (DSC)
0
0
0
DMA Control Register 2
SWI7
0
SWI6
0
SWI5
0
SWI4
0
SWI3
0
SWI2
0
SWI1
0
SWI0
0
$004E Write:
Reset:
(DC2)
$004F
Reserved
Read:
Write:
Reset:
Read: POR
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
BW
Clear BW
0
Break Status Register
(BSR)
R
R
R
R
R
R
0
R
0
$FE00
$FE01
$FE03
$FE04
PIN
COP
ILOP
ILAD
LVI
Reset Status Register
(RSR)
1
0
0
0
0
0
0
0
Break Flag Control
Register (BFCR)
BCFE
R
R
R
R
R
R
R
0
IF6
R
IF5
R
0
IF4
R
0
IF3
R
0
IF2
R
0
IF1
R
0
0
R
0
0
R
0
Interrupt Status Register 1
(INT1)
0
= Unimplemented
R = Reserved
Figure 2. I/O Register Summary (Continued)
10-mem_a
MC68HC708XL36
30
Memory Map
MOTOROLA
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Memory Map
Input/Output (I/O) Section
Register Name
Addr.
Bit 7
Read: IF14
6
IF13
R
0
0
R
0
0
5
IF12
R
0
0
R
0
0
4
IF11
R
0
0
R
0
0
3
IF10
R
0
0
R
0
0
2
IF9
R
0
0
R
0
1
IF8
R
0
0
R
0
Bit 0
IF7
R
0
IF15
R
Interrupt Status Register 2
(INT2)
$FE05
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
R
0
0
R
0
Interrupt Status Register 3
(INT3)
$FE06
$FE07
$FE0C
$FE0D
$FE0E
$FE0F
0
0
EPROM Control Register
(EPMCR)
R
0
ELAT
EPGM
0
0
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
1
Break Address Register
High (BRKH)
Bit 15
0
14
Bit 8
0
0
Break Address Register
Low (BRKL)
Bit 7
0
6
0
5
4
3
2
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
Break Status and Control
Register (BSCR)
BRKE
0
Read: LVIOUT
Write:
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LVI Status Register
(LVISR)
Reset:
0
0
0
0
0
0
0
0
Read:
$FFFF Write:
Reset:
Low byte of reset vector
Writing clears COP counter
Unaffected by Reset
COP Control Register
(COPCTL)
= Unimplemented
R = Reserved
Figure 2. I/O Register Summary (Continued)
11-mem_a
MC68HC708XL36
31
MOTOROLA
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Me m ory Ma p
Table 1 is a list of vector locations.
Table 1. Vector Addresses
Address
$FFDE
$FFDF
$FFE0
$FFE1
$FFE2
$FFE3
$FFE4
$FFE5
$FFE6
$FFE7
$FFE8
$FFE9
$FFEA
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
Vector
Keyboard Vector (High)
Keyboard Vector (Low)
IRQ2 Vector (High)
IRQ2 Vector (Low)
SCI Transmit Vector (High)
SCI Transmit Vector (Low)
SCI Receive Vector (High)
SCI Receive Vector (Low)
SCI Error Vector (High)
SCI Error Vector (Low)
SPI Transmit Vector (High)
SPI Transmit Vector (Low)
SPI Receive Vector (High)
SPI Receive Vector (Low)
TIM Overflow Vector (High)
TIM Overflow Vector (Low)
TIM Channel 3 Vector (High)
TIM Channel 3 Vector (Low)
TIM Channel 2 Vector (High)
TIM Channel 2 Vector (Low)
TIM Channel 1 Vector (High)
TIM Channel 1 Vector (Low)
TIM Channel 0 Vector (High)
TIM Channel 0 Vector (Low)
DMA Vector (High)
DMA Vector (Low)
PLL Vector (High)
PLL Vector (Low)
IRQ1 Vector (High)
IRQ1 Vector (Low)
SWI Vector (High)
SWI Vector (Low)
Reset Vector (High)
Reset Vector (Low)
12-mem_a
MC68HC708XL36
32
Memory Map
MOTOROLA
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Ra nd om Ac c e ss Me m ory
RAM
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Introd uc tion
This section describes the 1024 bytes of RAM.
Func tiona l De sc rip tion
Addresses $0050 through $044F are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64-Kbyte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page 0 are 176 bytes of RAM. Because the location of the stack
RAM is programmable, all page 0 RAM locations can be used for I/O
control and user data or code. When the stack pointer is moved from its
reset location at $00FF, direct addressing mode instructions can access
efficiently all page 0 RAM locations. Page 0 RAM, therefore, provides
ideal locations for frequently accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
1-ram02_a
MC68HC708XL36
MOTOROLA
RAM
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RAM
NOTE: For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
2-ram02_a
MC68HC708XL36
34
RAM
MOTOROLA
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Nonvola tile Me m ory
EPROM
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
EPROM Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Introd uc tion
This section describes the 36 Kbytes of nonvolatile memory.
1-epm36k_b
MC68HC708XL36
MOTOROLA
EPROM
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EPROM
Func tiona l De sc rip tion
An MCU with a quartz window has 36 Kbytes of erasable, programmable
ROM (EPROM). The quartz window allows EPROM erasure by using
ultraviolet light. An unprogrammed or erased location reads as $00. The
following addresses are user EPROM locations:
•
•
$6E00–$FDFF
$FFE0–$FFFF — These locations are reserved for user-defined
interrupt and reset vectors.
Programming tools are available from Motorola. Contact your local
Motorola representative for more information.
1
NOTE: A security feature discourages viewing of the EPROM.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM difficult for unauthorized users.
2-epm36k_b
MC68HC708XL36
36
EPROM
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EPROM
EPROM Control Register
EPROM Control Re g iste r
The EPROM control register controls EPROM programming.
Address: $FE07
Bit 7
6
0
5
0
4
0
3
0
2
ELAT
0
1
0
Bit 0
EPGM
0
Read:
Write:
Reset:
R
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 1. EPROM Control Register (EPMCR)
ELAT — EPROM Latch Control Bit
This read/write bit latches the address and data buses for
programming the EPROM. Clearing ELAT also clears the EPGM bit.
EPROM data cannot be read when ELAT is set.
1 = Buses configured for EPROM programming
0 = Buses configured for normal operation
EPGM — EPROM Program Control Bit
This read/write bit applies the programming voltage from the
IRQ1/V pin to the EPROM. To write to the EPGM bit, the ELAT bit
PP
must be set already. The STOP instruction clears the EPGM bit.
Reset also clears EPGM.
1 = EPROM programming power switched on
0 = EPROM programming power switched off
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EPROM
EPROM Prog ra m m ing Se q ue nc e
Use the following procedure to program a byte of EPROM:
1. Apply V to the IRQ1/V pin.
PP
PP
2. Set the ELAT bit.
NOTE: Writing logic 1s to both the ELAT and EPGM bits with a single instruction
sets only the ELAT bit. EPGM must be set by a separate instruction in
the programming sequence.
3. Write to any user EPROM address.
NOTE: Writing to an invalid address prevents the programming voltage from
being applied.
4. Set the EPGM bit.
5. Wait for a time, t
.
epgm
6. Clear the ELAT and EPGM bits.
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Config ura tion Re g iste r
CONFIG
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Introd uc tion
The configuration register controls the following options:
•
•
•
•
•
•
•
Operation of low-voltage inhibit module (LVI) during stop mode
Resets caused by the LVI
Power to the LVI
Stop mode recovery time (32 or 4096 CGMXCLK cycles)
18
4
13
4
COP timeout period (2 – 2 or 2 – 2 CGMXCLK cycles)
STOP instruction
Operation of the computer operating properly module (COP)
Func tiona l De sc rip tion
The configuration register initializes certain MCU options and can be
written only once after each reset.
Address: $001F
Bit 7
6
5
4
3
2
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
COPRS LVISTOP LVIRSTD LVIPWRD SSREC
0
0
0
0
0
0
= Unimplemented
Figure 1. Configuration Register (CONFIG)
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CONFIG
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
13
4
1 = COP timeout period = 2 – 2 CGMXCLK cycles
18
4
0 = COP timeout period = 2 – 2 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
NOTE: If the LVIPWRD bit is at logic 0, the LVISTOP bit must be at logic 0 to
meet the minimum stop mode I specification.
DD
LVIRSTD — LVI Reset Disable Bit
When the LVIPWRD bit is clear, setting the LVIRSTD bit disables the
reset signal from the LVI module. Reset clears LVRSTD.
1 = LVI module reset disabled
0 = LVI module reset enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables LVI. Reset clears LVIPWRD.
1 = LVI power disabled
0 = LVI power enabled
SSREC — Short Stop Recovery Bit
SSREC shortens stop mode recovery time from 4096 CGMXCLK
cycles to 32 CGMXCLK cycles. Reset clears SSREC.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE: Do not set the SSREC bit if using an external crystal oscillator.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction. Reset clears STOP.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. Reset clears COPD.
1 = COP module disabled
0 = COP module enabled
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Ce ntra l Proc e ssor Unit
CPU
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Introd uc tion
The M68HC08 CPU is an enhanced and fully object-code-compatible
version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola
document number CPU08RM/AD) contains a description of the CPU
instruction set, addressing modes, and architecture.
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Fe a ture s
Features of the CPU include the following:
•
•
•
•
•
•
•
•
•
•
Object Code Fully Upward-Compatible with M68HC05 Family
16-Bit Stack Pointer with Stack Manipulation Instructions
16-Bit Index Register with X-Register Manipulation Instructions
8-MHz CPU Internal Bus Frequency
64-Kbyte Program/Data Memory Space
16 Addressing Modes
Memory-to-Memory Data Moves without Using Accumulator
Fast 8-Bit by 8-Bit Multiply and 16-Bit by 8-Bit Divide Instructions
Enhanced Binary-Coded Decimal (BCD) Data Handling
Modular Architecture with Expandable Internal Bus Definition for
Extension of Addressing Range beyond 64 Kbytes
•
Low-Power Stop and Wait Modes
CPU Re g iste rs
Figure 1 shows the five CPU registers. CPU registers are not part of the
memory map.
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CPU
CPU Registers
7
0
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
7
V 1
1
H
I
N Z C CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 1. CPU Registers
Ac c um ula tor
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by Reset
Figure 2. Accumulator (A)
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Ind e x Re g iste r
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
Bit
15
Bit
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 3. Index Register (H:X)
The index register can serve also as a temporary data storage location.
Sta c k Pointe r
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
15
Bit
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 4. Stack Pointer (SP)
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CPU Registers
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
Prog ra m Counte r
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15
Bit
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 5. Program Counter (PC)
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Cond ition Cod e
Re g iste r
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
V
6
1
1
5
1
1
4
3
I
2
1
Bit 0
C
Read:
Write:
Reset:
H
X
N
X
Z
X
X
1
X
X = Indeterminate
Figure 6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or
add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA
instruction uses the states of the H and C flags to determine the
appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
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CPU Registers
NOTE: To maintain M6805 compatibility, the upper byte of the index register (H)
is not stacked automatically. If the interrupt service routine modifies H,
then the user must stack and unstack H using the PSHH and PULH
instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can only be cleared by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Nonzero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
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Arithm e tic / Log ic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Motorola document number
CPU08RM/AD) for a description of the instructions and addressing
modes and more detail about the architecture of the CPU.
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
Wa it Mod e
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock.
Stop Mod e
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock.
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
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CPU During Break Interrupts
CPU During Bre a k Inte rrup ts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. (See Break Module on page 149.) The
program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor
mode).
If the break interrupt has been deasserted, a return-from-interrupt
instruction (RTI) in the break routine ends the break interrupt and returns
the MCU to normal operation.
Instruc tion Se t Sum m a ry
Table 1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
ADC #opr
IMM
DIR
EXT
IX2
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
2
3
4
4
3
2
4
5
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
↕ ↕ – ↕ ↕ ↕
IX1
IX
SP1
SP2
F9
ADC opr,SP
ADC opr,SP
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
IMM
DIR
EXT
IX2
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
2
3
4
4
3
2
4
5
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry
A ← (A) + (M)
↕ ↕ – ↕ ↕ ↕
IX1
IX
SP1
SP2
FB
9EEB ff
9EDB ee ff
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7 ii
AF ii
2
2
AND #opr
AND opr
IMM
DIR
EXT
IX2
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
2
3
4
4
3
2
4
5
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
Logical AND
A ← (A) & (M)
0
–
–
↕ ↕ –
IX1
IX
F4
SP1
SP2
9EE4 ff
9ED4 ee ff
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Table 1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
ASL opr
DIR
INH
INH
IX1
IX
38 dd
48
4
1
1
4
3
5
ASLA
ASLX
Arithmetic Shift Left
58
↕ –
↕ –
–
↕ ↕ ↕
↕ ↕ ↕
C
0
ASL opr,X
ASL ,X
(Same as LSL)
68 ff
78
9E68 ff
b7
b0
ASL opr,SP
SP1
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
INH
IX1
IX
37 dd
47
4
1
1
4
3
5
57
C
Arithmetic Shift Right
–
–
67 ff
77
b7
b0
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
–
–
–
– REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
BCS rel
BEQ rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25 rr
27 rr
3
3
Branch if Greater Than or Equal To
(Signed Operands)
BGE opr
BGT opr
PC ← (PC) + 2 + rel ? (N V) = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
90 rr
92 rr
3
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N V) = 0
3
3
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
28 rr
29 rr
22 rr
3
3
3
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
– REL
24 rr
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
2F rr
2E rr
3
3
BIT #opr
BIT opr
IMM
DIR
EXT
IX2
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
2
3
4
4
3
2
4
5
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
(A) & (M)
0
–
–
↕ ↕ –
IX1
IX
F5
SP1
SP2
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal To
(Signed Operands)
BLE opr
PC ← (PC) + 2 + rel ? (Z) | (N V) = 1
–
–
–
–
–
– REL
93 rr
3
BLO rel
BLS rel
BLT opr
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Less Than (Signed Operands)
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
PC ← (PC) + 2 + rel ? (N V) =1
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
25 rr
23 rr
91 rr
2C rr
2B rr
2D rr
26 rr
2A rr
3
3
3
3
3
3
3
3
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
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Instruction Set Summary
Table 1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
BRA rel
Branch Always
PC ← (PC) + 2 + rel
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
20 rr
3
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 2
↕
BRN rel
Branch Never
– REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
↕
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
4
4
4
4
4
4
4
4
BSET n,opr
BSR rel
Set Bit n in M
Mn ← 1
–
–
–
–
–
–
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to Subroutine
–
–
–
–
–
–
–
–
–
–
– REL
AD rr
4
PC ← (PC) + rel
CBEQ opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
31 dd rr
41 ii rr
51 ii rr
61 ff rr
71 rr
5
4
4
5
4
6
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
IMM
IMM
Compare and Branch if Equal
–
IX1+
IX+
CBEQ opr,SP,rel
SP1
9E61 ff rr
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
0
–
–
–
–
0 INH
– INH
98
9A
1
2
Clear Interrupt Mask
CLR opr
CLRA
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
3F dd
4F
3
1
1
1
3
2
4
CLRX
INH
5F
CLRH
Clear
0
–
–
0
1
– INH
IX1
IX
SP1
8C
CLR opr,X
CLR ,X
6F ff
7F
CLR opr,SP
9E6F ff
CMP #opr
CMP opr
IMM
DIR
EXT
IX2
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
2
3
4
4
3
2
4
5
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Compare A with M
(A) – (M)
↕ –
–
–
↕ ↕ ↕
IX1
IX
F1
SP1
SP2
9EE1 ff
9ED1 ee ff
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33 dd
43
4
1
1
4
3
5
53
Complement (One’s Complement)
0
–
↕ ↕ 1
63 ff
73
SP1
9E63 ff
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Table 1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
CPHX #opr
CPHX opr
IMM
DIR
65 ii ii+1
75 dd
3
4
Compare H:X with M
(H:X) – (M:M + 1)
↕ –
↕ –
–
–
↕ ↕ ↕
↕ ↕ ↕
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
2
3
4
4
3
2
4
5
Compare X with M
(X) – (M)
F3
9EE3 ff
9ED3 ee ff
DAA
Decimal Adjust A
(A)
U
–
–
–
–
–
↕ ↕ ↕ INH
72
2
10
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DIR
INH
3B dd rr
4B rr
Decrement and Branch if Not Zero
–
–
– INH
IX1
5B rr
6B ff rr
7B rr
IX
SP1
9E6B ff rr
DEC opr
DECA
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
3A dd
4A
4
1
1
4
3
5
DECX
5A
Decrement
Divide
↕ –
–
–
↕ ↕ –
DEC opr,X
DEC ,X
DEC opr,SP
IX1
IX
6A ff
7A
9E6A ff
SP1
A ← (H:A)/(X)
H ← Remainder
DIV
–
0
–
–
–
↕ ↕ INH
52
7
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
2
3
4
4
3
2
4
5
Exclusive OR M with A
A ← (A
M)
–
–
↕ ↕ –
F8
9EE8 ff
9ED8 ee ff
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C dd
4C
4
1
1
4
3
5
5C
Increment
↕ –
↕ ↕ –
6C ff
7C
SP1
9E6C ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
BC dd
CC hh ll
DC ee ff
EC ff
2
3
4
3
2
EXT
Jump
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
– IX2
IX1
IX
FC
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
– IX2
IX1
BD dd
CD hh ll
DD ee ff
ED ff
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
Jump to Subroutine
IX
FD
LDA #opr
LDA opr
IMM
DIR
EXT
IX2
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
2
3
4
4
3
2
4
5
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
Load A from M
A ← (M)
0
0
–
–
–
–
↕ ↕ –
↕ ↕ –
IX1
IX
F6
SP1
SP2
9EE6 ff
9ED6 ee ff
LDHX #opr
LDHX opr
IMM
DIR
45 ii jj
55 dd
3
4
Load H:X from M
H:X ← (M:M + 1)
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Instruction Set Summary
Table 1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
LDX #opr
IMM
DIR
EXT
IX2
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
2
3
4
4
3
2
4
5
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
Load X from M
X ← (M)
0
–
–
↕ ↕ –
IX1
IX
SP1
SP2
FE
LDX opr,SP
LDX opr,SP
9EEE ff
9EDE ee ff
LSL opr
LSLA
DIR
INH
INH
IX1
IX
38 dd
48
4
1
1
4
3
5
LSLX
Logical Shift Left
(Same as ASL)
58
C
0
↕ –
↕ –
–
–
↕ ↕ ↕
LSL opr,X
LSL ,X
LSL opr,SP
68 ff
78
9E68 ff
b7
b0
b0
SP1
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
DIR
INH
INH
IX1
IX
34 dd
44
4
1
1
4
3
5
54
0
C
Logical Shift Right
0 ↕ ↕
64 ff
74
b7
SP1
9E64 ff
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E dd dd
5E dd
5
4
4
4
(M)
← (M)
Source
Destination
DIX+
IMD
IX+D
Move
0
–
–
0
–
–
↕ ↕ –
6E ii dd
7E dd
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
MUL
Unsigned multiply
–
–
0 INH
42
5
NEG opr
NEGA
DIR
INH
INH
30 dd
40
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
NEGX
50
Negate (Two’s Complement)
↕ –
–
↕ ↕ ↕
NEG opr,X
NEG ,X
NEG opr,SP
IX1
IX
60 ff
70
9E60 ff
SP1
NOP
NSA
No Operation
Nibble Swap A
None
–
–
–
–
–
–
–
–
–
–
– INH
– INH
9D
62
1
3
A ← (A[3:0]:A[7:4])
ORA #opr
ORA opr
IMM
DIR
EXT
IX2
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
2
3
4
4
3
2
4
5
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
A ← (A) | (M)
0
–
–
↕ ↕ –
IX1
IX
FA
SP1
SP2
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
PULA
PULH
PULX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Pull H from Stack
Pull X from Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
– INH
– INH
– INH
87
8B
89
86
8A
88
2
2
2
2
2
2
ROL opr
ROLA
DIR
INH
INH
39 dd
49
4
1
1
4
3
5
ROLX
59
C
Rotate Left through Carry
↕ –
–
↕ ↕ ↕
ROL opr,X
ROL ,X
ROL opr,SP
IX1
IX
69 ff
79
9E69 ff
b7
b0
SP1
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Table 1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
ROR opr
DIR
INH
INH
IX1
IX
36 dd
46
4
1
1
4
3
5
RORA
RORX
56
C
Rotate Right through Carry
↕ –
–
–
↕ ↕ ↕
ROR opr,X
ROR ,X
66 ff
76
9E66 ff
b7
b0
ROR opr,SP
SP1
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
– INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕ ↕ ↕ ↕ ↕ ↕ INH
80
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
Subtract with Carry
–
–
–
–
–
–
– INH
81
4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
2
3
4
4
3
2
4
5
A ← (A) – (M) – (C)
↕ –
↕ ↕ ↕
F2
9EE2 ff
9ED2 ee ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
–
–
–
–
–
1
–
–
–
–
1 INH
– INH
99
9B
1
2
Set Interrupt Mask
STA opr
DIR
EXT
IX2
B7 dd
C7 hh ll
D7 ee ff
E7 ff
3
4
4
3
2
4
5
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
↕ ↕ – IX1
IX
SP1
SP2
F7
9EE7 ff
9ED7 ee ff
STHX opr
STOP
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
–
0
↕ ↕ – DIR
35 dd
8E
4
1
Enable IRQ Pin; Stop Oscillator
I ← 0; Stop Oscillator
–
–
– INH
STX opr
DIR
EXT
IX2
BF dd
CF hh ll
DF ee ff
EF ff
3
4
4
3
2
4
5
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
–
↕ ↕ – IX1
IX
SP1
SP2
FF
9EEF ff
9EDF ee ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
2
3
4
4
3
2
4
5
IX2
↕ ↕ ↕
IX1
Subtract
A ← (A) – (M)
↕ –
IX
SP1
SP2
F0
9EE0 ff
9ED0 ee ff
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
↕ ↕ ↕ ↕ ↕ ↕ INH
– INH
84
97
2
1
–
– – – –
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Opcode Map
Table 1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
TPA
Transfer CCR to A
A ← (CCR)
–
–
–
–
–
–
– INH
85
1
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
DIR
INH
INH
IX1
IX
SP1
3D dd
4D
3
1
1
3
2
4
5D
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
↕ ↕ –
6D ff
7D
9E6D ff
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
(SP) ← (H:X) – 1
A
C
Accumulator
Carry/borrow bit
n
Any bit
opr Operand (one or two bytes)
PC Program counter
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DD Direct to direct addressing mode
DIR Direct addressing mode
rel
rr
Relative program counter offset byte
Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP Stack pointer
U
V
X
Z
&
|
ff
H
H
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
hh ll High and low bytes of operand address in extended addressing
I
Interrupt mask
ii
Immediate operand byte
IMD Immediate source to direct destination addressing mode
IMM Immediate addressing mode
INH Inherent addressing mode
( )
IX
Indexed, no offset addressing mode
–( ) Negation (two’s complement)
IX+
Indexed, no offset, post increment addressing mode
#
Immediate value
Sign extend
Loaded with
If
IX+D Indexed with post increment to direct addressing mode
IX1 Indexed, 8-bit offset addressing mode
IX1+ Indexed, 8-bit offset, post increment addressing mode
«
←
?
IX2
M
N
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
:
↕
—
Concatenated with
Set or cleared
Not affected
Op c od e Ma p
Table 2 on page 56 is the opcode map for the MC68HC708XL36.
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Re se ts a nd Inte rrup ts
Re se ts a nd Inte rrup ts
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
COP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Low-Voltage Inhibit Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
IRQ1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
CGM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
IRQ2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
KB0–KB7 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
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Re se ts a nd Inte rrup ts
Introd uc tion
Resets and interrupts are responses to exceptional events during
program execution. A reset reinitializes the MCU to its startup condition.
An interrupt vectors the program counter to a service routine.
Re se ts
A reset returns the MCU to a known startup condition and begins
program execution from a user-defined memory location.
Effe c ts
A reset:
•
•
•
Immediately stops the operation of the instruction being executed.
Initializes certain control and status bits.
Loads the program counter with a user-defined reset vector
address from locations $FFFE and $FFFF.
•
Selects CGMXCLK divided by four as the bus clock.
Exte rna l Re se t
Inte rna l Re se t
A logic 0 applied to the RST pin for a time, t , generates an external
reset. An external reset sets the PIN bit in the reset status register.
IRL
Sources:
•
•
•
•
•
Power-on reset
COP
Low-voltage inhibit
Illegal opcode
Illegal address
All internal reset sources pull the RST pin low for 32 CGMXCLK cycles
to allow resetting of external devices. The MCU is held in reset for an
additional 32 CGMXCLK cycles after releasing the RST pin.
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Resets and Interrupts
Resets
PULLED LOW BY MCU
RST PIN
32 CYCLES
32 CYCLES
CGMXCLK
INTERNAL
RESET
Figure 1. Internal Reset Timing
Po we r-On Re se t
A power-on reset (POR) is an internal reset caused by a positive
transition on the V pin. A power-on reset:
DD
•
Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles.
•
•
Drives the RST pin low during the oscillator stabilization delay.
Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay.
•
•
Releases the CPU to begin the reset vector sequence 64
CGMXCLK cycles after the oscillator stabilization delay.
Sets the POR bit in the reset status register and clears all other
bits in the register.
OSC1
(1)
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST PIN
INTERNAL
RESET
1. PORRST is an internally generated power-on reset pulse.
Figure 2. Power-On Reset Recovery
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Re se ts a nd Inte rrup ts
COP Re se t
A COP reset is an internal reset caused by an overflow of the COP
counter. A COP reset sets the COP bit in the reset status register.
To clear the COP counter and prevent a COP reset, write any value to
the COP control register at location $FFFF.
Lo w-Vo lta g e
Inhib it Re se t
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI
voltage. An LVI reset:
tripf
•
Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to the LVI voltage.
tripr
•
•
•
•
Drives the RST pin low for as long as V is below the LVI
voltage and during the oscillator stabilization delay.
DD
tripr
Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay.
Releases the CPU to begin the reset vector sequence 64
CGMXCLK cycles after the oscillator stabilization delay.
Sets the LVI bit in the reset status register.
Ille g a l Op c o d e
Re se t
An illegal opcode reset is an internal reset caused by an opcode that is
not in the instruction set. An illegal opcode reset sets the ILOP bit in the
reset status register.
If the stop enable bit, STOP, in the configuration register is logic 0, the
STOP instruction causes an illegal opcode reset.
Ille g a l Ad d re ss
Re se t
An illegal address reset is an internal reset caused by an opcode fetch
from an unmapped address. An illegal address reset sets the ILAD bit in
the reset status register.
A data fetch from an unmapped address does not generate a reset.
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Resets and Interrupts
Resets
Re se t Sta tus
Re g iste r
This read-only register contains six flags that show the source of the last
reset. Clear the reset status register by reading it. A power-on reset sets
the POR bit and clears all other bits in the register.
NOTE: A reset source that becomes active before recovery from a previous
reset can prevent the previous reset from setting its reset status bit.
Address: $FE01
Bit 7
POR
6
5
4
3
2
0
1
Bit 0
0
Read:
Write:
POR:
PIN
COP
ILOP
ILAD
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 3. Reset Status Register (RSR)
POR — Power-On Reset Bit
1 = Last reset caused by power-on
0 = Read of RSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of RSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by timeout of COP counter
0 = POR or read of RSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of RSR
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of RSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low power supply voltage
0 = POR or read of RSR
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Re se ts a nd Inte rrup ts
Inte rrup ts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. An interrupt does not stop the operation of
the instruction being executed, but begins when the current instruction
completes its operation.
Effe c ts
An interrupt:
•
Saves the CPU registers on the stack. At the end of the interrupt,
the RTI instruction recovers the CPU registers from the stack so
that normal processing can resume.
•
•
•
CONDITION CODE REGISTER
ACCUMULATOR
5
4
3
2
1
1
2
3
4
5
STACKING
ORDER
INDEX REGISTER (LOW BYTE)*
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
UNSTACKING
ORDER
•
•
•
$00FF DEFAULT ADDRESS ON RESET
*High byte of index register is not stacked.
Figure 4. Interrupt Stacking Order
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Resets and Interrupts
Interrupts
•
•
Sets the interrupt mask (I bit) to prevent additional interrupts.
Once an interrupt is latched, no other interrupt can take
precedence, regardless of its priority.
Loads the program counter with a user-defined vector address.
After every instruction, the CPU checks all pending interrupts if the I bit
is not set. If more than one interrupt is pending when an instruction is
done, the highest priority interrupt is serviced first. If an interrupt is
pending upon exit from the interrupt service routine, the pending
interrupt is serviced before the LDA instruction is executed.
CLI
LDA #$FF
BACKGROUND
ROUTINE
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 5. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE: To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, save the
H register and then restore it prior to exiting the routine.
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Re se ts a nd Inte rrup ts
FROM RESET
YES
BREAK INTERRUPT?
NO
YES
I BIT SET?
NO
IRQ1
YES
YES
INTERRUPT?
NO
CGM
INTERRUPT?
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
ALL OTHER HARDWARE
INTERRUPTS ON CHIP
FETCH NEXT
INSTRUCTION.
SWI
YES
YES
INSTRUCTION?
NO
RTI
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
INSTRUCTION?
NO
Figure 6. Interrupt Processing
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Resets and Interrupts
Interrupts
Sourc e s
The following sources can generate CPU interrupt requests:
Table 1. Interrupt Sources
SWI Instruction
IRQ1 Pin
None
None
None
IF1
0
1
2
$FFFC–$FFFD
$FFFA–$FFFB
$FFF8–$FFF9
IRQ1F IMASK1
CGM
PLLF
IFC0
IFC1
IFC2
CH0F
CH1F
CH2F
CH3F
TOF
PLLIE
IEC0
IF2
DMA Channel 0
DMA Channel 1
DMA Channel 2
TIM Channel 0
TIM Channel 1
TIM Channel 2
TIM Channel 3
TIM Overflow
IEC1
IF3
3
$FFF6–$FFF7
IEC2
CH0IE
CH1IE
CH2IE
CH3IE
TOIE
IF4
IF5
IF6
IF7
IF8
4
5
6
7
8
$FFF4–$FFF5
$FFF2–$FFF3
$FFF0–$FFF1
$FFEE–$FFEF
$FFEC–$FFED
SPI Receiver Full
SPI Overflow
SPRF
OVRF
MODF
SPTE
OR
SPRIE
ERRIE
ERRIE
SPTIE
ORIE
NEIE
IF9
9
$FFEA–$FFEB
$FFE8–$FFE9
SPI Mode Fault
SPI Transmitter Empty
SCI Receiver Overrun
SCI Noise Flag
SCI Framing Error
SCI Parity Error
SCI Receiver Full
SCI Input Idle
IF10
10
NF
IF11
11
$FFE6–$FFE7
FE
FEIE
PE
PEIE
SCRF
IDLE
SCTE
TC
SCRIE
ILIE
IF12
IF13
12
13
$FFE4–$FFE5
$FFE2–$FFE3
SCI Transmitter Empty
SCI Transmission Complete
IRQ2 Pin
SCTIE
TCIE
IRQ2F IMASK2 IF14
KEYF IMASKK IF15
14
15
$FFE0–$FFE1
$FFDE–$FFDF
Keyboard Pin
1. The I bit in the condition code register is a global mask for all interrupt sources except the
SWI instruction.
2. 0 = highest priority
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Re se ts a nd Inte rrup ts
SWI Instruc tio n
The software interrupt instruction (SWI) causes a nonmaskable
interrupt.
NOTE: A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
Bre a k Inte rrup t
The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.
IRQ1 Pin
CGM
A logic 0 on the IRQ1 pin latches an external interrupt request.
The CGM can generate a CPU interrupt request every time the
phase-locked loop circuit (PLL) enters or leaves the locked state. When
the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the
PLL bandwidth control register. PLLF is in the PLL control register.
DMA
The DMA module can generate a CPU interrupt request when a channel
x CPU interrupt flag (IFCx) becomes set.
•
IFCx is set at the end of a DMA block transfer. The channel x CPU
interrupt enable bit, IECx, enables DMA channel x CPU interrupt
requests.
•
IFCx is set at the end of a DMA transfer loop. The channel x CPU
interrupt enable bit, IECx, enables DMA channel x CPU interrupt
requests.
The IFCx bit is the DMA status and control register. The IECx bit is in
DMA control register 1.
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Resets and Interrupts
Interrupts
TIM
TIM CPU interrupt sources:
•
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
TIM channel flags (CH3F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. The channel
x interrupt enable bit, CHxIE, enables channel x TIM CPU
interrupt requests. CHxF and CHxIE are in the TIM channel x
status and control register.
SPI
SPI CPU interrupt sources:
•
•
•
SPI receiver full bit (SPRF) — The SPRF bit is set every time a
byte transfers from the shift register to the receive data register.
The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU
interrupt requests. SPRF is in the SPI status and control register
and SPRIE is in the SPI control register.
SPI transmitter empty (SPTE) — The SPTE bit is set every time a
byte transfers from the transmit data register to the shift register.
The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU
interrupt requests. SPTE is in the SPI status and control register
and SPTIE is in the SPI control register.
Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the
SS pin goes high during a transmission with the mode fault enable
bit (MODFEN) set. In a master SPI, the MODF bit is set if the SS
pin goes low at any time with the MODFEN bit set. The error
interrupt enable bit, ERRIE, enables MODF CPU interrupt
requests. MODF, MODFEN, and ERRIE are in the SPI status and
control register.
•
Overflow bit (OVRF) — The OVRF bit is set if software does not
read the byte in the receive data register before the next full byte
enters the shift register. The error interrupt enable bit, ERRIE,
enables OVRF CPU interrupt requests. OVRF and ERRIE are in
the SPI status and control register.
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Re se ts a nd Inte rrup ts
SCI
SCI CPU interrupt sources:
•
•
SCI transmitter empty bit (SCTE) — SCTE is set when the SCI
data register transfers a character to the transmit shift register.
The SCI transmit interrupt enable bit, SCTIE, enables transmitter
CPU interrupt requests. SCTE is in SCI status register 1. SCTIE is
in SCI control register 2.
Transmission complete bit (TC) — TC is set when the transmit
shift register and the SCI data register are empty and no break or
idle character has been generated. The transmission complete
interrupt enable bit, TCIE, enables transmitter CPU interrupt
requests. TC is in SCI status register 1. TCIE is in SCI control
register 2.
•
SCI receiver full bit (SCRF) — SCRF is set when the receive shift
register transfers a character to the SCI data register. The SCI
receive interrupt enable bit, SCRIE, enables receiver CPU
interrupts. SCRF is in SCI status register 1. SCRIE is in SCI
control register 2.
•
•
Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive logic
1s shift in from the RxD pin. The idle line interrupt enable bit, ILIE,
enables IDLE CPU interrupt requests. IDLE is in SCI status
register 1. ILIE is in SCI control register 2.
Receiver overrun bit (OR) — OR is set when the receive shift
register shifts in a new character before the previous character
was read from the SCI data register. The overrun interrupt enable
bit, ORIE, enables OR to generate SCI error CPU interrupt
requests. OR is in SCI status register 1. ORIE is in SCI control
register 3.
•
Noise flag (NF) — NF is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, enables NF to
generate SCI error CPU interrupt requests. NF is in SCI status
register 1. NEIE is in SCI control register 3.
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Resets and Interrupts
Interrupts
•
•
Framing error bit (FE) — FE is set when a logic 0 occurs where the
receiver expects a stop bit. The framing error interrupt enable bit,
FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.
Parity error bit (PE) — PE is set when the SCI detects a parity
error in incoming data. The parity error interrupt enable bit, PEIE,
enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.
IRQ2 Pin
A logic 0 on the IRQ2 pin latches an external interrupt request.
KB0–KB7 Pins
A logic 0 on a keyboard interrupt pin latches an external interrupt
request.
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Re se ts a nd Inte rrup ts
Inte rrup t Sta tus
Re g iste rs
The flags in the interrupt status registers identify maskable interrupt
sources. Table 2 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 2. Interrupt Source Flags
Interrupt Status
Interrupt Source
Register Flag
Reset
—
—
SWI Instruction
IRQ1 Pin
IF1
CGM
IF2
DMA
IF3
TIM Channel 0
TIM Channel 1
TIM Channel 2
TIM Channel 3
TIM Overflow
SPI Receiver
SPI Transmitter
SCI Error
IF4
IF5
IF6
IF7
IF8
IF9
IF10
IF11
IF12
IF13
IF14
IF15
SCI Receiver
SCI Transmitter
IRQ2 Pin
Keyboard Pin
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Resets and Interrupts
Interrupts
Inte rrup t Sta tus
Re g iste r 1
Address: $FE04
Bit 7
IF6
6
IF5
R
5
IF4
R
4
IF3
R
3
IF2
R
2
IF1
R
1
0
Bit 0
0
Read:
Write:
Reset:
R
R
0
R
0
0
0
0
0
0
0
R = Reserved
Figure 7. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 6–1
These flags indicate the presence of interrupt requests from the
sources shown in Table 2.
1 = Interrupt request present
0 = No interrupt request present
Bits 0–1 — Always read 0
Inte rrup t Sta tus
Re g iste r 2
Address: $FE05
Bit 7
6
IF13
R
5
IF12
R
4
IF11
R
3
IF10
R
2
IF9
R
1
IF8
R
Bit 0
IF7
R
Read:
Write:
Reset:
IF14
R
0
0
0
0
0
0
0
0
R = Reserved
Figure 8. Interrupt Status Register 2 (INT2)
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the
sources shown in Table 2.
1 = Interrupt request present
0 = No interrupt request present
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Re se ts a nd Inte rrup ts
Inte rrup t Sta tus
Re g iste r 3
Address: $FE06
Bit 7
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
IF15
R
Read:
0
Write:
Reset:
R
R
0
R
0
R
0
R
0
R
0
R
0
0
0
R = Reserved
Figure 9. Interrupt Status Register 3 (INT3)
Bits 7–1 — Always read 0
IF15 — Interrupt Flag 15
This flag indicates the presence of an interrupt request from the
source shown in Table 2.
1 = Interrupt request present
0 = No interrupt request present
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Low-Powe r Mod e s
Low-Powe r Mod e s
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Computer Operating Properly Module (COP) . . . . . . . . . . . . . . . . . . .76
Direct Memory Access Module (DMA) . . . . . . . . . . . . . . . . . . . . . . . .76
External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Keyboard Interrupt Module (KB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . .78
Serial Peripheral Interface Module (SPI). . . . . . . . . . . . . . . . . . . . . . .79
Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
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Low-Powe r Mod e s
Introd uc tion
The WAIT instruction puts the MCU in a low-power standby mode in
which the CPU clock is disabled but the bus clock continues to run. The
STOP instruction disables both the CPU clock and the bus clock.
Ce ntra l Proc e ssor Unit (CPU)
Wa it Mod e
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock.
Stop Mod e
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock.
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
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Clock Generator Module (CGM)
Cloc k Ge ne ra tor Mod ule (CGM)
Wa it Mod e
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
Stop Mod e
The STOP instruction disables the CGM and holds low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
Bre a k Mod ule (BRK)
Wa it Mod e
If enabled, the break module is active in wait mode. A DMA-generated
address that matches the break address registers in wait mode sets the
BSW in the break status register.
The DMA can also use the break status and control register as its
destination address in order to write to the BRKA and BRKE bits during
wait mode. A DMA write to the break status and control register sets the
BSW bit.
Stop Mod e
The break module is inactive in stop mode. The STOP instruction does
not affect break module register states.
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Low-Powe r Mod e s
Com p ute r Op e ra ting Prop e rly Mod ule (COP)
Wa it Mod e
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine
or a DMA service routine.
Stop Mod e
Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
The STOP bit in the configuration register (CONFIG) enables the STOP
instruction. To prevent inadvertently turning off the COP with a STOP
instruction, disable the STOP instruction by clearing the STOP bit.
Dire c t Me m ory Ac c e ss Mod ule (DMA)
Wa it Mod e
If enabled by the DMAWE bit in the DMA status and control register, the
DMA remains active in wait mode. The DMA can transfer data to and
from peripherals while the MCU remains in wait mode.
If the WAIT instruction occurs during a DMA transfer while DMAWE is
set, the DMA transfer continues to completion. If the DMAWE bit is clear,
a WAIT instruction suspends the current DMA transfer. If the DMA
priority bit (DMAP) is set, the suspended transfer resumes when the
MCU exits wait mode.
Stop Mod e
The DMA is inactive during stop mode. A STOP instruction suspends
any DMA transfer in progress. If an external interrupt brings the MCU out
of stop mode and the DMA priority bit (DMAP) is set, the suspended
DMA transfer resumes. If a reset brings the MCU out of stop mode, the
transfer is aborted.
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Low-Power Modes
External Interrupt Module (IRQ)
Entering stop mode when a DMA channel is enabled may fail to clear the
interrupt mask (I bit) in the condition code register. To make sure the I
bit is cleared when entering stop mode:
•
Before executing the STOP instruction, wait until any current DMA
transfer is complete. Then disable DMA transfers by clearing bits
TEC[2:0] in DMA control register 1.
Or,
•
Execute the clear-interrupt-mask instruction (CLI) before entering
stop mode.
Exte rna l Inte rrup t Mod ule (IRQ)
Wa it Mod e
The IRQ module remains active in wait mode. Clearing the IMASK1 or
IMASK2 bit in the IRQ status and control register enables IRQ1 or IRQ2
CPU interrupt requests to bring the MCU out of wait mode.
Stop Mod e
The IRQ module remains active in stop mode. Clearing the IMASK1 or
IMASK2 bit in the IRQ status and control register enables IRQ1 or IRQ2
CPU interrupt requests to bring the MCU out of stop mode.
Ke yb oa rd Inte rrup t Mod ule (KB)
Wa it Mod e
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
Stop Mod e
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
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Low-Powe r Mod e s
Low-Volta g e Inhib it Mod ule (LVI)
Wa it Mod e
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets, the LVI module can generate a reset and bring the
MCU out of wait mode.
Stop Mod e
If enabled, the LVI module remains active in stop mode. If enabled to
generate resets, the LVI module can generate a reset and bring the
MCU out of stop mode.
Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
Wa it Mod e
The SCI module remains active in wait mode. Any enabled CPU
interrupt request from the SCI module can bring the MCU out of wait
mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
The DMA can service the SCI without exiting wait mode.
Stop Mod e
The SCI module is inactive in stop mode. The STOP instruction does not
affect SCI register states. SCI module operation resumes after the MCU
exits stop mode.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
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Low-Power Modes
Serial Peripheral Interface Module (SPI)
Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
Wa it Mod e
The SPI module remains active in wait mode. Any enabled CPU interrupt
request from the SPI module can bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
The DMA can service the SPI without exiting wait mode.
Stop Mod e
The SPI module is inactive in stop mode. The STOP instruction does not
affect SPI register states. SPI operation resumes after an external
interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.
Tim e r Inte rfa c e Mod ule (TIM)
Wa it Mod e
The TIM remains active in wait mode. Any enabled CPU interrupt
request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
The DMA can service the TIM without exiting wait mode.
Stop Mod e
The TIM is inactive in stop mode. The STOP instruction does not affect
register states or the state of the TIM counter. TIM operation resumes
when the MCU exits stop mode after an external interrupt.
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Low-Powe r Mod e s
Exiting Wa it Mod e
The following events restart the CPU clock and load the program counter
with the reset vector or with an interrupt vector:
•
External reset — A logic 0 on the RST pin resets the MCU and
loads the program counter with the contents of locations $FFFE
and $FFFF.
•
External interrupt — A high-to-low transition on an external
interrupt pin loads the program counter with the contents of
locations:
– $FFFA and $FFFB (IRQ1 pin)
– $FFE0 and $FFE1 (IRQ2 pin)
•
•
Break interrupt — A break interrupt loads the program counter
with the contents of $FFFC and $FFFD.
Computer operating properly module (COP) reset — A timeout of
the COP counter resets the MCU and loads the program counter
with the contents of $FFFE and $FFFF.
•
•
•
Low-voltage inhibit module (LVI) reset — A power supply voltage
below the LVI
voltage resets the MCU and loads the program
tripf
counter with the contents of locations $FFFE and $FFFF.
Clock generator module (CGM) interrupt — A CPU interrupt
request from the phase-locked loop (PLL) loads the program
counter with the contents of $FFF8 and $FFF9.
Direct memory access module (DMA) interrupt — A CPU interrupt
request from the DMA loads the program counter with the
contents of $FFF6 and $FFF7.
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Low-Power Modes
Exiting Wait Mode
•
Timer interface module (TIM) interrupt — A CPU interrupt request
from the TIM loads the program counter with the contents of:
– $FFEC and $FFED (TIM overflow)
– $FFEE and $FFEF (TIM channel 3)
– $FFF0 and $FFF1 (TIM channel 2)
– $FFF2 and $FFF3 (TIM channel 1)
– $FFF4 and $FFF5 (TIM channel 0)
•
•
Serial peripheral interface module (SPI) interrupt — A CPU
interrupt request from the SPI loads the program counter with the
contents of:
– $FFE8 and $FFE9 (SPI transmitter)
– $FFEA and $FFEB (SPI receiver)
Serial communications interface module (SCI) interrupt — A CPU
interrupt request from the SCI loads the program counter with the
contents of:
– $FFE2 and $FFE3 (SCI transmitter)
– $FFE4 and $FFE5 (SCI receiver)
– $FFE6 and $FFE7 (SCI receiver error)
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Low-Powe r Mod e s
Exiting Stop Mod e
The following events restart the system clocks and load the program
counter with the reset vector or with an interrupt vector:
•
External reset — A logic 0 on the RST pin resets the MCU and
loads the program counter with the contents of locations $FFFE
and $FFFF.
•
External interrupt — A high-to-low transition on an external
interrupt pin loads the program counter with the contents of
locations:
– $FFFA and $FFFB (IRQ1 pin)
– $FFE0 and $FFE1 (IRQ2 pin)
– $FFDE and $FFDF (keyboard interrupt pins)
Low-voltage inhibit (LVI) reset — A power supply voltage below
•
•
the LVI
voltage resets the MCU and loads the program counter
tripf
with the contents of locations $FFFE and $FFFF.
Break interrupt — A break interrupt loads the program counter
with the contents of locations $FFFC and $FFFD.
Upon exit from stop mode, the system clocks begin running after an
oscillator stabilization delay. A 12-bit stop recovery counter inhibits the
system clocks for 4096 CGMXCLK cycles after the reset or external
interrupt.
The short stop recovery bit, SSREC, in the configuration register
controls the oscillator stabilization delay during stop recovery. Setting
SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32
CGMXCLK cycles.
NOTE: Use the full stop recovery time (SSREC = 0) in applications that use an
external crystal.
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Cloc k Ge ne ra tor Mod ule
CGM
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . .88
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . . . .90
Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . .90
Programming the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Special Programming Exceptions. . . . . . . . . . . . . . . . . . . . . . . .93
Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
CGM External Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . .96
Crystal Amplifier Output Pin (OSC2). . . . . . . . . . . . . . . . . . . . . . . .96
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . .96
Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . .96
Crystal Output Frequency Signal (CGMXCLK). . . . . . . . . . . . . . . .97
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . .97
CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
PLL Bandwidth Control Register (PBWC). . . . . . . . . . . . . . . . . . .100
PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . . . . . .102
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
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CGM
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . .106
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . .106
Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . .108
Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Introd uc tion
The CGM generates the crystal clock signal, CGMXCLK, which operates
at the frequency of the crystal. The CGM also generates the base clock
signal, CGMOUT, from which the system clocks are derived. CGMOUT
is based on either the crystal clock divided by two or the phase-locked
loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency
generator designed for use with 1-MHz to 16-MHz crystals or ceramic
resonators. The PLL can generate an 8-MHz bus frequency without
using a 32-MHz crystal.
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CGM
Features
Fe a ture s
Features of the CGM include the following:
•
•
Phase-Locked Loop with Output Frequency in Integer Multiples of
the Crystal Reference
Programmable Hardware Voltage-Controlled Oscillator (VCO) for
Low-Jitter Operation
•
•
•
Automatic Bandwidth Control Mode for Low-Jitter Operation
Automatic Frequency Lock Detector
CPU Interrupt on Entry or Exit from Locked Condition
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CGM
Func tiona l De sc rip tion
The CGM consists of three major submodules:
•
•
•
Crystal oscillator circuit — The crystal oscillator circuit generates
the constant crystal frequency clock, CGMXCLK.
Phase-locked loop (PLL) — The PLL generates the
programmable VCO frequency clock CGMVCLK.
Base clock selector circuit — This software-controlled circuit
selects either CGMXCLK divided by two or the VCO clock,
CGMVCLK, divided by two as the base clock, CGMOUT. The
system clocks are derived from CGMOUT.
Figure 1 shows the structure of the CGM.
Crysta l Osc illa tor
Circ uit
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal enables the crystal oscillator
circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components.
An externally generated clock also can feed the OSC1 pin of the crystal
oscillator circuit. Connect the external clock to the OSC1 pin and let the
OSC2 pin float.
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CGM
Functional Description
CRYSTAL OSCILLATOR
OSC2
STOP RECOVERY COUNTER,
COP PRESCALER,
CGMXCLK
RESET COUNTER,
SCI BAUD RATE GENERATOR
OSC1
SIMOSCEN
A
B
÷ 2
CGMOUT
CPU CLOCK,
BUS CLOCK
CLOCK
SELECT
CIRCUIT
÷ 2
S
WHEN S = 0, CGMOUT = B
CGMRDV
CGMRCLK
BCS
USER MODE
PC3 PIN
V
CGMXFC
V
SS
DDA
VRS[7:4]
MONITOR MODE
VOLTAGE
CONTROLLED
OSCILLATOR
PHASE
DETECTOR
LOOP
FILTER
PLL ANALOG
CGMINT
LOCK
DETECTOR
BANDWIDTH
CONTROL
INTERRUPT
CONTROL
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL[7:4]
CGMVDV
CGMVCLK
FREQUENCY
DIVIDER
Figure 1. CGM Block Diagram
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CGM
Register Name
Bit 7
PLLIE
0
6
5
PLLON
1
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
BCS
0
PLL Control Register (PCTL) Write:
Reset:
Read:
0
1
0
1
0
1
0
1
0
LOCK
AUTO
ACQ
XLD
PLL Bandwidth Control Register
Write:
(PBWC)
Reset:
Read:
PLL Programming Register (PPG) Write:
Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6
1
VRS5
1
VRS4
0
= Unimplemented
Figure 2. I/O Register Summary
Table 1. I/O Register Address Summary
Register:
Address:
PCTL
PBWC
$001D
PPG
$001C
$001E
Pha se -Loc ke d
Loop Circ uit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
Circ uits
The PLL consists of the following circuits:
•
•
•
•
•
Voltage-controlled oscillator (VCO)
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
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CGM
Functional Description
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f .
vrs
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f is equal to the nominal center-of-range
vrs
frequency, f
, (4.9152 MHz) times a linear factor L, or (L)f
.
nom
nom
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f , and is fed to the PLL through a
rclk
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency f = f
.
rclk
rdv
The VCO’s output clock, CGMVCLK, running at a frequency f , is fed
vclk
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency f
= f /N. (See
vclk
vdv
Programming the PLL on page 92 for more information.)
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the dc voltage on the external capacitor connected to
CGMXFC based on the width and direction of the correction pulse. The
filter can make fast or slow corrections depending on its mode,
described in Acquisition and Tracking Modes on page 90. The value
of the external capacitor and the reference frequency determines the
speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency f . The circuit determines the mode of the PLL and the lock
rdv
condition based on this comparison.
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Ac q uisitio n a nd
Tra c king Mo d e s
The PLL filter is manually or automatically configurable into one of two
operating modes:
•
Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth
control register. (See PLL Bandwidth Control Register (PBWC)
on page 100.)
•
Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See Base Clock Selector Circuit on page 94.) The PLL
is automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
Ma nua l a nd
Auto m a tic PLL
Ba nd wid th Mo d e s
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See PLL Bandwidth Control Register (PBWC) on page
100.) If PLL CPU interrupt requests are enabled, the software can wait
for a PLL CPU interrupt request and then check the LOCK bit. If CPU
interrupts are disabled, software can poll the LOCK bit continuously
(during PLL startup, usually) or at periodic intervals. In either case, when
the LOCK bit is set, the VCO clock is safe to use as the source for the
base clock. (See Base Clock Selector Circuit on page 94.) If the VCO
is selected as the source for the base clock and the LOCK bit is clear,
the PLL has suffered a severe noise hit and the software must take
appropriate action, depending on the application. (See Interrupts on
page 104.)
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CGM
Functional Description
The following conditions apply when the PLL is in automatic bandwidth
control mode:
•
The ACQ bit (see PLL Bandwidth Control Register (PBWC) on
page 100) is a read-only indicator of the mode of the filter. (See
Acquisition and Tracking Modes on page 90.)
•
The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆ , and is cleared when the VCO frequency is out of a
trk
certain tolerance, ∆ . (See Specifications on page 333.)
unt
•
•
The LOCK bit is a read-only indicator of the locked state of the
PLL.
The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆
, and is cleared when the VCO frequency is out of
Lock
a certain tolerance, ∆ . (See Specifications on page 333.)
unl
•
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See PLL Control
Register on page 98.)
The PLL also can operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below f
and
busmax
require fast startup. The following conditions apply when in manual
mode:
•
•
•
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
Before entering tracking mode (ACQ = 1), software must wait a
given time, t (see Specifications on page 333), after turning on
acq
the PLL by setting PLLON in the PLL control register (PCTL).
Software must wait a given time, t , after entering tracking mode
al
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
•
•
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
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CGM
Pro g ra m m ing the
PLL
Use the following procedure to program the PLL.
1. Choose the desired bus frequency, f
.
busdes
Example: f
= 8 MHz
busdes
2. Calculate the desired VCO frequency, f
.
vclkdes
= 4 × f
busdes
f
vclkdes
Example: f
= 4 × 8 MHz = 32 MHz
vclkdes
3. Using a reference frequency, f , equal to the crystal frequency,
rclk
calculate the VCO frequency multiplier, N.
NOTE: The round function means that the result is rounded to the nearest
integer.
fvclkdes
N = round
----------------
frclk
32 MHz
Example: N = -------------------- = 8
4 MHz
4. Calculate the VCO frequency, f
.
vclk
fvclk = N × frclk
= 8 × 4 MHz = 32 MHz
Example: f
vclk
5. Calculate the bus frequency, f , and compare f
with f
.
bus
bus
busdes
fvclk
fbus = ---------
4
32 MHz
Example: f bus= -------------------- = 8 MHz
4
If the calculated f
is not within the tolerance limits of your
bus
application, select another f
or another f
.
busdes
rclk
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CGM
Functional Description
6. Using the value 4.9152 MHz for f
, calculate the VCO linear
nom
range multiplier, L. The linear range multiplier controls the
frequency range of the PLL.
fvclk
L = round
----------
fnom
32 MHz
Example: L =
= 7
-------------------------------
4.9152 MHz
7. Calculate the VCO center-of-range frequency, f . The
vrs
center-of-range frequency is the midpoint between the minimum
and maximum frequencies attainable by the PLL.
f
= L × f
nom
vrs
Example: f = 7 × 4.9152 MHz = 34.4 MHz
vrs
NOTE: For proper operation,
fnom
-------------
2
f vrs – fvclk
≤
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
8. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG),
program the binary equivalent of L.
Sp e c ia l
Pro g ra m m ing
Exc e p tio ns
The programming method described in Programming the PLL on
page 92 does not account for two possible exceptions. A value of 0
for N or L is meaningless when used in the equations given. To
account for these exceptions:
•
•
A 0 value for N is interpreted the same as a value of 1.
A 0 value for L disables the PLL and prevents its selection as the
source for the base clock. (See Base Clock Selector Circuit on
page 94.)
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CGM
Ba se Cloc k
Se le c tor Circ uit
This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a
0. This value would set up a condition inconsistent with the operation of
the PLL, so that the PLL would be disabled and the crystal clock would
be forced as the source of the base clock.
CGM Exte rna l
Conne c tions
In its typical configuration, the CGM requires seven external
components. Five of these are for the crystal oscillator and two are for
the PLL.
The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in Figure 3. Figure 3 shows only the logical
representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
•
•
•
•
•
Crystal, X
1
Fixed capacitor, C
1
Tuning capacitor, C (can also be a fixed capacitor)
2
Feedback resistor, R
B
Series resistor, R (optional)
S
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CGM
Functional Description
The series resistor (R ) may not be required for all ranges of operation,
S
especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.
Figure 3 also shows the external components for the PLL:
•
•
Bypass capacitor, C
byp
Filter capacitor, C
F
Routing should be done with great care to minimize signal cross talk and
noise. (See Acquisition/Lock Time Specifications on page 106 for
routing information and more information on the filter capacitor’s value
and its effects on PLL performance.)
SIMOSCEN
CGMXCLK
V
DD
*
R
C
S
F
C
R
BYP
B
X
1
C
C
2
1
*R can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data.
S
Figure 3. CGM External Connections
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CGM
I/ O Sig na ls
The following paragraphs describe the CGM I/O signals.
The OSC1 pin is an input to the crystal oscillator amplifier.
Crysta l Am p lifie r
Inp ut Pin (OSC1)
Crysta l Am p lifie r
Outp ut Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
Exte rna l Filte r
Ca p a c itor Pin
(CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor is connected to this pin.
NOTE: To prevent noise problems, C should be placed as close to the
F
CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the C connection.
F
Ana log Powe r Pin
(V
V
V
is a power pin used by the analog portions of the PLL. Connect the
pin to the same voltage potential as the V pin.
DD
DDA
DDA
)
DDA
NOTE: Route V
carefully for maximum noise immunity and place bypass
DDA
capacitors as close as possible to the package.
Osc illa tor Ena b le
The SIMOSCEN signal enables the oscillator and PLL.
Sig na l (SIMOSCEN)
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CGM
I/O Signals
Crysta l Outp ut
Fre q ue nc y Sig na l
(CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f ) and comes directly from the crystal oscillator circuit.
xclk
Figure 3 shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
CGM Ba se Cloc k
Outp ut (CGMOUT)
CGMOUT is the clock output of the CGM. This signal is used to generate
the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice
the bus frequency. CGMOUT is software programmable to be either the
oscillator output, CGMXCLK, divided by two or the VCO clock,
CGMVCLK, divided by two.
CGM CPU Inte rrup t
(CGMINT)
CGMINT is the CPU interrupt signal generated by the PLL lock detector.
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CGM
CGM Re g iste rs
The following registers control and monitor operation of the CGM:
•
•
•
PLL control register (PCTL) (See PLL Control Register on page
98.)
PLL bandwidth control register (PBWC) (See PLL Bandwidth
Control Register (PBWC) on page 100.)
PLL programming register (PPG) (See PLL Programming
Register (PPG) on page 102.)
PLL Control
Re g iste r
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Address: $001C
Bit 7
PLLIE
0
6
5
PLLON
1
4
BCS
0
3
1
2
1
1
1
Bit 0
1
Read:
Write:
Reset:
PLLF
0
1
1
1
1
= Unimplemented
Figure 4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate a CPU interrupt
request when the LOCK bit toggles, setting the PLL flag, PLLF. When
the AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
1 = PLL CPU interrupt requests enabled
0 = PLL CPU interrupt requests disabled
PLLF — PLL Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates a CPU interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
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CGM
CGM Registers
NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). (See Base Clock Selector Circuit
on page 94.) Reset sets this bit so that the loop can stabilize as the
MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. (See Base
Clock Selector Circuit on page 94.) Reset and the STOP instruction
clear the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE: PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. (See Base Clock Selector Circuit on page 94.)
PCTL[3:0] — Unimplemented bits
These bits provide no function and always read as logic 1s.
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CGM
PLL Ba nd wid th
Control Re g iste r
(PBWC)
The PLL bandwidth control register does the following:
•
Selects automatic or manual (software-controlled) bandwidth
control mode
•
•
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
•
In manual operation, forces the PLL into acquisition or tracking
mode
Address: $001D
Bit 7
6
5
ACQ
0
4
XLD
0
3
0
2
0
1
0
Bit 0
0
Read:
AUTO
Write:
LOCK
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
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CGM
CGM Registers
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
XLD — Crystal Loss Detect Bit
When the VCO output, CGMVCLK, is driving CGMOUT, this
read/write bit can indicate whether the crystal reference frequency is
active or not.
1 = Crystal reference not active
0 = Crystal reference active
To check the status of the crystal reference, do the following:
1.
2.
3.
Write a logic 1 to XLD.
Wait N × 4 cycles. (N is the VCO frequency multiplier.)
Read XLD.
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as logic 0.
PBWC[3:0] — Reserved for Test
These bits enable test functions not available in user mode. To
ensure software portability from development systems to user
applications, software should write 0s to PBWC[3:0] whenever writing
to PBWC.
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PLL Prog ra m m ing
Re g iste r (PPG)
The PLL programming register contains the programming information
for the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
Address: $001E
Bit 7
MUL7
0
6
MUL6
1
5
MUL5
1
4
MUL4
0
3
VRS7
0
2
VRS6
1
1
VRS5
1
Bit 0
VRS4
0
Read:
Write:
Reset:
Figure 6. PLL Programming Register (PPG)
MUL[7:4] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See Circuits on page 88 and
Programming the PLL on page 92.) A value of $0 in the multiplier
select bits configures the modulo feedback divider the same as a
value of $1. Reset initializes these bits to $6 to give a default multiply
value of 6.
Table 2. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
VCO Frequency Multiplier (N)
0000
0001
0010
0011
1
1
2
3
1101
1110
1111
13
14
15
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CGM Registers
NOTE: The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS[7:4] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency
f . (See Circuits on page 88, Programming the PLL on page 92,
vrs
and PLL Control Register on page 98.) VRS[7:4] cannot be written
when the PLLON bit in the PLL control register (PCTL) is set. (See
Special Programming Exceptions on page 93.) A value of $0 in the
VCO range select bits disables the PLL and clears the BCS bit in the
PCTL. (See Base Clock Selector Circuit on page 94 and Special
Programming Exceptions on page 93 for more information.) Reset
initializes the bits to $6 to give a default range multiply value of 6.
NOTE: The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
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Inte rrup ts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupt requests from the PLL. PLLF, the interrupt flag in the
PCTL, becomes set whether CPU interrupt requests are enabled or not.
When the AUTO bit is clear, CPU interrupt requests from the PLL are
disabled and PLLF reads as logic 0.
Software should read the LOCK bit after a PLL CPU interrupt request to
see if the request was due to an entry into lock or an exit from lock. When
the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not
frequency-sensitive, CPU interrupt requests should be disabled to
prevent PLL interrupt service routines from impeding software
performance or from exceeding stack limitations.
NOTE: Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
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Low-Power Modes
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
Wa it Mod e
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
Stop Mod e
The STOP instruction disables the CGM and holds low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
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CGM During Bre a k Inte rrup ts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Break Module on page
149.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.
Ac q uisition/ Loc k Tim e Sp e c ific a tions
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
Ac q uisition/ Loc k
Tim e De finitions
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percent of the
step input or when the output settles to the desired value plus or minus
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5% acquisition time tolerance. If a
command instructs the system to change from 0 Hz to 1 MHz, the
acquisition time is the time taken for the frequency to reach
1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is
operating at 1 MHz and suffers a –100 kHz noise hit, the acquisition time
is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5%
of the 100-kHz step input.
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Acquisition/Lock Time Specifications
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are as follows:
•
Acquisition time, t , is the time the PLL takes to reduce the error
acq
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance, ∆ .
trk
Acquisition time is based on an initial frequency error,
(f
– f )/f , of not more than ±100%. In automatic bandwidth
orig des
des
control mode (see Manual and Automatic PLL Bandwidth
Modes on page 90), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
•
Lock time, t
, is the time the PLL takes to reduce the error
Lock
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance, ∆ . Lock
Lock
time is based on an initial frequency error, (f – f )/f , of not
des
orig des
more than ±100%. In automatic bandwidth control mode, lock time
expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). (See Manual and Automatic PLL
Bandwidth Modes on page 90.)
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
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Pa ra m e tric
Influe nc e s on
Re a c tion Tim e
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL
is the reference frequency, f . This frequency is the input to the phase
rdv
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is also under user control via the choice of
crystal frequency f
.
xclk
Another critical parameter is the external filter capacitor. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus change in charge) is proportional to the
capacitor size. The size of the capacitor also is related to the stability of
the PLL. If the capacitor is too small, the PLL cannot make small enough
adjustments to the voltage and the system cannot lock. If the capacitor
is too large, the PLL may not be able to adjust the voltage in a
reasonable time. (See Choosing a Filter Capacitor on page 109.)
Also important is the operating voltage potential applied to V
. The
DDA
power supply potential alters the characteristics of the PLL. A fixed value
is best. Variable supplies, such as batteries, are acceptable if they vary
within a known range at very slow speeds. Noise on the power supply is
not acceptable, because it causes small frequency errors which
continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
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CGM
Acquisition/Lock Time Specifications
Choosing a Filte r
Ca p a c itor
As described in Parametric Influences on Reaction Time on page
108, the external filter capacitor, C , is critical to the stability and reaction
F
time of the PLL. The PLL is also dependent on reference frequency and
supply voltage. The value of the capacitor must, therefore, be chosen
with supply potential and reference frequency in mind. For proper
operation, the external filter capacitor must be chosen according to the
following equation:
VDDA
CF = Cfact
------------
frdv
For acceptable values of C , (see Specifications on page 333). For
fact
the value of V
, choose the voltage potential at which the MCU is
DDA
operating. If the power supply is variable, choose a value near the
middle of the range of possible supply values.
This equation does not always yield a commonly available capacitor
size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL may become unstable. Also, always choose a capacitor with a tight
tolerance (±20% or better) and low dissipation.
Re a c tion Tim e
Ca lc ula tion
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
•
Correct selection of filter capacitor, C (See Choosing a Filter
F
Capacitor on page 109.)
•
•
•
Room temperature operation
Negligible external leakage on CGMXFC
Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K
is the K factor when the PLL is configured in acquisition mode, and
acq
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CGM
K
is the K factor when the PLL is configured in tracking mode. (See
trk
Acquisition and Tracking Modes on page 90.)
VDDA
8
tACQ
=
----------- ----------
frdv Kacq
VDDA
4
tal =
----------- --------
frdv Ktrk
tLock = tacq + tal
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See Manual
and Automatic PLL Bandwidth Modes on page 90.) A certain number
of clock cycles, n , is required to ascertain that the PLL is within the
acq
tracking mode entry tolerance, ∆ , before exiting acquisition mode. A
trk
certain number of clock cycles, n , is required to ascertain that the PLL
trk
is within the lock mode entry tolerance, ∆
. Therefore, the acquisition
Lock
time, t , is an integer multiple of n /f , and the acquisition to lock
acq
acq rdv
time, t , is an integer multiple of n /f . Also, since the average
al
trk rdv
frequency over the entire measurement period must be within the
specified tolerance, the total time usually is longer than t
calculated above.
as
Lock
In manual mode, it is usually necessary to wait considerably longer than
before selecting the PLL clock (see Base Clock Selector Circuit
t
Lock
on page 94) because the factors described in Parametric Influences on
Reaction Time on page 108 may slow the lock time considerably.
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Dire c t Me m ory Ac c e ss Mod ule
DMA
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
DMA/CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Hardware-Initiated DMA Service Requests. . . . . . . . . . . . . . . . . .121
Software-Initiated DMA Service Requests . . . . . . . . . . . . . . . . . .122
DMA Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
DMA Source/Destination Address Calculation . . . . . . . . . . . . . . .123
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
DMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
DMA Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
DMA Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . .136
DMA Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
DMA Channel Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . .140
DMA Source Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .143
DMA Destination Address Registers. . . . . . . . . . . . . . . . . . . . . . .145
DMA Block Length Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
DMA Byte Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
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DMA
Introd uc tion
The DMA can perform data transfers to and from any two CPU-addres-
sable locations without CPU intervention.
Fe a ture s
Features of the DMA include the following:
•
•
•
•
•
•
Modular Architecture
Service Request-Driven Operation without CPU Intervention
Three Independent Channels
Byte or Word Transfer Capability
Block Transfers and Loop Transfers
CPU Interrupt Capability on Completion of Block Transfer or on
Loop Restart
•
•
Programmable DMA Bus Bandwidth (25%, 50%, 67%, or 100% of
Total Bus Bandwidth)
Programmable DMA Service Request/CPU Interrupt Request
Priority
•
•
•
Programmable DMA Enable during Wait Mode
Block Transfers Up to 256 Bytes
Expandable Architecture Up to Seven Channels and Eight
Transfer Source Inputs
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DMA
Functional Description
Func tiona l De sc rip tion
The DMA is a coprocessor for servicing peripheral devices that require
data block transfers. For transmitting or receiving blocks of data to or
from peripherals, DMA transfers are faster and more code-efficient than
CPU interrupts. The following tasks that contribute to CPU interrupt
overhead are not part of a DMA transfer:
•
•
•
•
•
•
•
Stacking and unstacking CPU registers
Loading interrupt vectors
Loading address pointers
Incrementing address pointers
Storing address pointers
Clearing interrupt flags
Returning from interrupt
Once the DMA is initialized to transfer a block of data, a DMA service
request usually requires only two bus cycles per 8-bit byte or four cycles
per 16-bit word to transfer the source data to a destination.
Figure 1 shows the structure of the DMA. Each DMA channel can
transfer data independently between any addresses in the memory map.
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DMA
INTERNAL BUS
7
0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL CONTROL
REGISTERS
7
0
CHANNEL 0
CHANNEL 1
CHANNEL 2
BLOCK LENGTH
REGISTERS
CPU
SYSTEM
CONTROL
LOGIC
INTERRUPT
7
0
REQUEST
CHANNEL 0
CHANNEL 1
CHANNEL 2
BYTE COUNT
REGISTERS
ALU
15
15
0
CHANNEL 0
CHANNEL 1
CHANNEL 2
DESTINATION ADDRESS
REGISTERS
0
CHANNEL 0
CHANNEL 1
CHANNEL 2
SOURCE ADDRESS
REGISTERS
= BUS SWITCH
Figure 1. DMA Module Block Diagram
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
DMA Channel 0 Source Address
Register High (D0SH)
Indeterminate after Reset
AD4 AD3
Indeterminate after Reset
AD12 AD11
Indeterminate after Reset
AD4 AD3
Indeterminate after Reset
AD7
AD15
AD7
AD6
AD14
AD6
AD5
AD13
AD5
AD2
AD10
AD2
AD1
AD9
AD1
AD0
AD8
AD0
DMA Channel 0 Source Address
Register Low (D0SL)
DMA Channel 0 Destination
Address Register High (D0DH)
DMA Channel 0 Destination
Address Register Low (D0DL)
Figure 2. I/O Register Summary
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DMA
Functional Description
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
SDC3
SDC2
SDC1
SDC0
BWC
DTS2
DTS1
DTS0
DMA Channel 0 Control Register
(D0C)
Indeterminate after Reset
BL4 BL3
Indeterminate after Reset
BL7
BL6
BL5
BL2
BL1
BL0
DMA Channel 0 Block Length
Register (D0BL)
BC7
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
0
BC1
0
BC0
0
DMA Channel 0 Byte Count
Register (D0BC)
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
DMA Channel 1 Source Address
Register High (D1SH)
Indeterminate after Reset
AD4 AD3
Indeterminate after Reset
AD12 AD11
Indeterminate after Reset
AD4 AD3
Indeterminate after Reset
SDC0 BWC
Indeterminate after Reset
BL4 BL3
Indeterminate after Reset
AD7
AD15
AD7
AD6
AD14
AD6
AD5
AD13
AD5
AD2
AD10
AD2
AD1
AD9
AD1
DTS1
BL1
AD0
AD8
AD0
DTS0
BL0
DMA Channel 1 Source Address
Register Low (D1SL)
DMA Channel 1 Destination
Address Register High (D1DH)
DMA Channel 1 Destination
Address Register Low (D1DL)
SDC3
BL7
SDC2
BL6
SDC1
BL5
DTS2
BL2
DMA Channel 1 Control Register
(D1C)
DMA Channel 1 Block Length
Register (D1BL)
BC7
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
0
BC1
0
BC0
0
DMA Channel 1 Byte Count
Register (D1BC)
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
DMA Channel 2 Source Address
Register High (D2SH)
Indeterminate after Reset
AD4 AD3
Indeterminate after Reset
AD12 AD11
Indeterminate after Reset
AD4 AD3
Indeterminate after Reset
AD7
AD15
AD7
AD6
AD14
AD6
AD5
AD13
AD5
AD2
AD10
AD2
AD1
AD9
AD1
AD0
AD8
AD0
DMA Channel 2 Source Address
Register Low (D2SL)
DMA Channel 2 Destination
Address Register High (D2DH)
DMA Channel 2 Destination
Address Register Low (D2DL)
Figure 2. I/O Register Summary
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DMA
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
SDC3
SDC2
SDC1
SDC0
BWC
DTS2
DTS1
DTS0
DMA Channel 2 Control Register
(D2C)
Indeterminate after Reset
BL4 BL3
Indeterminate after Reset
BL7
BL6
BL5
BLL2
BL1
BL0
DMA Channel 2 Block Length
Register (D2BL)
BC7
0
BC6
0
BC5
0
BC4
0
BC3
BC2
0
BC1
0
BC0
0
DMA Channel 2 Byte Count
Register (D2BC)
0
TEC1
0
BB1
0
BB0
0
TEC2
0
IEC2
0
IEC1
0
TEC0
0
IEC0
0
DMA Control Register 1 (DC1) Write:
Reset:
Read:
DMAP
0
L2
L1
L0
DMAWE
0
IFC2
0
IFC1
0
IFC0
0
DMA Status and Control Register
Write:
(DSC)
Reset:
0
0
0
Read:
DMA Control Register 2 (DC2) Write:
Reset:
SWI7
0
SWI6
0
SWI5
0
SWI4
0
SWI33
0
SWI2
0
SWI1
0
SWI0
0
Figure 2. I/O Register Summary
Table 1. I/O Register Address Summary
Register D0SH
Address $0034
D0SL
D0DH
$0036
D0DL
$0037
D0C
D0BL
D0BC
D1SH
D1SL
D1DH
$0035
$0038
$0039 $003B $003C $003D $003E
Register D1DL
Address $003F
D1C
D1BL
D1BC
$0043
D2SH
$0044
D2SL
D2DH
$0046
D2DL
$0047
D2C
D2BL
$0040
$0041
$0045
$0048
$0049
Register D2BC
DC1
DSC
DC2
Address $004B $004C $004D $004E
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DMA
Functional Description
DMA/ CPU Tim ing
When the DMA transfers data, it takes control of the address bus, data
bus, and R/W line. During DMA transfers, the CPU clock is suspended.
The state of the CPU remains unchanged until the end of the DMA
transfer when the DMA relinquishes control of the buses and R/W line.
Then the CPU resumes operation as though nothing had happened.
Figure 3 and Figure 4 show the timing of DMA transfers.
1
2
3
4
5
6
7
8
9
10
STATE
CGMOUT
ADDRESS
BUS
DATA
BUS
R/W
CPU-CONTROLLED BUS CYCLE
DMA-CONTROLLED BUS CYCLE
Figure 3. Single Byte Transfer Timing (Any DMA Bus Bandwidth)
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DMA
Table 2. DMA Byte Transfer Activity
State
Activity
1
2
3
DMA service request occurs.
DMA arbitrates channel priority.
DMA generates internal control signals.
DMA calculates source address.
DMA latches source address in temporary register.
4
5
6
DMA drives source address onto address bus.
DMA drives R/W line high.
DMA calculates destination address.
DMA latches destination address into temporary register.
DMA latches source data into temporary register.
DMA increments byte count register.
DMA drives destination address onto address bus.
DMA drives R/W line low.
7
DMA subtracts byte count register from block length register.
If difference = 0, DMA disables channel by clearing TECx bit.
If difference = 0 and IECx = 1, DMA generates CPU interrupt request.
8
9
DMA drives source data onto data bus.
DMA releases address bus and R/W line to CPU.
DMA releases data bus to CPU.
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
STATE
CGMOUT
ADDRESS
BUS
DATA
BUS
R/W
CPU-CONTROLLED BUS CYCLE
DMA-CONTROLLED BUS CYCLE
Figure 4. Single Word Transfer Timing (100% DMA Bus Bandwidth)
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DMA
Functional Description
Table 3. DMA Word Transfer Activity
State
Activity
1
2
3
DMA service request occurs.
DMA arbitrates channel priority.
DMA generates internal control signals.
DMA calculates low byte of source address.
DMA latches low byte of source address in temporary register.
4
5
6
DMA drives low byte of source address onto address bus.
DMA drives R/W line high.
DMA calculates low byte of destination address.
DMA latches low byte of destination address into temporary register.
DMA latches low byte of source data into temporary register.
DMA increments byte count register.
DMA drives low byte of destination address onto address bus.
DMA drives R/W line low.
7
8
DMA subtracts byte count register from block length register.
If difference = 0, DMA disables channel by clearing TECx bit.
If difference = 0 and IECx = 1, DMA generates CPU interrupt request.
DMA drives low byte of source data onto data bus.
DMA calculates high byte of source address.
DMA latches high byte of source address into temporary register.
DMA drives the high byte of source address onto address bus.
DMA drives R/W line high.
DMA calculates high byte of destination address.
DMA latches high byte of destination address in temporary register.
9
DMA latches high byte of source data into temporary register.
DMA increments the byte count register.
10
DMA drives high byte of destination address onto address bus.
DMA drives R/W line low.
11
DMA subtracts byte count register from block length register.
If difference = 0, DMA disables channel by clearing TECx bit.
If difference = 0 and IECx bit set, CPU receives interrupt request.
12
13
14
DMA drives high byte of destination address onto address bus.
DMA releases the address bus and R/W line to CPU.
DMA releases data bus to CPU.
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DMA
The following procedure shows how to program a DMA transfer on a
selected channel:
1. In DMA control register 1 (DC1), disable the channel by clearing
the TECx bit. (See DMA Control Register 1 on page 133.)
2. In the source address registers (DxSH and DxSL), write the
source base address. (See DMA Source Address Registers on
page 143.)
3. In the destination address registers (DxDH and DxDL), write the
destination base address. (See DMA Destination Address
Registers on page 145.)
4. In the DMA channel x control register (DxC), make the following
selections (see DMA Channel Control Registers on page 140):
a. Select increment, decrement, or remain static for the source
and destination addresses by writing to the source/destination
address control bits, SDC[3:0].
b. Select 8-bit or 16-bit data by writing to the byte/word control
bit, BWC.
c. Assign a DMA channel to the DMA transfer source input by
writing to the DMA transfer source bits, DTS[2:0].
5. In the channel x DMA block length register (DxBL), write the
number of bytes to transfer. (See DMA Block Length Registers
on page 146.) For word transfers, the block length number is two
times the number of words.
6. In the DMA status and control register (DSC), make the following
selections (see DMA Status and Control Register on page 136):
a. Enable or disable looping of the source and destination
addresses by writing to the loop enable bit, Lx.
b. Select DMA service request/CPU interrupt request priority by
writing to the DMA priority bit, DMAP.
c. Enable or disable DMA transfers during wait mode by writing
to the DMA wait enable bit, DMAWE.
7. In DMA control register 1 (DC1), make the following selections
(see DMA Control Register 1 on page 133):
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DMA
Functional Description
a. Enable the DMA channel x by writing to the transfer enable bit,
TECx.
b. Enable or disable DMA channel x to generate CPU interrupts
on transfer completion by writing to the CPU interrupt enable
bit, IECx.
c. Select the DMA bus bandwidth by writing to the bus bandwidth
control bits, BB0 and BB1.
8. To initiate the DMA transfer with software, set the software initiate
bit, SWIx, in DMA control register 2 (DC2). (See DMA Control
Register 2 on page 139.)
Ha rdwa re -Initia te d
DMA Se rvic e
Re q ue sts
The following sources can generate DMA service requests:
•
Timer interface module (TIM) — The TIM can generate the
following DMA service requests:
– TIM channel 0 input capture/output compare
– TIM channel 1 input capture/output compare
– TIM channel 2 input capture/output compare
– TIM channel 3 input capture/output compare
•
•
Serial peripheral interface module (SPI) — The SPI can generate
the following DMA service requests:
– SPI receiver full
– SPI transmitter empty
Serial communications interface module (SCI) — The SCI can
generate the following DMA service requests:
– SCI receiver full
– SCI transmitter empty
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DMA
The DMA has eight inputs for transfer sources. Each DMA transfer
source input corresponds to one of the above DMA service requests. To
enable a transfer on one of the three DMA channels, software must first
assign the channel to one of the transfer source inputs. The channel
control register of each channel determines its transfer source
assignment. (See Table 10. DMA Transfer Source Selection.)
Softwa re -Initia te d
DMA Se rvic e
Re q ue sts
Software can initiate a DMA service request by writing to DMA control
register 2 (DC2). A software-initiated transfer begins when the following
conditions are met:
•
•
The channel is enabled by the channel x transfer enable bit, TECx,
in DMA control register 1 (DC1).
The channel is assigned to a DMA transfer source input by the
DMA transfer source bits, DTS[2:0], in the channel x control
register (DxC).
•
The corresponding software initiate bit, SWIx, in DMA control
register 2 (DC2) is set, enabling a transfer on the transfer source
input to which the channel is assigned.
During a DMA transfer on channel x, the channel x byte count register
increments with every byte transferred. When the value in the channel x
byte count register matches the value in the channel x block length
register, the channel x CPU interrupt flag, IFCx, becomes set. If the
channel x CPU interrupt enable bit, IECx, is also set, the DMA issues a
CPU interrupt request.
DMA La te nc y
When one DMA channel is active, the normal DMA latency is two cycles.
Writing to the destination/source address registers, the channel control
registers, or the block length registers of another DMA channel during a
transfer adds three cycles to DMA latency.
If more than one DMA channel is active, the latency of lower-priority
channels increases.
If two or more DMA channels have pending service requests, at least
one CPU cycle executes between each channel transfer.
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DMA
Functional Description
DMA
Sourc e / De stina tion
Ad d re ss
Three 16-bit buses connect the 16-bit DMA arithmetic/logic unit (ALU) to
the DMA channel registers. During a DMA transfer, the DMA ALU:
•
•
•
Calculates the transfer source and transfer destination addresses.
Increments the DMA byte count register for each byte transferred.
Ca lc ula tion
Determines when a block or loop transfer is complete by
comparing the DMA byte count register with the value
programmed in the DMA block length register.
The DMA source address register and destination address register
contain the base addresses for a DMA transfer. The DMA ALU uses
these address registers as base pointers when it starts the transfer. The
DMA byte count register contains the number of bytes transferred in the
current DMA operation. The DMA ALU uses the source/destination
address registers and the byte count register to calculate the actual
source and destination addresses in the following manner:
•
•
•
When an address is configured to increment, the DMA ALU adds
the byte count register to the base address.
When an address is configured to decrement, the DMA ALU
subtracts the byte counter register from the base address.
When an address is configured to remain static, the DMA ALU
uses the base address as is.
The DMA can be programmed to:
•
•
Stop the transfer after a number of bytes is transferred or
After a number of bytes is transferred, loop back to the base
addresses and continue the transfer.
Figure 5 through Figure 13 show how the DMA calculates source and
destination addresses.
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DMA
15
15
0
0
0
CHANNEL x SOURCE BASE ADDRESS
–
SOURCE ADDRESS
CHANNEL x DESTINATION BASE ADDRESS
–
DESTINATION ADDRESS
7
CHANNEL x BYTE COUNT
+ 1
= ?
NOTE:
7
0
0
When byte count = block length, the CPU
interrupt flag (IFCx) is set and the byte count
is reset.
If in loop mode (Lx = 1), leave TECx set.
If in finite transfer mode (Lx = 0), clear TECx.
CHANNEL x CONTROL
7
CHANNEL x BLOCK LENGTH
Figure 5. Decremented Source and Decremented Destination
15
0
0
0
CHANNEL x SOURCE BASE ADDRESS
+
SOURCE ADDRESS
15
CHANNEL x DESTINATION BASE ADDRESS
+
DESTINATION ADDRESS
7
CHANNEL x BYTE COUNT
+ 1
= ?
NOTE:
7
0
0
When byte count = block length, the CPU
interrupt flag (IFCx) is set and the byte count
is reset.
If in loop mode (Lx = 1), leave TECx set.
If in finite transfer mode (Lx = 0), clear TECx.
CHANNEL x CONTROL
7
CHANNEL x BLOCK LENGTH
Figure 6. Incremented Source and Incremented Destination
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DMA
Functional Description
15
0
0
0
CHANNEL x SOURCE BASE ADDRESS
SOURCE ADDRESS
DESTINATION ADDRESS
NOTE:
15
CHANNEL x DESTINATION BASE ADDRESS
–
7
CHANNEL x BYTE COUNT
+ 1
= ?
7
0
0
When byte count = block length, the CPU
interrupt flag (IFCx) is set and the byte count
is reset.
If in loop mode (Lx = 1), leave TECx set.
If in finite transfer mode (Lx = 0), clear TECx.
CHANNEL x CONTROL
7
CHANNEL x BLOCK LENGTH
Figure 7. Static Source and Decremented Destination
15
15
0
CHANNEL x SOURCE BASE ADDRESS
–
SOURCE ADDRESS
0
0
CHANNEL x DESTINATION BASE ADDRESS
DESTINATION ADDRESS
7
CHANNEL x BYTE COUNT
+ 1
= ?
NOTE:
7
0
0
When byte count = block length, the CPU
interrupt flag (IFCx) is set and the byte count
is reset.
If in loop mode (Lx = 1), leave TECx set.
If in finite transfer mode (Lx = 0), clear TECx.
CHANNEL x CONTROL
7
CHANNEL x BLOCK LENGTH
Figure 8. Decremented Source and Static Destination
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DMA
15
0
0
0
SOURCE ADDRESS
CHANNEL x SOURCE BASE ADDRESS
15
CHANNEL x DESTINATION BASE ADDRESS
+
DESTINATION ADDRESS
7
CHANNEL x BYTE COUNT
+ 1
= ?
NOTE:
7
0
0
When byte count = block length, the CPU
interrupt flag (IFCx) is set and the byte count
is reset.
If in loop mode (Lx = 1), leave TECx set.
If in finite transfer mode (Lx = 0), clear TECx.
CHANNEL x CONTROL
7
CHANNEL x BLOCK LENGTH
Figure 9. Static Source and Incremented Destination
15
0
CHANNEL x SOURCE BASE ADDRESS
+
SOURCE ADDRESS
15
0
0
CHANNEL x DESTINATION BASE ADDRESS
DESTINATION ADDRESS
7
CHANNEL x BYTE COUNT
+ 1
= ?
NOTE:
7
0
0
When byte count = block length, the CPU
interrupt flag (IFCx) is set and the byte count
is reset.
If in loop mode (Lx = 1), leave TECx set.
If in finite transfer mode (Lx = 0), clear TECx.
CHANNEL x CONTROL
7
CHANNEL x BLOCK LENGTH
Figure 10. Incremented Source and Static Destination
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DMA
Functional Description
15
0
0
0
CHANNEL x SOURCE BASE ADDRESS
–
SOURCE ADDRESS
15
CHANNEL x DESTINATION BASE ADDRESS
+
DESTINATION ADDRESS
7
CHANNEL x BYTE COUNT
+ 1
= ?
NOTE:
7
0
0
When byte count = block length, the CPU
interrupt flag (IFCx) is set and the byte count
is reset.
If in loop mode (Lx = 1), leave TECx set.
If in finite transfer mode (Lx = 0), clear TECx.
CHANNEL x CONTROL
7
CHANNEL x BLOCK LENGTH
Figure 11. Decremented Source and Incremented Destination
15
0
0
0
CHANNEL x SOURCE BASE ADDRESS
+
SOURCE ADDRESS
15
CHANNEL x DESTINATION BASE ADDRESS
–
DESTINATION ADDRESS
7
CHANNEL x BYTE COUNT
+ 1
= ?
NOTE:
7
0
0
When byte count = block length, the CPU
interrupt flag (IFCx) is set and the byte count
is reset.
If in loop mode (Lx = 1), leave TECx set.
If in finite transfer mode (Lx = 0), clear TECx.
CHANNEL x CONTROL
7
CHANNEL x BLOCK LENGTH
Figure 12. Incremented Source and Decremented Destination
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15
0
0
0
CHANNEL x SOURCE BASE ADDRESS
SOURCE ADDRESS
15
DESTINATION ADDRESS
CHANNEL x DESTINATION BASE ADDRESS
7
CHANNEL x BYTE COUNT
+ 1
= ?
NOTE:
7
0
0
When byte count = block length, the CPU
interrupt flag (IFCx) is set and the byte count
is reset.
If in loop mode (Lx = 1), leave TECx set.
If in finite transfer mode (Lx = 0), clear TECx.
CHANNEL x CONTROL
7
CHANNEL x BLOCK LENGTH
Figure 13. Static Source and Static Destination
Table 4. DMA Address Calculation (Byte Mode)
From To
From To From
To
From
To From
To
(1)
(2)
1
2
3
4
S
D
S
D
D
D
D
S
S
S
S
D
S
D
D
D
D
S
S
S
S
D
S
D
S +1
S +2
S +3
D +1
D +2
D +3
S –1
S –2
S –3
D –1
D –2
D –3
S
S
D
D
n
S
D
S +n –1
D
S
D +n –1 S –(n –1)
D
S
D –(n –1)
1. S = Source base address
2. D = Destination base address
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DMA
Functional Description
Table 5. DMA Address Calculation (Word Mode)
From To
From
To From
To
From
To From
To
(1)
(2)
1
2
3
4
5
6
S
D
S
D
S
D
S
D
S
D
1
2
3
S +1 D +1
S +1
S +2
S +3
S +4
S +5
D +1 S +1
D +1
D +2
D +3
D +4
D +5
S –1
S –2
S –3
S –4
S –5
D +1 S +1
D –1
D –2
D –3
D –4
D –5
S
D
D
S
D
S
S +1 D +1
D +1 S +1
D +1 S +1
S
D
D
S
D
S
S +1 D +1
D +1 S +1
D +1 S +1
2n –1
S
D
S +2n –2
D
S
D +2n –2 S –(2n –2)
D
S
D –(2n –2)
n
2n S +1 D +1 S +2n –1 D +1 S +1 D +2n –1 S –(2n –1) D +1 S +1 D –(2n –1)
1. S = Source base address
2. D = Destination base address
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DMA
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
Wa it Mod e
If enabled by the DMAWE bit in the DMA status and control register, the
DMA remains active in wait mode. The DMA can transfer data to and
from peripherals while the MCU remains in wait mode.
If the WAIT instruction occurs during a DMA transfer while DMAWE is
set, the DMA transfer continues to completion. If the DMAWE bit is clear,
a WAIT instruction suspends the current DMA transfer. If the DMA
priority bit (DMAP) is set, the suspended transfer resumes when the
MCU exits wait mode.
Stop Mod e
The DMA is inactive during stop mode. A STOP instruction suspends
any DMA transfer in progress. If an external interrupt brings the MCU out
of stop mode and the DMA priority bit (DMAP) is set, the suspended
DMA transfer resumes. If a reset brings the MCU out of stop mode, the
transfer is aborted.
Entering stop mode when a DMA channel is enabled may fail to clear the
the interrupt mask (I bit) in the condition code register. To make sure the
I bit is cleared when entering stop mode:
•
Before executing the STOP instruction, wait until any current DMA
transfer is complete. Then disable DMA transfers by clearing bits
TEC[2:0] in DMA control register 1.
Or,
•
Execute the clear-interrupt-mask instruction (CLI) before entering
stop mode.
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DMA During Break Interrupts
DMA During Bre a k Inte rrup ts
If the DMA is enabled, clear the DMAP bit in the DMA status and control
register before executing a break interrupt.
If a DMA-generated address matches the contents of the break address
registers, a break interrupt begins at the end of the current CPU
instruction.
If a break interrupt is asserted during the current address cycle and the
DMA is active, the DMA releases the internal address and data buses at
the next address boundary to preserve the current MCU state. During
the break interrupt, the DMA continues to arbitrate DMA channel
priorities. After the break interrupt, the DMA becomes active again and
resumes transferring data according to its highest priority service
request.
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Break Module on page
149.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
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DMA
DMA Re g iste rs
The following registers control and monitor operation of the DMA:
•
•
•
DMA control register 1 (DC1)
DMA status and control register (DSC)
DMA control register 2 (DC2)
DC1, DSC, and DC2 can be written during a DMA transfer without
affecting DMA latency.
The following registers control operation of each of the DMA channels:
•
•
DMA source address registers, high and low (D0SH:D0SL,
D1SH:D1SL, and D2SH:D2SL)
DMA destination address registers, high and low (D0DH:D0DL,
D1DH:D1DL, and D2DH:D2DL)
•
•
•
DMA channel x control registers (D0C–D2C)
DMA channel x byte count registers (D0BC–D2BC)
DMA channel x block length registers (D0BL–D2BL)
Writing to DxSH:DxSL, DxDH:DxDL, DxC, and DxBL during a transfer
affects DMA latency. A write to a channel x control register during a
transfer has a two-bus cycle latency if the transfer is first suspended by
disabling the channel. Disable the channel by writing a 0 to the TECx bit
in DMA control register 1. Without first suspending the transfer, a write
to a channel x control register during a transfer has a three-bus cycle
latency.
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DMA
DMA Registers
DMA Control
Re g iste r 1
DMA control register 1:
•
Enables channels to transfer data when DMA service requests
occur.
•
•
Enables channels to generate CPU interrupt requests.
Controls how much of the bus bandwidth the DMA uses.
Address: $004C
Bit 7
6
BB0
0
5
TEC2
0
4
IEC2
0
3
TEC1
0
2
IEC1
0
1
TEC0
0
Bit 0
IEC0
0
Read:
BB1
Write:
Reset:
0
Figure 14. DMA Control Register 1 (DC1)
BB1 and BB0 — Bus Bandwidth Control Bits
These read/write bits control the ratio of DMA/CPU bus activity during
a DMA transfer. As Table 6 shows, the DMA can use 25%, 50%, 67%,
or 100% of the bus bandwidth. Reset clears bits BB1 and BB0.
Table 6. DMA/CPU Bus Control Selection
DMA Transfer
BB1:BB0
DMA Bus Cycles
2 (25%)
CPU Bus Cycles
6 (75%)
00
01
10
11
2 (50%)
2 (50%)
2 (67%)
1 (33%)
All (100%)
0 (0%)
Figure 15, Figure 16, and Figure 17 show the timing of DMA
transfers with DMA bus bandwidths of 25%, 50%, and 67%.
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DMA
CGMOUT
ADDRESS
BUS
DATA
BUS
R/W
CPU-CONTROLLED BUS CYCLE
DMA-CONTROLLED BUS CYCLE
Figure 15. Multiple Byte/Word Transfer Timing: 25% DMA Bus Bandwidth
CGMOUT
ADDRESS
BUS
DATA
BUS
R/W
CPU-CONTROLLED BUS CYCLE
DMA-CONTROLLED BUS CYCLE
Figure 16. Multiple Byte/Word Transfer Timing: 50% DMA Bus Bandwidth
CGMOUT
ADDRESS
BUS
DATA
BUS
R/W
CPU-CONTROLLED BUS CYCLE
DMA-CONTROLLED BUS CYCLE
Figure 17. Multiple Byte/Word Transfer Timing: 67% DMA Bus Bandwidth
NOTE: When two or more DMA channels have transfers pending, the CPU
executes at least one cycle between each DMA block length, even if the
DMA channels have 100% of the bus bandwidth.
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DMA
DMA Registers
For DMA transfers of one byte or one word, giving the DMA 100% of
the bus bandwidth is appropriate. However, for large,
software-initiated transfers, limiting the bus bandwidth of the DMA
may be useful to keep from slowing CPU activity.
TEC[2:0] — Transfer Enable Bits
These read/write bits enable the corresponding channels to perform
transfers when DMA service requests occur. When two or more
channels are enabled, a transfer on one channel cannot begin while
another channel is transferring a byte or word. Reset clears the
TEC[2:0] bits.
1 = Corresponding DMA channel enabled
0 = Corresponding DMA channel disabled
IEC[2:0] — CPU Interrupt Enable Bits
These read/write bits enable the corresponding channels to generate
CPU interrupt requests upon completion of DMA block transfers or at
the restart of DMA transfer loops. Reset clears the IEC[2:0] bits.
1 = CPU interrupts from corresponding channel enabled
0 = CPU interrupts from corresponding channel disabled
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DMA Sta tus a nd
Control Re g iste r
The DMA status and control register:
•
•
•
Flags completion of DMA transfers.
Controls looping of source and destination address counts.
Controls priority of DMA service requests and CPU interrupt
requests.
Address: $004D
Bit 7
6
L2
0
5
L1
0
4
L0
0
3
DMAWE
0
2
IFC2
0
1
IFC1
0
Bit 0
IFC0
0
Read:
DMAP
Write:
Reset:
0
Figure 18. DMA Status and Control Register (DSC)
DMAP — DMA Priority Bit
This read/write bit controls the priority of CPU interrupt requests
during DMA transfers. Reset clears the DMAP bit.
1 = CPU interrupt requests inhibited during DMA transfers — When
DMAP is set, a CPU interrupt request is not recognized until
the end of the current DMA transfer. During a block transfer,
the increase in CPU interrupt latency depends on the block
size and on the bus bandwidth bits, BB[1:0]. (See DMA
Control Register 1 on page 133.)
0 = CPU interrupt requests recognized during DMA transfers —
When DMAP is clear, a CPU interrupt request is recognized
after the transfer of the current byte or word in the current DMA
transfer. The CPU interrupt disables the DMA by clearing the
transfer enable bits, TEC[2:0]. (See DMA Control Register 1
on page 133.) The DMA can increase CPU interrupt latency by
up to three cycles in a byte transfer or five cycles in a word
transfer.
NOTE: When DMAP = 0, a CPU interrupt clears the TECx bit if the channel has
a pending DMA transfer. Software must re-enable channel x after each
CPU interrupt by setting the TECx bit.
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DMA
DMA Registers
Table 7 shows the effect of the DMAP bit when the DMA has 100%
of the bus bandwidth (BB[1:0] = 1:1).
Table 7. DMA Transfer/CPU Interrupt Request Priority Selection
DMAP = 0
DMAP = 1
Highest Priority
Lowest Priority
CPU Interrupt Requests
DMA Channel 0 Transfer
DMA Channel 1 Transfer
DMA Channel 2 Transfer
DMA Channel 0 Transfer
DMA Channel 1 Transfer
DMA Channel 2 Transfer
CPU Interrupt Requests
L[2:0] — Loop Enable Bits
These read/write bits enable looping of the DMA back to the base
addresses in the source address and destination address registers
during block transfers. Reset clears the L[2:0] bits.
1 = Looping enabled — After transferring the number of bytes
equal to the number programmed in the DMA block length
register, the DMA:
•
•
•
•
Sets the CPU interrupt flag (IFCx) for that channel.
Generates a CPU interrupt request if enabled (IECx = 1).
Clears the byte count register.
Continues the transfer from the base address.
0 = Looping disabled — After transferring the number of bytes
equal to the number programmed in the DMA block length
register, the DMA:
•
•
•
•
Sets the CPU interrupt flag (IFCx) for that channel.
Generates a CPU interrupt request if enabled (IECx = 1).
Clears the byte count register.
Disables the channel by clearing the TECx bit.
NOTE: The CPU executes a minimum of one cycle before the next DMA loop
begins, even if the DMA has 100% of the bus bandwidth.
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DMAWE — DMA Wait Enable Bit
This read/write bit enables the DMA to operate while in wait mode.
Reset clears the DMAWE bit.
1 = DMA transfer enabled after WAIT instruction
0 = DMA transfer suspended after WAIT instruction
IFC[2:0] — CPU Interrupt Flag Bits
These read/write bits become set when a DMA transfer is complete
or at the end of each transfer loop. IFC2, IFC1, or IFC0 can generate
a CPU interrupt request if the corresponding IECx bit is set in DMA
control register 1. Clear IFC[2:0] by reading them and then writing 0s
to them. Reset clears the IFC[2:0] bits.
1 = DMA transfer complete
0 = DMA transfer not complete
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DMA
DMA Registers
DMA Control
Re g iste r 2
DMA control register 2 can perform two functions:
•
•
Initiate DMA transfers through software
Simulate DMA service requests for test purposes
Address: $004E
Bit 7
6
SWI6
0
5
SWI5
0
4
SWI4
0
3
SWI3
0
2
SWI2
0
1
SWI1
0
Bit 0
SWI0
0
Read:
SWI7
Write:
Reset:
0
Figure 19. DMA Control Register 2 (DC2)
SWI[7:0] — Software Initiate Bits
Each of these read/write bits corresponds to one of the eight DMA
transfer sources. (See Table 10 on page 142.) Setting an SWIx bit
can initiate a DMA service request from the selected transfer source.
1 = DMA software transfer initiated
0 = DMA software transfer halted or not initiated
Use the following steps to generate a software-initiated DMA service
request:
1. Enable a channel to perform a transfer by setting its TECx bit.
(See DMA Control Register 1 on page 133.)
2. Assign the channel to a DMA transfer source by writing a binary
value from 000 to 111 to its DTS[2:0] bits. (See DMA Channel
Control Registers on page 140.)
3. Set the SWIx bit that corresponds to the selected transfer source.
The bit positions (0–7) of the SWIx bits correspond to the binary
values (000–111) that select the DMA transfer source. For
example, after selecting transfer source 100 (binary), set bit SWI4
to initiate the DMA service request.
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DMA
DMA Cha nne l
Each DMA channel control register:
Control Re g iste rs
•
•
•
Controls calculation of source and destination addresses.
Selects transfer of 8-bit bytes or 16-bit words on the channel.
Assigns the channel to one of eight DMA transfer sources.
The state of the DMA channel control registers after reset is
indeterminate.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
SDC3
SDC2
SDC1
SDC0
BWC
DTS2
DTS1
DTS0
Indeterminate after Reset
Figure 20. DMA Channel Control Registers (D0C–D2C)
Table 8. DMA Channel Control Register Address Summary
Register
Address
D0C
D1C
D2C
$0038
$0040
$0048
SDC[3:0] — Source/Destination Address Control Bits
These read/write bits control calculation of the source and destination
addresses as shown in Table 9.
Table 9. Source/Destination Address Register Control
SDC[3:0]
1010
1001
1000
0110
0101
0100
0010
0001
0000
Source Address
Increment
Increment
Increment
Decrement
Decrement
Decrement
Static
Destination Address
Increment
Decrement
Static
Increment
Decrement
Static
Increment
Decrement
Static
Static
Static
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DMA
DMA Registers
The DMA calculates an incremented address by adding the byte
count register to the base address. To calculate a decremented
address, the DMA subtracts the byte count register from the base
address. To determine a static address, the DMA reads the base
address.
BWC — Byte/Word Control Bit
This read/write bit determines whether the DMA channel transfers
8-bit bytes or 16-bit words. The BWC bit has no effect unless either
the source or destination address is static or both are static.
1 = 16-bit words
0 = 8-bit bytes
NOTE: To transfer a block of 16-bit words (BWC = 1), set the block length to the
number of words times two. (See DMA Block Length Registers on
page 146.)
When both the source and destination addresses are static, the first byte
of the word transfers from the source base address to the destination
base address. The second byte transfers from the source base address
plus one to the destination address plus one. When either the source or
destination address increments or decrements, the DMA transfers bytes
from or to incrementing or decrementing addresses.
The CPU interrupt flag (IFCx) becomes set when the byte count register
equals the block length register.
DTS[2:0] — DMA Transfer Source Bits
These read/write bits assign the DMA channels to the eight transfer
source inputs as shown in Table 10.
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DMA
Table 10. DMA Transfer Source Selection
Transfer Source
DTS2:DTS1:DTS0
TIM Channel 0 Interrupt Request
TIM Channel 1 Interrupt Request
TIM Channel 2 Interrupt Request
TIM Channel 3 Interrupt Request
SPI Receive Interrupt Request
SPI Transmit Interrupt Request
SCI Receive Interrupt Request
SCI Transmit Interrupt Request
000
001
010
011
100
101
110
111
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DMA
DMA Registers
DMA Sourc e
Ad d re ss Re g iste rs
Each DMA channel takes its data from a source base address contained
in a 16-bit source address register. During a block transfer, the DMA
determines successive source addresses by adding to (to increment) or
subtracting from (to decrement) the base address. In static address
transfers, the DMA finds the source address by merely reading the
source address registers. Figure 21 shows the DMA source address
registers. The state of the source address registers after reset is
indeterminate.
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DMA
Bit 7
6
5
4
3
2
1
Bit 0
AD8
Read:
Write:
Reset:
AD15
AD14
AD13
AD12
AD11
AD10
AD9
Indeterminate after Reset
Bit 7
AD7
6
5
4
3
2
1
Bit 0
AD0
Read:
Write:
Reset:
AD6
AD5
AD4
AD3
AD2
AD1
Indeterminate after Reset
Figure 21. DMA Source Address Registers (D0SH/L–D2SH/L)
Table 11. DMA Source Address Register Address Summary
Register
Address
D0SH
$0034
D0SL
D1SH
D1SL
D2SH
$0044
D2SL
$0035
$003C
$003D
$0045
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DMA
DMA Registers
DMA De stina tion
Ad d re ss Re g iste rs
Each DMA channel transfers data to the destination base address
contained in a 16-bit destination address register. During a block
transfer, the DMA determines successive destination addresses by
adding to (to increment) or subtracting from (to decrement) the base
address. In static address transfers, the DMA finds the destination
address by merely reading the destination address registers. Figure 22
shows the DMA destination address registers. The state of the
destination address registers after reset is indeterminate.
Bit 7
6
5
4
3
2
1
Bit 0
AD8
Read:
Write:
Reset:
AD15
AD14
AD13
AD12
AD11
AD10
AD9
Indeterminate after Reset
Bit 7
AD7
6
5
4
3
2
1
Bit 0
AD0
Read:
Write:
Reset:
AD6
AD5
AD4
AD3
AD2
AD1
Indeterminate after Reset
Figure 22. DMA Destination Address Registers (D0DH/L–D2DH/L)
Table 12. Destination Address Register Address Summary
Register
Address
D0DH
$0036
D0DL
$0037
D1DH
$003E
D1DL
D2DH
$0046
D2DL
$0047
$003F
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DMA
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DMA
DMA Bloc k Le ng th
Re g iste rs
The read/write block length registers control the number of bytes
transferred. During a block transfer, the DMA compares the number
programmed into the channel’s DMA block length register to the number
in its DMA byte count register. When the byte count reaches the value in
the block length register, the DMA:
•
Sets the CPU interrupt flag (IFCx) for that channel in the DMA
status and control register.
•
•
Generates a CPU interrupt request if enabled.
Resets the byte count register.
If looping is disabled (Lx bit in DMA status and control register = 0), the
DMA then stops the transfer by clearing the TECx bit in DMA control
register 1, disabling the channel. If looping is enabled (Lx bit = 1), the
DMA continues the transfer from the base address.
The block length of a word transfer is twice the number of words. The
state of the DMA block length registers after reset is indeterminate.
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DMA
DMA Registers
Bit 7
BL7
6
5
4
3
2
1
Bit 0
BL0
Read:
Write:
Reset:
BL6
BL5
BL4
BL3
BL2
BL1
Indeterminate after Reset
Figure 23. DMA Block Length Registers (D0BL–D2BL)
Table 13. DMA Block Length Register Address Summary
Register
Address
D0BL
D1BL
D2BL
$0039
$0041
$0049
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DMA
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DMA
DMA Byte Count
Re g iste rs
Each read/write DMA byte count register contains the number of bytes
transferred on that channel in the current DMA transfer.
Bit 7
BC7
0
6
BC6
0
5
BC5
0
4
BC4
0
3
BC3
0
2
BC2
0
1
BC1
0
Bit 0
BC0
0
Read:
Write:
Reset:
Figure 24. DMA Byte Count Registers (D0BC–D2BC)
Table 14. DMA Byte Count Register Address Summary
Register
Address
D0BC
$003B
D1BC
$0043
D2BC
$004B
Writing to the channel x source address or destination address register
clears the channel x byte count register. The channel x byte count
register also is cleared when its count reaches the value in the channel
x block length register. Reset clears the byte count registers.
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Bre a k Mod ule
BRK
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . .152
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
DMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . .154
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Introd uc tion
The break module can generate a break interrupt that stops normal
program flow at a defined address to enter a background program.
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BRK
Fe a ture s
•
•
•
•
Accessible I/O Registers during Break Interrupts
CPU-Generated and DMA-Generated Break Interrupts
Software-Generated Break Interrupts
COP Disabling during Break Interrupts
Func tiona l De sc rip tion
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
•
•
•
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
During a DMA transfer, a DMA-generated address matches the
contents of the break address registers.
Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU- or DMA-generated address matches the contents of the
break address registers, the break interrupt begins after the CPU
completes its current instruction. A return-from-interrupt instruction (RTI)
in the break routine ends the break interrupt and returns the MCU to
normal operation. Figure 1 shows the structure of the break module.
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BRK
Functional Description
IAB[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
CONTROL
IAB[15:0]
BREAK
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 1. Break Module Block Diagram
Register Name
Bit 7
6
0
R
0
5
0
R
0
4
1
R
1
3
0
R
0
2
0
R
0
1
BW
0
Bit 0
Read:
0
R
0
0
R
0
Break Status Register (BSR) Write:
Reset:
0
Read:
Write:
Reset:
BFCE
0
R
R
R
R
R
R
R
Break Flag Control Register
(BFCR)
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Bit 15
0
14
13
0
12
0
11
0
10
0
9
0
1
Bit 8
0
Break Address Register High
(BRKH)
0
Bit 7
0
6
5
4
3
2
Bit 0
Break Address Register Low
(BRKL)
0
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
BRKE
0
Break Status and Control Register
(BSCR)
Reset:
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 2. I/O Register Summary
Table 1. I/O Register Address Summary
Register
Address
BSR
BFCR
$FE03
BRKH
$FE0C
BRKL
BSCR
$FE0E
$FE00
$FE0D
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BRK
Fla g Prote c tion
During Bre a k
Inte rrup ts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state.
CPU During Bre a k
Inte rrup ts
The CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction.
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode).
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
DMA During Bre a k
Inte rrup ts
If the DMA is enabled, clear the DMAP bit in the DMA status and control
register before executing a break interrupt.
If a break interrupt is asserted during the current address cycle and the
DMA is active, the DMA releases the internal address and data buses at
the next address boundary to preserve the current MCU state. During
the break interrupt, the DMA continues to arbitrate DMA channel
priorities. After the break interrupt, the DMA becomes active again and
resumes transferring data according to its highest priority service
request.
TIM During Bre a k
Inte rrup ts
A break interrupt stops the timer counter.
COP During Bre a k
Inte rrup ts
The COP is disabled during a break interrupt when V + V is present
DD Hi
on the RST pin.
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BRK
Low-Power Modes
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
Wa it Mod e
If enabled, the break module is active in wait mode. A DMA-generated
address that matches the break address registers in wait mode sets the
BW in the break status register.
The DMA can also use the break status and control register as its
destination address in order to write to the BRKA and BRKE bits during
wait mode. A DMA write to the break status and control register sets the
BW bit.
Stop Mod e
The break module is inactive in stop mode. The STOP instruction does
not affect break module register states.
Bre a k Mod ule Re g iste rs
These registers control and monitor operation of the break module:
•
•
•
•
•
Break status and control register (BSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
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BRK
Bre a k Sta tus a nd
Control Re g iste r
The break status and control register contains break module enable and
status bits.
Address: $FE0E
Bit 7
BRKE
0
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 3. Break Status and Control Register (BSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
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BRK
Break Module Registers
Bre a k Ad d re ss
Re g iste rs
The break address registers contain the high and low bytes of the
desired breakpoint address. Reset clears the break address registers.
Register: BRKH
Address: $FE0C
Bit 7
BRKL
$FE0D
6
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
1
0
Bit 0
Bit 8
0
Read:
Bit 15
Write:
14
0
Reset:
Read:
Write:
Reset:
0
Bit 7
0
6
5
4
3
2
Bit 0
0
0
0
0
0
0
Figure 4. Break Address Registers (BRKH and BRKL)
Bre a k Sta tus
Re g iste r
The break status register contains a flag to indicate that a break caused
an exit from wait mode. The flag is useful in applications requiring a
return to wait mode after exiting from a break interrupt.
Address: $FE00
Bit 7
6
0
5
0
4
1
3
0
2
0
1
BW
NOTE
0
Bit 0
0
Read:
Write:
Reset:
0
R
R
0
R
0
R
1
R
0
R
0
R
0
0
R = Reserved
NOTE: Writing a logic 0 clears BW.
Figure 5. Break Status Register (BSR)
BW — Break Wait Bit
This read/write bit is set when a break interrupt causes an exit from
wait mode. Clear BW by writing a logic 0 to it. Reset clears BW.
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
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BRK
BW is for applications that require a return to wait mode after exiting wait
mode for a DMA-generated break interrupt. BW can be read within the
break interrupt routine. The user can modify the return address on the
stack by subtracting 1 from it. The following code is an example.
;This code works if the H register was stacked in the break
;interrupt routine. Execute this code at the end of the break
;interrupt routine.
HIBYTEEQU
LOBYTEEQU
5
6
;
If not BW, do RTI
BRCLRBW,BSR, RETURN
;See if wait mode or stop mode
;was exited by break.
TST LOBYTE,SP
BNE DOLO
;If RETURNLO is not 0,
;then just decrement low byte.
;Else deal with high byte also.
;Point to WAIT/STOP opcode.
;Restore H register.
DEC HIBYTE,SP
DOLO DEC LOBYTE,SP
RETURNPULH
RTI
Bre a k Fla g Control
Re g iste r
The break flag control register contains a bit that enables software to
clear status bits while the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R = Reserved
Figure 6. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
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Monitor ROM
MON
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Introd uc tion
Execution of code in the monitor ROM in monitor mode allows complete
testing of the MCU through a single-wire interface with a host computer.
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MON
Fe a ture s
Features of monitor mode include the following:
•
•
Normal User-Mode Pin Functionality
One Pin Dedicated to Serial Communication between Monitor
ROM and Host Computer
•
Standard Mark/Space Non-Return-to-Zero (NRZ) Communication
with Host Computer
•
•
•
Execution of Code in Either RAM or EPROM
EPROM Programming
EPROM Security
Func tiona l De sc rip tion
The monitor ROM receives and executes commands from a host.
Figure 1 shows an example circuit used to enter monitor mode and
communicate with a host via a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor
mode, the MCU can execute the code in RAM loaded by the host while
all MCU pins retain normal operating mode functions. All communication
between the host and the MCU is through the PA0 pin at a chosen baud
rate. A level-shifting and multiplexing interface is required between PA0
and the host. PA0 is used in a wired-OR configuration and requires a
pullup resistor.
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MON
Functional Description
V
DD
10 kΩ
0.1 µF
RST
V
+ V
Hi
DD
10 Ω
IRQ1
IRQ2
V
DD
10 kΩ
V
DDA
V
DDA
0.1 µF
CGMXFC
OSC1
1
20
MC145407
0.1 µF
10 MΩ
+
+
+
+
10 µF
10 µF
10 µF
3
4
18
17
20 pF
V
DD
X1
4.9152 MHz
10 µF
2
19
OSC2
20 pF
CGND
DB-25
2
V
5
6
16
15
SS
V
DD
3
7
V
V
DD
DD
V
DD
0.1 µF
1
2
6
4
7
14
3
MC74HC125
10 kΩ
PA0
PA7
5
10 kΩ
V
DD
PC3
V
DD
10 kΩ
10 kΩ
PC0
PC1
A
See
NOTE.
B
10 kΩ
10 kΩ
NOTE: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4
Position B — Bus clock = CGMXCLK ÷ 2
Figure 1. Monitor Mode Circuit
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MON
Ente ring Monitor
Mod e
Table 1 shows the pin conditions for entering monitor mode.
Table 1. Monitor Mode Entry
Bus Clock Frequency
CGMXCLK
CGMVCLK
1
0
----------------------------- or -----------------------------
4
4
V
+ V
Hi
0
1
0
1
DD
CGMXCLK
-----------------------------
2
If the PC3 pin is low upon monitor mode entry, the bus frequency is equal
to the frequency of CGMXCLK divided by two. CGMXCLK is a buffered
version of the clock on the OSC1 pin. If PC3 is high upon monitor mode
entry, the bus frequency is equal to the frequency of CGMXCLK divided
by four. The PLL can be engaged after monitor mode entry to multiply
the bus frequency by programming the CGM. For information on how to
program the PLL, see Clock Generator Module on page 83. To use the
PLL, PC3 must be high during monitor mode entry. With the PLL
engaged, the bus frequency is equal to the PLL output, CGMVCLK,
divided by four.
NOTE: If CGMXCLK divided by two is selected as the bus frequency (PC3 = 0),
the OSC1 signal must have a 50% duty cycle at maximum bus
frequency.
Enter monitor mode with one of the pin configurations shown in Table 1
by pulling RST low and then high. The rising edge of RST latches
monitor mode. Once monitor mode is latched, the values on the PC0,
PC1, PA0, and PC3 pins can be changed.
NOTE: The PA7 pin must remain at logic 0 for 24 bus cycles after the RST pin
goes high.
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MON
Functional Description
Once out of reset, the MCU waits for the host to send eight security
bytes. (See Security on page 169.) After the security bytes, the MCU
sends a break signal (10 consecutive logic 0s) to the host, indicating that
it is ready to receive a command.
In monitor mode, the MCU uses different vectors for reset, SWI, and
break interrupt than those for user mode. The alternate vectors are in the
$FE page instead of the $FF page and allow code execution from the
internal monitor firmware instead of user code.
The COP module is disabled in monitor mode as long as V + V is
DD
Hi
applied to either the IRQ pin or the RST pin.
Table 2 summarizes the differences between user mode and monitor
mode.
Table 2. Mode Differences
Functions
Reset
Vector Vector Vector Vector Vector Vector
High Low High Low High Low
Reset
Break
Break
SWI
SWI
Modes
COP
User
Enabled
$FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
$FEFE $FEFF $FEFC $FEFD $FEFC $FEFD
(1)
Monitor Disabled
1. If the high voltage (VDD + VHi) is removed from the IRQ pin or the RST pin, the COP is
enabled. The COP is a mask option enabled or disabled by the COPD bit in the config-
uration register.
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MON
Da ta Form a t
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
START
BIT
STOP
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 2. Monitor Data Format
Bre a k Sig na l
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PA0 pin high for the
duration of two bits and then echos back the break signal.
NO STOP BIT
2-BIT DELAY TIME BEFORE 0 ECHO
PA0
START
BIT TIME
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
Figure 3. Break Transaction
Ba ud Ra te
The bus clock frequency of the MCU in monitor mode is determined by:
•
•
•
The external clock frequency
The value on the PC3 pin
Whether the phase-locked loop (PLL) is engaged
The internal monitor firmware performs a division by 256 (for sampling
data); therefore, the bus frequency divided by 256 is the baud rate of the
monitor mode data transfer.
For example, with a 4.9152-MHz external clock and the PC3 pin at logic
1 during reset, data is transferred between the monitor and host at 4800
baud. If the PC3 pin is at logic 0 during reset, the monitor baud rate is
9600.
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Functional Description
The PLL can be engaged to increase the baud rate of instruction transfer
between the host and the MCU and to increase the speed of program
execution. Monitor mode must be entered with PTC high to use the PLL.
See Entering Monitor Mode on page 160. Initially, the bus frequency is
a divide-by-four of the input clock.
After the PLL is programmed and selected as the base clock,
communication between the host and MCU must be re-established at
the new baud rate. One way to accomplish this is with a program
downloaded from the host into the MCU RAM. The downloaded routine
can program the PLL and send a new baud rate flag to the host just
before engaging the PLL onto the bus. Then an SWI instruction can be
used to return program control to the monitor firmware.
Com m a nd s
The monitor ROM firmware uses the following commands:
•
•
•
•
•
•
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer + 1)
RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PA0
pin for error checking. An 11-bit delay at the end of each command
allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ,
IREAD, or READSP data is returned. The data returned by a read
command appears after the echo of the last byte of the command.
NOTE: Wait one bit time after each echo before sending the next byte.
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MON
FROM
HOST
Address
High
Address
High
Address
Low
Address
Low
READ
READ
Data
4
4
1
1
4
1
3, 2
4
ECHO
NOTE: 1 = Echo delay (2 bit times)
RETURN
2 = Data return delay (2 bit times)
3 = Cancel command delay (11 bit times)
4 = Wait 1 bit time before sending next byte.
Figure 4. Read Transaction
FROM
HOST
Address
High
Address
High
Address
Low
Address
Low
Data
Data
WRITE
WRITE
4
4
1
1
4
1
4
1
3, 4
ECHO
NOTE: 1 = Echo delay (2 bit times)
3 = Cancel command delay (11 bit times)
4 = Wait 1 bit time before sending next byte.
Figure 5. Write Transaction
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MON
Functional Description
A brief description of each monitor mode command follows:
Table 3. READ (Read Memory) Command
Description Read byte from memory
Operand 2-byte address in high byte:low byte order
Data
Returned
Returns contents of specified address
Opcode $4A
Command Sequence
SENT TO
MONITOR
Address
High
Address
High
Address
Low
Address
Low
READ
READ
Data
ECHO
RETURN
Table 4. WRITE (Write Memory) Command
Description Write byte to memory
2-byte address in high byte:low byte order; low byte followed by
data byte
Operand
Data
Returned
None
Opcode $49
Command Sequence
FROM
HOST
Address
High
Address
High
Address
Low
Address
Low
Data
Data
WRITE
WRITE
ECHO
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MON
Table 5. IREAD (Indexed Read) Command
Description Read next 2 bytes in memory from last address accessed
Operand 2-byte address in high byte:low byte order
Data
Returned
Returns contents of next two addresses
Opcode $1A
Command Sequence
FROM
HOST
IREAD
IREAD
Data
Data
ECHO
RETURN
Table 6. IWRITE (Indexed Write) Command
Description Write to last address accessed + 1
Operand Single data byte
Data
None
Returned
Opcode $19
Command Sequence
FROM
HOST
Data
Data
IWRITE
ECHO
IWRITE
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Functional Description
A sequence of IREAD or IWRITE commands can access a block of
memory sequentially over the full 64-Kbyte memory map.
Table 7. READSP (Read Stack Pointer) Command
Description Reads stack pointer
Operand None
Returns incremented stack pointer value (SP + 1) in high byte:low
byte order.
Data
Returned
Opcode $0C
Command Sequence
FROM
HOST
SP
High
SP
Low
READSP
READSP
ECHO
RETURN
Table 8. RUN (Run User Program) Command
Description Executes PULH and RTI instructions
Operand None
Data
None
Returned
Opcode $28
Command Sequence
FROM
HOST
RUN
RUN
ECHO
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MON
The MCU executes the SWI and PSHH instructions when it enters
monitor mode. The RUN command tells the MCU to execute the PULH
and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program.
The READSP command returns the incremented stack pointer value,
SP + 1. The high and low bytes of the program counter are at addresses
SP + 5 and SP + 6.
SP
HIGH BYTE OF INDEX REGISTER
CONDITION CODE REGISTER
ACCUMULATOR
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
SP + 7
LOW BYTE OF INDEX REGISTER
HIGH BYTE OF PROGRAM COUNTER
LOW BYTE OF PROGRAM COUNTER
Figure 6. Stack Pointer at Monitor Mode Entry
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MON
Security
Se c urity
A security feature discourages unauthorized reading of EPROM
locations while in monitor mode. The host can bypass the security
feature at monitor mode entry by sending eight security bytes that match
the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain
user-defined data.
NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons,
program locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PA0.
V
DD
4096 + 32 CGMXCLK CYCLES
24 CGMXCLK CYCLES
RST
PA7
256 CGMXCLK CYCLES (ONE BIT TIME)
FROM HOST
FROM MCU
PA0
1
1
4
1
4
2
1
NOTE: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
4 = Wait 1 bit time before sending next byte.
Figure 7. Monitor Mode Entry Timing
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MON
If the received bytes match those at locations $FFF6–$FFFD, the host
bypasses the security feature and can read all EPROM locations and
execute code from EPROM. Security remains bypassed until a power-on
reset occurs. After the host bypasses security, any reset other than a
power-on reset requires the host to send another eight bytes. If the reset
was not a power-on reset, security remains bypassed regardless of the
data that the host sends.
If the received bytes do not match the data at locations $FFF6–$FFFD,
the host fails to bypass the security feature. The MCU remains in monitor
mode, but reading EPROM locations returns undefined data, and trying
to execute code from EPROM causes an illegal address reset. After the
host fails to bypass security, any reset other than a power-on reset
causes an endless loop of illegal address resets.
After receiving the eight security bytes from the host, the MCU transmits
a break character signalling that it is ready to receive a command.
NOTE: The MCU does not transmit a break character until after the host sends
the eight security bytes.
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Tim e r Inte rfa c e Mod ule
TIM
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Buffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
Pulse Width Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . .180
Buffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . . . .181
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
TIM Clock Pin (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
TIM Channel I/O Pins (TCH0–TCH3) . . . . . . . . . . . . . . . . . . . . . .186
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
TIM Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . .188
TIM DMA Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .192
TIM Channel Status and Control Registers. . . . . . . . . . . . . . . . . .192
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TIM
TIM Channel 0 Status and Control Register . . . . . . . . . . . . . . .193
TIM Channel 1 Status and Control Register . . . . . . . . . . . . . . .193
TIM Channel 2 Status and Control Register . . . . . . . . . . . . . . .193
TIM Channel 3 Status and Control Register . . . . . . . . . . . . . . .194
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Introd uc tion
The TIM is a 4-channel timer that provides a timing reference with input
capture, output compare, and pulse-width-modulation functions. Figure
1 is a block diagram of the TIM.
Fe a ture s
Features of the TIM include the following:
•
Four Input Capture/Output Compare Channels
– Rising-Edge, Falling-Edge, or Any-Edge Input Capture Trigger
– Set, Clear, or Toggle Output Compare Action
•
•
Buffered and Unbuffered Pulse Width Modulation (PWM) Signal
Generation
Programmable TIM Clock Input
– 7-Frequency Internal Bus Clock Prescaler Selection
– External TIM Clock Input (4-MHz Maximum Frequency)
Free-Running or Modulo Up-Count Operation
Toggle Any Channel Pin on Overflow
•
•
•
•
•
TIM Counter Stop and Reset Bits
DMA Service Request Generation
Modular Architecture Expandable to Eight Channels
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Pin Name Conventions
Pin Na m e Conve ntions
The generic names of the TIM I/O pins are:
•
•
•
•
•
TCLK (TIM external clock input pin)
TCH0 (TIM channel 0 I/O pin)
TCH1 (TIM channel 1 I/O pin)
TCH2 (TIM channel 2 I/O pin)
TCH3 (TIM channel 3 I/O pin)
TIM pins are shared by parallel I/O ports. The full name of a TIM pin
reflects the name of the shared port pin. The generic pin names appear
in the text that follows. Table 1 shows the full names of the TIM I/O pins.
Table 1. Pin Name Conventions
Generic
Pin Names
TCLK
TCH0
TCH1
TCH2
TCH3
Full
Pin Names
PE3/TCLK PE4/TCH0 PE5/TCH1 PE6/TCH2 PE7/TCH3
Func tiona l De sc rip tion
Figure 1 shows the structure of the TIM. The central component of the
TIM is the 16-bit TIM counter that can operate as a free-running counter
or a modulo up-counter. The TIM counter provides the timing reference
for the input capture and output compare functions. The TIM counter
modulo registers, TMODH:TMODL, control the modulo value of the TIM
counter. Software can read the TIM counter value at any time without
affecting the counting sequence.
The four TIM channels are programmable independently as input
capture or output compare channels.
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TIM
TCLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
PS2
PS1
PS0
16-BIT COUNTER
INTER-
RUPT
LOGIC
TOF
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
ELS0B
ELS0A
PORT
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0MAX
TCH0
TCH1
TCH2
TCH3
LOGIC
CH0F
INTER-
RUPT
LOGIC
16-BIT LATCH
DMA0S
CH0IE
MS0A
MS0B
CH1F
TOV1
ELS1B
ELS1A
PORT
LOGIC
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1MAX
INTER-
RUPT
LOGIC
16-BIT LATCH
DMA1S
CH1IE
MS1A
TOV2
ELS2B
ELS2A
PORT
LOGIC
CHANNEL 2
16-BIT COMPARATOR
TCH2H:TCH2L
CH2MAX
CH2F
MS2B
INTER-
RUPT
LOGIC
16-BIT LATCH
DMA2S
CH2IE
MS2A
TOV3
ELS3B
ELS3A
PORT
LOGIC
CHANNEL 3
16-BIT COMPARATOR
TCH3H:TCH3L
CH3MAX
CH3F
INTER-
RUPT
LOGIC
16-BIT LATCH
DMA3S
CH3IE
MS3A
Figure 1. TIM Block Diagram
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Functional Description
Register Name
Bit 7
TOF
0
0
0
6
5
4
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
Read:
0
TRST
0
TOIE
TSTOP
TIM Status and Control Register
(TSC)
0
0
1
0
0
0
DMA3S DMA2S DMA1S DMA0S
TIM DMA Select Register (TDMA) Write:
Reset:
0
0
14
0
13
0
12
0
11
0
10
0
9
0
Bit 8
Read: Bit 15
Write:
TIM Counter Register High
(TCNTH)
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
Read: Bit 7
TIM Counter Register Low (TCNTL Write:
Reset:
0
Bit 15
1
0
0
13
1
0
12
1
0
0
0
0
Bit 8
1
Read:
Write:
(TMODH)
14
11
10
9
TIM Counter Modulo Register High
Reset:
1
1
1
1
Read:
Write:
Reset:
Read: CH0F
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
1
6
1
5
4
3
2
1
Bit 0
1
TIM Counter Modulo Register Low
(TMODL)
1
1
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
TIM Channel 0 Status and Control
Register (TSC0)
0
0
Bit 15
14
13
12
11
10
9
Bit 8
TIM Channel 0 Register High
(TCH0H)
Indeterminate after Reset
Bit 7
6
5
0
4
3
2
1
Bit 0
TIM Channel 0 Register Low
(TCH0L)
Indeterminate after Reset
Read: CH1F
CH1IE
0
MS1A
0
ELS1B
ELS1A
TOV1
CH1MAX
TIM Channel 1 Status and Control
Register (TSC1)
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
0
0
9
0
Bit 15
14
13
12
11
10
Bit 8
TIM Channel 1 Register High
(TCH1H)
Indeterminate after Reset
Bit 7
6
5
4
3
2
1
Bit 0
TIM Channel 1 Register Low
(TCH1L)
Indeterminate after Reset
Read: CH2F
CH2IE
0
MS2B
0
MS2A
0
ELS2B
ELS2A
TOV2
CH2MAX
TIM Channel 2 Status and Control
Register (TSC2)
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
0
9
0
Bit 15
14
13
12
11
10
Bit 8
TIM Channel 2 Register High
(TCH2H)
Indeterminate after Reset
= Unimplemented
Figure 2. I/O Register Summary
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Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
TIM Channel 2 Register Low
(TCH2L)
Indeterminate after Reset
Read: CH3F
0
CH3IE
0
MS3A
0
ELS3B
ELS3A
TOV3
CH3MAX
TIM Channel 3 Status and Control
Register (TSC3)
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
0
0
9
0
Bit 15
14
13
12
11
10
Bit 8
TIM Channel 3 Register High
(TCH3H)
Indeterminate after Reset
Bit 7
6
5
4
3
2
1
Bit 0
TIM Channel 3 Register Low
(TCH3L)
Indeterminate after Reset
= Unimplemented
Figure 2. I/O Register Summary
Table 2. I/O Register Address Summary
Register
TSC
TDMA TCNTH TCNTL TMODH TMODL TSC0 TCH0H TCH0L TSC1
$0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029
Address $0020
Register TCH1H TCH1L TSC2 TCH2H TCH2L TSC3 TCH3H TCH3L
Address $002A $002B $002C $002D $002E $002F $0030
$0031
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TIM
Functional Description
TIM Counte r
Pre sc a le r
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, TCLK. The prescaler generates seven clock rates from
the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register select the TIM clock source.
Inp ut Ca p ture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input capture latency can be up to three bus clock
cycles. Input captures can generate TIM CPU interrupt requests or
TIM DMA service requests.
Outp ut Com p a re
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests or TIM DMA service requests.
Unb uffe re d
Outp ut Com p a re
Any output compare channel can generate unbuffered output compare
pulses as described in Output Compare. The pulses are unbuffered
because changing the output compare value requires writing the new
value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
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TIM
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
•
When changing to a larger output compare value, enable
channel x TIM overflow interrupts and write the new value in the
TIM overflow interrupt routine. The TIM overflow interrupt occurs
at the end of the current counter overflow period. Writing a larger
value in an output compare interrupt routine (at the end of the
current pulse) could cause two output compares to occur in the
same counter overflow period.
Buffe re d Outp ut
Com p a re
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the TCH0 pin. Writing
to the TIM channel 1 registers enables the TIM channel 1 registers to
synchronously control the output after the TIM overflows. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare
channel whose output appears on the TCH2 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2)
links channel 2 and channel 3. The output compare value in the TIM
channel 2 registers initially controls the output on the TCH2 pin. Writing
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Functional Description
to the TIM channel 3 registers enables the TIM channel 3 registers to
synchronously control the output after the TIM overflows. At each
subsequent overflow, the TIM channel registers (2 or 3) that control the
output are the ones written to last. TSC2 controls and monitors the
buffered output compare function, and TIM channel 3 status and control
register (TSC3) is unused. While the MS2B bit is set, the channel 3 pin,
TCH3, is available as a general-purpose I/O pin.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
Pulse Wid th
Mod ula tion
By using the toggle-on-overflow feature with an output compare
channel, the TIM can generate a PWM signal. The value in the TIM
counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM
counter modulo registers. The time between overflows is the period of
the PWM signal.
As Figure 3 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 3. PWM Period and Pulse Width
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TIM
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000. See TIM Status and Control Register on page 188.
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
Unb uffe re d PWM
Sig na l Ge ne ra tion
Any output compare channel can generate unbuffered PWM pulses as
described in Pulse Width Modulation on page 179. The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel
registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
•
When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
•
When changing to a longer pulse width, enable channel x TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
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TIM
Functional Description
the current PWM period. Writing a larger value in an output
compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Buffe re d PWM
Sig na l Ge ne ra tion
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the
buffered PWM function, and TIM channel 1 status and control register
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,
is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose
output appears on the TCH2 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2)
links channel 2 and channel 3. The TIM channel 2 registers initially
control the pulse width on the TCH2 pin. Writing to the TIM channel 3
registers enables the TIM channel 3 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (2 or 3) that control the
pulse width are the ones written to last. TSC2 controls and monitors the
buffered PWM function, and TIM channel 3 status and control register
(TSC3) is unused. While the MS2B bit is set, the channel 3 pin, TCH3,
is available as a general-purpose I/O pin.
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TIM
NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
PWM Initia liza tion
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB:MSxA. See Table 4 on page 197.
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. See Table 4 on page
197.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
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TIM
Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIM channel 2 registers (TCH2H:TCH2L) initially
control the PWM output. TIM status control register 2 (TSCR2) controls
and monitors the PWM signal from the linked channels. MS2B takes
priority over MS2A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. See TIM Channel
Status and Control Registers on page 192.
Inte rrup ts
The following TIM sources can generate interrupt requests:
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
•
TIM channel flags (CH3F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests and TIM DMA service requests are
controlled by the channel x interrupt enable bit, CHxIE, and the
channel x DMA select bit, DMAxS. Channel x TIM CPU interrupt
requests are enabled when CHxIE:DMAxS = 1:0. Channel x
TIM DMA service requests are enabled when CHxIE:DMAxS =
1:1. CHxF and CHxIE are in the TIM channel x status and control
register. DMAxS is in the TIM DMA select register.
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TIM
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
Wa it Mod e
The TIM remains active in wait mode. Any enabled CPU interrupt
request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
The DMA can service the TIM without exiting wait mode.
Stop Mod e
The TIM is inactive in stop mode. The STOP instruction does not affect
register states or the state of the TIM counter. TIM operation resumes
when the MCU exits stop mode after an external interrupt.
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TIM
TIM During Break Interrupts
TIM During Bre a k Inte rrup ts
A break interrupt stops the TIM counter.
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. See Break Module on page
149.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
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TIM
I/ O Sig na ls
Port E shares five of its pins with the TIM. TCLK is an external clock input
to the TIM prescaler. The four TIM channel I/O pins are TCH0, TCH1,
TCH2, and TCH3.
TIM Cloc k Pin
(TCLK)
TCLK is an external clock input that can be the clock source for the TIM
counter instead of the prescaled internal bus clock. Select the TCLK
input by writing logic 1s to the three prescaler select bits, PS[2:0]. See
TIM Status and Control Register on page 188. The minimum TCLK
pulse width, TCLK
or TCLK
, is:
hmin
lmin
1
------------------------------------- + tSU
bus frequency
The maximum TCLK frequency is:
bus frequency ÷ 2
TCLK is available as a general-purpose I/O pin when not used as the
TIM clock input. When the TCLK pin is the TIM clock input, it is an input
regardless of the state of the DDRE3 bit in data direction register E.
TIM Cha nne l I/ O
Pins (TCH0–TCH3)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. TCH0 and TCH2 can be
configured as buffered output compare or buffered PWM pins.
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TIM
I/O Registers
I/ O Re g iste rs
These I/O registers control and monitor operation of the TIM:
•
•
•
•
•
TIM status and control register (TSC)
TIM DMA select register (TDMA)
TIM control registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0, TSC1, TSC2, and
TSC3)
•
TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L,
TCH2H:TCH2L, and TCH3H:TCH3L)
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TIM
TIM Sta tus a nd
The TIM status and control register:
Control Re g iste r
•
•
•
•
•
Enables TIM overflow interrupts
Flags TIM overflows
Stops the TIM counter
Resets the TIM counter
Prescales the TIM counter clock
Address: $0020
Bit 7
6
TOIE
0
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TOF
0
TRST
0
0
0
= Unimplemented
Figure 4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter resets to $0000 after
reaching the modulo value programmed in the TIM counter modulo
registers. Clear TOF by reading the TIM status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIM
overflow occurs before the clearing sequence is complete, then
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = Modulo value reached
0 = Modulo value not reached
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
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TIM
I/O Registers
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic 0. Reset clears the
TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the TCLK pin or one of the seven
prescaler outputs as the input to the TIM counter as Table 3 shows.
Reset clears the PS[2:0] bits.
Table 3. Prescaler Selection
PS[2:0]
000
TIM Clock Source
Internal Bus Clock
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
TCLK
001
010
011
100
101
110
111
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TIM
TIM DMA Se le c t
Re g iste r
The TIM DMA select register enables either TIM CPU interrupt requests
or TIM DMA service requests.
Address: $0021
Bit 7
0
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
DMA3S DMA2S DMA1S DMA0S
0
0
0
0
0
0
0
0
= Unimplemented
Figure 5. TIM DMA Select Register (TDMA)
DMA3S — DMA Channel 3 Select Bit
This read/write bit enables TIM DMA service requests on channel 3.
Reset clears the DMA3S bit.
1 = TIM DMA service requests enabled on channel 3
TIM CPU interrupt requests disabled on channel 3
0 = TIM DMA service requests disabled on channel 3
TIM CPU interrupt requests enabled on channel 3
DMA2S — DMA Channel 2 Select Bit
This read/write bit enables TIM DMA service requests on channel 2.
Reset clears the DMA2S bit.
1 = TIM DMA service requests enabled on channel 2
TIM CPU interrupt requests disabled on channel 2
0 = TIM DMA service requests disabled on channel 2
TIM CPU interrupt requests enabled on channel 2
DMA1S — DMA Channel 1 Select Bit
This read/write bit enables TIM DMA service requests on channel 1.
Reset clears the DMA1S bit.
1 = TIM DMA service requests enabled on channel 1
TIM CPU interrupt requests disabled on channel 1
0 = TIM DMA service requests disabled on channel 1
TIM CPU interrupt requests enabled on channel 1
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TIM
I/O Registers
DMA0S — DMA Channel 0 Select Bit
This read/write bit enables TIM DMA service requests on channel 0.
Reset clears the DMA0S bit.
1 = TIM DMA service requests enabled on channel 0
TIM CPU interrupt requests disabled on channel 0
0 = TIM DMA service requests disabled on channel 0
TIM CPU interrupt requests enabled on channel 0
TIM Counte r
Re g iste rs
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: $0022:$0023
Bit 7
Read: Bit 15
Write:
6
5
4
3
2
1
9
Bit 0
Bit 8
14
13
12
11
10
Reset:
0
0
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
Bit 7
Bit 7
Bit 0
Bit 0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 6. TIM Counter Registers (TCNTH:TCNTL)
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TIM Counte r
Mod ulo Re g iste rs
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next clock. Writing to the high byte (TMODH) inhibits
the TOF bit and overflow interrupts until the low byte (TMODL) is written.
Reset sets the TIM counter modulo registers.
Address: $0024:$0025
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
14
13
12
11
10
1
1
6
1
5
1
4
1
3
1
2
1
1
1
Bit 7
Bit 0
Read:
Write:
Reset:
Bit 7
1
6
1
5
1
4
1
3
1
2
1
1
1
Bit 0
1
Figure 7. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
TIM Cha nne l Sta tus
Each of the TIM channel status and control registers:
a nd Control
Re g iste rs
•
•
•
•
•
•
•
•
Flags input captures and output compares.
Enables input capture and output compare interrupts.
Selects input capture, output compare, or PWM operation.
Selects high, low, or toggling output on output compare.
Selects rising, falling, or any edge as the input capture trigger.
Selects output toggling on TIM overflow.
Selects 100% PWM duty cycle.
Selects buffered or unbuffered output compare/PWM operation.
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TIM
I/O Registers
TIM Cha nne l 0
Sta tus a nd Co ntro l
Re g iste r
Address: $0026
Bit 7
Read: CH0F
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
Bit 0
TOV0
0
CH0MAX
0
Write:
Reset:
0
0
Figure 8. TIM Channel 0 Status and Control Register (TSC0)
TIM Cha nne l 1
Sta tus a nd Co ntro l
Re g iste r
Address: $0029
Bit 7
Read: CH1F
6
CH1IE
0
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Write:
Reset:
0
0
0
= Unimplemented
Figure 9. TIM Channel 1 Status and Control Register (TSC1)
TIM Cha nne l 2
Sta tus a nd Co ntro l
Re g iste r
Address: $002C
Bit 7
6
CH2IE
0
5
MS2B
0
4
MS2A
0
3
ELS2B
0
2
ELS2A
0
1
TOV2
0
Bit 0
CH2MAX
0
Read: CH2F
Write:
Reset:
0
0
Figure 10. TIM Channel 2 Status and Control Register (TSC2)
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TIM Cha nne l 3
Sta tus a nd Co ntro l
Re g iste r
Address: $002F
Bit 7
Read: CH3F
6
CH3IE
0
5
0
4
MS3A
0
3
ELS3B
0
2
ELS3A
0
1
TOV3
0
Bit 0
CH3MAX
0
Write:
Reset:
0
0
0
= Unimplemented
Figure 11. TIM Channel 3 Status and Control Register (TSC3)
CHxF— Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled
(CHxIE:DMAxS = 1:0), clear CHxF by reading TIM channel x status
and control register with CHxF set and then writing a logic 0 to CHxF.
If another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
When TIM DMA service requests are enabled (CHxIE:DMAxS = 1:1),
clear CHxF by reading or writing to the low byte of the TIM channel x
registers (TCHxL).
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
NOTE: Reading the high byte of the timer channel x registers (TCHxH) inhibits
the CHxF bit until the low byte (TCHxL) is read.
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I/O Registers
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupts and TIM DMA service
requests on channel x. The DMAxS bit in the TIM DMA select register
selects channel x TIM DMA service requests or TIM CPU interrupt
requests.
NOTE: TIM DMA service requests cannot be used in buffered PWM mode. In
buffered PWM mode, disable TIM DMA service requests by clearing the
DMAxS bit in the TIM DMA select register.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests and DMA service requests
enabled
0 = Channel x CPU interrupt requests and DMA service requests
disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0 and TIM channel 2 status and
control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and
reverts TCH3 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
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MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. See
Table 4.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin. See Table 4. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
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I/O Registers
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port E, and pin TCHx is available as a general-purpose I/O pin.
Table 4 shows how ELSxB and ELSxA work. Reset clears the ELSxB
and ELSxA bits.
Table 4. Mode, Edge, and Level Selection
MSx[B:A] ELSx[B:A]
Mode
Configuration
Pin under Port Control; Initial Output Level High
Pin under Port Control; Initial Output Level Low
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
X0
X1
00
00
00
01
01
01
1X
1X
1X
00
00
01
10
11
01
10
11
01
10
11
Output
Preset
Input
Capture
Output
Compare
or PWM
Clear Output on Compare
Set Output on Compare
Toggle Output on Compare
Buffered Output
Compare or Clear Output on Compare
Buffered PWM
Set Output on Compare
NOTE: Before enabling a TIM channel register for input capture operation, make
sure that the CHx pin is stable for at least two bus clocks.
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TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE: When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
NOTE: Reading the high byte of the timer channel x registers (TCHxH) prevents
the channel x pin from toggling until the low byte (TCHxL) is read.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 12 shows, the CHxMAX bit takes effect in the cycle after it is
set or cleared. The output stays at the 100% duty cycle level until the
cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 12. CHxMAX Latency
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TIM
I/O Registers
TIM Cha nne l
Re g iste rs
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 15
14
13
12
11
10
Indeterminate after Reset
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after Reset
Figure 13. TIM Channel Registers (TCH0H/L–TCH3H/L)
Table 5. TIM Channel Register Address Summary
Register TCH0H TCH0L TCH1H TCH1L TCH2H TCH2L TCH3H TCH3L
Address $0027 $0028 $002A $002B $002D $002E $0030 $0031
In input capture mode, reading TCHxH prevents the input capture value
from latching into the channel registers and inhibits the CHxF bit until
TCHxL is read.
In output compare mode, writing to TCHxH prevents the channel x pin
from toggling and inhibits the CHxF bit until TCHxL is written.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule
SPI
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Transmission Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . .208
Transmission Format When CPHA = 0. . . . . . . . . . . . . . . . . . . . .208
Transmission Format When CPHA = 1. . . . . . . . . . . . . . . . . . . . .210
Transmission Initiation Latency. . . . . . . . . . . . . . . . . . . . . . . . . . .211
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
Error Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Overflow Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
Resetting the SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
SPI During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
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I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .230
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
Introd uc tion
The SPI allows full-duplex, synchronous, serial communications with
peripheral devices.
Fe a ture s
Features of the SPI module include the following:
•
•
•
Full-Duplex Operation
Master and Slave Modes
Double-Buffered Operation with Separate Transmit and Receive
Registers
•
•
•
•
•
Four Master Mode Frequencies (Maximum = Bus Frequency ÷ 2)
Maximum Slave Mode Frequency = Bus Frequency
Clock Ground for Reduced Radio Frequency (RF) Interference
Serial Clock with Programmable Polarity and Phase
Two Separately Enabled Interrupts with DMA or CPU Service:
– SPRF (SPI Receiver Full)
– SPTE (SPI Transmitter Empty)
•
•
•
•
Mode Fault Error Flag with CPU Interrupt Capability
Overflow Error Flag with CPU Interrupt Capability
Programmable Wired-OR Mode
2
Limited I C (Inter-Integrated Circuit) Compatibility
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SPI
Pin Name Conventions
Pin Na m e Conve ntions
The generic names of the SPI I/O pins are:
•
•
•
•
•
SS (slave select)
SPSCK (SPI serial clock)
CGND (clock ground)
MOSI (master out slave in)
MISO (master in slave out)
SPI pins are shared by parallel I/O ports or have alternate functions. The
full name of an SPI pin reflects the name of the shared port pin or the
name of an alternate pin function. The generic pin names appear in the
text that follows. Table 1 shows the full names of the SPI I/O pins.
Table 1. Pin Name Conventions
Generic
Pin Names
MISO
MOSI
SS
SPSCK
CGND
Full
Pin Names
PF3/MISO
PF2/MOSI
PF0/SS
PF1/SPSCK CGND/EV
SS
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SPI
Func tiona l De sc rip tion
Figure 1 shows the structure of the SPI module and Figure 2 shows the
locations and contents of the SPI I/O registers.
INTERNAL BUS
TRANSMIT DATA REGISTER
SHIFT REGISTER
BUS CLOCK ÷ 2
÷ 2
MISO
MOSI
7
6
5
4
3
2
1
0
÷ 8
CLOCK
RECEIVE DATA REGISTER
DIVIDER
÷ 32
PIN
CONTROL
LOGIC
÷ 128
CLOCK
SELECT
SPSCK
SS
SPMSTR
SPE
M
CLOCK
LOGIC
S
SPR1
SPR0
SPMSTR
CPHA
CPOL
TRANSMITTER DMA SERVICE REQUEST
TRANSMITTER CPU INTERRUPT REQUEST
RECEIVER DMA SERVICE REQUEST
MODFEN
ERRIE
SPTIE
SPRIE
DMAS
SPE
SPWOM
SPI
CONTROL
RECEIVER/ERROR CPU INTERRUPT REQUEST
SPRF
SPTE
OVRF
MODF
Figure 1. SPI Module Block Diagram
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SPI
Functional Description
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
SPTIE
0
Read:
Write:
Reset:
SPI Control Register (SPCR)
SPRIE DMAS SPMSTR CPOL
CPHA SPWOM SPE
0
0
1
0
0
0
0
Read: SPRF
Write:
OVRF
MODF
SPTE
SPI Status and Control Register (SPSCR)
SPI Data Register (SPDR)
ERRIE
MODFEN SPR1
SPR0
Reset:
Read:
Write:
Reset:
0
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
1
R3
T3
0
0
0
R0
T0
R2
T2
R1
T1
Unaffected by Reset
= Unimplemented
Figure 2. SPI I/O Register Summary
Table 2. I/O Register Address Summary
Register
Address
SPCR
$0010
SPSCR
$0011
SPDR
$0012
The SPI module allows full-duplex, synchronous, serial communication
between the MCU and peripheral devices, including other MCUs.
Software can poll the SPI status flags or SPI operation can be
interrupt-driven. All SPI interrupts can be serviced by the CPU, and the
transmitter empty (SPTE) and receiver full (SPRF) flags can also be
configured for DMA service.
During DMA transmissions, the DMA fetches data from memory for the
SPI to transmit and/or the DMA stores received data in memory.
The following paragraphs describe the operation of the SPI module.
Ma ste r Mod e
The SPI operates in master mode when the SPI master bit, SPMSTR, is
set.
NOTE: Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave
SPI before disabling the master SPI.
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SPI
Only a master SPI module can initiate transmissions. Software begins
the transmission from a master SPI module by writing to the transmit
data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte
begins shifting out on the MOSI pin under the control of the serial clock.
(See Figure 3.)
The SPR1 and SPR0 bits control the baud rate generator and determine
the speed of the shift register. (See SPI Status and Control Register
on page 230.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts
in from the slave on the master’s MISO pin. The transmission ends when
the receiver full bit, SPRF, becomes set. At the same time that SPRF
becomes set, the byte from the slave transfers to the receive data
register. In normal operation, SPRF signals the end of a transmission.
Software clears SPRF by reading the SPI status and control register with
SPRF set and then reading the SPI data register. Writing to the SPI data
register clears the SPTE bit.
When the DMAS bit is set, the SPI status and control register does not
have to be read to clear the SPRF bit. A read of the SPI data register by
either the CPU or the DMA clears the SPRF bit. A write to the SPI data
register by the CPU or by the DMA clears the SPTE bit.
MASTER MCU
SLAVE MCU
MISO
MOSI
MISO
MOSI
SHIFT REGISTER
SHIFT REGISTER
SPSCK
SS
SPSCK
SS
BAUD RATE
GENERATOR
V
DD
Figure 3. Full-Duplex Master-Slave Connections
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SPI
Functional Description
Sla ve Mod e
The SPI operates in slave mode when the SPMSTR bit is clear. In slave
mode, the SPSCK pin is the input for the serial clock from the master
MCU. Before a data transmission occurs, the SS pin of the slave SPI
must be at logic 0. SS must remain low until the transmission is
complete. (See Mode Fault Error on page 218.)
In a slave SPI module, data enters the shift register under the control of
the serial clock from the master SPI module. After a byte enters the shift
register of a slave SPI, it transfers to the receive data register, and the
SPRF bit is set. To prevent an overflow condition, slave software then
must read the receive data register before another full byte enters the
shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave
is the bus clock speed (which is twice as fast as the fastest master
SPSCK clock that can be generated). The frequency of the SPSCK for
an SPI configured as a slave does not have to correspond to any SPI
baud rate. The baud rate only controls the speed of the SPSCK
generated by an SPI configured as a master. Therefore, the frequency
of the SPSCK for an SPI configured as a slave can be any frequency
less than or equal to the bus speed.
When the master SPI starts a transmission, the data in the slave shift
register begins shifting out on the MISO pin. The slave can load its shift
register with a new byte for the next transmission by writing to its transmit
data register. The slave must write to its transmit data register at least
one bus cycle before the master starts the next transmission. Otherwise
the byte already in the slave shift register shifts out on the MISO pin.
Data written to the slave shift register during a transmission remains in
a buffer until the end of the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts
a transmission. When CPHA is clear, the falling edge of SS starts a
transmission. (See Transmission Formats on page 208.)
NOTE: SPSCK must be in the proper idle state before the slave is enabled to
prevent SPSCK from appearing as a clock edge.
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SPI
Tra nsm ission Form a ts
During an SPI transmission, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially). A serial clock synchronizes
shifting and sampling on the two serial data lines. A slave select line
allows selection of an individual slave SPI device; slave devices that are
not selected do not interfere with SPI bus activities. On a master SPI
device, the slave select line can optionally be used to indicate
multiple-master bus contention.
Cloc k Pha se a nd
Pola rity Controls
Software can select any of four combinations of serial clock (SPSCK)
phase and polarity using two bits in the SPI control register (SPCR). The
clock polarity is specified by the CPOL control bit, which selects an
active high or low clock and has no significant effect on the transmission
format.
The clock phase (CPHA) control bit selects one of two fundamentally
different transmission formats. The clock phase and polarity should be
identical for the master SPI device and the communicating slave device.
In some cases, the phase and polarity are changed between
transmissions to allow a master device to communicate with peripheral
slaves having different requirements.
NOTE: Before writing to the CPOL bit or the CPHA bit, disable the SPI by
clearing the SPI enable bit (SPE).
Tra nsm ission
Figure 4 shows an SPI transmission in which CPHA is logic 0. The figure
Form a t Whe n
CPHA = 0
should not be used as a replacement for data sheet parametric
information.Two waveforms are shown for SPSCK: one for CPOL = 0
and another for CPOL = 1. The diagram may be interpreted as a master
or slave timing diagram since the serial clock (SPSCK), master in/slave
out (MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
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SPI
Transmission Formats
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See Mode Fault Error on page 218.) When CPHA = 0, the first
SPSCK edge is the MSB capture strobe. Therefore, the slave must
begin driving its data before the first SPSCK edge, and a falling edge on
the SS pin is used to start the slave data transmission. The slave’s SS
pin must be toggled back to high and then low again between each byte
transmitted as shown in Figure 5.
SPSCK CYCLE #
1
2
3
4
5
6
7
8
(FOR REFERENCE)
SPSCK (CPOL = 0)
SPSCK (CPOL =1)
MOSI
MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
LSB
LSB
(FROM MASTER)
MISO
MSB
(FROM SLAVE)
SS (TO SLAVE)
CAPTURE STROBE
Figure 4. Transmission Format (CPHA = 0)
MISO/MOSI
MASTER SS
BYTE 1
BYTE 2
BYTE 3
SLAVE SS
(CPHA = 0)
SLAVE SS
(CPHA = 1)
Figure 5. CPHA/SS Timing
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the falling edge of SS. Any data
written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
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SPI
Tra nsm ission
Form a t Whe n
CPHA = 1
Figure 6 shows an SPI transmission in which CPHA is logic 1. The figure
should not be used as a replacement for data sheet parametric
information. Two waveforms are shown for SPSCK: one for CPOL = 0
and another for CPOL = 1. The diagram may be interpreted as a master
or slave timing diagram since the serial clock (SPSCK), master in/slave
out (MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See Mode Fault Error on page 218.) When CPHA = 1, the master
begins driving its MOSI pin on the first SPSCK edge. Therefore, the
slave uses the first SPSCK edge as a start transmission signal. The SS
pin can remain low between transmissions. This format may be
preferable in systems having only one master and only one slave driving
the MISO data line.
SPSCK CYCLE #
(FOR REFERENCE)
1
2
3
4
5
6
7
8
SPSCK (CPOL = 0)
SPSCK (CPOL =1)
MOSI
MSB
MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
LSB
(FROM MASTER)
MISO
(FROM SLAVE)
LSB
SS (TO SLAVE)
CAPTURE STROBE
Figure 6. Transmission Format (CPHA = 1)
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SPI
Transmission Formats
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the first edge of SPSCK. Any
data written after the first edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
Tra nsm ission
Initia tion La te nc y
When the SPI is configured as a master (SPMSTR = 1), writing to the
SPDR starts a transmission. CPHA has no effect on the delay to the start
of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first
half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle
begins with an edge on the SPSCK line from its inactive to its active
level. The SPI clock rate (selected by SPR1:SPR0) affects the delay
from the write to SPDR and the start of the SPI transmission. (See
Figure 7 on page 212.) The internal SPI clock in the master is a
free-running derivative of the internal MCU clock. To conserve power, it
is enabled only when both the SPE and SPMSTR bits are set. SPSCK
edges occur halfway through the low time of the internal MCU clock.
Since the SPI clock is free-running, it is uncertain where the write to the
SPDR occurs relative to the slower SPSCK. This uncertainty causes the
variation in the initiation delay shown in Figure 7. This delay is no longer
than a single SPI bit time. That is, the maximum delay is two MCU bus
cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for
DIV32, and 128 MCU bus cycles for DIV128.
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SPI
WRITE
TO SPDR
INITIATION DELAY
MSB
BUS
CLOCK
MOSI
BIT 6
BIT 5
SPSCK
(CPHA = 1)
SPSCK
(CPHA = 0)
SPSCK CYCLE
NUMBER
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE
TO SPDR
BUS
CLOCK
SPSCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
EARLIEST LATEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
LATEST
LATEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
Figure 7. Transmission Start Delay (Master)
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SPI
Queuing Transmission Data
Que uing Tra nsm ission Da ta
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the transmit
data register only when the SPTE bit is high. Figure 8 shows the timing
associated with doing back-to-back transmissions with the SPI (SPSCK
has CPHA:CPOL = 1:0).
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
1
3
8
WRITE TO SPDR
SPTE
5
10
2
SPSCK
(CPHA:CPOL = 1:0)
MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
6
5
4
3
2
1
6
5
4
3
2
1
6
5
4
BYTE 1
BYTE 2
BYTE 3
4
9
SPRF
READ SPSCR
READ SPDR
6
11
7
12
1
2
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
7
8
CPU READS SPDR, CLEARING SPRF BIT.
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
3
4
10
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
11
12
CPU READS SPSCR WITH SPRF BIT SET.
CPU READS SPDR, CLEARING SPRF BIT.
5
6
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU READS SPSCR WITH SPRF BIT SET.
Figure 8. SPRF/SPTE CPU Interrupt Timing
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SPI
For an idle master or idle slave that has no data loaded into its transmit
buffer, the SPTE is set again no more than two bus cycles after the
transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of
the shift register cannot occur until the transmission is completed. This
implies that a back-to-back write to the transmit data register is not
possible. The SPTE indicates when the next write can occur.
Error Cond itions
The following flags signal SPI error conditions:
•
Overflow (OVRF) — Failing to read the SPI data register before
the next full byte enters the shift register sets the OVRF bit. The
new byte does not transfer to the receive data register, and the
unread byte still can be read. OVRF is in the SPI status and control
register.
•
Mode fault error (MODF) — The MODF bit indicates that the
voltage on the slave select pin (SS) is inconsistent with the mode
of the SPI. MODF is in the SPI status and control register.
Ove rflow Error
The overflow flag (OVRF) becomes set if the receive data register still
has unread data from a previous transmission when the capture strobe
of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs
in the middle of SPSCK cycle 7. (See Figure 4 on page 209 and Figure
6 on page 210.) If an overflow occurs, all data received after the overflow
and before the OVRF bit is cleared does not transfer to the receive data
register and does not set the SPI receiver full bit (SPRF). The unread
data that transferred to the receive data register before the overflow
occurred can still be read. Therefore, an overflow error always indicates
the loss of data. Clear the overflow flag by reading the SPI status and
control register and then reading the SPI data register.
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SPI
Error Conditions
OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. When the DMAS bit is low, the
SPRF, MODF, and OVRF interrupts share the same CPU interrupt
vector. When the DMAS bit is high, SPRF generates a receiver DMA
service request, and MODF and OVRF can generate a receiver/error
CPU interrupt request. (See Figure 12 on page 222.) It is not possible
to enable MODF or OVRF individually to generate a receiver/error CPU
interrupt request. However, leaving MODFEN low prevents MODF from
being set.
When the DMA is enabled to service the SPRF flag, it clears SPRF when
it reads the receive data register. The OVRF bit, however, still requires
the two-step clearing mechanism of reading the flag when it is set and
then reading the receive data register. In this way, the DMA cannot
directly clear the OVRF. However, if the CPU reads the SPI status and
control register with the OVRF bit set, and then the DMA reads the
receive data register, the OVRF bit is cleared.
OVRF interrupt requests to the CPU should be enabled when using the
DMA to service the SPRF if there is any chance that the overflow
condition might occur. (See Figure 9 on page 216.) Even if the DMA
clears the SPRF bit, no new data transfers from the shift register to the
receive data register with the OVRF bit high. This means that no new
SPRF interrupt requests are generated until the CPU clears the OVRF
bit. If the CPU reads the data register to clear the OVRF bit, it could clear
a pending SPRF service request to the DMA.
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SPI
BYTE 1
1
BYTE 2
3
BYTE 3
4
BYTE 4
6
BYTE 5
SPI RECEIVE
COMPLETE
SPRF
OVRF
DMA READ
OF SPDR
2
5
1
4
5
6
BYTE 1 TRANSFERS FROM SHIFT
REGISTER TO DATA REGISTER,
SETTING SPRF BIT.
BYTE 3 CAUSES OVERFLOW. BYTE 3 IS LOST.
DMA READS BYTE 2, CLEARING SPRF BIT.
2
3
DMA READS BYTE 1, CLEARING SPRF BIT.
BYTE 4 IS LOST. NO NEW SPRF DMA SERVICE
REQUESTS AND NO TRANSFERS TO DATA
REGISTER UNTIL OVRF IS CLEARED.
BYTE 2 TRANSFERS FROM SHIFT
REGISTER TO DATA REGISTER,
SETTING SPRF BIT.
Figure 9. Overflow Condition with DMA Service of SPRF
The overflow service routine may need to disable the DMA and manually
recover since an overflow indicates the loss of data. Loss of data may
prevent the DMA from reaching its byte count.
If an application requires the DMA to bring the MCU out of wait mode,
enable the OVRF bit to generate CPU interrupt requests. An overflow
condition in wait mode can cause the MCU to hang in wait mode
because the DMA cannot reach its byte count. Setting the error interrupt
enable bit (ERRIE) in the SPI status and control register enables the
OVRF bit to bring the MCU out of wait mode.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition. Figure 10 shows how it is possible to
miss an overflow. The first part of Figure 10 shows how it is possible to
read the SPSCR and SPDR to clear the SPRF without problems.
However, as illustrated by the second transmission example, the OVRF
bit can be set in between the time that SPSCR and SPDR are read.
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SPI
Error Conditions
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ
2
5
5
SPSCR
READ
SPDR
3
7
1
2
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
6
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
3
4
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 2 SETS SPRF BIT.
8
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
Figure 10. Missed Read of Overflow Condition
In this case, an overflow can easily be missed. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it is not obvious
that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the
SPSCR following the read of the SPDR. This ensures that the OVRF
was not set before the SPRF was cleared and that future transmissions
can set the SPRF bit. Figure 11 illustrates this process. Generally, to
avoid this second SPSCR read, enable the OVRF to the CPU by setting
the ERRIE bit.
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SPI
BYTE 1
1
BYTE 2
5
BYTE 3
7
BYTE 4
11
SPI RECEIVE
COMPLETE
SPRF
OVRF
READ
SPSCR
2
4
6
9
12
14
READ
SPDR
3
8
10
13
1
2
8
9
BYTE 1 SETS SPRF BIT.
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
3
4
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
10
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
11
12
13
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
5
6
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 11. Clearing SPRF When OVRF Interrupt Is Not Enabled
Mod e Fa ult Error
Setting the SPMSTR bit selects master mode and configures the
SPSCK and MOSI pins as outputs and the MISO pin as an input.
Clearing SPMSTR selects slave mode and configures the SPSCK and
MOSI pins as inputs and the MISO pin as an output. The mode fault bit,
MODF, becomes set any time the state of the slave select pin, SS, is
inconsistent with the mode selected by SPMSTR. To prevent SPI pin
contention and damage to the MCU, a mode fault error occurs if:
•
•
The SS pin of a slave SPI goes high during a transmission.
The SS pin of a master SPI goes low at any time.
For the MODF flag to be set, the mode fault error enable bit (MODFEN)
must be set. Clearing the MODFEN bit does not clear the MODF flag but
does prevent MODF from being set again after MODF is cleared.
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SPI
Error Conditions
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. When the DMAS bit is low, the
SPRF, MODF, and OVRF interrupts share the same CPU interrupt
vector. When the DMAS bit is high, SPRF generates a receiver DMA
service request instead of a CPU interrupt request, but MODF and
OVRF can generate a receiver/error CPU interrupt request. (See Figure
12 on page 222.) It is not possible to enable MODF or OVRF individually
to generate a receiver/error CPU interrupt request. However, leaving
MODFEN low prevents MODF from being set.
In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master
SPI causes the following events to occur:
•
If ERRIE = 1, the SPI generates an SPI receiver/error CPU
interrupt request.
•
•
•
•
The SPE bit is cleared.
The SPTE bit is set.
The SPI state counter is cleared.
The data direction register of the shared I/O port regains control of
port drivers.
NOTE: When the MODF flag is set, it does not clear the SPMSTR bit. The
SPMSTR bit has no function when SPE = 0. Reading SPMSTR when
MODF = 1 indicates whether the SPI was a master or a slave when
MODF became set.
NOTE: To prevent bus contention with another master SPI after a mode fault
error, clear all SPI bits of the data direction register of the shared I/O port
before enabling the SPI.
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SPI
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS
goes high during a transmission. When CPHA = 0, a transmission begins
when SS goes low and ends once the incoming SPSCK goes back to its
idle level following the shift of the eighth data bit. When CPHA = 1, the
transmission begins when the SPSCK leaves its idle level and SS is
already low. The transmission continues until the SPSCK returns to its
idle level following the shift of the last data bit. (See Transmission
Formats on page 208.)
NOTE: When CPHA = 0, a MODF occurs if an idle slave is selected (SS is at
logic 0) and later unselected (SS is at logic 1) even if no SPSCK is sent
to that slave. This happens because SS at logic 0 indicates the start of
the transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, an idle slave can be selected and then later
unselected with no transmission occurring. Therefore, MODF does not
occur since a transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by clearing the SPE bit of the slave.
NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if it was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then
write to the SPCR register. This entire clearing mechanism must occur
with no MODF condition existing or else the flag is not cleared.
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SPI
Interrupts
Inte rrup ts
Four SPI status flags can be enabled to generate CPU interrupt requests
or DMA service requests:
Table 3. SPI Interrupts
Flag
SPTE
Transmitter
Empty
Conditions for Enabling Interrupt Request
SPI Transmitter CPU Interrupt Request (DMAS = 0, SPTIE = 1,SPE = 1)
SPI Transmitter DMA Service Request (DMAS = 1, SPTIE = 1, SPE = 1)
SPRF
Receiver
Full
SPI Receiver CPU Interrupt Request (DMAS = 0, SPRIE = 1)
SPI Receiver DMA Service Request (DMAS = 1, SPRIE = 1)
OVRF
Overflow
SPI Receiver/Error Interrupt Request (ERRIE = 1)
SPI Receiver/Error Interrupt Request (ERRIE = 1)
MODF
Mode Fault
The DMA select bit (DMAS) controls whether SPTE and SPRF generate
CPU interrupt requests or DMA service requests. When DMAS = 0,
reading the SPI status and control register with SPRF set and then
reading the receive data register clears SPRF. When DMAS = 1, any
read of the receive data register clears the SPRF flag. The clearing
mechanism for the SPTE flag is always just a write to the transmit data
register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests or transmitter DMA
service requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests or receiver DMA service
requests, regardless of the state of the SPE bit. (See Figure 12.)
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SPI
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF bits to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF bit is enabled by the ERRIE bit to
generate receiver/error CPU interrupt requests.
SPI TRANSMITTER
DMA SERVICE REQUEST
SPTE
SPTIE
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
DMAS
SPI RECEIVER
DMA SERVICE REQUEST
SPRIE
SPRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
ERRIE
MODF
OVRF
Figure 12. SPI Interrupt Request Generation
Re se tting the SPI
Any system reset completely resets the SPI. Partial resets occur
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the
following occurs:
•
•
•
The SPTE flag is set.
Any transmission currently in progress is aborted.
The shift register is cleared.
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SPI
Low-Power Modes
•
•
The SPI state counter is cleared, making it ready for a new
complete transmission.
All the SPI port logic is defaulted back to being general purpose
I/O.
The following items are reset only by a system reset:
•
•
All control bits in the SPCR register.
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,
and SPR0).
•
The status flags SPRF, OVRF, and MODF.
By not resetting the control bits when SPE is low, the user can clear SPE
between transmissions without having to set all control bits again when
SPE is set back high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still
service these interrupts after the SPI has been disabled. The user can
disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled
by a mode fault occuring in an SPI that was configured as a master with
the MODFEN bit set.
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
Wa it Mod e
The SPI module remains active in wait mode. Any enabled CPU interrupt
request from the SPI module can bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
The DMA can service the SPI without exiting wait mode.
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SPI
Stop Mod e
The SPI module is inactive in stop mode. The STOP instruction does not
affect SPI register states. SPI operation resumes after an external
interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.
SPI During Bre a k Inte rrup ts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Break Module on page
149.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the transmit data register in break mode does not
initiate a transmission nor is this data transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
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SPI
I/O Signals
I/ O Sig na ls
The SPI module has five I/O pins and shares four of them with a parallel
I/O port.
•
•
•
•
•
MISO — Master data in, slave data out
MOSI — Master data out, slave data in
SPSCK — Serial clock
SS — Slave select
CGND — Clock ground
2
The SPI has limited inter-integrated circuit (I C) capability (requiring
software support) as a master in a single-master environment. To
communicate with I C peripherals, MOSI becomes an open-drain output
2
2
when the SPWOM bit in the SPI control register is set. In I C
communication, the MOSI and MISO pins are connected to a
2
bidirectional pin from the I C peripheral and through a pullup resistor to
V
.
DD
MISO (Ma ste r
In/ Sla ve Out)
MISO is one of the two SPI module pins that transmits serial data. In full
duplex operation, the MISO pin of the master SPI module is connected
to the MISO pin of the slave SPI module. The master SPI simultaneously
receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is
configured as a slave. The SPI is configured as a slave when its
SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a
high-impedance state.
When enabled, the SPI controls data direction of the MISO pin
regardless of the state of the data direction register of the shared I/O
port.
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SPI
MOSI (Ma ste r
Out/ Sla ve In)
MOSI is one of the two SPI module pins that transmits serial data. In full
duplex operation, the MOSI pin of the master SPI module is connected
to the MOSI pin of the slave SPI module. The master SPI simultaneously
transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin
regardless of the state of the data direction register of the shared I/O
port.
SPSCK (Se ria l
Cloc k)
The serial clock synchronizes data transmission between master and
slave devices. In a master MCU, the SPSCK pin is the clock output. In a
slave MCU, the SPSCK pin is the clock input. In full duplex operation,
the master and slave MCUs exchange a byte of data in eight serial clock
cycles.
When enabled, the SPI controls data direction of the SPSCK pin
regardless of the state of the data direction register of the shared I/O
port.
SS (Sla ve Se le c t)
The SS pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS is used to select a slave.
For CPHA = 0, the SS is used to define the start of a transmission. (See
Transmission Formats on page 208.) Since it is used to indicate the
start of a transmission, the SS must be toggled high and low between
each byte transmitted for the CPHA = 0 format. However, it can remain
low between transmissions for the CPHA = 1 format. See Figure 13.
MISO/MOSI
MASTER SS
BYTE 1
BYTE 2
BYTE 3
SLAVE SS
(CPHA = 0)
SLAVE SS
(CPHA = 1)
Figure 13. CPHA/SS Timing
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
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SPI
I/O Signals
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See SPI Status
and Control Register on page 230.)
NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK
clocks, even if it was already in the middle of a transmission.
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See Mode Fault Error on page 218.) For the state
of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK
register must be set. If the MODFEN bit is low for an SPI master, the SS
pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an
input-only pin to the SPI regardless of the state of the data direction
register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the port data register. (See
Table 4.)
Table 4. SPI Configuration
SPE SPMSTR
MODFEN
SPI Configuration
Not Enabled
State of SS Logic
General-purpose I/O;
SS ignored by SPI
(1)
0
1
1
1
X
X
X
0
1
0
Slave
Input-only to SPI
General-purpose I/O;
SS ignored by SPI
1
1
Master without MODF
Master with MODF
Input-only to SPI
1. X = don’t care
CGND (Cloc k
Ground )
CGND is the ground return for the serial clock pin, SPSCK, and the
ground for the port output buffers. To reduce the ground return path loop
and minimize radio frequency (RF) emissions, connect the ground pin of
the slave to the CGND pin of the master.
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SPI
I/ O Re g iste rs
Three registers control and monitor SPI operation:
•
•
•
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
SPI Control
Re g iste r
The SPI control register does the following:
•
•
•
•
•
Enables SPI module interrupt requests
Selects CPU interrupt requests or DMA service requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
•
Enables the SPI module
Address: $0010
Bit 7
6
5
4
3
2
1
SPE
0
Bit 0
SPTIE
0
Read:
SPRIE
Write:
DMAS SPMSTR CPOL
CPHA SPWOM
Reset:
0
0
1
0
1
0
Figure 14. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests or DMA service
requests generated by the SPRF bit. The SPRF bit is set when a byte
transfers from the shift register to the receive data register. Reset
clears the SPRIE bit.
1 = SPRF CPU interrupt requests or SPRF DMA service requests
enabled
0 = SPRF CPU interrupt requests or SPRF DMA service requests
disabled
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SPI
I/O Registers
DMAS —DMA Select Bit
This read/write bit selects DMA service requests when:
•
The SPI receiver full bit, SPRF, becomes set and the SPI receiver
interrupt enable bit, SPIE, is also set
•
The SPI transmitter empty bit, SPTE, becomes set and the SPI
transmitter interrupt enable bit, SPTIE, is also set
Setting the DMAS bit disables SPRF CPU interrupt requests and
SPTE CPU interrupt requests. Reset clears the DMAS bit.
1 = SPRF DMA and SPTE DMA service requests selected
SPRF CPU and SPTE CPU interrupt requests disabled
0 = SPRF DMA and SPTE DMA service requests disabled
SPRF CPU and SPTE CPU interrupt requests selected
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See Figure 4 on page 209 and Figure 6 on
page 210.) To transmit data between SPI modules, the SPI modules
must have identical CPOL values. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See Figure 4 on page 209 and Figure 6 on page
210.) To transmit data between SPI modules, the SPI modules must
have identical CPHA values. When CPHA = 0, the SS pin of the slave
SPI module must be set to logic 1 between bytes. (See Figure 13 on
page 226.) Reset sets the CPHA bit.
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SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. (See Resetting the SPI on page 222.) Reset
clears the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables CPU interrupt requests or DMA service
requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset
clears the SPTIE bit.
1 = SPTE CPU interrupt requests or SPTE DMA service requests
enabled
0 = SPTE CPU interrupt requests or SPTE DMA service requests
disabled
SPI Sta tus a nd
Control Re g iste r
The SPI status and control register contains flags to signal the following
conditions:
•
•
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow
error)
•
•
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
The SPI status and control register also contains bits that perform the
following functions:
•
•
•
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
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SPI
I/O Registers
Address: $0011
Bit 7
6
ERRIE
0
5
4
3
2
1
Bit 0
Read: SPRF
Write:
OVRF
MODF
SPTE
MODFEN SPR1
SPR0
0
Reset:
0
0
0
1
0
0
= Unimplemented
Figure 15. SPI Status and Control Register (SPSCR)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request or a DMA service request if the SPRIE bit in the SPI
control register is set also.
The DMA select bit (DMAS) in the SPI control register determines
whether SPRF generates an SPRF CPU interrupt request or an
SPRF DMA service request. During an SPRF CPU interrupt
(DMAS = 0), the CPU clears SPRF by reading the SPI status and
control register with SPRF set and then reading the SPI data register.
During an SPRF DMA transmission (DMAS = 1), any read of the SPI
data register clears the SPRF bit.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
NOTE: When the DMA is configured to service the SPI (DMAS = 1), a read by
the CPU of the receive data register can inadvertently clear the SPRF bit
and cause the DMA to miss a service request.
ERRIE — Error Interrupt Enable Bit
This read/write bit enables the MODF and OVRF bits to generate
CPU interrupt requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
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OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next full byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the receive data register. Reset clears the OVRF bit.
1 = Overflow
0 = No overflow
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes
high during a transmission with the MODFEN bit set. In a master SPI,
the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear the MODF bit by reading the SPI status and
control register (SPSCR) with MODF set and then writing to the SPI
control register (SPCR). Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request or an SPTE DMA service request if the
SPTIE bit in the SPI control register is set also.
NOTE: Do not write to the SPI data register unless the SPTE bit is high.
The DMA select bit (DMAS) in the SPI control register determines
whether SPTE generates an SPTE CPU interrupt request or an
SPTE DMA service request. During an SPTE CPU interrupt
(DMAS = 0), the CPU clears the SPTE bit by writing to the transmit
data register. During an SPTE DMA transmission (DMAS = 1), the
DMA automatically clears SPTE when it writes to the transmit data
register.
NOTE: When the DMA is configured to service the SPI (DMAS = 1), a write by
the CPU to the transmit data register can inadvertently clear the SPTE
bit and cause the DMA to miss a service request.
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SPI
I/O Registers
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If
the MODF flag is set, clearing the MODFEN does not clear the MODF
flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available for general-purpose I/O.
If the MODFEN bit is set, then this pin is not available for
general-purpose I/O. When the SPI is enabled as a slave, the SS pin
is not available as a general purpose I/O regardless of the value of
MODFEN. (See SS (Slave Select) on page 226.)
If the MODFEN bit is low, the level of the SS pin does not affect the
operation of an enabled SPI configured as a master. For an enabled
SPI configured as a slave, having MODFEN low only prevents the
MODF flag from being set. It does not affect any other part of SPI
operation. (See Mode Fault Error on page 218.)
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as
shown in Table 5. SPR1 and SPR0 have no effect in slave mode.
Reset clears SPR1 and SPR0.
Table 5. SPI Master Baud Rate Selection
SPR1:SPR0
Baud Rate Divisor (BD)
00
01
10
11
2
8
32
128
Use the following formula to calculate the SPI baud rate:
BUS CLOCK
Baud rate = ----------------------------------
BD
where:
CGMOUT = base clock output of the clock generator module (CGM)
BD = baud rate divisor
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SPI
SPI Da ta Re g iste r
The SPI data register consists of the read-only receive data register and
the write-only transmit data register. Writing to the SPI data register
writes data into the transmit data register. Reading the SPI data register
reads data from the receive data register. The transmit data and receive
data registers are separate registers that can contain different values.
(See Figure 1 on page 204.)
Address: $0012
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Indeterminate after Reset
Figure 16. SPI Data Register (SPDR)
R7:R0/T7:T0 — Receive/Transmit Data Bits
NOTE: Do not use read-modify-write instructions on the SPI data register since
the register read is not the same as the register written.
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Se ria l Com m unic a tions Inte rfa c e Mod ule
SCI
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . .246
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Error Flags During DMA Service Requests . . . . . . . . . . . . . . .259
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .262
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SCI
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
Introd uc tion
The SCI allows asynchronous communications with peripheral devices
and other MCUs.
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SCI
Features
Fe a ture s
•
•
•
•
•
•
•
•
•
Full Duplex Operation
Standard Mark/Space Non-Return-to-Zero (NRZ) Format
32 Programmable Baud Rates
Programmable 8-Bit or 9-Bit Character Length
Separately Enabled Transmitter and Receiver
Separate Receiver and Transmitter CPU Interrupt Requests
Separate Receiver and Transmitter DMA Service Requests
Programmable Transmitter Output Polarity
Two Receiver Wakeup Methods:
– Idle Line Wakeup
– Address Mark Wakeup
•
Interrupt-Driven Operation with Eight Interrupt Flags:
– Transmitter Empty
– Transmission Complete
– Receiver Full
– Idle Receiver Input
– Receiver Overrun
– Noise Error
– Framing Error
– Parity Error
•
•
•
Receiver Framing Error Detection
Hardware Parity Checking
1/16 Bit-Time Noise Detection
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SCI
Pin Na m e Conve ntions
The generic names of the SCI I/O pins are:
•
•
RxD (receive data)
TxD (transmit data)
SCI I/O lines are implemented by sharing parallel I/O port pins. The full
name of an SCI input or output reflects the name of the shared port pin.
Table 1 shows the full names and the generic names of the SCI I/O
pins.The generic pin names appear in the text of this section.
Table 1. Pin Name Conventions
Generic Pin Names
Full Pin Names
RxD
TxD
PE1/RxD
PE2/TxD
Func tiona l De sc rip tion
Figure 1 shows the structure of the SCI module. The SCI allows
full-duplex, asynchronous, NRZ serial communication between the MCU
and remote devices, including other MCUs. The transmitter and receiver
of the SCI operate independently, although they use the same baud rate
generator. During normal operation, the CPU monitors the status of the
SCI, writes the data to be transmitted, and processes received data.
During DMA transfers, the DMA fetches data from memory for the SCI
to transmit and/or the DMA stores received data in memory.
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SCI
Functional Description
INTERNAL BUS
SCI DATA
REGISTER
SCI DATA
REGISTER
RECEIVE
SHIFT REGISTER
TRANSMIT
TxD
RxD
SHIFT REGISTER
TXINV
SCTIE
R8
T8
TCIE
SCRIE
ILIE
DMARE
DMATE
TE
SCTE
TC
RE
RWU
SBK
SCRF
IDLE
OR
NF
FE
PE
ORIE
NEIE
FEIE
PEIE
LOOPS
ENSCI
LOOPS
RECEIVE
CONTROL
FLAG
CONTROL
TRANSMIT
CONTROL
WAKEUP
CONTROL
M
BKF
RPF
ENSCI
WAKE
ILTY
PEN
PTY
PRE-
BAUD RATE
÷ 4
CGMXCLK
SCALER GENERATOR
DATA SELECTION
CONTROL
÷ 16
Figure 1. SCI Module Block Diagram
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SCI
Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
TXINV
0
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
SCI Control Register 1 (SCC1) Write:
Reset:
Read:
SCTIE
TCIE
0
SCRIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
SCI Control Register 2 (SCC2) Write:
Reset:
0
0
Read:
SCI Control Register 3 (SCC3) Write:
Reset:
R8
T8
DMARE DMATE
ORIE
NEIE
FEIE
PEIE
U
U
0
0
0
0
0
0
Read: SCTE
SCI Status Register 1 (SCS1) Write:
Reset:
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
Read:
BKF
RPF
SCI Status Register 2 (SCS2) Write:
Reset:
0
0
0
0
0
0
0
0
Read:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Data Register (SCDR) Write:
Reset:
Unaffected by Reset
Read:
SCI Baud Rate Register (SCBR) Write:
Reset:
SCP1
0
SCP0
0
R
0
SCR2
0
SCR1
0
SCR0
0
0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 2. SCI I/O Register Summary
Table 2. SCI I/O Register Address Summary
Register SCC1
Address $0013
SCC2
$0014
SCC3
$0015
SCS1
$0016
SCS2
$0017
SCDR
$0018
SCBR
$0019
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Functional Description
Da ta Form a t
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 3.
8-BIT DATA FORMAT
PARITY
(BIT M IN SCC1 CLEAR)
OR DATA
NEXT
START
BIT
BIT
START
BIT
STOP
BIT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
9-BIT DATA FORMAT
(BIT M IN SCC1 SET)
PARITY
OR DATA
BIT
NEXT
START
BIT
START
BIT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP
BIT
Figure 3. SCI Data Formats
Tra nsm itte r
Figure 4 shows the structure of the SCI transmitter.
Cha ra c te r Le ng th
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
Cha ra c te r
Tra nsm issio n
During an SCI transmission, the transmit shift register shifts a character
out to the TxD pin. The SCI data register (SCDR) is the write-only buffer
between the internal data bus and the transmit shift register. To initiate
an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)
in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable
bit (TE) in SCI control register 2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status
register 1 (SCS1) and then writing to the SCDR. In a DMA transfer,
the DMA automatically clears the SCTE bit by writing to the
SCDR.
4. Repeat step 3 for each subsequent transmission.
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SCI
At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic 1s. After the
preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes
into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the
SCDR transfers a byte to the transmit shift register. The SCTE bit
indicates that the SCDR can accept new data from the internal data bus.
If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the
SCTE bit generates a transmitter CPU interrupt request or a transmitter
DMA service request.
The SCTE bit generates a transmitter DMA service request if the DMA
transfer enable bit, DMATE, in SCI control register 3 (SCC3) is set.
Setting the DMATE bit enables the SCTE bit to generate transmitter
DMA service requests and disables transmitter CPU interrupt requests.
When the transmit shift register is not transmitting a character, the TxD
pin goes to the idle condition, logic 1. If at any time software clears the
ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver
relinquish control of the port E pins.
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SCI
Functional Description
INTERNAL BUS
PRE-
BAUD
÷ 16
÷ 4
SCI DATA REGISTER
SCALER DIVIDER
SCP1
SCP0
SCR1
SCR2
SCR0
11-BIT
TRANSMIT
SHIFT REGISTER
H
8
7
6
5
4
3
2
1
0
L
TxD
TXINV
M
PEN
PTY
PARITY
GENERATION
T8
DMATE
TRANSMITTER
CONTROL LOGIC
DMATE
SCTIE
SCTE
SCTE
SBK
DMATE
SCTE
LOOPS
ENSCI
TE
SCTIE
SCTIE
TC
TC
TCIE
TCIE
Figure 4. SCI Transmitter
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Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
TXINV
0
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
SCI Control Register 1 (SCC1) Write:
Reset:
Read:
SCTIE
TCIE
0
SCRIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
SCI Control Register 2 (SCC2) Write:
Reset:
0
0
Read:
SCI Control Register 3 (SCC3) Write:
Reset:
R8
T8
DMARE DMATE
ORIE
NEIE
FEIE
PEIE
U
U
0
0
0
0
0
0
Read: SCTE
SCI Status Register 1 (SCS1) Write:
Reset:
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
Read:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Data Register (SCDR) Write:
Reset:
Unaffected by Reset
Read:
SCI Baud Rate Register (SCBR) Write:
Reset:
SCP1
0
SCP0
0
R
0
SCR2
0
SCR1
0
SCR0
0
0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 5. SCI Transmitter I/O Register Summary
Table 3. SCI Transmitter I/O Address Summary
Register
SCC1
SCC2
$0014
SCC3
$0015
SCS1
$0016
SCDR
$0018
SCBR
$0019
Address $0013
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Functional Description
Bre a k Cha ra c te rs
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit
shift register with a break character. A break character contains all logic
zeros and has no start, stop, or parity bit. Break character length
depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter
logic continuously loads break characters into the transmit shift register.
After software clears the SBK bit, the shift register finishes transmitting
the last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be.
Receiving a break character has the following effects on SCI registers:
•
•
•
•
•
•
Sets the framing error bit (FE) in SCS1
Sets the SCI receiver full bit (SCRF) in SCS1
Clears the SCI data register (SCDR)
Clears the R8 bit in SCC3
Sets the break flag bit (BKF) in SCS2
May set the overrun (OR), noise flag (NF), parity error (PE), or
reception in progress flag (RPF) bits
Id le Cha ra c te rs
An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit in SCC1. The preamble is a
synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle
after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle character to be
sent after the character currently being transmitted.
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NOTE: When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the TxD pin. Setting TE after
the stop bit appears on TxD causes data previously written to the SCDR
to be lost.
A good time to toggle the TE bit for a queued idle character is when the
SCTE bit becomes set and just before writing the next byte to the SCDR.
Inve rsio n o f
Tra nsm itte d
Outp ut
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
(See SCI Control Register 1 on page 264.)
Tra nsm itte r
Inte rrup ts
The following conditions can generate CPU interrupt requests from the
SCI transmitter:
•
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request
or a transmitter DMA service request. Setting the SCI transmit
interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to
generate transmitter CPU interrupt requests. Setting both the
SCTIE bit and the DMA transfer enable bit, DMATE, in SCC3
enables the SCTE bit to generate transmitter DMA service
requests.
•
Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.
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Functional Description
Re c e ive r
Figure 6 shows the structure of the SCI receiver.
INTERNAL BUS
SCR1
SCP1
SCP0
SCR2
SCI DATA REGISTER
SCR0
PRE-
BAUD
÷ 4
÷ 16
SCALER DIVIDER
11-BIT
RECEIVE SHIFT REGISTER
CGMXCLK
DATA
RECOVERY
H
8
7
6
5
4
3
2
1
0
L
RxD
ALL ZEROS
BKF
RPF
M
RWU
SCRF
IDLE
WAKE
ILTY
WAKEUP
LOGIC
PEN
PTY
R8
PARITY
CHECKING
IDLE
ILIE
ILIE
DMARE
SCRF
SCRIE
DMARE
SCRIE
SCRF
SCRIE
DMARE
DMARE
OR
OR
ORIE
ORIE
NF
NF
NEIE
NEIE
FE
FE
FEIE
FEIE
PE
PE
PEIE
PEIE
Figure 6. SCI Receiver Block Diagram
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Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
TXINV
0
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
SCI Control Register 1 (SCC1)
SCI Control Register 2 (SCC2)
SCI Control Register 3 (SCC3)
SCI Status Register 1 (SCS1)
SCI Status Register 2 (SCS2)
SCI Data Register (SCDR)
SCTIE
TCIE
0
SCRIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
0
R8
0
T8
DMARE DMATE
ORIE
NEIE
FEIE
PEIE
U
U
TC
0
0
IDLE
0
OR
0
NF
0
FE
0
PE
Read: SCTE
Write:
SCRF
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
1
1
0
0
0
0
0
BKF
0
RPF
0
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
0
R3
T3
0
R2
T2
0
R1
T1
0
R0
T0
Unaffected by Reset
SCP1
0
SCP0
0
R
0
SCR2
0
SCR1
0
SCR0
0
SCI Baud Rate Register (SCBR) Write:
Reset:
0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 7. SCI I/O Register Summary
Table 4. SCI Receiver I/O Address Summary
Register SCC1
Address $0013
SCC2
$0014
SCC3
$0015
SCS1
$0016
SCS2
$0017
SCDR
$0018
SCBR
$0019
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Functional Description
Cha ra c te r Le ng th
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
Cha ra c te r
Re c e p tio n
During an SCI reception, the receive shift register shifts characters in
from the RxD pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt
request or a receiver DMA service request.
The SCRF bit generates a receiver DMA service request if the DMA
receive enable bit, DMARE, in SCI control register 3 (SCC3) is set.
Setting the DMARE bit enables the SCRF bit to generate receiver DMA
service requests and disables receiver CPU interrupt requests.
Da ta Sa m p ling
The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock is resynchronized at the following
times (see Figure 8):
•
•
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
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START BIT
LSB
RxD
START BIT
QUALIFICATION
START BIT
DATA
SAMPLES
VERIFICATION SAMPLING
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
Figure 8. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 5 summarizes the results of the
start bit verification samples.
Table 5. Start Bit Verification
RT3, RT5, and RT7 Samples
Start Bit Verification
Noise Flag
000
001
010
011
100
101
110
111
Yes
Yes
Yes
No
0
1
1
0
1
0
0
0
Yes
No
No
No
If start bit verification is not successful, the RT clock is reset and a new
search for a start bit begins.
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Functional Description
To determine the value of a data bit and to detect noise, recovery logic
takes samples at RT8, RT9, and RT10. Table 6 summarizes the results
of the data bit samples.
Table 6. Data Bit Recovery
RT8, RT9, and RT10 Samples
Data Bit Determination
Noise Flag
000
001
010
011
100
101
110
111
0
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit.
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To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. Table 7 summarizes the results of the stop bit
samples.
Table 7. Stop Bit Recovery
RT8, RT9, and RT10 Samples
Framing Error Flag
Noise Flag
000
001
010
011
100
101
110
111
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
0
Fra m ing Erro rs
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error bit, FE, in
SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is
set.
Ba ud Ra te
To le ra nc e
A transmitting device may be operating at a baud rate below or above
the receiver baud rate. Accumulated bit time misalignment can cause
one of the three stop bit data samples to fall outside the actual stop bit.
Then a noise error occurs. If more than one of the samples is outside the
stop bit, a framing error occurs. In most applications, the baud rate
tolerance is much more than the degree of misalignment that is likely to
occur.
As the receiver samples an incoming character, it resynchronizes the RT
clock on any valid falling edge within the character. Resynchronization
within characters corrects misalignments between transmitter bit times
and receiver bit times.
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Functional Description
Slow Data Tolerance
Figure 9 shows how much a slow received character can be misaligned
without causing a noise error or a framing error. The slow stop bit begins
at RT8 instead of RT1 but arrives in time for the stop bit data samples at
RT8, RT9, and RT10.
MSB
STOP
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 9. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 9, the receiver counts
154 RT cycles at the point when the count of the transmitting device is
9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit character with no errors is
154 – 147
× 100 = 4.54%
-------------------------
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 9, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
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The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is
170 – 163
× 100 = 4.12%
-------------------------
170
Fast Data Tolerance
Figure 10 shows how much a fast received character can be misaligned
without causing a noise error or a framing error. The fast stop bit ends at
RT10 instead of RT16 but is still there for the stop bit data samples at
RT8, RT9, and RT10.
STOP
IDLE OR NEXT CHARACTER
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 10. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 10, the receiver counts
154 RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 8-bit character with no errors is
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
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Functional Description
154 – 160
-------------------------
154
˙
× 100 = 3.90%
With the misaligned character shown in Figure 10, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
11 bit times × 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 9-bit character with no errors is
170 – 176
× 100 = 3.53%
-------------------------
170
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Re c e ive r Wa ke up
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are
disabled.
Depending on the state of the WAKE bit in SCC1, either of two
conditions on the RxD pin can bring the receiver out of the standby state:
•
Address mark — An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
•
Idle input line condition — When the WAKE bit is clear, an idle
character on the RxD pin wakes the receiver from the standby
state by clearing the RWU bit. The idle character that wakes the
receiver does not set the receiver idle bit, IDLE, or the SCI receiver
full bit, SCRF. The idle line type bit, ILTY, determines whether the
receiver begins counting logic ones as idle character bits after the
start bit or after the stop bit.
NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
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Functional Description
Re c e ive r Inte rrup ts
The following sources can generate CPU interrupt requests from the SCI
receiver:
•
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request or a receiver
DMA service request. Setting the SCI receive interrupt enable bit,
SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU
interrupts. Setting both the SCRIE bit and the DMA receive enable
bit, DMARE, in SCC3 enables receiver DMA service requests and
disables receiver CPU interrupt requests.
•
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the RxD pin. The idle line
interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.
NOTE: When receiver DMA service requests are enabled (DMARE = 1), then
receiver CPU interrupt requests are disabled.
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Erro r Inte rrup ts
The following receiver error flags in SCS1 can generate CPU interrupt
requests:
•
Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI
error CPU interrupt requests.
•
•
•
Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, in SCC3 enables
NF to generate SCI error CPU interrupt requests.
Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI
error CPU interrupt requests.
Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU
interrupt requests.
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Functional Description
Erro r Fla g s During
DMA Se rvic e
Re q ue sts
When the DMA is servicing the SCI receiver, it clears the SCRF bit when
it reads the SCI data register. The DMA does not clear the other status
bits (BKF or RPF), nor does it clear error flags (OR, NF, FE, and PE). To
clear error flags while the DMA is servicing the receiver, enable SCI error
CPU interrupts and clear the bits in an interrupt routine. The application
may require retransmission in case of error. If the application requires
the receptions to continue, note the following latency considerations:
1. If interrupt latency is short enough for an error bit to be serviced
before the next SCRF, then it can be determined which byte
caused the error. If interrupt latency is long enough for a new
SCRF to occur before servicing an error bit, then:
a. It cannot be determined whether the error bit being serviced is
due to the byte in the SCI data register or to a previous byte.
Multiple errors can accumulate that correspond to different
bytes. In a message-based system, you may have to repeat
the entire message.
b. When the DMA is enabled to service the SCI receiver, merely
reading the SCI data register clears the SCRF bit. The second
step in clearing an error bit, reading the SCI data register,
could inadvertently clear a new, unserviced SCRF that
occurred during the error-servicing routine. Then the DMA
would ignore the byte that set the new SCRF, and the new
byte would be lost.
To prevent clearing of an unserviced SCRF bit, clear the
SCRIE bit at the beginning of the error-servicing interrupt
routine and set it at the end. Clearing SCRIE disables DMA
service so that both a read of SCS1 and a read of SCDR are
required to clear the SCRF bit. Setting SCRIE enables DMA
service so that the DMA can recognize a service request that
occurred during the error-servicing interrupt routine.
c. In the CPU interrupt routine to service error bits, do not use
BRSET or BRCLR instructions. BRSET and BRCLR read the
SCS1 register, which is the first step in clearing the register.
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Then the DMA could read the SCI data register, the second
step in clearing it, thereby clearing all error bits. The next read
of the data register would miss any error bits that were set.
2. DMA latency should be short enough so that an SCRF is serviced
before the next SCRF occurs. If DMA latency is long enough for a
new SCRF to occur before servicing an error bit, then:
a. Overruns occur. Set the ORIE bit to enable SCI error CPU
interrupt requests and service the overrun in an interrupt
routine. In a message-based system, disable the DMA in the
interrupt routine and manually recover. Otherwise, the byte
that was lost in the overrun could prevent the DMA from
reaching its byte count. If the DMA reaches it byte count in the
following message, two messages may be corrupted.
b. If the CPU does not service an overrun interrupt request, the
DMA can eventually clear the SCRF bit by reading the SCI
data register. The OR bit remains set. Each time a new byte
sets the SCRF bit, new data transfers from the shift register to
the SCI data register (provided that another overrun does not
occur), even though the OR bit is set. The DMA removed the
overrun condition by reading the data register, but the OR bit
has not been cleared.
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Low-Power Modes
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
Wa it Mod e
The SCI module remains active in wait mode. Any enabled CPU
interrupt request from the SCI module can bring the MCU out of wait
mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
The DMA can service the SCI without exiting wait mode.
Stop Mod e
The SCI module is inactive in stop mode. The STOP instruction does not
affect SCI register states. SCI module operation resumes after the MCU
exits stop mode.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
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SCI During Bre a k Mod ule Inte rrup ts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Break Module on page
149.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
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I/O Signals
I/ O Sig na ls
Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:
•
•
TxD — Transmit data
RxD — Receive data
TxD
The TxD pin is the serial data output from the SCI transmitter. The SCI
shares the TxD pin with port E. When the SCI is enabled, the TxD pin is
an output regardless of the state of the DDRE2 bit in data direction
register E (DDRE).
(Tra nsm it Da ta )
RxD
(Rece ive Da ta )
The RxD pin is the serial data input to the SCI receiver. The SCI shares
the RxD pin with port E. When the SCI is enabled, the RxD pin is an input
regardless of the state of the DDRE1 bit in data direction register E
(DDRE).
I/ O Re g iste rs
The following I/O registers control and monitor SCI operation:
•
•
•
•
•
•
•
SCI control register 1 (SCC1)
SCI control register 2 (SCC2)
SCI control register 3 (SCC3)
SCI status register 1 (SCS1)
SCI status register 2 (SCS2)
SCI data register (SCDR)
SCI baud rate register (SCBR)
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SCI Control
Re g iste r 1
SCI control register 1:
•
•
•
•
•
•
•
•
Enables loop mode operation.
Enables the SCI.
Controls output polarity.
Controls character length.
Controls SCI wakeup method.
Controls idle character detection.
Enables parity function.
Controls parity type.
Address: $0013
Bit 7
6
ENSCI
0
5
TXINV
0
4
M
0
3
WAKE
0
2
ILLTY
0
1
PEN
0
Bit 0
PTY
0
Read:
LOOPS
Write:
Reset:
0
Figure 11. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the
RxD pin is disconnected from the SCI, and the transmitter output goes
into the receiver input. Both the transmitter and the receiver must be
enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
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I/O Registers
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or
nine bits long. (See Table 8.) The ninth bit can serve as an extra stop
bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M
bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition on the RxD pin. Reset clears the WAKE
bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s
as idle character bits. The counting begins either after the start bit or
after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
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PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 8.)
When enabled, the parity function inserts a parity bit in the most
significant bit position. (See Figure 3 on page 241.) Reset clears the
PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. (See Table 8.) Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
NOTE: Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 8. Character Format Selection
Control Bits
PEN–PTY
Character Format
Start
Bits
Data
Bits
Stop
Parity
Character
Length
M
Bits
0
1
0
0
1
1
0X
0X
10
11
10
11
1
1
1
1
1
1
8
9
7
7
8
8
None
None
Even
Odd
1
1
1
1
1
1
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
Even
Odd
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I/O Registers
SCI Control
Re g iste r 2
SCI control register 2:
•
Enables the following CPU interrupt requests and DMA service
requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests or transmitter DMA service requests.
– Enables the TC bit to generate transmitter CPU interrupt
requests.
– Enables the SCRF bit to generate receiver CPU interrupt
requests or receiver DMA service requests.
– Enables the IDLE bit to generate receiver CPU interrupt
requests.
•
•
•
•
Enables the transmitter.
Enables the receiver.
Enables SCI wakeup.
Transmits SCI break characters.
Address: $0014
Bit 7
6
TCIE
0
5
SCRIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
Read:
SCTIE
Write:
Reset:
0
Figure 12. SCI Control Register 2 (SCC2)
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SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests or DMA service requests. Setting the SCTIE
bit and clearing the DMA transfer enable bit, DMATE, in SCC3
enables the SCTE bit to generate CPU interrupt requests. Setting
both the SCTIE and DMATE bits enables the SCTE bit to generate
DMA service requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt or DMA service
requests
0 = SCTE not enabled to generate CPU interrupt or DMA service
requests
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests or SCI receiver DMA service requests. Setting
the SCRIE bit and clearing the DMA receive enable bit, DMARE, in
SCC3 enables the SCRF bit to generate CPU interrupt requests.
Setting both SCRIE and DMARE enables SCRF to generate DMA
service requests. Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt or DMA service
requests
0 = SCRF not enabled to generate CPU interrupt or DMA service
requests
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
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I/O Registers
NOTE: When SCI receiver DMA service requests are enabled (DMARE = 1),
then SCI receiver CPU interrupt requests are disabled, and the state of
the ILIE bit has no effect.
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition
(logic 1). Clearing and then setting TE during a transmission queues
an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
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SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break
character followed by a logic 1. The logic 1 after the break character
guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s
between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit.
Toggling SBK before the preamble begins causes the SCI to send a
break character instead of a preamble.
SCI Control
Re g iste r 3
SCI control register 3:
•
Stores the ninth SCI data bit received and the ninth SCI data bit to
be transmitted.
•
•
•
Enables SCI receiver full (SCRF) DMA service requests.
Enables SCI transmitter empty (SCTE) DMA service requests.
Enables the following interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
– Parity error interrupts
Address: $0015
Bit 7
6
T8
U
5
4
3
ORIE
0
2
NEIE
0
1
FEIE
0
Bit 0
PEIE
0
Read:
Write:
Reset:
R8
DMARE DMATE
U
0
0
= Unimplemented
U = Unaffected
Figure 13. SCI Control Register 3 (SCC3)
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I/O Registers
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
DMARE — DMA Receive Enable Bit
This read/write bit enables the DMA to service SCI receiver DMA
service requests generated by the SCRF bit. Setting the DMARE bit
disables SCI receiver CPU interrupt requests. Reset clears the
DMARE bit.
1 = DMA enabled to service SCI receiver DMA service requests
generated by the SCRF bit (SCI receiver CPU interrupt
requests disabled)
0 = DMA not enabled to service SCI receiver DMA service requests
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
NOTE: To enable the SCRF bit to generate DMA service requests, the SCI
receive interrupt enable bit (SCRIE) must be set.
DMATE — DMA Transfer Enable Bit
This read/write bit enables SCI transmitter empty (SCTE) DMA
service requests. (See SCI Status Register 1 on page 273.) Setting
the DMATE bit disables SCTE CPU interrupt requests. Reset clears
DMATE.
1 = SCTE DMA service requests enabled
SCTE CPU interrupt requests disabled
0 = SCTE DMA service requests disabled
SCTE CPU interrupt requests enabled
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NOTE: To enable the SCTE bit to generate DMA service requests, the SCI
transmit interrupt enable bit (SCTIE) must be set.
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
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I/O Registers
SCI Sta tus Register 1
SCI status register 1 contains flags to signal the following conditions:
•
•
•
•
•
•
•
•
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
Address: $0016
Bit 7
6
5
4
3
2
1
Bit 0
PE
Read: SCTE
Write:
TC
SCRF
IDLE
OR
NF
FE
Reset:
1
1
0
0
0
0
0
0
= Unimplemented
Figure 14. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request or an SCI transmitter DMA service
request. When the SCTIE bit in SCC2 is set and the DMATE bit in
SCC3 is clear, SCTE generates an SCI transmitter CPU interrupt
request. With both the SCTIE and DMATE bits set, SCTE generates
an SCI transmitter DMA service request. In normal operation, clear
the SCTE bit by reading SCS1 with SCTE set and then writing to
SCDR. In DMA transfers, the DMA automatically clears the SCTE bit
when it writes to the SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
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NOTE: When DMATE = 1, a write by the CPU to the SCI data register can clear
the SCTE bit inadvertently and cause the DMA to miss a service request.
NOTE: Setting the TE bit for the first time also sets the SCTE bit. When enabling
SCI transmitter DMA service requests, set the TE bit after setting the
DMATE bit. Otherwise setting the TE and SCTIE bits generates an SCI
transmitter CPU interrupt request instead of a DMA service request.
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. When the DMA services an SCI transmitter DMA service request,
the DMA clears the TC bit by writing to the SCDR. TC is cleared
automatically when data, preamble, or break is queued and ready to
be sent. There may be up to 1.5 transmitter clocks of latency between
queueing data, preamble, and break and the transmission actually
starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request or an SCI receiver DMA service
request. When the SCRIE bit in SCC2 is set and the DMARE bit in
SCC3 is clear, SCRF generates a CPU interrupt request. With both
the SCRIE and DMARE bits set, SCRF generates a DMA service
request. In normal operation, clear the SCRF bit by reading SCS1
with SCRF set and then reading the SCDR. In DMA transfers, the
DMA clears the SCRF bit when it reads the SCDR. Reset clears
SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
NOTE: When DMARE = 1, a read by the CPU of the SCI data register can clear
the SCRF bit inadvertently and cause the DMA to miss a service request.
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I/O Registers
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI error CPU
interrupt request if the ILIE bit in SCC2 is also set and the DMARE bit
in SCC3 is clear. Clear the IDLE bit by reading SCS1 with IDLE set
and then reading the SCDR. After the receiver is enabled, it must
receive a valid character that sets the SCRF bit before an idle
condition can set the IDLE bit. Also, after the IDLE bit has been
cleared, a valid character must again set the SCRF bit before an idle
condition can set the IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1
and SCDR in the flag-clearing sequence. Figure 15 shows the normal
flag-clearing sequence and an example of an overrun caused by a
delayed flag-clearing sequence. The delayed read of SCDR does not
clear the OR bit because OR was not set when SCS1 was read. Byte 2
caused the overrun and is lost. The next flag-clearing sequence reads
byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the flag-clearing
routine can check the OR bit in a second read of SCS1 after reading the
data register.
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NORMAL FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 15. Flag Clearing Sequence
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the
RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in
SCC3 is also set. Clear the NF bit by reading SCS1 and then reading
the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
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I/O Registers
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
SCI Sta tus Register 2
SCI status register 2 contains flags to signal the following conditions:
•
•
Break character detected
Incoming data
Address: $0017
Bit 7
6
5
4
0
3
0
2
0
1
Bit 0
RPF
Read:
BKF
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 16. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break
character on the RxD pin. In SCS1, the FE and SCRF bits are also
set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.
BKF does not generate a CPU interrupt request or a DMA service
request. Clear BKF by reading SCS2 with BKF set and then reading
the SCDR. Once cleared, BKF can become set again only after logic
1s again appear on the RxD pin followed by another break character.
Reset clears the BKF bit.
1 = Break character detected
0 = No break character detected
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RPF —Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch), or when the
receiver detects an idle character. Polling RPF before disabling the
SCI module or entering stop mode can show whether a reception is
in progress.
1 = Reception in progress
0 = No reception in progress
SCI Da ta Re g iste r
The SCI data register is the buffer between the internal data bus and the
receive and transmit shift registers. Reset has no effect on data in the
SCI data register.
Address: $0018
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Unaffected by Reset
Figure 17. SCI Data Register (SCDR)
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading address $0018 accesses the read-only received data bits,
R7–R0. Writing to address $0018 writes the data to be transmitted,
T7–T0. Reset has no effect on the SCI data register.
NOTE: Do not use read-modify-write instructions on the SCI data register.
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I/O Registers
SCI Ba ud Ra te
Re g iste r
The baud rate register selects the baud rate for both the receiver and the
transmitter.
Address: $0019
Bit 7
0
6
5
SCP1
0
4
3
R
0
2
SCR2
0
1
SCR1
0
Bit 0
SCR0
0
Read:
Write:
Reset:
SCP0
0
0
= Unimplemented
R = Reserved
Figure 18. SCI Baud Rate Register (SCBR)
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown
in Table 9. Reset clears SCP1 and SCP0.
Table 9. SCI Baud Rate Prescaling
SCP[1:0]
Prescaler Divisor (PD)
00
01
10
11
1
3
4
13
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SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in
Table 10. Reset clears SCR2–SCR0.
Table 10. SCI Baud Rate Selection
SCR[2:1:0]
000
Baud Rate Divisor (BD)
1
2
001
010
4
011
8
100
16
32
64
128
101
110
111
Use the following formula to calculate the SCI baud rate:
fCrystal
Baud rate = ------------------------------------
64 × PD × BD
where:
f
= crystal frequency
Crystal
PD = prescaler divisor
BD = baud rate divisor
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SCI
I/O Registers
Table 11 shows the SCI baud rates that can be generated with a
4.9152-MHz crystal.
Table 11. SCI Baud Rate Selection Examples
Prescaler
Divisor
(PD)
Baud Rate
Divisor
(BD)
Baud Rate
= 4.9152 MHz)
SCP[1:0]
SCR[2:1:0]
(f
Crystal
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
1
1
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
1
2
76,800
38,400
19,200
9600
4800
2400
1200
600
1
4
1
8
1
16
32
64
128
1
1
1
1
3
25,600
12,800
6400
3200
1600
800
3
2
3
4
3
8
3
16
32
64
128
1
3
3
400
3
200
4
19,200
9600
4800
2400
1200
600
4
2
4
4
4
8
4
16
32
64
128
1
4
4
300
4
150
13
13
13
13
13
13
13
13
5908
2954
1477
739
2
4
8
16
32
64
128
369
185
92
46
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Inp ut/ Outp ut Ports
I/ O Ports
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
Port H Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
Data Direction Register H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
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I/ O Ports
Introd uc tion
Fifty-four bidirectional input-output (I/O) pins form eight parallel ports. All
I/O pins are programmable as inputs or outputs.
NOTE: Connect any unused I/O pins to an appropriate logic level, either V or
DD
V . Although the I/O ports do not require termination for proper
SS
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port A Data Register (PORTA) Write:
Reset:
Read:
Unaffected by Reset
PB4 PB3
Unaffected by Reset
PC4 PC3
Unaffected by Reset
PD4 PD3
Unaffected by Reset
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
PB7
PC7
PD7
PB6
PC6
PD6
PB5
PC5
PD5
PB2
PC2
PD2
PB1
PC1
PD1
PB0
PC0
PD0
Port B Data Register (PORTB) Write:
Reset:
Read:
Port C Data Register (PORTC) Write:
Reset:
Read:
Port D Data Register (PORTD) Write:
Reset:
Read:
Data Direction Register A (DDRA) Write:
Reset:
0
0
0
0
0
0
0
0
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Data Direction Register B (DDRB) Write:
Reset:
0
0
0
0
0
0
0
0
Read:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Data Direction Register C (DDRC) Write:
Reset:
0
0
0
0
0
0
0
0
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Data Direction Register D (DDRD) Write:
Reset:
0
0
0
0
0
0
0
0
Read:
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Port E Data Register (PORTE) Write:
Reset:
Unaffected by Reset
PF4 PF3
Unaffected by Reset
Read:
Port F Data Register (PORTF) Write:
Reset:
0
0
PF5
PF2
PF1
PF0
= Unimplemented
Figure 1. I/O Register Summary
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I/O Ports
Introduction
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
PG3
PG2
PG1
PG0
Port G Data Register (PORTG) Write:
Reset:
Unaffected by Reset
Read:
0
0
0
0
PH3
PH2
PH1
PH0
Port H Data Register (PORTH) Write:
Reset:
Unaffected by Reset
Read:
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
Data Direction Register E (DDRE) Write:
Reset:
Read:
0
0
0
0
0
0
0
DDRF3
0
0
DDRF2
0
0
DDRF1
0
0
DDRF0
0
DDRF5
DDRF4
Data Direction Register F (DDRF) Write:
Reset:
Read:
0
0
0
0
0
0
0
0
DDRG3 DDRG2 DDRG1 DDRG0
Data Direction Register G (DDRG) Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Data Direction Register H (DDRH) Write:
Reset:
DDRH3 DDRH2 DDRH1 DDRH0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 1. I/O Register Summary
Table 1. I/O Register Address Summary
Register PORTA PORTB PORTC PORTD DDRA DDRB DDRC DDRD PORTE PORTF
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009
Register PORTG PORTH DDRE
DDRF DDRG DDRH
Address $000A $000B $000C $000D $000E $000F
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I/ O Ports
Port A
Port A is an 8-bit, general-purpose bidirectional I/O port.
Port A Da ta
Re g iste r
PORTA contains the data latches for the eight port A pins.
Address: $0000
Bit 7
6
5
4
3
2
1
Bit 0
PA0
Read:
Write:
Reset:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
Unaffected by Reset
Figure 2. Port A Data Register (PORTA)
PA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
Da ta Dire c tion
Re g iste r A
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
Address: $0004
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0
0
0
0
0
0
0
0
Figure 3. Data Direction Register A (DDRA)
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I/O Ports
Port A
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
DDRAx
RESET
WRITE PORTA ($0000)
PAx
PAx
READ PORTA ($0000)
Figure 4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 2 summarizes the operation of
the port A pins.
Table 2. Port A Pin Operation
Access to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Pin
Write
(1)
0
1
Input, high-impedance
Output
Latch
Latch
Latch
1. Writing affects data register, but does not affect input.
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Port B
Port B is an 8-bit, general-purpose bidirectional I/O port.
Port B Da ta
Re g iste r
PORTB contains the data latches for the eight port B pins.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
PB0
Read:
Write:
Reset:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
Unaffected by Reset
Figure 5. Port B Data Register (PORTB)
PB[7:0] — Port B Data Bits
These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
Da ta Dire c tion
Re g iste r B
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
Address: $0005
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0
0
0
0
0
0
0
0
Figure 6. Data Direction Register B (DDRB)
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Port B
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 7 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
DDRBx
RESET
WRITE PORTB ($0001)
PBx
PBx
READ PORTB ($0001)
Figure 7. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 3 summarizes the operation of
the port B pins.
Table 3. Port B Pin Operation
Access to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Pin
Write
(1)
0
1
Input, high-impedance
Output
Latch
Latch
Latch
1. Writing affects data register, but does not affect input.
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Port C
Port C is an 8-bit, general-purpose bidirectional I/O port.
Port C Da ta
Re g iste r
PORTC contains the data latches for the eight port C pins.
Address: $0002
Bit 7
6
5
4
3
2
1
Bit 0
PC0
Read:
Write:
Reset:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
Unaffected by Reset
Figure 8. Port C Data Register (PORTC)
PC[7:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
Da ta Dire c tion
Re g iste r C
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer
for the corresponding port C pin; a logic 0 disables the output buffer.
Address: $0006
Bit 7
6
5
4
3
2
1
DDRC
0
Bit 0
DDRC0
0
Read:
Write:
Reset:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2
0
0
0
0
0
0
Figure 9. Data Direction Register C (DDRC)
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Port C
DDRC[7:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 10 shows the port C I/O logic.
READ DDRC ($0006)
WRITE DDRC ($0006)
DDRCx
RESET
WRITE PORTC ($0002)
PCx
PCx
READ PORTC ($0002)
Figure 10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PCx data
latch. When bit DDRCx is a logic 0, reading address $0002 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 4 summarizes the operation of
the port C pins.
Table 4. Port C Pin Operation
Access to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Pin
Write
(1)
0
1
Input, high-impedance
Output
Latch
Latch
Latch
1. Writing affects data register, but does not affect input.
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Port D
Port D is an 8-bit, general-purpose I/O port.
Port D Da ta
Re g iste r
PORTD contains the data latches for the eight port D pins.
Address: $0003
Bit 7
6
5
4
3
2
1
Bit 0
PD0
Read:
Write:
Reset:
PD7
PD6
PD5
PD4
PD3
PD2
PD1
Unaffected by Reset
Figure 11. Port D Data Register (PORTD)
PD[7:0] — Port D Data Bits
These read/write bits are software-programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
The keyboard interrupt enable bits, KBIE[7:0], in the keyboard
interrupt control register (KBICR), enable the port D pins as external
interrupt pins. (See External Interrupt Module on page 311.)
Da ta Dire c tion
Re g iste r D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
0
0
0
0
0
0
0
0
Figure 12. Data Direction Register D (DDRD)
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Port D
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 13 shows the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
DDRDx
RESET
WRITE PORTD ($0003)
PDx
PDx
READ PORTD ($0003)
Figure 13. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PDx data
latch. When bit DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 5 summarizes the operation of
the port D pins.
Table 5. Port D Pin Operation
Access to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Pin
Write
(1)
0
1
Input, high-impedance
Output
Latch
Latch
Latch
1. Writing affects data register, but does not affect input.
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Port E
Port E is an 8-bit special function port that shares five of its pins with the
timer interface module (TIM) and two of its pins with the serial
communications interface module (SCI).
Port E Da ta
Re g iste r
PORTE contains the data latches for the eight port E pins.
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
PE0
Read:
Write:
Reset:
PE7
PE6
PE5
PE4
PE3
PE2
PE1
Unaffected by Reset
TCH0 TCLK
Alternate
Function:
TCH3
TCH2
TCH1
TxD
RxD
Figure 14. Port E Data Register (PORTE)
PE[7:0] — Port E Data Bits
PE[7:0] are read/write, software programmable bits. Data direction of
each port E pin is under the control of the corresponding bit in data
direction register E.
TCH[3:0] — Timer Channel I/O Bits
The PE7/TCH3–PE4/TCH0 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PE7/TCH3–PE4/TCH0 pins are timer channel I/O pins or
general-purpose I/O pins. (See Timer Interface Module on page
171.)
NOTE: Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 6.)
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Port E
TCLK — Timer Clock Input
The PE3/TCLK pin is the external clock input for the TIM. The
prescaler select bits, PS[2:0], select PE3/TCLK as the TIM clock
input. (See Timer Interface Module on page 171.) When not
selected as the TIM clock, PE3/TCLK is available for general-purpose
I/O.
TxD — SCI Transmit Data Output
The PE2/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled
and the PE2/TxD pin is available for general-purpose I/O. (See Serial
Communications Interface Module on page 235.)
NOTE: Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 6.)
RxD — SCI Receive Data Input
The PE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled and
the PE1/RxD pin is available for general-purpose I/O. (See Serial
Communications Interface Module on page 235.)
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Da ta Dire c tion
Re g iste r E
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
Address: $000C
Bit 7
DDR37
0
6
5
4
3
2
1
DDTE1
0
Bit 0
DDRE0
0
Read:
Write:
Reset:
DDRE6 DDRE5 DDRE4 DDRE3 DDRE2
0
0
0
0
0
Figure 15. Data Direction Register E (DDRE)
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[7:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE: Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 16 shows the port E I/O logic.
READ DDRE ($000C)
WRITE DDRE ($000C)
DDREx
RESET
WRITE PORTE ($0008)
PEx
PEx
READ PORTE ($0008)
Figure 16. Port E I/O Circuit
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I/O Ports
Port F
When bit DDREx is a logic 1, reading address $0008 reads the PEx data
latch. When bit DDREx is a logic 0, reading address $0008 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 6 summarizes the operation of
the port E pins.
Table 6. Port E Pin Operation
Access to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Pin
Write
(1)
0
1
Input, high-impedance
Output
Latch
Latch
Latch
1. Writing affects data register, but does not affect input.
Port F
PORTF is a 6-bit, special function port that shares four of its pins with
the serial peripheral interface module (SPI).
Port F Da ta
Re g iste r
PORTF contains the data latches for the six port F pins.
Address: $0009
Bit 7
0
6
0
5
4
3
2
1
Bit 0
PF0
Read:
Write:
Reset:
PF5
PF4
PF3
PF2
PF1
Unaffected by Reset
MISO
Alternate
Function:
MOSI
SPSCK
SS
= Unimplemented
Figure 17. Port F Data Register (PORTF)
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PF[5:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of
each port F pin is under the control of the corresponding bit in data
direction register F. Reset has no effect on PF[5:0].
MISO — Master In/Slave Out
The PF3/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled and the PF3/MISO pin is available for general-purpose I/O.
(See Serial Peripheral Interface Module on page 201.)
NOTE: Data direction register F (DDRF) does not affect the data direction of port
F pins that are being used by the SPI module. However, the DDRF bits
always determine whether reading port F returns the states of the
latches or the states of the pins. (See Table 7.)
MOSI — Master Out/Slave In
The PF2/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PPF2/MOSI pin is available for
general-purpose I/O. (See Serial Peripheral Interface Module on
page 201.)
SPSCK — SPI Serial Clock
The PF1/SPSCK pin is the serial clock input of the SPI module. When
the SPE bit is clear, the PF1/SPSCK pin is available for
general-purpose I/O.
SS — Slave Select
The PF0/SS pin is the slave select input of the SPI module. When the
SPE bit is clear or when the SPI master bit, SPMSTR, is set, the
PF0/SS pin is available for general-purpose I/O. (See Serial
Peripheral Interface Module on page 201.) When the SPI is
enabled, the DDRF0 bit in data direction register F (DDRF) has no
effect on the PF0/SS pin.
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I/O Ports
Port F
Da ta Dire c tion
Re g iste r F
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic 1 to a DDRF bit enables the output buffer for
the corresponding port F pin; a logic 0 disables the output buffer.
Address: $000D
Bit 7
0
6
5
DDRF5
0
4
DDRF4
0
3
DDRF3
0
2
DDRF2
0
1
DDRF1
0
Bit 0
DDRF0
0
Read:
Write:
Reset:
0
= Unimplemented
Figure 18. Data Direction Register F (DDRF)
DDRF[5:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears
DDRF[5:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE: Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 19 shows the port F I/O logic.
READ DDRF ($000D)
WRITE DDRF ($000D)
DDRFx
RESET
WRITE PORTF ($0009)
PFx
PFx
READ PORTF ($0009)
Figure 19. Port F I/O Circuit
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I/ O Ports
When bit DDRFx is a logic 1, reading address $0009 reads the PFx data
latch. When bit DDRFx is a logic 0, reading address $0009 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 7 summarizes the operation of
the port F pins.
Table 7. Port F Pin Operation
Access to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Pin
Write
(1)
0
1
Input, high-impedance
Output
Latch]
Latch
Latch
1. Writing affects data register, but does not affect input.
Port G
Port G is a 4-bit, general-purpose bidirectional I/O port.
NOTE: Port G is available only on the 64-pin QFP.
Port G Da ta
Re g iste r
PORTG contains the data latches for the four port G pins.
Address: $000A
Bit 7
0
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
PG3
PG2
PG1
PG0
Unaffected by Reset
= Unimplemented
Figure 20. Port G Data Register (PORTG)
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I/O Ports
Port G
PG[3:0] — Port G Data Bits
These read/write bits are software-programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register G. Reset has no effect on port G data.
Da ta Dire c tion
Re g iste r G
Data direction register G determines whether each port G pin is an input
or an output. Writing a logic 1 to a DDRG bit enables the output buffer
for the corresponding port G pin; a logic 0 disables the output buffer.
Address: $000E
Bit 7
0
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
DDRG3 DDRG2 DDRG1 DDRG0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 21. Data Direction Register G (DDRG)
DDRG[3:0] — Data Direction Register G Bits
These read/write bits control port G data direction. Reset clears
DDRG[3:0], configuring all port G pins as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE: Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 22 shows the port G I/O logic.
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I/ O Ports
READ DDRG ($000E)
WRITE DDRG ($000E)
DDRGx
RESET
WRITE PORTG ($000A)
PGx
PGx
READ PORTG ($000A)
Figure 22. Port G I/O Circuit
When bit DDRGx is a logic 1, reading address $000A reads the PGx
data latch. When bit DDRGx is a logic 0, reading address $000A reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 8 summarizes the
operation of the port G pins.
Table 8. Port G Pin Operation
Access to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Pin
Write
(1)
0
1
Input, high-impedance
Output
Latch]
Latch
Latch
1. Writing affects data register, but does not affect input.
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I/O Ports
Port H
Port H
Port H is a 4-bit, general-purpose bidirectional I/O port.
NOTE: Port H is available only on the 64-pin QFP.
Port H Da ta
Re g iste r
PORTH contains the latches for the four port H pins.
Address: $000B
Bit 7
0
6
0
5
0
4
0
3
2
1
Bit 0
PH0
Read:
Write:
Reset:
PH3
PH2
PH1
Unaffected by Reset
= Unimplemented
Figure 23. Port H Data Register (PORTH)
PH[3:0] — Port H Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register H. Reset has no effect on port H data.
Da ta Dire c tion
Re g iste r H
Data direction register H determines whether each port H pin is an input
or an output. Writing a logic 1 to a DDRH bit enables the output buffer
for the corresponding port H pin; a logic 0 disables the output buffer.
Address: $000F
Bit 7
0
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
DDRH3 DDRH2 DDRH1 DDRH0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 24. Data Direction Register H (DDRH)
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I/ O Ports
DDRH[3:0] — Data Direction Register H Bits
These read/write bits control port H data direction. Reset clears
DDR[3:0], configuring all port H pins as inputs.
1 = Corresponding port H pin configured as output
0 = Corresponding port H pin configured as input
NOTE: Avoid glitches on port H pins by writing to the port H data register before
changing the data direction register H bits from 0 to 1.
Figure 25 shows the port H I/O logic.
READ DDRH ($000F)
WRITE DDRH ($000F)
DDRHx
RESET
WRITE PORTH ($000B)
PHx
PHx
READ PORTH ($000B)
Figure 25. Port H I/O Circuit
When bit DDRHx is a logic 1, reading address $000B reads the PHx data
latch. When bit DDRHx is a logic 0, reading address $000B reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 9 summarizes the operation of
the port H pins.
Table 9. Port H Pin Operation
Access to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Pin
Write
(1)
0
1
Input, high-impedance
Output
Latch
Latch
Latch
1. Writing affects data register, but does not affect input.
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Com p ute r Op e ra ting Prop e rly Mod ule
COP
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
COPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
COPRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . .310
Introd uc tion
The COP module contains a free-running counter that generates a reset
if allowed to overflow. The COP module helps software recover from
runaway code. Prevent a COP reset by periodically clearing the COP
counter.
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COP
Func tiona l De sc rip tion
12-BIT COP PRESCALER
CGMXCLK
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
RESET
RESET STATUS
REGISTER
6-BIT COP COUNTER
COPD FROM CONFIG
RESET
CLEAR COP
COPCTL WRITE
COUNTER
COPRS FROM CONFIG
Figure 1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler. If not cleared by software, the COP counter overflows and
13
4
18
4
generates an asynchronous reset after 2 – 2 or 2 – 2 CGMXCLK
cycles, depending on the state of the COP rate select bit, COPRS, in the
configuration register. When COPRS = 0, a 4.9152-MHz crystal gives a
COP timeout period of 53.3 ms. Writing any value to location $FFFF
before an overflow occurs prevents a COP reset by clearing the COP
counter and stages 5 through 12 of the prescaler.
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COP
I/O Signals
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is
held at V + V . During the break state, V + V on the RST pin
DD
Hi
DD
Hi
disables the COP.
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
I/ O Sig na ls
The following paragraphs describe the signals shown in Figure 1.
CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
STOP Instruc tion
COPCTL Write
The STOP instruction clears the COP prescaler.
Writing any value to the COP control register (COPCTL) (see COP
Control Register on page 308) clears the COP counter and clears
stages 12 through 5 of the COP prescaler. Reading the COP control
register returns the reset vector.
Powe r-On Re se t
The power-on reset (POR) circuit clears the COP prescaler 4096
CGMXCLK cycles after power-up.
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COP
Inte rna l Re se t
Re se t Ve c tor Fe tc h
An internal reset clears the COP prescaler and the COP counter.
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
COPD
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register. (See Configuration Register on page 39.)
COPRS
The COPRS signal reflects the state of the COP rate select bit.
COP Control Re g iste r
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Low byte of reset vector
Clear COP counter
Unaffected by Reset
Figure 2. COP Control Register (COPCTL)
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COP
Interrupts
Inte rrup ts
The COP does not generate CPU interrupt requests or DMA service
requests.
Monitor Mod e
The COP is disabled in monitor mode when V + V is present on the
DD
Hi
IRQ1/VPP pin or on the RST pin.
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
Wa it Mod e
Stop Mod e
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine
or a DMA service routine.
Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
The STOP bit in the configuration register (CONFIG) enables the STOP
instruction. To prevent inadvertently turning off the COP with a STOP
instruction, disable the STOP instruction by clearing the STOP bit.
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COP
COP Mod ule During Bre a k Inte rrup ts
The COP is disabled during a break interrupt when V + V is present
DD
Hi
on the RST pin.
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Exte rna l Inte rrup t Mod ule
IRQ
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
IRQ1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
IRQ2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .318
IRQ Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .318
Introd uc tion
The IRQ module provides two independently maskable external
interrupt pins.
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IRQ
Fe a ture s
Features of the IRQ module include the following:
•
Two Dedicated External Interrupt Pins with Separate External
Interrupt Masks
•
•
•
•
Hysteresis Buffers
Programmable Edge-Only or Edge- and Level- Interrupt Sensitivity
Automatic Interrupt Acknowledge
Exit from Low-Power Modes
Func tiona l De sc rip tion
A logic 0 applied to any of the external interrupt pins can latch a CPU
interrupt request. Figure 1 shows the structure of the IRQ module.
Interrupt signals on the IRQ1 pin are latched separately from interrupt
signals on the IRQ2 pin. CPU interrupt requests remain latched until one
of the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the CPU interrupt request that
caused the vector fetch.
•
Software clear — Software can clear a latched CPU interrupt
request by writing to the appropriate acknowledge bit in the
interrupt status and control register (ISCR). Writing a logic 1 to the
ACK1 bit clears the IRQ1 CPU interrupt request. Writing a logic 1
to the ACK2 bit clears the IRQ2 CPU interrupt request.
•
Reset — A reset automatically clears both IRQ1 and IRQ2 CPU
interrupt requests.
All of the external interrupt pins are falling-edge-triggered and are
software-configurable to be both falling-edge and low-level-triggered.
The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ1
pin. The MODE2 bit controls the triggering sensitivity of the IRQ2 pin.
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IRQ
Functional Description
I N T E R N A L A D D R E S S B U S
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IRQ
When an interrupt pin is edge-triggered only, the CPU interrupt request
remains latched until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
CPU interrupt request remains latched until both of the following occur:
•
•
Vector fetch or software clear
Return of the interrupt pin to logic 1
The vector fetch or software clear can occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the CPU interrupt request
remains pending. A reset clears the CPU interrupt request and the
MODEx control bit even if the pin stays low.
When set, the IMASK1 and IMASK2 bits in the ISCR mask all external
interrupt requests. A latched CPU interrupt request is not presented to
the interrupt priority logic unless the corresponding IMASK bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
CPU interrupt requests, including external interrupt requests.
IRQ1 Pin
A logic 0 on the IRQ1 pin can latch a CPU interrupt request. A vector
fetch, software clear, or reset clears the IRQ1 CPU interrupt request.
If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE1 set, both of the following actions must
occur to clear the IRQ1 CPU interrupt request:
•
Vector fetch, software clear, or reset — A vector fetch generates
an interrupt acknowledge signal to clear the CPU interrupt
request. Software can generate the interrupt acknowledge signal
by writing a logic 1 to the ACK1 bit in the interrupt status and
control register (ISCR). The ACK1 bit is useful in applications that
poll the IRQ1 pin and require software to clear the IRQ1 CPU
interrupt request. Writing to the ACK1 bit before leaving an
interrupt service routine can also prevent spurious interrupts due
to noise. Setting ACK1 does not affect subsequent transitions on
the IRQ1 pin. A falling edge that occurs after writing to the ACK1
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IRQ
Functional Description
bit latches another CPU interrupt request. If the IRQ1 mask bit,
IMASK1, is clear, the CPU loads the program counter with the
vector address at locations $FFFA and $FFFB.
•
Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at
logic 0, the IRQ1 CPU interrupt request remains latched.
The vector fetch, software clear, or reset and the return of the IRQ1 pin
to logic 1 can occur in any order. A reset clears the CPU interrupt request
and the MODE1 bit, clearing the CPU interrupt request even if the pin
stays low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only.
With MODE1 clear, a vector fetch or software clear immediately clears
the IRQ1 CPU interrupt request.
The IRQF1 bit in the ISCR register can be used to check for pending
CPU interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which
makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE: To avoid spurious CPU interrupts caused by noise, mask CPU interrupt
requests in the interrupt routine when using the level-sensitive interrupt
trigger.
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IRQ2 Pin
A logic 0 on the IRQ2 pin can latch a CPU interrupt request. A vector
fetch, software clear, or reset clears the IRQ2 CPU interrupt request.
If the MODE2 bit is set, the IRQ2 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE2 set, both of the following actions must
occur to clear an IRQ2 CPU interrupt request:
•
Vector fetch, software clear, or reset — A vector fetch generates
an interrupt acknowledge signal to clear the CPU interrupt
request. Software can generate the interrupt acknowledge signal
by writing a logic 1 to the ACK2 bit in the interrupt status and
control register (ISCR). The ACK2 bit is useful in applications that
poll the IRQ2 pin and require software to clear the IRQ2 CPU
interrupt request. Writing to the ACK2 bit before leaving an
interrupt service routine can also prevent spurious CPU interrupts
due to noise. Setting ACK2 does not affect subsequent transitions
on the IRQ2 pin. A falling edge that occurs after writing to the
ACK2 bit latches another CPU interrupt request. If the IRQ2 mask
bit, IMASK2, is clear, the CPU loads the program counter with the
vector address at locations $FFE0 and $FFE1.
•
Return of the IRQ2 pin to logic 1 — As long as the IRQ2 pin is at
logic 0, the IRQ2 CPU interrupt request remains latched.
The vector fetch, software clear, or reset and the return of the IRQ2 pin
to logic 1 can occur in any order. A reset clears the CPU interrupt request
and the MODE2 bit, clearing the CPU interrupt request even if the pin
stays low.
If the MODE2 bit is clear, the IRQ2 pin is falling-edge-sensitive only.
With MODE2 clear, a vector fetch or software clear immediately clears
the IRQ2 CPU interrupt request.
The IRQF2 bit in the ISCR register can be used to check for pending
CPU interrupts. The IRQF2 bit is not affected by the IMASK2 bit, which
makes it useful in applications where polling is preferred.
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IRQ
Low-Power Modes
There is no direct way to determine the logic level on the IRQ2 pin.
However, it is possible to use the IRQF2 bit in the ISCR to infer the state
of the IRQ2 pin. If the MODE2 bit is a logic 1, the IRQF2 bit in the ISCR
is the opposite value of the IRQ2 pin as long as the IRQ2 CPU interrupt
request is cleared. (See Figure 1.) Clear the IRQ2 CPU interrupt request
by writing a logic 1 to the acknowledge bit. Recall, however, that every
falling edge on the IRQ2 pin latches an IRQ2 CPU interrupt request. So
an additional acknowledge is necessary after each falling edge on IRQ2
to maintain the opposite relationship between IRQF2 and the IRQ2 pin.
Set the IMASK2 bit in the ISCR to prevent the IRQF2 from generating
CPU interrupts when used in this manner.
NOTE: To avoid spurious CPU interrupts caused by noise, mask CPU interrupt
requests in the interrupt routine when using the level-sensitive interrupt
trigger.
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
Wa it Mod e
Stop Mod e
The IRQ module remains active in wait mode. Clearing the IMASK1 or
IMASK2 bit in the IRQ status and control register enables IRQ1 or IRQ2
CPU interrupt requests to bring the MCU out of wait mode.
The IRQ module remains active in stop mode. Clearing the IMASK1 or
IMASK2 bit in the IRQ status and control register enables IRQ1 or IRQ2
CPU interrupt requests to bring the MCU out of stop mode.
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IRQ
IRQ Mod ule During Bre a k Inte rrup ts
The BCFE bit in the break flag control register (BFCR) enables software
to clear CPU interrupt requests during the break state. (See Break
Module on page 149.)
To allow software to clear IRQ1 and IRQ2 CPU interrupt requests during
a break interrupt, write a logic 1 to the BCFE bit. If a CPU interrupt
request is cleared during the break state, it remains cleared when the
MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to
the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK1
and ACK2 bits in the IRQ status and control register during the break
state has no effect on the IRQ interrupt flags.
IRQ Sta tus a nd Control Re g iste r
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has the following functions:
•
•
•
•
Shows the state of the IRQ1 and IRQ2 interrupt flags
Clears IRQ1 and IRQ2 CPU interrupt flags
Masks IRQ1 and IRQ2 CPU interrupt requests
Controls triggering sensitivity of the IRQ1 and IRQ2 CPU interrupt
pins
Address: $0032
Bit 7
6
0
5
4
3
2
0
1
Bit 0
Read: IRQF2
Write:
IRQF1
IMASK2 MODE2
IMASK1 MODE1
ACK2
ACK1
Reset:
= Unimplemented
Figure 2. IRQ Status and Control Register (ISCR)
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IRQ
IRQ Status and Control Register
IRQ2F — IRQ2 Flag
This read-only bit is high when an IRQ2 CPU interrupt is pending.
Reset clears IRQ2F.
1 = IRQ2 CPU interrupt pending
0 = IRQ2 CPU interrupt not pending
ACK2 — IRQ2 Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ2 CPU interrupt
request. ACK2 always reads as logic 0. Reset clears ACK2.
IMASK2 — IRQ2 Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ2 CPU interrupt
requests. Reset clears IMASK2.
1 = IRQ2 CPU interrupt requests masked
0 = IRQ2 CPU interrupt requests not masked
MODE2 — IRQ2 Interrupt Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ2 pin.
Reset clears MODE2.
1 = IRQ2 CPU interrupt requests on falling edges and low levels
0 = IRQ2 CPU interrupt requests on falling edges only
IRQ1F — IRQ1 Flag
This read-only bit is high when an IRQ1 CPU interrupt is pending.
1 = IRQ1 CPU interrupt pending
0 = IRQ1 CPU interrupt not pending
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ1 CPU interrupt
request. ACK1 always reads as logic 0. Reset clears ACK1.
IMASK1 — IRQ1 Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ1 CPU interrupt
requests. Reset clears IMASK1.
1 = IRQ1 CPU interrupt requests masked
0 = IRQ1 CPU interrupt requests not masked
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IRQ
MODE1 — IRQ1 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1 pin.
Reset clears MODE1.
1 = IRQ1 CPU interrupt requests on falling edges and low levels
0 = IRQ1 CPU interrupt requests on falling edges only
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Ke yb oa rd Inte rrup t Mod ule
KBI
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . . . . . .326
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
Keyboard Status and Control Register . . . . . . . . . . . . . . . . . . . . .327
Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . .328
Introd uc tion
The keyboard module provides eight independently maskable external
interrupt pins.
Fe a ture s
•
Eight Keyboard Interrupt Pins with Separate Keyboard Interrupt
Enable Bits and One Keyboard Interrupt Mask
•
•
•
•
Hysteresis Buffers
Programmable Edge-Only or Edge- and Level- Interrupt Sensitivity
Automatic Interrupt Acknowledge
Exit from Low-Power Modes
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KBI Sp e c ific a tion
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KBI
Functional Description
Func tiona l De sc rip tion
Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register
independently enables or disables each port D pin as a keyboard
interrupt pin. Enabling a keyboard interrupt pin also enables its internal
pullup device. A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes
low after all were high. The MODEK bit in the keyboard status and
control register controls the triggering mode of the keyboard interrupt.
•
If the keyboard interrupt is edge-sensitive only, a falling edge on a
keyboard pin does not latch an interrupt request if another
keyboard pin is already low. To prevent losing an interrupt request
on one pin because another pin is still low, software can disable
the latter pin while it is low.
•
If the keyboard interrupt is falling edge- and low level-sensitive, an
interrupt request is present as long as any keyboard pin is low.
If the MODEK bit is set, the keyboard interrupt pins are both falling edge-
and low level-sensitive, and both of the following actions must occur to
clear a keyboard interrupt request:
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register (KBSCR). The ACKK bit is useful in applications that poll
the keyboard interrupt pins and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFDE and
$FFDF.
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KBI
•
Return of all enabled keyboard interrupt pins to logic 1 — As long
as any enabled keyboard interrupt pin is at logic 0, the keyboard
interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is
falling-edge-sensitive only. With MODEK clear, a vector fetch or
software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data
direction register to configure the pin as an input and read the data
register.
NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.
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KBI
Keyboard Initialization
Ke yb oa rd Initia liza tion
When a keyboard interrupt pin is enabled, it takes time for the internal
pullup to reach a logic 1. Therefore a false interrupt can occur as soon
as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the
keyboard status and control register.
2. Enable the KB pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register
to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRD bits in data direction register D.
2. Write logic 1s to the appropriate port D data register bits.
3. Enable the KB pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
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KBI
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
Wa it Mod e
Stop Mod e
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
Ke yb oa rd Mod ule During Bre a k Inte rrup ts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Break Module on page
149.)
To allow software to clear the KEYF bit during a break interrupt, write a
logic 1 to the BCFE bit. If KEYF is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the KEYF bit during the break state, write a logic 0 to the
BCFE bit. With BCFE at logic 0, writing to the keyboard acknowledge bit
(ACKK) in the keyboard status and control register during the break state
has no effect. (See Keyboard Status and Control Register on page
327.)
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KBI
I/O Registers
I/ O Re g iste rs
The following registers control and monitor operation of the keyboard
module:
•
•
Keyboard status and control register (KBSCR)
Keyboard interrupt enable register (KBIER)
Ke yb oa rd Sta tus
a nd Control
Re g iste r
The keyboard status and control register:
•
•
•
•
Flags keyboard interrupt requests.
Acknowledges keyboard interrupt requests.
Masks keyboard interrupt requests.
Controls keyboard interrupt triggering sensitivity.
Address: $001A
Bit 7
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
0
KEYF
0
ACKK
0
IMASKK MODEK
0
0
0
0
0
0
0
= Unimplemented
Figure 3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending. Reset
clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
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KBI
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt
request. ACKK always reads as logic 0. Reset clears ACKK.
IMASKK — Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests. Reset
clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
Ke yb oa rd
Inte rrup t Ena b le
Re g iste r
The keyboard interrupt enable register enables or disables each port D
pin to operate as a keyboard interrupt pin.
Address: $001B
Bit 7
KBIE7
0
6
KBIE6
0
5
KBIE5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
Figure 4. Keyboard Interrupt Enable Register (KBIER)
KBIE[7:0] — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard
interrupt pin to latch interrupt requests. Reset clears the keyboard
interrupt enable register.
1 = PDx pin enabled as keyboard interrupt pin
0 = PDx pin not enabled as keyboard interrupt pin
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Low-Volta g e Inhib it Mod ule
LVI
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
Polled LVI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
LVI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
Introd uc tion
The low-voltage inhibit module monitors the voltage on the V pin and
DD
can force a reset when the V voltage falls to the LVI trip voltage.
DD
Fe a ture s
Features of the LVI module include the following:
•
•
•
Programmable LVI Reset
Programmable Power Consumption
Programmable stop mode operation
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LVI
Func tiona l De sc rip tion
Figure 1 shows the structure of the LVI module. The LVI module
contains a bandgap reference circuit and comparator. Clearing the LVI
power disable bit, LVIPWRD, enables the LVI to monitor V voltage.
DD
Clearing the LVI reset disable bit, LVIRSTD, enables the LVI module to
generate a reset when V falls below a voltage, V
. Setting the LVI
DD
LVR
enable in stop mode bit, LVISTOP, enables the LVI to operate in stop
mode. LVIPWRD, LVIRSTD, and LVISTOP are in the configuration
register.
Once an LVI reset occurs, the MCU remains in reset until V rises
DD
above a voltage, V
+ H
. A power-on reset occurs when V
LVR
LVR DD
reaches V
+ H
.The output of the comparator controls the state of
LVR
LVR
the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V
DD
STOP INSTRUCTION
LVISTOP
FROM CONFIG
FROM CONFIG
LVIRSTD
LVIPWRD
FROM CONFIG
V
> LVI = 0
LVI RESET
DD
Trip
LOW V
DD
DETECTOR
V
≤ LVI = 1
DD
Trip
LVIOUT
Figure 1. LVI Module Block Diagram
Polle d LVI
Op e ra tion
In applications that can operate at V levels below the V
level,
DD
LVR
software can monitor V by polling the LVIOUT bit. In the configuration
DD
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
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LVI
LVI Status Register
Forc e d Re se t
Op e ra tion
In applications that require V to remain above the V
enabling LVI resets allows the LVI module to reset the MCU when V
trip level,
DD
LVR
DD
falls to the V
level. In the configuration register, the LVIPWRD and
LVR
LVIRSTD bits must be at logic 0 to enable the LVI module and to enable
LVI resets.
LVI Sta tus Re g iste r
The LVI status register flags V voltages below the V
level.
LVR
DD
Address: $FE0F
Bit 7
Read: LVIOUT
Write:
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V voltage falls below the
DD
V
trip voltage. (See Table 1.) Reset clears the LVIOUT bit.
LVR
Table 1. LVIOUT Bit Indication
V
LVIOUT
DD
V
> V
+ H
0
DD
LVR
LVR
V
< V
1
DD
LVR
LVR
V
< V < V
+ H
LVR
Previous Value
LVR
DD
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LVI
LVI Inte rrup ts
The LVI module does not generate CPU interrupt requests.
Low-Powe r Mod e s
The STOP and WAIT instructions put the MCU in low power-consump-
tion standby modes.
Wa it Mod e
Stop Mod e
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets, the LVI module can generate a reset and bring the
MCU out of wait mode.
If enabled, the LVI module remains active in stop mode. If enabled to
generate resets, the LVI module can generate a reset and bring the
MCU out of stop mode.
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Sp e c ific a tions
Sp e c ific a tions
Conte nts
Preliminary Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .333
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . .343
Clock Generation Module Electrical Characteristics . . . . . . . . . .343
Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
Pre lim ina ry Ele c tric a l Sp e c ific a tions
These electrical and timing specifications are design targets and have
not been fully characterized.
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Sp e c ific a tions
Ma xim um Ra ting s
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
(1)
Table 1. Maximum Ratings
Characteristic
Supply Voltage
Symbol
Value
Unit
V
V
–0.3 to +6.0
DD
V
V
– 0.3 to V + 0.3
Input Voltage
V
In
SS
DD
V
V
– 0.3 to + 14.0
SS
Programming Voltage
Maximum Current Per Pin
V
PP
I
±25
mA
Excluding V and V
DD
SS
T
Storage Temperature
–55 to +150
100
°C
mA
mA
stg
I
Maximum Current out of V
Maximum Current into V
SS
mvss
I
100
DD
mvdd
1. Voltages referenced to V
.
SS
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to Table 4 on page 336 and Table 5 on page 337 for
guaranteed operating conditions.
2-spec_a
MC68HC708XL36
334
Specifications
MOTOROLA
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Specifications
Preliminary Electrical Specifications
Func tiona l
Op e ra ting Ra ng e
Table 2. Operating Range
Characteristic
Symbol
Value
Unit
T
Operating Temperature Range
–40 to +85
°C
A
3.3 ±10%
5.0 ±10%
V
Operating Voltage Range
V
DD
The rm a l
Cha ra c te ristic s
Table 3. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal Resistance
QFP (64 pin)
SDIP (56 pin)
θ
85
50
°C/W
JA
P
I/O Pin Power Dissipation
User-Determined
W
W
I/O
P = (I × V ) + P =
I/O
D
DD
DD
(1)
P
Power Dissipation
D
K/(T + 273 °C)
J
P x (T + 273 °C)
J
A
(2)
Constant
K
W°C
2
+ P × θ
D
JA
T
T + (P × θ
)
Average Junction Temperature
Maximum Junction Temperature
°C
°C
J
A
D
JA
T
125
JM
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined for a known T and measured
A
P . With this value of K, P and T can be determined for any value of T .
D
D
J
A
3-spec_a
MC68HC708XL36
335
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Specifications
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Sp e c ific a tions
DC Ele c tric a l
Cha ra c te ristic s
(1)
Table 4. DC Electrical Characteristics (V = 5.0 Vdc ± 10%)
DD
(2)
Characteristic
Symbol
Min
Max
—
Unit
V
Typ
Output High Voltage
(I
= –2.0 mA) All I/O Pins
V
V
– 0.8
—
Load
OH
DD
Output Low Voltage
(I = 1.6 mA) All I/O Pins
V
—
—
0.4
V
Load
OL
Input High Voltage
All Ports, IRQs, RESET, OSC1
V
0.7 x V
V
—
V
IH
DD
DD
Input Low Voltage
All Ports, IRQs, RESET, OSC1
V
V
0.3 x V
DD
—
V
IL
SS
V
Supply Current
DD
(3)
Run
Wait
—
—
—
—
30
12
mA
mA
(4)
(5)
I
DD
Stop
—
—
—
—
—
—
—
—
5
15
320
380
µA
µA
µA
µA
25 °C
0 °C to 85 °C
25 °C with LVI Enabled
0 °C to 85 °C with LVI Enabled
I
I/O Ports Hi-Z Leakage Current
Input Current
—
—
—
—
±10
µA
µA
IL
I
1
In
C
Capacitance
Ports (Input or Output)
Out
—
—
—
—
12
8
pF
C
In
V
Low-Voltage Inhibit Reset
2.6
60
0
2.7
80
2.8
100
100
800
—
V
LVR
H
Low-Voltage Inhibit Reset/Recover Hysteresis
mV
LVR
(6)
V
POR ReArm Voltage
—
mV
POR
(7)
V
POR Reset Voltage
0
700
—
mV
PORRST
(8)
R
POR Rise Time Ramp Rate
0.035
V/ms
POR
1. V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T , unless otherwise noted.
SS A L H
DD
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I measured using external square wave clock source (f = 32.8 MHz). All inputs 0.2 V
DD
osc
from rail. No dc loads. Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs.
L
OSC2 capacitance linearly affects run I . Measured with all modules enabled.
4. Wait I measured using external square wave clock source (f
dc loads. Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 ca-
pacitance linearly affects wait I . Measured with PLL and LVI enabled.
measured with OSC1 = V
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
DD
= 32.8 MHz). All inputs 0.2 V from rail. No
DD
osc
L
DD
5. Stop I
.
DD
SS
8. If minimum V
is not reached before the internal POR reset is released, RST must be driven low externally
DD
until minimum V
is reached.
DD
4-spec_a
MC68HC708XL36
336
Specifications
MOTOROLA
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Specifications
Preliminary Electrical Specifications
(1)
Table 5. DC Electrical Characteristics (V = 3.3 Vdc ± 10%)
DD
(2)
Characteristic
Output High Voltage
(I = –2.0 mA) All Ports
Symbol
Min
Max
—
Unit
V
Typ
V
VDD – 0.8
—
—
—
—
—
Load
Output Low Voltage
(I = 1.6 mA) All Ports
OH
V
0.4
V
Load
OL
Input High Voltage
All Ports, IRQs, RESET, OSC1
V
0.7 x V
V
V
IH
DD
DD
Input Low Voltage
All Ports, IRQs, RESET, OSC1
V
V
0.3 x V
DD
V
IL
SS
V
Supply Current
DD
(3)
Run
Wait
—
—
—
—
10
6
mA
mA
(4)
(5)
I
DD
Stop
—
—
—
—
—
—
—
—
3
10
200
250
µA
µA
µA
µA
25 °C
0 °C to 85 °C
25 °C with LVI Enabled
0 °C to 85 °C with LVI Enabled
I
I/O Ports Hi-Z Leakage Current
Input Current
—
—
—
—
±10
µA
µA
IL
I
1
In
C
Capacitance
Ports (Input or Output)
Out
—
—
—
—
12
8
pF
C
In
V
Low-Voltage Inhibit Reset
2.6
60
0
2.7
80
2.8
100
200
800
—
V
LVR
H
Low-Voltage Inhibit Reset/Recover Hysteresis
mV
LVR
(6)
V
POR ReArm Voltage
—
mV
POR
(7)
V
POR Reset Voltage
0
700
—
mV
PORRST
(8)
R
POR Rise Time Ramp Rate
0.02
V/ms
POR
1. V
= 3.3 Vdc 10%, V = 0 Vdc, T = T to T , unless otherwise noted.
SS A L H
DD
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I measured using external square wave clock source (f = 16.4 MHz). All inputs 0.2 V
from rail. No dc loads. Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs.
OSC2 capacitance linearly affects run I . Measured with all modules enabled.
4. Wait I
dc loads. Less than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capac-
itance linearly affects wait I . Measured with PLL and LVI enabled.
5. Stop I
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
DD
osc
L
DD
measured using external square wave clock source (f
= 16.4 MHz). All inputs 0.2V from rail. No
DD
osc
L
DD
measured with OSC1 = V
.
DD
SS
8. If minimum V
is not reached before the internal POR reset is released, RST must be driven low externally
DD
until minimum V
is reached.
DD
5-spec_a
MC68HC708XL36
337
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Sp e c ific a tions
Control Tim ing
(1)
Table 6. Control Timing (V = 5.0 Vdc ± 10%)
DD
Characteristic
Symbol
Min
Max
Unit
(2)
Frequency of Operation
f
Crystal Option
External Clock Option
1
dc
8
32.8
MHz
osc
(3)
(4)
f
Internal Operating Frequency
RESET Input Pulse Width Low
—
8.2
—
MHz
ns
op
(5)
(6)
t
50
IRL
IRQ Interrupt Pulse Width Low
(Edge-Triggered)
t
50
—
ns
ILIH
1. V = 0 Vdc; timing shown with respect to 20% V
SS
and 70% V unless noted
SS
DD
2. See Table 11 and Table 12 for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation. See
appropriate table for this information.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse
width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be
recognized.
(1)
Table 7. Control Timing (V = 3.3 Vdc ± 10%)
DD
Characteristic
Symbol
Min
Max
Unit
(2)
Frequency of Operation
f
Crystal Option
External Clock Option
1
dc
8
16.4
MHz
osc
(3)
(4)
f
Internal Operating Frequency
RESET Input Pulse Width Low
—
4.1
—
MHz
ns
op
(5)
(6)
t
125
IRL
IRQ Interrupt Pulse Width Low
(Edge-Triggered)
t
125
—
ns
ILIH
1. V = 0 Vdc; timing shown with respect to 20% V
SS
and 70% V unless noted
SS
DD
2. See Table 11 and Table 12 for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation. See
appropriate table for this information.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse
width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be
recognized.
6-spec_a
MC68HC708XL36
338
Specifications
MOTOROLA
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Specifications
Preliminary Electrical Specifications
SPI
Cha ra c te ristic s
(1)
Table 8. SPI Timing (V = 5.0 Vdc ± 10%)
DD
Diagram
Number
Characteristic
Symbol
Min
Max
Unit
(2)
Operating Frequency
Master
Slave
f
f
/2
f
/128
op(m)
op
f
MHz
op
f
dc
op(s)
op
Cycle Time
Master
Slave
t
t
1
cyc(m)
2
1
128
—
cyc
t
cyc(s)
t
2
3
Enable Lead Time
Enable Lag Time
15
15
ns
ns
Lead(s)
t
Lag(s)
Clock (SCK) High Time
Master
Slave
t
4
5
6
7
sckh(m)
100
50
—
—
ns
ns
ns
ns
t
sckh(s)
Clock (SCK) Low Time
Master
Slave
t
sckl(m)
100
50
—
—
t
sckl(s)
Data Setup Time (Inputs)
Master
Slave
t
su(m)
45
5
—
—
t
su(s)
Data Hold Time (Inputs)
Master
Slave
t
h(m)
0
15
—
—
t
h(s)
(3)
Access Time, Slave
t
8
9
a(cp0)
0
0
40
20
ns
ns
ns
CPHA = 0
CPHA = 1
t
a(cp1)
(4)
t
Disable Time, Slave
—
25
dis(s)
Data Valid Time (After Enable Edge)
Master
t
10
v(m)
—
—
10
40
(5)
t
Slave
v(s)
Data Hold Time (Outputs, After Enable Edge)
Master
Slave
t
11
ho(m)
0
5
—
—
ns
t
ho(s)
1. All timing is shown with respect to 20% V
and 70% V , unless noted; 100 pf load on all SPI pins.
DD
DD
2. Numbers refer to dimensions in Figure 1 and Figure 2.
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
7-spec_a
MC68HC708XL36
339
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Sp e c ific a tions
(1)
Table 9. SPI Timing (V = 3.3 Vdc ± 10%)
DD
Diagram
Number
Characteristic
Symbol
Min
Max
Unit
(2)
Operating Frequency
Master
Slave
f
f
/2
f
/128
op(m)
op
f
MHz
op
f
dc
op(s)
op
Cycle Time
Master
Slave
t
t
1
cyc(m)
2
1
128
—
cyc
t
cyc(s)
t
2
3
Enable Lead Time
Enable Lag Time
30
30
—
—
ns
ns
Lead(s)
t
Lag(s)
Clock (SCK) High Time
Master
Slave
t
4
5
6
7
sckh(m)
200
100
—
—
ns
ns
ns
ns
t
sckh(s)
Clock (SCK) Low Time
Master
Slave
t
sckl(m)
200
100
—
—
t
sckl(s)
Data Setup Time (Inputs)
Master
Slave
t
su(m)
90
10
—
—
t
su(s)
Data Hold Time (Inputs)
Master
Slave
t
h(m)
0
30
—
—
t
h(s)
(3)
Access Time, Slave
t
8
9
a(cp0)
0
0
80
40
ns
ns
ns
CPHA = 0
CPHA = 1
t
a(cp1)
(4)
t
Disable Time, Slave
—
50
dis(s)
Data Valid Time (After Enable Edge)
Master
t
10
v(m)
—
—
20
80
(5)
t
Slave
v(s)
Data Hold Time (Outputs, After Enable Edge)
Master
Slave
t
11
ho(m)
0
10
—
—
ns
t
ho(s)
1. All timing is shown with respect to 20% V
and 70% V , unless noted; 100 pf load on all SPI pins.
DD
DD
2. Numbers refer to dimensions in Figure 1 and Figure 2.
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
8-spec_a
MC68HC708XL36
340
Specifications
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Specifications
Preliminary Electrical Specifications
SS
INPUT
SS PIN OF MASTER HELD HIGH
1
5
4
SCK (CPOL = 0)
OUTPUT
NOTE
4
5
SCK CPOL = 1
OUTPUT
NOTE
10
6
7
MISO
INPUT
MSB IN
BITS 6–1
BITS 6–1
LSB IN
11
MASTER MSB OUT
10
11
MOSI
OUTPUT
MASTER LSB OUT
NOTE: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
INPUT
SS PIN OF MASTER HELD HIGH
1
SCK (CPOL = 0)
OUTPUT
5
NOTE
NOTE
4
SCK (CPOL = 1)
OUTPUT
5
4
6
7
LSB IN
11
MISO
MSB IN
11
BITS 6–1
BITS 6–1
INPUT
10
10
MOSI
OUTPUT
MASTER MSB OUT
MASTER LSB OUT
NOTE: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 1. SPI Master Timing
9-spec_a
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Sp e c ific a tions
SS
INPUT
3
1
SCK (CPOL = 0)
INPUT
11
4
2
SCK (CPOL = 1)
INPUT
5
4
9
8
MISO
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
11
NOTE
INPUT
11
6
7
10
MOSI
OUTPUT
MSB IN
LSB IN
NOTE: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
1
SCK (CPOL = 0)
INPUT
5
4
5
2
3
SCK (CPOL = 1)
INPUT
4
10
9
8
MISO
NOTE
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
OUTPUT
11
6
7
10
MOSI
INPUT
MSB IN
LSB IN
NOTE: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 2. SPI Slave Timing
10-spec_a
MC68HC708XL36
342
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Specifications
Preliminary Electrical Specifications
TIm e r Inte rfa c e
Mod ule
Cha ra c te ristic s
Table 10. TIM Timing
Characteristic
Input Capture Pulse Width
Input Clock Pulse Width
Symbol
Min
Max
—
Unit
ns
t
, t
125
tih til
t
, t
(1/f ) + 5
op
—
ns
tch tcl
Cloc k Ge ne ra tion
Mod ule Ele c tric a l
Cha ra c te ristic s
Table 11. CGM Component Specifications
Characteristic
Symbol Min
Typ
4.9152
—
Max Unit
Crystal (X1) Frequency
f
1
8
MHz
xclk
(1)
(MHz)
(2)
(2)
C
Crystal Load Capacitance
—
—
—
—
0
—
—
—
—
3.3
—
—
pF
pF
pF
MΩ
kΩ
pF
µF
L
C
2 × C
Crystal Fixed Capacitance
1
L
(2)
C
2 × C
Crystal Tuning Capacitance
2
L
R
Feedback Bias Resistor
1
B
(3)
R
Series Resistor
—
S
C
× (V
/f
)
xclk
C
Filter Capacitor
—
—
DDA
F
fact
(4)
C
Bypass Capacitor
0.1
byp
1. Fundamental mode crystals only
2. Consult crystal manufacturer’s data.
3. Not required
4. C
must provide low AC impedance from f = f
/100 to 100 × f , so series resistance
vclk
byp
xclk
must be considered.
11-spec_a
MC68HC708XL36
343
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Sp e c ific a tions
Table 12. CGM Operating Conditions
Characteristic
Crystal Reference Frequency
Symbol
Min
Typ
Max
Unit
f
1
—
8
MHz
xclk
f
Range Nominal Multiplier
—
4.9152
4.9152
1
4.9152
—
—
32.8
16.4
15
MHz
MHz
MHz
—
nom
(1)
VCO Center-of-Range Frequency
f
vrs
(2)
Medium Voltage VCO Center-of-Range Frequency
VCO Frequency Multiplier
—
N
L
—
VCO Center-of-Range Multiplier
VCO Operating Frequency
1
—
15
—
f
f
f
vrsmax
—
MHz
vclk
vrsmin
1. 5.0 V ±10% V
2. 3.3 V ±10% V
only
only
DD
DD
12-spec_a
MC68HC708XL36
344
Specifications
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Specifications
Preliminary Electrical Specifications
Table 13. CGM Acquisition and Lock Time Specifications
Description
Filter Capacitor Multiply Factor
Acquisition Mode Time Factor
Tracking Mode Time Factor
Symbol Min
Typ
Max
—
Unit
F/sV
V
C
—
—
—
0.0154
0.1135
0.0174
fact
K
—
acq
K
—
V
trk
8 × VDDA
(1)
t
Manual Mode Time to Stable
—
—
—
—
s
s
------------------------------
acq
f
× K
acq
xclk
4 × V DDA
(1)
t
---------------------------
Manual Stable to Lock Time
al
f
× K
xclk
trk
t
t
+ t
Manual Acquisition Time
—
0
—
s
—
Lock
acq al
∆
Tracking Mode Entry Frequency Tolerance
Acquisition Mode Entry Frequency Tolerance
LOCK Entry Frequency Tolerance
—
3.6%
7.2%
0.9%
1.8%
—
trk
∆
—
—
—
6.3%
0
acq
∆
—
Lock
∆
LOCK Exit Frequency Tolerance
—
—
0.9%
—
unl
n
Reference Cycles per Acquisition Mode Measurement
Reference Cycles per Tracking Mode Measurement
32
Cyc.
Cyc.
acq
n
—
128
—
trk
n
8 × VDDA
acq
(1)
t
—
s
----------- ------------------------------
Automatic Mode Time to Stable
acq
f
f
× K
acq
xclk
xclk
n
4 × V DDA
trk
(1)
t
—
—
s
s
----------
---------------------------
Automatic Stable to Lock Time
al
f
f
× K
trk
xclk
xclk
t
t
+t
Automatic Lock Time
—
Lock
acq al
f
× 0.025%
crys
(2)
f
PLL Jitter
0
—
Hz
J
P
× 2 N/4
1. If C chosen correctly
F
2. Deviation of average bus frequency over 2 ms. N = VCO frequency multiplier.
13-spec_a
MC68HC708XL36
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Sp e c ific a tions
Me m ory
Cha ra c te ristic s
Table 14. Memory Characteristics
Characteristic
Symbol
Min
12.5
—
Typ
13.0
10.0
Max
13.5
—
Unit
V
V
EPROM Programming Voltage
EPROM Data Retention
PP
t
Years
dret
t
EPROM Programming Time
RAM Data Retention Voltage
—
1
—
—
ms/byte
V
epgm
V
0.7
—
rm
14-spec_a
MC68HC708XL36
346
Specifications
MOTOROLA
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Specifications
Mechanical Specifications
Me c ha nic a l Sp e c ific a tions
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
56
29
28
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010)
–B–
INCHES
DIM MIN MAX
MILLIMETERS
MIN MAX
1
A
B
C
D
E
2.035 2.065 51.69 52.45
0.540 0.560 13.72 14.22
L
0.155 0.200
0.014 0.022
0.035 BSC
3.94
0.36
0.89 BSC
5.08
0.56
H
C
F
0.032 0.046
0.070 BSC
0.300 BSC
0.81
1.778 BSC
7.62 BSC
0.20
2.92
15.24 BSC
1.17
G
H
J
K
L
–T–
K
0.008 0.015
0.38
3.43
SEATING
0.115
0.135
PLANE
0.600 BSC
N
G
M
F
M
N
0
15
0
0.51
15
1.02
0.020 0.040
E
J 56 PL
D 56 PL
M
S
0.25 (0.010)
T A
M
S
0.25 (0.010)
T B
Figure 3. Case Outline Drawing 859-01
15-spec_a
MC68HC708XL36
347
MOTOROLA
Specifications
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Sp e c ific a tions
L
48
33
49
32
B
B
P
–A–
–B–
L
V
B
–A–, –B–, –D–
DETAIL A
DETAIL A
F
64
17
1
16
–D–
A
M
S
S
S
0.20 (0.008)
C A–B
D
J
N
0.05 (0.002) A–B
S
BASE
METAL
M
S
0.20 (0.008)
H A–B
D
E
C
D
DETAILC
M
M
S
S
0.02 (0.008)
C A–B
D
DATUM
PLANE
–H–
–C–
SEATING
PLANE
0.01 (0.004)
M
H
G
U
NOTES:
MILLIMETERS
INCHES
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
DIM MIN
MAX
MIN
MAX
0.555
0.555
0.096
0.018
0.094
0.016
A
B
13.90
13.90
2.15
0.30
2.00
0.30
14.10 0.547
14.10 0.547
2.45 0.085
0.45 0.012
2.40 0.079
0.40 0.012
2. CONTROLLING DIMENSION: MILLIMETER.
T
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
C
D
E
R
F
G
H
J
K
L
M
N
P
Q
R
S
0.80 BSC
0.031 BSC
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) PER SIDE.
TOTAL IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION. DAMBAR
CANNOT BE LOCATED ON THE LOWER RADIUS
OR THE FOOT.
DATUM
PLANE
–H–
–––
0.13
0.65
0.25
0.23 0.005
0.95 0.026
–––
0.010
0.009
0.037
Q
12.00 REF
0.472 REF
5
10
5
10
0.13
0.17 0.005
0.007
0.016 BSC
K
0.40 BSC
0
0.13
16.95
0.13
0
7
0
7
W
0.30 0.005
17.45 0.667
––– 0.005
0.012
0.687
–––
X
T
U
V
W
X
–––
0
–––
DETAIL C
16.95
0.35
17.45 0.667
0.45 0.014
0.687
0.018
0.063 REF
1.6 REF
Figure 4. Case Outline Drawing 840B-01
16-spec_a
MC68HC708XL36
348
Specifications
MOTOROLA
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Specifications
Mechanical Specifications
B
B
L
–A–, –B–, –D–
33
48
32
49
P
B
L
V
DETAIL A
BASE
METAL
F
DETAIL A
J
N
17
64
D
16
1
M
S
S
0.20 (0.008)
C A–B
D
–D–
SECTION B–B
A
NOTES:
M
S
S
S
0.20 (0.008)
H A–B
D
D
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
0.05 (0.002) A–B
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
S
M
S
0.20 (0.008)
C A–B
4. DATUMS A–B AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
–H–
DATUM PLANE
C
E
H
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED 0.53
(0.021). DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT.
0.10 (0.004)
SEATING PLANE
–C–
G
DETAIL C
8. DIMENSION K IS TO BE MEASURED FROM THE
THEORETICAL INTERSECTION OF LEAD FOOT
AND LEG CENTERLINES.
U
MILLIMETERS
DIM MIN MAX
INCHES
M
MIN
MAX
0.555
0.555
0.097
0.018
0.094
–––
T
A
B
C
D
E
F
13.90
13.90
2.07
0.30
2.00
0.30
14.10 0.547
14.10 0.547
2.46 0.081
0.45 0.012
2.40 0.079
––– 0.012
R
G
H
J
K
L
M
N
P
0.80 BSC
0.031 BSC
0.067
0.130
0.50
0.250 0.003
0.230 0.005
0.66 0.020
0.010
0.090
0.026
Q
12.00 REF
0.472 REF
SEATING PLANE
5
10
5
10
K
0.130
0.170 0.005
0.007
0.016 BSC
0.40 BSC
Q
R
S
T
U
V
X
2
0.13
16.20
8
2
8
0.30 0.005
16.60 0.638
0.012
0.654
X
M
0.20 REF
0.008 REF
0
0
16.20
1.10
–––
–––
0.654
0.051
16.60 0.638
1.30 0.043
DETAIL C
Figure 5. Case Outline Drawing 840C-04
17-spec_a
MC68HC708XL36
349
MOTOROLA
Specifications
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Sp e c ific a tions
L
B
B
P
33
32
48
49
–A–, –B–, –D–
–B–
–A–
L
B
V
DETAIL A
F
DETAIL A
J
N
17
64
16
1
BASE METAL
D
–D–
M
S
S
0.02 (0.008)
C A–B
D
A
VIEW ROTATED 90
CLOCKWISE
M
S
S
0.20 (0.008)
C A–B
D
0.05 (0.002) A–B
SECTION B–B
S
NOTES:
M
S
S
0.20 (0.008)
H A–B
D
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS A AND B DEFINE MAXIMUM
CERAMIC BODY DIMENSION INCLUDING GLASS
PROTRUSION AND MISMATCH BETWEEN
CERAMIC BODY AND COVER.
C
E
DATUM
–H–
PLANE
–C–
0.01 (0.004)
G
SEATING
H
PLANE
DETAIL C
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.555
0.555
0.162
0.018
0.127
0.016
A
B
C
D
E
13.90
13.90
3.00
0.30
2.54
0.30
14.10 0.547
14.10 0.547
4.11
0.45 0.012
3.22 0.100
0.40 0.012
U
0.118
T
R
F
–H–
DATUM
PLANE
G
H
J
K
L
0.80 BSC
0.031 BSC
Q
0.45
0.13
0.65
0.89 0.018
0.23 0.005
0.95 0.026
0.035
0.009
0.037
12.00 REF
0.472 REF
0.007
0.016 BSC
K
N
P
0.13
0.17 0.005
W
0.40 BSC
Q
R
S
0
7
0
7
X
0.13
16.95
0.13
0
16.95
0.35
0.30 0.005
17.45 0.667
––– 0.005
0.012
0.687
–––
–––
0.687
0.018
DETAIL C
T
U
V
W
X
–––
0
17.45 0.667
0.45 0.014
1.60 REF
0.063 REF
Figure 6. Case Outline Drawing 963-02
18-spec_a
MC68HC708XL36
350
Specifications
MOTOROLA
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Glossa ry
Glossa ry
A — See “accumulator (A).”
accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the
accumulator to hold operands and results of arithmetic and logic operations.
acquisition mode — A mode of PLL operation during startup before the PLL locks on a
frequency. Also see "tracking mode."
address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
addressing mode — The way that the CPU determines the operand address for an instruction.
The M68HC08 CPU has 16 addressing modes.
ALU — See “arithmetic logic unit (ALU).”
arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform
arithmetic, logic, and manipulation operations on operands.
asynchronous — Refers to logic circuits and operations that are not synchronized by a common
reference signal.
baud rate — The total number of bits transmitted per unit of time.
BCD — See “binary-coded decimal (BCD).”
binary — Relating to the base 2 number system.
binary number system — The base 2 number system, having two digits, 0 and 1. Binary
arithmetic is convenient in digital circuit design because digital circuits have two
permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to
correspond to the two digital voltage levels.
MC68HC708XL36
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binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10
decimal digits and that retains the same positional structure of a decimal number. For
example,
234 (decimal) = 0010 0011 0100 (BCD)
bit — A binary digit. A bit has a value of either logic 0 or logic 1.
branch instruction — An instruction that causes the CPU to continue processing at a memory
location other than the next sequential address.
break module — A module in the M68HC08 Family. The break module allows software to halt
program execution at a programmable point in order to enter a background routine.
breakpoint — A number written into the break address registers of the break module. When a
number appears on the internal address bus that is the same as the number in the break
address registers, the CPU executes the software interrupt instruction (SWI).
break interrupt — A software interrupt caused by the appearance on the internal address bus
of the same value that is written in the break address registers.
bus — A set of wires that transfers logic signals.
bus clock — The bus clock is derived from the CGMOUT output from the CGM. The bus clock
frequency, f , is equal to the frequency of the oscillator output, CGMXCLK, divided by
op
four.
byte — A set of eight bits.
C — The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit
when an addition operation produces a carry out of bit 7 of the accumulator or when a
subtraction operation requires a borrow. Some logical operations and data manipulation
instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and
shifts and rotates).
CCR — See “condition code register.”
central processor unit (CPU) — The primary functioning unit of any computer system. The
CPU controls the execution of instructions.
MC68HC708XL36
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Glossary
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Glossary
CGM — See “clock generator module (CGM).”
clear — To change a bit from logic 1 to logic 0; the opposite of set.
clock — A square wave signal used to synchronize events in a computer.
clock generator module (CGM) — A module in the M68HC08 Family. The CGM generates a
base clock signal from which the system clocks are derived. The CGM may include a
crystal oscillator circuit and or phase-locked loop (PLL) circuit.
comparator — A device that compares the magnitude of two inputs. A digital comparator defines
the equality or relative differences between two binary numbers.
computer operating properly module (COP) — A counter module in the M68HC08 Family that
resets the MCU if allowed to overflow.
condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt
mask bit and five bits that indicate the results of the instruction just executed.
control bit — One bit of a register manipulated by software to control the operation of the
module.
control unit — One of two major units of the CPU. The control unit contains logic functions that
synchronize the machine and direct various operations. The control unit decodes
instructions and generates the internal control signals that perform the requested
operations. The outputs of the control unit drive the execution unit, which contains the
arithmetic logic unit (ALU), CPU registers, and bus interface.
COP — See "computer operating properly module (COP)."
counter clock — The input clock to the TIM counter. This clock is an output of the prescaler
sub-module. The frequency of the counter clock is fTCNT, and the period is tTCNT
.
CPU — See “central processor unit (CPU).”
CPU08 — The central processor unit of the M68HC08 Family.
CPU clock — The CPU clock is derived from the CGMOUT output from the CGM. The CPU
clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by
four.
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Glossa ry
CPU cycles — A CPU clock cycle is one period of the internal bus-rate clock, fOP, normally
derived by dividing a crystal oscillator source by two or more so the high and low times
will be equal. The length of time required to execute an instruction is measured in CPU
clock cycles.
CPU registers — Memory locations that are wired directly into the CPU logic instead of being
part of the addressable memory map. The CPU always has direct access to the
information in these registers. The CPU registers in an M68HC08 are:
•
•
•
•
•
A (8-bit accumulator)
H:X (16-bit index register)
SP (16-bit stack pointer)
PC (16-bit program counter)
CCR (condition code register containing the V, H, I, N, Z, and C bits)
CSIC — customer-specified integrated circuit
cycle time — The period of the operating frequency: tCYC = 1/fOP.
decimal number system — Base 10 numbering system that uses the digits zero through nine.
direct memory access module (DMA) — A M68HC08 Family module that can perform data
transfers between any two CPU-addressable locations without CPU intervention. For
transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster
and more code-efficient than CPU interrupts.
DMA — See "direct memory access module (DMA)."
DMA service request — A signal from a peripheral to the DMA module that enables the DMA
module to transfer data.
duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is
usually represented by a percentage.
EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of
memory that can be electrically reprogrammed.
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Glossary
EPROM — Erasable, programmable, read-only memory. A non-volatile type of memory that can
be erased by exposure to an ultraviolet light source and then reprogrammed.
exception — An event such as an interrupt or a reset that stops the sequential execution of the
instructions in the main program.
external interrupt module (IRQ) — A module in the M68HC08 Family with both dedicated
external interrupt pins and port pins that can be enabled as interrupt pins.
fetch — To copy data from a memory location into the accumulator.
firmware — Instructions and data programmed into nonvolatile memory.
free-running counter — A device that counts from zero to a predetermined number, then rolls
over to zero and begins counting again.
full-duplex transmission — Communication on a channel in which data can be sent and
received simultaneously.
H — The upper byte of the 16-bit index register (H:X) in the CPU08.
H — The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from
the low-order four bits of the accumulator value to the high-order four bits. The half-carry
bit is required for binary-coded decimal arithmetic operations. The decimal adjust
accumulator (DAA) instruction uses the state of the H and C bits to determine the
appropriate correction factor.
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
through F.
high byte — The most significant eight bits of a word.
illegal address — An address not within the memory map
illegal opcode — A nonexistent opcode.
I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts
are disabled.
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Glossa ry
index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The
lower byte is called X. In the indexed addressing modes, the CPU uses the contents of
H:X to determine the effective address of the operand. H:X can also serve as a temporary
data storage location.
input/output (I/O) — Input/output interfaces between a computer system and the external world.
A CPU reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
instructions — Operations that a CPU can perform. Instructions are expressed by programmers
as assembly language mnemonics. A CPU interprets an opcode and its associated
operand(s) and instruction.
interrupt — A temporary break in the sequential execution of a program to respond to signals
from peripheral devices by executing a subroutine.
interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to
execute a subroutine.
I/O — See “input/output (I/0).”
IRQ — See "external interrupt module (IRQ)."
jitter — Short-term signal instability.
latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power
is applied to the circuit.
latency — The time lag between instruction completion and data movement.
least significant bit (LSB) — The rightmost digit of a binary number.
logic 1 — A voltage level approximately equal to the input power voltage (VDD).
logic 0 — A voltage level approximately equal to the ground voltage (VSS).
low byte — The least significant eight bits of a word.
low voltage inhibit module (LVI) — A module in the M68HC08 Family that monitors power
supply voltage.
MC68HC708XL36
356
Glossary
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Glossary
LVI — See "low voltage inhibit module (LVI)."
M68HC08 — A Motorola family of 8-bit MCUs.
mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.
mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used
in integrated circuit fabrication to transfer an image onto silicon.
mask option — An optional microcontroller feature that the customer chooses to enable or
disable.
mask option register (MOR) — An EPROM location containing bits that enable or disable
certain MCU features.
MCU — Microcontroller unit. See “microcontroller.”
memory location — Each M68HC08 memory location holds one byte of data and has a unique
address. To store information in a memory location, the CPU places the address of the
location on the address bus, the data information on the data bus, and asserts the write
signal. To read information from a memory location, the CPU places the address of the
location on the address bus and asserts the read signal. In response to the read signal,
the selected memory location places its data onto the data bus.
memory map — A pictorial representation of all memory locations in a computer system.
microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU,
memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.
modulo counter — A counter that can be programmed to count to any number from zero to its
maximum possible modulus.
monitor ROM — A section of ROM that can execute commands from a host computer for testing
purposes.
MOR — See "mask option register (MOR)."
most significant bit (MSB) — The leftmost digit of a binary number.
multiplexer — A device that can select one of a number of inputs and pass the logic level of that
input on to the output.
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Glossa ry
N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit
when an arithmetic operation, logical operation, or data manipulation produces a negative
result.
nibble — A set of four bits (half of a byte).
object code — The output from an assembler or compiler that is itself executable machine code,
or is suitable for processing to produce executable machine code.
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
connected to the power supply to provide the logic 1 output voltage.
operand — Data on which an operation is performed. Usually a statement consists of an
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
oscillator — A circuit that produces a constant frequency square wave that is used by the
computer as a timing and sequencing reference.
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that
cannot be reprogrammed.
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
In a system that uses odd parity, every byte is expected to have an odd number of logic
ones. In an even parity system, every byte should have an even number of logic ones. In
the transmitter, a parity generator appends an extra bit to each byte to make the number
of logic 1s odd for odd parity or even for even parity. A parity checker in the receiver
counts the number of logic 1s in each byte. The parity checker generates an error signal
if it finds a byte with an incorrect number of logic 1s.
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
MC68HC708XL36
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Glossary
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Glossary
phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is
synchronized to a reference signal.
PLL — See "phase-locked loop (PLL)."
pointer — Pointer register. An index register is sometimes called a pointer register because its
contents are used in the calculation of the address of an operand, and therefore points to
the operand.
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different
voltage levels, VDD and VSS.
polling — Periodically reading a status bit to monitor the condition of a peripheral device.
port — A set of wires for communicating with off-chip devices.
prescaler — A circuit that generates an output signal related to the input signal by a fractional
scale factor such as 1/2, 1/8, 1/10 etc.
program — A set of computer instructions that cause a computer to perform a desired operation
or operations.
program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of
the next instruction or operand that the CPU will use.
pull — An instruction that copies into the accumulator the contents of a stack RAM location. The
stack RAM address is in the stack pointer.
pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage
of the power supply.
pulse-width — The amount of time a signal is on as opposed to being in its off state.
pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a
signal with a constant frequency.
push — An instruction that copies the contents of the accumulator to the stack RAM. The stack
RAM address is in the stack pointer.
PWM period — The time required for one complete cycle of a PWM waveform.
MC68HC708XL36
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RAM — Random access memory. All RAM locations can be read or written by the CPU. The
contents of a RAM memory location remain valid until the CPU writes a different value or
until power is turned off.
RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.
read — To copy the contents of a memory location to the accumulator.
register — A circuit that stores a group of bits.
reserved memory location — A memory location that is used only in special factory-test
modes. Writing to a reserved location has no effect. Reading a reserved location returns
an unpredictable value.
reset — To force a device to a known condition.
ROM — Read-only memory. A type of memory that can be read but cannot be changed (written).
The contents of ROM must be specified before manufacturing the MCU.
SCI — See "serial communication interface module (SCI)."
serial — Pertaining to sequential transmission over a single line.
serial communications interface module (SCI) — A module in the M68HC08 Family that
supports asynchronous communication.
serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports
synchronous communication.
set — To change a bit from logic 0 to logic 1; opposite of clear.
shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to
them and that can shift the logic levels to the right or left through adjacent circuits in the
chain.
signed — A binary number notation that accommodates both positive and negative numbers.
The most significant bit is used to indicate whether the number is positive or negative,
normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the
magnitude of the number.
software — Instructions and data that control the operation of a microcontroller.
MC68HC708XL36
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Glossary
software interrupt (SWI) — An instruction that causes an interrupt and its associated vector
fetch.
SPI — See "serial peripheral interface module (SPI)."
stack — A portion of RAM reserved for storage of CPU register contents and subroutine return
addresses.
stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available
storage location on the stack.
start bit — A bit that signals the beginning of an asynchronous serial transmission.
status bit — A register bit that indicates the condition of a device.
stop bit — A bit that signals the end of an asynchronous serial transmission.
subroutine — A sequence of instructions to be used more than once in the course of a program.
The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each
place in the main program where the subroutine instructions are needed, a jump or branch
to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the
flow of the main program to execute the instructions in the subroutine. When the RTS
instruction is executed, the CPU returns to the main program where it left off.
synchronous — Refers to logic circuits and operations that are synchronized by a common
reference signal.
TIM — See "timer interface module (TIM)."
timer interface module (TIM) — A module used to relate events in a system to a point in time.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a
frequency. Also see "acquisition mode."
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two’s complement — A means of performing binary subtraction using addition techniques. The
most significant bit of a two’s complement number indicates the sign of the number (1
indicates negative). The two’s complement negative of a number is obtained by inverting
each bit in the number and then adding 1 to the result.
unbuffered — Utilizes only one register for data; new data overwrites current data.
unimplemented memory location — A memory location that is not used. Writing to an
unimplemented location has no effect. Reading an unimplemented location returns an
unpredictable value. Executing an opcode at an unimplemented location causes an illegal
address reset.
V —The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when
a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE,
and BLT use the overflow bit.
variable — A value that changes during the course of program execution.
VCO — See "voltage-controlled oscillator."
vector — A memory location that contains the address of the beginning of a subroutine written
to service an interrupt or reset.
voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a
frequency that is controlled by a dc voltage applied to a control input.
waveform — A graphical representation in which the amplitude of a wave is plotted against time.
wired-OR — Connection of circuit outputs so that if any output is high, the connection point is
high.
word — A set of two bytes (16 bits).
write — The transfer of a byte of data from the CPU to a memory location.
X — The lower byte of the index register (H:X) in the CPU08.
Z — The zero bit in the condition code register of the CPU08. The CPU08 sets the zero bit when
an arithmetic operation, logical operation, or data manipulation produces a result of $00.
MC68HC708XL36
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Ind e x
Ind e x
A
effects on COP 152, 310
accumulator (A) 43, 46
ACK1 bit (IRQ1 interrupt request acknowledge
bit) 312, 314, 318–319
effects on CPU 49, 152
effects on DMA 131, 152
effects on SPI 224
effects on TIM 152, 185
flag protection during 66
break module
break address registers (BRKH/L) 131
break signal 162
ACK2 bit (IRQ2 interrupt request acknowledge
bit) 312, 316, 318–319
ACKK bit (keyboard acknowledge bit) 328
ACQ bit (acquisition mode bit) 90–91,
100–101, 107
ADC instruction 46
ADD instruction 46
arithmetic/logic unit (ALU) 48
AUTO bit (automatic bandwidth control bit) 91,
98, 100, 104
BRK module 149, 156
break address registers (BRKH/L) 75, 150,
152–155
break flag control register (BFCR) 156
break status and control register (BSCR)
75, 150, 153–154
break status register (BSR) 155
in stop mode 75
in wait mode 75
B
baud rate
mismatch 252
SCI module 278–281
BB[1:0] bits (DMA bus bandwidth control bits)
121, 133, 136–137
BCD arithmetic 46
BCFE bit (break clear flag enable bit) 131,
156, 185, 262, 318, 326
BCS bit (base clock select bit) 75, 91, 94, 99,
101, 103–105
BRKA bit (break active bit) 75, 150, 153–154
BRKE bit (break enable bit) 75, 153–154
bus frequency 12, 42, 92, 97, 186
BW bit (break/wait bit) 75, 153, 156
BWC bit (DMA byte/word control bit) 141
BWCx bits (DMA byte/word control bits) 120
C
C bit (carry/borrow flag) 46–47
ceramic resonator 84
BIH instruction 315
BIL instruction 315
CGM 84, 110
BKF bit (SCI break flag bit) 277
branch instructions 45–46
break character 245, 267, 274
break interrupt 66, 82
in stop mode 75, 105
in wait mode 75, 105
PLL bandwidth control register (PBWC)90,
98, 100, 104, 107
PLL control register (PCTL) 75, 94, 98,
103, 105
causes 150
during wait mode 80
MC68HC708XL36
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Freescale Semiconductor, Inc.
Ind e x
PLL programming register (PPG) 93, 98,
102
CGMINT signal 75, 97, 105
CGMOUT signal 75, 84, 86, 90, 94, 97, 99,
101, 104–105, 233
CGMRCLK signal 86, 89
CGMRDV signal 89
CGMVCLK signal 75, 84, 86, 90, 94, 97,
99–100, 104–105
CPU interrupts
DMA 122, 138, 146
external 79, 184
masking 46
PLL 90–91, 97–98, 104
SCI 78, 242, 246, 257, 261, 268, 273
software 66
SPI 79, 223, 231
TIM 194
TIM input capture 177
TIM output compare 177
TIM overflow 67, 183
CPU registers
H register 34
stack pointer 33
crosstalk 95
crystal 75, 84, 86, 97, 105, 108, 162, 306–307
CGMVDV signal 89
CGMXCLK signal 58–60, 75–76, 84, 86, 94,
97, 99, 105, 306–307, 309
duty cycle 97
CGMXFC pin 18, 96, 109
CGND pin 227
CGND/EV pin 18
SS
CHxF bits (TIM channel interrupt flag bits) 67,
183, 194
CHxIE bits (TIM channel interrupt enable bits)
67, 183, 194–195
CHxMAX bits (TIM maximum duty cycle bits)
183, 198
CLI instruction 47
D
DAA instruction 46
DMA module 112, 148
block transfers 135–136, 143, 145–146
destination address registers
(D0DH/L–D2DH/L) 120
condition code register (CCR) 46, 314
configuration register (CONFIG) 39–40, 60,
76, 308–309, 330–331
COP bit (COP reset bit) 60, 307
COP control register (COPCTL) 307–308
COP counter 76, 305–309
COP module 305, 310
DMA block length registers (D0BL–D2BL)
120, 122–123, 132, 141, 146–148
DMA bus bandwidth 121, 133–134, 137
DMA byte count registers (D0BC–D2BC)
122–123, 132, 137, 141, 146, 148
DMA channel control registers (D0C–D2C)
122, 132, 140
DMA control register 1 (DC1) 120, 122,
132–133, 138, 146
DMA control register 2 (DC2) 121–122,
132, 139
during break interrupt 310
in stop mode 76
in wait mode 76
COP timeout period 39–40, 76, 306, 309
COPD (COP disable bit) 40
COPRS bit (COP rate select bit) 40
CPHA bit (SPI clock phase bit) 209, 226, 229
CPOL bit (SPI clock polarity bit) 229
CPU interrupt
DMA destination address registers
(D0DH/L–D2DH/L) 122–123, 137,
140, 145, 148
DMA latency 122, 132
DMA service request priority 136–137
DMA source address registers
(D0SH/L–D2SH/L) 120, 122–123,
137, 140, 143–144
external 18, 76, 130
software 49, 150
MC68HC708XL36
364
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Index
DMA status and control register (DSC)
120, 132, 136, 146
in stop mode 76
external filter capacitor 96, 108–109
external reset 58
in wait mode 76, 138
F
looping transfers 123, 135, 146
transfer sources 122–123, 139, 142
DMA service request priority 120
DMA service requests
f
(bus frequency) 92
FE bit (SCI framing error bit) 69, 258
FE bit (SCI receiver framing error bit) 276
FEIE bit (SCI framing error interrupt enable bit)
69, 258
FEIE bit (SCI receiver framing error interrupt
enable bit) 272, 276
flag protection in break mode 66
bus
SCI 242, 246, 257, 268, 273
SPI 231
TIM 194
TIM input capture 177
TIM output compare 177
f
f
f
(nominal center-of-range frequency) 89
(PLL reference clock frequency) 89
nom
DMAP bit (DMA priority bit) 76, 120, 130, 136
DMARE bit (SCI DMA receive enable bit) 257,
268, 274
DMAS bit (SPI DMA select bit) 229, 231
DMATE bit (SCI DMA transfer enable bit) 246,
268, 271–273
DMAWE bit (DMA wait enable bit) 120, 138
DTS[2:0] bits (DMA transfer source bits) 120,
122, 139, 141
rclk
(PLL final reference frequency) 89, 108,
110
(VCO output frequency) 89
(VCO programmed center-of-range
frequency) 89, 93, 103
rdv
f
f
vclk
vrs
H
H bit (half-carry flag) 46
E
ELAT bit (EPROM latch control bit) 37–38
electrostatic damage 284
ELSxA/B bits (TIM edge/level select bits) 182,
196–197
ENSCI bit (enable SCI bit) 241, 264
EPGM bit (EPROM program control bit) 37–38
EPMCPD bit (EPROM charge
pump disable bit) 37
I
I bit (interrupt mask) 46, 63, 314, 319
I/O port pin termination 284
I/O registers
locations 24
IDLE bit (SCI receiver idle bit) 68, 257, 275
idle character 68, 245–246, 264–265
IECx bits (DMA CPU interrupt enable bits)
135, 137
IFC[2:0] bits (DMA CPU interrupt flag bits) 138
IFCx bits (DMA CPU interrupt flag bits) 137,
141, 146
ILAD bit (illegal address reset bit) 60–61
ILIE bit (SCI idle line interrupt enable bit) 68,
257, 268
ILOP bit (illegal opcode reset bit) 60–61
ILTY bit (SCI idle line type bit) 265
EPROM
erasure 36
locations 36
programming 18
programming tools 36
security 12, 36, 158, 169
size 12, 22
EPROM control register (EPMCR) 37
external crystal 82, 101
MC68HC708XL36
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Ind e x
IMASK1 bit (IRQ1 interrupt mask bit) 314, 319
IMASK2 bit (IRQ2 interrupt mask bit)314, 316,
319
IMASKK (keyboard interrupt mask bit) 328
index register (H:X) 44, 63
input capture 67, 172–173, 177, 183, 186,
192, 199, 294
L
L (VCO linear range multiplier) 93
L[2:0] bits (DMA loop enable bits) 137
LDA instruction 63
literature distribution centers 371
LOCK bit (lock indicator bit) 90, 98, 100, 104,
107
LOOPS bit (SCI loop mode select bit) 264
LVI bit (low-voltage inhibit reset bit) 60
LVI module
internal address bus 150
internal reset 58
timing 58
interrupt status and control register (ISCR)
in stop mode 78
in wait mode 78
312
LVI status register (LVISR) 330–331
interrupts
LVI trip voltage 329
vector addresses 65
LVIOUT bit (LVI output bit) 330–331
LVIPWRD bit (LVI power disable bit) 40
LVIRST bit (LVI reset bit) 330
LVIRSTD bit (LVI reset disable bit) 40
LVISTOP bit (LVI enable in stop mode bit) 40
IRQ module
in stop mode 77
in wait mode 77
IRQ status and control register (ISCR) 318
IRQ1 pin 18, 37–38, 309, 314–315
triggering sensitivity 312
IRQ2 pin 18, 316
triggering sensitivity 312
IRQ2F bit (IRQ2 interrupt flag) 319
M
M bit (SCI character length bit) 241, 245, 265
M6805 compatibility 34
M68HC08 Family 12, 41
MODE1 bit (IRQ1 edge/level select bit) 312,
314, 320
J
jump instructions 45
MODE2 bit (IRQ2 interrupt edge/level select
bit) 312, 316, 319
MODEK bit (keyboard triggering sensitivity bit)
323, 328
MODF bit (mode fault error bit) 214
MODF bit (SPI mode fault bit) 232
monitor commands
K
KBIEx bits (keyboard interrupt enable bits)
324, 328
keyboard interrupt enable register (KBIER)
328
keyboard interrupt pins 19
keyboard status and control register (KBSCR)
327
IREAD 166
IWRITE 166
READ 165
READSP 167
KEYF bit (keyboard flag bit) 327
KEYF bit (keyboard interrupt flag bit) 324
RUN 167
WRITE 165
MC68HC708XL36
366
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Index
monitor mode 49, 150, 152, 309
OVRF bit (overflow bit) 214
alternate vector addresses 161
baud rate 162
OVRF bit (SPI overflow bit) 232
commands 158
echoing 162–163
P
packages
EPROM programming 158
monitor ROM 22
QFP 16, 300, 303
SDIP 15
MSxA/B bits (TIM mode select bits) 178,
181–183, 195–196
MSxB bits (TIM mode select bits) 181
parity
SCI module 69, 258, 264, 266, 272
PE bit (SCI parity error bit) 69, 258
PE bit (SCI receiver parity error bit) 277
N
PEIE bit (SCI parity error interrupt enable bit)
69, 258
N (VCO frequency multiplier) 92–93
N bit (negative flag) 47
NEIE bit (SCI noise error interrupt enable bit)
68, 258, 276
NEIE bit (SCI receiver noise error interrupt
enable bit) 272
PEIE bit (SCI receiver parity error interrupt en-
able bit) 272, 277
PEN bit (SCI parity enable bit) 266
phase-locked loop (PLL) 75, 84, 86, 88, 92,
94, 96–97, 104–110
NF bit (SCI noise flag bit) 68, 258, 276
noise 17, 68, 89–90, 95–96, 106, 108–109,
181–182, 258, 276, 278
acquisition mode 88, 90, 100–101,
106–109
acquisition time 106–110
automatic bandwidth mode 90
lock detector 88, 90, 97
lock time 106, 108–110
O
object code 12
loop filter 88, 90, 96
Opcode map 56
manual bandwidth mode 100
phase detector 88, 108
OR bit (SCI receiver overrun bit) 68, 258, 275
ordering information
tracking mode 88, 90, 100, 107, 110
voltage-controlled oscillator (VCO) 75, 86,
88, 90, 94, 100, 102–105, 108
PIN bit (external reset bit) 58, 61
PLLF bit (PLL flag bit) 104
literature distribution centers 371
Mfax 372
Web server 372
Web site 372
ORIE bit (SCI overrun interrupt enable bit) 68,
PLLF bit (PLL interrupt flag bit) 98
PLLIE bit (PLL interrupt enable bit) 66, 91, 98
PLLON bit (PLL on bit) 75, 91, 99, 103, 105
POR bit (power-on reset bit) 59, 61
port A 19, 286–287
data direction register A (DDRA) 286
port A data register (PORTA) 286
port B 19, 288–289
258
ORIE bit (SCI receiver overrun interrupt
enable bit) 272, 275
OSC1 pin 18, 96–97
OSC2 pin 18, 96–97
oscillator 86, 94, 96, 307
pins 18
stabilization delay 59–60
output compare 67, 172–173, 177–179,
182–183, 186, 192, 199, 294
data direction register B (DDRB) 288
port B data register (PORTB) 288
MC68HC708XL36
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Ind e x
port C 19, 290–291
RE bit (SCI receiver enable bit) 269
reset
COP 58, 61, 76, 305, 309
data direction register C (DDRC) 290
port C data register (PORTC) 290
port D 19, 292–293
external 61
data direction register D (DDRD) 292
keyboard interrupt enable register (KBICR)
292
external reset pin (RST) 18
illegal address 58, 60–61
illegal opcode 58, 60–61
internal 18, 58–59, 308
LVI 58
port D data register (PORTD) 292
port E 19, 294, 297
POR 58–59, 61
power-on 307
data direction register E (DDRE) 296
port E data register (PORTE) 294
port F 19, 297, 300
data direction register F (DDRF) 299
port F data register (PORTF) 297
port G 20, 300, 302
data direction register G (DDRG) 301
port G data register (PORTG) 300
port H 20, 303–304
data direction register H (DDRH) 303
port H data register (PORTH) 303
power supply 108
reset status register (RSR) 58, 60–61, 307
RPF bit (SCI reception in progress flag bit) 278
RST pin 58, 61, 307
RTI instruction 47, 49, 63, 150
RWU bit (SCI receiver wake-up bit) 269
S
SBK bit (SCI send break bit) 245, 270
SCI module 236, 281
baud rate 237, 278
character format 266
DMA service requests 121
error conditions 68, 258
framing error 252, 276
I/O pins 263
bypassing 17
pins 17
program counter (PC) 45, 49, 152, 315–316,
323
PS[2:0] bits (TIM prescaler select bits) 177,
189
in stop mode 78
in wait mode 78
noise error 276
overrun error 272
parity 266, 272, 277
PSHH instruction 47
PTY bit (SCI parity bit) 266
PULH instruction 47
pulse-width modulation 172
pulse-width modulation (PWM) 179–181, 186,
192
parity error 69, 258
SCI baud rate register (SCBR) 279
SCI control register 1 (SCC1) 241, 245,
264
SCI control register 2 (SCC2) 68, 241,
245–246, 257, 267, 273
SCI control register 3 (SCC3) 68, 241, 246,
257–258, 268, 270, 273
SCI data register (SCDR) 68, 241–242,
246, 249, 257–258, 271, 274,
277–278
duty cycle 180, 183, 198
frequency 180
initialization 182
R
R8 bit (SCI received bit 8) 271
RAM 33–34, 158
size 12, 22
stack RAM 45
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Freescale Semiconductor, Inc.
Index
SCI status register 1 (SCS1) 68, 242, 246,
SPRF bit (SPI receiver full bit) 67, 206–207,
249, 257–258, 264, 273
SCI status register 2 (SCS2) 277
SCP1–SCP0 bits (SCI baud rate prescaler
bits) 279
SCRF bit (SCI receiver full bit) 68, 249, 257,
268, 274
SCRIE bit (SCI receiver interrupt enable bit)
68, 257, 268, 274
SCTE bit (SCI transmitter empty bit) 68, 242,
246, 264, 268, 273
213, 228, 230–231
SPRIE bit (SPI receiver interrupt enable bit)
67, 228, 231
SPTE bit (SPI transmitter empty bit) 67, 206,
213, 229–230, 232
SPTE bit (SPI transmitter enable bit) 233
SPTIE bit (SPI transmitter interrupt enable bit)
67, 230, 232
SPWOM bit (SPI wired-OR mode bit) 225, 230
SSREC bit (short stop recovery bit) 40, 82
stack pointer (SP) 33, 44
SCTIE bit (SCI transmitter interrupt enable bit)
68, 242, 246, 268, 273
stack RAM 33, 45
SDC[3:0] bits (DMA source/destination ad-
dress control bits) 120, 140
SIMOSCEN signal 86, 96
start bit 162
SCI data 242, 245, 249, 265, 270, 278
stop bit
SPE bit (SPI enable bit) 230
SPI module 201, 234
SCI data 69, 242, 245–246, 252–254, 256,
258, 265, 276
baud rate 230, 233
DMA service requests 121
I/O pins 225
in stop mode 79, 224
in wait mode 79
mode fault error 214, 232
overflow error 214, 232
receive data register 67, 206–207, 215,
221, 228, 230–232, 234
STOP bit (STOP enable bit) 40, 60, 76, 309
STOP instruction 74–79, 99, 105, 130, 153,
184, 223–224, 261, 307, 309, 332
enabling 39
stop mode 75–76, 78–79, 130, 153, 184, 224,
261, 278, 309, 332
stop mode recovery time 39
SWI instruction 49, 66, 150, 152
SWI[7:0] bits (DMA software initiate bits) 139
slave select pin 214, 230
SPI control register (SPCR) 225, 228, 231
SPI data register 214, 231
SPI data register (SPDR) 206, 234
SPI status and control register 232
SPI status and control register (SPSCR)
206, 214, 230–231
T
T8 bit (SCI transmitted bit 8) 271
T8 bit (transmitted SCI bit 8) 241
TC bit (SCI transmission complete bit) 264,
268, 274
TC bit (transmission complete bit) 68, 246
TCIE bit (SCI transmission complete interrupt
enable bit) 268, 274
TE bit (SCI transmitter enable bit) 246, 269
TE bit (transmitter enable bit) 241
TECx bits (DMA transfer enable bits) 77,
120–121, 135–136
transmit data register 67, 206–207, 209,
211, 213, 224, 230, 232, 234
SPMSTR bit (SPI master mode bit) 205, 207,
225, 229
SPR[0:1] bits (SPI baud rate select bits) 206
SPR1[1:0] bits (SPI baud rate select bits) 233
MC68HC708XL36
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Ind e x
TIM 172, 199
TRST bit (TIM reset bit) 182, 189, 191, 196
clock input pin (TCLK) 177, 186
DMA service requests 121
in stop mode 184
TSTOP bit (TIM stop bit) 182, 189, 196
TXINV bit 265
TXINV bit (SCI transmit inversion bit) 246, 265
in wait mode 184
prescaler 177
TIM channel registers
U
ultraviolet light 36
user vectors 22
(TCH0H/L–TCH3H/L) 177–181,
186, 197, 199
addresses 32
TIM channel registers (TCHxH/L) 177
TIM channel status and control registers
(TSC0–TSC3) 178, 181, 192
TIM counter modulo registers (TMODH/L)
67, 180, 183, 192
TIM counter modulo registers
(TMODH:TMODL) 182
TIM counter registers (TCNTH/L) 191, 194
TIM counter registers
V
V bit (overflow flag) 46
V
V
pin 17
DD
pin 18, 96, 108–109
DDA
voltage-controlled oscillator (VCO) 92, 97, 99
VRS[7:4] bits (VCO range select bits) 103
V
pin 17
SS
(TCNTH:TCNTL) 191
TIM DMA select register (TDMA) 183, 190,
195
W
WAIT instruction 74, 76, 130, 138, 153, 184,
223, 261, 309, 332
TIM modulo registers
wait mode 75–76, 78–79, 130, 153, 184, 189,
223, 261, 309, 332
exit by break interrupt 155
WAKE bit (SCI wake-up condition bit) 265
Web server 372
(TMODH:TMODL) 173
TIM status and control register (TSC) 67,
177, 182–183, 188, 196
TIM counter 173, 185
TOF bit (TIM overflow bit) 67, 183
TOF bit (TIM overflow flag bit) 188, 192
TOIE bit (TIM overflow interrupt enable bit) 67,
183, 188
Web site 372
X
XLD bit (crystal loss detect bit) 101
TOVx (TIM toggle on overflow bits) 183
TOVx bits (TIM overflow bits) 182
TOVx bits (TIM toggle on overflow bits) 183,
198
Z
Z bit (zero flag) 47
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