MC68HC711F1CFB1_技术文档

Freescale Semiconductor, Inc.

HC11

MC68HC11D3

Technical Data

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

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Freescale Semiconductor, Inc.

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TABLE OF CONTENTS

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Section 1

INTRODUCTION

1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Section 2

PIN DESCRIPTIONS

2.1 V_DD, V_SS, and EV_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.3 Crystal Driver and External Clock Input (XTAL, EXTAL) . . . . . . . . . . . . . . . . . . . . 2-3

2.4 E-Clock Output (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.5 Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.6 Non-Maskable Interrupt (XIRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.7 MODA and MODB (MODA/LIR,and MODB/V_STBY). . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.8 PD6/AS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.9 PD7/R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.10 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.10.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.10.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.10.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.10.4 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Section 3

CENTRAL PROCESSING UNIT

3.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Accumulators A, B, and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.2 Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.3 Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.1.6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.1.6.1 Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.1.6.2 Overflow (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.1.6.3 Zero (Z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.1.6.4 Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.1.6.5 Interrupt Mask (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.1.6.6 Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.1.6.7 X Interrupt Mask (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.1.6.8 Stop Disable (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.2 Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.3 Opcodes and Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.4 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.4.1 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4.2 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4.2.1 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4.2.2 Indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4.2.3 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4.2.4 Relative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

TECHNICAL DATA

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Section 4

OPERATING MODES AND ON-CHIP MEMORY

4.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.2 Expanded Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.3 Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.1.4 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.1 Priority and Mode Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.2.2 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.2.2.1 CONFIG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.2.2.2 INIT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.2.2.3 OPTION Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Section 5

RESETS AND INTERRUPTS

5.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.2 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.3 COP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.4 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.1.5 Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.1.6 CONFIG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.3 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.2.4 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.2.5 Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.2.6 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.2.7 COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.2.8 SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.2.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.2.10 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.3 Reset and Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.3.1 Highest Priority Interrupt and Miscellaneous Register . . . . . . . . . . . . . . . . . 5-7

5.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.4.1 Interrupt Recognition and Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.4.2 Non-Maskable Interrupt Request XIRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.4.3 Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.4.4 Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5.4.5 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5.4.6 Reset and Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5.5 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

5.5.1 WAIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

5.5.2 STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

Section 6

PARALLEL I/O

6.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.3 Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

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6.4 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.5 Parallel I/O Control Register (PIOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Section 7

SERIAL COMMUNICATIONS INTERFACE

7.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.3 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.4 Wake-up Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.4.1 Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.4.2 Address-Mark Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.5 SCI Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.6 SCI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.6.1 Serial Communications Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . 7-5

7.6.2 Serial Communications Control Register 1 (SCCR1). . . . . . . . . . . . . . . . . . 7-5

7.6.3 Serial Communications Control Register 2 (SCCR2). . . . . . . . . . . . . . . . . . 7-6

7.6.4 Serial Communication Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . 7-7

7.6.5 Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.7 Status Flags and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

Section 8

SERIAL PERIPHERAL INTERFACE

8.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 SPI Transfer Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.2.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3 SPI Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3.1 Master In Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3.2 Master Out Slave In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3.3 Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3.4 Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.4 SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.5 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.5.1 Serial Peripheral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.5.2 Serial Peripheral Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.5.3 Serial Peripheral Data I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

Section 9

TIMING SYSTEM

9.1 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.2.1 Timer Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.2.2 Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.2.3 Timer Input Capture 4/Output Compare 5 Register . . . . . . . . . . . . . . . . . . . 9-6

9.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.3.1 Timer Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.3.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.3.3 Output Compare Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.3.4 Output Compare 1 Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.5 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.6 Timer Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.7 Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

9.3.8 Timer Interrupt Flag 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

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9.3.9 Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11

9.3.10 Timer Interrupt Flag 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

9.4 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

9.4.1 Timer Interrupt Flag 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13

9.4.2 Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.5 Computer Operating Properly Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . 9-15

9.6 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15

9.6.1 Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

9.6.2 Pulse Accumulator Count Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

9.6.3 Pulse Accumulator Status and Interrupt Bits . . . . . . . . . . . . . . . . . . . . . . . 9-18

Appendix A

ELECTRICAL CHARACTERISTICS

Appendix B

MECHANICAL DATA AND ORDERING INFORMATION

B.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

Appendix C

DEVELOPMENT SUPPORT

C.1 Development System Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

C.2 MC68HC11D3 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

INDEX

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LIST OF ILLUSTRATIONS

Figure

Title

Page

1-1

MC68HC11D3 Block Diagram ........................................................................ 1-2

2-1

2-2

2-3

2-4

2-5

2-6

Pin Assignments for 44-Pin PLCC ................................................................. 2-1

Pin Assignments for 40-Pin DIP ..................................................................... 2-2

External Reset Circuit ..................................................................................... 2-3

Common Crystal Connections ........................................................................ 2-3

External Oscillator Connections ..................................................................... 2-4

One Crystal Driving Two MCUs ..................................................................... 2-4

3-1

3-2

Programming Model ....................................................................................... 3-1

Stacking Operations ....................................................................................... 3-3

4-1

4-2

4-3

Address/Data Demultiplexing ......................................................................... 4-2

MC68HC11D3 Memory Map .......................................................................... 4-3

RAM Standby MODB/V

Connections ...................................................... 4-6

STBY

5-1

5-2

5-3

Processing Flow out of Reset (1 of 2) .......................................................... 5-12

Interrupt Priority Resolution (1 of 2) ............................................................. 5-14

Interrupt Source Resolution within SCI ........................................................ 5-16

7-1

7-2

7-3

7-4

SCI Transmitter Block Diagram ...................................................................... 7-2

SCI Receiver Block Diagram .......................................................................... 7-3

SCI Baud Rate Diagram ............................................................................... 7-10

Interrupt Source Resolution within SCI ........................................................ 7-12

8-1

8-2

SPI Block Diagram ......................................................................................... 8-2

SPI Transfer Format ....................................................................................... 8-3

9-1

9-2

9-3

Timer Clock Divider Chains ............................................................................ 9-2

Capture/Compare Block Diagram .................................................................. 9-4

Pulse Accumulator ....................................................................................... 9-16

A-1

A-2

A-3

A-4

A-5

A-6

A-7

A-8

A-9

Test Methods ..................................................................................................A-3

Timer Inputs ...................................................................................................A-4

POR and External Reset Timing Diagram ......................................................A-5

STOP Recovery Timing Diagram ...................................................................A-6

WAIT Recovery Timing Diagram ....................................................................A-7

Port Write Timing Diagram .............................................................................A-8

Port Read Timing Diagram .............................................................................A-8

Multiplexed Expansion Bus Timing Diagram ................................................A-10

SPI Master Timing (CPHA = 0) ....................................................................A-12

MC68HC11D3

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LIST OF ILLUSTRATIONS

(Continued)

Figure

Title

Page

A-10

A-11

A-12

SPI Master Timing (CPHA = 1) ....................................................................A-12

SPI Slave Timing (CPHA = 0) ......................................................................A-13

SPI Slave Timing (CPHA = 1) ......................................................................A-13

B-1

B-2

B-3

40-Pin DIP ......................................................................................................B-1

44-Pin PLCC ..................................................................................................B-2

44-Pin QFP .....................................................................................................B-3

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LIST OF TABLES

Table

Title

Page

2-1 Port Signal Functions............................................................................................. 2-6

3-2 Instruction Set........................................................................................................ 3-8

4-1 Register and Control Bit Assignments ................................................................. 4-4

4-2 Hardware Mode Select Summary.......................................................................... 4-6

4-3 RAM Mapping........................................................................................................ 4-9

4-4 Register Mapping................................................................................................... 4-9

5-1 COP Time-out........................................................................................................ 5-2

5-2 Reset Cause, Reset Vector, and Operating Mode ................................................ 5-4

5-3 Highest Priority Interrupt Selection ........................................................................ 5-8

5-4 Interrupt and Reset Vector Assignments............................................................... 5-9

5-5 Stacking Order on Entry to Interrupts .................................................................. 5-10

7-1 Baud Rate Prescale Selects.................................................................................. 7-8

7-2 Baud Rate Selects................................................................................................ 7-9

9-1 Timer Summary ..................................................................................................... 9-3

9-2 Timer Control Configuration................................................................................... 9-5

9-3 Pulse Accumulator Timing................................................................................... 9-16

A-1 Maximum Ratings..................................................................................................A-1

A-2 Thermal Characteristics ........................................................................................A-1

A-3 DC Electrical Characteristics.................................................................................A-2

A-4 Control Timing.......................................................................................................A-4

A-5 Peripheral Port Timing...........................................................................................A-8

A-6 Expansion Bus Timing...........................................................................................A-9

A-7 Serial Peripheral Interface Timing.......................................................................A-11

B-1 Ordering Information .............................................................................................B-3

MC68HC11D3

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SECTION 1

INTRODUCTION

The MC68HC11D3 and MC68HC11D0 are ROM-based high-performance microcon-

trollers (MCUs) based on the MC68HC11E9 design. Members of the Dx series are de-

rived from the same mask and feature a high speed multiplexed bus capable of

running at up to 3 MHz, and a fully static design that allows operations at frequencies

to dc.

The only difference between the MCUs in the Dx series is whether or not the ROM has

been tested and guaranteed.

1.1 Features

• MC68HC11 CPU

• Power Saving STOP and WAIT Modes

• 4 Kbytes of On-Chip ROM

• 192 Bytes of On-Chip RAM (All Saved During Standby)

• 16-Bit Timer System

— 3 Input Capture (IC) Channels

— 4 Output Compare (OC) Channels

— One IC or OC Channel (Software Selectable)

• 8-Bit Pulse Accumulator

• Real-Time Interrupt Circuit

• Computer Operating Properly (COP) Watchdog System

• Synchronous Serial Peripheral Interface (SPI)

• Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)

• 26 Input/Output (I/O) Pins

— 16 Bidirectional I/O Pins

— 3 Input Only Pins

— 3 Output Only Pins (One Output Only Pin in the 40-Pin Package)

• Available in a 44-Pin Plastic Leaded Chip Carrier (PLCC) and 40-Pin Dual In-Line

Package (DIP)

1.2 Structure

Refer to Figure 1-1, which shows the structure of the MC68HC11D3 MCU.

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MODB/

MODA/

LIR

IRQ/

V

XTAL EXTAL

E

XIRQ

RESET

STBY

OSCILLATOR

CLOCK LOGIC

4 KBYTES ROM

192 BYTES RAM

MODE

CONTROL

INTERRUPT LOGIC

R

CPU

E

COP

V

DD

N

SS

R

O

BUS EXPANSION

ADDRESS

R

A

ADDRESS/DATA

W

L

P

U

S

R

TIMER

M

U

SYSTEM

C

SPI

SCI

E A C

I

S

O

STROBE AND HANDSHAKE

PARALLEL I/O

L

D

S

U

CONTROL

PORT B

CONTROL

PORT C

CONTROL

PORT D

PORT A

Figure 1-1 MC68HC11D3 Block Diagram

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SECTION 2

PIN DESCRIPTIONS

The MC68HC11D3 is available packaged as a 40-pin dual in-line package (DIP), a 44-

pin plastic leaded chip carrier (PLCC), or a 44-pin quad flat pack (QFP). Most pins on

this MCU serve two or more functions, as described in the following paragraphs. Refer

to Figure 2-1 and Figure 2-2, which shows the MC68HC11D3 pin assignments.

39

PB0/ADDR8

PB1/ADDR9

7

PC4/ADDR4

PC5/ADDR5

PC6/ADDR6

8

38

37

36

9

PB2/ADDR10

PB3/ADDR11

10

PC7/ADDR7

11

12

35

PB4/ADDR12

PB5/ADDR13

XIRQ/V

PP

MC68HC(7)11D3

34

33

PD7/R/W

13

14

PB6/ADDR14

PB7/ADDR15

NC

PD6/AS

RESET

32

31

30

15

IRQ

PA0/IC3

PA1/IC2

16

17

PD0/RxD

29

PD1/TxD

Figure 2-1 Pin Assignments for 44-Pin PLCC

. . I n c .

S e m i c o n d u F c r t e o e r , s c a l e

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40 XTAL

V

SS

1

39 EXTAL

PC0/ADDR0

PC1/ADDR1

PC2/ADDR2

PC3/ADDR3

PC4/ADDR4

PC5/ADDR5

PC6/ADDR6

PC7/ADDR7

2

38

E

3

37 MODA/LIR

36 MODB/V

4

5

STBY

35 PB0/ADDR8

34 PB1/ADDR9

33 PB2/ADDR10

32 PB3/ADDR11

31 PB4/ADDR12

30 PB5/ADDR13

29 PB6/ADDR14

28 PB7/ADDR15

27 PA0/IC3

6

7

MC68HC(7)11D3

8

9

XIRQ/V

PP

10

PD7/R/W 11

PD6/AS 12

RESET 13

IRQ 14

26 PA1/IC2

PD0/RxD 15

PD1/TxD 16

PD2/MISO 17

PD3/MOSI 18

PD4/SCK 19

PD5/SS 20

25 PA2/IC1

24 PA3/IC4/OC5/OC1

23 PA5/OC3/OC1

22 PA7/PAI/OC1

21

V

DD

D3 40-PIN DIP

Figure 2-2 Pin Assignments for 40-Pin DIP

2.1 V , V , and EV

DD SS

SS

Power is supplied to the MCU through V

and V . V

is the power supply, and

DD

SS SS

V

is ground. EV , available on the 44-pin PLCC, is an additional ground pin that

SS

must be grounded with V . The MCU operates from a single 5-volt (nominal) power

SS

supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times

place high, short duration current demands on the power supply. To prevent noise

problems, provide good power supply bypassing at the MCU. Also, use bypass capac-

itors that have good high-frequency characteristics and situate them as close to the

MCU as possible. Bypass requirements vary, depending on how heavily the MCU pins

are loaded.

2.2 Reset (RESET)

An active low bidirectional control signal, RESET, acts as an input to initialize the MCU

to a known startup state. It also acts as an open-drain output to indicate that an internal

failure has been detected in either the clock monitor or COP watchdog circuit. The

CPU distinguishes between internal and external reset conditions by sensing whether

the reset pin rises to a logic one in less than two E-clock cycles after a reset has oc-

curred. It is not advisable to connect an external resistor-capacitor (RC) power-up de-

lay circuit to the reset pin of M68HC11 devices because the circuit charge time

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constant can cause the device to misinterpret the type of reset that occurred. Refer to

SECTION 5 RESETS AND INTERRUPTS for further information.

Figure 2-3 illustrates a reset circuit that uses an external switch. Use a low voltage

interrupt circuit, however, to prevent corruption of RAM.

V

DD

2

4.7 kΩ

IN

1

TO RESET

OF M68HC11

RESET

MC34(0/1)64

GND

3

EXT RESET CIRCUIT

Figure 2-3 External Reset Circuit

2.3 Crystal Driver and External Clock Input (XTAL, EXTAL)

These two pins provide the interface for either a crystal or a CMOS compatible clock

to control the internal clock generator circuitry. The frequency applied to these pins is

four times higher than the desired E-clock rate.

The XTAL pin is normally left unterminated when an external CMOS compatible clock

input is connected to the EXTAL pin. However, a 10 kΩ to 100 kΩ load resistor con-

nected from XTAL to ground can be used to reduce RFI noise emission. The XTAL

output is normally intended to drive only a crystal. The XTAL output can be buffered

with a high impedance buffer, or it can be used to drive the EXTAL input of another

M68HC11.

In all cases, use caution around the oscillator pins. Load capacitances shown in the

oscillator circuits include all stray layout capacitances. Refer to Figure 2-4, Figure 2-

5, and Figure 2-6.

25 pF *

EXTAL

10 MΩ

4 x E

CRYSTAL

MCU

25 pF *

XTAL

* THIS VALUE INCLUDES ALL STRAY CAPACITANCES.

COMMON XTAL CONN

Figure 2-4 Common Crystal Connections

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4 x E

EXTAL

CMOS-COMPATIBLE

EXTERNAL OSCILLATOR

MCU

XTAL

NC

EXT EXTAL CONN

Figure 2-5 External Oscillator Connections

220 Ω

25 pF *

EXTAL

SECOND

MCU

10 MΩ

4 x E

CRYSTAL

FIRST

MCU

25 pF *

NC

XTAL

* THIS VALUE INCLUDES ALL STRAY CAPACITANCES.

DUAL-MCU XTAL CONN

Figure 2-6 One Crystal Driving Two MCUs

2.4 E-Clock Output (E)

E is the output connection for the internally generated E clock. The signal from E is

used as a timing reference. The frequency of the E-clock output is one fourth that of

the input frequency at the XTAL and EXTAL pins. When E-clock output is low, an in-

ternal process is taking place. When it is high, data is being accessed. All clocks, in-

cluding the E clock, are halted when the MCU is in STOP mode. The E clock can be

turned off in single-chip modes to reduce the effects of radio frequency interference

(RFI).

2.5 Interrupt Request (IRQ)

The IRQ input provides a means of applying asynchronous interrupt requests to the

MCU. Either negative edge-sensitive triggering or level-sensitive triggering is program

selectable (OPTION register). IRQ is always configured to level-sensitive triggering at

reset. Connect an external pullup resistor, typically 4.7 kΩ, to V

when IRQ is used

DD

in a level sensitive wired-OR configuration.

2.6 Non-Maskable Interrupt (XIRQ)

The XIRQ input provides a means of requesting a nonmaskable interrupt after reset

initialization. During reset, the X bit in the condition code register (CCR) is set and any

interrupt is masked until MCU software enables it. Because the XIRQ input is level-

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sensitive, it can be connected to a multiple-source wired-OR network with an external

pullup resistor to V . XIRQ is often used as a power loss detect interrupt.

DD

Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ must be config-

ured for level-sensitive operation if there is more than one source of IRQ interrupt),

each source must drive the interrupt input with an open-drain type of driver to avoid

contention between outputs. There should be a single pullup resistor near the MCU

interrupt input pin (typically 4.7 kΩ). There must also be an interlock mechanism at

each interrupt source so that the source holds the interrupt line low until the MCU rec-

ognizes and acknowledges the interrupt request. If one or more interrupt sources are

still pending after the MCU services a request, the interrupt line will still be held low

and the MCU will be interrupted again as soon as the interrupt mask bit in the MCU is

cleared (normally upon return from an interrupt). Refer to SECTION 5 RESETS AND

INTERRUPTS.

2.7 MODA and MODB (MODA/LIR,and MODB/V

)

STBY

During reset, MODA and MODB select one of the four operating modes. Refer to SEC-

TION 4 OPERATING MODES AND ON-CHIP MEMORY.

After the operating mode has been selected, the LIR pin provides an open-drain output

to indicate that execution of an instruction has begun. A series of E-clock cycles occurs

during execution of each instruction. The LIR signal goes low during the first E-clock

cycle of each instruction (opcode fetch). This output is provided for assistance in pro-

gram debugging.

The V

pin is used to input RAM standby power. When the voltage on this pin is

STBY

more than one MOS threshold (about 0.7 volts) above the V

voltage, the internal

DD

192-byte RAM and part of the reset logic are powered from this signal rather than the

input. This allows RAM contents to be retained without V power applied to the

V

DD

MCU. Reset must be driven low before V is removed and must remain low until V

DD

has been restored to a valid level.

2.8 PD6/AS

This pin performs either of two separate functions, depending on the operating mode.

In single-chip and bootstrap modes, the pin functions as input/output port D bit 6. In

the expanded multiplexed and test modes, it provides an address strobe (AS) function.

The AS can demultiplex the address and data signals at port C. Refer to SECTION 4

OPERATING MODES AND ON-CHIP MEMORY for further information.

2.9 PD7/R/W

This pin provides two separate functions, depending on the operating mode. In single-

chip and bootstrap modes, PD7/R/W acts as input/output port D bit 7. Refer to SEC-

TION 6 PARALLEL I/O for further information.

In expanded multiplexed and test modes, PD7/R/W performs a read/write function.

PD7/R/W controls the direction of transfers on the external data bus. A high on this pin

indicates that a read cycle is in progress.

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2.10 Port Signals

In the 44-pin PLCC package, 32 input/output lines are arranged into four 8-bit ports:

A, B, C, and D. The lines of ports B, C, and D are fully bidirectional. Each of these four

ports serves a purpose other than I/O, depending on the operating mode or peripheral

functions selected. Note that ports B, C, and two bits of port D are available for I/O

functions only in single-chip and bootstrap modes. Refer to Table 2-1 for details about

the 32 port signals' functions within different operating modes.

Table 2-1 Port Signal Functions

Port/Bit

Single-Chip and

Bootstrap Mode

Expanded Multiplexed and

Special Test Mode

PA0

PA1

PA2

PA3

PA4*

PA5

PA6*

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PA0/IC3

PA1/IC2

PA2/IC1

PA3/OC5/IC4/OC1

PA4/OC4/OC1

PA5/OC3/OC1

PA6/OC2/OC1

PA7/PAI/OC1

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR0/DATA0

ADDR1/DATA1

ADDR2/DATA2

ADDR3/DATA3

ADDR4/DATA4

ADDR5/DATA5

ADDR6/DATA6

ADDR7/DATA7

PD0/RxD

PD1/TxD

PD2/MISO

PD3/MOSI

PD4/SCK

PD5/SS

PD6

PD7

AS

R/W

*In the 40-pin package, pins PA4 and PA6 are not bonded. Their associated I/O and output compare functions are

not available externally. They can still be used as internal software timers, however.

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2.10.1 Port A

Port A can be read at any time. Inputs return the pin level; outputs return the pin driver

input level. If written, port A stores the data in an internal latch. It drives the pins only

if they are configured as outputs. Writes to port A do not change the pin state when

the pins are configured for timer output compares.

Out of reset, port A bits 7 and [3:0] are general high impedance inputs, while bits [6:4]

are outputs, driving low. Bidirectional lines PA7 and PA3 in PACTL are not changed

and do not have any effect on those bits. When the output compare functions associ-

ated with these pins are disabled, the DDR bits in PACTL govern the I/O state.

Refer to SECTION 6 PARALLEL I/O.

2.10.2 Port B

Port B is an 8-bit general-purpose I/O port with a data register (PORTB) and a data

direction register (DDRB). In single-chip mode, port B pins are general-purpose I/O

pins (PB[7:0]). In the expanded multiplexed mode, all of the port B pins act as the high-

order address bits (ADDR[15:8]) of the address bus.

Port B can be read at any time. Inputs return the sensed levels at the pin, while outputs

return the input level of the port B pin drivers. If port B is written, the data is stored in

an internal latch and can be driven only if port B is configured as general-purpose out-

puts in single-chip or bootstrap modes.

Port B pins are general-purpose inputs out of reset in single-chip and bootstrap

modes. These pins are outputs (the high order address bits) out of reset in expanded

multiplexed and test modes.

Refer to SECTION 6 PARALLEL I/O.

2.10.3 Port C

Port C is an 8-bit general-purpose I/O port with a data register (PORTC) and a data

direction register (DDRC). In the single-chip mode, port C pins are general-purpose I/

O pins (PC[7:0]). In the expanded multiplexed mode, port C pins are configured as

multiplexed address/data pins. During the address cycle, bits [7:0] of the address are

output on PC[7:0]. During the data cycle, bits [7:0] (PC[7:0]) are bidirectional data pins

controlled by the R/W signal.

Port C can be read at any time. Inputs return the sensed levels at the pin, while outputs

return the input level of the port C pin drivers. If port C is written, the data is stored in

an internal latch and can be driven only if port C is configured for general-purpose out-

puts in single-chip or bootstrap mode. Port C pins are general-purpose inputs out of

reset in single-chip and bootstrap modes. These pins are multiplexed low-order ad-

dress and data bus lines out of reset in expanded multiplexed and test modes.

The CWOM control bit in the PIOC register disables port C's P-channel output driver.

CWOM simultaneously affects all eight bits of port C. Because the N-channel driver is

not affected by CWOM, setting CWOM causes port C to become an open-drain-type

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output port suitable for wired-OR operation. In wired-OR mode (a port C bit is at logic

level zero), it is actively driven low by the N-channel driver. When a port C bit is at logic

level one, the associated pin has high impedance, as neither the N- nor the P-channel

devices are active. It is customary to have an external pullup resistor on lines that are

driven by open-drain devices. Port C can only be configured for wired-OR operation

when the MCU is in single-chip mode. Refer to SECTION 6 PARALLEL I/O for addi-

tional information about port C functions.

2.10.4 Port D

Port D, an 8-bit, general-purpose I/O port has a data register (PORTD) and a data di-

rection register (DDRD). The eight port D bits (D[7:0]) can be used for general-purpose

I/O, for the serial communications interface (SCI) and serial peripheral interface (SPI)

subsystems, or for bus data direction control.

Port D can be read at any time and inputs return the sensed levels at the pin; whereas,

the outputs return the input level of the port D pin drivers. If PORTD is written, the data

is stored in an internal latch, and can be driven only if port D is configured for general-

purpose output. This port shares functions with the on-chip SCI and SPI subsystems,

while bits 6 and 7 control the direction of data flow on the bus in expanded and special

test modes.

Refer to SECTION 6 PARALLEL I/O.

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SECTION 3

CENTRAL PROCESSING UNIT

This section presents information on M68HC11 central processing unit (CPU) archi-

tecture, data types, addressing modes, the instruction set, and special operations,

such as subroutine calls and interrupts.

The CPU is designed to treat all peripheral, I/O, and memory locations identically as

addresses in the 64 Kbyte memory map. This is referred to as memory-mapped I/O.

There are no special instructions for I/O that are separate from those used for memory.

This architecture also allows accessing an operand from an external memory location

with no execution-time penalty.

3.1 CPU Registers

M68HC11 CPU registers are an integral part of the CPU and are not addressed as if

they were memory locations. The seven registers, discussed in the following para-

graphs, are shown in Figure 3-1.

8-BIT ACCUMULATORS A & B

OR 16-BIT DOUBLE ACCUMULATOR D

7

15

A

0

7

B

0

D

IX

IY

INDEX REGISTER X

INDEX REGISTER Y

STACK POINTER

SP

PC

PROGRAM COUNTER

CONDITION CODES

7

S

0

X

H

I

N

Z

V

C

CARRY/BORROW FROM MSB

OVERFLOW

ZERO

NEGATIVE

I-INTERRUPT MASK

HALF CARRY (FROM BIT 3)

X-INTERRUPT MASK

STOP DISABLE

HC11 PROG MODEL

Figure 3-1 Programming Model

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3.1.1 Accumulators A, B, and D

Accumulators A and B are general-purpose 8-bit registers that hold operands and re-

sults of arithmetic calculations or data manipulations. For some instructions, these two

accumulators are treated as a single double-byte (16-bit) accumulator called accumu-

lator D. Although most operations can use accumulators A or B interchangeably, the

following exceptions apply:

The ABX and ABY instructions add the contents of 8-bit accumulator B to the contents

of 16-bit register X or Y, but there are no equivalent instructions that use A instead of B.

The TAP and TPA instructions transfer data from accumulator A to the condition code

register, or from the condition code register to accumulator A, however there are no

equivalent instructions that use B rather than A.

The decimal adjust accumulator (DAA) instruction is used after binary-coded decimal

(BCD) arithmetic operations, but there is no equivalent BCD instruction to adjust ac-

cumulator B.

The add, subtract, and compare instructions associated with both A and B (ABA, SBA,

and CBA) only operate in one direction, making it important to plan ahead to ensure

the correct operand is in the correct accumulator.

3.1.2 Index Register X (IX)

The IX register provides a 16-bit indexing value that can be added to the 8-bit offset

provided in an instruction to create an effective address. The IX register can also be

used as a counter or as a temporary storage register.

3.1.3 Index Register Y (IY)

The 16-bit IY register performs an indexed mode function similar to that of the IX reg-

ister. However, most instructions using the IY register require an extra byte of machine

code and an extra cycle of execution time because of the way the opcode map is im-

plemented. Refer to 3.3 Opcodes and Operands for further information.

3.1.4 Stack Pointer (SP)

The M68HC11 CPU has an automatic program stack. This stack can be located any-

where in the address space and can be any size up to the amount of memory available

in the system. Normally the SP is initialized by one of the first instructions in an appli-

cation program. The stack is configured as a data structure that grows downward from

high memory to low memory. Each time a new byte is pushed onto the stack, the SP

is decremented. Each time a byte is pulled from the stack, the SP is incremented. At

any given time, the SP holds the 16-bit address of the next free location in the stack.

Figure 3-2 is a summary of SP operations.

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JSR, JUMP TO SUBROUTINE

WAI, WAIT FOR INTERRUPT

STACK

7

0

7

0

MAIN PROGRAM

INTERRUPT ROUTINE

$3E = WAI

SP

SP+1

SP+2

SP+3

SP+4

SP+5

SP+6

SP+7

SP+8

➩ SP+9

PC

SP

SP+1

SP+2

SP+3

SP+4

SP+5

SP+6

SP+7

SP+8

➩ SP+9

$9D = JSR

dd

CCR

ACCB

ACCA

DIRECT

INDEXED, X

INDEXED, Y

CCR

ACCB

ACCA

RTN

NEXT MAIN INSTR.

MAIN PROGRAM

IX

H

IX

H

PC

$AD = JSR

IX

L

IX

L

ff

IY

H

IY

H

RTN

NEXT MAIN INSTR.

IY

L

IY

L

RTN

H

RTN

H

MAIN PROGRAM

RTN

L

RTN

L

PC

$18 = PRE

$AD = JSR

ff

SWI, SOFTWARE INTERRUPT

RTN

STACK

7

0

MAIN PROGRAM

NEXT MAIN INSTR.

PC

➩ SP–9

SP–8

SP–7

SP–6

SP–5

SP–4

SP–3

SP–2

SP–1

SP

$3F = SWI

CCR

ACCB

ACCA

MAIN PROGRAM

PC

$BD = PRE

hh

INDEXED, Y

IX

H

RTN

ll

WAI, WAIT FOR INTERRUPT

IX

L

NEXT MAIN INSTR.

MAIN PROGRAM

IY

H

PC

IY

$3E = WAI

L

JMP, JUMP

RTN

H

RTN

MAIN PROGRAM

L

PC

$6E = JMP

ff

BSR, BRANCH TO SUBROUTINE

INDEXED, X

STACK

7

0

MAIN PROGRAM

PC

➩ SP–2

SP–1

SP

$8D = BSR

X + ff

PC

NEXT MAIN INSTR.

MAIN PROGRAM

RTN

H

RTN

L

$18 = PRE

$6E = JMP

ff

RTS, RETURN FROM

SUBROUTINE

INDEXED, Y

STACK

7

0

MAIN PROGRAM

PC

SP

SP+1

$39 = RTS

X + ff

PC

NEXT MAIN INSTR.

MAIN PROGRAM

RTN

H

➩ SP+2

RTN

L

$7E = JMP

LEGEND:

hh

ll

RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO

EXTENDED

BE EXECUTED UPON RETURN FROM SUBROUTINE

RTN

=

MOST SIGNIFICANT BYTE OF RETURN ADDRESS

LEAST SIGNIFICANT BYTE OF RETURN ADDRESS

H

L

➩ = STACK POINTER POSITION AFTER OPERATION IS COMPLETE

dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED

TO BE $00)

hh ll

NEXT MAIN INSTR.

ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (256) IS ADDED TO INDEX

hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS

ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS

rr= SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET

RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE

OFFSET BYTE)

HC11 STACK OPERATIONS

Figure 3-2 Stacking Operations

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When a subroutine is called by a jump to subroutine (JSR) or branch to subroutine

(BSR) instruction, the address of the instruction after the JSR or BSR is automatically

pushed onto the stack, least significant byte first. When the subroutine is finished, a

return from subroutine (RTS) instruction is executed. The RTS pulls the previously

stacked return address from the stack, and loads it into the program counter. Execu-

tion then continues at this recovered return address.

When an interrupt is recognized, the current instruction finishes normally, the return

address (the current value in the program counter) is pushed onto the stack, all of the

CPU registers are pushed onto the stack, and execution continues at the address

specified by the vector for the interrupt. At the end of the interrupt service routine, an

RTI instruction is executed. The RTI instruction causes the saved registers to be pulled

off the stack in reverse order. Program execution resumes at the return address.

There are instructions that push and pull the A and B accumulators and the X and Y

index registers. These instructions are often used to preserve program context. For ex-

ample, pushing accumulator A onto the stack when entering a subroutine that uses ac-

cumulator A, and then pulling accumulator A off the stack just before leaving the

subroutine, ensures that the contents of a register will be the same after returning from

the subroutine as it was before starting the subroutine.

3.1.5 Program Counter (PC)

The program counter, a 16-bit register, contains the address of the next instruction to

be executed. After reset, the program counter is initialized from one of six possible

vectors, depending on operating mode and the cause of reset.

Table 3-1 Reset Vector Comparison

POR or Pin

$FFFE, F

$BFFE, F

Clock Monitor

$FFFC, D

COP Watchdog

$FFFA, B

Normal

Test or Boot

$BFFC, D

$BFFA, B

3.1.6 Condition Code Register (CCR)

This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two inter-

rupt masking bits, (IRQ and XIRQ) and a stop disable bit (S). In the M68HC11 CPU,

condition codes are automatically updated by most instructions. For example, load ac-

cumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or

clear the N, Z, and V condition code flags. Pushes, pulls, add B to X (ABX), add B to

Y (ABY), and transfer/exchange instructions do not affect the condition codes. Refer

to Table 3-2, which shows what condition codes are affected by a particular instruc-

tion.

3.1.6.1 Carry/Borrow (C)

The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an

arithmetic operation. The C bit also acts as an error flag for multiply and divide opera-

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tions. Shift and rotate instructions operate with and through the carry bit to facilitate

multiple-word shift operations.

3.1.6.2 Overflow (V)

The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V

bit is cleared.

3.1.6.3 Zero (Z)

The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is

zero. Otherwise, the Z bit is cleared. Compare instructions do an internal implied sub-

traction and the condition codes, including Z, reflect the results of that subtraction. A

few operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags.

For these operations, only = and - conditions can be determined.

3.1.6.4 Negative (N)

The N bit is set if the result of an arithmetic, logic, or data manipulation operation is

negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative if its

most significant bit (MSB) is a one. A quick way to test whether the contents of a mem-

ory location has the MSB set is to load it into an accumulator and then check the status

of the N bit.

3.1.6.5 Interrupt Mask (I)

The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable in-

terrupt sources. While the I bit is set, interrupts can become pending, but the operation

of the CPU continues uninterrupted until the I bit is cleared. After any reset, the I bit is

set by default and can only be cleared by a software instruction. When an interrupt is

recognized, the I bit is set after the registers are stacked, but before the interrupt vector

is fetched. After the interrupt has been serviced, a return from interrupt instruction is

normally executed, restoring the registers to the values that were present before the

interrupt occurred. Normally, the I bit is zero after a return from interrupt is executed.

Although the I bit can be cleared within an interrupt service routine, “nesting” interrupts

in this way should only be done when there is a clear understanding of latency and of

the arbitration mechanism. Refer to SECTION 5 RESETS AND INTERRUPTS.

3.1.6.6 Half Carry (H)

The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit

during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half carry is

used during BCD operations.

3.1.6.7 X Interrupt Mask (X)

The XIRQ mask (X) bit disables interrupts from the pin. After any reset, X is set by de-

fault and must be cleared by a software instruction. When an interrupt is recognized,

the X and I bits are set after the registers are stacked, but before the interrupt vector

is fetched. After the interrupt has been serviced, an RTI instruction is normally execut-

ed, causing the registers to be restored to the values that were present before the in-

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terrupt occurred. The X interrupt mask bit is set only by hardware (or acknowledge). X

is cleared only by program instruction (TAP, where the associated bit of A is 0; or RTI,

where bit 6 of the value loaded into the CCR from the stack has been cleared). There

is no hardware action for clearing X.

3.1.6.8 Stop Disable (S)

Setting the STOP disable (S) bit prevents the STOP instruction from putting the

M68HC11 into a low-power stop condition. If the STOP instruction is encountered by

the CPU while the S bit is set, it is treated as a no-operation (NOP) instruction, and

processing continues to the next instruction. S is set by reset —STOP disabled by de-

fault.

3.2 Data Types

The M68HC11 CPU supports the following data types:

• Bit data

• 8-bit and 16-bit signed and unsigned integers

• 16-bit unsigned fractions

• 16-bit addresses

A byte is eight bits wide and can be accessed at any byte location. A word is composed

of two consecutive bytes with the most significant byte at the lower value address. Be-

cause the M68HC11 is an 8-bit CPU, there are no special requirements for alignment

of instructions or operands.

3.3 Opcodes and Operands

The M68HC11 family of microcontrollers uses 8-bit opcodes. Each opcode identifies

a particular instruction and associated addressing mode to the CPU. Several opcodes

are required to provide each instruction with a range of addressing capabilities. Only

256 opcodes would be available if the range of values were restricted to the number

able to be expressed in 8-bit binary numbers.

A four-page opcode map has been implemented to expand the number of instructions.

An additional byte, called a prebyte, directs the processor from page 0 of the opcode

map to one of the other three pages. As its name implies, the additional byte precedes

the opcode.

A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or

three operands. The operands contain information the CPU needs for executing the

instruction. Complete instructions can be from one to five bytes long.

3.4 Addressing Modes

Six addressing modes; immediate, direct, extended, indexed, inherent, and relative,

detailed in the following paragraphs, can be used to access memory. All modes except

inherent mode use an effective address. The effective address is the memory address

from which the argument is fetched or stored, or the address from which execution is

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to proceed. The effective address can be specified within an instruction, or it can be

calculated.

3.4.1 Immediate

In the immediate addressing mode an argument is contained in the byte(s) immediate-

ly following the opcode. The number of bytes following the opcode matches the size

of the register or memory location being operated on. There are two-, three-, and four-

(if prebyte is required) byte immediate instructions. The effective address is the ad-

dress of the byte following the instruction.

3.4.2 Direct

In the direct addressing mode, the low-order byte of the operand address is contained

in a single byte following the opcode, and the high-order byte of the address is as-

sumed to be $00. Addresses $00–$FF are thus accessed directly, using two-byte in-

structions. Execution time is reduced by eliminating the additional memory access

required for the high-order address byte. In most applications, this 256-byte area is re-

served for frequently referenced data. In M68HC11 MCUs, the memory map can be

configured for combinations of internal registers, RAM or external memory to occupy

these addresses.

3.4.2.1 Extended

In the extended addressing mode, the effective address of the argument is contained

in two bytes following the opcode byte. These are three-byte instructions (or four-byte

instructions if a prebyte is required). One or two bytes are needed for the opcode and

two for the effective address.

3.4.2.2 Indexed

In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction

is added to the value contained in an index register (IX or IY) — the sum is the effective

address. This addressing mode allows referencing any memory location in the 64

Kbyte address space. These are from two- to five-byte instructions, depending on

whether or not a prebyte is required.

3.4.2.3 Inherent

In the inherent addressing mode, all the information necessary to execute the instruc-

tion is contained in the opcode. Operations that use only the index registers or accu-

mulators, as well as control instructions with no arguments, are included in this

addressing mode. These are one- or two-byte instructions.

3.4.2.4 Relative

The relative addressing mode is used only for branch instructions. If the branch con-

dition is true, an 8-bit signed offset included in the instruction is added to the contents

of the program counter to form the effective branch address. Otherwise, control pro-

ceeds to the next instruction. These are usually two-byte instructions.

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3.5 Instruction Set

Refer to Table 3-2, which shows all the M68HC11 instructions in all possible address-

ing modes. For each instruction, the table shows the operand construction, the number

of machine code bytes, and execution time in CPU E-clock cycles.

Table 3-2 Instruction Set (Sheet 1 of 7)

Mnemonic

Operation

Description

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Opcode

1B

S

—

X

—

H

I

N

Z

V

C

ABA

Add

A + B

A

INH

—

2

∆

—

∆

Accumulators

ABX

ABY

Add B to X

Add B to Y

IX + (00 : B)

IY + (00 : B)

A + M + C

IX

IY

A

INH

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

3A

89 ii

99 dd

B9 hh ll

A9 ff

C9 ii

D9 dd

F9 hh ll

E9 ff

8B ii

9B dd

BB hh ll

AB ff

CB ii

DB dd

FB hh ll

EB ff

—

3

4

2

3

4

5

2

3

4

5

2

3

4

5

—

∆

—

∆

—

∆

—

∆

—

∆

18

ADCA (opr) Add with Carry

to A

A

B

A

B

ADCB (opr) Add with Carry

to B

B + M + C

B

—

∆

—

∆

0

∆

ADDA (opr)

ADDB (opr)

Add Memory

to A

A + M

A

B

Add Memory

to B

B + M

2

3

4

5

∆

IND,X

IND,Y

EB ff

ADDD (opr) Add 16-Bit to D D + (M : M + 1)

D

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

EXT

IND,X

IND,Y

C3 jj kk

D3 dd

F3 hh ll

E3 ff

84 ii

94 dd

B4 hh ll

A4 ff

C4 ii

D4 dd

F4 hh ll

E4 ff

78 hh ll

68 ff

4

5

6

7

2

3

4

5

2

3

4

5

6

7

—

∆

ANDA (opr)

ANDB (opr)

ASL (opr)

AND A with

Memory

A • M

B • M

A

B

A

B

—

∆

AND B with

Memory

18

Arithmetic

Shift Left

0

68 ff

b7

b0

C

ASLA

ASLB

Arithmetic

Shift Left A

A

B

INH

48

58

05

—

2

3

—

∆

0

b7

b0

C

Arithmetic

Shift Left B

—

ASLD

Arithmetic

Shift Left D

∆

0

b7A b0 b7 B b0

C

ASR

Arithmetic

Shift Right

EXT

IND,X

IND,Y

77 hh ll

67 ff

6

7

∆

18

b7

b0

C

ASRA

ASRB

BCC (rel)

Arithmetic

Shift Right A

A

B

INH

REL

47

—

2

3

∆

Arithmetic

Shift Right B

57

—

∆

Branch if Carry

Clear

? C = 0

24 rr

—

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Table 3-2 Instruction Set (Sheet 2 of 7)

Mnemonic

Operation

Description

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Opcode

S

X

H

I

N

Z

V

C

BCLR (opr)

Clear Bit(s)

M • (mm)

M

DIR

IND,X

IND,Y

15 dd mm

1D ff mm

6

7

8

—

∆

0

—

(msk)

18

BCS (rel)

BEQ (rel)

BGE (rel)

BGT (rel)

BHI (rel)

BHS (rel)

Branch if Carry

Set

Branch if =

Zero

Branch if ∆

Zero

? C = 1

? Z = 1

REL

25 rr

27 rr

2C rr

2E rr

22 rr

24 rr

3

—

? N V = 0

? Z + (N V) = 0

? C + Z = 0

? C = 0

Branch if >

Zero

Branch if

Higher

Branch if

Higher or

Same

BITA (opr)

Bit(s) Test A

with Memory

A • M

A

IMM

DIR

EXT

IND,X

IND,Y

85 ii

—

∆

0

—

2

3

4

5

2

3

4

5

95 dd

B5 hh ll

A5 ff

18

A5 ff

BITB (opr)

Bit(s) Test B

with Memory

B • M

B

IMM

DIR

EXT

IND,X

IND,Y

C5 ii

—

∆

0

—

D5 dd

F5 hh ll

E5 ff

BLE (rel)

BLO (rel)

BLS (rel)

Branch if ∆

Zero

? Z + (N V) = 1

? C = 1

REL

2F rr

25 rr

23 rr

—

3

Branch if

Lower

Branch if

Lower or

Same

? C + Z = 1

BLT (rel)

BMI (rel)

BNE (rel)

Branch if <

Zero

Branch if

Minus

Branch if not =

Zero

? N V = 1

? N = 1

REL

2D rr

2B rr

26 rr

—

3

? Z = 0

BPL (rel)

BRA (rel)

Branch if Plus

? N = 0

? 1 = 1

REL

2A rr

20 rr

—

3

6

7

8

Branch Always

BRCLR(opr)

Branch if

Bit(s) Clear

DIR

IND,X

IND,Y

13 dd mm rr

1F ff mm rr

? M • mm = 0

(msk)

(rel)

18

Branch Never

REL

21 rr

—

BRN (rel)

BRSET(opr)

(msk)

? 1 = 0

? (M) • mm = 0

3

Branch if Bit(s)

Set

DIR

IND,X

IND,Y

12 dd mm rr

1E ff mm rr

6

7

8

6

7

8

(rel)

18

BSET (opr)

(msk)

Set Bit(s)

DIR

IND,X

IND,Y

14 dd mm

1C ff mm

—

∆

0

—

M + mm

M

Branch to

Subroutine

Branch if

Overflow Clear

REL

INH

8D rr

28 rr

29 rr

—

∆

—

∆

—

∆

—

∆

BSR (rel)

BVC (rel)

BVS (rel)

CBA

See Figure 3–2

? V = 0

6

3

2

Branch if

Overflow Set

Compare A to

B

? V = 1

11

—

A – B

Clear Carry Bit

INH

0C

0E

—

0

—

0

CLC

CLI

0

C

I

2

Clear Interrupt

Mask

—

Clear Memory

Byte

EXT

IND,X

IND,Y

7F hh ll

6F ff

—

0

1

0

CLR (opr)

0

M

6

7

18

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Table 3-2 Instruction Set (Sheet 3 of 7)

Mnemonic

Operation

Description

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Opcode

S

X

H

I

N

Z

V

C

CLRA

CLRB

CLV

Clear

Accumulator A

Clear

Accumulator B

ClearOverflow

Flag

0

A

B

V

A

B

INH

4F

—

2

—

0

1

0

INH

5F

0A

—

0

—

∆

1

—

∆

0

∆

0

—

∆

CMPA (opr) Compare A to

Memory

A – M

A

IMM

DIR

EXT

IND,X

IND,Y

81 ii

91 dd

B1 hh ll

A1 ff

2

3

4

5

18

A1 ff

CMPB (opr) Compare B to

Memory

B – M

B

IMM

DIR

EXT

IND,X

IND,Y

EXT

IND,X

IND,Y

INH

C1 ii

2

3

4

5

6

7

—

∆

D1 dd

F1 hh ll

E1 ff

73 hh ll

63 ff

18

COM (opr)

COMA

Ones

Complement

Memory Byte

Ones

Complement

A

$FF – M

$FF – A

$FF – B

M

A

B

—

∆

0

∆

1

∆

63 ff

43

A

B

—

2

COMB

Ones

Complement

B

53

—

2

CPD (opr)

Compare D to

Memory 16-Bit

D – M : M + 1

IX – M : M + 1

IY – M : M + 1

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

1A

CD

83 jj kk

93 dd

B3 hh ll

A3 ff

5

6

7

4

5

6

7

5

6

7

A3 ff

CPX (opr)

CPY (opr)

Compare X to

Memory 16-Bit

8C jj kk

9C dd

BC hh ll

AC ff

—

∆

CD

AC ff

Compare Y to

Memory 16-Bit

18

1A

18

8C jj kk

9C dd

BC hh ll

AC ff

DAA

DecimalAdjust Adjust Sum to BCD

A

INH

19

—

2

—

∆

DEC (opr)

Decrement

M – 1

A – 1

B – 1

M

A

B

EXT

IND,X

IND,Y

INH

7A hh ll

6A ff

6

7

—

Memory Byte

18

DECA

DECB

Decrement

Accumulator

A

B

4A

—

2

—

∆

—

Decrement

Accumulator

B

5A

—

2

DES

DEX

Decrement

Stack Pointer

Decrement

Index Register

X

SP – 1

IX – 1

SP

IX

INH

34

09

—

3

—

∆

DEY

Decrement

Index Register

Y

Exclusive OR

A with Memory

IY – 1

IY

A

INH

18

09

—

4

—

∆

—

0

—

EORA (opr)

A

B

M

A

B

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

88 ii

98 dd

B8 hh ll

A8 ff

2

3

4

5

2

3

4

5

∆

18

EORB (opr)

Exclusive OR

B with Memory

M

B

C8 ii

—

∆

0

—

D8 dd

F8 hh ll

E8 ff

FDIV

IDIV

Fractional

Divide 16 by

16

Integer Divide D / IX

16 by 16

D / IX

IX; r

D

INH

03

—

41

—

∆

IX; r

INH

02

—

41

0

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Table 3-2 Instruction Set (Sheet 4 of 7)

Mnemonic

Operation

Description

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Opcode

S

X

H

I

N

Z

V

C

INC (opr)

Increment

Memory Byte

M + 1

A + 1

B + 1

M

A

B

EXT

IND,X

IND,Y

INH

7C hh ll

6C ff

6

7

—

∆

—

18

INCA

INCB

Increment

Accumulator

A

B

4C

—

2

—

∆

—

Increment

Accumulator

B

5C

—

2

INS

INX

Increment

Stack Pointer

Increment

Index Register

X

SP + 1

IX + 1

SP

IX

INH

31

08

—

3

—

∆

INY

Increment

Index Register

Y

IY + 1

IY

INH

18

08

—

4

—

∆

—

JMP (opr)

JSR (opr)

Jump

See Figure 3–2

EXT

IND,X

IND,Y

7E hh ll

6E ff

3

4

—

18

Jump to

Subroutine

DIR

EXT

IND,X

IND,Y

9D dd

BD hh ll

AD ff

5

6

7

AD ff

LDAA (opr)

LDAB (opr)

LDD (opr)

LDS (opr)

LDX (opr)

LDY (opr)

Load

Accumulator

A

M

A

B

A

IMM

DIR

EXT

IND,X

IND,Y

86 ii

2

3

4

5

—

∆

0

—

96 dd

B6 hh ll

A6 ff

18

CD

A6 ff

Load

Accumulator

B

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

C6 ii

2

3

4

5

3

4

5

6

3

4

5

6

3

4

5

6

D6 dd

F6 hh ll

E6 ff

Load Double

Accumulator

D

M

A,M + 1

B

CC jj kk

DC dd

FC hh ll

EC ff

Load Stack

Pointer

M : M + 1

SP

8E jj kk

9E dd

BE hh ll

AE ff

Load Index

Register

X

M : M + 1

IX

IY

CE jj kk

DE dd

FE hh ll

EE ff

Load Index

Register

Y

IMM

DIR

EXT

IND,X

IND,Y

18

1A

18

CE jj kk

DE dd

FE hh ll

EE ff

4

5

6

EE ff

LSL (opr)

LSLA

Logical Shift

Left

EXT

IND,X

IND,Y

78 hh ll

68 ff

6

7

—

∆

0

∆

0

18

b7

b0

C

Logical Shift

Left A

A

B

INH

48

58

05

—

2

3

0

LSLB

Logical Shift

Left B

—

LSLD

Logical Shift

Left Double

0

b7 A b0 b7 B b0

C

LSR (opr)

LSRA

Logical Shift

Right

EXT

IND,X

IND,Y

74 hh ll

64 ff

6

7

0

18

b7

b0

C

Logical Shift

Right A

A

INH

44

—

2

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Table 3-2 Instruction Set (Sheet 5 of 7)

Mnemonic

Operation

Description

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Opcode

S

X

H

I

N

Z

V

C

LSRB

Logical Shift

Right B

B

INH

54

—

2

—

0

∆

0

b7

b0

C

LSRD

Logical Shift

Right Double

INH

04

3

—

0

∆

0

b7 A b0 b7 B b0

C

MUL

Multiply 8 by 8

A

B

D

3D

10

—

∆

NEG (opr)

Two’s

Complement

Memory Byte

Two’s

Complement

A

0 – M

0 – A

0 – B

M

EXT

IND,X

IND,Y

INH

IMM

DIR

EXT

IND,X

IND,Y

70 hh ll

60 ff

40

50

01

8A ii

9A dd

BA hh ll

AA ff

6

7

2

3

4

5

2

3

4

5

∆

18

NEGA

NEGB

A

B

A

B

—

∆

Two’s

Complement

B

NOP

ORAA (opr)

No operation

No Operation

A + M

—

∆

—

∆

—

0

—

OR

Accumulator

A (Inclusive)

A

B

18

ORAB (opr)

OR

Accumulator

B (Inclusive)

B + M

B

IMM

DIR

EXT

IND,X

IND,Y

CA ii

—

∆

0

—

DA dd

FA hh ll

EA ff

PSHA

PSHB

PSHX

Push A onto

Stack

Push B onto

Stack

A

B

Stk,SP = SP – 1

A

INH

36

37

3C

—

3

4

—

B

—

Push X onto IX Stk,SP = SP – 2

Stack (Lo

First)

PSHY

Push Y onto IY Stk,SP = SP – 2

INH

18

3C

—

5

—

Stack (Lo

First)

PULA

PULB

PULX

Pull A from SP = SP + 1, A Stk A

Stack

INH

32

33

38

—

4

5

—

Pull B from SP = SP + 1, B Stk B

Stack

Pull X From

Stack (Hi

First)

SP = SP + 2, IX

Stk

PULY

ROL (opr)

ROLA

Pull Y from

Stack (Hi

First)

SP = SP + 2, IY

Stk

INH

18

38

—

6

—

∆

—

∆

—

∆

—

∆

Rotate Left

Rotate Left A

Rotate Left B

Rotate Right

Rotate Right A

Rotate Right B

EXT

IND,X

IND,Y

79 hh ll

69 ff

6

7

b7

b0

C

A

B

INH

49

—

2

C

ROLB

INH

59

—

2

C

ROR (opr)

RORA

EXT

IND,X

IND,Y

76 hh ll

66 ff

6

7

b7

b0

C

18

A

B

INH

46

—

2

b7

C

RORB

INH

56

—

2

RTI

RTS

SBA

Return from

Interrupt

Return from

Subroutine

Subtract B

from A

See Figure 3–2

INH

3B

39

10

—

12

5

∆

↓

∆

—

∆

—

∆

—

∆

—

∆

See Figure 3–2

—

A – B

A

2

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Table 3-2 Instruction Set (Sheet 6 of 7)

Mnemonic

Operation

Description

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Opcode

82 ii

S

X

H

I

N

Z

V

C

SBCA (opr)

Subtract with

Carry from A

A – M – C

B – M – C

A

B

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

2

3

4

5

—

∆

92 dd

B2 hh ll

A2 ff

18

A2 ff

SBCB (opr)

Subtract with

Carry from B

B

C2 ii

2

3

4

5

—

∆

D2 dd

F2 hh ll

E2 ff

SEC

SEI

Set Carry

Set Interrupt

Mask

1

C

I

INH

0D

0F

—

2

—

1

—

1

—

SEV

Set Overflow

Flag

Store

Accumulator

A

1

V

M

INH

0B

—

2

—

1

0

—

STAA (opr)

A

B

DIR

EXT

IND,X

IND,Y

DIR

EXT

IND,X

IND,Y

97 dd

B7 hh ll

A7 ff

3

4

5

3

4

5

∆

18

A7 ff

STAB (opr)

STD (opr)

Store

Accumulator

B

M

D7 dd

F7 hh ll

E7 ff

—

∆

0

—

E7 ff

Store

Accumulator

D

A

M, B

M + 1

DIR

EXT

IND,X

IND,Y

DD dd

FD hh ll

ED ff

4

5

6

ED ff

STOP

Stop Internal

Clocks

—

INH

CF

—

2

—

0

—

STS (opr)

Store Stack

Pointer

SP

IX

M : M + 1

DIR

EXT

IND,X

IND,Y

DIR

EXT

IND,X

IND,Y

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

9F dd

BF hh ll

AF ff

4

5

6

4

5

6

5

6

2

3

4

5

2

3

4

5

4

5

6

7

∆

18

AF ff

STX (opr)

STY (opr)

SUBA (opr)

Store Index

Register X

DF dd

FF hh ll

EF ff

—

∆

0

∆

—

∆

CD

EF ff

Store Index

Register Y

IY

18

1A

18

DF dd

FF hh ll

EF ff

80 ii

90 dd

B0 hh ll

A0 ff

C0 ii

Subtract

Memory from

A

A – M

A

B

A

18

SUBB (opr)

SUBD (opr)

SWI

Subtract

Memory from

B

B – M

—

1

∆

D0 dd

F0 hh ll

E0 ff

IND,X

IND,Y

IMM

DIR

EXT

E0 ff

Subtract

Memory from

D

D – M : M + 1

D

83 jj kk

93 dd

B3 hh ll

A3 ff

IND,X

IND,Y

A3 ff

Software

Interrupt

See Figure 3–2

INH

3F

—

14

—

TAB

TAP

Transfer A to B

A

B

INH

16

06

—

2

—

∆

0

—

Transfer A to

CC Register

A

CCR

∆

↓

∆

TBA

Transfer B to A

B

A

INH

17

00

—

2

*

—

∆

0

—

TEST

TEST (Only in Address Bus Counts

Test Modes)

—

TPA

Transfer CC

Register to A

Test for Zero

or Minus

CCR

A

INH

07

—

2

—

0

—

0

TST (opr)

M – 0

EXT

IND,X

IND,Y

7D hh ll

6D ff

6

7

∆

18

TSTA

TSTB

Test A for Zero

or Minus

A – 0

B – 0

A

B

INH

4D

—

2

—

∆

0

Test B for Zero

or Minus

INH

5D

—

2

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Table 3-2 Instruction Set (Sheet 7 of 7)

Mnemonic

Operation

Description

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Opcode

S

X

H

I

N

Z

V

C

TSX

TSY

Transfer Stack

Pointer to X

Transfer Stack

Pointer to Y

Transfer X to

Stack Pointer

Transfer Y to

Stack Pointer

Wait for

Interrupt

Exchange D

with X

SP + 1

IX – 1

IY – 1

IX

IY

INH

30

—

3

4

3

4

**

3

4

—

INH

18

30

35

3E

8F

—

TXS

SP

TYS

18

WAI

Stack Regs & WAIT

XGDX

XGDY

IX

IY

D, D

IX

IY

Exchange D

with Y

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SECTION 4

OPERATING MODES AND ON-CHIP MEMORY

This section contains information about the modes that define MC68HC11D3 operat-

ing conditions, and about the on-chip memory that allows the MCU to be configured

for various applications.

4.1 Operating Modes

The values of the mode select inputs MODB and MODA during reset determine the

operating mode. Single chip and expanded multiplexed are the normal modes. With

single-chip mode only on-board memory is available. Expanded multiplexed mode,

however, allows access to external memory. Each of these two normal modes is

paired with a special mode. Bootstrap, a variation of the single-chip mode, is a special

mode that executes a bootloader program in an internal bootstrap ROM. Test is a spe-

cial mode that allows privileged access to internal resources.

4.1.1 Single-Chip Mode

In single-chip mode, ports B and C are available for general-purpose parallel I/O. In

expanded multiplexed mode the MCU can access a 64 Kbyte address space. The total

address space includes the same on-chip memory addresses used for single-chip

mode plus external memory and peripheral devices.

4.1.2 Expanded Multiplexed Mode

Expanded memory access is achieved by providing multiplexed external data and ad-

dress buses on two of the M68HC11 ports; therefore only 18 pins are needed for an

8-bit data bus, a 16-bit address bus and two bus control lines. Port B is designated for

ADDR[15:8], while port C is multiplexed ADDR[7:0]/DATA[7:0]. The address, R/W,

and AS signals are active and valid for all bus cycles including accesses to internal

memory locations. Refer to Figure 4-1, which illustrates a recommended method of

demultiplexing low order addresses from data at port C.

OPERATING MODES AND ON-CHIP MEMORY

TECHNICAL DATA

4-1

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PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

ADDR15

ADDR14

ADDR13

ADDR12

ADDR11

ADDR10

ADDR9

ADDR8

HC373

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

D1

D2

D3

D4

D5

D6

D7

D8

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

LE

OE

AS

R/W

E

WE

OE

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

MCU

ADDR/DATA DEMUX

Figure 4-1 Address/Data Demultiplexing

4.1.3 Special Test Mode

Special test, a variation of the expanded multiplexed mode, is primarily used during

Motorola's internal production testing; however, it is accessible for programming the

CONFIG register, and supporting emulation and debugging during development.

4.1.4 Bootstrap Mode

When the MCU is reset in special bootstrap mode, a small amount of on-chip ROM is

enabled at address $BF00–$BFFF. The ROM contains a bootloader program and a

special set of interrupt and reset vectors. The MCU fetches the reset vector, then ex-

ecutes the bootloader.

For normal use of the bootloader program, send $FF to the SCI receiver at either E

clock ÷16, or E clock ÷104 (1200 baud for E clock equals 2 MHz). Then download up

to 192 bytes of program data, which is put into RAM starting at $0040. These charac-

ters are echoed through the transmitter. When loading is complete, the program jumps

to location $0040 and begins executing the code. The bootloader program ends the

download after 192 bytes, or when the received data line is idle for at least four char-

acter times. Use of an external pullup resistor is required when using the SCI transmit-

ter pin because port D pins are configured for wired-OR operation by the bootloader.

In bootstrap mode, the interrupt vectors are directed to RAM. This allows the use of

interrupts through a jump table. Refer to Freescale application note AN1060,

MC68HC11 Bootstrap Mode.

OPERATING MODES AND ON-CHIP MEMORY

4-2

TECHNICAL DATA

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4.2 Memory Map

The operating mode determines memory mapping and whether memory is addressed

on- or off-chip. Refer to Figure 4-2, which illustrates the memory maps for each of the

four modes of operation. Memory locations for on-chip resources are the same for both

expanded multiplexed and single-chip modes. 192-byte RAM is mapped to $0040 af-

ter reset. It can be placed at any other 4K boundary ($x040) by writing an appropriate

value to the INIT register. The 64-byte register block is mapped to $0000 after reset

and can also be placed at any 4K boundary ($x000) by writing an appropriate value to

the INIT register. Refer to Table 4-1, which details the MCU register and control bit

assignments.

$0000

$0040

0000 64-BYTE REGISTER BLOCK

003F

0040 192 BYTES STATIC RAM

00FF

EXT

$7000

7000

4 KBYTES ROM

7FFF

BFC0

BOOT

ROM

SPECIAL MODES

INTERRUPT

VECTORS

BF00

BFFF

4 KBYTES ROM

FFC0 NORMAL

MODES

$F000

$FFFF

F000

INTERRUPT

VECTORS

FFFF

SINGLE

CHIP

EXPANDED BOOTSTRAP

SPECIAL

TEST

D3 MEM MAP

Figure 4-2 MC68HC11D3 Memory Map

OPERATING MODES AND ON-CHIP MEMORY

TECHNICAL DATA

4-3

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Table 4-1 Register and Control Bit Assignments

Bit 7

PA7

6

5

4

3

2

1

Bit 0

PA0

$0000

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$0023

$0024

$0025

$0026

$0027

$0028

$0029

$002A

PA6

PA5

PA4

PA3

PA2

PA1

PORTA

Reserved

PIOC

CWOM

PC5

PC7

PB7

PC6

PB6

PC4

PB4

PC3

PB3

PC2

PB2

PC1

PB1

PC0

PB0

PORTC

PB5

PORTB

Reserved

DDRB

DDB7

DDC7

PD7

DDB6

DDC6

PD6

DDB5

DDC5

PD5

DDB4

DDC4

PD4

DDB3

DDC3

PD3

DDB2

DDC2

PD2

DDB1

DDC1

PD1

DDB0

DDC0

PD0

DDRC

PORTD

DDD7

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

DDRD

Reserved

CFORC

FOC1

OC1M7

OC1D7

Bit 15

Bit 7

FOC2

FOC3

FOC4

FOC5

0

OC1M6

OC1M5

OC1M4

OC1M3

0

OC1M

OC1D6

OC1D5

OC1D4

OC1D3

0

OC1D

14

6

13

12

11

10

2

9

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

IC3F

PR0

0

TCNT (High)

TCNT (Low)

TIC1 (High)

TIC1 (Low)

TIC2 (High)

TIC2 (Low)

TIC3 (High)

TIC3 (Low)

TOC1(High)

TOC1 (Low)

TOC2 (High)

TOC2 (Low)

TOC3 (High)

TOC3 (Low)

TOC4 (High)

TOC4 (Low)

TFLG1

5

4

3

1

Bit 15

Bit 7

14

13

12

11

10

2

9

6

5

4

3

1

Bit 15

Bit 7

14

13

12

11

10

2

9

6

5

4

3

1

Bit 15

Bit 7

14

13

12

11

10

2

9

6

5

4

12

3

1

Bit 15

Bit 7

14

13

11

10

2

9

6

5

4

3

1

Bit 15

Bit 7

14

13

12

11

10

2

9

6

5

4

3

1

Bit 15

Bit 7

14

13

12

11

10

2

9

6

5

13

4

3

1

Bit 15

Bit 7

14

12

11

10

2

9

1

6

5

4

3

OC1F

TOI

OC2F

RTII

RTIF

PAEN

6

OC3F

PAOVI

PAOVF

PAMOD

5

OC4F

PAII

PAIF

PEDGE

4

I4/O5F

IC1F

0

IC2F

PR1

0

TMSK2

TOF

0

TFLG2

DDRA7

Bit 7

DDRA3

I4/O5

2

RTR1

1

RTR0

Bit 0

SPR0

0

PACTL

3

PACNT

SPIE

SPIF

Bit 7

SPE

WCOL

6

DWOM

0

MSTR

MODF

4

CPOL

CPHA

0

SPR1

0

SPCR

0

3

SPSR

5

2

1

Bit 0

SPDR

OPERATING MODES AND ON-CHIP MEMORY

4-4

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Table 4-1 Register and Control Bit Assignments (Continued)

Bit 7

TCLR

R8

6

0

5

4

3

2

SCR2

0

1

Bit 0

SCR0

0

$002B

$002C

$002D

$002E

$002F

$0030

to

SCP1

0

SCP0

M

RCKB

WAKE

TE

SCR1

0

BAUD

SCCR1

SCCR2

SCSR

T8

TIE

TCIE

TC

RIE

ILIE

RE

RWU

FE

SBK

0

TDRE

R7/T7

RDRF

R5/T5

IDLE

R4/T4

OR

NF

R6/T6

R3/T3

R2/T2

R1/T1

R0/T0

SCDR

Reserved

$0038

$0039

$003A

$003B

$003C

$003D

$003E

$003F

Reserved

OPTION

COPRST

Reserved

HPRIO

0

6

IRQE

5

DLY

4

CME

3

0

2

CR1

1

CR0

Bit 0

Bit 7

RBOOT

RAM3

TILOP

0

SMOD

MDA

RAM1

OCCR

0

IRVNE

RAM0

CBYP

0

PSEL3

REG3

DISR

0

PSEL2

REG2

FCM

PSEL1

REG1

FCOP

PSEL0

RAM2

REG0

INIT

0

TEST1

NOCOP ROMON

CONFIG

The bootloader program is contained in the 192-byte bootstrap ROM. This ROM,

which appears as internal memory space at locations $BF40–$BFFF, is enabled only

if the MCU is reset in special bootstrap mode.

Memory locations are the same for expanded multiplexed and single-chip modes, ex-

cept for ROM in expanded mode and the bootloader ROM in special bootstrap mode.

The on-board 192-byte RAM is initially located at $0040 after reset, but can be placed

at any other 4K boundary ($x040) by writing an appropriate value to the INIT register.

The 4 Kbyte ROM is located at $F000 through $FFFF in all modes except expanded

multiplexed, in which it is located at $7000. ROM can be located at $F000 in expanded

multiplexed by entering single-chip mode out of reset and setting the MDA bit in the

HPRIO register to 1, thereby entering expanded mode from internal ROM. Disable

ROM by clearing the ROMON bit in the CONFIG register.

Hardware priority is built into RAM and I/O remapping. Registers and RAM have prior-

ity over ROM. In the event of conflicts, the higher priority resource takes precedence.

The 192 bytes of fully static RAM store instructions, variables, and temporary data.

The direct addressing mode can access RAM locations using a one-byte address op-

erand, saving program memory space and execution time, depending on the applica-

tion. RAM contents are preserved during periods of processor inactivity by two

methods, both of which reduce power consumption.

In the software-based STOP mode, the clocks are stopped while V

powers the

DD

MCU. Because power supply current is directly related to operating frequency in

CMOS integrated circuits, only a very small amount of leakage exists when the clocks

are stopped.

OPERATING MODES AND ON-CHIP MEMORY

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In the second method, the MODB/V

pin can supply RAM power from a battery

STBY

backup or from a second power supply, as shown in Figure 4-3. Using the MODB/

V

pin may require external hardware, but can be justified when a significant

STBY

amount of external circuitry is operating from V . If V

is used to maintain RAM

DD

STBY

contents, reset must be held low whenever V is below normal operating level. Refer

DD

to SECTION 5 RESETS AND INTERRUPTS.

V

DD

MAX

690

V

DD

4.7k

TO MODB/V

STBY

OF M68HC11

V

OUT

BATT

4.8 V

NiCd

+

MODB/VSTBY CONN

Figure 4-3 RAM Standby MODB/V

Connections

STBY

4.2.1 Priority and Mode Select Register

The four operating modes are selected with the logic states of the mode A (MODA)

and mode B (MODB) pins during reset. The MODA and MODB logic levels determine

the logic state of the special mode (SMOD) and mode A (MDA) control bits in the

HPRIO register.

After reset is released, the mode select pins no longer influence the MCU operating

mode. For single-chip mode, the MODA pin is connected to a logic zero. For expanded

mode, MODA is normally connected to V

through a pull-up resistor of 4.7 kΩ. The

DD

MODA pin also functions as the load instruction register (LIR) pin when the MCU is not

in reset. The open drain active low LIR output pin drives low during the first E cycle of

each instruction. The MODB pin also functions as standby power input, V

which

STBY,

maintains RAM contents in the absence of V . Refer to Table 4-2 for information

DD

about hardware mode selection.

Table 4-2 Hardware Mode Select Summary

Inputs

Mode

Latched at Reset

MODB

MODA

RBOOT SMOD

MDA

1

0

1

0

1

Single-Chip

Expanded Multiplexed

Special Bootstrap

Special Test

0

1

0

1

0

1

0

1

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HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous

$003C

Bit 0

Bit 7

RBOOT

—

6

SMOD

—

5

4

IRVNE

—

3

PSEL3

0

2

PSEL2

1

PSEL1

0

MDA

—

PSEL0

1

RESET:

The values of the RBOOT, SMOD, IRVNE, and MDA at reset depend on the mode dur-

ing initialization. Refer to Table 4-2.

RBOOT — Read Bootstrap ROM

Has meaning only when the SMOD bit is a one (special bootstrap mode or special test

mode). At all other times this bit is clear and cannot be written.

0 = Bootloader ROM disabled and not in map

1 = Bootloader ROM enabled and located in map at $BF40–$BFFF

SMOD — Special Mode Select

This bit reflects the inverse of the MODB input pin at the rising edge of reset. It is set

if the MODB input pin is low during reset. If MODB is high during reset, it is cleared.

SMOD can be cleared under software control from the special modes, thus changing

the operating mode of the MCU. SMOD can never be set by software.

0 = Normal mode variation in effect

1 = Special mode variation in effect

MDA — Mode Select A

The mode select A bit reflects the status of the MODA input pin at the rising edge of

reset. While the SMOD bit is set (special bootstrap or special test mode in effect), the

MDA bit can be written, thus changing the operating mode of the MCU. When the

SMOD bit is clear, the MODA bit is read-only and the operating mode cannot be

changed without going through a reset sequence.

0 = Normal single-chip or special bootstrap mode in effect

1 = Normal expanded or special test mode in effect

IRVNE — Internal Read Visibility/Not E

The IRVNE control bit allows internal read accesses to be available on the external

data bus during factory testing or emulation. If this capability is used for other purpos-

es, bus conflicts can occur because the bidirectional data bus is driven out during a

read of internal addresses, even though the R/W line suggests a high impedance

read mode.

0 = No internal read visibility on external bus

1 = Internal read data driven out data bus

In single-chip modes, this bit determines whether the E clock drives out of the chip.

0 = E driven out

1 = E pin driven low

OPERATING MODES AND ON-CHIP MEMORY

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Mode

IRVNE Out

of Reset

E Clock Out

of Reset

IRV Out of

Reset

IRVNE

Affects Only

Single-Chip

Expanded

Boot

0

1

On

Off

On

E

IRV

E

Special Test

IRV

PSEL[3:0] — Priority Select Bits

Refer to SECTION 5 RESETS AND INTERRUPTS.

4.2.2 System Initialization

Registers and bits that control initialization and the basic configuration of the MCU are

protected against writes except under special circumstances. The protection mecha-

nism, overridden in special operating modes, permits writing these bits only within the

first 64 bus cycles after any reset, and then only once after each reset. If the MCU is

going to be changed to a normal mode after being reset in a special mode, write to the

protected registers before writing the SMOD control bit to zero.

4.2.2.1 CONFIG Register

The CONFIG register consists of static latches that control the startup configuration of

the MCU. CONFIG is writable only once in expanded and single-chip modes (SMOD

= 0). In these modes, the COP watchdog timer is enabled out of reset.

CONFIG — System Configuration

$003F

Bit 7

6

0

5

0

4

0

3

0

2

NOCOP

—

1

ROMON

—

Bit 0

0

RESET:

Bits [7:3] and 0 — Not implemented

Always read zero

NOCOP — COP System Disable

This bit is cleared out of reset in normal modes (COP enabled). Refer to SECTION 5

RESETS AND INTERRUPTS.

0 = COP system enabled

1 = COP system disabled

ROMON — ROM Enable

In all modes, ROMON is forced to one out of reset. Writable once in normal modes and

writable at any time in special modes.

0 = ROM removed from the memory map

1 = ROM present in the memory map

OPERATING MODES AND ON-CHIP MEMORY

4-8

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NOTE

In expanded mode, ROM is located at $7000–$7FFF out of reset. In

all other modes, ROM is located at $F000–$FFFF.

4.2.2.2 INIT Register

The internal registers used to control the operation of the MCU can be relocated on 4K

boundaries within the memory space with the use of INIT. This 8-bit special-purpose

register can change the default locations of the RAM and control registers within the

MCU memory map. It can be written to only once within the first 64 E-clock cycles after

a reset, and then it becomes a read-only register.

INIT — RAM and I/O Mapping Register

$003D

Bit 0

Bit 7

RAM3

0

6

RAM2

0

5

RAM1

0

4

RAM0

0

3

REG3

0

2

REG2

0

1

REG1

0

REG0

1

RESET:

RAM[3:0] — RAM Map Position

These four bits, which specify the upper hexadecimal digit of the RAM address, control

position of RAM in the memory map. RAM can be positioned at the beginning of any

4K page in the memory map. It is initialized to address $0040 out of reset. Refer to

Table 4-3.

REG[3:0] — 64-Byte Register Block Position

These four bits specify the upper hexadecimal digit of the address for the 64-byte block

of internal registers. The register block, positioned at the beginning of any 4K page in

the memory map, is initialized to address $0000 out of reset. Refer to Table 4-4.

Table 4-3 RAM Mapping

Table 4-4 Register Mapping

RAM[3:0]

Address

REG[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Address

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

$0040–$00FF

$1040–$10FF

$2040–$20FF

$3040–$30FF

$4040–$40FF

$5040–$50FF

$6040–$60FF

$7040–$70FF

$8040–$80FF

$9040–$90FF

$A040–$A0FF

$B040–$B0FF

$C040–$C0FF

$D040–$D0FF

$E040–$E0FF

$F040–$F0FF

$0000–$003F

$1000–$103F

$2000–$203F

$3000–$303F

$4000–$403F

$5000–$503F

$6000–$603F

$7000–$703F

$8000–$803F

$9000–$903F

$A000–$A03F

$B000–$B03F

$C000–$C03F

$D000–$D03F

$E000–$E03F

$F000–$F03F

OPERATING MODES AND ON-CHIP MEMORY

TECHNICAL DATA

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4.2.2.3 OPTION Register

The 8-bit special-purpose OPTION register sets internal system configuration options

during initialization. The time protected control bits, IRQE, DLY, and CR[1:0] can be

written to only once after a reset and then they become read-only. This minimizes the

possibility of any accidental changes to the system configuration.

OPTION — System Configuration Options

$0039

Bit 0

CR0*

0

Bit 7

6

0

5

IRQE*

0

4

DLY*

1

3

CME

0

2

0

1

CR1*

0

RESET:

*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes

Bits [7:6] and 2 — Not implemented

Always read zero

IRQE — IRQ Select Edge Sensitive only

0 = IRQ is configured for level sensitive operation

1 = IRQ is configured for edge sensitive only operation

DLY — Enable Oscillator Startup Delay

0 = The oscillator startup delay coming out of STOP is bypassed and the MCU re-

sumes processing within about four bus cycles.

1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started

up from the STOP power-saving mode. This delay allows the crystal oscillator

to stabilize.

CME — Clock Monitor Enable

Refer to SECTION 5 RESETS AND INTERRUPTS.

CR[1:0] — COP Timer Rate Select Bits

The internal E clock is first divided by 2¹⁵before it enters the COP watchdog system.

These control bits determine a scaling factor for the watchdog timer. Refer to SEC-

TION 5 RESETS AND INTERRUPTS.

OPERATING MODES AND ON-CHIP MEMORY

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SECTION 5

RESETS AND INTERRUPTS

Resets and interrupt operations load the program counter with a vector that points to

a new location from which instructions are to be fetched. A reset immediately stops

execution of the current instruction and forces the program counter to a known starting

address. Internal registers and control bits are initialized so the MCU can resume ex-

ecuting instructions. An interrupt temporarily suspends normal program execution

while an interrupt service routine is being executed. After an interrupt has been ser-

viced, the main program resumes as if there had been no interruption.

5.1 Resets

There are four possible sources of reset. Power-on reset (POR) and external reset

share the normal reset vector. The computer operating properly (COP) system and the

clock monitor each has its own vector.

5.1.1 Power-On Reset

A positive transition on V

generates a power-on reset (POR), which is used only for

DD

power-up conditions. POR cannot be used to detect drops in power supply voltages.

A 4064 t (internal clock cycle) delay after the oscillator becomes active allows the

CYC

clock generator to stabilize. If RESET is at logical zero at the end of 4064 t

CPU remains in the reset condition until goes to logical one.

, the

CYC

It is important to protect the MCU during power transitions. Most M68HC11 systems

need an external circuit that holds the RESET pin low whenever V is below the min-

DD

imum operating level. This external voltage level detector, or other external reset cir-

cuits, are the usual source of reset in a system. The POR circuit only initializes internal

circuitry during cold starts. Refer to Figure 2-3.

5.1.2 External Reset (RESET)

The CPU distinguishes between internal and external reset conditions by sensing

whether the reset pin rises to a logic one in less than two E-clock cycles after an inter-

nal device releases reset. When a reset condition is sensed, the RESET pin is driven

low by an internal device for four E-clock cycles, then released. Two E-clock cycles

later it is sampled. If the pin is still held low, the CPU assumes that an external reset

has occurred. If the pin is high, it indicates that the reset was initiated internally by ei-

ther the COP system or the clock monitor. It is not advisable to connect an external

resistor capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices be-

cause the circuit charge time constant can cause the device to misinterpret the type of

reset that occurred.

5.1.3 COP Reset

The MCU includes a COP system to help protect against software failures. When the

RESETS AND INTERRUPTS

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COP is enabled, the software is responsible for keeping a free-running watchdog timer

from timing out. When the software is no longer being executed in the intended se-

quence, a system reset is initiated.

The state of the NOCOP bit in the CONFIG register determines whether the COP sys-

tem is enabled or disabled. In normal modes, COP is enabled out of reset and does

not depend on software action. To disable the COP system, set the NOCOP bit in the

CONFIG register. In the special test and bootstrap operating modes, the COP system

is initially inhibited by the disable resets (DISR) control bit in the TEST1 register. The

DISR bit can subsequently be written to zero to enable COP resets.

The COP timer rate control bits CR[1:0] in the OPTION register determine the COP

time-out period. The system E clock is divided by 2¹⁵and then further scaled by a fac-

tor shown in Table 5-1. After reset, these bits are zero, which selects the fastest time-

out period. In normal operating modes, these bits can only be written once within 64

bus cycles after reset.

Table 5-1 COP Time-out

Divide

E/2¹⁵

By

XTAL = 4.0 MHz

Time-out

–0/+32.8 ms

XTAL = 8.0 MHz

Time-out

–0/+16.4 ms

XTAL = 12.0 MHz

Time-out

CR[1:0]

–0/+10.9 ms

0 0

0 1

1 0

1 1

1

4

32.768 ms

131.072 ms

524.288 ms

2.097 sec

1.0 MHz

16.384 ms

65.536 ms

262.140 ms

1.049 sec

2.0 MHz

10.923 ms

43.691 ms

174.76 ms

699.05 ms

3.0 MHz

16

64

E =

COPRST — Am/Reset COP Timer Circuitry

$003A

Bit 7

6

0

5

0

4

0

3

0

2

0

1

0

Bit 0

7

0

RESET:

Complete the following reset sequence to service the COP timer. Write $55 to CO-

PRST to arm the COP timer clearing mechanism. Then write $AA to COPRST to clear

the COP timer. Performing instructions between these two steps is possible as long as

both steps are completed in the correct sequence before the timer times out.

5.1.4 Clock Monitor Reset

The clock monitor circuit is based on an internal RC time delay. If no MCU clock edges

are detected within this RC time delay, the clock monitor can optionally generate a sys-

tem reset. The clock monitor function is enabled or disabled by the CME control bit in

the OPTION register. The presence of a time-out is determined by the RC delay, which

allows the clock monitor to operate without any MCU clocks.

Clock monitor is used as a backup for the COP system. Because the COP needs a

clock to function, it is disabled when the clocks stop. Therefore, the clock monitor sys-

tem can detect clock failures not detected by the COP system.

RESETS AND INTERRUPTS

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Semiconductor wafer processing causes variations of the RC time-out values between

individual devices. An E-clock frequency below 10 kHz is detected as a clock monitor

error. An E-clock frequency of 200 kHz or more prevents clock monitor errors. Using

the clock monitor function when the E clock is below 200 kHz is not recommended.

Special considerations are needed when a STOP instruction is executed and the clock

monitor is enabled. Because the STOP function causes the clocks to be halted, the

clock monitor function generates a reset sequence if it is enabled at the time the STOP

mode was initiated. Before executing a STOP instruction, clear the CME bit in the OP-

TION register to zero to disable the clock monitor. After recovery from STOP, set the

CME bit to logic one to enable the clock monitor.

5.1.5 Option Register

OPTION — System Configuration Options

$0039

Bit 7

6

0

5

IRQE*

0

4

DLY*

1

3

CME

0

2

0

1

CR1*

0

Bit 0

CR0*

0

RESET:

*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.

Bits [7:6] and 2 — Not implemented

Always read zero

IRQE — Configure IRQ for Edge Sensitive Only Operation

This bit can be written only once during the first 64 E-clock cycles after reset in normal

modes.

0 = Low level recognition

1 = Falling edge recognition

DLY — Enable Oscillator Startup Delay

This bit is set during reset and can be written only once during the first 64 E-clock cy-

cles after reset in normal modes. If an external clock source rather than a crystal is

used, the stabilization delay can be inhibited because the clock source is assumed to

be stable.

0 = No stabilization delay on exit from STOP

1 = Stabilization delay enabled on exit from STOP

CME — Clock Monitor Enable

This control bit can be read or written at any time and controls whether or not the in-

ternal clock monitor circuit triggers a reset sequence when the system clock is slow or

absent. When it is clear, the clock monitor circuit is disabled. When it is set, the clock

monitor circuit is enabled. Reset clears the CME bit.

CR[1:0] — COP Timer Rate Select

These control bits determine a scaling factor for the watchdog timer.

RESETS AND INTERRUPTS

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5.1.6 CONFIG Register

CONFIG — Configuration Control Register

$003F

Bit 7

6

0

5

0

4

0

3

0

2

NOCOP

—

1

ROMON

—

Bit 0

0

RESET:

Bits [7:4] and 0 — Not implemented

Always read zero

NOCOP — COP System Disable

This bit is cleared out of reset in normal modes, enabling the COP system. It is set out

of reset in special modes. NOCOP is writable once in normal modes and at any time

in special modes.

0 = The COP system is enabled as the MCU comes out of reset.

1 = The COP system is disabled and does not generate system resets.

ROMON — Enable On-Chip ROM

Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY.

5.2 Effects of Reset

When a reset condition is recognized, the internal registers and control bits are forced

to an initial state. Depending on the cause of the reset and the operating mode, the

reset vector can be fetched from any of six possible locations. Refer to Table 5-2.

Table 5-2 Reset Cause, Reset Vector, and Operating Mode

Cause of Reset

POR or RESET Pin

Normal Mode Vector

$FFFE, FFFF

Special Test or Bootstrap

$BFFE, BFFF

Clock Monitor Failure

$FFFC, FFFD

$BFFC, $BFFD

COP Watchdog Time-out

$FFFA, FFFB

$BFFA, BFFB

These initial states then control on-chip peripheral systems to force them to known

startup states, as follows:

5.2.1 CPU

After reset, the CPU fetches the restart vector from the appropriate address during the

first three cycles, and begins executing instructions. The stack pointer and other CPU

registers are indeterminate immediately after reset; however, the X and I interrupt

mask bits in the condition code register (CCR) are set to mask any interrupt requests.

Also, the S bit in the CCR is set to inhibit the STOP mode.

5.2.2 Memory Map

After reset, the INIT register is initialized to $00, putting the 192 bytes of RAM at loca-

tions $0040 through $00FF, and the control registers at locations $0000 through

$003F.

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5.2.3 Parallel I/O

When a reset occurs in expanded multiplexed operating modes, the pins used for par-

allel I/O are dedicated to the expansion bus. In single-chip and bootstrap modes, all

ports are parallel I/O data ports. In expanded multiplexed and test modes, ports B, C,

and lines DATA6/AS and DATA7/R/W are a memory expansion bus with port B as a

high-order address bus, port C as a multiplexed address and data bus, AS as the de-

multiplexing signal, and R/as the data bus direction control. The CWOM bit in PIOC is

cleared so that port C is not in wired-OR mode. Port A, bits [0:3] and 7; and ports B,

C, and D are general-purpose I/O at reset and set for input. For this reason the pins

are configured as high impedance upon reset. Port A bits [4:6] are outputs, so high im-

pedance protection is not necessary.

NOTE

Do not confuse pin function with the electrical state of the pin at reset.

All general-purpose I/O pins configured as inputs at reset are in a

high impedance state. Port data registers reflect the port's functional

state at reset. The pin function is mode dependent.

5.2.4 Timer

During reset, the timing system is initialized to a count of $0000. The prescaler bits are

cleared, and all output compare registers are initialized to $FFFF. All input capture reg-

isters are indeterminate after reset. The output compare 1 mask (OC1M) register is

cleared so that successful OC1 compares do not affect any I/O pins. The other four

output compares are configured so that they do not affect any I/O pins on successful

compares. All input capture edge-detector circuits are configured for capture disabled

operation. The timer overflow interrupt flag and all eight timer function interrupt flags

are cleared. All nine timer interrupts are disabled because their mask bits have been

cleared.

The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as OC5;

however, the OM5:OL5 control bits in the TCTL1 register are clear so OC5 does not

control the PA3 pin.

5.2.5 Real-Time Interrupt

The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are

masked. The rate control bits are cleared after reset and can be initialized by software

before the real-time interrupt (RTI) system is used. After reset, a full RTI period elaps-

es before the first RTI interrupt.

5.2.6 Pulse Accumulator

The pulse accumulator system is disabled at reset so that the PAI input pin defaults to

being a general-purpose input pin (PA7).

RESETS AND INTERRUPTS

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5.2.7 COP

The COP watchdog system is enabled if the NOCOP control bit in the CONFIG regis-

ter is clear, and disabled if NOCOP is set. The COP rate is set for the shortest duration

time-out.

5.2.8 SCI

The reset condition of the SCI system is independent of the operating mode. At reset,

the SCI baud rate is indeterminate and must be established by a software write to the

BAUD register. All transmit and receive interrupts are masked and both the transmitter

and receiver are disabled so the port pins default to being general-purpose I/O lines.

The SCI frame format is initialized to an 8-bit character size. The send break and re-

ceiver wake-up functions are disabled. The TDRE and TC status bits in the SCI status

register are both set, indicating that there is no transmit data in either the transmit data

register or the transmit serial shift register. The RDRF, IDLE, OR, NF, and FE receive-

related status bits are cleared.

5.2.9 SPI

The SPI system is disabled by reset. The port pins associated with this function default

to being general-purpose I/O lines.

5.2.10 System

The memory system is configured for normal read operation. PSEL[3:0] are initialized

with the value $0101, causing the external IRQ pin to have the highest I-bit interrupt

priority. The IRQ pin is configured for level sensitive operation (for wired-OR systems).

The RBOOT, SMOD, and MDA bits in the HPRIO register reflect the status of the

MODB and MODA inputs at the rising edge of reset. The DLY control bit in OPTION is

set to specify that an oscillator start-up delay is imposed upon recovery from STOP.

The clock monitor system is disabled by CME equals zero.

5.3 Reset and Interrupt Priority

Resets and interrupts have a hardware priority that determines which reset or interrupt

is serviced first when simultaneous requests occur. Any maskable interrupt can be giv-

en priority over other maskable interrupts.

The first six interrupt sources are not maskable. The priority arrangement for these

sources is as follows:

1. POR or RESET pin

2. Clock monitor reset

3. COP watchdog reset

4. XIRQ interrupt

5. Illegal opcode interrupt

6. Software interrupt (SWI)

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The maskable interrupt sources have the following priority arrangement:

1. IRQ

2. Real-time interrupt

3. Timer input capture 1

4. Timer input capture 2

5. Timer input capture 3

6. Timer output compare 1

7. Timer output compare 2

8. Timer output compare 3

9. Timer output compare 4

10. Timer input capture 4/output compare 5

11. Timer overflow

12. Pulse accumulator overflow

13. Pulse accumulator input edge

14. SPI transfer complete

15. SCI system

Any one of these interrupts can be assigned the highest maskable interrupt priority by

writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise, the

priority arrangement remains the same. An interrupt that is assigned highest priority is

still subject to global masking by the I bit in the CCR, or by any associated local bits.

Interrupt vectors are not affected by priority assignment. To avoid race conditions,

HPRIO can be written only while I-bit interrupts are inhibited.

5.3.1 Highest Priority Interrupt and Miscellaneous Register

HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous

$003C

Bit 7

RBOOT

—

6

SMOD

—

5

4

IRVNE

—

3

PSEL3

0

2

PSEL2

1

PSEL1

0

Bit 0

PSEL0

1

MDA

—

RESET:

The values of the RBOOT, SMOD, IRVNE, and MDA reset bits depend on the mode

during initialization. Refer to Table 5-3.

RBOOT — Read Bootstrap ROM

Has meaning only when the SMOD bit is a one (special bootstrap mode or special test

mode). At all other times this bit is clear and cannot be written. Refer to SECTION 4

OPERATING MODES AND ON-CHIP MEMORY for more information.

SMOD — Special Mode Select

This bit reflects the inverse of the MODB input pin at the rising edge of reset. Refer to

SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more information.

MDA — Mode Select A

The mode select A bit reflects the status of the MODA input pin at the rising edge of

reset. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more

information.

IRVNE — Internal Read Visibility Enable/Not E

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The IRVNE control bit allows internal read accesses to be available on the external

data bus during factory testing or emulation. Refer to SECTION 4 OPERATING

MODES AND ON-CHIP MEMORY for more information.

PSEL[3:0] — Priority Select Bits

These bits select one interrupt source to be elevated above all other I-bit-related

sources and can be written to only while the I bit in the CCR is set (interrupts disabled).

Table 5-3 Highest Priority Interrupt Selection

PSEL[3:0]

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Interrupt Source Promoted

Timer Overflow

Pulse Accumulator Overflow

Pulse Accumulator Input Edge

SPI Serial Transfer Complete

SCI Serial System

Reserved (Default to IRQ)

IRQ (External Pin)

Real-Time Interrupt

Timer Input Capture 1

Timer Input Capture 2

Timer Input Capture 3

Timer Output Compare 1

Timer Output Compare 2

Timer Output Compare 3

Timer Output Compare 4

Timer Input Capture 4/Output Compare 5

5.4 Interrupts

The MCU has 18 interrupt vectors that support 22 interrupt sources. The 19 maskable

interrupts are generated by on-chip peripheral systems. These interrupts are recog-

nized when the global interrupt mask bit (I) in the condition code register (CCR) is

clear. The three non-maskable interrupt sources are illegal opcode trap, software in-

terrupt, and XIRQ pin. Refer to Table 5-4, which shows the interrupt sources and vec-

tor assignments for each source.

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Table 5-4 Interrupt and Reset Vector Assignments

Vector Address

Interrupt Source

CCR Mask

Local

Mask

FFC0, C1 — FFD4, D5

FFD6, D7

Reserved

—

SCI Serial System

I Bit

• SCI Transmit Complete

• SCI Transmit Data Register Empty

• SCI Idle Line Detect

• SCI Receiver Overrun

• SCI Receive Data Register Full

SPI Serial Transfer Complete

Pulse Accumulator Input Edge

Pulse Accumulator Overflow

Timer Overflow

TCIE

TIE

ILIE

RIE

FFD8, D9

FFDA, DB

FFDC, DD

FFDE, DF

FFE0, E1

FFE2, E3

FFE4, E5

FFE6, E7

FFE8, E9

FFEA, EB

FFEC, ED

FFEE, EF

FFF0, F1

FFF2, F3

FFF4, F5

FFF6, F7

FFF8, F9

FFFA, FB

FFFC, FD

FFFE, FF

I Bit

SPIE

PAII

I Bit

PAOVI

TOI

I Bit

Timer Input Capture 4/Output Compare 5

Timer Output Compare 4

Timer Output Compare 3

Timer Output Compare 2

Timer Output Compare 1

Timer Input Capture 3

Timer Input Capture 2

Timer Input Capture 1

Real Time Interrupt

I Bit

I4/O5I

OC4I

OC3I

OC2I

OC1I

IC3I

I Bit

IC2I

I Bit

IC1I

I Bit

RTII

IRQ (External Pin)

I Bit

None

NOCOP

CME

None

XIRQ Pin

X Bit

None

Software Interrupt

Illegal Opcode Trap

COP Failure

Clock Monitor Fail

RESET

5.4.1 Interrupt Recognition and Register Stacking

An interrupt can be recognized at any time after it is enabled by its local mask, if any,

and by the global mask bit in the CCR. Once an interrupt source is recognized, the

CPU responds at the completion of the instruction being executed. Interrupt latency

varies according to the number of cycles required to complete the current instruction.

When the CPU begins to service an interrupt, the contents of the CPU registers are

pushed onto the stack in the order shown in Table 5-5. After the CCR value is stacked,

the I bit and the X bit, if XIRQ is pending, are set to inhibit further interrupts. The inter-

rupt vector for the highest priority pending source is fetched, and execution continues

at the address specified by the vector. At the end of the interrupt service routine, the

return from interrupt instruction is executed and the saved registers are pulled from the

stack in reverse order so that normal program execution can resume. Refer to SEC-

TION 3 CENTRAL PROCESSING UNIT for further information.

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Table 5-5 Stacking Order on Entry to Interrupts

Memory Location

SP

CPU Registers

PCL

SP – 1

PCH

SP –2

IYL

SP – 3

IYH

SP – 4

IXL

SP – 5

IXH

SP – 6

ACCA

ACCB

CCR

SP – 7

SP – 8

5.4.2 Non-Maskable Interrupt Request XIRQ

Non-maskable interrupts are useful because they can always interrupt CPU opera-

tions. The most common use for such an interrupt is for serious system problems, such

as program runaway or power failure. The XIRQ input is an updated version of the

nonmaskable NMI input of earlier MCUs.

Upon reset, both the X bit and I bits of the CCR are set to inhibit all maskable interrupts

and XIRQ. After minimum system initialization, software can clear the X bit by a TAP

instruction, enabling XIRQ interrupts. Thereafter, software cannot set the X bit. Thus,

an XIRQ interrupt is a nonmaskable interrupt. Because the operation of the I-bit-relat-

ed interrupt structure has no effect on the X bit, the internal XIRQ pin remains non-

masked. In the interrupt priority logic, the XIRQ interrupt has a higher priority than any

source that is maskable by the I bit. All I-bit-related interrupts operate normally with

their own priority relationship.

When an I-bit-related interrupt occurs, the I bit is automatically set by hardware after

stacking the CCR byte. The X bit is not affected. When an X-bit-related interrupt oc-

curs, both the X and I bits are automatically set by hardware after stacking the CCR.

A return from interrupt instruction restores the X and I bits to their pre-interrupt request

state.

5.4.3 Illegal Opcode Trap

Because not all possible opcodes or opcode sequences are defined, the MCU in-

cludes an illegal opcode detection circuit, which generates an interrupt request. When

an illegal opcode is detected and the interrupt is recognized, the current value of the

program counter is stacked. After interrupt service is complete, reinitialize the stack

pointer so repeated execution of illegal opcodes does not cause stack underflow. Left

uninitialized, the illegal opcode vector can point to a memory location that contains an

illegal opcode. This condition causes an infinite loop that causes stack underflow. The

stack grows until the system crashes.

The illegal opcode trap mechanism works for all unimplemented opcodes on all four

opcode map pages. The address stacked as the return address for the illegal opcode

interrupt is the address of the first byte of the illegal opcode. Otherwise, it would be

almost impossible to determine whether the illegal opcode had been one or two bytes.

RESETS AND INTERRUPTS

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The stacked return address can be used as a pointer to the illegal opcode so the illegal

opcode service routine can evaluate the offending opcode.

5.4.4 Software Interrupt

SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhib-

ited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit,

once an SWI interrupt begins, other interrupts are inhibited until SWI is complete, or

until user software clears the I bit in the CCR.

5.4.5 Maskable Interrupts

The maskable interrupt structure of the MCU can be extended to include additional ex-

ternal interrupt sources through the IRQ pin. The default configuration of this pin is a

low-level sensitive wired-OR network. When an event triggers an interrupt, a software

accessible interrupt flag is set. When enabled, this flag causes a constant request for

interrupt service. After the flag is cleared, the service request is released.

5.4.6 Reset and Interrupt Processing

Figure 5-1 and Figure 5-1 illustrate the reset and interrupt process. Figure 5-1 illus-

trates how the CPU begins from a reset and how interrupt detection relates to normal

opcode fetches. Figure 5-1 is an expansion of a block in Figure 5-1 and illustrates in-

terrupt priorities. Figure 5-2 shows the resolution of interrupt sources within the SCI

subsystem.

RESETS AND INTERRUPTS

TECHNICAL DATA

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HIGHEST

PRIORITY

POWER-ON RESET

(POR)

DELAY 4064 E CYCLES

EXTERNAL RESET

CLOCK MONITOR FAIL

(WITH CME = 1)

LOWEST

PRIORITY

COP WATCHDOG

TIMEOUT

(WITH NOCOP = 0)

LOAD PROGRAM COUNTER

WITH CONTENTS OF

$FFFE, $FFFF

LOAD PROGRAM COUNTER

WITH CONTENTS OF

$FFFC, $FFFD

LOAD PROGRAM COUNTER

WITH CONTENTS OF

$FFFA, $FFFB

(VECTOR FETCH)

SET BITS S, I, AND X

RESET MCU

HARDWARE

BEGIN INSTRUCTION

SEQUENCE

1A

BIT X IN

Y

CCR = 1?

N

XIRQ

PIN LOW?

Y

STACK CPU

REGISTERS

N

SET BITS I AND X

FETCH VECTOR

$FFF4, $FFF5

2A

FLOW OUT OF RESET P1

Figure 5-1 Processing Flow out of Reset (1 of 2)

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2A

Y

BIT I IN

CCR = 1?

N

ANY I-BIT

INTERRUPT

PENDING?

Y

STACK CPU

REGISTERS

N

FETCH OPCODE

Y

ILLEGAL

OPCODE?

STACK CPU

REGISTERS

N

SET BIT I IN CCR

WAI

INSTRUCTION?

FETCH VECTOR

$FFF8, $FFF9

Y

STACK CPU

REGISTERS

N

SWI

Y

ANY

INTERRUPT

PENDING?

STACK CPU

REGISTERS

N

INSTRUCTION?

N

SET BIT I IN CCR

Y

FETCH VECTOR

$FFF6, $FFF7

RTI

SET BIT I IN CCR

INSTRUCTION?

RESOLVE INTERRUPT

PRIORITY AND FETCH

VECTOR FOR HIGHEST

PENDING SOURCE

SEE FIGURE 5–2

N

RESTORE CPU

REGISTERS

FROM STACK

EXECUTE THIS

INSTRUCTION

1A

FLOW OUT OF RESET P2

Figure 5-1 Processing Flow out of Reset (2 of 2)

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BEGIN

X BIT

IN CCR

SET ?

YES

XIRQ PIN

LOW ?

SET X BIT IN CCR

FETCH VECTOR

$FFF4, FFF5

NO

HIGHEST

PRIORITY

INTERRUPT

?

FETCH VECTOR

NO

FETCH VECTOR

$FFF2, FFF3

IRQ ?

NO

YES

REAL-TIME

INTERRUPT

?

FETCH VECTOR

$FFF0, FFF1

RTII = 1 ?

NO

FETCH VECTOR

$FFEE, FFEF

TIMER

IC1F ?

IC1I = 1 ?

NO

FETCH VECTOR

$FFEC, FFED

TIMER

IC2F ?

IC2I = 1 ?

NO

YES

FETCH VECTOR

$FFEA, FFEB

TIMER

IC3F ?

IC3I = 1 ?

NO

FETCH VECTOR

$FFE8, FFE9

TIMER

OC1F ?

OC1I = 1 ?

NO

2A

2B

INT PRIORITY RES P1

Figure 5-2 Interrupt Priority Resolution (1 of 2)

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2A

2B

Y

FLAG

FETCH VECTOR

OC2I = 1?

N

OC2F = 1?

$FFE6, $FFE7

N

Y

FLAG

OC3F = 1

FETCH VECTOR

$FFE4, $FFE5

OC3I = 1?

N

FLAG

OC4F = 1?

FETCH VECTOR

$FFE2, $FFE3

OC4I = 1?

N

Y

FLAG

OC5F = 1?

FETCH VECTOR

$FFE0, $FFE1

OC5I = 1?

N

FLAG

TOF = 1?

FETCH VECTOR

$FFDE, $FFDF

TOI = 1?

N

Y

FLAG

PAOVF = 1

FETCH VECTOR

$FFDC, $FFDD

PAOVI = 1?

N

FLAG

PAIF = 1?

FETCH VECTOR

$FFDA, $FFDB

PAII = 1?

N

FLAGS

SPIF = 1? OR

MODF = 1?

Y

FETCH VECTOR

$FFD8, $FFD9

SPIE = 1?

N

SCI

FETCH VECTOR

INTERRUPT?

SEE FIGURE

9–7

$FFD6, $FFD7

FETCH VECTOR

$FFF2, $FFF3

N

END

INT PRI RES P2

Figure 5-2 Interrupt Priority Resolution (2 of 2)

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BEGIN

Y

FLAG

RDRF = 1?

N

Y

OR = 1?

N

RIE = 1?

N

RE = 1?

N

Y

TDRE = 1?

N

TE = 1?

N

TIE = 1?

N

TC = 1?

N

TCIE = 1?

N

Y

IDLE = 1?

RE = 1?

N

ILIE = 1?

N

NO

VALID SCI REQUEST

INT SOURCE RES

Figure 5-3 Interrupt Source Resolution within SCI

5.5 Low-Power Operation

Both STOP and WAIT suspend CPU operation until a reset or interrupt occurs. The

WAIT condition suspends processing and reduces power consumption to an interme-

diate level. The STOP condition turns off all on-chip clocks and reduces power con-

sumption to an absolute minimum while retaining the contents of all 192 bytes of RAM.

5.5.1 WAIT

The WAI opcode places the MCU in the WAIT condition, during which the CPU regis-

ters are stacked and CPU processing is suspended until a qualified interrupt is detect-

ed. The interrupt can be an external IRQ, an XIRQ, or any of the internally generated

interrupts, such as the timer or serial interrupts. The on-chip crystal oscillator remains

active throughout the WAIT standby period.

The reduction of power in the WAIT condition depends on how many internal clock sig-

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nals driving on-chip peripheral functions can be shut down. The CPU is always shut

down during WAIT. While in the wait state, the address/data bus repeatedly runs read

cycles to the address where the CCR contents were stacked. The MPU leaves the wait

state when it senses any interrupt that has not been masked.

The free-running timer system is shut down only if the I bit is set to one and the COP

system is disabled by NOCOP being set to one. Several other systems can also be in

a reduced power consumption state depending on the state of software-controlled

configuration control bits. The SPI system is enabled or disabled by the SPE control

bit. The SCI transmitter is enabled or disabled by the TE bit, and the SCI receiver is

enabled or disabled by the RE bit. Therefore the power consumption in WAIT is de-

pendent on the particular application.

5.5.2 STOP

Executing the STOP instruction while the S bit in the CCR is equal to zero places the

MCU in the STOP condition. If the S bit is not zero, the STOP opcode is treated as a

no-op (NOP). The STOP condition offers minimum power consumption because all

clocks, including the crystal oscillator, are stopped while in this mode. To exit STOP

and resume normal processing, a logic low level must be applied to one of the external

interrupts (IRQ or XIRQ), or to the RESET pin. A pending edge-triggered IRQ can also

bring the CPU out of STOP.

Because all clocks are stopped in this mode, all internal peripheral functions also stop.

The data in the internal RAM is retained as long as V power is maintained. The CPU

DD

state and I/O pin levels are static and are unchanged by STOP. Therefore, when an

interrupt comes to restart the system, the MCU resumes processing as if there were

no interruption. If reset is used to restart the system a normal reset sequence results

where all I/O pins and functions are also restored to their initial states.

To use the IRQ pin as a means of recovering from STOP, the I bit in the CCR must be

clear (IRQ not masked). The XIRQ pin can be used to wake up the MCU from STOP

regardless of the state of the X bit in the CCR, although the recovery sequence de-

pends on the state of the X bit. If X is set to zero (XIRQ not masked), the MCU starts

up, beginning with the stacking sequence leading to normal service of the XIRQ re-

quest. If X is set to one (XIRQ masked or inhibited), then processing continues with

the instruction that immediately follows the STOP instruction, and no XIRQ interrupt

service is requested or pending.

Because the oscillator is stopped in STOP mode, a restart delay may be imposed to

allow oscillator stabilization upon leaving STOP. If the internal oscillator is being used,

this delay is required; however, if a stable external oscillator is being used, the DLY

control bit can be used to bypass this startup delay. The DLY control bit is set by reset

and can be optionally cleared during initialization. If the DLY equal to zero option is

used to avoid startup delay on recovery from STOP, then reset should not be used as

the means of recovering from STOP, as this causes DLY to be set again by reset, im-

posing the restart delay. This same delay also applies to power-on-reset, regardless

of the state of the DLY control bit, but does not apply to a reset while the clocks are

running.

RESETS AND INTERRUPTS

TECHNICAL DATA

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SECTION 6

PARALLEL I/O

The MC68HC11D3 has four 8-bit I/O ports; A, B, C, and D. In single-chip and bootstrap

modes, all ports are parallel I/O data ports. In expanded multiplexed and test modes,

ports B and C, and lines DATA6/AS and DATA7/R/W are a memory expansion bus

with port B as the high order address bus, port C as the multiplexed address and data

bus, AS as the demultiplexing signal, and R/W as the data bus direction control. Refer

to Table 6-1, which is a summary of the ports and their shared functions:

Table 6-1 I/O Ports

Port

Input Pins Output Pins

Bidirectional Pins

Shared Functions

TImer

Port A

Port B

Port C

Port D

3

2

8

—

High Order Address

Low Order Address and Data Bus

SCI, SPI, AS, and R/

6.1 Port A

Port A bits handle the timer functions and can also be used as general-purpose I/O. In

both the normal operating modes, port A can be configured for four timer input capture

(IC) and three timer output compare (OC) functions, or four OC and three IC functions

with either a pulse accumulator input (PAI) or a fifth OC function.

PORTA — Port A Data

$0000

Bit 7

6

5

PA5

0

4

PA4*

0

3

2

1

Bit 0

PA0

HiZ

PA7

HiZ

PA6*

0

PA3

HiZ

PA2

HiZ

PA1

HiZ

RESET:

Alt. Func:

And/or:

PAI

OC2

OC1

OC3

OC1

OC4

OC1

IC4/OC5

OC1

IC1

—

IC2

—

IC3

—

OC1

*This pin is not bonded in the 40-pin version.

6.2 Port B

In single-chip mode, all port B pins are general-purpose I/O (PB[7:0]). In expanded

multiplexed mode, all port B pins act as high-order address bits (ADDR[15:8]).

PORTB — Port B Data

$0004

Bit 7

6

5

4

3

2

1

Bit 0

PB0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

S. Chip

or Boot:

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

RESET:

Reset configures pins as HiZ inputs

Expan.

or Test:

ADDR15

ADDR14

ADDR13 ADDR12 ADDR11 ADDR10

ADDR9

ADDR8

RESET:

Reset configures pins as high-order address outputs

PARALLEL I/O

TECHNICAL DATA

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DDRB — Data Direction Register for Port B

$0006

Bit 7

DDB7

0

6

DDB6

0

5

DDB5

0

4

DDC4

0

3

DDB3

0

2

DDB2

0

1

DDB1

0

Bit 0

DDB0

0

RESET:

DDB[7:0] — Data Direction for Port B

0 = Corresponding port B pin configured for input only

1 = Corresponding port B pin configured as output

6.3 Port C

Port C pins are general-purpose I/O (PC[7:0]) in single-chip mode. In expanded mul-

tiplexed mode, port C pins are configured as multiplexed address/data pins. During the

data cycle, bits [7:0] (PC[7:0]) are bidirectional data pins controlled by the R/W signal.

PORTC — Port C Data

$0003

Bit 7

6

5

4

3

2

1

Bit 0

PC0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

S. Chip

or Boot:

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

RESET:

Reset configures pins as HiZ inputs

Expan.

or Test:

ADDR7/

DATA7

ADDR6/

DATA6

ADDR5/

DATA5

ADDR4/

DATA4

ADDR3/

DATA3

ADDR2/

DATA2

ADDR1/

DATA1

ADDR0/

DATA0

RESET:

Reset configures pins as multiplexed, low-order address/data I/O

DDRC — Data Direction Register for Port C

$0007

Bit 7

DDC7

0

6

DDC6

0

5

DDC5

0

4

DDC4

0

3

DDC3

0

2

DDC2

0

1

DDC1

0

Bit 0

DDC0

0

RESET:

DDC[7:0] — Data Direction for Port C

0 = Input

1 = Output

6.4 Port D

The eight port D bits (PD[7:0]) can be used for general-purpose I/O, for the SCI and

SPI subsystems, or for bus data direction control. Port D can be read at any time. In-

puts return the sensed levels at the pin; outputs return the input level of the port D pin

drivers. If port D is written, the data is stored in an internal latch, and can be driven only

if port D is configured for general-purpose output. This port shares functions with the

on-chip SCI and SPI subsystems, while bits 6 and 7 control the direction of data flow

on the bus in expanded and special test modes.

PARALLEL I/O

6-2

TECHNICAL DATA

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PORTD — Port D Data

$0008

Bit 7

6

5

PD5

0

4

3

PD3

0

2

PD2

0

1

Bit 0

PD0

0

PD7

0

PD6

0

PD4

0

PD1

0

RESET:

Alt. Func.:

R/W

AS

SCK

MOSI

MISO

TxD

RxD

DDRD — Data Direction Register for Port D

$0009

Bit 7

DDD7

0

6

DDD6

0

5

DDD5

0

4

DDD4

0

3

DDD3

0

2

DDD2

0

1

DDD1

0

Bit 0

DDD0

0

RESET:

DDD[7:0] — Data Direction for Port D

When port D is a general-purpose I/O port, the DDRD register controls the direction of

the I/O pins as follows:

0 = Configures the corresponding port D pin for input

1 = Configures the corresponding port D pin for output

In expanded and test modes, bits 6 and 7 are dedicated AS and R/W outputs.

When port D is functioning with the SPI system enabled, bit 5 is dedicated as the slave

select (SS) input. In SPI slave mode, DDD5 has no meaning or effect. In SPI master

mode, DDD5 affects port D bit 5 as follows:

0 = Port D bit 5 is an error-detect input to the SPI.

1 = Port D bit 5 is configured as a general-purpose output line.

If the SPI is enabled and expects port D bits 2, 3, and 4 (MISO, MOSI, and SCK) to be

inputs, then they are inputs, regardless of the state of DDRD bits 2, 3, and 4. If the SPI

expects port D bits 2, 3, and 4 to be outputs, they are outputs only if DDRD bits 2, 3,

and 4 are set.

PACTL — Pulse Accumulator Control

$0026

Bit 7

DDRA7

0

6

PAEN

0

5

PAMOD

0

4

PEDGE

0

3

DDRA3

0

2

I4/O5

0

1

RTR1

0

Bit 0

RTR0

0

RESET:

DDRA7 — Data Direction Control for Port A Bit 7

Refer to SECTION 9 TIMING SYSTEM.

PAEN — Pulse Accumulator System Enable

Refer to SECTION 9 TIMING SYSTEM.

PAMOD — Pulse Accumulator Mode

Refer to SECTION 9 TIMING SYSTEM.

PEDGE — Pulse Accumulator Edge Control

Refer to SECTION 9 TIMING SYSTEM.

DDRA3 — Data Direction for Port A Bit 3

Overridden if an output compare function is configured to control the PA3 pin.

0 = Input only

1 = Output

PARALLEL I/O

TECHNICAL DATA

6-3

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I4/O5 — Configure TI4/O5 register for IC4 or OC5

0 = OC5 function enabled

1 = IC4 function enabled

RTR[1:0] — Real-Time Interrupt (RTI) Rate

Refer to SECTION 9 TIMING SYSTEM.

6.5 Parallel I/O Control Register (PIOC)

PIOC configures and controls handshake I/O functions in MCUs where this function is

available. In the MC68HC11D3, however, only the CWOM bit in the PIOC register is

usable. The CWOM bit is cleared so that port C is not in wired-OR mode.

PIOC— Parallel I/O Control

$0002

Bit 7

6

0

5

CWOM

0

4

0

3

0

2

0

1

0

Bit 0

0

RESET:

CWOM — Port C Wired-OR Mode (affects all eight port C pins)

0 = Port C outputs are normal CMOS outputs

1 = Port C outputs are open-drain outputs

PARALLEL I/O

6-4

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SECTION 7

SERIAL COMMUNICATIONS INTERFACE

The serial communications interface (SCI) is a universal asynchronous receiver trans-

mitter (UART), one of two independent serial I/O subsystems in the MC68HC11D3. It

has a standard nonreturn to zero (NRZ) format (one start, eight or nine data, and one

stop bit). Several baud rates are available. The SCI transmitter and receiver are inde-

pendent, but use the same data format and bit rate.

7.1 Data Format

The serial data format requires the following conditions:

1. An idle line in the high state before transmission or reception of a message

2. A start bit, logic zero, transmitted or received, that indicates the start of each

character

3. Data that is transmitted and received least significant bit (LSB) first

4. A stop bit, logic one, used to indicate the end of a frame (A frame consists of a

start bit, a character of eight or nine data bits, and a stop bit.)

5. A break (defined as the transmission or reception of a logic zero for some mul-

tiple number of frames).

Selection of the word length is controlled by the M bit of SCI control register SCCR1.

7.2 Transmit Operation

The SCI transmitter includes a parallel transmit data register (SCDR) and a serial shift

register. The contents of the serial shift register can only be written through the SCDR.

This double buffered operation allows a character to be shifted out serially while an-

other character is waiting in the SCDR to be transferred into the serial shift register.

The output of the serial shift register is applied to TxD as long as transmission is in

progress or the transmit enable (TE) bit of serial communication control register 2

(SCCR2) is set. The block diagram, Figure 7-1, shows the transmit serial shift register,

and the buffer logic at the top of the figure.

SERIAL COMMUNICATIONS INTERFACE

TECHNICAL DATA

7-1

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TRANSMITTER

BAUD RATE

CLOCK

(WRITE ONLY)

SCDR Tx BUFFER

DDD1

10 (11) - BIT Tx SHIFT REGISTER

PIN BUFFER

AND CONTROL

PD1

TxD

H

(8)

7

6

5

4

3

2

1

0

L

s

R

E

9

E

s

/

L

0

1

8

B

M

F

MA

Z

A

U

8

J

S

B

E

—

x

T

E

F

T

J

R

B

S HI

M

B

A

E

A NS F E

P

R

T

FORCE PIN

DIRECTION (OUT)

TRANSMITTER

CONTROL LOGIC

8

SCCR1 SCI CONTROL 1

SCSRINTERRUPT STATUS

8

TDRE

TIE

TC

TCIE

SCCR2 SCI CONTROL 2

SCI Rx

REQUESTS

SCI INTERRUPT

REQUEST

INTERNAL

DATA BUS

11 SCI TX BLOCK

Figure 7-1 SCI Transmitter Block Diagram

7.3 Receive Operation

During receive operations, the transmit sequence is reversed. The serial shift register

receives data and transfers it to a parallel receive data register (SCDR) as a complete

word. Refer to Figure 7-2. This double buffered operation allows a character to be

shifted in serially while another character is already in the SCDR. An advanced data

SERIAL COMMUNICATIONS INTERFACE

7-2

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recovery scheme distinguishes valid data from noise in the serial data stream. The

data input is selectively sampled to detect receive data, and a majority voting circuit

determines the value and integrity of each bit.

RECEIVER

BAUD RATE

CLOCK

DDD0

T

÷16

P

10 (11) - BIT

O

Rx SHIFT REGISTER

T

PIN BUFFER

AND CONTROL

DATA

RECOVERY

PD0

RxD

(8)

7

6

5

4

3

2

1

0

MSB

ALL ONES

DISABLE

DRIVER

RE

M

WAKEUP

LOGIC

RWU

8

SCSR SCI STATUS 1

SCDR Rx BUFFER

(READ ONLY)

SCCR1 SCI CONTROL 1

8

RDRF

RIE

IDLE

ILIE

OR

RIE

8

SCCR2 SCI CONTROL 2

SCI Tx

REQUESTS

SCI INTERRUPT

REQUEST

INTERNAL

DATA BUS

11 SCI RX BLOCK

Figure 7-2 SCI Receiver Block Diagram

SERIAL COMMUNICATIONS INTERFACE

TECHNICAL DATA

7-3

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7.4 Wake-up Feature

The wake-up feature reduces SCI service overhead in multiple receiver systems. Soft-

ware for each receiver evaluates the first character of each message. The receiver is

placed in wakeup mode by writing a one to the RWU bit in the SCCR2 register. While

RWU is one, all of the receiver-related status flags (RDRF, IDLE, OR, NF, and FE) are

inhibited (cannot become set). Although RWU can be cleared by a software write to

SCCR2, to do so would be unusual. Normally RWU is set by software and is cleared

automatically with hardware. Whenever a new message begins, logic alerts the sleep-

ing receivers to wake up and evaluate the initial character of the new message.

Two methods of wake-up are available: idle line wake-up and address mark wake-up.

During idle line wake-up, a sleeping receiver awakens as soon as the RxD line be-

comes idle. In the address mark wake-up, logic one in the most significant bit (MSB)

of a character wakes up all sleeping receivers.

7.4.1 Idle-Line Wakeup

To use the receiver wake-up method, establish a software addressing scheme to allow

the transmitting devices to direct a message to individual receivers or to groups of re-

ceivers. This addressing scheme can take any form as long as all transmitting and re-

ceiving devices are programmed to understand the same scheme. Because the

addressing information is usually the first frame(s) in a message, receivers that are not

part of the current task do not become burdened with the entire set of addressing

frames. All receivers are awake (RWU = 0) when each message begins. As soon as

a receiver determines that the message is not intended for it, software sets the RWU

bit (RWU = 1), which inhibits further flag setting until the RxD line goes idle at the end

of the message. As soon as an idle line is detected by receiver logic, hardware auto-

matically clears the RWU bit so that the first frame of the next message can be re-

ceived. This type of receiver wakeup requires a minimum of one idle-line frame time

between messages, and no idle time between frames in a message.

7.4.2 Address-Mark Wakeup

The serial characters in this type of wakeup consist of seven (eight if M = 1) information

bits and an MSB, which indicates an address character (when set to one — mark). The

first character of each message is an addressing character (MSB = 1). All receivers in

the system evaluate this character to determine if the remainder of the message is di-

rected toward this particular receiver. As soon as a receiver determines that a mes-

sage is not intended for it, the receiver activates the RWU function by using a software

write to set the RWU bit. Because setting RWU inhibits receiver-related flags, there is

no further software overhead for the rest of this message. When the next message be-

gins, its first character has its MSB set, which automatically clears the RWU bit and

enables normal character reception. The first character whose MSB is set is also the

first character to be received after wakeup because RWU gets cleared before the stop

bit for that frame is serially received. This type of wakeup allows messages to include

gaps of idle time, unlike the idle-line method, but there is a loss of efficiency because

of the extra bit time for each character (address bit) required for all characters.

SERIAL COMMUNICATIONS INTERFACE

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7.5 SCI Error Detection

Three error conditions, SCDR overrun, received bit noise, and framing can occur dur-

ing generation of SCI system interrupts. Three bits (OR, NF, and FE) in the serial com-

munications status register (SCSR) indicate if one of these error conditions exists. The

overrun error (OR) bit is set when the next byte is ready to be transferred from the re-

ceive shift register to the SCDR and the SCDR is already full (RDRF bit is set). When

an overrun error occurs, the data that caused the overrun is lost and the data that was

already in SCDR is not disturbed. The OR is cleared when the SCSR is read (with OR

set), followed by a read of the SCDR.

The noise flag (NF) bit is set if there is noise on any of the received bits, including the

start and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit is cleared

when the SCSR is read (with FE equal to one) followed by a read of the SCDR.

When no stop bit is detected in the received data character, the framing error (FE) bit

is set. FE is set at the same time as the RDRF. If the byte received causes both fram-

ing and overrun errors, the processor only recognizes the overrun error. The framing

error flag inhibits further transfer of data into the SCDR until it is cleared. The FE bit is

cleared when the SCSR is read (with FE equal to one) followed by a read of the SCDR.

7.6 SCI Registers

There are five addressable registers in the SCI.

7.6.1 Serial Communications Data Register (SCDR)

SCDR is a parallel register that performs two functions. It is the receive data register

when it is read, and the transmit data register when it is written. Reads access the re-

ceive data buffer and writes access the transmit data buffer. Receive and transmit are

double buffered.

SCDR — SCI Data Register

$002F

Bit 7

R7/T7

U*

6

R6/T6

U

5

R5/T5

U

4

R4/T4

U

3

R3/T3

U

2

R2/T2

U

1

R1/T1

U

Bit 0

R0/T0

U

RESET:

*U = Unaffected

7.6.2 Serial Communications Control Register 1 (SCCR1)

The SCCR1 register provides the control bits that determine word length and select

the method used for the wake-up feature.

SCCR1 — SCI Control Register 1

$002C

Bit 7

R8

U

6

T8

U

5

0

4

M

0

3

WAKE

0

2

0

1

0

Bit 0

0

RESET:

R8 — Receive Data Bit 8

If M bit is set, R8 stores the ninth bit in the receive data character.

SERIAL COMMUNICATIONS INTERFACE

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T8 — Transmit Data bit 8

If M bit is set, T8 stores ninth bit in transmit data character.

M — Mode (Select Character Format)

0 = Start bit, 8 data bits, 1 stop bit

1 = Start bit, 9 data bits, 1 stop bit

WAKE — Wake-up by Address Mark/Idle

0 = Wake-up by IDLE line recognition

1 = Wake-up by address mark (most significant data bit set)

7.6.3 Serial Communications Control Register 2 (SCCR2)

The SCCR2 register provides the control bits that enable or disable individual SCI

functions.

SCCR2 — SCI Control Register 2

$002D

Bit 7

TIE

0

6

TCIE

0

5

RIE

0

4

ILIE

0

3

TE

0

2

RE

0

1

RWU

0

Bit 0

SBK

0

RESET:

TIE — Transmit Interrupt Enable

0 = TDRE interrupts disabled

1 = SCI interrupt requested when TDRE status flag is set

TCIE — Transmit Complete Interrupt Enable

0 = TC interrupts disabled

1 = SCI interrupt requested when TC status flag is set

RIE — Receiver Interrupt Enable

0 = RDRF and OR interrupts disabled

1 = SCI interrupt requested when RDRF flag or the OR status flag is set

ILIE — Idle Line Interrupt Enable

0 = IDLE interrupts disabled

1 = SCI interrupt requested when IDLE status flag is set

TE — Transmitter Enable

When TE goes from zero to one, one unit of idle character time (logic one) is queued

as a preamble.

0 = Transmitter disabled

1 = Transmitter enabled

RE — Receiver Enable

0 = Receiver disabled

1 = Receiver enabled

RWU — Receiver Wake-Up Control

0 = Normal SCI receiver

1 = Wake-up enabled and receiver interrupts inhibited

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SBK — Send Break

At least one character time of break is queued and sent each time SBK is written to

one. More than one break may be sent if the transmitter is idle at the time the SBK bit

is toggled on and off, as the baud rate clock edge could occur between writing the one

and writing the zero to SBK.

0 = Break generator off

1 = Break codes generated as long as SBK = 1

7.6.4 Serial Communication Status Register (SCSR)

The SCSR provides inputs to the interrupt logic circuits for generation of the SCI sys-

tem interrupt.

SCSR — SCI Status Register

$002E

Bit 7

TDRE

1

6

TC

1

5

RDRF

0

4

IDLE

0

3

OR

0

2

NF

0

1

FE

0

Bit 0

0

RESET:

TDRE — Transmit Data Register Empty Flag

This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with

TDRE set and then writing to SCDR.

0 = SCDR busy

1 = SCDR empty

TC — Transmit Complete Flag

This flag is set when the transmitter is idle (no data, preamble, or break transmission

in progress). Clear the TC flag by reading SCSR with TC set and then writing to SCDR.

0 = Transmitter busy

1 = Transmitter idle

RDRF — Receive Data Register Full Flag

This flag is set if a received character is ready to be read from SCDR. Clear the RDRF

flag by reading SCSR with RDRF set and then reading SCDR.

0 = SCDR empty

1 = SCDR full

IDLE — Idle Line Detected Flag

This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD

line has been active and becomes idle again. The IDLE flag is inhibited when RWU =

1. Clear IDLE by reading SCSR with IDLE set and then reading SCDR.

0 = RxD line is active

1 = RxD line is idle

OR — Overrun Error Flag

OR is set if a new character is received before a previously received character is read

from SCDR. Clear the OR flag by reading SCSR with OR set and then reading SCDR.

0 = No overrun

1 = Overrun detected

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NF — Noise Error Flag

NF is set if majority sample logic detects anything other than a unanimous decision.

Clear NF by reading SCSR with NF set and then reading SCDR.

0 = Unanimous decision

1 = Noise detected

FE — Framing Error

FE is set when a 0 is detected where a stop bit was expected. Clear the FE flag by

reading SCSR with FE set and then reading SCDR.

0 = Stop bit detected

1 = 0 detected

7.6.5 Baud Rate Register (BAUD)

Use this register to select different baud rates for the SCI system. The SCP[1:0] bits

function as a prescaler for the SCR[2:0] bits. Together, these five bits provide multiple

baud rate combinations for a given crystal frequency. Normally, this register is written

once during initialization. The prescaler is set to its fastest rate by default out of reset,

and can be changed at any time. Refer to Table 7-1 and Table 7-2 for normal baud

rate selections.

BAUD — Baud Rate

$002B

Bit 7

6

0

5

SCP1

0

4

SCP0

0

3

RCKB

0

2

SCR2

U

1

SCR1

U

Bit 0

SCR0

U

TCLR

RESET:

0

TCLR — Clear Baud Rate Counters (Test)

RCKB — SCI Baud Rate Clock Check (Test)

SCP1, SCP0 — SCI Baud Rate Prescaler Selects

These two bits select a prescale factor for the SCI baud rate generator that determines

the highest possible baud rate.

Table 7-1 Baud Rate Prescale Selects

SCP[1:0]

Divide

Crystal Frequency in MHz

Internal Clock 4.0 MHz 8.0 MHz 10.0 MHz 12.0 MHz

By

1

(Baud)

62.50 K

20.83 K

(Baud)

0 0

0 1

1 0

1 1

125.0 K 156.25 K 187.5 K

3

41.67 K

52.08 K

38.4 K

62.5 K

46.88 K

14.42 K

4

15.625 K 31.25 K

4800 9600

13

12.02 K

SCR[2:0] — SCI Baud Rate Selects

These three bits select receiver and transmitter bit rate based on output from baud rate

prescaler stage.

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Table 7-2 Baud Rate Selects

SCR[2:0]

Divide

Prescaler

Highest Baud Rate

(Prescaler Output from Previous Table)

By

1

4800

2400

1200

600

300

150

—

9600

4800

2400

1200

600

38.4 K

19.2 K

9600

4800

2400

1200

600

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

2

4

8

16

32

64

128

300

150

—

300

The prescale bits, SCP[1:0], determine the highest baud rate and the SCR[2:0] bits se-

lect an additional binary submultiple (≥1, ≥2, ≥4, through ≥128) of this highest baud

rate. The result of these two dividers in series is the 16 X receiver baud rate clock. The

SCR[2:0] bits are not affected by reset and can be changed at any time, although they

should not be changed when any SCI transfer is in progress.

Figure 7-3 illustrates the SCI baud rate timing chain. The prescale select bits deter-

mine the highest baud rate. The rate select bits determine additional divide by two

stages to arrive at the receiver timing (RT) clock rate. The baud rate clock is the result

of dividing the RT clock by 16.

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EXTAL

XTAL

INTERNAL BUS CLOCK (PH2)

OSCILLATOR

AND

CLOCK GENERATOR

÷3

÷4

÷ 13

(÷4)

SCP[1:0]

1:1

0:0

0:1

1:0

E

AS

SCR[2:0]

0:0:0

÷2

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 16

SCI

TRANSMIT

BAUD RATE

(1X)

SCI

RECEIVE

BAUD RATE

(16X)

SCI BAUD GENERATOR

Figure 7-3 SCI Baud Rate Diagram

7.7 Status Flags and Interrupts

The SCI transmitter has two status flags. These status flags can be read by software

(polled) to tell when the corresponding condition exists. Alternatively, a local interrupt

enable bit can be set to enable each of these status conditions to generate interrupt

requests when the corresponding condition is present. Status flags are automatically

set by hardware logic conditions, but must be cleared by software, which provides an

interlock mechanism that enables logic to know when software has noticed the status

indication. The software clearing sequence for these flags is automatic — functions

that are normally performed in response to the status flags also satisfy the conditions

of the clearing sequence.

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TDRE and TC flags are normally set when the transmitter is first enabled (TE set to

one). The TDRE flag indicates there is room in the transmit queue to store another

data character in the TDR. The TIE bit is the local interrupt mask for TDRE. When TIE

is zero, TDRE must be polled. When TIE and TDRE are one, an interrupt is requested.

The TC flag indicates the transmitter has completed the queue. The TCIE bit is the lo-

cal interrupt mask for TC. When TCIE is zero, TC must be polled; when TCIE is one

and TC is one, an interrupt is requested.

Writing a zero to TE requests that the transmitter stop when it can. The transmitter

completes any transmission in progress before actually shutting down. Only an MCU

reset can cause the transmitter to stop and shut down immediately. If TE is written to

zero when the transmitter is already idle, the pin reverts to its general-purpose I/O

function (synchronized to the bit-rate clock). If anything is being transmitted when TE

is written to zero, that character is completed before the pin reverts to general-purpose

I/O, but any other characters waiting in the transmit queue are lost. The TC and TDRE

flags are set at the completion of this last character, even though TE has been dis-

abled.

The SCI receiver has five status flags, three of which can generate interrupt requests.

The status flags are set by the SCI logic in response to specific conditions in the re-

ceiver. These flags can be read (polled) at any time by software. Refer to Figure 7-4,

which shows SCI interrupt arbitration.

When an overrun takes place, the new character is lost, and the character that was in

its way in the parallel RDR is undisturbed. RDRF is set when a character has been

received and transferred into the parallel RDR. The OR flag is set instead of RDRF if

overrun occurs. A new character is ready to be transferred into RDR before a previous

character is read from RDR.

The NF and FE flags provide additional information about the character in the RDR,

but do not generate interrupt requests.

The last receiver status flag and interrupt source come from the IDLE flag. The RxD

line is idle if it has constantly been at logic one for a full character time. The IDLE flag

is set only after the RxD line has been busy and becomes idle, which prevents repeat-

ed interrupts for the whole time RxD remains idle.

SERIAL COMMUNICATIONS INTERFACE

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BEGIN

Y

FLAG

RDRF = 1?

N

Y

OR = 1?

N

RIE = 1?

N

RE = 1?

N

Y

TDRE = 1?

N

TE = 1?

N

TIE = 1?

N

TC = 1?

N

TCIE = 1?

N

Y

IDLE = 1?

RE = 1?

N

ILIE = 1?

N

NO

VALID SCI REQUEST

INT SOURCE RES

Figure 7-4 Interrupt Source Resolution within SCI

SERIAL COMMUNICATIONS INTERFACE

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SECTION 8

SERIAL PERIPHERAL INTERFACE

The serial peripheral interface (SPI), an independent serial communications sub-

system, allows the MCU to communicate synchronously with peripheral devices, such

as transistor-transistor logic (TTL) shift registers, liquid crystal diode (LCD) display

drivers, analog-to-digital converter subsystems, and other microprocessors. The SPI

is also capable of inter-processor communication in a multiple master system. The SPI

system can be configured as either a master or a slave device with data rates as high

as one half of the E-clock rate when configured as master, and as fast as the E-clock

rate when configured as slave.

8.1 Functional Description

The central element in the SPI system is the block containing the shift register and the

read data buffer. The system is single buffered in the transmit direction and double

buffered in the receive direction. This means that new data for transmission cannot be

written to the shifter until the previous transfer is complete; however, received data is

transferred into a parallel read data buffer so the shifter is free to accept a second se-

rial character. As long as the first character is read out of the read data buffer before

the next serial character is ready to be transferred, no overrun condition occurs. A sin-

gle MCU register address is used for reading data from the read data buffer, and for

writing data to the shifter.

The SPI status block represents the SPI status functions (transfer complete, write col-

lision, and mode fault) performed by the serial peripheral status register (SPSR). The

SPI control block represents those functions that control the SPI system through the

serial peripheral control register (SPCR).

Refer to Figure 8-1, which shows the SPI block diagram.

SERIAL PERIPHERAL INTERFACE

TECHNICAL DATA

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INTERNAL

MCU CLOCK

MISO

PD2

S

M

MSB

LSB

M

S

MOSI

PD3

C

DIVIDER

8/16-BIT SHIFT REGISTER

÷2 ÷4 ÷16 ÷32

O IG

L

READ DATA BUFFER

O

R

T

O

CLOCK

P

SPI CLOCK (MASTER)

S

SELECT

SCK

PD4

CLOCK

LOGIC

M

1

0

R

SS

S

S P

PD5

MSTR

SPE

SPI CONTROL

8

SPI STATUS REGISTER

SPI CONTROL REGISTER

8

SPI INTERRUPT

REQUEST

INTERNAL

DATA BUS

11 SPI BLOCK

Figure 8-1 SPI Block Diagram

8.2 SPI Transfer Formats

During an SPI transfer, data is simultaneously transmitted and received. A serial clock

line synchronizes shifting and sampling of the information on the two serial data lines.

A slave select line allows individual selection of a slave SPI device; slave devices that

are not selected do not interfere with SPI bus activities. On a master SPI device, the

select line can optionally be used to indicate a multiple master bus contention. Refer

to Figure 8-2.

SERIAL PERIPHERAL INTERFACE

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SCK CYCLE #

1

2

3

4

5

6

7

8

SCK (CPOL = 0)

SCK (CPOL = 1)

SAMPLE INPUT

MSB

6

5

4

3

2

1

LSB

(CPHA = 0)

DATA OUT

SAMPLE INPUT

(CPHA = 1) DATA OUT

SS (TO SLAVE)

MSB

6

5

4

3

2

1

LSB

SLAVE CPHA=1 TRANSFER IN PROGRESS

3

MASTER TRANSFER IN PROGRESS

2

4

SLAVE CPHA=0 TRANSFER IN PROGRESS

1

5

1. SS ASSERTED

2. MASTER WRITES TO SPDR

3. FIRST SCK EDGE

4. SPIF SET

5. SS NEGATED

SPI TRANSFER FORMAT 1

Figure 8-2 SPI Transfer Format

8.2.1 Clock Phase and Polarity Controls

Software can select one of four combinations of serial clock phase and polarity using

two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL

control bit, which selects an active high or active low clock, and has no significant ef-

fect on the transfer format. The clock phase (CPHA) control bit selects one of two dif-

ferent transfer formats. The clock phase and polarity should be identical for the master

SPI device and the communicating slave device. In some cases, the phase and polar-

ity are changed between transfers to allow a master device to communicate with pe-

ripheral slaves having different requirements.

When CPHA equals zero, the slave select (SS) line must be negated and reasserted

between each successive serial byte. Also, if the slave writes data to the SPI data reg-

ister (SPDR) while SS is active low, a write collision error results.

When CPHA equals one, the SS line can remain low between successive transfers.

8.3 SPI Signals

The following paragraphs contain descriptions of the four SPI signals: master in slave

out (MISO), master out slave in (MOSI), serial clock (SCK), and SS.

SERIAL PERIPHERAL INTERFACE

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8.3.1 Master In Slave Out

MISO is one of two unidirectional serial data signals. It is an input to a master device

and an output from a slave device. The MISO line of a slave device is placed in the

high impedance state if the slave device is not selected.

8.3.2 Master Out Slave In

The MOSI line is the second of the two unidirectional serial data signals. It is an output

from a master device and an input to a slave device. The master device places data

on the MOSI line a half-cycle before the clock edge that the slave device uses to latch

the data.

8.3.3 Serial Clock

SCK, an input to a slave device, is generated by the master device and synchronizes

data movement in and out of the device through the MOSI and MISO lines. Master and

slave devices are capable of exchanging a byte of information during a sequence of

eight clock cycles.

There are four possible timing relationships that can be chosen by using control bits

CPOL and CPHA in the serial peripheral control register (SPCR). Both master and

slave devices must operate with the same timing. The SPI clock rate select bits,

SPR[1:0], in the SPCR of the master device, select the clock rate. In a slave device,

SPR[1:0] have no effect on the operation of the SPI.

8.3.4 Slave Select

The SS input of a slave device must be externally asserted before a master device can

exchange data with the slave device. must be low before data transactions and must

stay low for the duration of the transaction.

The SS line of the master must be held high. If it goes low, a mode fault error flag

(MODF) is set in the serial peripheral status register (SPSR). To disable the mode fault

circuit, write a one in bit 5 of the port D data direction register. This sets the SS pin to

act as a general-purpose output. The other three lines are dedicated to the SPI when-

ever the serial peripheral interface is on.

The state of the master and slave CPHA bits affects the operation of SS. CPHA set-

tings should be identical for master and slave. When CPHA = 0, the shift clock is the

OR of SS with SCK. In this clock phase mode, SS must go high between successive

characters in an SPI message. When CPHA = 1, SS can be left low between succes-

sive SPI characters. In cases where there is only one SPI slave MCU, its SS line can

be tied to V as long as only CPHA = 1 clock mode is used.

SS

8.4 SPI System Errors

Two system errors can be detected by the SPI system. The first type of error arises in

a multiple-master system when more than one SPI device simultaneously tries to be

a master. This error is called a mode fault. The second type of error, write collision,

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indicates that an attempt was made to write data to the SPDR while a transfer was in

progress.

When the SPI system is configured as a master and the SS input line goes to active

low, a mode fault error has occurred — usually because two devices have attempted

to act as master at the same time. In cases where more than one device is concurrent-

ly configured as a master, there is a chance of contention between two pin drivers. For

push-pull CMOS drivers, this contention can cause permanent damage. The mode

fault attempts to protect the device by disabling the drivers. The MSTR control bit in

the SPCR and all four DDRD control bits associated with the SPI are cleared. An in-

terrupt is generated subject to masking by the SPIE control bit and the I bit in the CCR.

Other precautions may need to be taken to prevent driver damage. If two devices are

made masters at the same time, mode fault does not help protect either one unless

one of them selects the other as slave. The amount of damage possible depends on

the length of time both devices attempt to act as master.

A write collision error occurs if the SPDR is written while a transfer is in progress. Be-

cause the SPDR is not double buffered in the transmit direction, writes to SPDR cause

data to be written directly into the SPI shift register. Because this write corrupts any

transfer in progress, a write collision error is generated. The transfer continues undis-

turbed, and the write data that caused the error is not written to the shifter.

A write collision is normally a slave error because a slave has no control over when a

master initiates a transfer. A master knows when a transfer is in progress, so there is

no reason for a master to generate a write-collision error, although the SPI logic can

detect write collisions in both master and slave devices.

The SPI configuration determines the characteristics of a transfer in progress. For a

master, a transfer begins when data is written to SPDR and ends when SPIF is set.

For a slave with CPHA equal to zero, a transfer starts when SS goes low and ends

when SS returns high. In this case, SPIF is set at the middle of the eighth SCK cycle

when data is transferred from the shifter to the parallel data register, but the transfer

is still in progress until SS goes high. For a slave with CPHA equal to one, transfer be-

gins when the SCK line goes to its active level, which is the edge at the beginning of

the first SCK cycle. The transfer ends in a slave in which CPHA equals one when SPIF

is set. For a slave, after a byte transfer, SCK must be in inactive state for at least 2 E-

clock cycles before the next byte transfer begins.

8.5 SPI Registers

The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and data

storage functions. Refer to the following information for a description of how these reg-

isters are organized.

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8.5.1 Serial Peripheral Control

SPCR — Serial Peripheral Control Register

$0028

Bit 7

SPIE

0

6

SPE

0

5

DWOM

0

4

MSTR

0

3

CPOL

0

2

CPHA

1

SPR1

U

Bit 0

SPR0

U

RESET:

SPIE — Serial Peripheral Interrupt Enable

0 = SPI interrupt disabled

1 = SPI interrupt enabled

SPE — Serial Peripheral System Enable

0 = SPI off

1 = SPI on

DWOM — Port D Wired-OR Mode

DWOM affects all six port D pins.

0 = Normal CMOS outputs

1 = Open-drain outputs

MSTR — Master Mode Select

0 = Slave mode

1 = Master mode

CPOL — Clock Polarity

When the clock polarity bit is cleared and data is not being transferred, the SCK pin of

the master device has a steady state low value. When CPOL is set, SCK idles high.

Refer to Figure 8-2 and 8.2.1 Clock Phase and Polarity Controls.

CPHA — Clock Phase

The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relation-

ship between master and slave. The CPHA bit selects one of two different clocking

protocols. Refer to Figure 8-2 and 8.2.1 Clock Phase and Polarity Controls.

SPR1 and SPR0 — SPI Clock Rate Selects

These two serial peripheral rate bits select one of four baud rates to be used as SCK

if the device is a master; however, they have no effect in the slave mode.

E Clock

Frequency at

SPR[1:0]

0 0

Divide By

E = 2 MHz (Baud)

2

4

1.0 MHz

500 kHz

125 kHz

62.5 kHz

0 1

1 0

16

32

1 1

SERIAL PERIPHERAL INTERFACE

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8.5.2 Serial Peripheral Status

SPSR — Serial Peripheral Status Register

$0029

Bit 7

SPIF

0

6

WCOL

0

5

0

4

MODF

0

3

0

2

0

1

0

Bit 0

0

RESET:

SPIF — SPI Transfer Complete Flag

SPIF is set upon completion of data transfer between the processor and the external

device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated.

To clear the SPIF bit, read the SPSR with SPIF set, then access the SPDR. Unless

SPSR is read (with SPIF set) first, attempts to write SPDR are inhibited.

WCOL — Write Collision

Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) fol-

lowed by an access of SPDR. Refer to 8.3.4 Slave Select and 8.4 SPI System Errors.

0 = No write collision

1 = Write collision

Bit 5 — Not implemented

Always reads zero

MODF — Mode Fault

To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer

to 8.3.4 Slave Select and 8.4 SPI System Errors.

0 = No mode fault

1 = Mode fault

Bits [3:0] — Not implemented

Always read zero

8.5.3 Serial Peripheral Data I/O

The SPDR is used when transmitting or receiving data on the serial bus. Only a write

to this register initiates transmission or reception of a byte, and this only occurs in the

master device. At the completion of transferring a byte of data, the SPIF status bit is

set in both the master and slave devices.

A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss

of the byte that caused the overrun, the first SPIF must be cleared by the time a second

transfer of data from the shift register to the read buffer is initiated.

SPDR — SPI Data Register

$002A

Bit 7

6

5

4

3

2

1

Bit 0

NOTE

SPI is double buffered in and single buffered out.

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SECTION 9

TIMING SYSTEM

The M68HC11 timing system is composed of five clock divider chains. The main clock

divider chain includes a 16-bit free-running counter, which is driven by a programma-

ble prescaler. The main timer's programmable prescaler provides one of the four

clocking rates to drive the 16-bit counter. Two prescaler control bits select the prescale

rate.

The prescaler output divides the system clock by 1, 4, 8, or 16. Taps off of this main

clocking chain drive circuitry that generates the slower clocks used by the pulse accu-

mulator, the real-time interrupt (RTI), and the computer operating properly (COP)

watchdog subsystems, also described in this section. Refer to Figure 9-1.

All main timer system activities are referenced to this free-running counter. The

counter begins incrementing from $0000 as the MCU comes out of reset, and contin-

ues to the maximum count, $FFFF. At the maximum count, the counter rolls over to

$0000, sets an overflow flag, and continues to increment. As long as the MCU is run-

ning in a normal operating mode, there is no way to reset, change, or interrupt the

counting. The capture/compare subsystem features three input capture channels, four

output compare channels, and one channel that can be selected to perform either in-

put capture or output compare. Each of the three input capture functions has its own

16-bit input capture register (time capture latch) and each of the output compare func-

tions has its own 16-bit compare register. All timer functions, including the timer over-

flow and RTI have their own interrupt controls and separate interrupt vectors.

The pulse accumulator contains an 8-bit counter and edge select logic. The pulse ac-

cumulator can operate in either event counting or gated time accumulation modes.

During event counting mode, the pulse accumulator's 8-bit counter increments when

a specified edge is detected on an input signal. During gated time accumulation mode,

an internal clock source increments the 8-bit counter while an input signal has a pre-

determined logic level.

RTI is a programmable periodic interrupt circuit that permits pacing the execution of

software routines by selecting one of four interrupt rates.

The COP watchdog clock input (E÷2¹⁵) is tapped off of the free-running counter chain.

The COP automatically times out unless it is serviced within a specific time by a pro-

gram reset sequence. If the COP is allowed to time out, a reset is generated, which

drives the RESET pin low to reset the MCU and the external system. Refer to Table

9-1 for crystal related frequencies and periods.

TIMING SYSTEM

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OSCILLATOR AND

CLOCK GENERATOR

(DIVIDE BY FOUR)

AS

E CLOCK

INTERNAL BUS CLOCK (PH2)

SPI

PRESCALER

(÷ 2, 4, 16, 32)

SPR[1:0]

PRESCALER

(÷ 1, 2, 4,....128)

SCR[2:0]

PRESCALER

(÷ 1, 3, 4, 13)

SCP[1:0]

SCI RECEIVER CLOCK

SCI TRANSMIT CLOCK

PULSE ACCUMULATOR

÷16

6

E÷2

PRESCALER

(÷ 1, 2, 4, 8)

RTR[1:0]

13

E÷2

REAL-TIME INTERRUPT

÷4

15

E÷2

PRESCALER

(÷ 1, 4, 8, 16)

PR[1:0]

PRESCALER

(÷1, 4, 16, 64)

CR[1:0]

TOF

TCNT

FF1

FF2

Q

S

R

Q

S

R

FORCE

COP

RESET

IC/OC

CLEAR COP

TIMER

SYSTEM

RESET

TIMER DIV CHAIN

Figure 9-1 Timer Clock Divider Chains

TIMING SYSTEM

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Table 9-1 Timer Summary

XTAL Frequencies

4.0 MHz

1.0 MHz

1000 ns

8.0 MHz

2.0 MHz

500 ns

12.0 MHz

3.0 MHz

333 ns

Other Rates

(E)

Control

Bits

(1/E)

PR[1:0]

Main Timer Count Rates

0 0

1 count —

overflow —

1.0 µs

65.536 ms

500 ns

32.768 ms

333 ns

21.845 ms

(E/1)

(E/2¹⁶)

0 1

1 count —

overflow —

4.0 µs

262.14 ms

2.0 µs

131.07 ms

1.333 µs

87.381 ms

(E/4)

(E/2¹⁸)

1 0

1 count —

overflow —

8.0 µs

524.29 ms

4.0 µs

262.14 ms

2.667 µs

174.76 ms

(E/8)

(E/2¹⁹)

1 1

1 count —

overflow —

16.0 µs

1.049 s

8.0 µs

524.29 ms

5.333 µs

349.52 ms

(E/16)

(E/2²⁰)

9.1 Timer Structure

Figure 9-1 shows the capture/compare system block diagram. The port A pin control

block includes logic for timer functions and for general-purpose I/O. For pins PA2,

PA1, and PA0, this block contains both the edge-detection logic and the control logic

that enables the selection of which edge triggers an input capture. The digital level on

PA[2:0] can be read at any time (read PORTA register), even if the pin is being used

for the input capture function. Pins PA[6:4] are used for either general-purpose output,

or as output compare pins. Pin PA3 can be used for general-purpose I/O, input capture

4, output compare 5, or output compare 1. When one of these pins is being used for

an output compare function, it cannot be written directly as if it were a general-purpose

output. Each of the output compare functions (OC5–OC2) is related to one of the port

A output pins. Output compare one (OC1) has extra control logic, allowing it optional

control of any combination of the PA[7:3] pins. The PA7 pin can be used as a general-

purpose I/O pin, as an input to the pulse accumulator, or as an OC1 output pin.

TIMING SYSTEM

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PRESCALER — DIVIDE BY

1, 4, 8, 16

TCNT (HI)

TCNT (LO)

TOI

9

SYSTEM

CLOCK

16-BIT FREE RUNNING

COUNTER

TOF

PR1

PR0

INTERRUPT REQUESTS

16-BIT TIMER BUS

FUNCTIONS

OC1I

OC2I

OC3I

OC4I

I4/O5I

8

16-BIT COMPARATOR =

OC1F

PA7

OC1

TOC1 (HI) TOC1 (LO)

BIT 7

FOC1

FOC2

FOC3

FOC4

FOC5

7

16-BIT COMPARATOR =

OC2F

OC3F

OC4F

PA6

OC2/OC1

BIT 6

TOC2 (HI) TOC2 (LO)

6

16-BIT COMPARATOR =

PA5

OC3/OC1

BIT 5

TOC3 (HI) TOC3 (LO)

5

16-BIT COMPARATOR =

PA4

OC4/OC1

BIT 4

TOC4 (HI) TOC4 (LO)

4

OC5

I4/O5F

IC4

16-BIT COMPARATOR =

TI4/O5(HI) TI4/O5 (LO)

16-BIT LATCH CLK

PA3

IC4/OC5

OC1

BIT 3

IC1I

IC2I

IC3I

I4/O5

3

PA2

IC1

CLK

TIC1 (LO)

BIT 2

16-BIT LATCH

IC1F

IC2F

IC3F

TIC1 (HI)

2

PA1

IC2

CLK

BIT 1

16-BIT LATCH

TIC2 (HI)

TIC2 (LO)

1

PA0

IC3

CLK

BIT 3

16-BIT LATCH

TIC3 (HI)

TIC3 (LO)

TFLG 1

STATUS

FLAGS

CFORC

TMSK 1

FORCE OUTPUT INTERRUPT

ENABLES

PARALLEL PORT

PIN CONTROL

COMPARE

11 CC BLOCK

Figure 9-2 Capture/Compare Block Diagram

9.2 Input Capture

The input capture function records the time an external event occurs by latching the

value of the free-running counter when a selected edge is detected at the associated

timer input pin. Software can store latched values and use them to compute the peri-

odicity and duration of events. For example, by storing the times of successive edges

of an incoming signal, software can determine the period and pulse width of a signal.

To measure period, two successive edges of the same polarity are captured. To mea-

sure pulse width, two alternate polarity edges are captured.

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In most cases, input capture edges are asynchronous to the internal timer counter,

which is clocked relative to the PH2 clock. These asynchronous capture requests are

synchronized to PH2 so that the latching occurs on the opposite half cycle of PH2 from

when the timer counter is being incremented. This synchronization process introduces

a delay from when the edge occurs to when the counter value is detected. Because

these delays offset each other when the time between two edges is being measured,

the delay can be ignored. When an input capture is being used with an output com-

pare, there is a similar delay between the actual compare point and when the output

pin changes state.

The control and status bits that implement the input capture functions are contained in

the PACTL, TCTL2, TMSK1, and TFLG1 registers.

To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL reg-

ister. Note that this bit is cleared out of reset. To enable PA3 as the fourth input cap-

ture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth

output compare out of reset, with bit I4/O5 being cleared. If the DDRA3 bit is set (con-

figuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on the

pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register

is acting as IC4.

9.2.1 Timer Control 2 Register

Use the control bits of this register to program input capture functions to detect a par-

ticular edge polarity on the corresponding timer input pin. Each of the input capture

functions can be independently configured to detect rising edges only, falling edges

only, any edge (rising or falling), or to disable the input capture function. The input cap-

ture functions operate independently of each other and can capture the same TCNT

value if the input edges are detected within the same timer count cycle.

TCTL2 — Timer Control 2

$0021

Bit 7

EDG4B

0

6

EDG4A

0

5

EDG1B

0

4

EDG1A

0

3

EDG2B

0

2

EDG2A

0

1

EDG3B

0

Bit 0

EDG3A

0

RESET:

EDGxB and EDGxA — Input Capture Edge Control

There are four pairs of these bits. Each pair is cleared to zero by reset and must be

encoded to configure the corresponding input capture edge detector circuit. IC4 func-

tions only if the I4/O5 bit in the PACTL register is set. Refer to Table 9-2 for timer con-

trol configuration.

Table 9-2 Timer Control Configuration

EDGxB

EDGxA

Configuration

Capture disabled

0

1

0

1

0

1

Capture on rising edges only

Capture on falling edges only

Capture on any edge

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9.2.2 Timer Input Capture Registers

When an edge has been detected and synchronized, the 16-bit free-running counter

value is transferred into the input capture register pair as a single 16-bit parallel trans-

fer. Timer counter value captures and timer counter incrementing occur on opposite

half-cycles of the phase two clock so that the count value is stable whenever a capture

occurs. The TICx registers are not affected by reset. Input capture values can be read

from a pair of 8-bit read-only registers. A read of the high-order byte of an input capture

register pair inhibits a new capture transfer for one bus cycle. If a double-byte read in-

struction, such as LDD, is used to read the captured value, coherency is assured.

When a new input capture occurs immediately after a high-order byte read, transfer is

delayed for an additional cycle but the value is not lost.

TIC1–TIC3 — Timer Input Capture

$0010–$0015

$0010

$0011

$0012

$0013

$0014

$0015

RESET:

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

9

1

9

1

Bit 8

TIC1 (High)

TIC1 (Low)

TIC2 (High)

TIC2 (Low)

TIC3 (High)

TIC3 (Low)

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

Input capture registers not affected by reset.

9.2.3 Timer Input Capture 4/Output Compare 5 Register

Use TI4/O5 as either an input capture register or an output compare register, depend-

ing on the function chosen for the I4/O5 pin. To enable it as an input capture pin, set

the I4/O5 bit in the pulse accumulator control register (PACTL) to logic level one. To

use it as an output compare register, set the I4/O5 bit to a logic level zero. Refer to 9.6

Pulse Accumulator.

TI4/O5 — Timer Input Capture 4/Output Compare 5

$001E, $001F

$001E

$001F

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

TI4/O5 (High)

TI4/O5 (Low)

RESET:

All I4/O5 register pairs reset to ones ($FFFF).

9.3 Output Compare

Use the output compare (OC) function to program an action to occur at a specific time

— when the 16-bit counter reaches a specified value. For each of the five output com-

pare functions, there is a separate 16-bit compare register and a dedicated 16-bit com-

parator. The value in the compare register is compared to the value of the free-running

counter on every bus cycle. When the compare register matches the counter value, an

output compare status flag is set. The flag can be used to initiate the automatic actions

for that output compare function.

To produce a pulse of a specific duration, write to the output compare register a value

representing the time the leading edge of the pulse is to occur. The output compare

circuit is configured to set the appropriate output either high or low, depending on the

TIMING SYSTEM

9-6

TECHNICAL DATA

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polarity of the pulse being produced. After a match occurs, the output compare register

is reprogrammed to change the output pin back to its inactive level at the next match.

A value representing the width of the pulse is added to the original value, and then writ-

ten to the output compare register. Because the pin state changes occur at specific

values of the free-running counter, the pulse width can be controlled accurately at the

resolution of the free-running counter, independent of software latencies. To generate

an output signal of a specific frequency and duty cycle, repeat this pulse-generating

procedure.

There are four 16-bit read/write output compare registers: TOC1, TOC2, TOC3, and

TOC4, and the TI4/O5 register, which functions under software control as either IC4

or OC5. Each of the OC registers is set to $FFFF on reset. A value written to an OC

register is compared to the free-running counter value during each E-clock cycle. If a

match is found, the particular output compare flag is set in timer interrupt flag register

1 (TFLG1). If that particular interrupt is enabled in the timer interrupt mask register 1

(TMSK1), an interrupt is generated. In addition to an interrupt, a specified action can

be initiated at one or more timer output pins. For OC5–OC2, the pin action is controlled

by pairs of bits (OMx and OLx) in the TCTL1 register. The output action is taken on

each successful compare, regardless of whether or not the OCxF flag in the TFLG1

register was previously cleared.

OC1 is different from the other output compares in that a successful OC1 compare can

affect any or all five of the OC pins. The OC1 output action taken when a match is

found is controlled by two 8-bit registers with three bits unimplemented: the output

compare 1 mask register, OC1M, and the output compare 1 data register, OC1D.

OC1M specifies which port A outputs are to be used, and OC1D specifies what data

is placed on these port pins.

9.3.1 Timer Output Compare Registers

All output compare registers are 16-bit read-write. Each is initialized to $FFFF at reset.

If an output compare register is not used for an output compare function, it can be used

as a storage location. A write to the high-order byte of an output compare register pair

inhibits the output compare function for one bus cycle. This inhibition prevents inap-

propriate subsequent comparisons. Coherency requires a complete 16-bit read or

write. However, if coherency is not needed, byte accesses can be used.

For output compare functions, write a comparison value to output compare registers

TOC1–TOC4 and TI4/O5. When TCNT value matches the comparison value, speci-

fied pin actions occur.

TIMING SYSTEM

TECHNICAL DATA

9-7

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TOC1–TOC4 — Timer Output Compare

$0016–$001D

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

9

1

9

1

9

1

Bit 8

TOC1 (High)

TOC1 (Low)

TOC2 (High)

TOC2 (Low)

TOC3 (High)

TOC3 (Low)

TOC4 (High)

TOC4 (Low)

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

All TOCx register pairs reset to ones ($FFFF)

TI4/O5 — Timer Input Capture 4/Output Compare 5

$001E, $001F

Refer to 9.2.3 Timer Input Capture 4/Output Compare 5 Register.

9.3.2 Timer Compare Force Register

The CFORC register allows forced early compares. FOC[1:5] correspond to the five

output compares. These bits are set for each output compare that is to be forced. The

action taken as a result of a forced compare is the same as if there were a match be-

tween the OCx register and the free-running counter, except that the corresponding

interrupt status flag bits are not set. The forced channels trigger their programmed pin

actions to occur at the next timer count transition after the write to CFORC.

The CFORC bits should not be used on an output compare function that is pro-

grammed to toggle its output on a successful compare because a normal compare that

occurs immediately before or after the force can result in an undesirable operation.

CFORC — Timer Compare Force

$000B

Bit 7

FOC1

0

6

FOC2

0

5

FOC3

0

4

FOC4

0

3

FOC5

0

2

0

1

0

Bit 0

0

RESET:

FOC1–FOC5 — Write Ones to Force Compare(s)

0 = Not affected

1 = Output x action occurs

Bits [2:0] — Not implemented, always read zero

9.3.3 Output Compare Mask Registers

Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1

compare. The bits of the OC1M register correspond to PA[7:3].

TIMING SYSTEM

9-8

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OC1M — Output Compare 1 Mask

$000C

Bit 7

OC1M7

0

6

OC1M6

0

5

OC1M5

0

4

OC1M4

0

3

OC1M3

0

2

0

1

0

Bit 0

0

RESET:

OC1M7–OC1M3 — Output Compare Masks

0 = OC1 is disabled

1 = OC1 is enabled to control the corresponding pin of port A

Bits [2:0] — Not implemented; always read zero

Set bit(s) to enable OC1 to control corresponding pin(s) of port A.

9.3.4 Output Compare 1 Data Register

Use this register with OC1 to specify the data that is to be stored on the affected pin

of port A after a successful OC1 compare. When a successful OC1 compare occurs,

a data bit in OC1D is stored in the corresponding bit of port A for each bit that is set in

OC1M.

OC1D — Output Compare 1 Data

$000D

Bit 7

OC1D7

0

6

OC1D6

0

5

OC1D5

0

4

OC1D4

0

3

OC1D3

0

2

0

1

0

Bit 0

0

RESET:

If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.

Bits [2:0] — Not implemented; always read zero

9.3.5 Timer Counter Register

The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A

full counter read addresses the most significant byte (MSB) first. A read of this address

causes the least significant byte (LSB) to be latched into a buffer for the next CPU cy-

cle so that a double-byte read returns the full 16-bit state of the counter at the time of

the MSB read cycle.

TCNT — Timer Counter

$000E, $000F

$000E

$000F

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

TCNT (High)

TCNT (Low)

TCNT resets to $0000.

In normal modes, TCNT is read-only.

9.3.6 Timer Control 1 Register

The bits of this register specify the action taken as a result of a successful OCx com-

pare.

TIMING SYSTEM

TECHNICAL DATA

9-9

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TCTL1 — Timer Control 1

$0020

Bit 7

OM2

0

6

OL2

0

5

OM3

0

4

OL3

0

3

OM4

0

2

OL4

0

1

OM5

0

Bit 0

OL5

0

RESET:

OM[2:5] — Output Mode

OL[2:5] — Output Level

These control bit pairs are encoded to specify the action taken after a successful OCx

compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to

the following table for the coding.

OMx

OLx

Action Taken on Successful Compare

Timer disconnected from output pin logic

Toggle OCx output line

0

1

0

1

0

1

Clear OCx output line to 0

Set OCx output line to 1

9.3.7 Timer Interrupt Mask 1 Register

Use this 8-bit register to enable or inhibit the timer input capture and output compare

interrupts.

TMSK1 — Timer Interrupt Mask 1

$0022

Bit 7

OC1I

0

6

OC2I

0

5

OC3I

0

4

OC4I

0

3

I4/O5I

0

2

IC1I

0

1

IC2I

0

Bit 0

IC3I

0

RESET:

OC1I–OC4I — Output Compare x Interrupt Enable

If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt se-

quence is requested.

I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable

When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When

I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit.

IC1I–IC3I — Input Capture x Interrupt Enable

If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence

is requested.

NOTE

Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in

TMSK1 enable the corresponding interrupt sources.

9.3.8 Timer Interrupt Flag 1 Register

Bits in this register indicate when timer system events have occurred. Coupled with the

bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a

TIMING SYSTEM

9-10

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polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in

the same position.

TFLG1 — Timer Interrupt Flag 1

$0023

Bit 7

OC1F

0

6

OC2F

0

5

OC3F

0

4

OC4F

0

3

I4/O5F

0

2

IC1F

0

1

IC2F

0

Bit 0

IC3F

0

RESET:

Clear flags by writing a one to the corresponding bit position(s).

OC1F–OC5F — Output Compare x Flag

Set each time the counter matches output compare x value

I4/O5F — Input Capture 4/Output Compare 5 Flag

Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL

IC1F–IC3F — Input Capture x Flag

Set each time a selected active edge is detected on the ICx input line

9.3.9 Timer Interrupt Mask 2 Register

Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The

timer prescaler control bits are included in this register.

TMSK2 — Timer Interrupt Mask 2

$0024

Bit 7

TOI

0

6

RTII

0

5

PAOVI

0

4

PAII

0

3

0

2

0

1

PR1

0

Bit 0

PR0

0

RESET:

TOI — Timer Overflow Interrupt Enable

0 = TOF interrupts disabled

1 = Interrupt requested when TOF is set to one

RTII — Real-time Interrupt Enable

Refer to 9.4 Real-Time Interrupt.

PAOVI — Pulse Accumulator Overflow Interrupt Enable

Refer to 9.6 Pulse Accumulator.

PAII — Pulse Accumulator Input Edge Interrupt Enable

Refer to 9.6 Pulse Accumulator.

NOTE

Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in

TMSK2 enable the corresponding interrupt sources.

TIMING SYSTEM

TECHNICAL DATA

9-11

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PR[1:0] — Timer Prescaler Select

These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0]

can only be written once, and the write must be within 64 cycles after reset. Refer to

Table 9-1 for specific timing values.

PR[1:0]

0 0

Prescaler

1

4

0 1

1 0

8

1 1

16

9.3.10 Timer Interrupt Flag 2 Register

Bits in this register indicate when certain timer system events have occurred. Coupled

with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to

operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds

to a bit in TMSK2 in the same position.

TFLG2 — Timer Interrupt Flag 2

$0025

Bit 7

TOF

0

6

RTIF

0

5

PAOVF

0

4

PAIF

0

3

0

2

0

1

0

Bit 0

0

RESET:

Clear flags by writing a one to the corresponding bit position(s).

TOF — Timer Overflow Interrupt Flag

Set when TCNT changes from $FFFF to $0000

RTIF — Real-Time (Periodic) Interrupt Flag

Refer to 9.4 Real-Time Interrupt.

PAOVF — Pulse Accumulator Overflow Interrupt Flag

Refer to 9.6 Pulse Accumulator.

PAIF — Pulse Accumulator Input Edge Interrupt Flag

Refer to 9.6 Pulse Accumulator.

Bits [3:0]— Not implemented

Always read zero

9.4 Real-Time Interrupt

The real-time interrupt feature, used to generate hardware interrupts at a fixed periodic

rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulse accumu-

lator control (PACTL) register. The RTII bit in the TMSK2 register enables the interrupt

capability. The four different rates available are a product of the MCU oscillator fre-

quency and the value of bits RTR[1:0]. Refer to the following table, which shows the

periodic real-time interrupt rates.

TIMING SYSTEM

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RTR[1:0]

E = 1 MHz

E = 2 MHz

E = 3 MHz

E = X MHz

(E/2¹³)

(E/2¹⁴)

(E/2¹⁵)

(E/2¹⁶)

0 0

0 1

1 0

1 1

2.731 ms

5.461 ms

10.923 ms

21.845 ms

4.096 ms

8.192 ms

16.384 ms

32.768 ms

8.192 ms

16.384 ms

32.768 ms

65.536 ms

The clock source for the RTI function is a free-running clock that cannot be stopped or

interrupted except by reset. This clock causes the time between successive RTI time-

outs to be a constant that is independent of the software latencies associated with flag

clearing and service. For this reason, an RTI period starts from the previous time-out,

not from when RTIF is cleared.

Every time-out causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt

request is generated. After reset, one entire real-time interrupt period elapses before

the RTIF flag is set for the first time. Refer to the TMSK2, TFLG2, and PACTL regis-

ters.

9.4.1 Timer Interrupt Mask 2 Register

This register contains the real-time interrupt enable bits.

TMSK2 — Timer Interrupt Mask 2

$0024

Bit 7

TOI

0

6

RTII

0

5

PAOVI

0

4

PAII

0

3

0

2

0

1

PR1

0

Bit 0

PR0

0

RESET:

TOI — Timer Overflow Interrupt Enable

Refer to 9.3 Output Compare.

RTII — Real-time Interrupt Enable

0 = RTIF interrupts disabled

1 = Interrupt requested when RTIF is set to one

PAOVI — Pulse Accumulator Overflow Interrupt Enable

Refer to 9.6 Pulse Accumulator.

PAII — Pulse Accumulator Input Edge

Refer to 9.6 Pulse Accumulator.

NOTE

Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in

TMSK2 enable the corresponding interrupt sources.

9.4.1 Timer Interrupt Flag 2 Register

Bits of this register indicate the occurrence of timer system events. Coupled with the

four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate

in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in

TMSK2 in the same position.

TIMING SYSTEM

TECHNICAL DATA

9-13

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TFLG2 — Timer Interrupt Flag 2

$0025

Bit 7

TOF

0

6

RTIF

0

5

PAOVF

0

4

PAIF

0

3

0

2

0

1

0

Bit 0

0

RESET:

Clear flags by writing a one to the corresponding bit position(s).

TOF — Timer Overflow Interrupt Flag

Set when TCNT changes from $FFFF to $0000

RTIF — Real-Time Interrupt Flag

The RTIF status bit is automatically set to one at the end of every RTI period. To clear

RTIF, write a byte to TFLG2 with bit 6 set.

PAOVF — Pulse Accumulator Overflow Interrupt Flag

Refer to 9.6 Pulse Accumulator.

PAIF — Pulse Accumulator Input Edge Interrupt Flag

Refer to 9.6 Pulse Accumulator.

Bits [3:0] — Not implemented

Always read zero

9.4.2 Pulse Accumulator Control Register

Bits RTR[1:0] of this register select the rate for the real-time interrupt system. Bit

DDRA3 determines whether Port A bit three is an input or an output when used for

general-purpose I/O. The remaining bits control the pulse accumulator.

PACTL — Pulse Accumulator Control

$0026

Bit 7

DDRA7

0

6

PAEN

0

5

PAMOD

0

4

PEDGE

0

3

DDRA3

0

2

I4/O5

0

1

RTR1

0

Bit 0

RTR0

0

RESET:

DDRA7 — Data Direction Control for Port A Bit 7

Refer to 9.6 Pulse Accumulator.

PAEN — Pulse Accumulator System Enable

Refer to 9.6 Pulse Accumulator.

PAMOD — Pulse Accumulator Mode

Refer to 9.6 Pulse Accumulator.

PEDGE — Pulse Accumulator Edge Control

Refer to 9.6 Pulse Accumulator.

DDRA3 — Data Direction Register for Port A Bit 3

Refer to SECTION 6 PARALLEL I/O.

I4/O5 — Input Capture 4/Output Compare 5

Refer to 9.2 Input Capture.

TIMING SYSTEM

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RTR[1:0] — RTI Interrupt Rate Select

These two bits determine the rate at which the RTI system requests interrupts. The

RTI system is driven by an E divided by 2¹³rate clock that is compensated so it is in-

dependent of the timer prescaler. These two control bits select an additional division

factor.

RTR[1:0]

E = 1 MHz

E = 2 MHz

E = 3 MHz

E = X MHz

(E/2¹³)

(E/2¹⁴)

(E/2¹⁵)

(E/2¹⁶)

0 0

0 1

1 0

1 1

2.731 ms

5.461 ms

10.923 ms

21.845 ms

4.096 ms

8.192 ms

16.384 ms

32.768 ms

8.192 ms

16.384 ms

32.768 ms

65.536 ms

9.5 Computer Operating Properly Watchdog Function

The clocking chain for the COP function, tapped off of the main timer divider chain, is

only superficially related to the main timer system. The CR[1:0] bits in the OPTION

register and the NOCOP bit in the CONFIG register determine the status of the COP

function. Refer to SECTION 5 RESETS AND INTERRUPTS for a more detailed dis-

cussion of the COP function.

9.6 Pulse Accumulator

The MC68HC11D3 has an 8-bit counter that can be configured to operate either as a

simple event counter, or for gated time accumulation, depending on the state of the

PAMOD bit in the PACTL register. Refer to the pulse accumulator block diagram, Fig-

ure 9-3.

In the event counting mode, the 8-bit counter is clocked to increasing values by an ex-

ternal pin. The maximum clocking rate for the external event counting mode is the E

clock divided by two. In gated time accumulation mode, a free-running E-clock ÷ 64

signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer to

Table 9-3. The pulse accumulator counter can be read or written at any time.

TIMING SYSTEM

TECHNICAL DATA

9-15

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1

INTERRUPT

REQUESTS

2

V

F

I

F

O

P

A

TMSK2

TFLG2

PAI EDGE

DISABLE

FLAG SETTING

E ÷ 64 CLOCK

(FROM MAIN TIMER)

INPUT BUFFER

&

EDGE DETECTION

OVERFLOW

ENABLE

PA7/

PAI/OC1

2:1

MUX

PACNT

8-BIT COUNTER

OUTPUT

BUFFER

FROM

MAIN TIMER

OC1

PAEN

PACTL

INTERNAL

DATA BUS

11 PULSE ACC BLOCK

Figure 9-3 Pulse Accumulator

Table 9-3 Pulse Accumulator Timing

Common XTAL Frequencies

Selected Crystal

4.0 MHz

1.0 MHz

1000 ns

8.0 MHz

2.0 MHz

500 ns

12.0 MHz

3.0 MHz

333 ns

CPU Clock

Cycle Time

(E)

(1/E)

Pulse Accumulator (in Gated Mode)

(E/2⁶)

(E/2¹⁴)

1 count -

overflow -

64.0 µs

16.384 ms

32.0 µs

8.192 ms

21.33 µs

5.461 ms

Pulse accumulator control bits are also located within two timer registers, TMSK2 and

TFLG2, as described in the following paragraphs.

TIMING SYSTEM

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9.6.1 Pulse Accumulator Control Register

Four of this register's bits control an 8-bit pulse accumulator system. Another bit en-

ables either the OC5 function or the IC4 function, while two other bits select the rate

for the real-time interrupt system.

PACTL — Pulse Accumulator Control

$0026

Bit 7

DDRA7

0

6

PAEN

0

5

PAMOD

0

4

PEDGE

0

3

DDRA3

0

2

I4/O5

0

1

RTR1

0

Bit 0

RTR0

0

RESET:

DDRA7 — Data Direction Control for Port A Bit 7

The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be used

as general-purpose I/O or as an output compare. Note that even when port A bit 7 is

configured as an output, the pin still drives the input to the pulse accumulator. Refer to

SECTION 6 PARALLEL I/O for more information.

PAEN — Pulse Accumulator System Enable

0 = Pulse accumulator disabled

1 = Pulse accumulator enabled

PAMOD — Pulse Accumulator Mode

0 = Event counter

1 = Gated time accumulation

PEDGE — Pulse Accumulator Edge Control

This bit has different meanings depending on the state of the PAMOD bit, as shown in

the following table:

PAMOD

PEDGE

Action on Clock

0

1

0

1

0

1

PAI Falling Edge Increments the Counter.

PAI Rising Edge Increments the Counter.

A Zero on PAI Inhibits Counting.

A One on PAI Inhibits Counting.

DDRA3 — Data Direction Register for Port A Bit 3

Refer to SECTION 6 PARALLEL I/O.

I4/O5 — Input Capture 4/Output Compare 5

Refer to 9.2 Input Capture.

RTR[1:0] — RTI Interrupt Rate Selects

Refer to 9.4 Real-Time Interrupt.

9.6.2 Pulse Accumulator Count Register

This 8-bit read/write register contains the count of external input events at the PAI in-

put, or the accumulated count. The counter is not affected by reset and can be read or

written at any time. Counting is synchronized to the internal PH2 clock so that incre-

menting and reading occur during opposite half cycles.

TIMING SYSTEM

TECHNICAL DATA

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PACNT — Pulse Accumulator Count

$0027

Bit 7

6

5

4

3

2

1

Bit 0

9.6.3 Pulse Accumulator Status and Interrupt Bits

The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF are located

within timer registers TMSK2 and TFLG2.

PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag

The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF

to $00. To clear this status bit, write a one in the corresponding data bit position (bit 5)

of the TFLG2 register. The PAOVI control bit allows configuring the pulse accumulator

overflow for polled or interrupt-driven operation and does not affect the state of

PAOVF. When PAOVI is zero, pulse accumulator overflow interrupts are inhibited, and

the system operates in a polled mode, which requires PAOVF to be polled by user soft-

ware to determine when an overflow has occurred. When the PAOVI control bit is set,

a hardware interrupt request is generated each time PAOVF is set. Before leaving the

interrupt service routine, software must clear PAOVF by writing to the TFLG2 register.

PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable and Flag

The PAIF status bit is automatically set each time a selected edge is detected at the

PA7/PAI/OC1 pin. To clear this status bit, write to the TFLG2 register with a one in the

corresponding data bit position (bit 4). The PAII control bit allows configuring the pulse

accumulator input edge detect for polled or interrupt-driven operation but does not af-

fect setting or clearing the PAIF bit. When PAII is zero, pulse accumulator input inter-

rupts are inhibited, and the system operates in a polled mode. In this mode, the PAIF

bit must be polled by user software to determine when an edge has occurred. When

the PAII control bit is set, a hardware interrupt request is generated each time PAIF is

set. Before leaving the interrupt service routine, software must clear PAIF by writing to

the TFLG register.

TMSK2 — Timer Interrupt Mask 2

$0024

Bit 7

TOI

0

6

RTII

0

5

PAOVI

0

4

PAII

0

3

0

2

0

1

PR1

0

Bit 0

PR0

0

RESET:

TFLG2 — Timer Interrupt Flag 2

$0025

Bit 7

TOF

0

6

RTIF

0

5

PAOVF

0

4

PAIF

0

3

0

2

0

1

0

Bit 0

0

RESET:

TIMING SYSTEM

9-18

TECHNICAL DATA

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APPENDIX A

ELECTRICAL CHARACTERISTICS

Table A-1 Maximum Ratings

Rating

Symbol

V_DD

V_in

Value

Unit

V

Supply Voltage

Input Voltage

– 0.3 to + 7.0

T_Lto T_H

V

Operating Temperature Range

MC6811D3

T_A

°C

0 to + 70

MC6811D3C

MC6811D3V

MC6811D3M

– 40 to + 85

– 40 to + 105

– 40 to + 125

Storage Temperature Range

T_stg

I_D

– 55 to + 150

25

°C

Current Drain per Pin*

Excluding V_DDand V_SS

mA

*One pin at a time, observing maximum power dissipation limits.

Internal circuitry protects the inputs against damage caused by high static voltages or

electric fields; however, normal precautions are necessary to avoid application of any

voltage higher than maximum-rated voltages to this high-impedance circuit. Extended

operation at the maximum ratings can adversely affect device reliability. Tying unused

inputs to an appropriate logic voltage level (either GND or V ) enhances reliability of

DD

operation.

Table A-2 Thermal Characteristics

Characteristic

Average Junction Temperature

Symbol

T_J

Value

Unit

°C

T_A+ (P_Dx Θ_JA

)

Ambient Temperature

T_A

User-determined

°C

Package Thermal Resistance

(Junction-to-Ambient)

Θ_JA

°C/W

44-Pin Plastic Leaded Chip Carrier (PLCC)

44-Pin Plastic Quad Flat Pack (QFP)

52-Pin Plastic Dip (P)

50

Total Power Dissipation

(Note 1)

P_D

P_INT+ P_I/O

W

/

_(TJ+ 273°C)

K

Device Internal Power Dissipation

I/O Pin Power Dissipation

A Constant

P_INT

P_I/O

K

I_DDx V_DD

W

(Note 2)

(Note 3)

User-determined

P_Dx (T_A+ 273°C) +

W < °C

2

Θ_JAx P_D

NOTES:

1. This is an approximate value, neglecting P_I/O

.

2. For most applications P_I/O« P_INTand can be neglected.

3. K is a constant pertaining to the device. Solve for K with a known T_Aand a measured P_D(at equilibrium). Use

this value of K to solve for P_Dand T_Jiteratively for any value of T_A.

ELECTRICAL CHARACTERISTICS

TECHNICAL DATA

A-1

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Table A-3 DC Electrical Characteristics

Characteristic

Symbol

Min

Max

Unit

Output Voltage (Note 1)

All Outputs except XTAL

All Outputs Except XTAL, RESET,

V_OL

V_OH

—

0.1

—

V

V_DD– 0.1

I_LOAD= ± 10.0 µA

and MODA

Output High Voltage (Note 1)

All Outputs Except XTAL,

RESET, and MODA

V_OH

V_DD– 0.8

—

V

I_LOAD= – 0.8 mA, V_DD= 4.5 V

Output Low Voltage

I_LOAD= 1.6 mA, V_DD= 5.0 V

All Outputs Except XTAL

V_OL

V_IH

—

0.4

Input High Voltage

All Inputs Except RESET

RESET

0.7 x V_DD

0.8 x VDD

V_DD+ 0.3

V

Input Low Voltage

All Inputs

V_IL

I_OZ

V_SS– 0.3

0.2 x V_DD

±10

V

I/O Ports, Three-State Leakage PA7,PA3,PB[7:0],PC[7:0],PD[7:0],

—

µA

V_in= V_IHor V_IL

MODA/LIR, RESET

Input Leakage Current

V_in= V_DDor V_SS

I_in

PA[2:0], IRQ, XIRQ

MODB/V_STBY

—

±1

±10

µA

RAM Standby Voltage

RAM Standby Current

Input Capacitance

Power down

V_SB

I_SB

4.0

—

V_DD

10

V

µA

PA[2:0], IRQ, XIRQ, EXTAL

C_in

—

8

12

pF

PA7, PA3, PB[7:0], PC[7:0], PD[7:0], MODA/LIR, RESET

Output Load Capacitance

C_L

—

90

100

pF

All Outputs Except PD[4:1]

Characteristic

PD[4:1]

Symbol

1 MHz

2 MHz

Unit

Maximum Total Supply Current (Note 2)

RUN:

Single-Chip Mode

I_DD

V

_DD= 5.5 V

8

14

15

27

mA

Expanded Multiplexed Mode

V_DD= 5.5 V

WAIT:

(All Peripheral Functions Shut Down)

V_DD= 5.5 V

W_IDD

Single-Chip Mode

Expanded Multiplexed Mode

STOP:

3

5

6

10

mA

V_DD= 5.5 V

S_IDD

P_D

Single-Chip Mode, No Clocks

V_DD= 5.5 V

50

µA

Maximum Power Dissipation

Single-Chip Mode

Expanded Multiplexed Mode

V_DD= 5.5 V

44

77

85

150

mW

NOTES:

1. V_OHspecification for RESET and MODA is not applicable because they are open-drain pins. V_OHspecification

not applicable to ports C and D in wired-OR mode.

2. EXTAL is driven with a square wave, and

t

_cyc= 1000 ns for 1 MHz rating;

t_cyc= 500 ns for 2 MHz rating;

_tcyc= 333 ns for 3 MHz rating;

V_IL≤ 0.2 V;V_IH≥ V_DD- 0.2 V;

No dc loads.

ELECTRICAL CHARACTERISTICS

A-2

TECHNICAL DATA

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V

~

DD

CLOCKS,

STROBES

V

– 0.8 Volts

DD

0.4 Volts

~ V

SS

NOM.

70% of V

DD

INPUTS

20% of V

DD

NOMINAL TIMING

V

~

DD

V

– 0.8 Volts

DD

OUTPUTS

0.4 Volts

~ V

SS

DC TESTING

~ V

DD

70% of V

SPEC

CLOCKS,

STROBES

DD

20% of V

SPEC

20% of V

DD

V

~

SS

(NOTE 2)

V

– 0.8 Volts

DD

70% of V

20% of V

DD

INPUTS

DD

0.4 Volts

SPEC TIMING

V

~ DD

70% of V

20% of V

DD

OUTPUTS

V

~ SS

AC TESTING

NOTES:

1. Full test loads are applied during all DC electrical tests and AC timing measurements.

2. During AC timing measurements, inputs are driven to 0.4 volts and VDD – 0.8 volts while timing

measurements are taken at the 20% and 70% of V_DDpoints.

TEST METHODS

Figure A-1 Test Methods

ELECTRICAL CHARACTERISTICS

TECHNICAL DATA

A-3

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Table A-4 Control Timing

Characteristic

Symbol

1.0 MHz

2.0 MHz

3.0 MHz

Unit

Min

Max

1.0

—

Min

Max

2.0

—

Min

Max

3.0

Frequency of Operation

f_o

dc

1000

—

dc

500

—

dc

333

—

MHz

ns

E-Clock Period

t_cyc

—

Crystal Frequency

f_XTAL

4 f_o

4.0

—

8.0

—

12.0

—

MHz

ns

External Oscillator Frequency

dc

Processor Control SetupTime

t_PCSU= 1/4 t_cyc+ 50 ns

t_PCSU

300

175

133

Reset Input Pulse Width

PW_RSTL

To Guarantee External Reset Vector

8

1

—

8

1

—

8

1

—

t_cyc

Minimum Input Time

(Can Be Preempted by Internal Reset)

Mode Programming Setup Time

t_MPS

t_MPH

2

—

2

—

2

—

t_cyc

ns

Mode Programming Hold Time

10

Interrupt Pulse Width,

IRQ Edge-Sensitive Mode

PW_IRQ= t_cyc+ 20 ns

PW_IRQ

1020

520

353

ns

Wait Recovery Startup Time

t_WRS

—

4

—

4

—

4

t_cyc

ns

Timer Pulse Width,

Input Capture Pulse

Accumulator Input

PW_TIM= t_cyc+ 20 ns

PW_TIM

1020

—

520

—

353

—

NOTES:

1. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four

clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt.

Refer to SECTION 5 RESETS AND INTERRUPTS for further detail.

2. All timing is shown with respect to 20% V_DDand 70% V_DD, unless otherwise noted.

1

PA[2:0]

2

PA[2:0]

1,3

PA7

PW

TIM

2,3

PA7

NOTES:

1. Rising edge sensitive input

2. Falling edge sensitive input

3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.

TIMER INPUTS TIM

Figure A-2 Timer Inputs

ELECTRICAL CHARACTERISTICS

A-4

TECHNICAL DATA

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M

I

T

C

E

N

R

X

F

R

F

O

P

F

E

F

E

H

F

M

t

E

F

Figure A-3 POR and External Reset Timing Diagram

ELECTRICAL CHARACTERISTICS

TECHNICAL DATA

A-5

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M

I

T

Y

OC

R

W

.

C

O

E

T

S

c

s

)

n

F

O

F

S

e

)

s

F

o

F

o

f

cih

8

w

–

n

P

t

s

Figure A-4 STOP Recovery Timing Diagram

ELECTRICAL CHARACTERISTICS

A-6

TECHNICAL DATA

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M

I

T

Y

R

E

V

OC

R

W

I

C

E

W

R

C

E

A

R

T

D

A

E

8

P

8

Figure A-5 WAIT Recovery Timing Diagram

ELECTRICAL CHARACTERISTICS

TECHNICAL DATA

A-7

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Table A-5 Peripheral Port Timing

Characteristic

Symbol

1.0 MHz

2.0 MHz

3.0 MHz

Unit

Min

Max

1.0

—

Min

Max

2.0

—

Min

Max

3.0

—

Frequency of Operation (E-Clock Frequency)

E-Clock Period

f_o

dc

MHz

ns

t_cyc

1000

100

500

100

333

100

Peripheral Data Setup Time

t_PDSU

—

ns

MCU Read of Ports A, B, C, and D

Peripheral Data Hold Time

MCU Read of Ports A, B, C, and D

t_PDH

t_PWD

50

—

50

—

50

—

ns

Delay Time, Peripheral Data Write

MCU Write to Port A

MCU Writes to Ports B, C, and D

t_PWD= 1/4 t_cyc+ 150 ns

—

200

350

—

200

225

—

200

183

ns

NOTES:

1. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respec-

tively).

2. All timing is shown with respect to 20% V_DDand 70% V_DD, unless otherwise noted.

MCU WRITE TO PORT

E

t

PWD

PORTS

B, C, D

PREVIOUS PORT DATA

NEW DATA VALID

t

PWD

PREVIOUS PORT DATA

NEW DATA VALID

PORT A

D3 PORT WRITE TIM

Figure A-6 Port Write Timing Diagram

MCU READ OF PORT

E

t

PDH

PDSU

PORTS

A, B, C, D

D3 PORT READ TIM

Figure A-7 Port Read Timing Diagram

ELECTRICAL CHARACTERISTICS

A-8

TECHNICAL DATA

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Table A-6 Expansion Bus Timing

Num

Characteristic

Symbol

1.0 MHz

2.0 MHz

3.0 MHz

Unit

Min

Max

Min

Max

Min

Max

Frequency of Operation (E-Clock

Frequency)

f_o

dc

1.0

dc

2.0

dc

3.0

MHz

1

2

Cycle Time

t_cyc

1000

477

—

500

227

—

333

146

—

ns

Pulse Width, E Low

PW_EL= 1/2 t_cyc- 23ns

PW_EL

3

Pulse Width, E High

PW_EH= 1/2 t_cyc- 28 ns

PW_EH

472

—

222

—

141

—

ns

4A E and AS Rise Time

t_r

t_f

—

20

—

20

—

20

15

ns

4B

E and AS Fall Time

9

Address Hold Time

t_AH= 1/8 t_cyc- 29.5 ns

t_AH

95.5

—

33

—

26

—

ns

(Note 1a)

12 Non-Muxed Address Valid Time to E Rise

t_AV= PW_EL- (t_ASD+ 80 ns) (Note 1a)

t_AV

281.5

—

94

—

54

—

ns

17 Read Data Setup Time

t_DSR

t_DHR

t_DDW

30

0

—

30

0

—

83

30

0

—

51

71

ns

18 Read Data Hold Time (Max = t_MAD

)

145.5

190.5

19 Write Data Delay Time

—

128

—

t_DDW= 1/8 t_cyc+ 65.5 ns

(Note 1a)

21 Write Data Hold Time

t_DHW= 1/8 t_cyc- 30 ns

t_DHW

t_AVM

95.5

271.5

151

—

33

84

26

33

53

96

53

307

—

26

54

13

31

63

31

196

—

ns

22 Muxed Address Valid Time to E Rise

_AVM= PW_{EL -}(t_ASD+ 90 ns) (Note 1a)

t

24 Muxed Address Valid Time to AS Fall

_ASL= PW_ASH- 70 ns

t_ASL

—

t

25 Muxed Address Hold Time

t_AHL= 1/8 t_cyc- 30 ns

t_AHL

95.5

115.5

221

—

(Note 1b)

(Note 1a)

26 Delay Time, E to AS Rise

t_ASD

—

t

_ASD= 1/8 t_cyc- 5 ns

27 Pulse Width, AS High

PW_ASH= 1/4 t_cyc- 30 ns

PW_ASH

t_ASED

t_ACCA

t_ACCE

t_MAD

—

28 Delay Time, AS to E Rise

t_ASED= 1/8 t_cyc- 5 ns

115.5

744.5

—

(Note 1b)

(Note 1a)

29 MPU Address Access Time

—

t_ACCA= t_cyc– (PW_EL– t_AVM) – t_DSR–t_f

35 MPU Access Time

_ACCE= PW_EH- t_DSR

36 Muxed Address Delay

(Previous Cycle MPU Read)

t_MAD= t_ASD+ 30 ns(Note 1a)

442

—

192

—

111

—

t

145.5

83

51

NOTES:

1. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock

duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following

expressions in place of 1/8 t_cycin the above formulas, where applicable:

(a) (1-DC) × 1/4 t_cyc

(b) DC × 1/4 t_cyc

Where:

DC is the decimal value of duty cycle percentage (high time).

2. All timing is shown with respect to 20% V_DDand 70% V_DD, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

TECHNICAL DATA

A-9

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1

2

3

E

4a

4b

12

9

R/W, ADDRESS

(NON-MUX)

22

35

17

36

29

18

21

READ

ADDRESS

DATA

ADDRESS/DATA

(MULTIPLEXED)

19

WRITE

ADDRESS

DATA

25

24

4a

26

4b

AS

27

28

NOTE: Measurement points shown are 20% and 70% of V_DD

.

MUX BUS TIM

Figure A-8 Multiplexed Expansion Bus Timing Diagram

ELECTRICAL CHARACTERISTICS

A-10

TECHNICAL DATA

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Table A-7 Serial Peripheral Interface Timing

Num

Characteristic

Symbol

2.0 MHz

3.0 MHz

Unit

Min

Max

Min

Max

Operating Frequency

Master

Slave

f_op(m)

f_op(s)

dc

0.5

2.0

dc

0.5

3.0

f_op

MHz

1

2

3

4

5

6

7

8

9

Cycle Time

Master

Slave

t_cyc(m)

t_cyc(s)

2.0

500

—

2.0

333

—

t_cyc

ns

Enable Lead Time

Master (Note 2)

Slave

t_lead(m)

t_lead(s)

—

250

—

240

—

ns

Enable Lag Time

Master (Note 2)

Slave

t_lag(m)

t_lag(s)

—

250

—

240

—

ns

Clock (SCK) High Time

Master

Slave

t_w(SCKH)m

t_w(SCKH)s

340

190

—

340

190

—

ns

Clock (SCK) Low Time

Master

Slave

t_w(SCKL)m

t_w(SCKL)s

340

190

—

340

190

—

ns

Data Setup Time (Inputs)

Master

Slave

t_su(m)

t_su(s)

100

—

100

—

ns

Data Hold Time (Inputs)

Master

Slave

t_h(m)

t_h(s)

100

—

100

—

ns

Access Time

(Time to Data Active from High-Imp. State)

Slave

t_a

0

120

0

120

ns

Disable Time

(Hold Time to High-Impedance State)

Slave

t_dis

t_v(s)

t_ho

—

0

240

—

0

167

—

ns

10

11

12

Data Valid (After Enable Edge) (Note 3)

Data Hold Time (Outputs) (After Enable Edge)

Rise Time (20% V_DDto 70% V_DD, C_L= 200 pF)

SPI Outputs (SCK, MOSI, and MISO)

SPI Inputs (SCK, MOSI, MISO, and SS)

t_rm

t_rs

—

100

2.0

—

100

2.0

ns

µs

13

Fall Time (70% V_DDto 20% V_DD, C_L= 200 pF)

SPI Outputs (SCK, MOSI, and MISO)

SPI Inputs (SCK, MOSI, MISO, and SS)

t_fm

t_fs

—

100

2.0

—

100

2.0

ns

µs

NOTES:

1. All timing is shown with respect to 20% V_DDand 70% V_DD, unless otherwise noted.

2. Signal production depends on software.

3. Assumes 100 pF load on all SPI pins.

ELECTRICAL CHARACTERISTICS

TECHNICAL DATA

A-11

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SS

(INPUT)

SS is held high on master.

1

12

13

12

5

SCK (CPOL = 0)

(OUTPUT)

SEE

NOTE

4

5

SCK (CPOL = 1)

(OUTPUT)

SEE

NOTE

4

6

7

MISO

(INPUT)

MSB IN

BIT 6 - - - -1

LSB IN

11 (ref)

10 (ref)

11

10

MOSI

(OUTPUT)

MASTER MSB OUT

MASTER LSB OUT

12

13

NOTE: This first clock edge is generated internally but is not seen at the SCK pin.

SPI MASTER CPHA0 TIM

Figure A-9 SPI Master Timing (CPHA = 0)

SS

(INPUT)

SS is held high on master.

1

12

13

5

SEE

NOTE

SCK (CPOL = 0)

(OUTPUT)

4

5

SCK (CPOL = 1)

(OUTPUT)

SEE

NOTE

4

12

7

6

MISO

(INPUT)

MSB IN

BIT 6 - - - -1

LSB IN

11 (ref)

10 (ref)

10

BIT 6 - - - -1

11

MOSI

(OUTPUT)

MASTER MSB OUT

13

NOTE: This last clock edge is generated internally but is not seen at the SCK pin.

MASTER LSB OUT

12

SPI MASTER CPHA1 TIM

Figure A-10 SPI Master Timing (CPHA = 1)

ELECTRICAL CHARACTERISTICS

A-12

TECHNICAL DATA

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SS

(INPUT)

1

13

12

3

5

4

SCK (CPOL = 0)

(INPUT)

4

5

2

SCK (CPOL = 1)

(INPUT)

12

13

9

8

SEE

NOTE

MISO

(OUTPUT)

BIT 6 - - - -1

11

BIT 6 - - - -1

MSB OUT

7

SLAVE LSB OUT

SLAVE

6

10

11

MOSI

(INPUT)

MSB IN

LSB IN

NOTE: Not defined but normally MSB of character just received.

SPI SLAVE CPHA0 TIM

Figure A-11 SPI Slave Timing (CPHA = 0)

SS

(INPUT)

1

12

13

5

4

SCK (CPOL = 0)

(INPUT)

4

5

2

3

SCK (CPOL = 1)

(INPUT)

13

12

9

8

10

SEE

NOTE

MISO

(OUTPUT)

SLAVE

6

MSB OUT

7

BIT 6 - - - -1

10

BIT 6 - - - -1

SLAVE LSB OUT

11

MOSI

(INPUT)

MSB IN

LSB IN

NOTE: Not defined but normally LSB of character previously transmitted.

SPI SLAVE CPHA1 TIM

Figure A-12 SPI Slave Timing (CPHA = 1)

ELECTRICAL CHARACTERISTICS

TECHNICAL DATA

A-13

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ELECTRICAL CHARACTERISTICS

A-14

TECHNICAL DATA

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APPENDIX B

MECHANICAL DATA AND ORDERING INFORMATION

B.1 Pin Assignments

The MC68HC11D3 is available in the 40-pin DIP, shown in Figure B-1, the 44-pin

PLCC, shown in Figure B-2, or the 44-pin quad flat pack (QFP), as shown in Figure

B-3. Refer to Table B-1 for ordering information.

40 XTAL

V

1

SS

39 EXTAL

PC0/ADDR0

PC1/ADDR1

PC2/ADDR2

PC3/ADDR3

PC4/ADDR4

PC5/ADDR5

PC6/ADDR6

PC7/ADDR7

2

38

E

3

37 MODA/LIR

36 MODB/V

4

5

STBY

35 PB0/ADDR8

34 PB1/ADDR9

33 PB2/ADDR10

32 PB3/ADDR11

31 PB4/ADDR12

30 PB5/ADDR13

29 PB6/ADDR14

28 PB7/ADDR15

27 PA0/IC3

6

7

MC68HC(7)11D3

8

9

XIRQ/V

10

PP

PD7/R/W 11

PD6/AS 12

RESET 13

IRQ 14

26 PA1/IC2

PD0/RxD 15

PD1/TxD 16

PD2/MISO 17

PD3/MOSI 18

PD4/SCK 19

PD5/SS 20

25 PA2/IC1

24 PA3/IC4/OC5/OC1

23 PA5/OC3/OC1

22 PA7/PAI/OC1

21

V

DD

D3 40-PIN DIP

Figure B-1 40-Pin DIP

MECHANICAL DATA AND ORDERING INFORMATION

TECHNICAL DATA

B-1

For More Information On This Product,

Go to: www.freescale.com

39

PB0/ADDR8

PB1/ADDR9

7

PC4/ADDR4

PC5/ADDR5

PC6/ADDR6

8

38

37

36

9

PB2/ADDR10

PB3/ADDR11

10

PC7/ADDR7

11

12

35

PB4/ADDR12

PB5/ADDR13

XIRQ/V

PP

MC68HC(7)11D3

34

33

PD7/R/W

13

14

PB6/ADDR14

PB7/ADDR15

NC

PD6/AS

RESET

32

31

30

15

IRQ

PA0/IC3

PA1/IC2

16

17

PD0/RxD

29

PD1/TxD

Figure B-2 44-Pin PLCC

. . I n c .

S e m i c o n d u F c r t e o e r , s c a l e

MC68HC11D3

B-2

TECHNICAL DATA

PB0/ADDR8

PB1/ADDR9

PB2/ADDR10

PB3/ADDR11

PB4/ADDR12

PB5/ADDR13

PB6/ADDR14

PB7/ADDR15

NC

PC4/ADDR4

PC5/ADDR5

PC6/ADDR6

PC7/ADDR7

1

2

3

4

33

32

31

30

29

28

27

5

XIRQ/V

PP

MC68HC(7)11D3

6

PD7/R/W

PD6/AS

RESET

7

8

26

25

24

23

9

IRQ

PA0/IC3

PD0/RxD

10

11

PA1/IC2

PD1/TxD

Figure B-3 44-Pin QFP

B.2 Package Dimensions

For case outline information check our web site at http://www.motsps.com.

B.3 Ordering Information

Add the proper suffix, from Table B-1, to the M68HC11- (or 711-) MCU number to

specify the appropriate device when placing an order. Figure B-4 identifies the codes

used to identify specific MCU options.

Table B-1 Ordering Information

MCU

Package

40-Pin DIP

Temperature

– 40 to +85°C

Description

BUFFALO ROM

No ROM

Suffix

CP1

D3

44-Pin PLCC

CFN1

CFBL

CP

44-Pin Quad Flat Pack

40-Pin DIP

D0

44-Pin PLCC

No ROM

CFN

CFB

44-Pin Quad Flat Pack

No ROM

. . I n c .

S e m i c o n d u F c r t e o e r , s c a l e

TECHNICAL DATA

B-3

Freescale Semiconductor, Inc.

Figure B-4 M68HC11 Part Number Options

MECHANICAL DATA AND ORDERING INFORMATION

B-4

TECHNICAL DATA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

APPENDIX C

DEVELOPMENT SUPPORT

C.1 Development System Tools

Freescale has developed tools for use in debugging and evaluating M68HC11 equip-

ment. Refer to the following list for those development tools that are available for use

with the MC68HC11D3. For information about Freescale and third party development

system hardware and software, contact your Freescale sales representative.

C.2 MC68HC11D3 Development Tools

• M68HC11D3EVS Evaluation System

• M68HC711D3PGMR Programmer Board

• M68HC711D3EVB Evaluation Board

DEVELOPMENT SUPPORT

TECHNICAL DATA

C-1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Home Page:

www.freescale.com

email:

support@freescale.com

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

(800) 521-6274

RoHS-compliant and/or Pb- free versions of Freescale products have the functionality

and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free

counterparts. For further information, see http://www.freescale.com or contact your

Freescale sales representative.

For information on Freescale.s Environmental Products program, go to

http://www.freescale.com/epp.

480-768-2130

support@freescale.com

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

support@freescale.com

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

1-8-1, Shimo-Meguro, Meguro-ku

Tokyo 153-0064, Japan

0120 191014

+81 2666 8080

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of

any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be

provided in Freescale Semiconductor data sheets and/or specifications can and do

vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Freescale Semiconductor product

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate,

Tai Po, N.T., Hong Kong

+800 2666 8080

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor

Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

(800) 441-2447

303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor

@hibbertgroup.com

Semiconductor was negligent regarding the design or manufacture of the part.

DEVELOPMENT SUPPORT

C-2

TECHNICAL DATA

For More Information On This Product,

Go to: www.freescale.com


型号：	MC68HC711F1CFB1
厂家：	Freescale
描述：	ROM-based high-performance microcontrollers 基于ROM的高性能微控制器微控制器
文件：	总124页 (文件大小：1874K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC68HC711F1CFB1 [FREESCALE]

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