MC68HLC908QT1 [FREESCALE]
M68HC08 Microcontrollers; M68HC08微控制器
| 型号： | MC68HLC908QT1 |
| 厂家： | 
Freescale |
| 描述： | M68HC08 Microcontrollers |
| 文件： | 总182页 (文件大小：1738K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HLC908QY4
MC68HLC908QT4
MC68HLC908QY2
MC68HLC908QT2
MC68HLC908QY1
MC68HLC908QT1
Data Sheet
M68HC08
Microcontrollers
MC68HLC908QY4/D
Rev. 3
07/2005
freescale.com
MC68HLC908QY4
MC68HLC908QT4
MC68HLC908QY2
MC68HLC908QT2
MC68HLC908QY1
MC68HLC908QT1
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
3
Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Revision
Level
Page
Number(s)
Date
Description
August,
2003
N/A
Initial release
N/A
26
Figure 2-2. Control, Status, and Data Registers Deleted unimplemented areas
from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available. Also
corrected $FFBF designation from unimplemented to reserved.
Figure 6-1. COP Block Diagram — Reworked for clarity
57
58
6.3.2 STOP Instruction — Added subsection for STOP instruction
13.4.2 Active Resets from Internal Sources — Reworked notes for clarity.
15.3 Monitor Module (MON) — Clarified seventh bullet.
October,
2003
1.0
115
154
169
16.5 DC Electrical Characteristics — Corrected notes 4 and 5.
16.6 Control Timing — Updated values for RST input pulse width low and IRQ
interrupt pulse width low
170
30
Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the
FLASH Block Protect Register at address location $FFBE and the Internal
Oscillator Trim Value at $FFC0.
January,
2004
2.0
3.0
Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for
clarity.
37
Reformatted to meet current documentation standards
Throughout
Chapter 7 Central Processor Unit (CPU) — In 7.7 Instruction Set Summary:
Reworked definitions for STOP instruction
70
71
Added WAIT instruction
July,
2005
13.8.1 SIM Reset Status Register — Clarified SRSR flag setting.
14.9.1 TIM Status and Control Register — Added information to TSTOP note.
17.3 Package Dimensions — Updated package information.
117
127
163
MC68HLC908QY/QT Family Data Sheet, Rev. 3
4
Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Chapter 6 Computer Operating Properly (COP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Chapter 8 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Chapter 10 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Chapter 11 Oscillator Module (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Chapter 12 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Chapter 13 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Chapter 14 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Chapter 17 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .163
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
5
List of Chapters
MC68HLC908QY/QT Family Data Sheet, Rev. 3
6
Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1
1.2
1.3
1.4
1.5
1.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Function Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 2
Memory
2.1
2.2
2.3
2.4
2.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.6
FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
Chapter 3
Analog-to-Digital Converter (ADC)
3.1
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5
3.5.1
3.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
7
Table of Contents
3.6
Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.7
Input/Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7.1
3.7.2
3.7.3
Chapter 4
Auto Wakeup Module (AWU)
4.1
4.2
4.3
4.4
4.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.6
Input/Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port A I/O Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.6.1
4.6.2
4.6.3
Chapter 5
Configuration Register (CONFIG)
5.1
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Chapter 6
Computer Operating Properly (COP)
6.1
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.4
6.5
6.6
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.7
6.7.1
6.7.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.8
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
MC68HLC908QY/QT Family Data Sheet, Rev. 3
8
Freescale Semiconductor
Chapter 7
Central Processor Unit (CPU)
7.1
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.5
7.5.1
7.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.6
7.7
7.8
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 8
External Interrupt (IRQ)
8.1
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3
8.3.1
8.3.2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.5
8.5.1
8.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.6
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.7
8.7.1
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
IRQ Input Pins (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.8
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 9
Keyboard Interrupt Module (KBI)
9.1
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3
9.3.1
9.3.2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Keyboard Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.4
9.5
9.6
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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9.7
Input/Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.7.1
9.7.2
Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.3.1
10.3.2
10.3.3
10.3.4
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.6.1
10.6.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Chapter 11
Oscillator Module (OSC)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.3.1
Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Internal to External Clock Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.3.1.1
11.3.1.2
11.3.2
11.3.3
11.3.4
11.4 Oscillator Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.4.7
11.4.8
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Internal Oscillator Clock (INTCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Oscillator Out 2 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Oscillator Out (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.5.1
11.5.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.7 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.8 Input/Output (I/O) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.8.1
11.8.2
Oscillator Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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Input/Output Ports (PORTS)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.2 Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.2.1
12.2.2
12.2.3
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3 Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.3.1
12.3.2
12.3.3
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 13
System Integration Module (SIM)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.3 SIM Bus Clock Control and Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.3.1
13.3.2
13.3.3
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.4.1
13.4.2
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.4.2.1
13.4.2.2
13.4.2.3
13.4.2.4
13.4.2.5
13.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.5.1
13.5.2
13.5.3
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.6.1.1
13.6.1.2
13.6.2
13.6.2.1
13.6.2.2
13.6.2.3
13.6.3
13.6.4
13.6.5
13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.7.1
13.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
13.8.1
13.8.2
SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Chapter 14
Timer Interface Module (TIM)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.4.1
14.4.2
14.4.3
14.4.3.1
14.4.3.2
14.4.4
14.4.4.1
14.4.4.2
14.4.4.3
TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.8 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.8.1
14.8.2
TIM Clock Pin (PTA2/TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.9 Input/Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.9.1
14.9.2
14.9.3
14.9.4
14.9.5
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Chapter 15
Development Support
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15.2.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Break Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
15.2.1.1
15.2.1.2
15.2.1.3
15.2.2
15.2.2.1
15.2.2.2
15.2.2.3
15.2.2.4
15.2.2.5
15.2.3
MC68HLC908QY/QT Family Data Sheet, Rev. 3
12
Freescale Semiconductor
15.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
15.3.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Normal Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
15.3.1.1
15.3.1.2
15.3.1.3
15.3.1.4
15.3.1.5
15.3.1.6
15.3.1.7
15.3.2
Chapter 16
Electrical Specifications
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
16.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
16.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
16.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
16.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
16.6 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
16.7 Typical 3.0-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
16.8 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
16.9 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
16.10 Analog-to-Digital (ADC) Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16.10.1
16.10.2
ADC Electrical Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
ADC Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16.11 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.12 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Chapter 17
Ordering Information and Mechanical Specifications
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
17.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
17.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
13
Table of Contents
MC68HLC908QY/QT Family Data Sheet, Rev. 3
14
Freescale Semiconductor
Chapter 1
General Description
1.1 Introduction
The MC68HLC908QY4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). The M68HC08 Family is a Complex Instruction Set Computer (CISC) with
a Von Neumann architecture. All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
0.4
Table 1-1. Summary of Device Variations
FLASH
Memory Size
Analog-to-Digital
Converter
Pin
Count
Device
MC68HLC908QT1
MC68HLC908QT2
MC68HLC908QT4
MC68HLC908QY1
MC68HLC908QY2
MC68HLC908QY4
1536 bytes
1536 bytes
4096 bytes
1536 bytes
1536 bytes
4096 bytes
—
8 pins
8 pins
4 ch, 8 bit
4 ch, 8 bit
—
8 pins
16 pins
16 pins
16 pins
4 ch, 8 bit
4 ch, 8 bit
1.2 Features
Features include:
•
•
•
•
•
High-performance M68HC08 CPU core
Fully upward-compatible object code with M68HC05 Family
Operating voltage range of 2.2 V to 3.6 V
2-MHz internal bus operation
Trimmable internal oscillator
–
–
–
1.0 MHz internal bus operation
8-bit trim capability allows 0.4% accuracy(1)
25% untrimmed
•
•
Auto wakeup from STOP capability
Configuration (CONFIG) register for MCU configuration options, including:
–
Low-voltage inhibit (LVI) trip point
•
•
In-system FLASH programming
FLASH security(2)
1. The oscillator frequency is guaranteed to 5% over temperature and voltage range after trimming.
2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
15
General Description
•
On-chip in-application programmable FLASH memory (with internal program/erase voltage
generation)
–
–
MC68HLC908QY4 and MC68HLC908QT4 — 4096 bytes
MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, and MC68HLC908QT1— 1536
bytes
•
•
•
128 bytes of on-chip random-access memory (RAM)
2-channel, 16-bit timer interface module (TIM)
4-channel, 8-bit analog-to-digital converter (ADC) on MC68HLC908QY2, MC68HLC908QY4,
MC68HLC908QT2, and MC68HLC908QT4
•
5 or 13 bidirectional input/output (I/O) lines and one input only:
–
–
–
–
–
–
–
Six shared with keyboard interrupt function and ADC
Two shared with timer channels
One shared with external interrupt (IRQ)
Eight extra I/O lines on 16-pin package only
High current sink/source capability on all port pins
Selectable pullups on all ports, selectable on an individual bit basis
Three-state ability on all port pins
•
•
6-bit keyboard interrupt with wakeup feature (KBI)
Low-voltage inhibit (LVI) module features:
–
Software selectable trip point in CONFIG register
•
System protection features:
–
–
–
–
Computer operating properly (COP) watchdog
Low-voltage detection with optional reset
Illegal opcode detection with reset
Illegal address detection with reset
•
External asynchronous interrupt pin with internal pullup (IRQ) shared with general-purpose
input pin
•
•
•
•
•
•
Master asynchronous reset pin (RST) shared with general-purpose input/output (I/O) pin
Power-on reset
Internal pullups on IRQ and RST to reduce external components
Memory mapped I/O registers
Power saving stop and wait modes
MC68HLC908QY4, MC68HLC908QY2, and MC68HLC908QY1 are available in these packages:
–
–
–
16-pin plastic dual in-line package (PDIP)
16-pin small outline integrated circuit (SOIC) package
16-pin thin shrink small outline package (TSSOP)
•
MC68HLC908QT4, MC68HLC908QT2, and MC68HLC908QT1 are available in these packages:
–
–
–
8-pin PDIP
8-pin SOIC
8-pin dual flat no lead (DFN) package
MC68HLC908QY/QT Family Data Sheet, Rev. 3
16
Freescale Semiconductor
MCU Block Diagram
Features of the CPU08 include the following:
•
•
•
•
•
•
•
•
•
•
Enhanced HC05 programming model
Extensive loop control functions
16 addressing modes (eight more than the HC05)
16-bit index register and stack pointer
Memory-to-memory data transfers
Fast 8 × 8 multiply instruction
Fast 16/8 divide instruction
Binary-coded decimal (BCD) instructions
Optimization for controller applications
Efficient C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HLC908QY4.
1.4 Pin Assignments
The MC68HLC908QT4, MC68HLC908QT2, and MC68HLC908QT1 are available in 8-pin packages and
the MC68HLC908QY4, MC68HLC908QY2, and MC68HLC908QY1 in 16-pin packages. Figure 1-2
shows the pin assignment for these packages.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
17
General Description
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
BREAK
MODULE
POWER-ON RESET
MODULE
MC68HLC908QY4 AND MC68HLC908QT4
4096 BYTES
KEYBOARD INTERRUPT
MODULE
8-BIT ADC
MC68HLC908QY2, MC68HLC908QY1,
MC68HLC908QT2, AND MC68HLC908QT1:
1536 BYTES
16-BIT TIMER
MODULE
USER FLASH
128 BYTES RAM
COP
MODULE
VDD
VSS
POWER SUPPLY
MONITOR ROM
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in
12.1 Introduction)
ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1
Figure 1-1. Block Diagram
MC68HLC908QY/QT Family Data Sheet, Rev. 3
18
Freescale Semiconductor
Pin Assignments
VSS
VSS
VDD
VDD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
PTA5/OSC1/KBI5
PTA4/OSC2/KBI4
PTA3/RST/KBI3
PTA5/OSC1/AD3/KBI5
PTA4/OSC2/AD2/KBI4
PTA3/RST/KBI3
PTA0/AD0/TCH0/KBI0
PTA0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
8-PIN ASSIGNMENT
MC68HC908QT1 PDIP/SOIC
8-PIN ASSIGNMENT
MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC
VDD
VDD
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PTB7
PTB6
PTB7
PTB6
PTB0
PTB0
PTB1
PTB1
PTA5/OSC1/AD3/KBI5
PTA4/OSC2/AD2/KBI4
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA5/OSC1/KBI5
PTA4/OSC2/KBI4
PTA0/TCH0/KBI0
PTA1/TCH1/KBI1
PTB5
PTB4
PTB5
PTB4
PTB2
PTB2
PTB3
PTB3
PTA2/IRQ/KBI2/TCLK
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTA3/RST/KBI3
16-PIN ASSIGNMENT
MC68HC908QY1 PDIP/SOIC
16-PIN ASSIGNMENT
MC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC
PTA0/TCH0/KBI0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PTA1/TCH1/KBI1
PTB2
PTB3
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTB4
PTA0/AD0/TCH0/KBI0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PTA1/AD1/TCH1/KBI1
PTB2
PTB3
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTB4
PTB1
PTB0
VSS
PTB1
PTB0
VSS
VDD
VDD
PTB7
PTB6
PTA5/OSC1/KBI5
PTB7
PTB6
PTA5/OSC1/AD3/KBI5
PTB5
PTA4/OSC2/KBI4
PTB5
PTA4/OSC2/AD2/KBI4
16-PIN ASSIGNMENT
MC68HC908QY1 TSSOP
16-PIN ASSIGNMENT
MC68HC908QY2 AND MC68HC908QY4 TSSOP
PTA0/TCH0/KBI0
1
8
PTA1/TCH1/KBI1
PTA0/AD0/TCH0/KBI0
1
8
PTA1/AD1/TCH1/KBI1
VSS
VDD
2
3
7
6
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
VSS
VDD
2
3
7
6
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTA5/OSC1/KB15
4
5
PTA4/OSC2/KBI4
PTA5//OSC1/AD3/KB15
4
5
PTA4/OSC2/AD2/KBI4
8-PIN ASSIGNMENT
MC68HC908QT1 DFN
8-PIN ASSIGNMENT
MC68HC908QT2 AND MC68HC908QT4 DFN
Figure 1-2. MCU Pin Assignments
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
19
General Description
1.5 Pin Functions
Table 1-2 provides a description of the pin functions.
Table 1-2. Pin Functions
Pin
Name
Description
Input/Output
VDD
VSS
Power supply
Power
Power supply ground
Power
Input/Output
Input
PTA0 — General purpose I/O port
AD0 — A/D channel 0 input
TCH0 — Timer Channel 0 I/O
KBI0 — Keyboard interrupt input 0
PTA1 — General purpose I/O port
AD1 — A/D channel 1 input
TCH1 — Timer Channel 1 I/O
KBI1 — Keyboard interrupt input 1
PTA0
PTA1
Input/Output
Input
Input/Output
Input
Input/Output
Input
PTA2 — General purpose input-only port
IRQ — External interrupt with programmable pullup and Schmitt trigger input
KBI2 — Keyboard interrupt input 2
Input
Input
PTA2
PTA3
Input
TCLK — Timer clock input
Input
PTA3 — General purpose I/O port
Input/Output
Input
RST — Reset input, active low with internal pullup and Schmitt trigger
KBI3 — Keyboard interrupt input 3
Input
PTA4 — General purpose I/O port
Input/Output
OSC2 —XTAL oscillator output (XTAL option only)
RC or internal oscillator output (OSC2EN = 1 in PTAPUE register)
Output
Output
PTA4
AD2 — A/D channel 2 input
Input
Input
KBI4 — Keyboard interrupt input 4
PTA5 — General purpose I/O port
OSC1 —XTAL, RC, or external oscillator input
AD3 — A/D channel 3 input
Input/Output
Input
PTA5
Input
KBI5 — Keyboard interrupt input 5
8 general-purpose I/O ports
Input
PTB[0:7](1)
Input/Output
1. The PTB pins are not available on the 8-pin packages (see note in 12.1 Introduction).
MC68HLC908QY/QT Family Data Sheet, Rev. 3
20
Freescale Semiconductor
Pin Function Priority
1.6 Pin Function Priority
Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin.
NOTE
Upon reset all pins come up as input ports regardless of the priority table.
Table 1-3. Function Priority in Shared Pins
Pin Name
PTA0
Highest-to-Lowest Priority Sequence
AD0 → TCH0 → KBI0 → PTA0
PTA1
AD1 →TCH1 → KBI1 → PTA1
IRQ → KBI2 → TCLK → PTA2
RST → KBI3 → PTA3
PTA2
PTA3
PTA4
OSC2 → AD2 → KBI4 → PTA4
OSC1 → AD3 → KBI5 → PTA5
PTA5
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
21
General Description
MC68HLC908QY/QT Family Data Sheet, Rev. 3
22
Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown
in Figure 2-1, includes:
•
•
4096 bytes of user FLASH for MC68HLC908QT4 and MC68HLC908QY4
1536 bytes of user FLASH for MC68HLC908QT2, MC68HLC908QT1, MC68HLC908QY2, and
MC68HLC908QY1
•
•
•
•
128 bytes of random access memory (RAM)
48 bytes of user-defined vectors, located in FLASH
416 bytes of monitor read-only memory (ROM)
1536 bytes of FLASH program and erase routines, located in ROM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can have unpredictable effects on MCU operation. In Figure 2-1
and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1 and in
register figures in this document, reserved locations are marked with the word Reserved or with the
letter R.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
23
Memory
$0000
↓
I/O REGISTERS
64 BYTES
$003F
$0040
↓
RESERVED(1)
64 BYTES
Note 1.
Attempts to execute code from addresses in this
$007F
$0080
↓
range will generate an illegal address reset.
RAM
128 BYTES
$00FF
$0100
↓
UNIMPLEMENTED(1)
9984 BYTES
$27FF
$2800
↓
AUXILIARY ROM
1536 BYTES
$2DFF
$2E00
↓
$EDFF
$2E00
↓
UNIMPLEMENTED(1)
49152 BYTES
UNIMPLEMENTED
51712 BYTES
$F7FF
$EE00
↓
$FDFF
FLASH MEMORY
MC68HLC908QT4 AND MC68HLC908QY4
4096 BYTES
$F800
↓
FLASH MEMORY
1536 BYTES
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
BREAK STATUS REGISTER (BSR)
RESET STATUS REGISTER (SRSR)
MC68HLC908QT1, MC68HLC908QT2,
MC68HLC908QY1, and MC68HLC908QY2
Memory Map
BREAK AUXILIARY REGISTER (BRKAR)
BREAK FLAG CONTROL REGISTER (BFCR)
INTERRUPT STATUS REGISTER 1 (INT1)
INTERRUPT STATUS REGISTER 2 (INT2)
INTERRUPT STATUS REGISTER 3 (INT3)
RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR)
FLASH CONTROL REGISTER (FLCR)
BREAK ADDRESS HIGH REGISTER (BRKH)
BREAK ADDRESS LOW REGISTER (BRKL)
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
LVISR
$FE0D
↓
$FE0F
RESERVED FOR FLASH TEST
3 BYTES
$FE10
↓
$FFAF
MONITOR ROM 416 BYTES
$FFB0
↓
$FFBD
FLASH
14 BYTES
$FFBE
$FFBF
$FFC0
FLASH BLOCK PROTECT REGISTER (FLBPR)
RESERVED FLASH
INTERNAL OSCILLATOR TRIM VALUE
$FFC1
RESERVED FLASH
$FFC2
↓
$FFCF
FLASH
14 BYTES
$FFD0
↓
$FFFF
USER VECTORS
48 BYTES
Figure 2-1. Memory Map
MC68HLC908QY/QT Family Data Sheet, Rev. 3
24
Freescale Semiconductor
Input/Output (I/O) Section
2.4 Input/Output (I/O) Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Additional I/O registers have these addresses:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
$FE00 — Break status register, BSR
$FE01 — Reset status register, SRSR
$FE02 — Break auxiliary register, BRKAR
$FE03 — Break flag control register, BFCR
$FE04 — Interrupt status register 1, INT1
$FE05 — Interrupt status register 2, INT2
$FE06 — Interrupt status register 3, INT3
$FE07 — Reserved
$FE08 — FLASH control register, FLCR
$FE09 — Break address register high, BRKH
$FE0A — Break address register low, BRKL
$FE0B — Break status and control register, BRKSCR
$FE0C — LVI status register, LVISR
$FE0D — Reserved
$FFBE — FLASH block protect register, FLBPR
$FFC0 — Internal OSC trim value — Optional
$FFFF — COP control register, COPCTL
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AWUL
PTA2
Port A Data Register
R
PTA5
PTA4
PTA3
PTA1
PTA0
$0000
(PTA) Write:
See page 98.
Reset:
Read:
Unaffected by reset
PTB4 PTB3
Unaffected by reset
Port B Data Register
PTB7
PTB6
PTB5
PTB2
PTB1
PTB0
$0001
$0002
$0003
(PTB) Write:
See page 100.
Reset:
Unimplemented
Unimplemented
Read:
0
0
Data Direction Register A
R
0
R
0
DDRA5
0
DDRA4
DDRA3
DDRA1
0
DDRA0
0
$0004
(DDRA) Write:
See page 98.
Reset:
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 6)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
25
Memory
Addr.
Register Name
Bit 7
DDRB7
0
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Data Direction Register B
$0005
(DDRB) Write:
See page 101.
Reset:
$0006
↓
Unimplemented
$000A
Read:
0
0
Port A Input Pullup Enable
OSC2EN
0
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
$000B
$000C
Register (PTAPUE) Write:
See page 99.
Reset:
0
0
0
0
0
0
Read:
Port B Input Pullup Enable
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0
Register (PTBPUE) Write:
See page 102.
Reset:
0
0
0
0
0
0
0
0
$000D
↓
$0019
Unimplemented
Read:
Keyboard Status and
Control Register (KBSCR) Write:
0
0
0
0
KEYF
0
ACKK
0
IMASKK
MODEK
$001A
See page 83.
Reset:
0
0
0
AWUIE
0
0
KBIE5
0
0
KBIE4
0
0
KBIE3
0
0
KBIE1
0
0
KBIE0
0
Read:
Keyboard Interrupt
Enable Register (KBIER) Write:
KBIE2
0
$001B
$001C
See page 84.
Reset:
0
0
Unimplemented
Read:
IRQ Status and Control
Register (INTSCR) Write:
0
0
0
0
IRQF
0
0
ACK
0
IMASK
MODE
0
$001D
$001E
See page 77.
Reset:
0
IRQPUD
0
0
IRQEN
0
0
R
0
0
R
0
Read:
Configuration Register 2
OSCOPT1 OSCOPT0
RSTEN
0(2)
R
0
(CONFIG2)(1) Write:
See page 53.
Reset:
0
0
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 6)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
26
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
COPRS
0
6
5
4
3
2
SSREC
0
1
STOP
0
Bit 0
COPD
0
Read:
Configuration Register 1
LVISTOP LVIRSTD LVIPWRD LVDLVR
0(2)
$001F
(CONFIG1)(1) Write:
See page 54.
Reset:
0
0
0
1. One-time writable register after each reset. Exceptions are LVDLVR and LVIRSTD bits.
2. LVDLVR reset to 0 by a power-on reset (POR) only.
Read:
TOF
0
0
0
TIM Status and Control
TOIE
TSTOP
PS2
PS1
PS0
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
Register (TSC) Write:
See page 127.
Reset:
TRST
0
0
0
1
0
0
0
0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TIM Counter Register High
(TCNTH) Write:
See page 129.
Reset:
Read:
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIM Counter Register Low
(TCNTL) Write:
See page 129.
Reset:
Read:
0
Bit 15
1
0
Bit 14
1
0
Bit 13
1
0
Bit 12
1
0
Bit 11
1
0
Bit 10
1
0
Bit 9
1
0
Bit 8
1
TIM Counter Modulo
Register High (TMODH) Write:
See page 129.
Reset:
Read:
TIM Counter Modulo
Register Low (TMODL) Write:
Bit 7
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
1
See page 129.
Reset:
1
CH0F
0
Read:
TIM Channel 0 Status and
Control Register (TSC0) Write:
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
TOV0
0
CH0MAX
0
See page 130.
Reset:
0
Read:
TIM Channel 0
Register High (TCH0H) Write:
Bit 15
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
See page 133.
Reset:
Indeterminate after reset
Bit 4 Bit 3
Indeterminate after reset
Read:
TIM Channel 0
Register Low (TCH0L) Write:
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
See page 133.
Reset:
Read:
TIM Channel 1 Status and
Control Register (TSC1) Write:
CH1F
0
0
CH1IE
0
MS1A
ELS1B
ELS1A
0
TOV1
0
CH1MAX
0
0
0
See page 130.
Reset:
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
27
Memory
Addr.
Register Name
TIM Channel 1
Register High (TCH1H) Write:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
$0029
$002A
See page 133.
Reset:
Indeterminate after reset
Bit 4 Bit 3
Indeterminate after reset
Read:
TIM Channel 1
Register Low (TCH1L) Write:
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
See page 133.
Reset:
$002B
↓
Unimplemented
$0035
Read:
ECGST
0
Oscillator Status Register
R
0
R
0
R
0
R
0
R
0
R
0
ECGON
0
$0036
$0037
(OSCSTAT) Write:
See page 95.
Reset:
Unimplemented Read:
Read:
Write:
Reset:
Oscillator Trim Register
(OSCTRIM)
See page 96.
TRIM7
1
TRIM6
0
TRIM5
0
TRIM4
0
TRIM3
0
TRIM2
0
TRIM1
0
TRIM0
0
$0038
$0039
↓
Unimplemented
$003B
Read: COCO
ADC Status and Control
Register (ADSCR) Write:
AIEN
0
ADCO
0
CH4
1
CH3
1
CH2
1
CH1
1
CH0
1
$003C
$003D
R
0
See page 43.
Reset:
Unimplemented
Read:
ADC Data Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
$003E
$003F
(ADR) Write:
See page 44.
Reset:
Indeterminate after reset
Read:
0
0
0
0
0
0
0
0
ADC Input Clock Register
ADIV2
0
ADIV1
0
ADIV0
0
(ADICLK) Write:
See page 45.
Reset:
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 6)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
28
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
SBSW
See note 1
0
Bit 0
Read:
Break Status Register
R
R
R
R
R
R
R
$FE00
(BSR) Write:
See page 139.
Reset:
1. Writing a 0 clears SBSW.
Read:
SIM Reset Status Register
(SRSR) Write:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
$FE01
$FE02
$FE03
$FE04
$FE05
See page 117.
POR:
Read:
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BDCOP
Break Auxiliary
Register (BRKAR) Write:
See page 139.
Reset:
0
0
0
0
0
0
0
0
Read:
Break Flag Control
Register (BFCR) Write:
BCFE
R
R
R
R
R
R
R
See page 139.
Reset:
0
0
Read:
IF5
R
0
IF4
R
0
IF3
R
0
0
R
0
IF1
R
0
0
R
0
0
R
Interrupt Status Register 1
(INT1) Write:
R
See page 77.
Reset:
Read:
0
0
IF14
R
0
0
0
0
0
0
0
Interrupt Status Register 2
(INT2) Write:
R
0
R
0
R
0
R
0
R
0
R
0
R
See page 77.
Reset:
Read:
0
0
0
0
0
0
0
0
0
IF15
R
Interrupt Status Register 3
$FE06
$FE07
(INT3) Write:
See page 77.
Reset:
R
R
0
R
0
R
0
R
0
R
0
R
0
0
0
Reserved
R
R
R
R
R
R
R
R
Read:
0
0
0
0
FLASH Control Register
HVEN
0
MASS
ERASE
PGM
0
$FE08
$FE09
$FE0A
(FLCR) Write:
See page 32.
Reset:
Read:
0
Bit 15
0
0
Bit 14
0
0
Bit 13
0
0
Bit 12
0
0
Bit 10
0
0
Bit 9
0
Break Address High
Bit 11
0
Bit 8
0
Register (BRKH) Write:
See page 138.
Reset:
Read:
Break Address low
Register (BRKL) Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
0
Bit 1
0
Bit 0
0
See page 138.
Reset:
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 6)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
29
Memory
Addr.
Register Name
Bit 7
BRKE
0
6
5
4
3
2
1
Bit 0
Read:
Break Status and Control
Register (BRKSCR) Write:
0
0
0
0
0
0
BRKA
$FE0B
$FE0C
See page 138.
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
Read: LVIOUT
Write:
R
LVI Status Register (LVISR)
See page 87.
Reset:
0
0
0
0
0
0
0
0
$FE0D
↓
$FE0F
Reserved for FLASH Test
R
R
R
R
R
R
R
R
Read:
FLASH Block Protect
Register (FLBPR) Write:
BPR7
R
BPR6
R
BPR5
R
BPR4
BPR3
BPR2
R
BPR1
R
BPR0
R
$FFBE
$FFBF
See page 37.
Reset:
Unaffected by reset
Reserved
R
R
Read:
TRIM7
R
TRIM6
R
TRIM5
R
TRIM4
TRIM3
TRIM2
R
TRIM1
R
TRIM0
R
Internal Oscillator Trim Value
(Optional)
$FFC0
$FFC1
Write:
Reset:
Unaffected by reset
Reserved
R
R
Read:
LOW BYTE OF RESET VECTOR
WRITING CLEARS COP COUNTER (ANY VALUE)
Unaffected by reset
COP Control Register
$FFFF
(COPCTL) Write:
See page 59.
Reset:
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 6)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
30
Freescale Semiconductor
Random-Access Memory (RAM)
.
Table 2-1. Vector Addresses
Vector Priority
Vector
Address
Vector
$FFDE
$FFDF
$FFE0
$FFE1
ADC conversion complete vector (high)
ADC conversion complete vector (low)
Keyboard vector (high)
Lowest
IF15
IF14
Keyboard vector (low)
IF13
↓
IF6
—
Not used
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
—
TIM overflow vector (high)
TIM overflow vector (low)
TIM Channel 1 vector (high)
TIM Channel 1 vector (low)
TIM Channel 0 vector (high)
TIM Channel 0 vector (low)
Not used
IF5
IF4
IF3
IF2
IF1
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
IRQ vector (high)
IRQ vector (low)
SWI vector (high)
—
—
SWI vector (low)
Reset vector (high)
Highest
Reset vector (low)
2.5 Random-Access Memory (RAM)
The 128 bytes of random-access memory (RAM) are located at addresses $0080–$00FF. The location
of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the
64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the
contents of the CPU registers.
NOTE
For M6805, M146805, and M68HC05 compatibility, the H register is not
stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
31
Memory
2.6 FLASH Memory (FLASH)
This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be
read, programmed, and erased from a single external supply. The program and erase operations are
enabled through the use of an internal charge pump.
The FLASH memory consists of an array of 4096 or 1536 bytes with an additional 48 bytes for user
vectors. The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of
FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase
operations are facilitated through control bits in the FLASH control register (FLCR). Details for these
operations appear later in this section. The address ranges for the user memory and vectors are:
•
•
$EE00 – $FDFF; user memory, 4096 bytes: MC68HLC908QY4 and MC68HLC908QT4
$F800 – $FDFF; user memory, 1536 bytes: MC68HLC908QY2, MC68HLC908QT2,
MC68HLC908QY1 and MC68HLC908QT1
•
$FFD0 – $FFFF; user interrupt vectors, 48 bytes.
NOTE
An erased bit reads as a 1 and a programmed bit reads as a 0. A security
feature prevents viewing of the FLASH contents.(1)
2.6.1 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
Address:
$FE08
Bit 7
0
6
0
5
0
4
0
3
HVEN
0
2
MASS
0
1
ERASE
0
Bit 0
PGM
0
Read:
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the memory for either program or
erase operation. It can only be set if either PGM =1 or ERASE =1 and the proper sequence for
program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
32
Freescale Semiconductor
FLASH Memory (FLASH)
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation.
1 = Mass Erase operation selected
0 = Mass Erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
2.6.2 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes
starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 48-byte user interrupt vectors area also
forms a page. Any FLASH memory page can be erased alone.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of the block to be erased.
4. Wait for a time, tNVS (minimum 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tErase (minimum 1 ms or 4 ms).
7. Clear the ERASE bit.
8. Wait for a time, tNVH (minimum 5 µs).
9. Clear the HVEN bit.
10. After time, tRCV (typical 1 µs), the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
CAUTION
A page erase of the vector page will erase the internal oscillator trim value
at $FFC0.
In applications that require more than 1000 program/erase cycles, use the 4 ms page erase specification
to get improved long-term reliability. Any application can use this 4 ms page erase specification. However,
in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and
speed is important, use the 1 ms page erase specification to get a shorter cycle time.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
33
Memory
2.6.3 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory to read as a 1:
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address(1) within the FLASH memory address range.
4. Wait for a time, tNVS (minimum 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tMErase (minimum 4 ms).
7. Clear the ERASE and MASS bits.
NOTE
Mass erase is disabled whenever any block is protected (FLBPR does not
equal $FF).
8. Wait for a time, tNVH (minimum 100 µs).
9. Clear the HVEN bit.
10. After time, tRCV (typical 1 µs), the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
CAUTION
A mass erase will erase the internal oscillator trim value at $FFC0.
2.6.4 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes
starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, or $XXE0. Use the
following step-by-step procedure to program a row of FLASH memory
Figure 2-4 shows a flowchart of the programming algorithm.
NOTE
Only bytes which are currently $FF may be programmed.
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range desired.
4. Wait for a time, tNVS (minimum 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tPGS (minimum 5 µs).
7. Write data to the FLASH address being programmed(2).
1. When in monitor mode, with security sequence failed (see 15.3.2 Security), write to the FLASH block protect register instead
of any FLASH address.
2. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM
bit, must not exceed the maximum programming time, tPROG maximum.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
34
Freescale Semiconductor
FLASH Memory (FLASH)
8. Wait for time, tPROG (minimum 30 µs).
9. Repeat step 7 and 8 until all desired bytes within the row are programmed.
10. Clear the PGM bit(1).
11. Wait for time, tNVH (minimum 5 µs).
12. Clear the HVEN bit.
13. After time, tRCV (typical 1 µs), the memory can be accessed in read mode again.
NOTE
The COP register at location $FFFF should not be written between steps
5-12, when the HVEN bit is set. Since this register is located at a valid
FLASH address, unpredictable behavior may occur if this location is written
while HVEN is set.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum, see 16.12
Memory Characteristics.
2.6.5 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made to protect blocks of memory from unintentional erase or program operations
due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be protected. The range of the
protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory
($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM
operations.
NOTE
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
When the FLBPR is programmed with all 0s, the entire memory is protected from being programmed and
erased. When all the bits are erased (all 1s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are
shown in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than
$FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass
erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be
erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also
allows entry from reset into the monitor mode.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
35
Memory
Algorithm for Programming
1
2
3
SET PGM BIT
a Row (32 Bytes) of FLASH Memory
READ THE FLASH BLOCK PROTECT REGISTER
WRITE ANY DATA TO ANY FLASH ADDRESS
WITHIN THE ROW ADDRESS RANGE DESIRED
4
5
6
WAIT FOR A TIME, tNVS
SET HVEN BIT
WAIT FOR A TIME, tPGS
7
8
WRITE DATA TO THE FLASH ADDRESS
TO BE PROGRAMMED
WAIT FOR A TIME, tPROG
COMPLETED
Y
PROGRAMMING
THIS ROW?
9
N
10
CLEAR PGM BIT
WAIT FOR A TIME, tNVH
CLEAR HVEN BIT
11
12
13
NOTES:
The time between each FLASH address change (step 7 to step 7),
or the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming
time, tPROG max.
WAIT FOR A TIME, tRCV
END OF PROGRAMMING
This row program algorithm assumes the row/s
to be programmed are initially erased.
Figure 2-4. FLASH Programming Flowchart
MC68HLC908QY/QT Family Data Sheet, Rev. 3
36
Freescale Semiconductor
FLASH Memory (FLASH)
2.6.6 FLASH Block Protect Register
The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can
only be written during a programming sequence of the FLASH memory. The value in this register
determines the starting address of the protected range within the FLASH memory.
Address: $FFBE
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
Unaffected by reset. Initial value from factory is 1.
Write to this register is by a programming sequence to the FLASH memory.
Figure 2-5. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Protection Register Bits [7:0]
These eight bits in FLBPR represent bits [13:6] of a 16-bit memory address. Bits [15:14] are 1s and
bits [5:0] are 0s.
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 within the FLASH
memory. See Figure 2-6 and Table 2-2.
16-BIT MEMORY ADDRESS
FLBPR VALUE
START ADDRESS OF
FLASH BLOCK PROTECT
1
1
0
0
0
0
0
0
Figure 2-6. FLASH Block Protect Start Address
Table 2-2. Examples of Protect Start Address
BPR[7:0]
Start of Address of Protect Range
The entire FLASH memory is protected.
$EE40 (1110 1110 0100 0000)
$EE80 (1110 1110 1000 0000)
$EEC0 (1110 1110 1100 0000)
$EF00 (1110 1111 0000 0000)
and so on...
$00–$B8
$B9 (1011 1001)
$BA (1011 1010)
$BB (1011 1011)
$BC (1011 1100)
$DE (1101 1110)
$DF (1101 1111)
$F780 (1111 0111 1000 0000)
$F7C0 (1111 0111 1100 0000)
$FF80 (1111 1111 1000 0000)
$FE (1111 1110)
FLBPR, OSCTRIM, and vectors are protected
$FF
The entire FLASH memory is not protected.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
37
Memory
2.6.7 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the
FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase operation on the
FLASH, or the operation will discontinue and the FLASH will be on standby mode.
2.6.8 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the
FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase operation on the
FLASH, or the operation will discontinue and the FLASH will be on standby mode
NOTE
Standby mode is the power-saving mode of the FLASH module in which all
internal control signals to the FLASH are inactive and the current
consumption of the FLASH is at a minimum.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
38
Freescale Semiconductor
Chapter 3
Analog-to-Digital Converter (ADC)
3.1 Introduction
This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 4-channel analog-to-
digital converter. The ADC module is only available on the MC68HLC908QY2, MC68HLC908QT2,
MC68HLC908QY4, and MC68HLC908QT4.
3.2 Features
Features of the ADC module include:
•
•
•
•
•
•
4 channels with multiplexed input
Linear successive approximation with monotonicity
8-bit resolution
Single or continuous conversion
Conversion complete flag or conversion complete interrupt
Selectable ADC clock frequency
3.3 Functional Description
Four ADC channels are available for sampling external sources at pins PTA0, PTA1, PTA4, and PTA5.
An analog multiplexer allows the single ADC converter to select one of the four ADC channels as an ADC
voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters.
The ADC resolution is eight bits. When the conversion is completed, ADC puts the result in the ADC data
register and sets a flag or generates an interrupt.
Figure 3-2 shows a block diagram of the ADC.
3.3.1 ADC Port I/O Pins
PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are shared with the ADC channels. The
channel select bits (ADC status and control register (ADSCR), $003C), define which ADC channel/port
pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the
ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as
general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect
on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a 0
if the corresponding DDR bit is at 0. If the DDR bit is 1, the value in the port data latch is read.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
39
Analog-to-Digital Converter (ADC)
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
BREAK
MODULE
POWER-ON RESET
MODULE
MC68HLC908QY4 AND MC68HLC908QT4
4096 BYTES
KEYBOARD INTERRUPT
MODULE
8-BIT ADC
MC68HLC908QY2, MC68HLC908QY1,
MC68HLC908QT2, AND MC68HLC908QT1:
1536 BYTES
16-BIT TIMER
MODULE
USER FLASH
128 BYTES RAM
COP
MODULE
VDD
VSS
POWER SUPPLY
MONITOR ROM
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4( see note in
12.1 Introduction)
ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1
Figure 3-1. Block Diagram Highlighting ADC Block and Pins
MC68HLC908QY/QT Family Data Sheet, Rev. 3
40
Freescale Semiconductor
Functional Description
INTERNAL
DATA BUS
READ DDRA
WRITE DDRA
DISABLE
DDRAx
PTAx
RESET
WRITE PTA
READ PTA
ADCx
DISABLE
ADC CHANNEL x
ADC DATA REGISTER
ADC VOLTAGE IN
ADCVIN
CONVERSION
COMPLETE
CHANNEL
SELECT
INTERRUPT
LOGIC
CH[4:0]
ADC
(1 OF 4 CHANNELS)
ADC CLOCK
AIEN
COCO
CLOCK
GENERATOR
BUS CLOCK
ADIV[2:0]
Figure 3-2. ADC Block Diagram
3.3.2 Voltage Conversion
When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input
voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line
linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS.
NOTE
Input voltage should not exceed the analog supply voltages.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
41
Analog-to-Digital Converter (ADC)
3.3.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on the
first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC internal
clock is selected to run at 1 MHz, then one conversion will take 16 µs to complete. With a 1-MHz ADC
internal clock the maximum sample rate is 62.5 kHz.
16 ADC Clock Cycles
Conversion Time =
ADC Clock Frequency
Number of Bus Cycles = Conversion Time × Bus Frequency
3.3.4 Continuous Conversion
In the continuous conversion mode (ADCO = 1), the ADC continuously converts the selected channel
filling the ADC data register (ADR) with new data after each conversion. Data from the previous
conversion will be overwritten whether that data has been read or not. Conversions will continue until the
ADCO bit is cleared. The COCO bit (ADSCR, $003C) is set after each conversion and will stay set until
the next read of the ADC data register.
When a conversion is in process and the ADSCR is written, the current conversion data should be
discarded to prevent an incorrect reading.
3.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a central processor unit (CPU)
interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit
is not used as a conversion complete flag when interrupts are enabled.
3.5 Low-Power Modes
The following subsections describe the ADC in low-power modes.
3.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the microcontroller unit (MCU) out of wait mode. If the ADC is not required to bring the MCU out
of wait mode, power down the ADC by setting the CH[4:0] bits in ADSCR to 1s before executing the WAIT
instruction.
3.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before using ADC data after exiting stop mode.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
42
Freescale Semiconductor
Input/Output Signals
3.6 Input/Output Signals
The ADC module has four channels that are shared with I/O port A.
ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC channels to the ADC
module.
3.7 Input/Output Registers
These I/O registers control and monitor ADC operation:
•
•
•
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC clock register (ADICLK)
3.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register (ADSCR). When a
conversion is in process and the ADSCR is written, the current conversion data should be discarded to
prevent an incorrect reading.
Address: $003C
Bit 7
6
5
ADCO
0
4
CH4
1
3
CH3
1
2
CH2
1
1
CH1
1
Bit 0
CH0
1
Read:
Write:
Reset:
COCO
AIEN
R
0
0
R
= Reserved
Figure 3-3. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion.
COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It
always reads as a 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1)
NOTE
The write function of the COCO bit is reserved. When writing to the ADSCR
register, always have a 0 in the COCO bit position.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when ADR is read or ADSCR is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update ADR at the end of each conversion.
Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
43
Analog-to-Digital Converter (ADC)
CH[4:0] — ADC Channel Select Bits
CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of the four ADC channels.
The five select bits are detailed in Table 3-1. Care should be taken when using a port pin as both an
analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to a 1.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Table 3-1. MUX Channel Select
ADC
CH4
CH3
CH2
CH1
CH0
Input Select
Channel
AD0
AD1
AD2
AD3
—
0
0
0
0
0
↓
1
1
1
0
0
0
0
0
↓
1
1
1
0
0
0
0
1
↓
0
0
1
0
0
1
1
0
↓
1
1
0
0
1
0
1
0
↓
0
1
0
PTA0
PTA1
PTA4
PTA5
Unused(1)
—
—
—
Reserved
Unused
—
(2)
1
1
1
0
1
—
VDDA
(2)
1
1
1
1
1
1
1
1
0
1
—
—
VSSA
ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be
unknown.
2. The voltage levels supplied from internal reference nodes, as specified in the
table, are used to verify the operation of the ADC converter both in
production test and for user applications.
3.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after reset
Figure 3-4. ADC Data Register (ADR)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
44
Freescale Semiconductor
Input/Output Registers
3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003F
Bit 7
ADIV2
0
6
ADIV1
0
5
ADIV0
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 3-5. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be
set according to the MCU operating voltage. Lower operating voltages will require lower ADC clock
frequencies for best accuracy. The analog input level should remain stable for the entire conversion
time (maximum = 17 ADC clock cycles).
Table 3-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
Bus clock ÷ 1
Bus clock ÷ 2
Bus clock ÷ 4
Bus clock ÷ 8
Bus clock ÷ 16
0
0
0
1
1
X
0
1
0
1
X
0
0
0
1
X = don’t care
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
45
Analog-to-Digital Converter (ADC)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
46
Freescale Semiconductor
Chapter 4
Auto Wakeup Module (AWU)
4.1 Introduction
This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during
stop mode to wake the part up without requiring an external signal. Figure 4-1 is a block diagram of the
AWU.
4.2 Features
Features of the auto wakeup module include:
•
One internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector
and keyboard interrupt mask bit
•
•
•
Exit from low-power stop mode without external signals
Selectable timeout periods
Dedicated low power internal oscillator separate from the main system clock sources
4.3 Functional Description
The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller
unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests,
with the difference that instead of a pin, the interrupt signal is generated by an internal logic.
Writing the AWUIE bit in the keyboard interrupt enable register enables or disables the auto wakeup
interrupt input (see Figure 4-1). A logic 1 applied to the AWUIREQ input with auto wakeup interrupt
request enabled, latches an auto wakeup interrupt request.
Auto wakeup latch, AWUL, can be read directly from the bit 6 position of port A data register (PTA). This
is a read-only bit which is occupying an empty bit position on PTA. No PTA associated registers, such as
PTA6 data direction or PTA6 pullup exist for this bit.
Entering stop mode will enable the auto wakeup generation logic. An internal RC oscillator (exclusive for
the auto wakeup feature) drives the wakeup request generator. Once the overflow count is reached in the
generator counter, a wakeup request, AWUIREQ, is latched and sent to the KBI logic. See Figure 4-1.
Wakeup interrupt requests will only be serviced if the associated interrupt enable bit, AWUIE, in KBIER
is set. The AWU shares the keyboard interrupt vector.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
47
Auto Wakeup Module (AWU)
COPRS (FROM CONFIG1)
VDD
AUTOWUGEN
TO PTA READ, BIT 6
AWUL
1 = DIV 29
D
E
Q
SHORT
0 = DIV 214
INT RC OSC
EN 32 kHz
OVERFLOW
AWUIREQ
R
CLK
RST
TO KBI INTERRUPT LOGIC (SEE
Figure 9-2. Keyboard Interrupt
Block Diagram)
CLRLOGIC
CLEAR
RESET
ACKK
(CGMXCLK)
BUSCLKX4
CLK
RST
RESET
ISTOP
RESET
AWUIE
Figure 4-1. Auto Wakeup Interrupt Request Generation Logic
The overflow count can be selected from two options defined by the COPRS bit in CONFIG1. This bit was
“borrowed” from the computer operating properly (COP) using the fact that the COP feature is idle (no
MCU clock available) in stop mode. The typical values of the periodic wakeup request are (at room
temperature):
•
•
COPRS = 0: 875 ms @ 3.0 V, 1.1 s @ 2.3 V
COPRS = 1: 22 ms @ 3.0 V, 27 ms @ 2.3 V
The auto wakeup RC oscillator is highly dependent on operating voltage and temperature. This feature is
not recommended for use as a time-keeping function.
The wakeup request is latched to allow the interrupt source identification. The latched value, AWUL, can
be read directly from the bit 6 position of PTA data register. This is a read-only bit which is occupying an
empty bit position on PTA. No PTA associated registers, such as PTA6 data, PTA6 direction, and PTA6
pullup exist for this bit. The latch can be cleared by writing to the ACKK bit in the KBSCR register. Reset
also clears the latch. AWUIE bit in KBI interrupt enable register (see Figure 4-1) has no effect on AWUL
reading.
The AWU oscillator and counters are inactive in normal operating mode and become active only upon
entering stop mode.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
48
Freescale Semiconductor
Wait Mode
4.4 Wait Mode
The AWU module remains inactive in wait mode.
4.5 Stop Mode
When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated
automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control
register enables keyboard interrupt requests to bring the MCU out of stop mode. The AWU counters start
from ‘0’ each time stop mode is entered.
4.6 Input/Output Registers
The AWU shares registers with the keyboard interrupt (KBI) module and the port A I/O module. The
following I/O registers control and monitor operation of the AWU:
•
•
•
Port A data register (PTA)
Keyboard interrupt status and control register (KBSCR)
Keyboard interrupt enable register (KBIER)
4.6.1 Port A I/O Register
The port A data register (PTA) contains a data latch for the state of the AWU interrupt request, in addition
to the data latches for port A.
Address: $0000
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
AWUL
PTA2
PTA5
PTA4
PTA3
PTA1
PTA0
0
0
Unaffected by reset
= Unimplemented
Figure 4-2. Port A Data Register (PTA)
AWUL — Auto Wakeup Latch
This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup
request signal is generated internally. There is no PTA6 port or any of the associated bits such as
PTA6 data direction or pullup bits.
1 = Auto wakeup interrupt request is pending
0 = Auto wakeup interrupt request is not pending
NOTE
PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature.
To see a description of these bits, see 12.2.1 Port A Data Register.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
49
Auto Wakeup Module (AWU)
4.6.2 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):
•
•
•
Flags keyboard/auto wakeup interrupt requests
Acknowledges keyboard/auto wakeup interrupt requests
Masks keyboard/auto wakeup interrupt requests
Address: $001A
Bit 7
0
6
0
5
0
4
0
3
2
1
IMASKK
0
Bit 0
MODEK
0
Read:
Write:
Reset:
KEYF
0
ACKK
0
0
0
0
0
0
= Unimplemented
Figure 4-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears
the KEYF bit.
1 = Keyboard/auto wakeup interrupt pending
0 = No keyboard/auto wakeup interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port A and auto
wakeup logic. ACKK always reads as 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating
interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit.
1 = Keyboard/auto wakeup interrupt requests masked
0 = Keyboard/auto wakeup interrupt requests not masked
NOTE
MODEK is not used in conjuction with the auto wakeup feature. To see a
description of this bit, see 9.7.1 Keyboard Status and Control Register.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
50
Freescale Semiconductor
Input/Output Registers
4.6.3 Keyboard Interrupt Enable Register
The keyboard interrupt enable register (KBIER) enables or disables the auto wakeup to operate as a
keyboard/auto wakeup interrupt input.
Address: $001B
Bit 7
0
6
AWUIE
0
5
KBIE5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
0
= Unimplemented
Figure 4-4. Keyboard Interrupt Enable Register (KBIER)
AWUIE — Auto Wakeup Interrupt Enable Bit
This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears
AWUIE.
1 = Auto wakeup enabled as interrupt input
0 = Auto wakeup not enabled as interrupt input
NOTE
KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature.
To see a description of these bits, see 9.7.2 Keyboard Interrupt Enable
Register.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
51
Auto Wakeup Module (AWU)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
52
Freescale Semiconductor
Chapter 5
Configuration Register (CONFIG)
5.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers
enable or disable the following options:
•
•
•
•
•
•
•
•
•
Stop mode recovery time (32 × BUSCLKX4 cycles or 4096 × BUSCLKX4 cycles)
STOP instruction
Computer operating properly module (COP)
COP reset period (COPRS): 8176 × BUSCLKX4 or 262,128 × BUSCLKX4
Low-voltage inhibit (LVI) enable and trip voltage selection
OSC option selection
IRQ pin
RST pin
Auto wakeup timeout period
5.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. Exceptions are bits LVDLVR and LVIRSTD which may be written at any
time. Most of the configuration register bits are cleared during reset. Since the various options affect the
operation of the microcontroller unit (MCU) it is recommended that this register be written immediately
after reset. The configuration registers are located at $001E and $001F, and may be read at anytime.
$001E
Address:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
POR:
IRQPUD
IRQEN
R
OSCOPT1 OSCOPT0
R
R
RSTEN
0
0
0
0
0
0
0
0
0
0
0
0
U
0
0
0
= Reserved
U = Unaffected
R
Figure 5-1. Configuration Register 2 (CONFIG2)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
53
Configuration Register (CONFIG)
IRQPUD — IRQ Pin Pullup Control Bit
1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ pin and VDD
IRQEN — IRQ Pin Function Selection Bit
1 = Interrupt request function active in pin
0 = Interrupt request function inactive in pin
OSCOPT1 and OSCOPT0 — Selection Bits for Oscillator Option
(0, 0) Internal oscillator
(0, 1) External oscillator
(1, 0) External RC oscillator
(1, 1) External XTAL oscillator
RSTEN — RST Pin Function Selection
1 = Reset function active in pin
0 = Reset function inactive in pin
NOTE
The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will
leave this bit unaffected.
$001F
Address:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
LVIRSTD
COPRS LVISTOP
LVIPWRD LVDLVR SSREC
STOP
COPD
Reset:
POR:
0
0
0
0
0
0
0
U
0
0
0
0
0
0
0
0
U = Unaffected
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS (Out of STOP Mode) — COP Reset Period Selection Bit
1 = COP reset short cycle = 8176 × BUSCLKX4
0 = COP reset long cycle = 262,128 × BUSCLKX4
COPRS (In STOP Mode) — Auto Wakeup Period Selection Bit
1 = Auto wakeup short cycle = 512 × INTRCOSC
0 = Auto wakeup long cycle = 16,384 × INTRCOSC
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. Unlike other configuration bits, the LVIRSTD
can be written at any time.
1 = LVI module resets disabled
0 = LVI module resets enabled
MC68HLC908QY/QT Family Data Sheet, Rev. 3
54
Freescale Semiconductor
Functional Description
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
1 = LVI module power disabled
0 = LVI module power enabled
LVDLVR — Low Voltage Detect or Low Voltage Reset Mode Bit
LVDLVR selects the trip voltage of the LVI module. LVD trip voltage can be used as a low voltage
warning, while LVR will commonly be used as a reset condition. Unlike other CONFIG bits, LVDLVR
can be written multiple times after reset.
1 = LVI trip voltage level set to LVD trip voltage
0 = LVI trip voltage level set to LVR trip voltage
NOTE
The LVDLVR bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096
BUSCLKX4 cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE
Exiting stop mode by an LVI reset will result in the long stop recovery.
The system stabilization time for power-on reset and long stop recovery (both 4096 BUSCLKX4
cycles) gives a delay longer than the LVI enable time for these startup scenarios. There is no period
where the MCU is not protected from a low-power condition. However, when using the short stop
recovery configuration option, the 32 BUSCLKX4 delay must be greater than the LVI’s turn on time to
avoid a period in startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
55
Configuration Register (CONFIG)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
56
Freescale Semiconductor
Chapter 6
Computer Operating Properly (COP)
6.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
configuration 1 (CONFIG1) register.
6.2 Functional Description
BUSCLKX4
RESET CIRCUIT
12-BIT SIM COUNTER
RESET STATUS REGISTER
STOP INSTRUCTION
INTERNAL RESET SOURCES
COPCTL WRITE
COP CLOCK
6-BIT COP COUNTER
COPEN (FROM SIM)
COP DISABLE (COPD FROM CONFIG1)
RESET
CLEAR
COP COUNTER
COPCTL WRITE
COP RATE SELECT
(COPRS FROM CONFIG1)
Figure 6-1. COP Block Diagram
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
57
Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
262,128 or 8176 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in
configuration register 1. With a 262,128 BUSCLKX4 cycle overflow option, the internal 4.0-MHz oscillator
gives a COP timeout period of 65.53 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 12–5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low (if the RSTEN bit is set in the CONFIG1 register) for 32 × BUSCLKX4
cycles and sets the COP bit in the reset status register (RSR). See 13.8.1 SIM Reset Status Register.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
6.3 I/O Signals
The following paragraphs describe the signals shown in Figure 6-1.
6.3.1 BUSCLKX4
BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the internal oscillator
frequency, crystal frequency, or the RC-oscillator frequency.
6.3.2 STOP Instruction
The STOP instruction clears the SIM counter.
6.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 6.4 COP Control Register) clears the COP
counter and clears stages 12–5 of the SIM counter. Reading the COP control register returns the low byte
of the reset vector.
6.3.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × BUSCLKX4 cycles after power
up.
6.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
6.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register 1
(CONFIG1). See Chapter 5 Configuration Register (CONFIG).
MC68HLC908QY/QT Family Data Sheet, Rev. 3
58
Freescale Semiconductor
COP Control Register
6.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1
(CONFIG1). See Chapter 5 Configuration Register (CONFIG).
6.4 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing
any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF
returns the low byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
LOW BYTE OF RESET VECTOR
CLEAR COP COUNTER
Unaffected by reset
Figure 6-2. COP Control Register (COPCTL)
6.5 Interrupts
The COP does not generate CPU interrupt requests.
6.6 Monitor Mode
The COP is disabled in monitor mode when VTST is present on the IRQ pin.
6.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.7.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically
clear the COP counter.
6.7.2 Stop Mode
Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
6.8 COP Module During Break Mode
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
59
Computer Operating Properly (COP)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
60
Freescale Semiconductor
Chapter 7
Central Processor Unit (CPU)
7.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a
description of the CPU instruction set, addressing modes, and architecture.
7.2 Features
Features of the CPU include:
•
•
•
•
•
•
•
•
•
•
Object code fully upward-compatible with M68HC05 Family
16-bit stack pointer with stack manipulation instructions
16-bit index register with x-register manipulation instructions
8-MHz CPU internal bus frequency
64-Kbyte program/data memory space
16 addressing modes
Memory-to-memory data moves without using accumulator
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
Enhanced binary-coded decimal (BCD) data handling
Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
•
Low-power stop and wait modes
7.3 CPU Registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
61
Central Processor Unit (CPU)
7
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
7
0
V
1
1
H
I
N
Z
C
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 7-1. CPU Registers
7.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-2. Accumulator (A)
7.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15 14 13 12 11 10
Bit
0
9
0
8
0
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 7-3. Index Register (H:X)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
62
Freescale Semiconductor
CPU Registers
7.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
15 14 13 12 11 10
Bit
0
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 7-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to
$00FF) frees direct address (page 0) space. For correct operation, the
stack pointer must point only to RAM locations.
7.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
15 14 13 12 11 10
Bit
0
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 7-5. Program Counter (PC)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
63
Central Processor Unit (CPU)
7.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
1
1
5
1
1
4
H
X
3
2
N
X
1
Z
X
Bit 0
Read:
Write:
Reset:
V
I
C
X
1
X
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
MC68HLC908QY/QT Family Data Sheet, Rev. 3
64
Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
7.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the
instructions and addressing modes and more detail about the architecture of the CPU.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
7.5.1 Wait Mode
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
•
7.5.2 Stop Mode
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
7.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
65
Central Processor Unit (CPU)
7.7 Instruction Set Summary
Table 7-1 provides a summary of the M68HC08 instruction set.
Table 7-1. Instruction Set Summary (Sheet 1 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
ADC #opr
IMM
DIR
EXT
IX2
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
2
3
4
4
3
2
4
5
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
ꢀ
ꢀ
ꢀ
ꢀ
–
–
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IX1
IX
SP1
SP2
F9
ADC opr,SP
ADC opr,SP
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
IMM
DIR
EXT
IX2
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
9EEB ff
9EDB ee ff
2
3
4
4
3
2
4
5
Add without Carry
A ← (A) + (M)
IX1
IX
SP1
SP2
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7 ii
AF ii
2
2
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
AND #opr
AND opr
IMM
DIR
EXT
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
2
3
4
4
3
2
4
5
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
IX2
Logical AND
A ← (A) & (M)
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
–
IX1
IX
F4
SP1
SP2
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
DIR
INH
38 dd
48
4
1
1
4
3
5
ASLX
Arithmetic Shift Left
(Same as LSL)
INH
58
C
0
ꢀ
ꢀ
ASL opr,X
ASL ,X
IX1
68 ff
78
b7
b7
b0
b0
IX
ASL opr,SP
SP1
9E68 ff
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
37 dd
47
4
1
1
4
3
5
INH
57
C
Arithmetic Shift Right
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
IX1
67 ff
77
IX
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
– REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
–
–
–
–
BCS rel
BEQ rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25 rr
27 rr
3
3
Branch if Greater Than or Equal To
(Signed Operands)
BGE opr
BGT opr
–
–
–
–
–
–
–
–
–
–
– REL
– REL
90 rr
92 rr
3
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
Branch if Greater Than (Signed
Operands)
3
3
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
28 rr
29 rr
22 rr
3
3
MC68HLC908QY/QT Family Data Sheet, Rev. 3
66
Freescale Semiconductor
Instruction Set Summary
Table 7-1. Instruction Set Summary (Sheet 2 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
– REL
24 rr
3
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
2F rr
2E rr
3
3
BIT #opr
BIT opr
IMM
DIR
EXT
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
2
3
4
4
3
2
4
5
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
IX2
Bit Test
(A) & (M)
0
–
–
ꢀ
ꢀ
–
IX1
IX
F5
SP1
SP2
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal To
(Signed Operands)
BLE opr
–
–
–
–
–
– REL
93 rr
3
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1
BLO rel
BLS rel
BLT opr
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Less Than (Signed Operands)
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
25 rr
23 rr
91 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ꢀ
BRN rel
Branch Never
– REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
ꢀ
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
4
4
4
4
4
4
4
4
BSET n,opr
BSR rel
Set Bit n in M
Mn ← 1
–
–
–
–
–
–
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to Subroutine
–
–
–
–
–
–
–
–
–
–
– REL
AD rr
4
PC ← (PC) + rel
CBEQ opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
31 dd rr
41 ii rr
51 ii rr
61 ff rr
71 rr
5
4
4
5
4
6
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
IMM
IMM
Compare and Branch if Equal
–
IX1+
IX+
CBEQ opr,SP,rel
SP1
9E61 ff rr
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
0
–
–
–
–
0 INH
– INH
98
9A
1
2
Clear Interrupt Mask
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
67
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 3 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
CLR opr
CLRA
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
3F dd
4F
3
1
1
1
3
2
4
CLRX
5F
CLRH
Clear
0
–
–
–
–
0
1
– INH
IX1
8C
CLR opr,X
CLR ,X
6F ff
7F
IX
SP1
CLR opr,SP
9E6F ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
IMM
DIR
EXT
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
2
3
4
4
3
2
4
5
IX2
Compare A with M
(A) – (M)
ꢀ
ꢀ
ꢀ
ꢀ
IX1
IX
F1
SP1
SP2
9EE1 ff
9ED1 ee ff
COM opr
COMA
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
33 dd
43
4
1
1
4
3
5
COMX
INH
53
Complement (One’s Complement)
Compare H:X with M
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
1
COM opr,X
COM ,X
COM opr,SP
IX1
63 ff
73
9E63 ff
IX
SP1
CPHX #opr
CPHX opr
IMM
ꢀ
65 ii ii+1
75 dd
3
4
(H:X) – (M:M + 1)
ꢀ
DIR
CPX #opr
CPX opr
IMM
DIR
EXT
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
2
3
4
4
3
2
4
5
CPX opr
CPX ,X
IX2
Compare X with M
(X) – (M)
(A)10
ꢀ
–
–
ꢀ
ꢀ
ꢀ
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
IX1
IX
F3
SP1
SP2
9EE3 ff
9ED3 ee ff
DAA
Decimal Adjust A
U
–
–
–
–
–
ꢀ
ꢀ
ꢀ INH
72
2
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DIR
INH
3B dd rr
4B rr
DBNZX rel
Decrement and Branch if Not Zero
–
–
– INH
IX1
5B rr
DBNZ opr,X,rel
DBNZ X,rel
6B ff rr
7B rr
IX
SP1
DBNZ opr,SP,rel
9E6B ff rr
DEC opr
DECA
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
3A dd
4A
4
1
1
4
3
5
DECX
INH
5A
Decrement
Divide
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
–
DEC opr,X
DEC ,X
DEC opr,SP
IX1
6A ff
7A
9E6A ff
IX
SP1
A ← (H:A)/(X)
DIV
–
–
ꢀ INH
52
7
H ← Remainder
EOR #opr
EOR opr
IMM
DIR
EXT
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
2
3
4
4
3
2
4
5
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IX2
Exclusive OR M with A
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
–
A ← (A ⊕ M)
IX1
IX
F8
SP1
SP2
9EE8 ff
9ED8 ee ff
INC opr
INCA
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
3C dd
4C
4
1
1
4
3
5
INCX
INH
5C
Increment
ꢀ
–
INC opr,X
INC ,X
IX1
6C ff
7C
IX
INC opr,SP
SP1
9E6C ff
MC68HLC908QY/QT Family Data Sheet, Rev. 3
68
Freescale Semiconductor
Instruction Set Summary
Table 7-1. Instruction Set Summary (Sheet 4 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
JMP opr
DIR
BC dd
CC hh ll
DC ee ff
EC ff
2
3
4
3
2
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
EXT
Jump
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
– IX2
IX1
IX
FC
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
– IX2
IX1
BD dd
CD hh ll
DD ee ff
ED ff
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
Jump to Subroutine
IX
FD
LDA #opr
LDA opr
IMM
DIR
EXT
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
2
3
4
4
3
2
4
5
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
IX2
Load A from M
Load H:X from M
Load X from M
A ← (M)
H:X ← (M:M + 1)
X ← (M)
0
0
0
–
–
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
–
IX1
IX
F6
SP1
SP2
9EE6 ff
9ED6 ee ff
LDHX #opr
LDHX opr
IMM
–
45 ii jj
55 dd
3
4
DIR
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
9EEE ff
9EDE ee ff
2
3
4
4
3
2
4
5
IX2
–
IX1
IX
SP1
SP2
LSL opr
LSLA
DIR
INH
38 dd
48
4
1
1
4
3
5
LSLX
Logical Shift Left
(Same as ASL)
INH
58
C
0
ꢀ
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
LSL opr,X
LSL ,X
LSL opr,SP
IX1
68 ff
78
9E68 ff
b7
b7
b0
b0
IX
SP1
LSR opr
LSRA
DIR
INH
34 dd
44
4
1
1
4
3
5
LSRX
INH
54
0
C
Logical Shift Right
0
ꢀ
LSR opr,X
LSR ,X
IX1
64 ff
74
IX
LSR opr,SP
SP1
9E64 ff
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E dd dd
5E dd
5
4
4
4
(M)Destination ← (M)Source
DIX+
Move
0
–
–
0
–
–
ꢀ
ꢀ
–
IMD
IX+D
6E ii dd
7E dd
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
MUL
Unsigned multiply
–
–
0 INH
42
5
NEG opr
NEGA
DIR
INH
30 dd
40
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
NEGX
INH
50
Negate (Two’s Complement)
ꢀ
–
–
ꢀ
ꢀ
ꢀ
NEG opr,X
NEG ,X
NEG opr,SP
IX1
60 ff
70
9E60 ff
IX
SP1
NOP
NSA
No Operation
Nibble Swap A
None
–
–
–
–
–
–
–
–
–
–
– INH
– INH
9D
62
1
3
A ← (A[3:0]:A[7:4])
ORA #opr
ORA opr
IMM
DIR
EXT
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
2
3
4
4
3
2
4
5
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
IX2
Inclusive OR A and M
A ← (A) | (M)
0
–
–
ꢀ
ꢀ
–
IX1
IX
FA
SP1
SP2
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
87
8B
89
2
2
2
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
69
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 5 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
PULA
PULH
PULX
Pull A from Stack
Pull H from Stack
Pull X from Stack
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
86
8A
88
2
2
2
ROL opr
ROLA
DIR
INH
39 dd
49
4
1
1
4
3
5
ROLX
INH
59
C
Rotate Left through Carry
Rotate Right through Carry
ꢀ
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ROL opr,X
ROL ,X
ROL opr,SP
IX1
69 ff
79
9E69 ff
b7
b0
IX
SP1
ROR opr
RORA
DIR
INH
36 dd
46
4
1
1
4
3
5
RORX
INH
56
C
ꢀ
ROR opr,X
ROR ,X
IX1
66 ff
76
b7
b0
IX
ROR opr,SP
SP1
9E66 ff
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
–
– INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ INH
80
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
Subtract with Carry
–
–
–
–
–
–
–
– INH
81
4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
IMM
DIR
EXT
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
2
3
4
4
3
2
4
5
IX2
A ← (A) – (M) – (C)
ꢀ
ꢀ
ꢀ
ꢀ
IX1
IX
SP1
SP2
F2
9EE2 ff
9ED2 ee ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
–
–
–
–
–
1
–
–
–
–
1 INH
– INH
99
9B
1
2
Set Interrupt Mask
STA opr
DIR
EXT
IX2
B7 dd
C7 hh ll
D7 ee ff
E7 ff
3
4
4
3
2
4
5
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
ꢀ
ꢀ
– IX1
IX
F7
SP1
SP2
9EE7 ff
9ED7 ee ff
STHX opr
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
–
0
ꢀ
ꢀ
– DIR
35 dd
4
Enable Interrupts, Stop Processing,
Refer to MCU Documentation
STOP
I ← 0; Stop Processing
–
–
– INH
8E
1
STX opr
DIR
EXT
IX2
BF dd
CF hh ll
DF ee ff
EF ff
3
4
4
3
2
4
5
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
– IX1
IX
FF
SP1
SP2
9EEF ff
9EDF ee ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
2
3
4
4
3
2
4
5
IX2
Subtract
A ← (A) – (M)
ꢀ
ꢀ
IX1
IX
F0
SP1
SP2
9EE0 ff
9ED0 ee ff
MC68HLC908QY/QT Family Data Sheet, Rev. 3
70
Freescale Semiconductor
Opcode Map
Table 7-1. Instruction Set Summary (Sheet 6 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
A ← (CCR)
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ INH
– INH
– INH
84
97
85
2
1
1
Transfer CCR to A
TST opr
TSTA
DIR
INH
3D dd
4D
3
1
1
3
2
4
TSTX
INH
5D
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
ꢀ
ꢀ
–
TST opr,X
TST ,X
TST opr,SP
IX1
6D ff
7D
9E6D ff
IX
SP1
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
(SP) ← (H:X) – 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
I bit ← 0; Inhibit CPU clocking
WAIT
Enable Interrupts; Wait for Interrupt
–
–
0
–
–
– INH
8F
1
until interrupted
A
Accumulator
n
Any bit
C
Carry/borrow bit
opr Operand (one or two bytes)
PC Program counter
CCR
dd
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP Stack pointer
U
V
X
Z
&
|
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
Relative program counter offset byte
Relative program counter offset byte
H
H
Undefined
Overflow bit
Index register low byte
Zero bit
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
ii
Logical AND
Logical OR
IMD
IMM
INH
IX
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
⊕
Logical EXCLUSIVE OR
Contents of
( )
–( ) Negation (two’s complement)
#
IX+
Immediate value
IX+D
IX1
IX1+
IX2
M
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
«
←
?
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
:
ꢀ
—
N
Negative bit
7.8 Opcode Map
See Table 7-2.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
71
Table 7-2. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
4
INH
IX1
SP1
9E6
IX
7
INH
INH
IMM
A
DIR
B
EXT
C
IX2
SP2
IX1
E
SP1
9EE
IX
F
MSB
0
1
2
5
6
8
9
D
9ED
LSB
5
4
3
4
1
NEGA
INH
1
NEGX
INH
4
5
3
7
3
2
3
4
4
5
3
4
2
0
BRSET0 BSET0
BRA
NEG
NEG
NEG
NEG
IX
RTI
BGE
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
IX
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
2
REL 2 DIR
1
1
2
IX1 3 SP1
5
1
2
1
1
1
2
1
1
1
1
1
2
1
1
2
1
1
1
INH
2
2
2
2
1
1
REL 2 IMM 2 DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT 3 IX2
4
4
4
4
4
4
4
4
4
4
4
4
SP2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IX1
3
3
3
3
3
3
3
3
3
3
3
3
SP1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
BRN
REL 3 DIR
5
4
4
6
4
CBEQ
IX+
2
DAA
INH
3
COM
IX
3
LSR
IX
4
CPHX
DIR
3
ROR
IX
3
ASR
IX
3
LSL
IX
3
ROL
IX
3
DEC
IX
4
DBNZ
IX
3
INC
IX
4
3
BLT
2
3
4
4
5
3
4
2
CMP
IX
2
SBC
IX
2
CPX
IX
2
AND
IX
2
BIT
IX
2
LDA
IX
2
STA
IX
2
EOR
IX
2
ADC
IX
2
ORA
IX
2
ADD
IX
2
JMP
IX
4
JSR
IX
2
LDX
IX
2
STX
IX
1
2
BRCLR0 BCLR0
CBEQ CBEQA CBEQX CBEQ
CBEQ
RTS
CMP
CMP
CMP
CMP
CMP
CMP
CMP
3
DIR
5
2
DIR
4
3
IMM 3 IMM 3 IX1+
4
SP1
INH
REL 2 IMM 2 DIR
EXT 3 IX2
SP2
IX1
SP1
3
5
7
3
3
BGT
2
SBC
3
SBC
4
SBC
EXT 3 IX2
4
CPX
EXT 3 IX2
4
AND
EXT 3 IX2
4
BIT
EXT 3 IX2
4
LDA
EXT 3 IX2
4
STA
EXT 3 IX2
4
EOR
EXT 3 IX2
4
ADC
EXT 3 IX2
4
ORA
EXT 3 IX2
4
ADD
EXT 3 IX2
3
JMP
EXT 3 IX2
5
JSR
EXT 3 IX2
4
LDX
EXT 3 IX2
4
STX
EXT 3 IX2
4
SBC
5
3
4
BRSET1 BSET1
BHI
MUL
INH
DIV
INH
NSA
SBC
SBC
SBC
3
DIR
5
2
DIR
4
REL
1
1
1
2
2
3
2
2
2
2
2
INH
REL 2 IMM 2 DIR
SP2
IX1
SP1
3
BLS
REL 2 DIR
3
BCC
REL 2 DIR
3
BCS
REL 2 DIR
3
BNE
REL 2 DIR
4
1
1
4
COM
IX1
4
LSR
IX1
3
CPHX
IMM
4
ROR
IX1
4
ASR
IX1
4
LSL
IX1
4
ROL
IX1
4
DEC
IX1
5
9
3
BLE
2
CPX
3
CPX
4
CPX
5
3
4
3
BRCLR1 BCLR1
COM
COMA
COMX
COM
SWI
CPX
CPX
CPX
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
SP1
1
1
1
1
1
1
1
1
1
1
INH
REL 2 IMM 2 DIR
SP2
IX1
SP1
4
LSR
1
LSRA
INH
1
LSRX
INH
5
2
2
2
AND
IMM 2 DIR
3
AND
4
AND
5
3
4
4
BRSET2 BSET2
LSR
TAP
TXS
AND
AND
AND
3
DIR
5
2
DIR
4
1
3
1
SP1
INH
INH
2
2
2
2
2
2
2
2
SP2
IX1
SP1
4
3
4
1
2
2
BIT
3
BIT
4
BIT
5
3
4
5
BRCLR2 BCLR2
STHX
LDHX
LDHX
TPA
TSX
BIT
BIT
BIT
3
DIR
5
2
DIR
4
IMM 2 DIR
INH
INH
IMM 2 DIR
SP2
IX1
SP1
4
ROR
1
1
5
2
PULA
INH
2
PSHA
INH
2
PULX
INH
2
PSHX
INH
2
PULH
INH
2
PSHH
INH
1
CLRH
INH
2
LDA
IMM 2 DIR
2
AIS
IMM 2 DIR
2
EOR
IMM 2 DIR
2
ADC
IMM 2 DIR
2
ORA
IMM 2 DIR
2
ADD
IMM 2 DIR
3
LDA
4
LDA
5
3
4
6
BRSET3 BSET3
RORA
RORX
ROR
LDA
LDA
LDA
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
3
3
3
4
3
3
SP1
5
SP2
IX1
SP1
3
BEQ
REL 2 DIR
3
4
ASR
1
ASRA
INH
1
LSLA
INH
1
ROLA
INH
1
DECA
INH
1
ASRX
INH
1
LSLX
INH
1
ROLX
INH
1
DECX
INH
1
3
STA
4
STA
5
3
4
7
BRCLR3 BCLR3
ASR
TAX
STA
STA
STA
3
DIR
5
2
DIR
4
1
1
1
1
1
1
1
1
SP1
5
1
1
1
1
1
1
1
INH
SP2
IX1
SP1
4
LSL
1
3
EOR
4
EOR
5
3
4
8
BRSET4 BSET4 BHCC
LSL
CLC
EOR
EOR
EOR
3
DIR
5
2
DIR
4
2
REL 2 DIR
3
SP1
5
INH
SP2
IX1
SP1
4
ROL
1
3
ADC
4
ADC
5
3
4
9
BRCLR4 BCLR4 BHCS
ROL
SEC
ADC
ADC
ADC
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
REL 2 DIR
SP1
5
INH
SP2
IX1
SP1
3
BPL
REL 2 DIR
3
BMI
REL 3 DIR
4
DEC
2
3
ORA
4
ORA
5
3
4
A
B
C
D
E
F
BRSET5 BSET5
DEC
CLI
ORA
ORA
ORA
3
DIR
5
2
DIR
4
SP1
6
INH
SP2
IX1
SP1
5
3
3
5
2
3
ADD
4
ADD
5
3
4
BRCLR5 BCLR5
DBNZ DBNZA DBNZX DBNZ
DBNZ
SEI
ADD
ADD
ADD
3
DIR
5
2
DIR
4
2
1
1
3
1
INH
1
2
1
1
2
1
INH
1
3
2
2
3
2
IX1
4
SP1
5
INH
SP2
IX1
SP1
3
4
INC
1
2
JMP
4
JMP
3
BRSET6 BSET6
BMC
INCA
INCX
INC
INC
RSP
JMP
3
DIR
5
2
DIR
4
REL 2 DIR
INH
1
INH
1
IX1
3
SP1
4
INH
2
DIR
4
IX1
3
BMS
3
TST
2
TST
IX
1
4
BSR
REL 2 DIR
2
LDX
IMM 2 DIR
2
AIX
IMM 2 DIR
6
JSR
5
BRCLR6 BCLR6
TSTA
TSTX
TST
TST
NOP
JSR
JSR
3
DIR
5
2
DIR
4
REL 2 DIR
3
INH
5
INH
4
IX1
4
SP1
INH
2
2
2
IX1
4
1
STOP
INH
1
WAIT
INH
3
LDX
4
LDX
5
3
4
BRSET7 BSET7
BIL
MOV
MOV
MOV
MOV
IX+D
LDX
LDX
LDX
*
1
TXA
INH
3
DIR
5
2
DIR
4
REL
3
DD
DIX+
IMD
3
1
1
4
4
SP2
IX1
3
3
SP1
3
CLR
1
CLRA
INH
1
CLRX
INH
4
2
CLR
IX
3
STX
4
STX
5
3
4
BRCLR7 BCLR7
BIH
CLR
IX1
CLR
SP1
STX
STX
STX
3
DIR
2
DIR
REL 2 DIR
3
1
SP2
IX1
SP1
INH Inherent
REL Relative
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
MSB
LSB
0
High Byte of Opcode in Hexadecimal
Cycles
IMM Immediate
DIR Direct
IX
Indexed, No Offset
IX1 Indexed, 8-Bit Offset
IX2 Indexed, 16-Bit Offset
IMD Immediate-Direct
EXT Extended
DD Direct-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
Low Byte of Opcode in Hexadecimal
0
BRSET0 Opcode Mnemonic
DIR Number of Bytes / Addressing Mode
3
Chapter 8
External Interrupt (IRQ)
8.1 Introduction
The IRQ pin (external interrupt), shared with PTA2 (general purpose input) and keyboard interrupt (KBI),
provides a maskable interrupt input.
8.2 Features
Features of the IRQ module include the following:
•
•
•
•
•
External interrupt pin, IRQ
IRQ interrupt control bits
Programmable edge-only or edge and level interrupt sensitivity
Automatic interrupt acknowledge
Selectable internal pullup resistor
8.3 Functional Description
IRQ pin functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A
zero disables the IRQ function and PTA2 will assume the other shared functionalities. A one enables the
IRQ function.
A low level applied to the external interrupt request (IRQ) pin can latch a CPU interrupt request.
Figure 8-2 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. The IRQ latch remains set until one of the
following actions occurs:
•
•
•
IRQ vector fetch — An IRQ vector fetch automatically generates an interrupt acknowledge signal
that clears the IRQ latch.
Software clear — Software can clear the IRQ latch by writing a 1 to the ACK bit in the interrupt
status and control register (INTSCR).
Reset — A reset automatically clears the IRQ latch.
The external interrupt pin is falling-edge-triggered out of reset and is software-configurable to be either
falling-edge or falling-edge and low-level triggered. The MODE bit in INTSCR controls the triggering
sensitivity of the IRQ pin.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
73
External Interrupt (IRQ)
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
BREAK
MODULE
POWER-ON RESET
MODULE
MC68HLC908QY4 AND MC68HLC908QT4
4096 BYTES
KEYBOARD INTERRUPT
MODULE
8-BIT ADC
MC68HLC908QY2, MC68HLC908QY1,
MC68HLC908QT2, AND MC68HLC908QT1:
1536 BYTES
16-BIT TIMER
MODULE
USER FLASH
128 BYTES RAM
COP
MODULE
VDD
VSS
POWER SUPPLY
MONITOR ROM
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in
12.1 Introduction)
ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1
Figure 8-1. Block Diagram Highlighting IRQ Block and Pins
When set, the IMASK bit in INTSCR masks the IRQ interrupt request. A latched interrupt request is not
presented to the interrupt priority logic unless IMASK is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including the IRQ interrupt request.
A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. An IRQ vector fetch,
software clear, or reset clears the IRQ latch.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
74
Freescale Semiconductor
Functional Description
ACK
RESET
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
IRQPUD
INTERNAL
PULLUP
DEVICE
VDD
IRQF
CLR
D
Q
SYNCHRO-
NIZER
IRQ
INTERRUPT
REQUEST
CK
IRQ
IRQ
LATCH
IMASK
MODE
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 8-2. IRQ Module Block Diagram
8.3.1 MODE = 1
If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set,
both of the following actions must occur to clear the IRQ interrupt request:
•
•
Return of the IRQ pin to a high level. As long as the IRQ pin is low, the IRQ request remains active.
IRQ vector fetch or software clear. An IRQ vector fetch generates an interrupt acknowledge signal
to clear the IRQ latch. Software generates the interrupt acknowledge signal by writing a 1 to ACK
in INTSCR. The ACK bit is useful in applications that poll the IRQ pin and require software to clear
the IRQ latch. Writing to ACK prior to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling
edge that occurs after writing to ACK latches another interrupt request. If the IRQ mask bit, IMASK,
is clear, the CPU loads the program counter with the IRQ vector address.
The IRQ vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order.
The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the IRQ latch and
the MODE control bit, thereby clearing the interrupt even if the pin stays low.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
8.3.2 MODE = 0
If the MODE bit is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetch
or software clear immediately clears the IRQ latch.
The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by
IMASK, which makes it useful in applications where polling is preferred.
NOTE
When using the level-sensitive interrupt trigger, avoid false IRQ interrupts
by masking interrupt requests in the interrupt routine.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
75
External Interrupt (IRQ)
8.4 Interrupts
The following IRQ source can generate interrupt requests:
•
Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode.
The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests.
8.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
8.5.1 Wait Mode
The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests
to bring the MCU out of wait mode.
8.5.2 Stop Mode
The IRQ module remains active in stop mode. Clearing IMASK in INTSCR enables IRQ interrupt requests
to bring the MCU out of stop mode.
8.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See Chapter 13 System Integration Module (SIM).
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
8.7 I/O Signals
The IRQ module shares its pin with the keyboard interrupt, input/output ports, and timer interface
modules.
NOTE
When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL
instructions can be used to read the logic level on the IRQ pin. If the IRQ
function is disabled, these instructions will behave as if the IRQ pin is a
logic 1, regardless of the actual level on the pin. Conversely, when the IRQ
function is enabled, bit 2 of the port A data register will always read a 0.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine. An internal pullup
resistor to VDD is connected to the IRQ pin; this can be disabled by setting
the IRQPUD bit in the CONFIG2 register ($001E).
MC68HLC908QY/QT Family Data Sheet, Rev. 3
76
Freescale Semiconductor
Registers
8.7.1 IRQ Input Pins (IRQ)
The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup
device.
8.8 Registers
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. See
Chapter 5 Configuration Register (CONFIG).
The INTSCR has the following functions:
•
•
•
•
Shows the state of the IRQ flag
Clears the IRQ latch
Masks the IRQ interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
Address: $001D
Bit 7
0
6
0
5
0
4
0
3
2
0
1
IMASK
0
Bit 0
MODE
0
Read:
Write:
Reset:
IRQF
ACK
0
0
0
0
0
0
= Unimplemented
Figure 8-3. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag
This read-only status bit is set when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables the IRQ interrupt request.
1 = IRQ interrupt request disabled
0 = IRQ interrupt request enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
1 = IRQ interrupt request on falling edges and low levels
0 = IRQ interrupt request on falling edges only
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
77
External Interrupt (IRQ)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
78
Freescale Semiconductor
Chapter 9
Keyboard Interrupt Module (KBI)
9.1 Introduction
The keyboard interrupt module (KBI) provides six independently maskable external interrupts, which are
accessible via the PTA0–PTA5 pins.
9.2 Features
Features of the keyboard interrupt module include:
•
Six keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt
mask
•
•
•
Software configurable pullup device if input pin is configured as input port bit
Programmable edge-only or edge and level interrupt sensitivity
Exit from low-power modes
9.3 Functional Description
The keyboard interrupt module controls the enabling/disabling of interrupt functions on the six port A pins.
These six pins can be enabled/disabled independently of each other.
9.3.1 Keyboard Operation
Writing to the KBIE0–KBIE5 bits in the keyboard interrupt enable register (KBIER) independently enables
or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also
enables its internal pullup device irrespective of PTAPUEx bits in the port A input pullup enable register
(see 12.2.3 Port A Input Pullup Enable Register). A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard interrupt inputs goes low after all were high.
The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard
interrupt.
•
If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard interrupt input does
not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt
request on one input because another input is still low, software can disable the latter input while
it is low.
•
If the keyboard interrupt is falling edge and low-level sensitive, an interrupt request is present as
long as any keyboard interrupt input is low.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
79
Keyboard Interrupt Module (KBI)
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
BREAK
MODULE
POWER-ON RESET
MODULE
MC68HLC908QY4 AND MC68HLC908QT4
4096 BYTES
KEYBOARD INTERRUPT
MODULE
8-BIT ADC
MC68HLC908QY2, MC68HLC908QY1,
MC68HLC908QT2, AND MC68HLC908QT1:
1536 BYTES
16-BIT TIMER
MODULE
USER FLASH
128 BYTES RAM
COP
MODULE
VDD
VSS
POWER SUPPLY
MONITOR ROM
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in
12.1 Introduction)
ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1
Figure 9-1. Block Diagram Highlighting KBI Block and Pins
MC68HLC908QY/QT Family Data Sheet, Rev. 3
80
Freescale Semiconductor
Functional Description
INTERNAL BUS
VECTOR FETCH
DECODER
ACKK
KBI0
VDD
RESET
KEYF
CLR
.
.
.
D
Q
SYNCHRONIZER
KBIE0
CK
TO PULLUP ENABLE
KEYBOARD
INTERRUPT
REQUEST
IMASKK
KBI5
KEYBOARD
INTERRUPT FF
MODEK
KBIE5
TO PULLUP ENABLE
1. For AWUGEN logic refer to Figure 4-1. Auto Wakeup Interrupt
Request Generation Logic.
AWUIREQ(1)
Figure 9-2. Keyboard Interrupt Block Diagram
If the MODEK bit is set, the keyboard interrupt inputs are both falling edge and low-level sensitive, and
both of the following actions must occur to clear a keyboard interrupt request:
•
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the interrupt request. Software may generate the interrupt acknowledge signal by writing a 1 to the
ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in
applications that poll the keyboard interrupt inputs and require software to clear the keyboard
interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also
prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on
the keyboard interrupt inputs. A falling edge that occurs after writing to the ACKK bit latches
another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the central
processor unit (CPU) loads the program counter with the vector address at locations $FFE0 and
$FFE1.
•
Return of all enabled keyboard interrupt inputs to logic 1 — As long as any enabled keyboard
interrupt pin is at logic 0, the keyboard interrupt remains set. The auto wakeup interrupt input,
AWUIREQ, will be cleared only by writing to ACKK bit in KBSCR or reset.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur
in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge sensitive only. With MODEK clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt input stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes
it useful in applications where polling is preferred.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
81
Keyboard Interrupt Module (KBI)
To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the
pin as an input and then read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a 0 for software to read the
pin.
9.3.2 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore
a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction
register A.
2. Write 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
9.4 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
9.5 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
9.6 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state.
To allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the BCFE bit.
If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the
break state has no effect.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
82
Freescale Semiconductor
Input/Output Registers
9.7 Input/Output Registers
The following I/O registers control and monitor operation of the keyboard interrupt module:
•
•
Keyboard interrupt status and control register (KBSCR)
Keyboard interrupt enable register (KBIER)
9.7.1 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):
•
•
•
•
Flags keyboard interrupt requests
Acknowledges keyboard interrupt requests
Masks keyboard interrupt requests
Controls keyboard interrupt triggering sensitivity
Address: $001A
Bit 7
0
6
0
5
0
4
0
3
2
1
IMASKK
0
Bit 0
MODEK
0
Read:
Write:
Reset:
KEYF
0
ACKK
0
0
0
0
0
0
= Unimplemented
Figure 9-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears
the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard interrupt request on port A and auto wakeup logic.
ACKK always reads as 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating
interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A and auto
wakeup. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
83
Keyboard Interrupt Module (KBI)
9.7.2 Keyboard Interrupt Enable Register
The port A keyboard interrupt enable register (KBIER) enables or disables each port A pin or auto wakeup
to operate as a keyboard interrupt input.
Address: $001B
Bit 7
0
6
AWUIE
0
5
KBIE5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
0
= Unimplemented
Figure 9-4. Keyboard Interrupt Enable Register (KBIER)
KBIE5–KBIE0 — Port A Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin on port A to latch
interrupt requests. Reset clears the keyboard interrupt enable register.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
NOTE
AWUIE bit is not used in conjunction with the keyboard interrupt feature. To
see a description of this bit, see Chapter 4 Auto Wakeup Module (AWU).
MC68HLC908QY/QT Family Data Sheet, Rev. 3
84
Freescale Semiconductor
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin
and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF
.
10.2 Features
Features of the LVI module include:
•
•
•
•
Programmable LVI reset
Programmable power consumption
Selectable LVI trip voltage
Programmable stop mode operation
10.3 Functional Description
Figure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD, LVDLVR, and LVIRSTD are
user selectable options found in the configuration register (CONFIG1). See Chapter 5 Configuration
Register (CONFIG).
VDD
STOP INSTRUCTION
LVISTOP
FROM CONFIG
FROM CONFIG
LVIRSTD
LVIPWRD
FROM CONFIG
V
DD > LVITRIP = 0
LVI RESET
LOW VDD
DETECTOR
VDD ≤ LVITRIP = 1
LVIOUT
LVDLVR
FROM CONFIG
Figure 10-1. LVI Module Block Diagram
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
85
Low-Voltage Inhibit (LVI)
The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator.
Clearing the LVI power disable bit (LVIPWRD) enables the LVI to monitor VDD voltage. Clearing the LVI
reset disable bit (LVIRSTD) enables the LVI module to generate a reset when VDD falls below a voltage,
VTRIPF or VDTRIPF. Setting the LVI enable in stop mode bit (LVISTOP) enables the LVI to operate in stop
mode. Setting the LVD or LVR trip point bit (LVDLVR) selects the LVD trip point voltage. The actual trip
thresholds are specified in 16.5 DC Electrical Characteristics. Either trip level can be used as a detect or
reset.
NOTE
After a power-on reset, the LVI’s default mode of operation is LVR trip
voltage. If a higher trip voltage is desired, the user must set the LVDLVR bit
to raise the trip point to the LVD voltage.
If the user requires the higher trip voltage and sets the LVDLVR bit after
power-on reset while the VDD supply is not above the VTRIPR for LVD
mode, the microcontroller unit (MCU) will immediately go into reset. The
next time the LVI releases the reset, the supply will be above the VTRIPR for
LVD mode.
Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which
causes the MCU to exit reset. See Chapter 13 System Integration Module (SIM) for the reset recovery
sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
10.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be cleared to enable the LVI module,
and the LVIRSTD bit must be set to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the
LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets.
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until
VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than
VTRIPF by the hysteresis voltage, VHYS
.
10.3.4 LVI Trip Selection
The LVDLVR bit in the configuration register selects whether the LVI is configured for LVD (low voltage
detect) or LVR (low voltage reset) protection. The LVD trip voltage can be used as a low voltage warning.
The LVR trip voltage will commonly be configured as a reset condition since it is very close to the minimum
operating voltage of the device. The LVDLVR bit can be written to anytime so that battery applications
can make use of the LVI as both a warning indicator and to generate a system reset.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
86
Freescale Semiconductor
LVI Status Register
Polling and forced reset operation modes can be combined to take full advantage of LVD and LVR trip
voltages selection. LVD (LVDLVR = 1) in polling mode (LVIRSTD = 1) can be used as a low voltage
warning in a slowly and continuously falling VDD application (for example, battery applications). Once LVD
has been identified, the part can be set to LVR (LVDLVR = 0) and reset enabled (LVIRSTD = 0). So, as
VDD continues to fall the part will reset when LVR trip voltage is reached. Unlike other bits in CONFIG
registers, LVIRSTD and LVDLVR bits are allowed to be written multiple times after reset.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (VTRIPF [LVD] or VTRIPF [LVR]) may be lower than this. See
16.5 DC Electrical Characteristics for the actual trip point voltages.
10.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level while
LVI resets have been disabled.
Address: $FE0C
Bit 7
Read: LVIOUT
Write:
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
R
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 10-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage and is cleared
when VDD voltage rises above VTRIPR. The difference in these threshold levels results in a hysteresis
that prevents oscillation into and out of reset (see Table 10-1). Reset clears the LVIOUT bit.
Table 10-1. LVIOUT Bit Indication
VDD
LVIOUT
VDD > VTRIPR
0
VDD < VTRIPF
1
VTRIPF < VDD < VTRIPR
Previous value
10.5 LVI Interrupts
The LVI module does not generate interrupt requests.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
87
Low-Voltage Inhibit (LVI)
10.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.6.2 Stop Mode
When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
88
Freescale Semiconductor
Chapter 11
Oscillator Module (OSC)
11.1 Introduction
The oscillator module is used to provide a stable clock source for the microcontroller system and bus. The
oscillator module generates two output clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is
used by the system integration module (SIM) and the computer operating properly module (COP). The
BUSCLKX2 clock is divided by two in the SIM to be used as the bus clock for the microcontroller.
Therefore the bus frequency will be one forth of the BUSCLKX4 frequency.
11.2 Features
The oscillator has these four clock source options available:
1. Internal oscillator: An internally generated, fixed frequency clock, trimmable to 5%. This is the
default option out of reset.
2. External oscillator: An external clock that can be driven directly into OSC1.
3. External RC: A built-in oscillator module (RC oscillator) that requires an external R connection only.
The capacitor is internal to the chip.
4. External crystal: A built-in oscillator module (XTAL oscillator) that requires an external crystal or
ceramic-resonator.
11.3 Functional Description
The oscillator contains these major subsystems:
•
•
•
•
•
Internal oscillator circuit
Internal or external clock switch control
External clock circuit
External crystal circuit
External RC clock circuit
11.3.1 Internal Oscillator
The internal oscillator circuit is designed for use with no external components to provide a clock source
with tolerance less than 25% untrimmed. An 8-bit trimming register allows adjustment to a tolerance of
less than 5%.
The internal oscillator will generate a clock of 4.0 MHz typical (INTCLK) resulting in a bus speed (internal
clock ÷ 4) of 1.0 MHz.
Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and, like the RC oscillator, OSC2 can output
BUSCLKX4 by setting OSC2EN in PTAPUE register. See Chapter 12 Input/Output Ports (PORTS).
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
89
Oscillator Module (OSC)
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
BREAK
MODULE
POWER-ON RESET
MODULE
MC68HLC908QY4 AND MC68HLC908QT4
4096 BYTES
KEYBOARD INTERRUPT
MODULE
8-BIT ADC
MC68HLC908QY2, MC68HLC908QY1,
MC68HLC908QT2, AND MC68HLC908QT1:
1536 BYTES
16-BIT TIMER
MODULE
USER FLASH
128 BYTES RAM
COP
MODULE
VDD
VSS
POWER SUPPLY
MONITOR ROM
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in
12.1 Introduction)
ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1
Figure 11-1. Block Diagram Highlighting OSC Block and Pins
MC68HLC908QY/QT Family Data Sheet, Rev. 3
90
Freescale Semiconductor
Functional Description
11.3.1.1 Internal Oscillator Trimming
The 8-bit trimming register, OSCTRIM, allows a clock period adjust of +127 and –128 steps. Increasing
OSCTRIM value increases the clock period. Trimming allows the internal clock frequency to be set to
4.0 MHz 5%.
All devices are programmed with a trim value in a reserved FLASH location, $FFC0. This value can be
copied from the FLASH to the OSCTRIM register ($0038) during reset initialization.
Reset loads OSCTRIM with a default value of $80.
WARNING
Bulk FLASH erasure will set location $FFC0 to $FF and the factory
programmed value will be lost.
11.3.1.2 Internal to External Clock Switching
When external clock source (external OSC, RC, or XTAL) is desired, the user must perform the following
steps:
1. For external crystal circuits only, OSCOPT[1:0] = 1:1: To help precharge an external crystal
oscillator, set PTA4 (OSC2) as an output and drive high for several cycles. This may help the
crystal circuit start more robustly.
2. Set CONFIG2 bits OSCOPT[1:0] according to . The oscillator module control logic will then set
OSC1 as an external clock input and, if the external crystal option is selected, OSC2 will also be
set as the clock output.
3. Create a software delay to wait the stabilization time needed for the selected clock source (crystal,
resonator, RC) as recommended by the component manufacturer. A good rule of thumb for crystal
oscillators is to wait 4096 cycles of the crystal frequency, i.e., for a 4-MHz crystal, wait
approximately 1 msec.
4. After the manufacturer’s recommended delay has elapsed, the ECGON bit in the OSC status
register (OSCSTAT) needs to be set by the user software.
5. After ECGON set is detected, the OSC module checks for oscillator activity by waiting two external
clock rising edges.
6. The OSC module then switches to the external clock. Logic provides a glitch free transition.
7. The OSC module first sets the ECGST bit in the OSCSTAT register and then stops the internal
oscillator.
NOTE
Once transition to the external clock is done, the internal oscillator will only
be reactivated with reset. No post-switch clock monitor feature is
implemented (clock does not switch back to internal if external clock dies).
11.3.2 External Oscillator
The external clock option is designed for use when a clock signal is available in the application to provide
a clock source to the microcontroller. The OSC1 pin is enabled as an input by the oscillator module. The
clock signal is used directly to create BUSCLKX4 and also divided by two to create BUSCLKX2.
In this configuration, the OSC2 pin cannot output BUSCLKX4. So the OSC2EN bit in the port A pullup
enable register will be clear to enable PTA4 I/O functions on the pin.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
91
Oscillator Module (OSC)
11.3.3 XTAL Oscillator
The XTAL oscillator circuit is designed for use with an external low-frequency crystal or ceramic resonator
to provide an accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal
circuit. The OSC2EN bit in the port A pullup enable register has no effect when this clock mode is
selected.
In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown
in Figure 11-2. This figure shows only the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five components:
•
•
•
•
•
Crystal, X1
Fixed capacitor, C1
Tuning capacitor, C2 (can also be a fixed capacitor)
Feedback resistor, RB
Series resistor, RS
FROM SIM
TO SIM
BUSCLKX4
XTALCLK
TO SIM
BUSCLKX2
÷ 2
SIMOSCEN
MCU
OSC1
OSC2
RS
RB
X1
C1
C2
Figure 11-2. XTAL Oscillator External Connections
11.3.4 RC Oscillator
The RC oscillator circuit is designed for use with an external resistor (REXT) to provide a clock source with
a tolerance within 25% of the expected frequency. See Figure 11-3.
The capacitor (C) for the RC oscillator is internal to the MCU. The REXT value must have a tolerance of
1% or less to minimize its effect on the frequency.
In this configuration, the OSC2 pin can be left in the reset state as PTA4. Or, the OSC2EN bit in the port
A pullup enable register can be set to enable the OSC2 output function on the pin. Enabling the OSC2
output slightly increases the external RC oscillator frequency, fRCCLK
.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
92
Freescale Semiconductor
Oscillator Module Signals
OSCRCOPT
TO SIM
FROM SIM
TO SIM
INTCLK
RCCLK
0
1
BUSCLKX4
BUSCLKX2
SIMOSCEN
EXTERNAL RC
OSCILLATOR
EN
÷ 2
1
0
PTA4
I/O
PTA4
OSC2EN
MCU
OSC1
PTA4/BUSCLKX4 (OSC2)
VDD
See Chapter 16 Electrical Specifications
for component value requirements.
REXT
Figure 11-3. RC Oscillator External Connections
11.4 Oscillator Module Signals
The following paragraphs describe the signals that are inputs to and outputs from the oscillator module.
11.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is either an input to the crystal oscillator amplifier, an input to the RC oscillator circuit, or
an external clock source.
For the internal oscillator configuration, the OSC1 pin can assume other functions according to Table 1-3.
Function Priority in Shared Pins.
11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4)
For the XTAL oscillator device, the OSC2 pin is the crystal oscillator inverting amplifier output.
For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function. The OSC2EN bit has
no effect.
For the internal oscillator or RC oscillator options, the OSC2 pin can assume other functions according to
Table 1-3. Function Priority in Shared Pins, or the output of the oscillator clock (BUSCLKX4).
Table 11-1. OSC2 Pin Function
Option
OSC2 Pin Function
Inverting OSC1
PTA4 I/O
XTAL oscillator
External clock
Internal oscillator
or
Controlled by OSC2EN bit in PTAPUE register
OSC2EN = 0: PTA4 I/O
RC oscillator
OSC2EN = 1: BUSCLKX4 output
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
93
Oscillator Module (OSC)
11.4.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables either the
XTAL oscillator circuit, the RC oscillator, or the internal oscillator.
11.4.4 XTAL Oscillator Clock (XTALCLK)
XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes
directly from the crystal oscillator circuit. Figure 11-2 shows only the logical relation of XTALCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be
unstable at start up.
11.4.5 RC Oscillator Clock (RCCLK)
RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of
external R and internal C. Figure 11-3 shows only the logical relation of RCCLK to OSC1 and may not
represent the actual circuitry.
11.4.6 Internal Oscillator Clock (INTCLK)
INTCLK is the internal oscillator output signal. Its nominal frequency is fixed to 4.0 MHz, but it can be also
trimmed using the oscillator trimming feature of the OSCTRIM register (see 11.3.1.1 Internal Oscillator
Trimming).
11.4.7 Oscillator Out 2 (BUSCLKX4)
BUSCLKX4 is the same as the input clock (XTALCLK, RCCLK, or INTCLK). This signal is driven to the
SIM module and is used to determine the COP cycles.
11.4.8 Oscillator Out (BUSCLKX2)
The frequency of this signal is equal to half of the BUSCLKX4, this signal is driven to the SIM for
generation of the bus clocks used by the CPU and other modules on the MCU. BUSCLKX2 will be divided
again in the SIM and results in the internal bus frequency being one fourth of either the XTALCLK,
RCCLK, or INTCLK frequency.
11.5 Low Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
11.5.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. BUSCLKX2 and BUSCLKX4 continue to drive
to the SIM module.
11.5.2 Stop Mode
The STOP instruction disables either the XTALCLK, the RCCLK, or INTCLK output, hence BUSCLKX2
and BUSCLKX4.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
94
Freescale Semiconductor
Oscillator During Break Mode
11.6 Oscillator During Break Mode
The oscillator continues to drive BUSCLKX2 and BUSCLKX4 when the device enters the break state.
11.7 CONFIG2 Options
Two CONFIG2 register options affect the operation of the oscillator module: OSCOPT1 and OSCOPT0.
All CONFIG2 register bits will have a default configuration. Refer to Chapter 5 Configuration Register
(CONFIG) for more information on how the CONFIG2 register is used.
Table 11-2 shows how the OSCOPT bits are used to select the oscillator clock source.
Table 11-2. Oscillator Modes
OSCOPT1
OSCOPT0
Oscillator Modes
Internal Oscillator
0
0
1
1
0
1
0
1
External Oscillator
External RC
External Crystal
11.8 Input/Output (I/O) Registers
The oscillator module contains these two registers:
1. Oscillator status register (OSCSTAT)
2. Oscillator trim register (OSCTRIM)
11.8.1 Oscillator Status Register
The oscillator status register (OSCSTAT) contains the bits for switching from internal to external clock
sources.
$0036
Address:
Bit 7
6
5
R
0
4
R
0
3
2
R
0
1
ECGON
0
Bit 0
Read:
Write:
Reset:
ECGST
R
R
R
0
0
0
0
= Reserved
= Unimplemented
R
Figure 11-4. Oscillator Status Register (OSCSTAT)
ECGON — External Clock Generator On Bit
This read/write bit enables external clock generator, so that the switching process can be initiated. This
bit is forced low during reset. This bit is ignored in monitor mode with the internal oscillator bypassed.
1 = External clock generator enabled
0 = External clock generator disabled
ECGST — External Clock Status Bit
This read-only bit indicates whether or not an external clock source is engaged to drive the system
clock.
1 = An external clock source engaged
0 = An external clock source disengaged
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
95
Oscillator Module (OSC)
11.8.2 Oscillator Trim Register (OSCTRIM)
$0038
Address:
Bit 7
6
TRIM6
0
5
TRIM5
0
4
TRIM4
0
3
TRIM3
0
2
TRIM2
0
1
TRIM1
0
Bit 0
TRIM0
0
Read:
Write:
Reset:
TRIM7
1
Figure 11-5. Oscillator Trim Register (OSCTRIM)
TRIM7–TRIM0 — Internal Oscillator Trim Factor Bits
These read/write bits change the size of the internal capacitor used by the internal oscillator. By
measuring the period of the internal clock and adjusting this factor accordingly, the frequency of the
internal clock can be fine tuned. Increasing (decreasing) this factor by one increases (decreases) the
period by approximately 0.2% of the untrimmed period (the period for TRIM = $80). The trimmed
frequency is guaranteed not to vary by more than 5% over the full specified range of temperature and
voltage. The reset value is $80, which sets the frequency to 4.0 MHz (1.0 MHz bus speed) 25%.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
96
Freescale Semiconductor
Chapter 12
Input/Output Ports (PORTS)
12.1 Introduction
The MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 have five bidirectional input-output
(I/O) pins and one input only pin. The MC68HLC908QY1, MC68HLC908QY2, and MC68HLC908QY4
have thirteen bidirectional pins and one input only pin. All I/O pins are programmable as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
8-pin devices have non-bonded pins. These pins should be configured
either as outputs driving low or high, or as inputs with internal pullups
enabled. Configuring these non-bonded pins in this manner will prevent any
excess current consumption caused by floating inputs.
12.2 Port A
Port A is a 6-bit special function port that shares all six of its pins with the keyboard interrupt (KBI) module
(see Chapter 9 Keyboard Interrupt Module (KBI)). Each port A pin also has a software configurable pullup
device if the corresponding port pin is configured as an input port.
NOTE
PTA2 is input only.
When the IRQ function is enabled in the configuration register 2
(CONFIG2), bit 2 of the port A data register (PTA) will always read a 0. In
this case, the BIH and BIL instructions can be used to read the logic level
on the PTA2 pin. When the IRQ function is disabled, these instructions will
behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will
read the actual logic level on the pin.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
97
Input/Output Ports (PORTS)
12.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the six port A pins.
$0000
Address:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
AWUL
PTA2
R
R
PTA5
PTA4
PTA3
PTA1
PTA0
Reset:
Unaffected by reset
KBI4 KBI3
Additional Functions:
KBI5
KBI2
KBI1
KBI0
= Reserved
= Unimplemented
Figure 12-1. Port A Data Register (PTA)
PTA[5:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
AWUL — Auto Wakeup Latch Data Bit
This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup
request signal is generated internally (see Chapter 4 Auto Wakeup Module (AWU)). There is no PTA6
port nor any of the associated bits such as PTA6 data register, pullup enable or direction.
KBI[5:0] — Port A Keyboard Interrupts
The keyboard interrupt enable bits, KBIE5–KBIE0, in the keyboard interrupt control enable register
(KBIER) enable the port A pins as external interrupt pins (see Chapter 9 Keyboard Interrupt Module
(KBI)).
12.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1
to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
$0004
Address:
Bit 7
6
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
0
1
DDRA1
0
Bit 0
DDRA0
0
Read:
Write:
Reset:
R
R
0
0
0
= Reserved
= Unimplemented
R
Figure 12-2. Data Direction Register A (DDRA)
DDRA[5:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
98
Freescale Semiconductor
Port A
Figure 12-3 shows the port A I/O logic.
READ DDRA ($0004)
PTAPUEx
WRITE DDRA ($0004)
RESET
DDRAx
PTAx
30 k
WRITE PTA ($0000)
PTAx
READ PTA ($0000)
TO KEYBOARD INTERRUPT CIRCUIT
Figure 12-3. Port A I/O Circuit
NOTE
Figure 12-3 does not apply to PTA2
When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When DDRAx is a 0, reading
address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit.
12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
if the six port A pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRAx, to be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRAx bit is configured as output.
$000B
Address:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
OSC2EN
0
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-4. Port A Input Pullup Enable Register (PTAPUE)
OSC2EN — Enable PTA4 on OSC2 Pin
This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is
selected. This bit has no effect for the XTAL or external oscillator options.
1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4)
0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup functions
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
99
Input/Output Ports (PORTS)
PTAPUE[5:0] — Port A Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup devices on port A pins.
1 = Corresponding port A pin configured to have internal pull if its DDRA bit is set to 0
0 = Pullup device is disconnected on the corresponding port A pin regardless of the state of its
DDRA bit
Table 12-1 summarizes the operation of the port A pins.
Table 12-1. Port A Pin Functions
Accesses to DDRA
Read/Write
Accesses to PTA
PTAPUE
Bit
DDRA
Bit
PTA
Bit
I/O Pin
Mode
Read
Write
(2)
X(1)
X
PTA5–PTA0(3)
PTA5–PTA0(3)
PTA5–PTA0(5)
1
0
X
0
0
1
DDRA5–DDRA0
DDRA5–DDRA0
DDRA5–DDRA0
Pin
Pin
Input, VDD
Input, Hi-Z(4)
Output
X
PTA5–PTA0
1. X = don’t care
2. I/O pin pulled to VDD by internal pullup.
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
5. Output does not apply to PTA2
12.3 Port B
Port B is an 8-bit general purpose I/O port. Port B is only available on the MC68HLC908QY1,
MC68HLC908QY2, and MC68HLC908QY4.
12.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port B pins.
$0001
Address:
Bit 7
PTB7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Unaffected by reset
Figure 12-5. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
100
Freescale Semiconductor
Port B
12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
$0005
Address:
Bit 7
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
DDRB7
0
Figure 12-6. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 12-7 shows the
port B I/O logic.
READ DDRB ($0005)
PTBPUEx
WRITE DDRB ($0005)
DDRBx
RESET
30 k
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 12-7. Port B I/O Circuit
When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading
address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit. Table 12-2 summarizes the operation of the port B pins.
Table 12-2. Port B Pin Functions
Accesses to DDRB
Read/Write
Accesses to PTB
Write
DDRB
Bit
PTB
Bit
I/O Pin
Mode
Read
Pin
X(1)
X
Input, Hi-Z(2)
Output
PTB7–PTB0(3)
PTB7–PTB0
0
1
DDRB7–DDRB0
DDRB7–DDRB0
Pin
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
101
Input/Output Ports (PORTS)
12.3.3 Port B Input Pullup Enable Register
The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each
of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRBx bit is configured as output.
$000C
Address:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE2 PTBPUE0
0
0
0
0
0
0
0
0
Figure 12-8. Port B Input Pullup Enable Register (PTBPUE)
PTBPUE[7:0] — Port B Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup devices on port B pins
1 = Corresponding port B pin configured to have internal pull if its DDRB bit is set to 0
0 = Pullup device is disconnected on the corresponding port B pin regardless of the state of its
DDRB bit.
Table 12-3 summarizes the operation of the port B pins.
Table 12-3. Port B Pin Functions
Accesses to DDRB
Read/Write
Accesses to PTB
PTBPUE
Bit
DDRB
Bit
PTB
Bit
I/O Pin
Mode
Read
Write
(2)
X(1)
X
PTB7–PTB0(3)
1
0
DDRB7–DDRB0
Pin
Input, VDD
Input, Hi-Z(4)
Output
PTB7–PTB0(3)
PTB7–PTB0
0
0
1
DDRB7–DDRB0
DDRB7–DDRB0
Pin
X
X
PTB7–PTB0
1. X = don’t care
2. I/O pin pulled to VDD by internal pullup.
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
MC68HLC908QY/QT Family Data Sheet, Rev. 3
102
Freescale Semiconductor
Chapter 13
System Integration Module (SIM)
13.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit
(MCU) activities. A block diagram of the SIM is shown in Figure 13-1. The SIM is a system state controller
that coordinates CPU and exception timing.
The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals
–
–
Stop/wait/reset/break entry and recovery
Internal clock control
•
•
Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
Interrupt control:
–
–
–
Acknowledge timing
Arbitration control timing
Vector address generation
•
CPU enable/disable timing
13.2 RST and IRQ Pins Initialization
RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be
activated by programing CONFIG2 accordingly. Refer to Chapter 5 Configuration Register (CONFIG).
Table 13-1. Signal Name Conventions
Signal Name
Description
BUSCLKX4
Buffered clock from the internal, RC or XTAL oscillator circuit.
The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM to
generate the internal bus clocks (bus clock = BUSCLKX4 ÷ 4).
BUSCLKX2
Address bus
Data bus
PORRST
IRST
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
R/W
Read/write signal
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
103
System Integration Module (SIM)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO OSCILLATOR)
SIM
COUNTER
COP CLOCK
BUSCLKX4 (FROM OSCILLATOR)
BUSCLKX2 (FROM OSCILLATOR)
÷2
VDD
CLOCK
CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
INTERNAL
PULL-UP
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
MASTER
RESET
CONTROL
COP TIMEOUT (FROM COP MODULE)
LVI RESET (FROM LVI MODULE)
SIM RESET STATUS REGISTER
FORCED MON MODE ENTRY (FROM MENRST MODULE)
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 13-1. SIM Block Diagram
13.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 13-2.
BUSCLKX4
BUSCLKX2
FROM
OSCILLATOR
SIM COUNTER
FROM
OSCILLATOR
BUS CLOCK
GENERATORS
÷ 2
SIM
Figure 13-2. SIM Clock Signals
MC68HLC908QY/QT Family Data Sheet, Rev. 3
104
Freescale Semiconductor
Reset and System Initialization
13.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four.
13.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The
IBUS clocks start upon completion of the time out.
13.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay time out. This time out is
selectable as 4096 or 32 BUSCLKX4 cycles. See 13.7.2 Stop Mode.
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
13.4 Reset and System Initialization
The MCU has these reset sources:
•
•
•
•
•
•
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 13.5 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). See 13.8 SIM Registers.
13.4.1 External Pin Reset
The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at
least the minimum tRL time. Figure 13-3 shows the relative timing. The RST pin function is only available
if the RSTEN bit is set in the CONFIG2 register.
BUSCLKX2
RST
VECT H VECT L
ADDRESS BUS
PC
Figure 13-3. External Reset Timing
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
105
System Integration Module (SIM)
13.4.2 Active Resets from Internal Sources
The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the
CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is set when
describing activity on the RST pin.
All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(see Figure 13-4). An internal reset can be caused by an illegal address, illegal opcode, COP time out,
LVI, or POR (see Figure 13-5).
NOTE
For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 13-4.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
IRST
RSTPULLED LOW BY MCU
32 CYCLES
RST
32 CYCLES
BUSCLKX4
ADDRESS
BUS
VECTOR HIGH
Figure 13-4. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
INTERNAL RESET
LVI
Figure 13-5. Sources of Internal Reset
Table 13-2. Reset Recovery Timing
Reset Recovery Type
POR/LVI
All others
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
106
Freescale Semiconductor
Reset and System Initialization
13.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
At power on, the following events occur:
•
•
•
•
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive BUSCLKX4.
Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow
stabilization of the oscillator.
•
The POR bit of the SIM reset status register (SRSR) is set.
See Figure 13-6.
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
BUSCLKX4
BUSCLKX2
RST
(RST PIN IS A GENERAL-PURPOSE INPUT AFTER A POR)
ADDRESS BUS
$FFFE
$FFFF
Figure 13-6. POR Recovery
13.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and stages 12–5 of the SIM counter. The SIM counter output, which occurs at least
every 4080 BUSCLKX4 cycles, drives the COP counter. The COP should be serviced as soon as possible
out of reset to guarantee the maximum amount of time before the first time out.
The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break
auxiliary register (BRKAR).
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
107
System Integration Module (SIM)
13.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an
illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal
reset sources.
13.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources. See Figure 2-1. Memory Map for memory ranges.
13.4.2.5 Low-Voltage Inhibit (LVI) Reset
The LVI asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIPF. The LVI
bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the
SIM counter counts out 4096 BUSCLKX4 cycles after VDD rises above VTRIPR. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
The SIM actively pulls down the (RST) pin for all internal reset sources.
13.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for
counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of BUSCLKX4.
13.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock
state machine.
13.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the
configuration register 1 (CONFIG1). If the SSREC bit is a 1, then the stop recovery is reduced from the
normal delay of 4096 BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications
using canned oscillators that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC cleared in the configuration
register 1 (CONFIG1).
MC68HLC908QY/QT Family Data Sheet, Rev. 3
108
Freescale Semiconductor
Exception Control
13.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see 13.7.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. See 13.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.
13.6 Exception Control
Normal sequential program execution can be changed in three different ways:
1. Interrupts
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
2. Reset
3. Break interrupts
13.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 13-7 flow charts the handling of system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 13-8 shows
interrupt entry timing. Figure 13-9 shows interrupt recovery timing.
13.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 13-10 demonstrates what happens when two interrupts are pending. If an interrupt
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
109
System Integration Module (SIM)
FROM RESET
YES
BREAK INTERRUPT?
NO
YES
I BIT SET?
NO
YES
YES
IRQ
INTERRUPT?
NO
TIMER
INTERRUPT?
NO
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
(AS MANY INTERRUPTS AS EXIST ON CHIP)
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
YES
NO
RTI
INSTRUCTION?
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
NO
Figure 13-7. Interrupt Processing
MC68HLC908QY/QT Family Data Sheet, Rev. 3
110
Freescale Semiconductor
Exception Control
MODULE
INTERRUPT
I BIT
ADDRESS BUS
DATA BUS
R/W
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H
VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8]
X
A
CCR
V DATA H V DATA L OPCODE
Figure 13-8. Interrupt Entry
MODULE
INTERRUPT
I BIT
ADDRESS BUS
DATA BUS
R/W
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
Figure 13-9. Interrupt Recovery
CLI
LDA #$FF
BACKGROUND ROUTINE
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 13-10. Interrupt Recognition Example
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
111
System Integration Module (SIM)
The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions.
However, in the case of the INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
13.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
13.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 13-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 13-3. Interrupt Sources
INT
Register
Flag
Vector
Address
Mask(1)
Priority
Source
Flag
Reset
—
—
—
—
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFE0–$FFE1
$FFDE–$FFDF
Highest
SWI instruction
—
—
IRQ pin
IRQF
CH0F
CH1F
TOF
IMASK
CH0IE
CH1IE
TOIE
IF1
IF3
IF4
IF5
IF14
IF15
Timer channel 0 interrupt
Timer channel 1 interrupt
Timer overflow interrupt
Keyboard interrupt
KEYF IMASKK
COCO AIEN
Lowest
ADC conversion complete interrupt
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI
instruction.
13.6.2.1 Interrupt Status Register 1
Address: $FE04
Bit 7
6
5
IF4
R
4
IF3
R
3
0
2
IF1
R
1
0
Bit 0
0
Read:
Write:
Reset:
0
IF5
R
0
R
R
0
R
0
R
0
0
0
0
0
R
= Reserved
Figure 13-11. Interrupt Status Register 1 (INT1)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
112
Freescale Semiconductor
Exception Control
IF1 and IF3–IF5 — Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 13-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, 3, and 7 — Always read 0
13.6.2.2 Interrupt Status Register 2
Address: $FE05
Bit 7
IF14
R
6
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
R
R
0
R
0
R
0
R
0
R
0
R
0
0
0
R
= Reserved
Figure 13-12. Interrupt Status Register 2 (INT2)
IF14 — Interrupt Flags
This flag indicates the presence of interrupt requests from the sources shown in Table 13-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0–6 — Always read 0
13.6.2.3 Interrupt Status Register 3
Address: $FE06
Bit 7
0
6
5
0
4
0
3
0
2
0
1
0
Bit 0
IF15
R
Read:
Write:
Reset:
0
R
R
R
0
R
0
R
0
R
0
R
0
0
0
0
R
= Reserved
Figure 13-13. Interrupt Status Register 3 (INT3)
IF15 — Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 13-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 1–7 — Always read 0
13.6.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
13.6.4 Break Interrupts
The break module can stop normal program flow at a software programmable break point by asserting its
break interrupt output. (See Chapter 15 Development Support.) The SIM puts the CPU into the break
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
113
System Integration Module (SIM)
state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to
see how each module is affected by the break state.
13.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
13.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing
interrupts to occur.
13.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 13-14 shows
the timing for wait mode entry.
ADDRESS BUS
DATA BUS
R/W
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 13-14. Wait Mode Entry Timing
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode
sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD,
in the configuration register is 0, then the computer operating properly module (COP) is enabled and
remains active in wait mode.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
114
Freescale Semiconductor
Low-Power Modes
Figure 13-15 and Figure 13-16 show the timing for wait recovery.
ADDRESS BUS
DATA BUS
$6E0B
$A6
$6E0C
$00FF
$00FE
$00FD
$00FC
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt
Figure 13-15. Wait Recovery from Interrupt
32
CYCLES
32
CYCLES
ADDRESS BUS
$6E0B
$A6
RSTVCTH RSTVCTL
DATA BUS $A6
$A6
RST(1)
BUSCLKX4
1. RST is only available if the RSTEN bit in the CONFIG1 register is set.
Figure 13-16. Wait Recovery from Internal Reset
13.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU
and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles
down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do
not require long start-up times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
115
System Integration Module (SIM)
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 13-17 shows stop mode entry timing and
Figure 13-18 shows the stop mode recovery time from interrupt or break
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
ADDRESS BUS
DATA BUS
R/W
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 13-17. Stop Mode Entry Timing
STOP RECOVERY PERIOD
BUSCLKX4
INTERRUPT
ADDRESS BUS
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
Figure 13-18. Stop Mode Recovery from Interrupt
13.8 SIM Registers
The SIM has three memory mapped registers. Table 13-4 shows the mapping of these registers.
Table 13-4. SIM Registers
Address
$FE00
$FE01
$FE03
Register
BSR
Access Mode
User
SRSR
BFCR
User
User
MC68HLC908QY/QT Family Data Sheet, Rev. 3
116
Freescale Semiconductor
SIM Registers
13.8.1 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the
register. All other reset sources set the individual flag bits but do not clear the register. More than one
reset source can be flagged at any time depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.
$FE01
Address:
Bit 7
6
5
4
3
2
1
Bit 0
0
Read:
Write:
POR:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 13-19. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (illegal attempt to fetch an opcode from an unimplemented
address)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
POR while IRQ ≠ VTST
0 = POR or read of SRSR
LVI — Low Voltage Inhibit Reset bit
1 = Last reset caused by LVI circuit
0 = POR or read of SRSR
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
117
System Integration Module (SIM)
13.8.2 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
$FE03
Address:
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
= Reserved
R
Figure 13-20. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HLC908QY/QT Family Data Sheet, Rev. 3
118
Freescale Semiconductor
Chapter 14
Timer Interface Module (TIM)
14.1 Introduction
This section describes the timer interface module (TIM). The TIM is a two-channel timer that provides a
timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 14-2
is a block diagram of the TIM.
14.2 Features
Features of the TIM include the following:
•
Two input capture/output compare channels
–
–
Rising-edge, falling-edge, or any-edge input capture trigger
Set, clear, or toggle output compare action
•
•
Buffered and unbuffered pulse width modulation (PWM) signal generation
Programmable TIM clock input
–
–
7-frequency internal bus clock prescaler selection
External TIM clock input
•
•
•
Free-running or modulo up-count operation
Toggle any channel pin on overflow
TIM counter stop and reset bits
14.3 Pin Name Conventions
The TIM shares two input/output (I/O) pins with two port A I/O pins. The full names of the TIM I/O pins are
listed in Table 14-1. The generic pin name appear in the text that follows.
Table 14-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM Pin Names:
TCH0
TCH1
TCLK
PTA0/TCH0
PTA1/TCH1
PTA2/TCLK
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
119
Timer Interface Module (TIM)
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
BREAK
MODULE
POWER-ON RESET
MODULE
MC68HLC908QY4 AND MC68HLC908QT4
4096 BYTES
KEYBOARD INTERRUPT
MODULE
8-BIT ADC
MC68HLC908QY2, MC68HLC908QY1,
MC68HLC908QT2, AND MC68HLC908QT1:
1536 BYTES
16-BIT TIMER
MODULE
USER FLASH
128 BYTES RAM
COP
MODULE
VDD
VSS
POWER SUPPLY
MONITOR ROM
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in
12.1 Introduction)
ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1
Figure 14-1. Block Diagram Highlighting TIM Block and Pins
MC68HLC908QY/QT Family Data Sheet, Rev. 3
120
Freescale Semiconductor
Functional Description
14.4 Functional Description
Figure 14-2 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value
at any time without affecting the counting sequence.
The two TIM channels are programmable independently as input capture or output compare channels.
PTA2/IRQ/KBI2/TCLK
PRESCALER SELECT
INTERNAL
PRESCALER
BUS CLOCK
TSTOP
PS2
PS1
PS0
TRST
16-BIT COUNTER
TOF
INTERRUPT
LOGIC
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
ELS0B
ELS0A
PORT
LOGIC
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0MAX
TCH0
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
CH0IE
MS0A
MS0B
CH1F
TOV1
ELS1B
ELS1A
PORT
LOGIC
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1MAX
TCH1
INTERRUPT
LOGIC
16-BIT LATCH
CH1IE
MS1A
Figure 14-2. TIM Block Diagram
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
121
Timer Interface Module (TIM)
14.4.1 TIM Counter Prescaler
The TIM clock source is one of the seven prescaler outputs or the TIM clock pin, TCLK. The prescaler
generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register (TSC) select the TIM clock source.
14.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM central processor unit (CPU) interrupt requests.
14.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
14.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 14.4.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
•
When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
•
When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
14.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
TCH0 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
MC68HLC908QY/QT Family Data Sheet, Rev. 3
122
Freescale Semiconductor
Functional Description
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare
function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
14.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM
signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 14-3 shows, the output compare value in the TIM channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM
to clear the channel pin on output compare if the state of the PWM pulse is logic 1 (ELSxA = 0). Program
the TIM to set the pin if the state of the PWM pulse is logic 0 (ELSxA = 1).
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is 000. See 14.9.1 TIM Status and Control Register.
The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of
an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers
produces a duty cycle of 128/256 or 50%.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
POLARITY = 1
(ELSxA = 0)
TCHx
TCHx
PULSE
WIDTH
POLARITY = 0
(ELSxA = 1)
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 14-3. PWM Period and Pulse Width
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
123
Timer Interface Module (TIM)
14.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 14.4.4 Pulse Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect
operation for up to two PWM periods. For example, writing a new value before the counter reaches the
old value but after the counter reaches the new value prevents any compare during that PWM period.
Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the
compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
•
When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
•
When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in
the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM
period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
14.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.
The TIM channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM
channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
124
Freescale Semiconductor
Interrupts
14.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM
period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB:MSxA. See Table 14-3.
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must
force the output to the complement of the pulse width level. See Table 14-3.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel
0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0
(TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. See 14.9.4 TIM Channel Status and Control Registers.
14.5 Interrupts
The following TIM sources can generate interrupt requests:
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
•
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE =1.
CHxF and CHxIE are in the TIM channel x status and control register.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
125
Timer Interface Module (TIM)
14.6 Wait Mode
The WAIT instruction puts the MCU in low power-consumption standby mode.
The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
14.7 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See 13.8.2 Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
14.8 Input/Output Signals
Port A shares three of its pins with the TIM. Two TIM channel I/O pins are PTA0/TCH0 and PTA1/TCH1
and an alternate clock source is PTA2/TCLK.
14.8.1 TIM Clock Pin (PTA2/TCLK)
PTA2/TCLK is an external clock input that can be the clock source for the TIM counter instead of the
prescaled internal bus clock. Select the PTA2/TCLK input by writing 1s to the three prescaler select bits,
PS[2–0]. (See 14.9.1 TIM Status and Control Register.) When the PTA2/TCLK pin is the TIM clock input,
it is an input regardless of port pin initialization.
14.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTA0/TCH0 can be configured as a buffered output compare or buffered PWM pin.
14.9 Input/Output Registers
The following I/O registers control and monitor operation of the TIM:
•
•
•
•
•
TIM status and control register (TSC)
TIM counter registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0 and TSC1)
TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
126
Freescale Semiconductor
Input/Output Registers
14.9.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
•
•
•
•
•
Enables TIM overflow interrupts
Flags TIM overflows
Stops the TIM counter
Resets the TIM counter
Prescales the TIM counter clock
Address: $0020
Bit 7
TOF
0
6
TOIE
0
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TRST
0
0
0
= Unimplemented
Figure 14-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete,
then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode. When the TSTOP bit is set and the timer is configured for
input capture operation, input captures are inhibited until the TSTOP bit is
cleared.
When using TSTOP to stop the timer counter, see if any timer flags are set.
If a timer flag is set, it must be cleared by clearing TSTOP, then clearing the
flag, then setting TSTOP again.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
127
Timer Interface Module (TIM)
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as a 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTA2/TCLK pin or one of the seven prescaler outputs as the
input to the TIM counter as Table 14-2 shows. Reset clears the PS[2:0] bits.
Table 14-2. Prescaler Selection
PS2
0
PS1
0
PS0
0
TIM Clock Source
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
PTA2/TCLK
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
14.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
128
Freescale Semiconductor
Input/Output Registers
Address: $0021
Bit 7
TCNTH
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0
0
0
0
0
0
0
0
$0022
TCNTL
6
Address:
Bit 7
Bit 7
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-5. TIM Counter Registers (TCNTH:TCNTL)
14.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter
reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow
interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: $0023
Bit 7
TMODH
6
5
Bit 13
1
4
Bit 12
1
3
Bit 11
1
2
Bit 10
1
1
Bit 9
1
Bit 0
Bit 8
1
Read:
Write:
Reset:
Bit 15
1
Bit 14
1
Address: $0024
Bit 7
TMODL
6
5
Bit 5
1
4
Bit 4
1
3
Bit 3
1
2
Bit 2
1
1
Bit 1
1
Bit 0
Bit 0
1
Read:
Write:
Reset:
Bit 7
1
Bit 6
1
Figure 14-6. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
129
Timer Interface Module (TIM)
14.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
•
•
•
•
•
•
•
•
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Address: $0025
Bit 7
TSC0
6
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read:
Write:
Reset:
CH0F
CH0IE
0
0
0
$0028
TSC1
Address:
Bit 7
CH1F
0
6
CH1IE
0
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read:
Write:
Reset:
0
0
= Unimplemented
Figure 14-7. TIM Channel Status and Control
Registers (TSC0:TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
Clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a
0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing
a 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing
of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM
channel 0 status and control register.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
130
Freescale Semiconductor
Input/Output Registers
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation.
See Table 14-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Table 14-3).
Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
Table 14-3. Mode, Edge, and Level Selection
MSxB
MSxA
ELSxB
ELSxA
Mode
Configuration
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
X
X
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
1
1
1
X
X
X
0
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
Output preset
Input capture
Toggle output on compare
Output compare
or PWM
Clear output on compare
Set output on compare
Toggle output on compare
Buffered output
compare or
buffered PWM
Clear output on compare
Set output on compare
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
131
Timer Interface Module (TIM)
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin. Table 14-3 shows how ELSxB and ELSxA work. Reset clears
the ELSxB and ELSxA bits.
NOTE
After initially enabling a TIM channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is a 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As Figure 14-8 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 14-8. CHxMAX Latency
14.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
132
Freescale Semiconductor
Input/Output Registers
Address: $0026
Bit 7
TCH0H
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after reset
$0027
TCH0L
6
Address:
Bit 7
Bit 7
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after reset
$0029
TCH1H
6
Address:
Bit 7
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after reset
$02A
TCH1L
6
Address:
Bit 7
Bit 7
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after reset
Figure 14-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
133
Timer Interface Module (TIM)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
134
Freescale Semiconductor
Chapter 15
Development Support
15.1 Introduction
This section describes the break module, the monitor read-only memory (MON), and the monitor mode
entry methods.
15.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
Features include:
•
•
•
•
Accessible input/output (I/O) registers during the break Interrupt
Central processor unit (CPU) generated break interrupts
Software-generated break interrupts
Computer operating properly (COP) disabling during break interrupts
15.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU
to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to
$FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
•
A CPU generated address (the address in the program counter) matches the contents of the break
address registers.
•
Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the microcontroller unit (MCU) to normal operation.
Figure 15-2 shows the structure of the break module.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
135
Development Support
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
CLOCK
GENERATOR
(OSCILLATOR)
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
BREAK
MODULE
POWER-ON RESET
MODULE
MC68HLC908QY4 AND MC68HLC908QT4
4096 BYTES
KEYBOARD INTERRUPT
MODULE
8-BIT ADC
MC68HLC908QY2, MC68HLC908QY1,
MC68HLC908QT2, AND MC68HLC908QT1:
1536 BYTES
16-BIT TIMER
MODULE
USER FLASH
128 BYTES RAM
COP
MODULE
VDD
VSS
POWER SUPPLY
MONITOR ROM
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in
12.1 Introduction)
ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1
Figure 15-1. Block Diagram Highlighting BRK and MON Blocks
ADDRESS BUS[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
ADDRESS BUS[15:0]
CONTROL
BKPT (TO SIM)
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
ADDRESS BUS[7:0]
Figure 15-2. Break Module Block Diagram
MC68HLC908QY/QT Family Data Sheet, Rev. 3
136
Freescale Semiconductor
Break Module (BRK)
When the internal address bus matches the value written in the break address registers or when software
writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt timing is:
•
•
•
When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode. When software does not
change the break address and clears the BRKA bit in the first break interrupt routine, the next break
interrupt will not be generated after exiting the interrupt routine even when the internal address bus
matches the value written in the break address registers.
15.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See 13.8.2 Break Flag Control Register and the Break Interrupts subsection
for each module.
15.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
15.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
15.2.2 Break Module Registers
These registers control and monitor operation of the break module:
•
•
•
•
•
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
137
Development Support
15.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
$FE0B
Bit 7
Address:
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
BRKE
0
0
0
0
0
0
0
= Unimplemented
Figure 15-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to
bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = Break address match
0 = No break address match
15.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
$FE09
Address:
Bit 7
6
Bit 14
0
5
Bit 13
0
4
Bit 12
0
3
Bit 11
0
2
Bit 10
0
1
Bit 9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Bit 15
0
Figure 15-4. Break Address Register High (BRKH)
$FE0A
Address:
Bit 7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
Bit 0
Bit 0
0
Read:
Write:
Reset:
Figure 15-5. Break Address Register Low (BRKL)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
138
Freescale Semiconductor
Break Module (BRK)
15.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
$FE02
Address:
Bit 7
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
BDCOP
0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-6. Break Auxiliary Register (BRKAR)
BDCOP — Break Disable COP Bit
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt.
15.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
SBSW
Note(1)
0
R
R
R
R
R
R
R
= Reserved
1. Writing a 0 clears SBSW.
Figure 15-7. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
15.2.2.5 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
$FE03
Address:
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
= Reserved
R
Figure 15-8. Break Flag Control Register (BFCR)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
139
Development Support
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
15.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If enabled,
the break module will remain enabled in wait and stop modes. However, since the internal address bus
does not increment in these modes, a break interrupt will never be triggered.
15.3 Monitor Module (MON)
This subsection describes the monitor module (MON) and the monitor mode entry methods. The monitor
allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with
a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as
long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for
in-circuit programming.
Features include:
•
•
•
•
•
•
•
•
•
Normal user-mode pin functionality on most pins
One pin dedicated to serial communication between MCU and host computer
Standard non-return-to-zero (NRZ) communication with host computer
Execution of code in random-access memory (RAM) or FLASH
FLASH memory security feature(1)
FLASH memory programming interface
Use of external 9.8304 MHz oscillator to generate internal frequency of 2.4576 MHz
Simple internal oscillator mode of operation (no external clock or high voltage)
Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain
$FF)
•
Standard monitor mode entry if high voltage is applied to IRQ
15.3.1 Functional Description
Figure 15-9 shows a simplified diagram of monitor mode entry.
The monitor module receives and executes commands from a host computer. Figure 15-10, Figure 15-11,
and Figure 15-12 show example circuits used to enter monitor mode and communicate with a host
computer via a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
140
Freescale Semiconductor
Monitor Module (MON)
POR RESET
YES
NO
IRQ = VTST
?
CONDITIONS
FROM Table 15-1
PTA0 = 1,
PTA1 = 1, AND
PTA4 = 0?
PTA0 = 1,
RESET VECTOR
BLANK?
NO
NO
YES
YES
FORCED
MONITOR MODE
NORMAL
USER MODE
NORMAL
MONITOR MODE
INVALID
USER MODE
HOST SENDS
8 SECURITY BYTES
YES
IS RESET
POR?
NO
ARE ALL
SECURITY BYTES
CORRECT?
YES
NO
ENABLE FLASH
DISABLE FLASH
MONITOR MODE ENTRY
DEBUGGING
AND FLASH
PROGRAMMING
(IF FLASH
IS ENABLED)
EXECUTE
MONITOR CODE
NO
YES
DOES RESET
OCCUR?
Figure 15-9. Simplified Monitor Mode Entry Flowchart
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
141
Development Support
VDD
VDD
10 kΩ*
VDD
RST (PTA3)
0.1 µF
9.8304 MHz CLOCK
VTST
MAX232
VDD
OSC1 (PTA5)
1
16
15
2
C1+
+
+
+
VDD
1 µF
1 µF
3
4
C1–
C2+
1 µF
+
1 kΩ
10 kΩ*
10 kΩ*
PTA1
V+
V–
IRQ (PTA2)
VDD
1 µF
6
5
9.1 V
C2–
1 µF
10 kΩ
+
PTA4
74HC125
6
DB9
5
10
9
2
7
8
PTA0
74HC125
3
2
4
3
5
VSS
1
* Value not critical
Figure 15-10. Monitor Mode Circuit (External Clock, with High Voltage)
VDD
N.C.
RST (PTA3)
VDD
0.1 µF
MAX232
VDD
1
16
15
2
9.8304 MHz CLOCK
C1+
OSC1 (PTA5)
+
+
1 µF
1 µF
3
4
1 µF
C1–
C2+
+
PTA1
N.C.
N.C.
10 kΩ*
V+
V–
VDD
+
IRQ (PTA2)
1 µF
6
PTA4
5
C2–
1 µF
10 kΩ
+
74HC125
DB9
5
10
9
2
7
8
6
PTA0
74HC125
3
4
3
5
2
VSS
1
* Value not critical
Figure 15-11. Monitor Mode Circuit (External Clock, No High Voltage)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
142
Freescale Semiconductor
Monitor Module (MON)
VDD
N.C.
N.C.
RST (PTA3)
VDD
0.1 µF
MAX232
VDD
OSC1 (PTA5)
IRQ (PTA2)
1
16
15
2
C1+
+
+
+
1 µF
1 µF
PTA1
PTA4
N.C.
N.C.
3
4
1 µF
C1–
C2+
+
10 kΩ*
VDD
V+
V–
1 µF
6
5
C2–
1 µF
10 kΩ
+
74HC125
DB9
5
10
9
2
7
8
6
PTA0
VSS
74HC125
3
2
4
3
5
1
* Value not critical
Figure 15-12. Monitor Mode Circuit (Internal Clock, No High Voltage)
The monitor code has been updated from previous versions of the monitor code to allow enabling the
internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out
of reset, is intended to support serial communication/programming at 4800 baud in monitor mode by using
the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if
programmed) to generate the desired internal frequency (1.0 MHz). Since this feature is enabled only
when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value
is not $FFFF) because entry into monitor mode in this case requires VTST on IRQ. The IRQ pin must
remain low during this monitor session in order to maintain communication.
Table 15-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
•
•
•
If $FFFE and $FFFF do not contain $FF (programmed state):
–
–
The external clock is 9.8304 MHz
IRQ = VTST
If $FFFE and $FFFF contain $FF (erased state):
–
–
The external clock is 9.8304 MHz
IRQ = VDD (this can be implemented through the internal IRQ pullup)
If $FFFE and $FFFF contain $FF (erased state):
IRQ = VSS (internal oscillator is selected, no external clock required)
–
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the
values on PTA1 and PTA4 pins can be changed.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
143
Development Support
Table 15-1. Monitor Mode Signal Requirements and Options
Serial
Communi-
cation
Mode
Selection
Communication
Speed
IRQ
RST
Reset
Mode
COP
Comments
(PTA2) (PTA3) Vector
External
Clock
Bus
Baud
PTA0
PTA1 PTA4
Frequency Rate
Normal
Monitor
9.8304
MHz
2.4576
9600
MHz
Provide external
clock at OSC1.
VTST
VDD
VSS
X
VDD
X
1
1
1
X
1
X
X
X
0
X
X
X
Disabled
Disabled
Disabled
Enabled
$FFFF
(blank)
9.8304
MHz
2.4576
9600
MHz
Provide external
clock at OSC1.
X
X
X
Forced
Monitor
$FFFF
(blank)
1.0 MHz
4800
Internal clock is
active.
X
X
(Trimmed)
Not
$FFFF
User
X
X
MON08
Function
[Pin No.]
VTST
[6]
RST
[4]
COM
[8]
MOD0 MOD1
[12] [10]
OSC1
[13]
—
—
—
—
1. PTA0 must have a pullup resistor to VDD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus
frequency / 256 and baud rate using internal oscillator is bus frequency / 206.
3. External clock is a 9.8304 MHz oscillator on OSC1.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC
NC
NC
NC
NC
1
3
5
7
9
2
4
6
8
GND
RST
IRQ
PTA0
10 PTA4
12 PTA1
14 NC
NC 11
OSC1 13
VDD
15
16 NC
Once out of reset, the MCU waits for the host to send eight security bytes (see 15.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
15.3.1.1 Normal Monitor Mode
RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as VTST is
applied to the IRQ pin. If the IRQ pin is lowered (no longer VTST) then the chip will still be operating in
monitor mode, but the pin functions will be determined by the settings in the configuration registers (see
Chapter 5 Configuration Register (CONFIG)) when VTST was lowered. With VTST lowered, the BIH and
BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register.
If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to
IRQ.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
144
Freescale Semiconductor
Monitor Module (MON)
15.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions,
(PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit
programming.
NOTE
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial power-on reset (POR). Once the reset
vector has been programmed, the traditional method of applying a voltage,
VTST, to IRQ must be used to enter monitor mode.
If monitor mode was entered as a result of the reset vector being blank, the COP is always disabled
regardless of the state of IRQ.
If the voltage applied to the IRQ is less than VTST, the MCU will come out of reset in user mode. Internal
circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors
are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode without requiring high
voltage on the IRQ pin. Once out of reset, the monitor code is initially executing with the internal clock at
its default frequency.
If IRQ is held high, all pins will default to regular input port functions except for PTA0 and PTA5 which will
operate as a serial communication port and OSC1 input respectively (refer to Figure 15-11). That will
allow the clock to be driven from an external source through OSC1 pin.
If IRQ is held low, all pins will default to regular input port function except for PTA0 which will operate as
serial communication port. Refer to Figure 15-12.
Regardless of the state of the IRQ pin, it will not function as a port input pin in monitor mode. Bit 2 of the
Port A data register will always read 0. The BIH and BIL instructions will behave as if the IRQ pin is
enabled, regardless of the settings in the configuration register. See Chapter 5 Configuration Register
(CONFIG).
The COP module is disabled in forced monitor mode. Any reset other than a power-on reset (POR) will
automatically force the MCU to come back to the forced monitor mode.
15.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
NOTE
Exiting monitor mode after it has been initiated by having a blank reset
vector requires a power-on reset (POR). Pulling RST (when RST pin
available) low will not exit monitor mode in this situation.
Table 15-2 summarizes the differences between user mode and monitor mode regarding vectors.
Table 15-2. Mode Difference
Functions
Modes
Reset
Reset
Break
Break
SWI
SWI
Vector High Vector Low Vector High Vector Low Vector High Vector Low
User
$FFFE
$FEFE
$FFFF
$FEFF
$FFFC
$FEFC
$FFFD
$FEFD
$FFFC
$FEFC
$FFFD
$FEFD
Monitor
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
145
Development Support
15.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
NEXT
START
BIT
START
BIT
BIT 6
STOP
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 7
Figure 15-13. Monitor Data Format
15.3.1.5 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 15-14. Break Transaction
15.3.1.6 Baud Rate
The monitor communication baud rate is controlled by the frequency of the external or internal oscillator
and the state of the appropriate pins as shown in Table 15-1.
Table 15-1 also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the
bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in
forced monitor mode, the effective baud rate is the bus frequency divided by 206.
15.3.1.7 Commands
The monitor ROM firmware uses these commands:
•
•
•
•
•
•
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
NOTE
Wait one bit time after each echo before sending the next byte.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
146
Freescale Semiconductor
Monitor Module (MON)
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
READ
READ
DATA
4
4
1
1
4
1
3, 2
4
ECHO
RETURN
Notes:
1 = Echo delay, approximately 2 bit times
2 = Data return delay, approximately 2 bit times
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-15. Read Transaction
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
WRITE
WRITE
3
3
1
1
3
1
3
1
2, 3
ECHO
Notes:
1 = Echo delay, approximately 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 15-16. Write Transaction
A brief description of each monitor mode command is given in Table 15-3 through Table 15-8.
Table 15-3. READ (Read Memory) Command
Description Read byte from memory
Operand 2-byte address in high-byte:low-byte order
Data Returned Returns contents of specified address
Opcode $4A
Command Sequence
SENT TO MONITOR
ADDRESS ADDRESS ADDRESS
HIGH HIGH LOW
ADDRESS
LOW
READ
READ
DATA
ECHO
RETURN
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
147
Development Support
Table 15-4. WRITE (Write Memory) Command
Description Write byte to memory
2-byte address in high-byte:low-byte order; low byte followed by data
byte
Operand
Data Returned None
Opcode $49
Command Sequence
FROM HOST
ADDRESS ADDRESS ADDRESS ADDRESS
HIGH HIGH LOW LOW
DATA
DATA
WRITE
ECHO
WRITE
Table 15-5. IREAD (Indexed Read) Command
Description Read next 2 bytes in memory from last address accessed
Operand None
Data Returned Returns contents of next two addresses
Opcode $1A
Command Sequence
FROM HOST
IREAD
IREAD
DATA
DATA
ECHO
RETURN
Table 15-6. IWRITE (Indexed Write) Command
Description Write to last address accessed + 1
Operand Single data byte
Data Returned None
Opcode $19
Command Sequence
FROM HOST
DATA
DATA
IWRITE
ECHO
IWRITE
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full
64-Kbyte memory map.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
148
Freescale Semiconductor
Monitor Module (MON)
Table 15-7. READSP (Read Stack Pointer) Command
Description Reads stack pointer
Operand None
Returns incremented stack pointer value (SP + 1) in
high-byte:low-byte order
Opcode $0C
Data Returned
Command Sequence
FROM HOST
SP
HIGH
SP
LOW
READSP
ECHO
READSP
RETURN
Table 15-8. RUN (Run User Program) Command
Description Executes PULH and RTI instructions
Operand None
Data Returned None
Opcode $28
Command Sequence
FROM HOST
RUN
ECHO
RUN
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command
tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program. The READSP command returns
the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at
addresses SP + 5 and SP + 6.
SP
HIGH BYTE OF INDEX REGISTER
CONDITION CODE REGISTER
ACCUMULATOR
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
SP + 7
LOW BYTE OF INDEX REGISTER
HIGH BYTE OF PROGRAM COUNTER
LOW BYTE OF PROGRAM COUNTER
Figure 15-17. Stack Pointer at Monitor Mode Entry
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
149
Development Support
15.3.2 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code from FLASH. Security remains
bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed
and security code entry is not required. See Figure 15-18.
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an
illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break
character, signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $80 is
set. If it is, then the correct security code has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation
clears the security code locations so that all eight security bytes become $FF (blank).
VDD
4096 + 32 CGMXCLK CYCLES
RST
FROM HOST
PA0
1
4
3
1
2
3
1
1
FROM MCU
Notes:
1 = Echo delay, approximately 2 bit times
2 = Data return delay, approximately 2 bit times
3 = Wait 1 bit time before sending next byte
4 = Wait until clock is stable and monitor runs
Figure 15-18. Monitor Mode Entry Timing
MC68HLC908QY/QT Family Data Sheet, Rev. 3
150
Freescale Semiconductor
Chapter 16
Electrical Specifications
16.1 Introduction
This section contains electrical and timing specifications.
16.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without
permanently damaging it.
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 16.5 DC Electrical Characteristics for guaranteed operating
conditions.
Characteristic(1)
Symbol
VDD
VIN
Value
Unit
V
Supply voltage
Input voltage
–0.3 to +6.0
VSS –0.3 to VDD +0.3
VSS –0.3 to +9.1
V
VTST
I
IPTA0— PTA5
Mode entry voltage, IRQ pin
V
Maximum current per pin excluding PTA0–PTA5, VDD, and VSS
15
25
mA
mA
°C
mA
mA
I
Maximum current for pins PTA0–PTA5
Storage temperature
TSTG
IMVSS
IMVDD
–55 to +150
100
Maximum current out of VSS
Maximum current into VDD
100
1. Voltages references to VSS
.
NOTE
This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD.)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
151
Electrical Specifications
16.3 Functional Operating Range
Temp
Code
Characteristic
Symbol
Value
Unit
Operating temperature range (TL to TH)
TA
–40 to 85
0 to 70
°C
C
—
Operating voltage range(1) (VDDMIN to VDDMAX
–40 to 85°C
0 to 70°C
)
VDD
2.4 to 3.6
2.2 to 3.6
V
C
—
1. VDD must be above VTRIPR upon power on.
16.4 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
8-pin PDIP
8-pin SOIC
105
142
173
76
90
133
θJA
8-pin DFN
°C/W
16-pin PDIP
16-pin SOIC
16-pin TSSOP
PI/O
PD
I/O pin power dissipation
Power dissipation(1)
User determined
W
W
PD = (IDD x VDD
)
+ PI/O = K/(TJ + 273°C)
PD x (TA + 273°C)
Constant(2)
K
W/°C
+ PD2 x θJA
TJ
TA + (PD x θJA)
Average junction temperature
°C
°C
TJM
Maximum junction temperature
150
1. Power dissipation is a function of temperature.
2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ
can be determined for any value of TA.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
152
Freescale Semiconductor
DC Electrical Characteristics
16.5 DC Electrical Characteristics
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
Output high voltage (for VDD > 2.7 V)
ILoad = –4 mA
ILoad = –10 mA, PTA0, PTA1, PTA3–PTA5 only
VDD–0.8
VDD–0.8
VOH
—
—
—
—
V
Output high voltage (for VDDMIN < VDD < VDDMAX
)
VDD–0.8
VDD–0.8
ILoad = –2 mA
ILoad = –5 mA, PTA0, PTA1, PTA3–PTA5 only
VOH
VOL
VOL
—
—
—
—
V
V
V
Output low voltage (for VDD > 2.7 V)
ILoad = 4 mA
ILoad = 10 mA, PTA0, PTA1, PTA3–PTA5 only
—
—
—
—
0.8
0.8
Output low voltage (for VDDMIN < VDD < VDDMAX
ILoad = 2 mA
ILoad = 5 mA, PTA0, PTA1, PTA3–PTA5 only
)
—
—
—
—
0.8
0.8
Maximum combined IOH (all I/O pins)
Maximum combined IOL (all I/O pins)
IOHT
IOLT
—
—
—
—
50
50
mA
mA
Input high voltage
PTA0–PTA5, PTB0–PTB7
VIH
VIL
0.7 x VDD
VSS
VDD
—
—
V
V
Input low voltage
PTA0–PTA5, PTB0–PTB7
0.3 x VDD
VHYS
IINJ
0.06 x VDD
–2
Input hysteresis
—
—
—
—
+2
V
DC injection current, all ports
Total dc current injection (sum of all I/O)
mA
mA
IINJTOT
–25
+25
Digital I/O ports Hi-Z leakage current
Typical at 25°C
–1
—
—
0.1
+1
—
IIL
µA
µA
IIN
Digital input only ports leakage current (PA2/IRQ/KBI2)
–1
—
+1
Capacitance
Ports (as input)
Ports (as output)
CIN
COUT
—
—
—
—
12
8
pF
POR rearm voltage(3)
VPOR
RPOR
VTST
0
—
—
—
100
—
mV
V/ms
V
POR rise time ramp rate(4)
Monitor mode entry voltage
0.035
VDD + 2.5
9.1
Pullup resistors(5)
PTA0–PTA5, PTB0–PTB7
RPU
16
26
36
kΩ
— Continued on next page
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
153
Electrical Specifications
Characteristic(1)
Typ(2)
2.12
2.18
60
Symbol
VTRIPF
VTRIPR
VHYS
Min
2.00
2.04
—
Max
2.24
2.30
—
Unit
V
Low-voltage inhibit reset, trip falling voltage (LVR)
Low-voltage inhibit reset, trip rising voltage (LVR)
Low-voltage inhibit reset/recover hysteresis
Low-voltage detect, trip falling voltage (LVD)
Low-voltage detect, trip rising voltage (LVD)
Low-voltage detect reset/recover hysteresis
V
mV
V
VDTRIPF
VDTRIPR
VDHYS
2.20
2.21
—
2.32
2.33
10
2.44
2.45
—
V
mV
1. VDD = VDDMIN to VDDMAX, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at VDD = 3.0 V, 25°C only.
3. Maximum is highest voltage that POR is guaranteed.
4. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum
VDD is reached.
5. RPU is measured at VDD = 3.0 V.
16.6 Control Timing
Characteristic(1)
Internal operating frequency
Symbol
fOP (fBus
tcyc
Min
Max
Unit
)
—
2
MHz
ns
Internal clock period (1/fOP
)
500
400
400
—
—
—
—
tRL
RST input pulse width low
ns
tILIH
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse period
ns
Note(2)
tILIL
tcyc
1. VDD >= 2.2 V, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted.
2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc
.
tRL
RST
tILIL
tILIH
IRQ
Figure 16-1. RST and IRQ Timing
MC68HLC908QY/QT Family Data Sheet, Rev. 3
154
Freescale Semiconductor
Typical 3.0-V Output Drive Characteristics
16.7 Typical 3.0-V Output Drive Characteristics
1.5
1.0
0.5
0.0
3V PTA
3V PTB
0
-5
-10
-15
-20
IOH (mA)
Figure 16-2. Typical 3-Volt Output High Voltage
versus Output High Current (25°C)
1.5
1.0
0.5
0.0
3V PTA
3V PTB
0
5
10
15
20
IOL (mA)
Figure 16-3. Typical 3-Volt Output Low Voltage
versus Output Low Current (25°C)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
155
Electrical Specifications
16.8 Oscillator Characteristics
Characteristic
Internal oscillator frequency(1)
Symbol
Min
—
30
2
Typ
4.0
Max
—
Unit
MHz
kHz
MHz
MHz
pF
fINTCLK
Crystal frequency, XTALCLK(1)
External RC oscillator frequency, RCCLK(1)
External clock reference frequency(1), (2)
Crystal load capacitance(3)
fOSCXCLK
fRCCLK
fOSCXCLK
CL
32.768
—
100
8
dc
—
—
—
1
—
8
12.5
2 x CL
2 x CL
—
Crystal fixed capacitance(3)
C1
—
—
Crystal tuning capacitance(3)
Feedback bias resistor
Series resistor
C2
—
—
RB
10
330
22
470
MΩ
kΩ
RS
100
REXT
RC oscillator external resistor
See Figure 16-4
—
1. Bus frequency, fOP, is oscillator frequency divided by 4.
2. No more than 10% duty cycle deviation from 50%.
3. Consult crystal vendor data sheet.
12
10
8
MCU
3V
2.3V
6
OSC1
4
VDD
REXT
2
0
0
10
20
30
40
50
60
REXT (KΩ)
Figure 16-4. Typical RC Oscillator Frequency versus REXT (25°C)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
156
Freescale Semiconductor
Supply Current Characteristics
16.9 Supply Current Characteristics
Bus Freq.
(MHz)
Characteristic
Voltage
Symbol
RIDD
Typ
Max
Unit
mA
mA
3.0
2.2
1
1
1.5
1.0
2.5
1.5
Run mode VDD supply current(1)
3.0
2.2
1
1
1.2
1.0
2.0
1.0
WAIT mode VDD supply current(2)
Stop mode VDD supply current(3)
WIDD
25°C
0.006
0.08
0.12
5.70
110
—
—
2.0
—
3.0
2.2
0 to 70°C
–40 to 85°C
25°C with auto wake-up enabled
Incremental current with LVI enabled at 25°C
µA
µA
—
SIDD
25°C
0 to 70°C
0.005
0.08
0.12
1.30
100
—
—
1.0
—
–40 to 85°C
25°C with auto wake-up enabled
Incremental current with LVI enabled at 25°C
—
1. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. All ports configured as inputs. Measured with all modules except ADC enabled.
2. Wait (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. All ports configured as inputs. Measured with all modules except ADC enabled.
3. Stop IDD measured with all ports driven 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configured as
inputs with pullups enabled.
2.5
2
1.5
1
0.5
0
2
2.5
3
3.5
4
VDD (V)
INT OSC w/ ADC
INT OSC w/o ADC
32K CRYSTAL w/ ADC
32K CRYSTAL w/o ADC
Figure 16-5. Typical Run Current versus VDD (25°C)
(fBus = 1 MHz for Internal Oscillator, fBus = 8 kHz for Crystal Oscillator)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
157
Electrical Specifications
1
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
VDD (V)
INT OSC w/ ADC
INT OSC w/o ADC
32K CRYSTAL w/ ADC
32K CRYSTAL w/o ADC
Figure 16-6. Typical Wait Current versus VDD (25°C)
f
Bus = 1 MHz for Internal Oscillator, fBus = 8 kHz for Crystal Oscillator)
10
8
6
4
2
0
2
2.2
2.4
2.6
2.8
VDD (V)
3
3.2
3.4
3.6
3.8
Figure 16-7. Typical Stop Current versus VDD (25°C)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
158
Freescale Semiconductor
Analog-to-Digital (ADC) Converter Characteristics
16.10 Analog-to-Digital (ADC) Converter Characteristics
16.10.1 ADC Electrical Operating Conditions
The ADC accuracy characteristics below are guaranteed over two operating conditions as stated here.
Characteristic
Symbol
Min
2.7
Max
3.6
1
Unit
V
VDD
ATD supply
fADIC
TA
Condition A
Condition B
ADC internal clock
Ambient temperature
ATD supply
0.008
TL
MHz
°C
TH
VDD
fADIC
TA
2.3
8
2.7
63
V
ADC internal clock
Ambient temperature
kHz
°C
TH
0
16.10.2 ADC Performance Characteristics
Characteristic
Symbol
Min
Max
Unit
Comments
VADIN
VSS
VDD
Input voltages
V
—
Resolution (1 LSB)
Condition A
Condition B
10.5
8.99
14.1
10.5
RES
mV
—
Absolute accuracy
(Total unadjusted error)
Condition A
Condition B
—
—
1.5
2.0
ETUE
LSB
Includes quantization
VAIN
tADPU
tADC
tADS
ZADI
FADI
CADI
IIL
VSS
16
16
5
VDD
—
17
—
01
FF
8
Conversion range
Power-up time
V
—
tADIC cycles
tADIC cycles
tADIC cycles
tADIC = 1/fADIC
tADIC = 1/fADIC
tADIC = 1/fADIC
Conversion time
Sample time(1)
Zero input reading(2)
V
IN = VSS
00
FE
—
Hex
Hex
pF
Full-scale reading(3)
Input capacitance
VIN = VDD
Not tested
—
Input leakage(3)
—
1
µA
ADC supply current (VDD = 3 V)
IADAD
Typical = 0.45
mA
Enabled
1. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
3. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
159
Electrical Specifications
16.11 Timer Interface Module Characteristics
Characteristic
Timer input capture pulse width
Timer input capture period
Symbol
tTH, TL
Min
Max
—
Unit
t
tcyc
2
Note(1)
tcyc + 5
tTLTL
tcyc
ns
—
t
TCL, tTCH
Timer input clock pulse width
—
1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc
.
tTLTL
tTH
INPUT CAPTURE
RISING EDGE
tTLTL
tTL
INPUT CAPTURE
FALLING EDGE
tTLTL
tTH
tTL
INPUT CAPTURE
BOTH EDGES
tTCH
TCLK
tTCL
Figure 16-8. Timer Input Timing
MC68HLC908QY/QT Family Data Sheet, Rev. 3
160
Freescale Semiconductor
Memory Characteristics
16.12 Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
Min
1.3
1
Typ
—
Max
—
Unit
V
VRDR
FLASH program bus clock frequency
—
—
—
MHz
V
FLASH PGM/ERASE supply voltage (VDD
FLASH read bus clock frequency
)
VPGM/ERASE
2.7
—
3.6
(1)
0
—
2
MHz
fRead
FLASH page erase time
<1 k cycles
>1 k cycles
tErase
0.9
3.6
1
4
1.1
5.5
ms
tMErase
tNVS
FLASH mass erase time
4
10
5
—
—
—
—
—
—
—
—
—
—
—
—
40
—
ms
µs
µs
µs
µs
µs
ms
FLASH PGM/ERASE to HVEN setup time
FLASH high-voltage hold time
tNVH
tNVHL
tPGS
FLASH high-voltage hold time (mass erase)
FLASH program setup time
FLASH program time
100
5
tPROG
30
1
(2)
FLASH return to read time
tRCV
(3)
FLASH cumulative program hv period
—
10 k
15
—
4
ms
tHV
FLASH endurance(4)
—
—
100 k
100
—
—
Cycles
Years
FLASH data retention time(5)
1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by
clearing HVEN to 0.
3. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) ≤ tHV maximum.
4. Typical endurance was evaluated for this product family. For additional information on how Freescale defines Typical
Endurance, please refer to Engineering Bulletin EB619.
5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please
refer to Engineering Bulletin EB618.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
161
Electrical Specifications
MC68HLC908QY/QT Family Data Sheet, Rev. 3
162
Freescale Semiconductor
Chapter 17
Ordering Information and Mechanical Specifications
17.1 Introduction
This section contains ordering numbers for MC68HLC908QY1, MC68HLC908QY2, MC68HLC908QY4,
MC68HLC908QT1, MC68HLC908QT2, and MC69HLC908QT4. Refer to Figure 17-1 for an example of
the device numbering system.
In addition, this section gives the package dimensions for:
•
•
•
•
•
•
8-pin plastic dual in-line package (PDIP)
8-pin small outline integrated circuit (SOIC) package
8-pin dual flat no lead (DFN) package
16-pin PDIP
16-pin SOIC
16-pin thin shrink small outline package (TSSOP)
17.2 MC Order Numbers
Table 17-1. MC Order Numbers
MC Order Number
MCL908QY1
MCL908QY2
MCL908QY4
MCL908QT1
MCL908QT2
MCL908QT4
ADC
—
FLASH Memory
1536 bytes
1536 bytes
4096 bytes
1536 bytes
1536 bytes
4096 bytes
Package
16-pins
PDIP, SOIC,
and TSSOP
Yes
Yes
—
8-pins
PDIP, SOIC,
and DFN
Yes
Yes
Temperature and package designators:
Blank = 0°C to 70°C
C = –40°C to 85°C
P = Plastic dual in-line package (PDIP)
DW = Small outline integrated circuit package (SOIC)
DT = Thin shrink small outline package (TSSOP)
FQ = Dual flat no lead (DFN)
M C L 9 0 8 Q Y 4 X X X E
Pb FREE
FAMILY
PACKAGE DESIGNATOR
TEMPERATURE RANGE
Figure 17-1. Device Numbering System
17.3 Package Dimensions
Refer to the following pages for detailed package dimensions.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
163
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MC68HLC908QY4
Rev. 3, 07/2005
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