MC74HCXXXXAD [FREESCALE]
Quad Analog Switch/Multiplexer/Demultiplexer; 四路模拟开关/多路复用器/多路解复用器
| 型号： | MC74HCXXXXAD |
| 厂家： | 
Freescale |
| 描述： | Quad Analog Switch/Multiplexer/Demultiplexer |
| 文件： | 总11页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
High–Performance Silicon–Gate CMOS
1
The MC54/74HC4066A utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF–
channel leakage current. This bilateral switch/multiplexer/demultiplexer
controls analog and digital voltages that may vary across the full
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
14
power–supply range (from V
to GND).
CC
The HC4066A is identical in pinout to the metal–gate CMOS MC14016
and MC14066. Each device has four independent switches. The device
1
has been designed so that the ON resistances (R
linear over input voltage than R
ON
The ON/OFF control inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL outputs.
For analog switches with voltage–level translators, see the HC4316A.
) are much more
of metal–gate CMOS analog switches.
ON
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
•
•
•
•
•
•
•
Fast Switching and Propagation Speeds
High ON/OFF Output Voltage Ratio
Low Crosstalk Between Switches
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
14
1
Diode Protection on All Inputs/Outputs
ORDERING INFORMATION
Wide Power–Supply Voltage Range (V
– GND) = 2.0 to 12.0 Volts
CC
– GND) = 2.0 to 12.0 Volts
MC54HCXXXXAJ
Ceramic
Plastic
SOIC
Analog Input Voltage Range (V
CC
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT
Improved Linearity and Lower ON Resistance over Input Voltage than
the MC14016 or MC14066
Low Noise
TSSOP
•
•
Chip Complexity: 44 FETs or 11 Equivalent Gates
PIN ASSIGNMENT
LOGIC DIAGRAM
V
X
1
2
3
4
14
13
12
11
CC
A
A ON/OFF
CONTROL
D ON/OFF
CONTROL
1
2
3
Y
X
Y
A
A
A
Y
B
13
4
A ON/OFF CONTROL
X
X
D
B
B ON/OFF
CONTROL
5
6
10
9
Y
D
C
X
Y
Y
Y
B
B
C
D
C ON/OFF
CONTROL
Y
7
8
X
ANALOG
GND
C
5
B ON/OFF CONTROL
OUTPUTS/INPUTS
8
9
X
C
FUNCTION TABLE
6
C ON/OFF CONTROL
On/Off Control
State of
Input
Analog Switch
11
10
L
H
Off
On
X
D
12
D ON/OFF CONTROL
ANALOG INPUTS/OUTPUTS = X , X , X , X
D
A
B
C
PIN 14 = V
CC
PIN 7 = GND
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
12/97
REV 0.1
Motorola, Inc. 1997
MC54/74HC4066A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
CC
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage (Referenced to GND)
Digital Input Voltage (Referenced to GND)
DC Current Into or Out of Any Pin
– 0.5 to + 14.0
V
IS
– 0.5 to V
– 0.5 to V
+ 0.5
+ 0.5
V
CC
V
in
V
CC
I
± 25
mA
mW
cuit. For proper operation, V and
in
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
450
V
should be constrained to the
out
range GND (V or V
)
V
.
in out
CC
TSSOP Package†
Unused inputs must always be
tied to an appropriate logic voltage
T
stg
Storage Temperature
– 65 to + 150
C
C
level (e.g., either GND or V ).
CC
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
Max
Unit
V
V
CC
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage (Referenced to GND)
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types
Input Rise and Fall Time, ON/OFF Control
12.0
V
IS
GND
GND
—
V
V
V
CC
V
in
V
CC
V
IO
*
1.2
V
T
A
– 55 + 125
C
t , t
r f
ns
Inputs (Figure 10)
V
V
V
V
= 2.0 V
= 3.0 V
= 4.5 V
= 9.0 V
0
0
0
0
0
1000
600
500
400
250
CC
CC
CC
CC
V
CC
= 12.0 V
* For voltage drops across the switch greater than 1.2 V (switch on), excessive V
current may
and switch input components.
CC
be drawn; i.e., the current out of the switch may contain both V
CC
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
Test Conditions
= Per Spec
25 C
Unit
85 C
125 C
V
IH
Minimum High–Level Voltage
ON/OFF Control Inputs
R
R
2.0
3.0
4.5
9.0
12.0
1.5
2.1
3.15
6.3
1.5
2.1
3.15
6.3
1.5
2.1
3.15
6.3
V
on
on
8.4
8.4
8.4
V
IL
Maximum Low–Level Voltage
ON/OFF Control Inputs
= Per Spec
2.0
3.0
0.5
0.9
0.5
0.9
0.5
0.9
V
4.5
9.0
1.35
2.7
1.35
2.7
1.35
2.7
12.0
3.6
3.6
3.6
I
Maximum Input Leakage Current
ON/OFF Control Inputs
V
= V
or GND
12.0
± 0.1
± 1.0
± 1.0
µA
µA
in
in
CC
CC
I
Maximum Quiescent Supply
Current (per Package)
V
V
= V
= 0 V
or GND
6.0
12.0
2
4
20
40
40
160
CC
in
IO
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
MC54/74HC4066A
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
– 55 to
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
R
Maximum “ON” Resistance
Ω
V
V
= V
= V
2.0†
3.0†
4.5
9.0
12.0
—
—
120
70
—
—
160
85
—
—
200
100
100
on
in
IS
IH
CC
to GND
I
S
2.0 mA (Figures 1, 2)
70
85
V
V
= V
2.0
3.0
4.5
9.0
12.0
—
—
70
50
30
—
—
85
60
60
—
—
100
80
in
IS
IH
= V
or GND (Endpoints)
CC
2.0 mA (Figures 1, 2)
I
S
80
∆R
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
= V
= 1/2 (V
2.0 mA
2.0
4.5
9.0
—
20
15
15
—
25
20
20
—
30
25
25
Ω
on
in
IS
IH
– GND)
CC
I
S
12.0
I
I
Maximum Off–Channel Leakage
Current, Any One Channel
V
V
= V
12.0
12.0
0.1
0.5
1.0
µA
µA
off
in
IL
= V
or GND
CC
IO
Switch Off (Figure 3)
Maximum On–Channel Leakage
Current, Any One Channel
V
V
= V
IH
= V
0.1
0.5
1.0
on
in
IS
or GND
CC
(Figure 4)
†At supply voltage (V ) approaching 3 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage
CC
operation, it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, ON/OFF Control Inputs: t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
25 C
Unit
85 C
125 C
t
t
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figures 8 and 9)
2.0
3.0
4.5
40
30
5
50
40
7
60
50
8
ns
PLH
PHL
9.0
5
7
8
12.0
5
7
8
t
t
,
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 11)
2.0
3.0
4.5
9.0
12.0
80
60
20
20
20
90
70
25
25
25
110
80
35
35
35
ns
ns
pF
PLZ
PHZ
t
t
,
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 1 1)
2.0
3.0
4.5
9.0
12.0
80
45
20
20
20
90
50
25
25
25
100
60
30
30
30
PZL
PZH
C
Maximum Capacitance
ON/OFF Control Input
—
10
10
10
Control Input = GND
Analog I/O
—
—
35
1.0
35
1.0
35
1.0
Feedthrough
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Switch) (Figure 13)*
pF
15
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
3
MOTOROLA
MC54/74HC4066A
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Limit*
25 C
54/74HC
V
CC
V
Symbol
Parameter
Test Conditions
= 1 MHz Sine Wave
Unit
BW
Maximum On–Channel Bandwidth or
Minimum Frequency Response
(Figure 5)
f
in
4.5
9.0
12.0
150
160
160
MHz
Adjust f Voltage to Obtain 0 dBm at V
in
OS
Increase f Frequency Until dB Meter Reads – 3 dB
in
R
= 50 Ω, C = 10 pF
L
L
—
—
Off–Channel Feedthrough Isolation
(Figure 6)
4.5
9.0
12.0
– 50
– 50
– 50
dB
f
Sine Wave
in
Adjust f Voltage to Obtain 0 dBm at V
in IS
f
in
= 10 kHz, R = 600 Ω, C = 50 pF
L
L
f
in
= 1.0 MHz, R = 50 Ω, C = 10 pF
4.5
9.0
12.0
– 40
– 40
– 40
L
L
Feedthrough Noise, Control to
Switch
(Figure 7)
V
1 MHz Square Wave (t = t = 6 ns)
4.5
9.0
12.0
60
130
200
mV
PP
in
r
f
Adjust R at Setup so that I = 0 A
L
S
R
= 600 Ω, C = 50 pF
L
L
R
= 10 kΩ, C = 10 pF
4.5
9.0
30
65
L
L
12.0
100
—
Crosstalk Between Any Two Switches
(Figure 12)
4.5
9.0
12.0
– 70
– 70
– 70
dB
f
Sine Wave
in
Adjust f Voltage to Obtain 0 dBm at V
in IS
f
in
= 10 kHz, R = 600 Ω, C = 50 pF
L
L
f
in
= 1.0 MHz, R = 50 Ω, C = 10 pF
4.5
9.0
12.0
– 80
– 80
– 80
L
L
THD
Total Harmonic Distortion
(Figure 14)
f
= 1 kHz, R = 10 kΩ, C = 50 pF
%
in
THD = THD
L
L
– THD
Measured
Source
V
IS
V
IS
= 4.0 V
sine wave
sine wave
sine wave
4.5
9.0
12.0
0.10
0.06
0.04
PP
PP
PP
= 8.0 V
= 11.0 V
V
IS
* Guaranteed limits not tested. Determined by design and verified by qualification.
MOTOROLA
4
MC54/74HC4066A
TBD
TBD
Figure 1a. Typical On Resistance, V
= 2.0 V
= 6.0 V
= 12 V
Figure 1b. Typical On Resistance, V
= 4.5 V
CC
CC
TBD
TBD
Figure 1c. Typical On Resistance, V
Figure 1d. Typical On Resistance, V
= 9.0 V
CC
CC
PLOTTER
PROGRAMMABLE
MINI COMPUTER
DC ANALYZER
POWER
SUPPLY
TBD
–
+
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
Figure 1e. Typical On Resistance, V
Figure 2. On Resistance Test Set–Up
CC
5
MOTOROLA
MC54/74HC4066A
V
CC
V
V
V
CC
CC
V
14
14
GND
CC
N/C
A
ON
A
OFF
GND
V
CC
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
IL
IH
7
7
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
Figure 4. Maximum On Channel Leakage Current,
Test Set–Up
V
V
V
OS
V
OS
V
CC
14
CC
14
IS
f
in
f
ON
OFF
in
dB
METER
dB
METER
0.1µF
0.1µF
C *
C *
L
R
L
L
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
CC
7
7
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 5. Maximum On–Channel Bandwidth
Test Set–Up
Figure 6. Off–Channel Feedthrough Isolation,
Test Set–Up
V
V
CC
V
CC/2
CC/2
14
R
S
R
L
L
V
OS
I
OFF/ON
V
CC
C *
L
50%
ANALOG IN
SELECTED
CONTROL
INPUT
GND
7
V
≤
1 MHz
t
t
PHL
in
PLH
t = t = 6 ns
r
f
V
CC
GND
CONTROL
50%
ANALOG OUT
*Includes all probe and jig capacitance.
Figure 7. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set–Up
Figure 8. Propagation Delays, Analog In to
Analog Out
MOTOROLA
6
MC54/74HC4066A
V
t
t
f
CC
r
14
V
CC
90%
50%
10%
CONTROL
ANALOG IN
ANALOG OUT
C *
TEST
POINT
ON
GND
L
t
t
t
PLZ
PZL
HIGH
IMPEDANCE
50%
50%
SELECTED
CONTROL
INPUT
V
CC
10%
90%
V
OL
ANALOG
OUT
7
t
PZH
PHZ
V
OH
HIGH
IMPEDANCE
*Includes all probe and jig capacitance.
Figure 9. Propagation Delay Test Set–Up
Figure 10. Propagation Delay, ON/OFF Control
to Analog Out
V
1
2
POSITION
POSITION
WHEN TESTING t
AND t
IS
PHZ
AND t
PLZ
PZH
V
CC
WHEN TESTING t
1
2
PZL
14
R
V
L
OS
V
f
in
ON
CC
V
0.1 µF
CC
1 kΩ
14
1
2
TEST
POINT
OFF
ON/OFF
V
OR GND
CC
R
C *
R
C *
L
L
L
L
C *
L
R
L
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
V
CC/2
CC/2
7
7
V
CC/2
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 11. Propagation Delay Test Set–Up
Figure 12. Crosstalk Between Any Two Switches,
Test Set–Up
V
CC
A
V
IS
V
CC
V
OS
14
0.1 µF
TO
N/C
N/C
OFF/ON
f
ON
DISTORTION
METER
in
C *
L
R
L
V
SELECTED
CONTROL
INPUT
CC/2
7
SELECTED
CONTROL
INPUT
V
CC
7
ON/OFF CONTROL
*Includes all probe and jig capacitance.
Figure 13. Power Dissipation Capacitance
Test Set–Up
Figure 14. Total Harmonic Distortion, Test Set–Up
7
MOTOROLA
MC54/74HC4066A
0
–10
–20
–30
–40
FUNDAMENTAL FREQUENCY
–50
–60
–70
–80
–90
DEVICE
SOURCE
1.0
2.0
FREQUENCY (kHz)
3.0
Figure 15. Plot, Harmonic Distortion
below, the difference between V
and GND is twelve volts.
APPLICATION INFORMATION
CC
Therefore, using the configuration in Figure 16, a maximum
analog signal of twelve volts peak–to–peak can be con-
trolled.
The ON/OFF Control pins should be at V
or GND logic
being recognized as logic high and GND being
CC
levels, V
CC
recognized as a logic low. Unused analog inputs/outputs
may be left floating (not connected). However, it is advisable
When voltage transients above V
and/or below GND
CC
are anticipated on the analog channels, external diodes (Dx)
are recommended as shown in Figure 17. These diodes
should be small signal, fast turn–on types able to absorb the
maximum anticipated current surges during clipping. An
alternate method would be to replace the Dx diodes with
MO sorbs (Motorola high current surge protectors).
MO sorbs are fast turn–on devices ideally suited for precise
DC protection with no inherent wear out mechanism.
to tie unused analog inputs and outputs to V
or GND
CC
through a low value resistor. This minimizes crosstalk and
feedthrough noise that may be picked–up by the unused I/O
pins.
The maximum analog voltage swings are determined by
the supply voltages V
voltage should not exceed V . Similarly, the negative peak
analog voltage should not go below GND. In the example
and GND. The positive peak analog
CC
CC
V
V
CC
CC
V
= 12 V
CC
D
D
D
D
14
x
16
x
+ 12 V
0 V
+ 12 V
0 V
ANALOG I/O
ANALOG O/I
ON
ON
x
x
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
CC
OTHER CONTROL
INPUTS
OR GND)
OTHER CONTROL
INPUTS
7
7
(V
CC
(V
OR GND)
CC
Figure 16. 12 V Application
Figure 17. Transient Suppressor Application
MOTOROLA
8
MC54/74HC4066A
+5 V
+5 V
14
14
ANALOG
SIGNALS
ANALOG
SIGNALS
ANALOG
SIGNALS
ANALOG
SIGNALS
HCT
BUFFER
R* R* R* R*
HC4066A
HC4066A
LSTTL/
NMOS
LSTTL/
NMOS
5
6
5
6
CONTROL
INPUTS
CONTROL
INPUTS
14
15
14
15
7
7
R* = 2 TO 10 k
Ω
a. Using Pull-Up Resistors
b. Using HCT Buffer
Figure 18. LSTTL/NMOS to HCMOS Interface
V
= 5 V
V
= 5 TO 12 V
DD
CC
1
16
14
13
3
ANALOG
SIGNALS
ANALOG
SIGNALS
HC4066A
5
7
2
5
6
MC14504
9
4
CONTROL
INPUTS
11
14
6
14
15
10
8
7
Figure 19. TTL/NMOS–to–CMOS Level Converter
Analog Signal Peak–to–Peak Greater than 5 V
(Also see HC4316A)
1 OF 4
SWITCHES
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 1
1 OF 4
SWITCHES
COMMON I/O
1 OF 4
SWITCHES
–
+
1 OF 4
SWITCHES
OUTPUT
1 OF 4
INPUT
LF356 OR
EQUIVALENT
SWITCHES
0.01
µF
1
2
3
4
CONTROL INPUTS
Figure 20. 4–Input Multiplexer
Figure 21. Sample/Hold Amplifier
9
MOTOROLA
MC54/74HC4066A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE Y
14
1
8
7
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
-B-
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.785
0.280
0.200
0.020
0.065
MIN
19.05
6.23
3.94
0.39
1.40
MAX
19.94
7.11
5.08
0.50
1.65
0.750
0.245
0.155
0.015
0.055
-T-
SEATING
PLANE
K
G
J
K
L
M
N
0.100 BSC
2.54 BSC
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
M
F
G
N
D 14 PL
0.25 (0.010)
J 14 PL
0.300 BSC
15
0.040
7.62 BSC
15
0.51 1.01
0°
°
0°
°
M
M
S
S
T
A
0.25 (0.010)
T
B
0.020
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
14
1
8
ISSUE L
2. DIMENSION L TO CENTER OF LEADS WHEN
B
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
7
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
C
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
0
10
0
10
0.015
0.039
0.39
1.01
H
G
D
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE F
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
P 7 PL
–B–
M
M
0.25 (0.010)
B
7
MILLIMETERS
INCHES
G
F
R X 45°
DIM
A
B
C
D
F
G
J
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
C
0.337
0.150
0.054
0.014
0.016
J
M
SEATING
PLANE
K
D 14 PL
0.25 (0.010)
1.27 BSC
0.050 BSC
0.19
0.10
0.25
0.25
0.008
0.004
0.009
0.009
M
S
S
T
B
A
K
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.228
0.010
MOTOROLA
10
MC54/74HC4066A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
NOTES:
14X K REF
0.10 (0.004)
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
T
U
V
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
7
2X L/2
M
B
L
N
–U–
PIN 1
IDENT.
F
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
K
0.15 (0.006) T
U
A
MILLIMETERS
INCHES
K1
DIM
A
B
C
D
F
G
H
J
J1
K
MIN
4.90
4.30
–––
0.05
0.50
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
–V–
0.193
0.169
–––
0.002
0.020
J J1
SECTION N–N
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60
0.20
0.16
0.30
0.25
0.020
0.004
0.004
0.007
0.007
0.024
0.008
0.006
0.012
0.010
–W–
C
K1
L
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
SEATING
PLANE
–T–
H
G
DETAIL E
D
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