MC9RS08KA4 [FREESCALE]
MCU Block Diagram; MCU框图型号: | MC9RS08KA4 |
厂家: | Freescale |
描述: | MCU Block Diagram |
文件: | 总40页 (文件大小:892K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MC9RS08KA8
Rev. 1 , 1/2008
MC9RS08KA8
20-Pin W-SOIC
Case 751D
16-Pin W-SOIC
Case 751G
20-Pin PDIP
Case 738C
16-Pin PDIP
Case 648
MC9RS08KA8 Series
Covers: MC9RS08KA8
Features:
– Single-Wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
• 8-Bit RS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 1.8 V to 5.5 V across temperature
range of –40°C to 85°C
• Peripherals
– ADC — 12-channel, 10-bit resolution; 2.5 μs
conversion time; automatic compare function; operation
in stop; fully functional from 2.7 V to 5.5 V (8-channels
available on 16-pin package)
– TPM — One 2-channel; selectable input capture, output
compare, or buffered edge- or center-aligned PWM on
each channel
– Subset of HC08 instruction set with added BGND
instruction
• On-Chip Memory
– 8 KB flash read/program/erase over full operating
voltage and temperature; KA4 has 4 KB flash
– 254 byte random-access memory (RAM); KA4 has 126
byte RAM
– IIC — Inter-Integrated circuit bus module capable of
operation up to 100 kbps with maximum bus loading;
capable of higher baudrates with reduced loading
– MTIM1 and MTIM2 — Two 8-bit modulo timers
– KBI — Keyboard interrupts with rising or falling edge
detect; eight KBI ports in 16-pin and 20-pin packages
– ACMP — Analog comparator: full rail-to-rail supply
operation; option to compare to fixed internal bandgap
reference voltage; can operate in stop mode
• Input/Output
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes
– Wait and stop
– Wakeup from power-saving modes using real-time
interrupt (RTI), KBI, or ACMP
• Clock Source Options
– Oscillator (XOSC) — Loop-Control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
39.0625 kHz or 1 MHz to 5 MHz
– 14/18 GPIOs including one output only pin and one
input only pin
– Hysteresis and configurable pullup device on all input
pins; configurable slew rate and drive strength on all
output pins
– Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; precision
trimming of internal reference allows 0.2% resolution
and 2% deviation over temperature and voltage;
supports bus frequencies up to 10 MHz
• System Protection
• Package Options
– 16-pin, 20-pin SOIC or PDIP
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1 kHz internal clock
source or bus clock
– Low-Voltage detection with reset or interrupt
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
• Development Support
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
2
3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.2 TPM/MTIM Module Timing. . . . . . . . . . . . . . . . 20
3.10 Analog Comparator (ACMP) Electrical . . . . . . . . . . . . 20
3.11 Internal Clock Source Characteristics . . . . . . . . . . . . . 21
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 26
3.14.2 Conducted Transient Susceptibility . . . . . . . . . 26
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .5
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .6
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .7
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .18
3.9 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Date
Description of Changes
1
1/22/2008
Initial public release
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9RS08KA8RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9RS08KA8 Series, Rev. 1
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of the MC9RS08KA8 MCU.
RS08 CORE
PTA5/TCLK/RESET/VPP
IIC MODULE(IIC)
PTA4/ACMPO/BKGD/MS
BDC
CPU
PTA3/KBIP3/SCL/ADP3
ANALOG COMPARATOR
(ACMP)
PTA2/KBIP2/SDA/ADP2
RS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PTA1/KBIP1/TPMCH1/ADP1/ACMP–
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPMCH1
COP
RTI
WAKEUP
LVD
KEYBOARD INTERRUPT
PTB4/TPMCH0
16-BIT TIMER/PWM
MODULE (TPM)
PTB3/KBIP7/ADP7
PTB2/KBIP6/ADP6
PTB1/KBIP5/ADP5
PTB0/KBIP4/ADP4
USER FLASH
(MC9RS08KA8 = 8192 BYTES)
(MC9RS08KA4 = 4096 BYTES)
VPP
8-BIT TIMER
(MTIM1 and MTIM2)
USER RAM
PTC3/ADP11
PTC2/ADP10
PTC1/ADP9
PTC0/ADP8
(MC9RS08KA8 = 254 BYTES)
(MC9RS08KA4 = 126 BYTES)
20-MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
31.25 kHz to 39.0625 kHz
1 MHz to 5 MHz
(XOSC)
VSS
VDD
VOLTAGE REGULATOR
Figure 1. MC9RS08KA8 Series Block Diagram
2
Pin Assignments
This section shows the pin assignments in the packages available for the MC9RS08KA8 series.
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Pin Assignments
Table 1. Pin Availability by Package Pin-Count
Pin
Number
<-- Lowest Priority --> Highest
20
16
Port Pin
PTA5
Alt 1
Alt 2
TCLK
Alt 3
RESET
Alt 4
1
2
1
2
VPP
PTA4
ACMPO
BKGD
MS
3
3
VDD
VSS
4
4
5
5
PTB7
PTB6
PTB5
PTB4
PTC3
PTC2
PTC1
PTC0
PTB3
SCL1
SDA1
TPMCH12
TPMCH02
EXTAL
XTAL
6
6
7
7
8
8
9
—
—
—
—
9
ADP11
ADP10
ADP9
ADP8
ADP7
ADP6
ADP5
ADP4
ADP3
ADP2
ADP1
ADP0
10
11
12
13
14
15
16
17
18
19
20
KBIP7
KBIP6
KBIP5
KBIP4
KBIP3
KBIP2
KBIP1
KBIP0
10 PTB2
11 PTB1
12 PTB0
13 PTA3
14 PTA2
15 PTA1
16 PTA0
SCL1
SDA1
TPMCH12
TPMCH02
ACMP–
ACMP+
1
2
IIC pins can be remapped to PTA3 and PTA2
TPM pins can be remapped to PTA0 and PTA1
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA1/KBIP1/TPMCH1/ADP1/ACMP–
PTA2/KBIP2/SDA/ADP2
PTA3/KBIP3/SCL/ADP3
PTB0/KBIP4/ADP4
1
20
19
18
17
16
15
14
13
PTA5/TCLK/RESET/VPP
2
PTA4/ACMPO/BKGD/MS
VDD
3
4
VSS
5
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPMCH1
PTB4/TPMCH0
6
PTB1/KBIP5/ADP5
7
PTB2/KBIP6/ADP6
8
PTB3/KBIP7/ADP7
9
PTC3/ADP11
PTC2/ADP10
12
11
PTC0/ADP8
PTC1/ADP9
10
Figure 2. MC9RS08KA8 Series in 20-Pin PDIP/SOIC Package
MC9RS08KA8 Series, Rev. 1
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
PTA5/TCLK/RESET/VPP
PTA4/ACMPO/BKGD/MS
VDD
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
16
15
14
13
1
2
3
4
5
6
7
8
PTA1/KBIP1/TPMCH1/ADP1/ACMP–
PTA2/KBIP2/SDA/ADP2
PTA3/KBIP3/SCL/ADP3
PTB0/KBIP4/ADP4
VSS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPMCH1
PTB4/TPMCH0
12
11
PTB1/KBIP5/ADP5
PTB2/KBIP6/ADP6
10
9
PTB3/KBIP7/ADP7
Figure 3. MC9RS08KA8 Series in 16-Pin PDIP/SOIC Package
3
Electrical Characteristics
3.1
Introduction
This chapter contains electrical and timing specifications for the MC9RS08KA8 series of microcontrollers available at the time
of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
Those parameters are guaranteed during production testing on each individual device.
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this chapter.
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
Electrical Characteristics
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, V or V ) or the programmable pull-up resistor associated with the pin is enabled.
SS
DD
Table 3. Absolute Maximum Ratings
Symbol
Rating
Value
Unit
Supply voltage
VDD
IDD
VIn
–0.3 to 5.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
Instantaneous maximum current
ID
±25
mA
Single pin limit (applies to all port pins)1 2 3
,
,
Storage temperature range
Tstg
–55 to 150
°C
1
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two
resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD except the RESET/VPP pin which is internally
clamped to VSS only.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater
than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are:
if no system clock is present, or if the clock rate is very low which would reduce overall power consumption.
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it
is user-determined rather than being controlled by the MCU design. In order to take P into account in power calculations,
I/O
determine the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except
SS
DD
in cases of unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very
SS
DD
small.
Table 4. Thermal Characteristics
Symbol
Rating
Value
Unit
Operating temperature range (packaged)
TA
TL to TH
–40 to 85
°C
°C
Maximum junction temperature
Thermal resistance 16-pin PDIP
Thermal resistance 16-pin SOIC
Thermal resistance 20-pin PDIP
Thermal resistance 20-pin SOIC
TJMAX
θJA
105
80
°C/W
°C/W
°C/W
°C/W
θJA
112
75
θJA
θJA
96
The average chip-junction temperature (TJ) in °C can be obtained from:
T = T + (P × θ
)
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, °C
A
MC9RS08KA8 Series, Rev. 1
Preliminary—Subject to Change Without Notice
6
Freescale Semiconductor
Electrical Characteristics
θ
= Package thermal resistance, junction-to-ambient, °C /W
JA
P = P + P
D
int
I/O
P
= I × V , Watts chip internal power
DD DD
int
I/O
P
= Power dissipation on input and output pins user determined
For most applications, P << P and can be neglected. An approximate relationship between PD and TJ
I/O
int
(if P is neglected) is:
I/O
P = K ÷ (T + 273°C)
Eqn. 2
Eqn. 3
D
J
Solving Equation 1 and Equation 2 for K gives:
K = P × (T + 273°C) + θ × (PD)
2
D
A
JA
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving equations 1 and 2 iteratively for any
A
D
J
value of T .
A
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions must be used to avoid exposure to static discharge. Qualification tests are performed to ensure that
these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Symbol
Value
1500
100
3
Unit
Ω
R1
C
Human
Body
Storage capacitance
Number of pulses per pin
Series resistance
pF
—
Ω
—
R1
C
0
Machine Storage capacitance
Number of pulses per pin
200
3
pF
—
V
—
—
—
Minimum input voltage limit
Latch-up
–2.5
7.5
Maximum input voltage limit
V
MC9RS08KA8 Series, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
7
Electrical Characteristics
No.
Table 6. ESD and Latch-Up Protection Characteristics
1
Symbol
Min
Max
Unit
Rating
1
2
3
Human body model (HBM)
Machine model (MM)
VHBM
VMM
±2000
±200
±500
—
—
—
V
V
V
Charge device model (CDM)
VCDM
Latch-up current at TA = 85°C
(applies to all pins except pin 9
PTC3/ADP11)
ILAT
±1002
±753
—
—
mA
mA
4
Latch-up current at TA = 85°C
(applies to pin 9 PTC3/ADP11)
ILAT
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
2
3
These pins meet JESD78A Class II (section 1.2) Level A (section 1.3) requirement of ±100mA.
This pin meets JESD78A Class II (section 1.2) Level B (section 1.3) characterization to ±75mA.
This pin is only present on 20 pin package types.
3.6
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
Table 7. DC Characteristics
(Temperature Range = –40 to 85°C Ambient)
Parameter
Symbol
Min
Typical
Max
Unit
Supply voltage (run, wait and stop modes.)
0 < fBus <10MHz
VDD
1.8
—
—
5.5
—
V
V
Minimum RAM retention supply voltage applied to VDD
VRAM
0.81
Low-voltage Detection threshold
(VDD falling)
(VDD rising)
VLVD
1.80
1.88
1.86
1.94
1.95
2.03
V
1
Power on RESET (POR) voltage
VPOR
0.9
—
—
—
—
1.7
—
V
V
V
V
Input high voltage (VDD > 2.3V) (all digital inputs)
Input high voltage (1.8 V ≤ VDD ≤ 2.3 V) (all digital inputs)
Input low voltage (VDD > 2.3 V) (all digital inputs)
VIH
VIH
VIL
0.70 × VDD
0.85 × VDD
—
—
0.30 × VDD
Input low voltage (1.8 V ≤ VDD ≤ 2.3 V)
(all digital inputs)
VIL
—
0.06 × VDD
—
—
—
0.30 × VDD
V
V
1
Input hysteresis (all digital inputs)
Input leakage current (per pin)
Vhys
—
|IIn|
0.025
1.0
μA
VIn = VDD or VSS, all input only pins
High impedance (off-state) leakage current (per pin)
VIn = VDD or VSS, all input/output
|IOZ|
—
0.025
1.0
μA
Internal pullup resistors2(all port pins)
Internal pulldown resistors2(all port pins except PTA5)
PTA5 Internal pulldown resistor
RPU
RPD
—
20
20
45
45
45
—
65
65
95
kΩ
kΩ
kΩ
MC9RS08KA8 Series, Rev. 1
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics
(Temperature Range = –40 to 85°C Ambient)
Parameter
Symbol
Min
Typical
Max
Unit
Output high voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 2 mA
3 V, ILoad = 1 mA
—
—
—
—
—
—
VDD – 0.8
1.8 V, ILoad = 0.5 mA
V
mA
V
VOH
Output high voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 5 mA
3 V, ILoad = 3 mA
—
—
—
—
—
—
VDD – 0.8
1.8 V, ILoad = 2 mA
Maximum total IOH for all port pins
|IOHT
|
—
—
40
Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 2 mA
3 V, ILoad = 1 mA
—
—
—
—
—
—
0.8
1.8 V, ILoad = 0.5 mA
VOL
Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 5 mA
3 V, ILoad = 3 mA
—
—
—
—
—
—
0.8
40
1.8 V, ILoad = 2 mA
Maximum total IOL for all port pins
IOLT
—
—
mA
DC injection current3 4 5 6
,
,
,
VIn < VSS, VIn > VDD
Single pin limit
Total MCU limit, includes sum of all stressed pins
—
—
—
—
0.2
0.8
mA
mA
Input capacitance (all non-supply pins)
CIn
—
—
7
pF
1
This parameter is characterized and not tested on each device.
2
3
Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown.
All functional non-supply pins are internally clamped to VSS and VDD except the RESET/VPP which is internally clamped
to VSS only.
4
5
6
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
This parameter is characterized and not tested on each device.
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
Electrical Characteristics
IOH vs VDD-VOH (High Drive) at VDD = 5.5 V
-50
-40
-30
-20
-10
0
85C
25C
-40C
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VDD-VOH (V)
Figure 4. Typical I vs. V –V
OH
DD OH
V
= 5.5 V (High Drive)
DD
IOH vs VDD-VOH (Low Drive) at VDD = 5.5 V
-12
-10
-8
85C
25C
-40C
-6
-4
-2
0
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VDD-VOH (V)
Figure 5. Typical I vs. V –V
OH
DD OH
V
= 5.5 V (Low Drive)
DD
MC9RS08KA8 Series, Rev. 1
10
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
IOH vs VDD-VOH (High Drive) at VDD = 3 V
-20
-15
-10
-5
85C
25C
-40C
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VDD-VOH (V)
Figure 6. Typical I vs. V –V
OH
DD OH
V
= 3 V (High Drive)
DD
IOH vs VDD-VOH (Low Drive) at VDD = 3 V
-5
-4
-3
-2
-1
0
85C
25C
-40C
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VDD-VOH (V)
Figure 7. Typical I vs. V –V
OH
DD OH
V
= 3 V (Low Drive)
DD
MC9RS08KA8 Series, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
11
Electrical Characteristics
IOH vs VDD-VOH (High Drive) at VDD = 1.8 V
-7
-6
-5
-4
-3
-2
-1
0
85C
25C
-40C
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VDD-VOH (V)
Figure 8. Typical I vs. V –V
OH
DD OH
V
= 1.8 V (High Drive)
DD
IOH vs VDD-VOH (Low Drive) at VDD = 1.8 V
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
85C
25C
-40C
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VDD-VOH (V)
Figure 9. Typical I vs. V –V
OH
DD OH
V
= 1.8 V (Low Drive)
DD
MC9RS08KA8 Series, Rev. 1
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
IOL vs VOL (High Drive) at VDD = 5.5 V
50
40
30
20
10
0
85C
25C
c
-40C
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VOL (V)
Figure 10. Typical I vs. V –V
OL
DD OL
V
= 5.5 V (High Drive)
DD
IOL vs VOL (Low Drive) at VDD = 5.5 V
15
85C
25C
-40C
10
5
0
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VOL (V)
Figure 11. Typical I vs. V –V
OL
DD OL
V
= 5.5 V (Low Drive)
DD
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
Electrical Characteristics
IOL vs VOL (High Drive) at VDD = 3 V
20
15
10
5
85C
25C
-40C
0
0.1
0.2
0.4
0.6
OL (V)
0.8
1.0
1.2
1.4
V
Figure 12. Typical I vs. V –V
OL
DD OL
V
= 3 V (High Drive)
DD
IOL vs VOL (Low Drive) at VDD = 3 V
5
4
3
2
1
0
85C
25C
-40C
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VOL (V)
Figure 13. Typical I vs. V –V
OL
DD OL
V
= 3 V (Low Drive)
DD
MC9RS08KA8 Series, Rev. 1
Preliminary—Subject to Change Without Notice
14
Freescale Semiconductor
Electrical Characteristics
IOL vs VOL (High Drive) at VDD = 1.8 V
5
4
3
2
1
0
85C
25C
-40C
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VOL (V)
Figure 14. Typical I vs. V –V
OL
DD OL
V
= 1.8 V (High Drive)
DD
IOL vs VOL (Low Drive) at VDD = 1.8 V
1.4
1.2
1
0.8
0.6
0.4
0.2
0
85C
25C
-40C
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VOL(V)
Figure 15. Typical I vs. V –V
OL
DD OL
V
= 1.8 V (Low Drive)
DD
3.7
Supply Current Characteristics
Table 8. Supply Current Characteristics
Parameter
Symbol
VDD (V)
Typical1
Max2
Temp. (°C)
25
85
5
2.4 mA
5 mA
—
Run supply current3 measured at
(fBus = 10 MHz)
25
85
RIDD10
3
2.4 mA
1.7 mA
25
85
1.80
—
MC9RS08KA8 Series, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
15
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Parameter
Symbol
VDD (V)
Typical1
Max2
Temp. (°C)
25
85
5
0.42 mA
2 mA
Run supply current3 measured at
(fBus = 1.25 MHz)
25
85
RIDD1
3
1.80
5
0.42 mA
0.3 mA
2.4 μA
2 μA
—
—
25
85
5 μA
8 μA
25
85
25
85
Stop mode supply current
ADC adder from stop4
SIDD
3
—
—
25
85
1.80
5
1.5 μA
128 μA
121 μA
79 μA
150 μA
165 μA
25
85
25
85
3
—
—
25
85
1.80
5
25
85
21 μA
22 μA
—
ACMP adder from stop
(ACME = 1)
25
85
3
18.5 μA
17.5 μA
2.4 μA
1.9 μA
1.5 μA
2.1 μA
1.6 μA
1.2 μA
70 μA
25
85
1.80
5
—
25
85
2 μA
—
RTI adder from stop
25
85
3
with 1 kHz clock source enabled5
25
85
1.80
5
—
25
85
2 μA
—
RTI adder from stop
with 1 MHz external clock source reference
enabled
25
85
3
25
85
1.80
5
—
25
85
80 μA
—
LVI adder from stop
(LVDE=1 and LVDSE=1)
25
85
3
65 μA
25
85
1.80
60 μA
—
1
Typicals are measured at 25°C.
Maximum value is measured at the nominal VDD voltage times 10% tolerance. Values given here are preliminary estimates
prior to completing characterization.
2
3
Not include any DC loads on port pins.
4
Required asynchronous ADC clock and LVD to be enabled.
MC9RS08KA8 Series, Rev. 1
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
5
Most customers are expected to find that auto-wakeup from stop can be used instead of the higher current wait mode. Wait
mode typical is 1.3 mA at 3 V and 1 mA at 2 V with fBus = 1 MHz.
Run IDD vs VDD at FEI mode
3.00
2.50
2.00
10 MHz
1.50
1.00
0.50
0.00
4 MHz
1.25 MHz
5.5
5.0
3.3
3.0
2.7
2.0
1.8
1.7
Run IDD (A)
Figure 16. Typical Run I vs. V for FEI Mode
DD
DD
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Electrical Characteristics
3.8
Num
1
External Oscillator (XOSC) Characteristics
Table 9. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient)
C
Rating
Symbol
Min
Typical1 Max Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
flo
fhi
fhi-hgo
fhi-lp
32
1
1
—
—
—
—
38.4 kHz
MHz
16 MHz
MHz
C
High range (RANGE = 1) FEE or FBE mode 2
High range (RANGE = 1, HGO = 1) FBELP mode
High range (RANGE = 1, HGO = 0) FBELP mode
5
1
8
See crystal or resonator
manufacturer’s
2
3
D
D
Load capacitors
C1, C2
recommendation.
Feedback resistor
Low range (32 kHz to 100 kHz)
High range (1 MHz to 16 MHz)
RF
—
—
10
1
—
—
MΩ
kΩ
Series resistor
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
—
—
—
0
100
0
—
—
—
4
5
D
RS
—
—
—
0
0
0
0
10
20
Crystal start-up time 3
t
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)4
High range, high gain (RANGE = 1, HGO = 1)4
—
—
—
—
200
400
5
—
—
—
—
CSTL-LP
t
C
D
ms
CSTL-HGO
t
CSTH-LP
t
—
CSTH-HGO
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
6
FEE or FBE mode 2
FBELP mode
fextal
0.03125
0
—
—
5
40
MHz
1
Typical data was characterized at 5.0 V, 25°C or is recommended value.
The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
2
3
This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to
achieve specifications.
4
4 MHz crystal.
MCU
EXTAL
XTAL
RS
RF
C1
Crystal or Resonator
C2
3.9
AC Characteristics
This section describes AC timing characteristics for each peripheral system.
MC9RS08KA8 Series, Rev. 1
18
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.9.1
Control Timing
Table 10. Control Timing
Num
C
Parameter
Bus frequency (tcyc = 1/fBus
Symbol
Min
Typical
Max
Unit
1
2
3
4
5
D
D
D
D
D
)
fBus
0
700
—
1000
—
10
1300
—
MHz
μs
Real time interrupt internal oscillator period
External RESET pulse width1
KBI pulse width2
tRTI
textrst
150
ns
tKBIPW
tKBIPWS
1.5 tcyc
100
—
—
ns
KBI pulse width in stop1
—
—
ns
Port rise and fall time (load = 50 pF)3
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
6
D
t
Rise, tFall
—
—
11
35
—
—
ns
1
This is the shortest pulse guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be recognized.
2
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
3
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.
textrst
RESET
Figure 17. Reset Timing
tKBIPWS
tKBIPW
KBI Pin
(rising or high level)
KBI Pin
(falling or low level)
tKBIPW
tKBIPWS
Figure 18. KBI Pulse Width
MC9RS08KA8 Series, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
19
Electrical Characteristics
3.9.2
TPM/MTIM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 11. TPM Input Timing
Num
C
Rating
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTPMext
tTPMext
tclkh
DC
4
fBus/4
—
MHz
tcyc
tcyc
tcyc
tcyc
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 19. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 20. Timer Input Capture Pulse
3.10 Analog Comparator (ACMP) Electrical
Table 12. Analog Comparator Electrical Specifications
Num
C
Characteristic
Supply voltage
Symbol
Min
Typical
Max
Unit
1
2
3
4
5
6
7
8
D
P
D
P
C
C
P
C
VDD
IDDAC
VAIN
VAIO
VH
1.80
—
—
20
—
5.5
35
V
Supply current (active)
Analog input voltage1
μA
V
VSS – 0.3
VDD
40
Analog input offset voltage1
Analog Comparator hysteresis1
Analog source impedance1
Analog input leakage current
Analog Comparator initialization delay
20
9.0
—
mV
mV
kΩ
μA
μs
3.0
—
—
—
15.0
10
RAS
IALKG
tAINIT
—
1.0
1.0
—
Analog Comparator bandgap reference
voltage
9
P
VBG
1.1
1.208
1.3
V
1
These data are characterized but not production tested.
MC9RS08KA8 Series, Rev. 1
20
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.11 Internal Clock Source Characteristics
Table 13. Internal Clock Source Specifications
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
1
2
3
4
5
C
P
C
P
C
Average internal reference frequency — untrimmed
Average internal reference frequency — trimmed
DCO output frequency range — untrimmed
DCO output frequency range — trimmed
fint_ut
fint_t
fdco_ut
fdco_t
25
31.25
12.8
16
31.25
39.06
16
41.66
39.0625
21.33
20
kHz
kHz
MHz
MHz
20
Resolution of trimmed DCO output frequency
at fixed voltage and temperature
Δfdco_res_t
—
—
0.2
%fdco
6
C
Total deviation of trimmed DCO output frequency
over voltage and temperature
Δfdco_t
—
—
—
—
2
1
%fdco
ms
FLL acquisition time2 3
tacquire
,
7
8
C
C
Stop recovery time (FLL wakeup to previous acquired
frequency)
t_wakeup
—
—
μs
IREFSTEN=0
IREFSTEN=1
100
86
1
2
3
Data in typical column was characterized at 3.0 V and 5.0 V, 25°C or is typical recommended value.
This parameter is characterized and not tested on each device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBILP) to FLL enabled (FEI, FBI).
3.12 ADC Characteristics
Table 14. 5 Volt 10-bit ADC Operating Conditions
C
Characteristic
Input voltage
Conditions
Symb
Min.
Typical
Max.
Unit
D
C
C
C
VADIN
—
VSS
—
—
8 bit
4.5
3
VDD
—
V
Accuracy
V
DD = 2 V
—
Input capacitance
Input resistance
CADIN
RADIN
—
5.5
5
pF
kΩ
—
10 bit mode
f
ADCK > 4MHz
—
—
—
—
5
10
Analog source resistance
external to MCU
C
D
RAS
kΩ
fADCK < 4MHz
8 bit mode (all valid fADCK
High Speed (ADLPC=0)
Low Power (ADLPC=1)
)
—
—
—
—
10
8.0
8.0
0.4
0.4
ADC conversion clock
frequency
fADCK
MHz
MC9RS08KA8 Series, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
21
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 21. ADC Input Impedance Equivalency Diagram
Table 15. 10-bit ADC Characteristics
Characteristic
Conditions
C
Symb
Min
Typical1
Max
Unit
Supply current
ADLPC = 1
ADLSMP = 1
ADCO = 1
T
IDDAD
—
133
—
μA
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
T
T
C
IDDAD
IDDAD
IDDAD
—
—
—
218
327
—
—
1
μA
μA
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
0.582
mA
Supply current
Stop, reset, module off
High speed (ADLPC = 0)
Low power (ADLPC = 1)
IDDAD
—
—
—
0.011
3.3
2
1
μA
T
T
—
—
ADC asynchronous clock
source
fADACK
MHz
MC9RS08KA8 Series, Rev. 1
Preliminary—Subject to Change Without Notice
22
Freescale Semiconductor
Electrical Characteristics
Table 15. 10-bit ADC Characteristics (continued)
Characteristic
Conditions
C
Symb
Min
Typical1
Max
Unit
Short sample (ADLSMP=0)
Long sample (ADLSMP=1)
Short sample (ADLSMP=0)
Long sample (ADLSMP=1)
10 bit mode
—
—
—
—
—
—
—
—
20
40
—
—
Conversion time (including
sample time)
ADCK
cycles
P
tADC
3.5
—
ADCK
cycles
Sample time
P
C
tADS
ETUE
DNL
23.5
±1
—
±2.5
±1.0
±1.0
±0.5
Total unadjusted error
LSB2
LSB2
8 bit mode
±0.5
±0.5
±0.3
10 bit mode
P
T
Differential non-linearity
8 bit mode
Monotonicity and No-Missing-Codes guaranteed
10 bit mode
8 bit mode
10 bit mode
8 bit mode
10 bit mode
8 bit mode
10 bit mode
8 bit mode
10 bit mode
8 bit mode
—
—
—
—
—
—
—
—
—
—
±0.5
±0.3
±0.5
±0.5
±0.5
±0.5
—
±1.0
±0.5
±1.5
±0.5
±1.5
±0.5
±0.5
±0.5
±2.5
±1
Integral non-linearity
Zero-scale error
C
INL
EZS
EFS
EQ
LSB2
LSB2
LSB2
LSB2
LSB2
P
T
P
T
Full-Scale error
VADIN = VDDA
Quantization error
D
D
—
±0.2
±0.1
Input leakage error
pad leakage3 * RAS
EIL
1
Typical values assume Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are
not tested in production.
2
3
1 LSB = (VREFH – VREFL)/2N
Based on input pad leakage current. Refer to pad electrical.
3.13 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory. For detailed
information about program/erase operations, see the reference manual.
Table 16. Flash Characteristics
Characteristic
Symbol
Min
Typical1
Max
Unit
Supply voltage for program/erase
Program/Erase voltage
VDD
VPP
2.7
—
5.5
V
V
11.8
12
12.2
VPP current
Program
Mass erase
IVPP_prog
IVPP_erase
—
—
—
—
200
100
μA
μA
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Electrical Characteristics
Table 16. Flash Characteristics (continued)
Characteristic
Symbol
Min
Typical1
Max
Unit
Supply voltage for read operation
0 < fBus < 10 MHz
VRead
1.8
—
5.5
V
Byte program time
tprog
tme
thv
20
500
—
—
—
—
40
—
8
μs
ms
ms
Mass erase time
Cumulative program HV time2
Total cumulative HV time
(total of tme & thv applied to device)
thv_total
—
—
2
hours
HVEN to program setup time
PGM/MASS to HVEN setup time
HVEN hold time for PGM
tpgs
tnvs
tnvh
tnvh1
tvps
tvph
tvrs
10
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
μs
μs
μs
μs
ns
ns
ns
μs
5
HVEN hold time for MASS
100
20
20
200
1
V
PP to PGM/MASS setup time
HVEN to VPP hold time
PP rise time3
V
Recovery time
trcv
Program/erase endurance
TL to TH = –40°C to 85°C
1000
15
—
—
cycles
years
Data retention
tD_ret
—
1
Typicals are measured at 25°C.
thv is the cumulative high voltage programming time to the same row before next erase. Same address can not be
programmed more than twice before next erase.
2
3
Fast VPP rise time may potentially trigger the ESD protection structure, which may result in over current flowing into the pad
and cause permanent damage to the pad. External filtering for the VPP power source is recommended. An example VPP
filter is shown in Figure 22.
100 Ω
V
PP
1 nF
12 V
Figure 22. Example V Filtering
PP
MC9RS08KA8 Series, Rev. 1
24
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
tprog
Next
Data
WRITE DATA1
Data
tpgs
PGM
tnvs
tnvh
trcv
HVEN
trs
2
VPP
tvps
tvph
thv
1 Next Data applies if programming multiple bytes in a single row, refer to MC9RS08KA8 Series Reference Manua
2 VDD must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure 23. Flash Program Timing
tme
trcv
MASS
tnvh1
tnvs
HVEN
trs
1
VPP
tvps
tvph
1 VDD must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure 24. Flash Mass Erase Timing
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
Electrical Characteristics
3.14 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
3.14.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 17. Radiated Emissions, Electric Field
Level1
Parameter
Symbol
Conditions
Frequency
fOSC/fBUS
Unit
(Max)
0.15 – 50 MHz
50 – 150 MHz
150 – 500 MHz
500 – 1000 MHz
IEC Level
TBD
TBD
TBD
TBD
TBD
TBD
dBμV
VDD = TBD
TA = 25oC
package type
TBD
Radiated emissions,
electric field
TBD crystal
TBD bus
VRE_TEM
—
—
SAE Level
1
Data based on qualification test results.
3.14.2 Conducted Transient Susceptibility
Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 18.
MC9RS08KA8 Series, Rev. 1
26
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 18. Conducted Susceptibility, EFT/B
Amplitude1
Unit
Parameter
Symbol
Conditions
fOSC/fBUS
Result
(Min)
A
B
C
D
TBD
VDD = TBD
TA = 25°C
package type
TBD
TBD
kV
TBD
Conducted susceptibility, electrical
fast transient/burst (EFT/B)
TBD crystal
TBD bus
VCS_EFT
TBD
1
Data based on qualification test results. Not tested in production.
The susceptibility performance classification is described in Table 19.
Table 19. Susceptibility Performance Classification
Performance Criteria
Result
A
No failure
The MCU performs as designed during and after exposure.
Self-recovering The MCU does not perform as designed during exposure. The MCU returns
B
C
D
failure
automatically to normal operation after exposure is removed.
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.
Soft failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.
Hard failure
Damage
The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.
E
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Ordering Information
4
Ordering Information
This section contains ordering numbers for MC9RS08KA8 series devices. See below for an example of the device numbering
system.
Table 20. Device Numbering System
Memory
Package
Device Number
Flash
RAM
Type
Designator
Document No.
16 PDIP
16 W-SOIC
20 PDIP
PG
WG
PJ
98ASB42431B
98ASB42567B
98ASB42899B
98ASB42343B
8K bytes
4K bytes
254 bytes
126 bytes
MC9RS08KA8
MC9RS08KA4
20 W-SOIC
WJ
MC 9 RS08 KA 8 C XX
Status
Package designator (See Table 20)
(MC = Fully qualified)
Temperature range
(C = –40°C to 85°C)
Approximate memory size (in KB)
Memory
(9 = Flash-Based)
Core
Family
5
Mechanical Drawings
This following pages contain mechanical specifications for MC9RS08KA8 Series package options.
•
•
•
•
16-pin PDIP (plastic dual in-line pin)
16-pin W-SOIC (wide body small outline integrated circuit)
20-pin PDIP (plastic dual in-line pin)
20-pin W-SOIC (wide body small outline integrated circuit)
MC9RS08KA8 Series, Rev. 1
Preliminary—Subject to Change Without Notice
28
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Document Number: MC9RS08KA8
Rev. 1
1/2008
Preliminary—Subject to Change Without Notice
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