MC9S08GW64 [FREESCALE]
HC08 instruction set with added BGND instruction; HC08指令集，增加了BGND指令
| 型号： | MC9S08GW64 |
| 厂家： | 
Freescale |
| 描述： | HC08 instruction set with added BGND instruction |
| 文件： | 总42页 (文件大小：999K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08GW64
Rev. 3, 1/2011
64-LQFP
80-LQFP
ase 91
14 14
MC9S08GW64 Series
Covers: MC9S08GW64 and
Case 840F
7A
C
10 10
MC9S08GW32
8-Bit HCS08 Central Processor Unit (CPU)
comparator can be used as hardware breakpoint. Full mode,
Comparator A compares address and Comparator B compares data.
Supports both tag and force breakpoints
Peripherals
–
–
New version of S08 core with same performace as traditional S08 and
lower power
Up to 20 MHz CPU at 3.6 V to 2.15 V and up to 10 MHz CPU at 3.6 V
to 1.8 V, across temperature range of –40 C to 85 C
HC08 instruction set with added BGND instruction
Support for up to 48 interrupt/reset sources
–
–
LCD — up to 440 or 836 LCD driver with internal charge pump and
option to provide an internally regulated LCD reference that can be
trimmed for contrast control
ADC16 — two analog-to-digital converters; 16-bit resolution; one
dedicated differential per ADC; up to 16-ch; up to 2.5 s conversion
time for 12-bit mode; automatic compare function; hardware
averaging; calibration registers; temperature sensor; internal bandgap
reference channel; operation in stop3; fully functional from 3.6 V to
1.8 V
–
–
On-Chip Memory
–
–
–
Flash read/program/erase over full operating voltage and temperature
Random-access memory (RAM)
Security circuitry to prevent unauthorized access to RAM and flash
contents
–
–
PRACMP —three rail to rail programmable reference analog
comparator; up to 8 inputs; on-chip programmable reference generator
output; selectable interrupt on rising, falling, or either edge of
comparator output; operation in stop3
SCI — four full duplex non-return to zero (NRZ); LIN master extended
break generation; LIN slave extended break detection; wakeup on
active edge; SCI0 designed for AMR operation; TxD of SCI1 and SCI2
can be modulated with timers and RxD can recieved through
PRACMP;
Power-Saving Modes
–
–
Two low power stop modes and reduced power wait mode
Low power run and wait modes allow peripherals to run while voltage
regulator is in standby
Peripheral clock gating register can disable clocks to unused modules,
thereby reducing currents
Very low power external oscillator that can be used in stop2 or stop3
modes to provide accurate clock source to real time counter
6 s typical wakeup time from stop3 mode
–
–
–
–
–
SPI— three full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first
shifting; SPI0 designed for AMR opeartion
IIC — up to 100 kbps with maximum bus loading; multi-master
operation; programmable slave address; interrupt driven byte-by-byte
data transfer; supporting broadcast mode and 10-bit addressing;
supporting SM BUS functionality; can wake from stop3
FTM — 2-channel flextimer module; selectable input capture, output
compare, or buffered edge- or center-aligned PWM on each channel
IRTC — independent real-time clock, independent power domain, 32
bytes RAM, 32.768 kHz input clock optional output to ICS, hardware
calendar, hardware compensation due to crystal or temperature
characteristics, tamper detection and indicator
Clock Source Options
–
–
Oscillator (XOSC1) — Loop-control Pierce oscillator; Crystal or
ceramic resonator of 32.768 kHz; Clock source for iRTC or ICS
Oscillator (XOSC2) — Loop-control Pierce oscillator; Crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz;
optional clock source for ICS
Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal or
external reference (XOSC1, XOSC2); precision trimming of internal
reference allows 0.2% resolution and 2% deviation over temperature
and voltage; supporting CPU/bus frequencies from 1 MHz to 20 MHz
–
–
–
–
–
–
–
PCRC — 16/32 bit programmable cyclic redundancy check for
high-speed CRC calculation
MTIM — two 8-bit and one 16-bit timers; configurable clock inputs
and interrupt generation on overflow
PDB — programmable delay block; optimized for scheduling ADC
conversions
PCNT — position counter; working in stop3 mode without waking
CPU; can be used to generate waveforms like timer
System Protection
–
Watchdog computer operating properly (COP) reset with option to run
from dedicated 1 kHz internal clock source or bus clock
Low-voltage warning with interrupt
Low-voltage detection with reset or interrupt
Illegal opcode and illegal address detection with reset
Flash block protection
–
–
–
–
Input/Output
–
–
–
57 GPIOs including one output-only pin
Eight KBI interrupts with selectable polarity
Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins.
Development Support
–
–
Single-wire background debug interface
Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus 3 more breakpoints in breakpoint unit)
Breakpoint (BKPT) debug module containing three comparators (A, B,
and C) with ability to match addresses in 64 KB space. Each
Package Options
–
–
80-pin LQFP, 64-pin LQFP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2010-2011. All rights reserved.
Table of Contents
1
2
3
Devices in the MC9S08GW64 Series. . . . . . . . . . . . . . . . . . . .3
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .10
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .10
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .11
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .12
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .23
3.8 External Oscillator (XOSCVLP) Characteristics . . . . . .26
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .27
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10.2 Timer (TPM/FTM) Module Timing . . . . . . . . . . 30
3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.11 Analog Comparator (PRACMP) Electricals . . . . . . . . . 34
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.13 VREF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.15 FLASH Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 40
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . 41
Package Information and Mechanical Drawings . . . . . . . . . . 41
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
1
2
5/26/2010
Initial public release
10/29/2010
Completed all the TBDs.
Updated the voltage output data in the Table 20.
Changed the classification marking of |IInT| to C in the Table 8.
3
1/28/2011
Updated Table 7.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08GW64RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
2
Freescale Semiconductor
Devices in the MC9S08GW64 Series
1
Devices in the MC9S08GW64 Series
Table 1 summarizes the feature set available in the MC9S08GW64 series of MCUs.
Table 1. MC9S08GW64 Series Features by MCU and Package
Feature
MC9S08GW64
80-pin
MC9S08GW32
80-pin
64-pin
LQFP
64-pin
LQFP
Package
LQFP
LQFP
FLASH
RAM
65,536 Bytes
4,032 Bytes
32,768 Bytes
2,048 Bytes
ADC01
Single-ended
Channels
7-ch
1
7-ch
0
7-ch
1
7-ch
0
ADC0 Differential
Channels2
ADC1
Single-ended
Channels
7-ch
1
7-ch
1
7-ch
1
7-ch
1
ADC1 Differential
Channels
BKPT
ICS
yes
yes
yes
yes
yes
8-ch
2
yes
yes
yes
yes
yes
8-ch
2
IIC
IRQ
IRTC
KBI
MTIM8
MTIM16
PCNT
PCRC
PDB
yes
yes
yes
yes
3
yes
yes
yes
yes
3
PRACMP
SCI
4
4
SPI
3
3
FTM
2-ch
2-ch
836
440
824
428
836
440
824
428
LCD
VREFO
XOSC
yes
yes
yes
yes
2
2
I/O pins3
57
45
57
45
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
3
Devices in the MC9S08GW64 Series
1
There are two 16-bit ADC modules, so two parallel conversions at two channels can be made
simultaneously.
2
3
Each differential channel consists of two pins (DADPx and DADMx).
The I/O pins include one output-only pin.
The block diagram in Figure 1 shows the structure of the MC9S08GW64 series MCUs.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
4
Freescale Semiconductor
Devices in the MC9S08GW64 Series
VDDA/VSSA
V
V
/V
PTA0/MOSI2/PCNTCH0/SCL/AD2
PTA1/MISO2/PCNTCH1/SDA/AD3
PTA2/SCLK2/FTMCH0/PCNT0/CMPP0
PTA3/SS2/FTMCH1/PCNT1/CMPP1
PTA4/MTIMCLK/RxD2/PCNT2/CMPP2
PTA5/FTMCLK/TxD2/EXTRIG/IRQ
PTA6/CMPOUT0/CLKOUT/BKGD/MS
PDB
DDA SSA
Port A:
VREFH/VREFL
trig[1]
sel[1]
trig[1:0]
sel[1:0]
EXTRIG
/V
REFH REFL
Port A,F,G,H:
AD[15]
AD[15:2]
DADP/M[1]
ADC1
KBI
Port B, D:
KBIP[7:0]
trig[0]
sel[0]
V
V
V
DDA/ SSA
Port A, C, F:
FTMCH[0:1]
FTMCLK
2-Channel FTM
/V
REFH REFL
PTB0/KBIP0/TxD1/EXTAL2
PTB1/KBIP1/RxD1/XTAL2
PTB2/KBIP2/MOSI0/MISO0/RxD0
PTB3/KBIP3/MISO0/MOSI0/TxD0
PTB4/KBIP4/SCLK0/SCL
PTB5/KBIP5/SS0/SDA
Port A,F,G,H:
AD[15:2]
DADP/M[0]
AD[15]
ADC0
VREFO
16-bit MTIM3
8-bit MTIM1
8-bit MTIM2
Port A, F:
MTIMCLK
VDD
VSS1
VSS2
VREG
PTB6/KBIP6/RxD2/LCD0
PTB7/KBIP7/TxD2/LCD1
Port A, F:
MTIMCLK
PTC0/MOSI1/LCD2
PTC1/MISO1/LCD3
PTC2/SCLK1/LCD4
PTC3/SS1/LCD5
Port A, F:
MTIMCLK
PCRC
PTC4/FTMCH0/RxD1/LCD6
PTC5/FTMCH1/TxD1/LCD7
PTC6/PCNTCH0/RxD3/LCD8
PTC7/PCNTCH1/TxD3/LCD9
S08 Core V6
CPU
Port B:
MOSI0 MISO0
SCLK0 SS0
SPI0
SPI1
BKGD/MS
RESETB
Port C, G:
MOSI1 MISO1
SCLK1 SS1
PTD0/KBIP0/MOSI2/LCD10
PTD1/KBIP1/MISO2/LCD11
PTD2/KBIP2/SCLK2/LCD12
PTD3/KBIP3/SS2/LCD13
PTD4/KBIP4/LCD14
PTD5/KBIP5/CLKOUT/LCD15
PTD6/KBIP6/LCD16
BKPT
INT
Port A, D:
MOSI2 MISO2
SCLK2 SS2
SPI2
IIC
SIM
Port A, B:
SDA
PTD7/KBIP7/LCD17
COP
SCL
PTE0/LCD18
PTE1/LCD19
PTE2/LCD20
PTE3/LCD21
PTE4/LCD22
PTE5/LCD23
PTE6/LCD24
PTE7/LCD25
LVD
Port B:
RxD0
TxD0
SCI0
FLASH
Port B, C:
RxD1
SCI1
GW64 64 KB
GW32 32 KB
TxD1
RAM
Port A, B:
RxD2
SCI2
PTF0/LCD26
PTF1/LCD27
PTF2/LCD28
PTF3/LCD29
PTF4/LCD30
PTF5/LCD31
GW64 4 KB
GW32 2 KB
TxD2
Port C, G:
RxD3
SCI3
Internal Clock Source
REF CLK IRCLK
TxD3
PTF6/MTIMCLK/AD4/LCD32
PTF7/FTMCLK/AD5/LCD33
PRACMP0
Port A, G, H:
CMPP0/1/2/3/4/5/6
Clock Check & Select
CMPOUT0
PTG0/MOSI1/AD6/LCD34
PTG1/MISO1/AD7/LCD35
PTG2/SCLK1/AD8/LCD36
PTG3/SS1/AD9/LCD37
PTG4/CMPOUT1/RxD3/AD10/LCD38
PTG5/CMPOUT2/TxD3/AD11/LCD39
PTG6/CMPP3/AD12/PCNT0/LCD40
PTG7/CMPP4/AD13/PCNT1/LCD41
XTAL2
PRACMP1
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT1
XOSC2
EXTAL2
CLKO
XTAL1
PRACMP2
PCNT
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT2
XOSC1
EXTAL1
CLKO
VBAT
TAMPER1
TAMPER2
PTH0/CMPP5/AD14/PCNT2/LCD42
PTH1/RTCCLKOUT/CMPP6/AD15/LCD43
Port A, C, G, H:
PCNT0 PCNT1 PCNT2
PCNTCH0 PCNTCH1
Independent
RTC
The RTC is in a separate
power domain
LCD
Port B, C, D, E, F, G, H:
LCD[0:43]
Figure 1. MC9S08GW64 Series Block Diagram
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
5
Pin Assignments
2
Pin Assignments
This section shows the pin assignments for the MC9S08GW64 series devices.
PTE6/LCD24
PTE7/LCD25
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTC7/PCNTCH1/TxD3/LCD9
PTC6/PCNTCH0/RxD3/LCD8
PTC5/FTMCH1/TxD1/LCD7
PTC4/FTMCH0/RxD1/LCD6
PTC3/SS1/LCD5
PTC2/SCLK1/LCD4
PTC1/MISO1/LCD3
PTC0/MOSI1/LCD2
PTF0/LCD26
PTF1/LCD27
3
4
PTF2/LCD28
PTF3/LCD29
PTF4/LCD30
PTF5/LCD31
5
6
7
8
9
PTF6/MTIMCLK/AD4/LCD32
PTF7/FTMCLK/AD5/LCD33
PTG0/MOSI1/AD6/LCD34
PTG1/MISO1/AD7/LCD35
PTG2/SCLK1/AD8/LCD36
PTG3/SS1/AD9/LCD37
PTB7/KBIP7/TxD2/LCD1
PTB6/KBIP6/RxD2/LCD0
PTB5/KBIP5/SS0/SDA
10
11
12
13
14
15
16
17
18
19
20
80 LQFP
PTB4/KBIP4/SCLK0/SCL
PTB3/KBIP3/MISO0/MOSI0/TxD0
PTB2/KBIP2/MOSI0/MISO0/RxD0
RESET
PTG4/CMPOUT1/RxD3/AD10/LCD38
PTG5/CMPOUT2/TxD3/AD11/LCD39
PTG6/CMPP3/AD12/PCNT0/LCD40
PTG7/CMPP4/AD13/PCNT1/LCD41
PTH0/CMPP5/AD14/PCNT2/LCD42
PTH1/RTCCLKOUT/AD15/LCD43
PTB1/KBIP1/RxD1/CMPP6/XTAL2
PTB0/KBIP0/TxD1/EXTAL2
V
V
SS
DD
PTA6/CMPOUT0/CLKOUT/BKGD/MS
Figure 2. MC9S08GW64 Series in 80-Pin LQFP Package
MC9S08GW64 Series MCU Data Sheet, Rev. 3
6
Freescale Semiconductor
Pin Assignments
PTE6/LCD24
PTE7/LCD25
PTF0/LCD26
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTC7/PCNTCH1/TxD3/LCD9
2
3
PTC6/PCNTCH0/RxD3/LCD8
PTC5/FTMCH1/TxD1/LCD7
PTC4/FTMCH0/RxD1/LCD6
PTB7/KBIP7/TxD2/LCD1
PTB6/KBIP6/RxD2/LCD0
PTB5/KBIP5/SS0/SDA
PTF1/LCD27
4
5
PTF6/MTIMCLK/AD4/LCD32
PTF7/FTMCLK/AD5/LCD33
PTG0/MOSI1/AD6/LCD34
PTG1/MISO1/AD7/LCD35
PTG2/SCLK1/AD8/LCD36
PTG3/SS1/AD9/LCD37
6
7
8
9
PTB4/KBIP4/SCLK0/SCL
PTB3/KBIP3/MISO0/MOSI0/TxD0
PTB2/KBIP2/MOSI0/MISO0/RxD0
RESET
PTB1/KBIP1/RxD1/CMPP6/XTAL2
PTB0/KBIP0/TxD1/EXTAL2
64 LQFP
10
11
12
13
14
15
16
PTG4/CMPOUT1/RxD3/AD10/LCD38
PTG5/CMPOUT2/TxD3/AD11/LCD39
PTG6/CMPP3/AD12/PCNT0/LCD40
PTG7/CMPP4/AD13/PCNT1/LCD41
PTH0/CMPP5/AD14/PCNT2/LCD42
PTH1/RTCCLKOUT/AD15/LCD43
V
V
SS
DD
PTA6/CMPOUT0/CLKOUT/BKGD/MS
Figure 3. MC9S08GW64 Series in 64-Pin LQFP Package
Table 2. Pin Availability by Package Pin-Count
80
64
Port Pin
Default func
Alt 1
Alt 2
Alt3
Alt4
1
2
3
4
5
6
1
2
3
4
PTE6
PTE7
PTF0
PTF1
PTF2
PTF3
PTE6
PTE7
PTF0
PTF1
PTF2
PTF3
LCD24
LCD25
LCD26
LCD27
LCD28
LCD29
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
7
Pin Assignments
Table 2. Pin Availability by Package Pin-Count (continued)
80
64
Port Pin
Default func
Alt 1
Alt 2
Alt3
Alt4
7
PTF4
PTF5
PTF6
PTF7
PTG0
PTG1
PTG2
PTG3
PTG4
PTG5
PTG6
PTG7
PTH0
PTH1
VDDA
PTF4
PTF5
PTF6
PTF7
PTG0
PTG1
PTG2
PTG3
PTG4
PTG5
PTG6
PTG7
PTH0
PTH1
VDDA
LCD30
LCD31
8
9
5
6
MTIMCLK
FTMCLK
MOSI1
AD4
AD5
LCD32
LCD33
LCD34
LCD35
LCD36
LCD37
AD10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
7
AD6
8
MISO1
AD7
9
SCLK1
AD8
10
11
12
13
14
15
16
SS1
AD9
CMPOUT1
CMPOUT2
CMPP3
RxD3
TxD3
AD12
AD13
AD14
AD15
LCD38
LCD39
LCD40
LCD41
LCD42
AD11
PCNT0
PCNT1
PCNT2
LCD43
CMPP4
CMPP5
RTCCLKOUT
17
18
VREFH
VREFH
V
V
SSA
SSA
VREFL
DADP0
DADM0
VREFO
DADP1
DADM1
VBAT
VREFL
DADP0
DADM0
VREFO
DADP1
DADM1
VBAT
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
EXTAL1
XTAL1
TAMPER11
TAMPER2
PTA0
EXTAL1
XTAL1
TAMPER1
TAMPER2
PTA0
MOSI2
MISO2
PCNTCH0
PCNTCH1
FTMCH0
FTMCH1
RxD2
SCL
SDA
AD2
AD3
PTA1
PTA1
PTA2
PTA2
SCLK2
PCNT0
PCNT1
PCNT2
EXTRIG
BKGD/MS
CMPP0
CMPP1
CMPP2
IRQ
PTA3
PTA3
SS2
PTA4
PTA4
MTIMCLK
FTMCLK
CMPOUT0
PTA52
PTA5
TxD2
PTA63
BKGD/MS
CLKOUT
MC9S08GW64 Series MCU Data Sheet, Rev. 3
8
Freescale Semiconductor
Pin Assignments
Alt4
Table 2. Pin Availability by Package Pin-Count (continued)
80
64
Port Pin
Default func
Alt 1
Alt 2
Alt3
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
34
35
36
37
38
39
40
41
42
43
44
VDD
VSS
VDD
VSS
PTB0
PTB11
RESET
PTB2
PTB34
PTB43
PTB53
PTB6
PTB7
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
VSS
PTB0
PTB1
RESET
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
VSS
KBIP0
KBIP1
TxD1
RxD1
EXTAL2
CMPP6
XTAL2
KBIP2
KBIP3
MOSI0
MISO0
SCLK0
SS0
MISO0
MOSI0
SCL
RxD0
TxD0
KBIP4
KBIP5
SDA
KBIP6
RxD2
LCD0
LCD1
KBIP7
TxD2
MOSI1
MISO1
SCLK1
SS1
LCD2
LCD3
LCD4
LCD5
RxD1
45
46
47
48
49
50
51
52
53
54
55
56
FTMCH0
FTMCH1
PCNTCH0
PCNTCH1
KBIP0
LCD6
LCD7
TxD1
RxD3
LCD8
TxD3
LCD9
MOSI2
MISO2
SCLK2
SS2
LCD10
LCD11
LCD12
LCD13
KBIP1
KBIP2
KBIP3
KBIP4
LCD14
CLKOUT
LCD16
LCD17
KBIP5
LCD15
KBIP6
KBIP7
LCD18
LCD19
LCD20
LCD21
57
58
59
60
LCD22
LCD23
VLL3
VLL3
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
9
Electrical Characteristics
Table 2. Pin Availability by Package Pin-Count (continued)
80
64
Port Pin
Default func
Alt 1
Alt 2
Alt3
Alt4
77
78
79
80
61
62
63
64
VLL2
VLL1
VLL2
VLL1
VCAP2
VCAP1
VCAP2
VCAP1
1
2
3
4
TAMPER0 pin is dedicatedly used for Battery Removal Tamper and not exposed on any SoC pins.
PTA5 is with double drive strength.
PTA6 is an output-only pin when it is configured as GPIO.
PTB2, PTB3 and PTB4 are compatible with 5 V devices with a pullup device.
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08GW64 sries of microcontrollers available at the time
of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3. Parameter Classifications
Those parameters are guaranteed during production testing on each individual device.
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
MC9S08GW64 Series MCU Data Sheet, Rev. 3
10
Freescale Semiconductor
Electrical Characteristics
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V or V ) or the programmable pull-up resistor associated with the pin is enabled.
SS
DD
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
ID
–0.3 to +3.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
25
Instantaneous maximum current
Single pin limit (applies to all port pins except PTA5
and PTB1)1, 2, 3
mA
Instantaneous maximum current
ID
50
mA
Single pin limit (applies to PTA5 and PTB1)1,2,3
Storage temperature range
Tstg
–55 to 150
C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine
I/O
the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of
SS
DD
unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
DD
Table 5. Thermal Characteristics
Symbol
Rating
Value
Unit
Operating temperature range
(packaged)
TA
TL to TH
–40 to 85
C
Maximum junction temperature
TJ
95
C
Thermal resistance
Single-layer board
80-pin LQFP
64-pin LQFP
JA
61
70
C/W
Thermal resistance
Four-layer board
80-pin LQFP
64-pin LQFP
JA
48
52
C/W
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
11
Electrical Characteristics
The average chip-junction temperature (T ) in C can be obtained from:
J
T = T + (P )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, C
A
= Package thermal resistance, junction-to-ambient, C/W
JA
P = P P
D
int
I/O
P
P
= I V , Watts — chip internal power
= Power dissipation on input and output pins — user determined
int
I/O
DD DD
For most applications, P P and can be neglected. An approximate relationship between P and T (if P is neglected)
I/O
int
D
J
I/O
is:
P = K (T + 273C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
K = P (T + 273C) + (P )
2
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Symbol
Value
Unit
Human
Body Model
R1
1500
Storage capacitance
C
100
3
pF
Number of pulses per pin
—
Charge
Device
Model
Series resistance
R1
0
Storage capacitance
C
200
3
pF
Number of pulses per pin
—
Latch-up Minimum input voltage limit
Maximum input voltage limit
–2.5
7.5
V
V
MC9S08GW64 Series MCU Data Sheet, Rev. 3
12
Freescale Semiconductor
Electrical Characteristics
Unit
Table 7. ESD and Latch-Up Protection Characteristics
1
No.
Symbol
Min
Max
Rating
VHBM
1
2
3
Human body model (HBM)
Machine Model (MM)
2000
200
—
—
—
V
V
V
VMM
VCDM
Charge device model (CDM)
Latch-up current at TA = 85C
500
(applies to all pins except pin
31EXTAL1 and pin 30 XTAL1 in
80-pin package, applies to all pins
except pin 23 EXTAL1 and pin 24
XTAL1 in 64-pin package)
1002
ILAT
—
—
mA
mA
4
Latch-up current at TA = 85C
(applies to pin 31EXTAL1 and pin
30 XTAL1 in 80-pin package,
applies to pin 23 EXTAL1 and pin
24 XTAL1 in 64-pin package)
623
ILAT
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
2
3
These pins meet JESD78A Class II (section 1.2) Level A (section 1.3) requirement of 100mA.
This pin meets JESD78A Class II (section 1.2) Level B (section 1.3) characterization to 62mA.
3.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num C
Characteristic
Operating Voltage
Symbol
Condition
Min
Typ1
Max
Unit
1
1.8
3.6
—
V
V
2
3
4
C Output high
voltage
All non-LCD pins
low-drive strength
VOH
VDD >1.8 V
ILoad = –0.6 mA
V
V
V
DD – 0.5
—
—
—
—
—
—
—
P
All non-LCD pins
high-drive strength
VDD > 2.7 V
ILoad = –10 mA
DD – 0.5
DD – 0.5
—
—
C
VDD > 1.8 V
ILoad = –3 mA
C Output high
voltage
All LCD/GPIO pins
low-drive strength
VOH
VDD >1.8 V
Load = –0.5 mA
VDD – 0.5
DD – 0.5
—
V
I
P
All LCD/GPIO pins
high-drive strength
VDD > 2.7 V
V
—
ILoad = –2.5 mA
DD > 1.8 V
ILoad = –1 mA
C
V
VDD – 0.5
—
—
D Output high
current
Max total IOH for all ports IOHT
100
mA
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
13
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
5
C Output low
voltage
All non-LCD pins
low-drive strength
VOL
VDD > 1.8 V
ILoad = 0.6 mA
—
—
0.5
V
P
All non-LCD pins
high-drive strength
VDD > 2.7 V
ILoad = 10 mA
—
—
—
—
—
—
—
—
—
—
—
—
0.5
0.5
0.5
0.5
0.5
100
C
VDD > 1.8 V
ILoad = 3 mA
6
C Output low
voltage
All LCD/GPIO pins
low-drive strength
VOL
VDD > 1.8 V
ILoad = 0.5 mA
V
P
All LCD/GPIO pins
high-drive strength
VDD > 2.7 V
ILoad = 3 mA
C
VDD > 1.8 V
ILoad = 1 mA
7
8
D Output low
current
Max total IOL for all ports
IOLT
VIH
mA
V
P Input high all digital inputs
VDD 2.7 V
VDD 1.8 V
VDD 2.7 V
VDD 1.8 V
0.70 x VDD
0.85 x VDD
—
—
—
—
—
—
—
—
voltage
C
9
P Input low
all digital inputs
all digital inputs
VIL
0.35 x VDD
0.30 x VDD
—
voltage
C
—
10 C Input
hysteresis
Vhys
|IIn|
0.06 x VDD
mV
11 P Input
leakage
current
all input only pins
(per pin)
VIn = VDD or VSS
VIn = VDD or VSS
—
—
0.025
0.025
1
1
A
12 P Hi-Z
all input/output
(per pin)
|IOZ
|
A
(off-state)
leakage
current
13 C Total
Total leakage current for all
pins
|IInT
|
VIn = VDD or VSS
—
—
—
—
2
A
k
k
leakage
current2
14 P Pullup,
Pulldown
all digital inputs, when
enabled
RPU,
RPD
17.5
17.5
52.5
52.5
resistors
15 P Pullup,
Pulldown
all digital inputs, when
enabled
RPU,
RPD
resistors
16 D DCinjection Single pin limit
current 3, 4,
IIC
VIN < VSS, VIN > VDD
–0.2
–5
—
—
0.2
5
mA
mA
Total MCU limit, includes
5
sum of all stressed pins
17 C Input Capacitance, all pins
18 C RAM retention voltage
19 C iRTC RAM retention voltage
20 C POR re-arm voltage6
21 D POR re-arm time
CIn
—
—
—
0.6
1.05
1.4
—
8
pF
V
VRAM
ViRAM
VPOR
tPOR
1.0
—
—
V
0.9
10
2.0
—
V
s
MC9S08GW64 Series MCU Data Sheet, Rev. 3
14
Freescale Semiconductor
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
Low-voltage High range — VDD falling
2.11
2.16
2.22
V
22 C detection
threshold
VLVDH
High range — VDD rising
2.16
1.80
1.86
2.36
2.52
2.23
1.85
1.92
2.46
2.49
2.27
1.91
1.99
2.56
2.71
Low-voltage Low range — VDD falling
23 C detection
threshold
V
V
V
VLVDL
Low range — VDD rising
Low-voltage VDD falling, LVWV = 1
24 C warning
threshold
VLVWH
V
DD rising, LVWV = 1
DD falling, LVWV = 0
V
2.10
2.15
—
2.16
2.23
80
2.23
2.26
—
Low-voltage
warning
25
C
VLVWL
Vhys
VDD rising, LVWV = 0
26 C Low-voltage inhibit reset/recover
hysteresis
mV
V
27 P Bandgap Voltage Reference7
VBG
1.15
1.17
1.19
1
2
Typical values are measured at 25C. Characterized, not tested
Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but
characterization data shows that individual pin leakage current maximums are less than 250nA.
3
4
All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
6
7
POR will occur below the minimum voltage.
Factory trimmed at VDD = 3.0 V, Temp = 25C
Figure 4. Non LCD pins I/O Pullup Typical Resistor Values
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
15
Electrical Characteristics
Figure 5. Non LCD pins I/O Pulldown Typical Resistor Values
Figure 6. Typical Low-Side Driver (Sink) Characteristics(Non LCD pins) — Low Drive (PTxDSn = 0)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
16
Freescale Semiconductor
Electrical Characteristics
Figure 7. Typical Low-Side Driver (Sink) Characteristics(Non LCD pins) — High Drive (PTxDSn = 1)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
17
Electrical Characteristics
Figure 8. Typical High-Side (Source) Characteristics (Non LCD pins)— Low Drive (PTxDSn = 0)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
18
Freescale Semiconductor
Electrical Characteristics
Figure 9. Typical High-Side (Source) Characteristics(Non LCD pins) — High Drive (PTxDSn = 1)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
19
Electrical Characteristics
Figure 10. Typical Low-Side Driver (Sink) Characteristics(LCD/GPIO pins) — Low Drive (PTxDSn = 0)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
20
Freescale Semiconductor
Electrical Characteristics
Figure 11. Typical Low-Side Driver (Sink) Characteristics(LCD/GPIO pins) — High Drive (PTxDSn = 1)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
21
Electrical Characteristics
Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO pins)— Low Drive (PTxDSn = 0)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
22
Freescale Semiconductor
Electrical Characteristics
Figure 13. Typical High-Side (Source) Characteristics(LCD/GPIO pins) — High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
VDD
(V)
Bus
Temp
Typ1
Num
C
Parameter
Run supply current
FEI mode, all modules on, running
from Flash
Symbol
Max
Unit
Freq
(C)
1
C
T
C
T
RIDD
20 MHz
2 MHz
17.4
2.6
20.5
—
mA
–40 to 85C
–40 to 85C
–40 to 85C
3
2
3
Run supply current
FEI mode, all modules off, running
from Flash
RIDD
20 MHz
2 MHz
10.5
1.6
—
—
mA
3
3
RIDD
16 kHz
FBILP
158
148
160
23
—
—
—
—
A
T
T
T
T
Run supply current
LPRS=0, all modules off, running
from Flash
16 kHz
FBELP
4
RIDD
16 kHz
FBILP
3
A
–40 to 85C
Run supply current
LPRS=1, all modules off; running
from Flash
16 kHz
FBELP
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
23
Electrical Characteristics
Table 9. Supply Current Characteristics
VDD
(V)
Bus
Temp
Typ1
Num
C
T
T
Parameter
Symbol
Max
Unit
Freq
(C)
5
RIDD
16 kHz
FBILP
3
137
—
A
–40 to 85C
Run supply current
LPRS=1, all modules off; running
from RAM
16 kHz
FBELP
8
—
6
7
C
C
WIDD
WIDD
20 MHz
2 MHz
3
5.4
1.1
131
7.5
—
mA
–40 to 85C
Wait mode supply current,
all modules off
16 kHz
FBILP
3
3
3
3
3
—
A
A
A
A
–40 to 85C
–40 to 85C
–40 to 85C
–40 to 85C
T
T
T
T
Wait mode supply current
LPRS = 0, all modules off
16 kHz
FBELP
123
159
5.6
—
—
—
8
9
WIDD
16 kHz
FBILP
Wait mode supply current
LPRS = 1, all modules off
16 kHz
FBELP
Stop2 mode supply current
S2IDD
N/A
N/A
N/A
N/A
330
1622
6000
—
1000
—
–40 to 25C
70C
C
C
C
C
—
85C
nA
2
3
2
—
–40 to 25C
70C
—
—
—
—
85C
10
Stop3 mode supply current
No clocks active
S3IDD
474
2608
9000
—
1100
—
–40 to 25C
70C
—
85C
nA
—
–40 to 25C
70C
—
—
—
—
85C
1
Typical values are measured at 25C. Characterized, not tested.
Table 10. Stop Mode Adders (V =3V, V
=V
)
DD
DD
DDA
Temperature (C)
Num
C
Parameter
Condition
Units
-40
25
70
85
1
2
3
4
5
C
C
C
C
C
LPO
100
600
—
100
737
73
150
830
80
175
863
92
nA
nA
A
A
A
ERREFSTEN
IREFSTEN1
LVD1
RANGE = HGO = 0
LVDSE = 1
110
30
112
35
112
40
113
55
PRACMP1
Not using the bandgap (BGBE = 0),
PRG enabled
MC9S08GW64 Series MCU Data Sheet, Rev. 3
24
Freescale Semiconductor
Electrical Characteristics
Table 10. Stop Mode Adders (continued)(V =3V, V
=V
)
DD
DD
DDA
Temperature (C)
Num
C
Parameter
Condition
Units
-40
25
70
85
6
C
VREFO
Not using the bandgap (BGBE = 0), in
tight regulation mode
264
286
296
298
A
7
8
C
C
IRTC
1.4
1.65
88.5
2.01
92.6
2.27
93.6
A
A
ADC1
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0),
single conversion
78.1
9
C
LCD
VIREG enabled for Contrast control, 1/8 0.67
Duty cycle, 8x24 configuration for
driving 192 Segments, 32Hz frame rate,
No LCD glass connected.
0.88
3.74
7.16
A
10
11
C
C
PCNT1
PCNT1
32KHz clock, without PWM output
32KHz clock, with PWM output
33
40
47
50
67
63
77
77
nA
nA
1
Not available in stop2 mode.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
25
Electrical Characteristics
3.8
External Oscillator (XOSCVLP) Characteristics
Reference Figure 14 and Figure 15 for crystal or resonator circuits.
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
1
C
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
2
3
4
D
D
D
Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
See Note 2
See Note 3
C1,C2
Feedback resistor
RF
M
Low range, low power (RANGE=0, HGO=0)2
Low range, high gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
—
—
—
—
10
1
—
—
—
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
—
—
—
—
100
0
—
—
—
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
RS
k
8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
5
6
C
D
Crystal start-up time 4
Low range, low power
Low range, high gain
High range, low power
High range, high gain
t
—
—
—
—
600
400
5
—
—
—
—
CSTL
ms
t
CSTH
15
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
fextal
0.03125
0
—
—
20
20
MHz
MHz
FBE or FBELP mode
1
2
3
4
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
See crystal or resonator manufacturer’s recommendation.
Proper PC board layout procedures must be followed to achieve specifications.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
26
Freescale Semiconductor
Electrical Characteristics
XOSCVLP
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
1
P
Average internal reference frequency — factory trimmed at
VDD = 3.6 V and temperature = 25 C
fint_ft
—
32.768
—
kHz
2
3
4
5
6
P
T
P
P
Average internal reference frequency - trimmed
Internal reference start-up time
fint_t
tIRST
fdco_ut
fdco_t
31.25
—
—
—
39.063
6
kHz
s
DCO output frequency range - untrimmed
DCO output frequency range - trimmed
12.8
16
16.8
—
21.33
20
MHz
MHz
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
fdco_res_t
fdco_res_t
fdco_t
%fdco
%fdco
%fdco
C
C
C
—
—
—
0.1
0.2
0.2
0.4
2
7
8
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
Total deviation from trimmed DCO output frequency over
voltage and temperature
+ 0.5
-1.0
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
27
Electrical Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient) (continued)
Num
C
Characteristic
Symbol
fdco_t
tAcquire
CJitter
Min
—
Typ1
0.5
—
Max
1
1
Unit
%fdco
ms
9
Total deviation from trimmed DCO output frequency over
fixed voltage and temperature range of 0C to 70 C
C
FLL acquisition time 2
10
11
C
C
—
Long term jitter of DCO output clock (averaged over 2-ms
interval) 3
%fdco
—
0.02
0.2
1
2
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
3
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in the crystal oscillator frequency increase the CJitter
percentage for a given interval.
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
28
Freescale Semiconductor
Electrical Characteristics
3.10.1 Control Timing
Table 13. Control Timing
Symbol
fBus
tLPO
textrst
trstdrv
Num
C
D
D
D
D
Rating
Min
Typ1
—
Max
20
Unit
MHz
s
1
2
3
4
5
Bus frequency (tcyc = 1/fBus
)
dc
700
Internal low power oscillator period
—
1300
—
External reset pulse width2
Reset low drive
100
—
ns
34 x tcyc
500
—
—
ns
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
tMSH
D
D
—
—
—
—
ns
6
7
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
100
s
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, IHIL
t
100
1.5 x tcyc
—
—
—
—
ns
ns
D
8
9
D
Keyboard interrupt pulse width
Asynchronous path2
tILIH, IHIL
t
100
1.5 x tcyc
—
—
—
—
Synchronous path4
Port rise and fall time — Non-LCD Pins
Low output drive (PTxDS = 0) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
—
—
16
23
—
—
C
C
Port rise and fall time — Non-LCD Pins
High output drive (PTxDS = 1) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
us
—
—
5
9
—
—
10
tVRR
Voltage Regulator Recovery time
—
6
10
1
2
3
Typical values are based on characterization data at VDD = 3.0 V, 25C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD
.
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5
6
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40C to 85C.
Except for LCD pins in Open Drain mode.
textrst
RESET PIN
Figure 17. Reset Timing
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
29
Electrical Characteristics
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 18. IRQ/KBIPx Timing
3.10.2 Timer (TPM/FTM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 14. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
fBus/4
—
Hz
tcyc
tcyc
tcyc
tcyc
4
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 19. Timer External Clock
tICPW
FTMCHn
FTMCHn
tICPW
MC9S08GW64 Series MCU Data Sheet, Rev. 3
30
Freescale Semiconductor
Electrical Characteristics
3.10.3 SPI Timing
Table 15 and Figure 20 through Figure 23 describe the timing requirements for the SPI system
1,2
.
Table 15. SPI Timing
No.
C
Function
Operating frequency
Symbol
Min
Max
Unit
—
fop
Hz
D
Master
Slave
fBus/2048
0
fBus/2
fBus/4
SPSCK period
Master
Slave
tSPSCK
tLead
tLag
D
D
D
D
D
D
2
4
2048
—
tcyc
tcyc
1
2
3
4
5
6
Enable lead time
Master
Slave
12
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
12
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc –30
tcyc – 30
1024 tcyc
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU
30
30
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
Slave access time
ta
tdis
tv
—
—
1
tcyc
D
D
7
8
9
Slave MISO disable time
1
tcyc
Data valid (after SPSCK edge)
D
D
D
D
Master
Slave
—
—
60
60
ns
ns
Data hold time (outputs)
Master
Slave
tHO
0
0
—
—
ns
ns
10
11
12
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
1.There is 20 pF load on the SPI ports.
2.There are three types of SPI ports in MC9S08GW64 Series. They are ports for AMR, ports shared with LCD pads
and normal ports. This timing is for normal ports condition.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
31
Electrical Characteristics
SS1
(OUTPUT)
1
2
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MS BIN2
LSB IN
BIT 6 . . . 1
9
9
10
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 20. SPI Master Timing (CPHA = 0)
SS1
(OUTPUT)
1
2
11
12
3
12
11
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
10
BIT 6 . . . 1
LSB IN
9
MOSI
(OUTPUT)
MASTER MSB OUT2
PORT DATA
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. SPI Master Timing (CPHA =1)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
32
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
11
12
3
1
12
11
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
10
9
10
MISO
(OUTPUT)
SEE
NOTE 1
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
6
SLAVE
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received.
Figure 22. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
12
2
11
SPSCK
(CPOL = 0)
(INPUT)
4
4
11
12
SPSCK
(CPOL = 1)
(INPUT)
9
10
8
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE
5
MSB OUT
6
NOTE 1
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE:
1. Not defined but normally LSB of character just received.
Figure 23. SPI Slave Timing (CPHA = 1)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
33
Electrical Characteristics
3.11 Analog Comparator (PRACMP) Electricals
Table 16. PRACMP Electrical Specifications
N
C
Characteristic
Supply voltage
Symbol
Min
Typical
Max
Unit
1
2
3
4
D
C
C
C
VPWR
IDDACT1
IDDACT2
IDDDIS
1.8
—
—
—
—
—
—
—
3.6
60
40
2
V
Supply current (active) (PRG enabled)
Supply current (active) (PRG disabled)
A
A
nA
Supply current (ACMP and PRG all
disabled)
5
6
D
C
C
P
C
C
C
C
Analog input voltage
VAIN
VAIO
V
SS – 0.3
—
—
5
VDD
40
V
mV
mV
nA
s
V
Analog input offset voltage
7
Analog comparator hysteresis
Analog input leakage current
VH
3.0
—
—
—
—
—
—
—
20.0
1
8
IALKG
9
Analog comparator initialization delay
Programmable reference generator inputs
Programmable reference generator inputs
tAINIT
VIn1(VDD
—
1.0
VDD
2.75
—
10
11
12
)
1.8
1.8
—
V
In2(VDD25
)
V
Programmable reference generator setup
delay
tPRGST
ns
13
14
C
C
Programmable reference generator step
size
Vstep
–0.25
VIn/32
1
0.25
Vin
LSB
V
Programmable reference generator voltage
range
Vprgout
—
3.12 ADC Characteristics
These specs all assume seperate V
supply for ADC and isolated pad segment for ADC supplies and differential inputs..
DDAD
Spec’s should be de-rated for V
= V condition.
REFH
bg
Table 17. 16-bit ADC Operating Conditions
Charact
eristic
Num
Conditions
Symb
Min
Typ1
Max
Unit
Comment
1
2
Absolute
Delta to VDD (VDD–VDDA
VDDA
1.8
—
0
3.6
V
Supply
voltage
2
)
VDDA
–100
100
mV
Ground
voltage
2
3
4
Delta to VSS (VSS–VSSA
)
VSSA
–100
1.15
0
100
mV
V
Ref
Voltage
High
VREFH
VDDA
VDDA
MC9S08GW64 Series MCU Data Sheet, Rev. 3
34
Freescale Semiconductor
Electrical Characteristics
Table 17. 16-bit ADC Operating Conditions
Charact
eristic
Num
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Ref
5
6
7
Voltage
Low
VREFL
VADIN
CADIN
VSSA
VREFL
—
VSSA
VSSA
V
V
Input
Voltage
—
VREFH
Input
Capacit
ance
16-bit modes
8/10/12-bit modes
8
4
10
5
pF
Input
Resista
nce
8
9
RADIN
—
2
5
k
16 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
0.5
1
2
13/12 bit modes
fADCK > 8MHz
—
—
—
—
—
—
1
2
5
10
Analog
Source
Resista
nce
External to MCU
4MHz < fADCK < 8MHz
fADCK < 4MHz
RAS
k
Assumes
ADLSMP=0
11/10 bit modes
fADCK > 8MHz
—
—
—
—
—
—
2
5
10
11
12
4MHz < fADCK < 8MHz
fADCK < 4MHz
9/8 bit modes
f
ADCK > 8MHz
—
—
—
—
5
10
fADCK < 8MHz
13
14
15
ADLPC = 0, ADHSC = 1
1.0
1.0
1.0
—
—
—
10
5
ADC
Convers
ion
Clock
Freq.
ADLPC = 0, ADHSC = 0
ADLPC = 1, ADHSC = 0
fADCK
MHz
2.5
1
2
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
DC potential difference.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
35
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 24. ADC Input Impedance Equivalency Diagram
Table 18. 16-bit ADC Characteristics full operating range(V
= V
, V
= V
, F
< 10MHz)
REFH
DDAD REFL
SSAD ADCK
Characteristic
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
Supply Current ADLPC = 1, ADHSC = 0
ADLPC = 0, ADHSC = 0
—
—
—
—
—
—
—
215
540
610
0.072
2.4
—
—
—
—
—
—
—
ADLSMP = 0
ADCO = 1
T
IDDA
A
A
ADLPC=0, ADHSC=1
Supply Current Stop, Reset, Module Off
C
IDDA
ADC
Asynchronous
Clock Source
ADLPC = 1, ADHSC = 0
ADLPC = 0, ADHSC = 0
ADLPC = 0, ADHSC = 1
5.2
P
fADACK
MHz
tADACK
=
1/fADACK
6.2
Sample Time
See reference manual for sample times
See reference manual for conversion times
Conversion
Time
1
2
All accuracy numbers assume the ADC is calibrated with VREFH = VDDAD
Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
36
Freescale Semiconductor
Electrical Characteristics
< 4MHz, ADHSC=1)
Table 19. 16-bit ADC Characteristics(V
= V
> 2.7V, V
Min
= V
, F
REFH
DDAD
REFL
SSAD ADCK
Characteristic
Conditions1
C
Symb
Typ2
Max
Unit
Comment
Total
Unadjusted
Error
16-bit differential mode
16-bit single-ended mode
T
TUE
—
—
16
20
24/-24
32/-20
LSB3
32x
Hardware
Averaging
(AVGE = %1
AVGS = %11)
13-bit differential mode
12-bit single-ended mode
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
—
—
1.5
1.75
2.0
2.5
11-bit differential mode
10-bit single-ended mode
—
—
0.7
0.8
1.0
1.25
9-bit differential mode
8-bit single-ended mode
—
—
0.5
0.5
1.0
1.0
Differential
Non-Linearity
16-bit differential mode
16-bit single-ended mode
DNL
—
—
2.5
2.5
3
3
LSB2
LSB2
LSB2
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
1
1
11-bit differential mode
10-bit single-ended mode
—
—
0.5
0.5
0.75
0.75
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5
Integral
Non-Linearity
16-bit differential mode
16-bit single-ended mode
INL
—
—
6.0
10.0
12.0
16.0
13-bit differential mode
12-bit single-ended mode
—
—
1.0
1.0
2.0
2.0
11-bit differential mode
10-bit single-ended mode
—
—
0.5
0.5
1.0
1.0
9-bit differential mode
8-bit single-ended mode
—
—
0.3
0.3
0.5
0.5
Zero-Scale
Error
16-bit differential mode
16-bit single-ended mode
EZS
—
—
4.0
4.0
+16/0
+16/-38
VADIN = VSSAD
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
2.0
2.0
11-bit differential mode
10-bit single-ended mode
—
—
0.4
0.4
1.0
1.0
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
37
Electrical Characteristics
Table 19. 16-bit ADC Characteristics(V
= V
> 2.7V, V
Min
= V
, F
< 4MHz, ADHSC=1)
REFH
DDAD
REFL
SSAD ADCK
Characteristic
Conditions1
C
Symb
Typ2
Max
Unit
Comment
Full-Scale
Error
16-bit differential mode
16-bit single-ended mode
T
EFS
—
—
+8/0
+12/0
+24/0
+24/0
LSB2
VADIN = VDDAD
13-bit differential mode
12-bit single-ended mode
T
T
T
D
—
—
0.7
0.7
2.0
2.5
11-bit differential mode
10-bit single-ended mode
—
—
0.4
0.4
1.0
1.0
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5
Quantization
Error
16 bit modes
EQ
—
—
-1 to 0
—
—
LSB2
Bits
<13 bit modes
0.5
Effective
Number of Bits
16 bit differential mode
Avg = 32
Avg = 16
Avg = 8
Avg = 4
C
ENOB
For
—
—
—
—
—
13.5
13.4
13.2
13
—
—
—
—
—
ADC_DIV=1,
ADC_CLK=10
MHz.
Avg = 1
12.6
16 bit single-ended mode
Avg = 32
Avg = 16
Avg = 8
Avg = 4
—
—
—
—
—
12.39
12.34
12.13
11.94
11.4
—
—
—
—
—
Avg = 1
Signal to Noise
plus Distortion
See ENOB
SINAD
THD
dB
dB
SINAD = 6.02 ENOB+ 1.76
Total Harmonic
Distortion
16-bit differential mode
Avg = 32
C
D
C
D
D
—
—
—
—
—
—
—
—
16-bit single-ended mode
Avg = 32
Spurious Free
Dynamic
Range
16-bit differential mode
Avg = 32
SFDR
dB
91.0
—
96.5
16-bit single-ended mode
Avg = 32
—
IIn = leakage
current
(refer to DC
characteristics)
Input Leakage
Error
all modes
EIL
IIn * RAS
mV
Temp Sensor
Slope
–40C–25C
25C–125C
25C
D
D
m
—
—
—
1.646
1.769
966
—
—
—
mV/C
Temp Sensor
Voltage
VTEMP25
mV
MC9S08GW64 Series MCU Data Sheet, Rev. 3
38
Freescale Semiconductor
Electrical Characteristics
1
2
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0 V, Temp = 25 C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
1 LSB = (VREFH–VREFL)/2N
3
3.13 VREF Characteristics
Table 20. Electrical specifications
Num
C
Characteristic
Supply voltage
Symbol
Min
Max
Unit
1
2
3
P
P
C
VDD
Top
1.80
–40
3.60
85
V
C
Operating temperature range
Maximum Load
10
mA
Operation across Temperature
Untrimmed
4
5
6
7
P
P
C
C
Voltage output room temperature
1.070–1.3
1.180–1.22
1.19–1.200
1.185–1.200
V
V
V
V
Voltage output room temperature
Factory trimmed1
–40 °C
85 °C
Factory trimmed
Factory trimmed
Load Bandwidth
8
9
C
C
Load Regulation Mode = 10 at 1mA
load
Mode = 10
20
100
V/mA
Line Regulation (Power Supply
Rejection)
DC
AC
0.1 from room temp voltage
–60
mV
dB
Power Consumption
I
10
C
Powered down Current (Stop Mode,
VREFEN = 0, VRSTEN = 0)
100
A
11
12
13
14
C
C
C
C
Bandgap only (Mode[1:0] 00)
I
I
I
I
75
125
1.1
A
A
Low Power buffer (Mode[1:0] 01)
Tight Regulation buffer (Mode[1:0] 10)
mA
mA
Low Power and Tight Regulation
(Mode[1:0] 11)
1.15
1
Factory trim is performed at the room temperature.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
39
Electrical Characteristics
3.14 LCD Specifications
Table 21. LCD Electricals, 3-V Glass
C
Characteristic
Symbol
Min
Typ
Max
Unit
D
D
D
D
D
LCD Frame Frequency
fFrame
CLCD
28
30
58
Hz
nF
nF
pF
V
LCD Charge Pump Capacitance
LCD Bypass Capacitance
LCD Glass Capacitance
VIREG
100
100
CBYLCD
Cglass
VIREG
100
100
2000
1.00
1.67
8000
1.15
1.851
HRefSel = 0
HRefSel = 1
.89
1.49
1.5
D
D
VIREG TRIM Resolution
VIREG Ripple
RTRIM
%
VIREG
HRefSel = 0
HRefSel = 1
.1
V
.15
1
VIREG Max can not exceed VDD -0.15 V
3.15 FLASH Specifications
This section provides details about program/erase times and program-erase endurance for the FLASH memory.
Program and erase operations do not require any special power sources other than the normal V supply. For more detailed
DD
information about program/erase operations, see the Memory section.
Table 22. FLASH Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
-40C to 85C
D
Vprog/erase
VRead
fFCLK
1.8
1.8
150
5
3.6
3.6
V
D
D
D
P
P
P
P
D
D
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time2
Mass erase time2
Byte program current3
Page erase current3
V
200
6.67
kHz
s
tFcyc
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
mA
mA
tBurst
4
4000
20,000
4
tPage
tMass
RIDDBP
RIDDPE
—
—
—
—
6
Program/erase endurance4
TL to TH = –40C to + 85C
T = 25C
C
10,000
15
—
100,000
—
—
cycles
years
C
Data retention5
tD_ret
100
—
1
The frequency of this clock is controlled by a software setting.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
40
Freescale Semiconductor
2
3
4
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please
refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
4
Ordering Information
This section contains the ordering information and the device numbering system for the MC9S08GW64 Series.
4.1
Device Numbering System
Example of the device numbering system:
GW 64
C
XX
9
MC S08
Status
(MC = Fully Qualified)
Package designator (see Table 23)
Temperature range
(C = –40C to 85C)
Memory
(9 = FLASH-based)
Core
Approximate FLASH size in KB
Family
5
Package Information and Mechanical Drawings
Table 23 provides the available package types and their document numbers. The latest package outline/mechanical drawings
are available on the MC9S08GW64 Series Product Summary pages at http://www.freescale.com.
To view the latest drawing, either:
•
•
Click on the appropriate link in Table 23, or
®
Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate document number
(from Table 23) in the “Enter Keyword” search box at the top of the page.
Table 23. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
80
64
Low Quad Flat Package
Low Quad Flat Package
LQFP
LQFP
LK
LH
917A
840F
98ASS23237W
98ASS23234W
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