MC9S08QE8 [FREESCALE]
8-Bit HCS08 Central Processor Unit; 8位HCS08中央处理器
| 型号： | MC9S08QE8 |
| 厂家： | 
Freescale |
| 描述： | 8-Bit HCS08 Central Processor Unit |
| 文件： | 总46页 (文件大小：942K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MC9S08QE8
Rev. 3, 1/2008
20-Pin SOIC
751D-07
MC9S08QE8 Series
Covers: MC9S08QE8 and
MC9S08QE4
32-Pin LQFP
Case 873A
16-Pin PDIP
648
28-Pin SOIC
751F-05
Features
16-Pin TSSOP
948F
•
8-Bit HCS08 Central Processor Unit (CPU)
–
Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of
–40°C to 85°C
–
–
HC08 instruction set with added BGND instruction
Support for up to 32 interrupt/reset sources
•
Peripherals
–
ADC — 10-channel, 12-bit resolution; 2.5 μs conversion time;
automatic compare function; 1.7 mV/°C temperature sensor;
internal bandgap reference channel; operation in stop3; fully
functional from 3.6 V to 1.8 V
•
On-Chip Memory
–
Flash read/program/erase over full operating voltage and
temperature
–
–
Random-Access memory (RAM)
Security circuitry to prevent unauthorized access to RAM and
flash contents
–
ACMPx — Two analog comparators with selectable interrupt on
rising, falling, or either edge of comparator output; compare
option to fixed internal bandgap reference voltage; outputs can be
optionally routed to TPM module; operation in stop3
SCI — Full-Duplex non-return to zero (NRZ); LIN master
extended break generation; LIN slave extended break detection;
wake-up on active edge
SPI — Full-Duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or
LSB-first shifting
IIC — Up to 100 kbps with maximum bus loading; multi-master
operation; programmable slave address; interrupt driven
byte-by-byte data transfer; supporting broadcast mode and 10-bit
addressing
TPMx — Two 3-channel (TPM1 and TPM2); selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel
•
Power-Saving Modes
–
–
–
Two low power stop modes
Reduced power wait mode
Low power run and wait modes allow peripherals to run while
voltage regulator is in standby
Peripheral clock gating register can disable clocks to unused
modules, thereby reducing currents
Very low power external oscillator that can be used in stop2 or
stop3 modes to provide accurate clock source to real time counter
6 μs typical wake-up time from stop3 mode
–
–
–
–
–
–
•
Clock Source Options
–
Oscillator (XOSC) — Loop-Control Pierce oscillator; crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to
16 MHz
Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal
or external reference; precision trimming of internal reference
allows 0.2% resolution and 2% deviation over temperature and
voltage; supporting bus frequencies from 1 MHz to 10 MHz
–
–
–
RTC — (Real-time counter) 8-bit modulus counter with binary or
decimal based prescaler; external clock source for precise time
base, time-of-day, calendar or task scheduling functions; free
running on-chip low power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes
•
•
System Protection
–
•
•
Input/Output
Watchdog computer operating properly (COP) reset with option to
run from dedicated 1 kHz internal clock source or bus clock
Low-Voltage warning with interrupt
Low-Voltage detection with reset or interrupt
Illegal opcode detection with reset
–
–
–
26 GPIOs, one output-only pin and one input-only pin
Eight KBI interrupts with selectable polarity
Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins.
–
–
–
–
–
Package Options
–
Illegal address detection with reset
Flash block protection
32-pin LQFP, 28-pin SOIC, 20-pin SOIC, 16-pin PDIP,
16-pin TSSOP
Development Support
–
–
Single-Wire background debug interface
Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus two more breakpoints in on-chip debug
module)
–
On-Chip in-circuit emulator (ICE) debug module containing two
comparators and nine trigger modes; eight deep FIFO for storing
change-of-flow addresses and event-only data; debug module
supports both tag and force breakpoints
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007–2008. All rights reserved.
Preliminary
Subject to Change Without Notice
Table of Contents
1
2
3
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 8
3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 8
3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . 9
3.5 ESD Protection and Latch-Up Immunity . . . . . . 10
3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 11
3.7 Supply Current Characteristics . . . . . . . . . . . . . 15
3.8 External Oscillator (XOSCVLP) Characteristics 16
3.9 Internal Clock Source (ICS) Characteristics . . . 17
3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1Control Timing. . . . . . . . . . . . . . . . . . . . . 19
3.10.2TPM Module Timing . . . . . . . . . . . . . . . . 20
3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .20
3.11 Analog Comparator (ACMP) Electricals . . . . . . .23
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .24
3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .27
3.14 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .28
3.14.1Conducted Transient Susceptibility. . . . . .28
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .29
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . .29
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
Initial preliminary product preview release.
2
3
7 Nov 2007
22 Jan 2008 Initial public release.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08QE8RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08QE8 Series, Rev. 3
2
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of MC9S08QE8 series MCU.
BKGD/MS
HCS08 CORE
DEBUG MODULE (DBG)
BDC
CPU
REAL-TIME COUNTER
(RTC)
PTA7/TPM2CH2/ADP9
HCS08 SYSTEM CONTROL
PTA6/TPM1CH2/ADP8
SCL
SDA
PTA5/IRQ/TCLK/RESET
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
IIC MODULE (IIC)
PTA4/ACMP1O/BKGD/MS
PTA3/KBIP3/SCL/ADP3
IRQ
RxD
TxD
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
PTA2/KBIP2/SDA/ADP2
COP
IRQ
LVD
PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+
SS
MISO
USER FLASH
(MC9S08QE8 = 8192 BYTES)
(MC9S08QE4 = 4096 BYTES)
PTB7/SCL/EXTAL
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
MOSI
SPSCK
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
TCLK
USER RAM
(MC9S08QE8 = 512 BYTES)
(MC9S08QE4 = 256 BYTES)
TPM1CH0
16-BIT TIMER PWM
MODULE (TPM1)
TPM1CH1
TPM1CH2
TCLK
20 MHz INTERNAL CLOCK
SOURCE (ICS)
TPM2CH0
16-BIT TIMER PWM
MODULE (TPM2)
PTC7/ACMP2–
PTC6/ACMP2+
PTC5/ACMP2O
PTC4
TPM2CH1
TPM2CH2
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
EXTAL
XTAL
(XOSCVLP)
ACMP1O
ACMP1–
ACMP1+
VSSA
VDDA
ANALOG COMPARATOR
(ACMP1)
PTC3
VSS
VDD
PTC2
VOLTAGE REGULATOR
ACMP2O
ACMP2–
ACMP2+
PTC1/TPM2CH2
PTC0/TPM1CH2
VSSA
VDDA
ANALOG COMPARATOR
(ACMP2)
VSSA/VREFL
VDDA/VREFH
PTD3
PTD2
PTD1
PTD0
12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC12)
ADP9–ADP0
KBIP7–KBIP0
VREFL
VREFH
KEYBOARD INTERRUPT
MODULE (KBI)
pins not available on 16-pin packages
pins not available on 16-pin or 20-pin packages
pins not available on 16-pin, 20-pin or 28-pin packages
Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device.
When PTA4 is configured as BKGD, pin becomes bi-directional.
For the 16-pin and 20-pin packages, VSSA/VREFL and VDDA/VREFH are double bonded to VSS and VDD respectively.
Figure 1. MC9S08QE8 Series Block Diagram
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
3
Subject to Change Without Notice
Pin Assignments
2
Pin Assignments
This section shows the pin assignments for the MC9S08QE8 series devices.
31 30 29 28 27 26 25
32
PTA2/KBIP2/SDA/ADP2
PTA3/KBIP3/SCL/ADP3
PTD1
PTD0
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PTD2
VDD
PTD3
VDDA/VREFH
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
VSSA/VREFL
VSS
PTB0/KBIP4/RxD/ADP4
PTB1/KBIP5/TxD/ADP5
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
9
15 16
10 11 12 13 14
Pins shown in bold type are lost in the next lower pin count package.
Figure 2. MC9S08QE8 Series in 32-LQFP
MC9S08QE8 Series, Rev. 3
4
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Pin Assignments
PTC6/ACMP2+
PTC7/ACMP2–
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PTC5/ACMP2O
PTC4
2
PTA5/IRQ/TCLK/RESET
PTA4/ACMP1O/BKGD/MS
VDD
3
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+
PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–
PTA2/KBIP2/SDA/ADP2
4
5
VDDA/VREFH
6
PTA3/KBIP3/SCL/ADP3
VSSA/VREFL
PTA6/TPM1CH2/ADP8
7
VSS
8
PTA7/TPM2CH2/ADP9
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
9
PTB0/KBIP4/RxD/ADP4
10
11
12
13
14
PTB1/KBIP5/TxD/ADP5
PTB2/KBIP6/SPSCK/ADP6
PTB3/KBIP7/MOSI/ADP7
PTC0/TPM1CH2
PTB4/TPM2CH1/MISO
PTC3
PTC2
PTC1/TPM2CH2
Pins shown in bold type are lost in the next lower pin count package.
Figure 3. MC9S08QE8 Series in 28-pin SOIC Package
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+
PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–
PTA2/KBIP2/SDA/ADP2
1
20
19
18
17
16
15
14
13
PTA5/IRQ/TCLK/RESET
PTA4/ACMP1O/BKGD/MS
VDD
2
3
4
PTA3/KBIP3/SCL/ADP3
VSS
5
PTB0/KBIP4/RxD/ADP4
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
6
PTB1/KBIP5/TxD/ADP5
7
PTB2/KBIP6/SPSCK/ADP6
PTB3/KBIP7/MOSI/ADP7
8
9
PTC3
PTC2
12
11
PTC0/TPM1CH2
PTC1/TPM2CH2
10
Pins shown in bold type are lost in the next lower pin count package.
Figure 4. MC9S08QE8 Series in 20-pin SOIC Package
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
5
Subject to Change Without Notice
Pin Assignments
16
15
14
13
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+
PTA1/KBIP1/TPM2CH0ADP1/ACMP1–
PTA2/KBIP2/SDA/ADP2
1
2
3
4
5
6
7
8
PTA5/IRQ/TCLK/RESET
PTA4/ACMP1O/BKGD/MS
VDD
PTA3/KBIP3/SCL/ADP3
VSS
12
11
PTB0/KBIP4/RxD/ADP4
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTB1/KBIP5/TxD/ADP5
10
9
PTB2/KBIP6/SPSCK/ADP6
PTB3/KBIP7/MOSI/ADP7
Figure 5. MC9S08QE8 Series in 16-pin PDIP and TSSOP Packages
MC9S08QE8 Series, Rev. 3
6
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Pin Assignments
Table 2-1. Pin Availability by Package Pin-Count
Pin Number
<-- Lowest Priority --> Highest
Alt 1 Alt 2 Alt 3
32
28
20
16
Port Pin
Alt 4
1
—
—
5
—
—
3
—
—
3
PTD1
PTD0
2
3
VDD
4
6
—
—
4
—
—
4
VDDA/VREFH
VSSA/VREFL
VSS
5
7
6
8
7
9
5
5
PTB7
PTB6
PTB5
PTB4
PTC3
PTC2
PTC1
PTC0
PTB3
SCL1
SDA1
EXTAL
8
10
11
12
13
14
15
16
17
18
19
20
21
22
—
—
23
24
25
26
27
28
1
6
6
XTAL
9
7
7
TPM1CH1 SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
8
8
TPM2CH1 MISO
9
—
—
—
—
9
10
11
12
13
14
15
16
—
—
—
—
17
18
19
20
—
—
—
—
1
TPM2CH22
TPM1CH23
KBIP7
MOSI
SPSCK
TxD
ADP7
10 PTB2
11 PTB1
12 PTB0
KBIP6
ADP6
ADP5
ADP4
ADP9
ADP8
KBIP5
KBIP4
RxD
—
—
—
—
PTA7
PTA6
PTD3
PTD2
TPM2CH22
TPM1CH23
13 PTA3
14 PTA2
15 PTA1
16 PTA0
KBIP3
KBIP2
KBIP1
KBIP0
SCL1
SDA1
TPM2CH0 ADP14
TPM1CH0 ADP04
ADP3
ADP2
ACMP1–4
ACMP1+4
ACMP2–
ACMP2+
ACMP2O
—
—
—
—
1
PTC7
PTC6
PTC5
PTC4
PTA5
PTA4
2
3
IRQ
TCLK
RESET
MS
4
2
2
ACMP1O
BKGD
1
2
3
4
IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2, default reset locations
are PTA3 and PTA2.
TPM2CH2 pin can be repositioned using TPM2CH2PS in SOPT2, default reset location is
PTA7.
TPM1CH2 pin can be repositioned using TPM1CH2PS in SOPT2, default reset location is
PTA6.
If ADC and ACMP1 are enabled, both modules will have access to the pin.
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
7
Subject to Change Without Notice
Electrical Characteristics
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08QE8 series of microcontrollers available at the time
of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
Those parameters are guaranteed during production testing on each individual device.
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V or V ) or the programmable pullup resistor associated with the pin is enabled.
SS
DD
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
–0.3 to 3.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
Instantaneous maximum current
ID
±25
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
°C
MC9S08QE8 Series, Rev. 3
8
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Electrical Characteristics
Input must be current limited to the value specified. To determine the value of the required
1
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine
I/O
the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of
SS
DD
unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
DD
Table 4. Thermal Characteristics
Symbol
Rating
Value
Unit
Operating temperature range
(packaged)
TL to TH
–40 to 85
TA
°C
°C
Maximum junction temperature
TJM
95
Thermal resistance
Single-layer board
32-pin LQFP
28-pin SOIC
20-pin SOIC
16-pin PDIP
16-pin TSSOP
66
57
θJA
71
°C/W
64
108
Thermal resistance
Four-layer board
32-pin LQFP
28-pin SOIC
20-pin SOIC
16-pin PDIP
16-pin TSSOP
47
42
52
47
78
θJA
°C/W
The average chip-junction temperature (T ) in °C can be obtained from:
J
T = T + (P × θ )
JA
Eqn. 1
J
A
D
where:
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
9
Subject to Change Without Notice
Electrical Characteristics
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P = P + P
D
int
I/O
P
P
= I × V , Watts — chip internal power
= Power dissipation on input and output pins — user determined
int
I/O
DD DD
For most applications, P << P and can be neglected. An approximate relationship between P and T (if P is neglected)
I/O
int
D
J
I/O
is:
P = K ÷ (T + 273°C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
K = P × (T + 273°C) + θ × (P )
2
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Symbol
Value
Unit
R1
1500
Ω
pF
—
Human
Body
Storage capacitance
C
100
3
Number of pulses per pin
—
Series resistance
R1
0
Ω
pF
—
V
Machine
Latch-up
Storage capacitance
C
200
3
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
—
—
—
–2.5
7.5
V
Table 6. ESD and Latch-Up Protection Characteristics
1
No.
1
Symbol
VHBM
Min
±2000
±200
Max
—
Unit
V
Rating
Human body model (HBM)
Machine model (MM)
VMM
2
—
V
MC9S08QE8 Series, Rev. 3
10
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics (continued)
VCDM
ILAT
3
4
Charge device model (CDM)
±500
±100
—
—
V
Latch-up current at TA = 85°C
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
3.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics
Num C
Characteristic
Symbol
Condition
Min.
Typical1
Max.
Unit
1
Operating Voltage
1.8
3.6
V
All I/O pins,
low-drive strength
VDD > 1.8 V,
ILoad = –2 mA
C
VDD – 0.5
VDD – 0.5
—
—
—
—
—
—
—
—
—
—
Output high
voltage
VDD > 2.7 V,
ILoad = –10 mA
2
P
C
D
C
P
C
D
VOH
V
mA
V
All I/O pins,
high-drive strength
VDD > 1.8V,
ILoad = –2 mA
VDD – 0.5
—
Output high
current
Max total IOH for all ports IOHT
—
—
—
—
—
—
100
0.5
0.5
0.5
100
3
4
All I/O pins,
low-drive strength
VDD > 1.8 V,
ILoad = 0.6 mA
Output low
voltage
VDD > 2.7 V,
ILoad = 10 mA
VOL
All I/O pins,
high-drive strength
VDD > 1.8 V,
ILoad = 3 mA
Output low
current
5
6
Max total IOL for all ports
all digital inputs
IOLT
VIH
—
mA
V
P
C
P
C
VDD > 2.7 V
VDD > 1.8 V
VDD > 2.7 V
VDD > 1.8 V
0.70 x VDD
—
—
—
—
—
Input high
voltage
0.85 x VDD
—
—
—
0.35 x VDD
0.30 x VDD
Input low
voltage
7
8
all digital inputs
VIL
Input
hysteresis
C
all digital inputs Vhys
—
0.06 x VDD
—
—
mV
Input
P leakage
current
all input only pins
|IIn|
9
VIn = VDD or VSS
—
0.1
1
μA
(Per pin)
Hi-Z
(off-state)
leakage
current
all input/output
10
P
|IOZ
|
VIn = VDD or VSS
—
0.1
—
1
μA
kΩ
(per pin)
all digital inputs, when
enabled (all I/O pins other RPU,
Pullup,
11a P Pulldown
resistors
17.5
52.5
than
RPD
—
PTA5/IRQ/TCLK/RESET
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
11
Subject to Change Without Notice
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
Characteristic
Symbol
Condition
Min.
Typical1
Max.
Unit
RPU,
RPD
Pullup,
11b C Pulldown
resistors
(PTA5/IRQ/TCLK/RESET)
Single pin limit
—
17.5
—
52.5
kΩ
(Note2)
–0.2
–5
—
—
0.2
5
mA
mA
DCinjection
12 C current 3, 4,
IIC
VIN < VSS, VIN > VDD
Total MCU limit, includes
sum of all stressed pins
5
13 C Input Capacitance, all pins
14 C RAM retention voltage
15 C POR re-arm voltage6
16 D POR re-arm time
CIn
—
—
—
—
—
—
—
0.6
1.4
—
8
pF
V
VRAM
VPOR
tPOR
1.0
2.0
—
0.9
10
V
μs
VDD falling
VDD rising
1.80
1.88
1.84
1.92
1.88
1.96
17 P Low-voltage detection threshold
VLVD
VLVW
V
V
VDD falling
VDD rising
18 P Low-voltage warning threshold
Low-voltage inhibit reset/recover
2.08
2.14
2.24
19
P
Vhys
VBG
—
—
—
80
—
mV
V
hysteresis
20 P Bandgap Voltage Reference7
1.15
1.17
1.18
1
2
Typical values are measured at 25°C. Characterized, not tested
The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when
measured externally on the pin.
3
4
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
6
7
Maximum is highest voltage that POR is guaranteed.
Factory trimmed at VDD = 3.0 V, Temp = 25 °C
PULLUP RESISTOR TYPICALS
PULLDOWN RESISTOR TYPICALS
40
35
30
25
20
85°C
40
35
30
25
20
85°C
25°C
25°C
–40°C
–40°C
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6
1.8
2.3
2.8
VDD (V)
3.3
3.6
VDD (V)
Figure 6. Pullup and Pulldown Typical Resistor Values (V = 3.0 V)
DD
MC9S08QE8 Series, Rev. 3
12
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Electrical Characteristics
TYPICAL VOL VS IOL AT VDD = 3.0 V
TYPICAL VOL VS VDD
0.2
0.15
0.1
1.2
1
85°C
25°C
–40°C
0.8
0.6
0.4
0.2
0
85
25
–40
°
C, IOL = 2 mA
C, IOL = 2 mA
C, IOL = 2 mA
0.05
0
°
°
1
2
3
4
0
5
10
OL (mA)
15
20
VDD (V)
I
Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.0 V
1
0.4
0.3
0.2
0.1
85°C
85°C
25°C
–40°C
25°C
0.8
0.6
0.4
0.2
–40°C
IOL = 10 mA
IOL = 6 mA
IOL = 3 mA
0
0
0
10
20
30
1
2
3
4
VDD (V)
IOL (mA)
Figure 8. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
TYPICAL VDD – VOH VS VDD AT SPEC IOH
85 C, IOH = 2 mA
1.2
1
0.25
0.2
85°C
°
25°C
25 C, IOH = 2 mA
°
–40°C
–40 C, IOH = 2 mA
°
0.8
0.6
0.4
0.2
0
0.15
0.1
0.05
0
0
–5
–10
IOH (mA))
–15
–20
1
2
3
4
VDD (V)
Figure 9. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
13
Subject to Change Without Notice
Electrical Characteristics
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.4
0.3
0.2
0.1
85°C
25°C
–40°C
TYPICAL V – V VS I AT V = 3.0 V
DD
OH
OH
DD
0.8
85°C
25°C
0.6
0.4
0.2
0
–40°C
IOH = –10 mA
IOH = –6 mA
I
OH = –3 mA
0
0
–5
–10
–15
–20
–25
–30
1
2
3
4
I
(mA)
OH
VDD (V)
Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
MC9S08QE8 Series, Rev. 3
14
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Electrical Characteristics
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 8. Supply Current Characteristics
Parameter
VDD
(V)
Bus
Freq
Temp
(°C)
Typical1
Num
C
Symbol
Max
Unit
P
T
T
T
10 MHz
1 MHz
10 MHz
1 MHz
5.60
0.80
3.60
0.51
8.2
—
—
—
Run supply current
FEI mode, all modules on
mA
1
RIDD
–40 to 85°C
3
3
Run supply current
FEI mode, all modules off
2
3
RIDD
mA
–40 to 85°C
–40 to 85°C
16 kHz
FBILP
T
T
T
T
T
T
165
105
77
—
—
—
—
—
—
Run supply current
LPRS=0, all modules off
RIDD
3
3
3
μA
16 kHz
FBELP
16 kHz
FBILP
Run supply current
LPRS=1, all modules off; running
from Flash
4
5
RIDD
μA
μA
–40 to 85°C
–40 to 85°C
16 kHz
FBELP
21
16 kHz
FBILP
77
Run supply current
LPRS=1, all modules off; running
from RAM
RIDD
16 kHz
FBELP
7.3
T
T
10 MHz
1 MHz
570
290
—
—
Wait mode supply current
FEI mode, all modules off
6
7
8
WIDD
WIDD
S2IDD
3
3
μA
μA
nA
–40 to 85°C
–40 to 85°C
Wait mode supply current
LPRS = 1, all modules off
16 kHz
FBELP
T
1
—
P
C
P
C
T
—
—
—
—
—
3
2
300
250
400
350
200
2500
2000
6000
5500
—
–40 to 85°C
–40 to 85°C
–40 to 85°C
–40 to 85°C
Stop2 mode supply current
3
Stop3 mode supply current
no clocks active
9
S3IDD
—
nA
nA
2
10
RTC using LPO
—
Stop2 and
Stop 3 adders:
RTC using low
power crystal
oscillator
EREFSTEN=1
IREFSTEN=1
–40 to 85°C
11
T
—
—
—
3
—
nA
500
12
13
14
15
16
T
T
T
T
T
—
—
—
—
—
—
—
—
—
—
300
70
—
—
—
—
—
nA
μA
μA
μA
μA
–40 to 85°C
–40 to 85°C
LVD
100
20
Stop3 adders:
ACMP2
ADC3
0.007
1
2
3
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Also applies to LPRun and LPWait modes.
ADC current measured on VDDA pin on 28-pin and 32-pin devices, adder to VDD on 16-pin and 20-pin packages.
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
15
Subject to Change Without Notice
Electrical Characteristics
3.8
External Oscillator (XOSCVLP) Characteristics
Refer to Figure 11 and Figure 12 for crystal or resonator circuits.
Table 9. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
Characteristic
Symbol
Min.
Typical1 Max. Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
1
C
Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
See Note2
See Note3
C1,C2
2
3
D
D
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
Low range, high gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
—
—
—
—
10
1
—
—
—
RF
MΩ
kΩ
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
—
—
—
—
100
0
—
—
—
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
RS
4
D
≥ 8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
Crystal start-up time 4
Low range, low power
Low range, high gain
High range, low power
High range, high gain
t
—
—
—
—
600
400
5
—
—
—
—
CSTL
5
6
C
D
ms
t
CSTH
15
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
fextal
0.03125
0
—
—
20
20
MHz
MHz
FBE or FBELP mode
1
2
3
4
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0.
See crystal or resonator manufacturer’s recommendation.
Proper PC board layout procedures must be followed to achieve specifications.
MC9S08QE8 Series, Rev. 3
16
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Electrical Characteristics
XOSCVLP
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
Characteristic
Symbol
Min. Typical1 Max.
Unit
Average internal reference frequency — factory trimmed
at VDD = 3.6 V and temperature = 25°C
fint_ft
1
P
—
32.768
—
kHz
Internal reference frequency — user trimmed
Internal reference start-up time
fint_ut
tIRST
fdco_u
2
3
4
P
T
P
31.25
—
—
60
—
39.06
100
60
kHz
μs
DCO output frequency range — trimmed2
48
MHz
DCO output frequency2
Reference = 32768 Hz and DMX32 = 1
fdco_DMX32
Δfdco_res_t
Δfdco_res_t
5
6
7
P
C
C
—
—
—
59.77
± 0.1
± 0.2
—
MHz
%fdco
%fdco
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)
± 0.2
± 0.4
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
Subject to Change Without Notice
17
Electrical Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Num
C
Characteristic
Symbol
Min. Typical1 Max.
Unit
Total deviation of trimmed DCO output frequency over voltage
and temperature
+ 0.5
Δfdco_t
%fdco
8
C
—
± 2
-1.0
± 0.5
—
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0°C to 70 °C
Δfdco_t
tAcquire
CJitter
%fdco
ms
9
C
C
C
—
—
—
± 1
1
FLL acquisition time3
10
11
Long term jitter of DCO output clock (averaged over 2-ms
interval)4
%fdco
0.02
0.2
1
2
3
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
1.00%
0.50%
0.00%
-60
-40
-20
0
20
40
60
80
100
120
-0.50%
-1.00%
-1.50%
-2.00%
Temperature
Figure 13. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08QE8 Series, Rev. 3
18
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Electrical Characteristics
3.10.1 Control Timing
Table 11. Control Timing
Num
C
D
D
D
D
Rating
Symbol
fBus
tLPO
textrst
trstdrv
Min
Typical1
Max
10
Unit
MHz
μs
Bus frequency (tcyc = 1/fBus
)
1
2
3
4
dc
700
—
—
—
—
Internal low power oscillator period
1300
—
External reset pulse width2
Reset low drive
100
ns
34 x tcyc
—
ns
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
tMSH
5
6
D
D
500
100
—
—
—
—
ns
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
μs
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, IHIL
t
100
1.5 × tcyc
—
—
—
—
ns
ns
7
D
8
D
Keyboard interrupt pulse width
Asynchronous path2
tILIH, IHIL
t
100
1.5 × tcyc
—
—
—
—
Synchronous path4
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise, tFall
ns
ns
—
—
16
23
—
—
9
C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
5
9
—
—
1
2
3
Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD
.
4
5
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.
textrst
RESET PIN
Figure 14. Reset Timing
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
19
Subject to Change Without Notice
Electrical Characteristics
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 15. IRQ/KBIPx Timing
3.10.2 TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 12. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
fBus/4
—
Hz
tcyc
tcyc
tcyc
tcyc
4
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 16. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 17. Timer Input Capture Pulse
3.10.3 SPI Timing
Table 13 and Figure 18 through Figure 21 describe the timing requirements for the SPI system.
MC9S08QE8 Series, Rev. 3
20
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Electrical Characteristics
Table 13. SPI Timing
Symbol
No.
C
Function
Operating frequency
Min
Max
Unit
—
D
Master
Slave
fop
tSPSCK
tLead
tLag
fBus/2048
0
fBus/2
fBus/4
Hz
SPSCK period
Master
Slave
1
2
3
4
5
6
D
D
D
D
D
D
2
4
2048
—
tcyc
tcyc
Enable lead time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
7
8
D
D
Slave access time
ta
—
—
1
1
tcyc
tcyc
Slave MISO disable time
tdis
Data valid (after SPSCK edge)
9
D
D
D
D
Master
Slave
tv
—
—
25
25
ns
ns
Data hold time (outputs)
Master
Slave
10
11
12
tHO
0
0
—
—
ns
ns
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
21
Subject to Change Without Notice
Electrical Characteristics
SS1
(OUTPUT)
1
2
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
LSB IN
BIT 6 . . . 1
9
9
10
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
11
2
3
12
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
11
12
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN(2)
BIT 6 . . . 1
BIT 6 . . . 1
LSB IN
9
10
MOSI
(OUTPUT)
MASTER MSB OUT(2)
PORT DATA
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. SPI Master Timing (CPHA =1)
MC9S08QE8 Series, Rev. 3
22
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Electrical Characteristics
SS
(INPUT)
11
12
3
1
12
11
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
10
9
10
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
SLAVE
6
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 20. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
12
2
11
SPSCK
(CPOL = 0)
(INPUT)
4
4
11
12
SPSCK
(CPOL = 1)
(INPUT)
9
10
8
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE
MSB OUT
NOTE
5
6
7
MOSI
(INPUT)
MSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 21. SPI Slave Timing (CPHA = 1)
3.11 Analog Comparator (ACMP) Electricals
Table 14. Analog Comparator Electrical Specifications
C
D
P
Characteristic
Symbol
VDD
Min
1.8
—
Typical
—
Max
Unit
V
Supply voltage
Supply current (active)
3.6
35
IDDAC
20
μA
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
23
Subject to Change Without Notice
Electrical Characteristics
Table 14. Analog Comparator Electrical Specifications (continued)
C
Characteristic
Analog input voltage
Symbol
Min
Typical
Max
Unit
D
P
C
VAIN
VAIO
VH
VSS – 0.3
—
20
VDD
40
V
Analog input offset voltage
—
mV
mV
Analog comparator hysteresis
3.0
9.0
15.0
IALKG
tAINIT
P
C
Analog input leakage current
—
—
—
—
1.0
1.0
μA
μs
Analog comparator initialization delay
3.12 ADC Characteristics
Table 15. 12-bit ADC Operating Conditions
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Supply voltage
Absolute
Delta to VDD (VDD-VDDAD
VDDAD
ΔVDDAD
ΔVSSAD
1.8
—
0
3.6
V
—
—
—
2
)
–100
–100
+100
+100
mV
mV
2
Ground voltage
Delta to VSS (VSS-VSSAD
)
0
Ref Voltage
High
—
—
—
VREFH
VADIN
CADIN
1.8
VREFL
—
VDDAD
—
VDDAD
VREFH
5.5
V
V
—
—
—
Input Voltage
Input
Capacitance
4.5
pF
Input
Resistance
—
RADIN
—
5
7
kΩ
kΩ
—
Analog Source
Resistance
12 bit mode
fADCK > 4MHz
fADCK < 4MHz
—
—
—
—
2
5
10 bit mode
RAS
External to MCU
f
ADCK > 4MHz
—
—
—
—
5
10
fADCK < 4MHz
8 bit mode (all valid fADCK
High Speed (ADLPC=0)
Low Power (ADLPC=1)
)
—
—
—
10
ADC
Conversion
Clock Freq.
0.4
8.0
fADCK
MHz
—
0.4
—
4.0
1
2
Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
DC potential difference.
MC9S08QE8 Series, Rev. 3
24
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 22. ADC Input Impedance Equivalency Diagram
Table 16. 12-bit ADC Characteristics (V = V , V = V
)
REFH
DDAD REFL
SSAD
C
Characteristic
Conditions
Symbol
Min.
Typical1
Max.
Unit
Comment
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
T
—
—
—
—
IDDAD
—
120
—
μA
μA
μA
mA
—
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
T
T
P
IDDAD
IDDAD
IDDAD
—
—
—
202
288
—
—
1
—
—
—
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
0.532
ADC
Asynchronous
Clock Source
High Speed
(ADLPC=0)
tADACK
1/fADACK
=
P
C
2
3.3
2
5
fADACK
MHz
Low Power
(ADLPC=1)
1.25
3.3
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
25
Subject to Change Without Notice
Electrical Characteristics
Table 16. 12-bit ADC Characteristics (V
= V
, V
= V
) (continued)
SSAD
REFH
DDAD REFL
C
Characteristic
Conditions
Symbol
Min.
Typical1
Max.
Unit
Comment
Conversion
Time(Including (ADLSMP=0)
sample time)
Short Sample
See ADC
chapter in the
QE8 Reference
Manual for
conversion time
variances
P
—
—
—
—
20
—
ADCK
cycles
tADC
Long Sample
C
P
C
40
3.5
—
—
—
(ADLSMP=1)
Short Sample
(ADLSMP=0)
Sample Time
ADCK
cycles
tADS
Long Sample
(ADLSMP=1)
23.5
T
P
Total
Unadjusted
Error
(28-pin and
32-pin
packages)
12 bit mode
10 bit mode
—
—
±3.0
±1
—
For 28-pin and
32-pin packages
only.
±2.5
ETUE
LSB2
Includes
quantization
T
8 bit mode
—
±0.5
±1.0
T
P
Total
Unadjusted
Error
(16-pin and
20-pin
package)
12 bit mode
10 bit mode
—
—
±4.0
±1.5
—
For 16-pin and
20-pin packages
only.
±3.5
ETUE
LSB2
Includes
quantization
T
8 bit mode
—
±0.7
±1.5
T
P
T
T
C
T
T
P
T
T
P
T
12 bit mode
10 bit mode3
8 bit mode3
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10 bit mode
8 bit mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±1.75
±0.5
±0.3
±1.5
±0.5
±0.3
±1.5
±0.5
±0.5
±1.0
±0.5
±0.5
–1 to 0
—
—
±1.0
±0.5
—
Differential
Non-Linearity
DNL
INL
EZS
EFS
EQ
LSB2
LSB2
LSB2
LSB2
LSB2
—
Integral
Non-Linearity
±1.0
±0.5
—
—
Zero-Scale
Error
±1.5
±0.5
—
VADIN = VSSAD
VADIN = VDDAD
—
Full-Scale
Error
±1
±0.5
—
Quantization
Error
D
±0.5
±0.5
—
MC9S08QE8 Series, Rev. 3
26
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Electrical Characteristics
) (continued)
Table 16. 12-bit ADC Characteristics (V
= V
, V
= V
REFH
DDAD REFL SSAD
C
Characteristic
Conditions
12 bit mode
Symbol
Min.
Typical1
Max.
Unit
Comment
—
—
—
—
—
±2
—
±4
Input Leakage
Error
Pad leakage4
*RAS
D
10 bit mode
8 bit mode
EIL
±0.2
LSB2
±0.1
±1.2
—
–40°C to 25°C
25°C to 85°C
1.646
1.769
Temp Sensor
Slope
D
D
m
mV/°C
—
Temp Sensor
Voltage
25°C
VTEMP25
—
701.2
—
mV
1
Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
3
4
1 LSB = (VREFH – VREFL)/2N
Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes
Based on input pad leakage current. Refer to pad electricals.
3.13 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
Program and erase operations do not require any special power sources other than the normal V supply. For more detailed
DD
information about program/erase operations, see the Memory section.
Table 17. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
–40°C to 85°C
D
—
Vprog/erase
VRead
fFCLK
1.8
1.8
150
5
3.6
3.6
V
D
D
D
P
P
P
P
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time2
Mass erase time2
Byte program current3
Page erase current3
—
V
—
200
6.67
kHz
μs
tFcyc
—
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
mA
mA
tBurst
4
4000
20,000
4
tPage
tMass
RIDDBP
RIDDPE
—
—
—
—
6
Program/erase endurance4
TL to TH = –40°C to + 85°C
T = 25°C
C
C
—
10,000
15
—
100,000
—
—
cycles
years
Data retention5
tD_ret
100
—
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
27
Subject to Change Without Notice
Electrical Characteristics
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
4
Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
3.14 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
3.14.1 Conducted Transient Susceptibility
Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 18.
Table 18. Conducted Susceptibility, EFT/B
Amplitude1
fOSC/fBUS
Parameter
Symbol
Conditions
Result
Unit
(Min)
A
B
C
D
2.3
VDD = 3.3 V
TA = +25oC
package type
32 LQFP
8 MHz
crystal
8 MHz bus
4.0
Conducted susceptibility, electrical
fast transient/burst (EFT/B)
VCS_EFT
kV
>4.0
>4.0
1
Data based on qualification test results. Not tested in production.
The susceptibility performance classification is described in Table 19.
Table 19. Susceptibility Performance Classification
Performance Criteria
Result
A
No failure
The MCU performs as designed during and after exposure.
Self-recovering The MCU does not perform as designed during exposure. The MCU returns
B
C
failure
automatically to normal operation after exposure is removed.
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.
Soft failure
MC9S08QE8 Series, Rev. 3
28
Preliminary
Freescale Semiconductor
Subject to Change Without Notice
Ordering Information
Table 19. Susceptibility Performance Classification (continued)
Performance Criteria
Result
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.
D
Hard failure
Damage
The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.
E
4
Ordering Information
This section contains ordering information for the device numbering system.
Example of the device numbering system:
8
C
XX
MC 9 S08 QE
Status
(MC = Fully Qualified)
Package designator (see Table 20)
Temperature range
(C = –40°C to 85°C)
Memory
(9 = Flash-based)
Core
Approximate flash size in Kbytes
Family
5
Package Information
Table 20. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
32
28
20
16
16
Low Quad Flat Package
LQFP
SOIC
LC
WL
WJ
PG
TG
873A
751F
751D
648
98ASH70029A
98ASB42345B
98ASB42343B
98ASB42431B
98ASH70247A
Small Outline Integrated Circuit
Small Outline Integrated Circuit
Plastic Dual In-line Package
Thin Shrink Small Outline Package
SOIC
PDIP
TSSOP
948F
5.1
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 20.
MC9S08QE8 Series, Rev. 3
Freescale Semiconductor
Preliminary
29
Subject to Change Without Notice
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Document Number: MC9S08QE8
Rev. 3
1/2008
Preliminary
Subject to Change Without Notice
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