MC9S12KG32VFU [FREESCALE]
Microcontrollers; 微控制器型号: | MC9S12KG32VFU |
厂家: | Freescale |
描述: | Microcontrollers |
文件: | 总126页 (文件大小:6823K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC9S12K Family
Device User Guide
Covers MC9S12KT256, MC9S12KG256,
MC9S12KG128, MC9S12KL128, MC9S12KC128,
MC9S12KG64, MC9S12KL64, MC9S12KC64
and MC9S12KG32
HCS12
Microcontrollers
9S12KT256DGV1/D
V01.09
9 SEP 2004
freescale.com
Device User Guide — 9S12KT256DGV1/D V01.09
Revision History
Version Revision
Author
Description of Changes
Number
Date
01.00
16 JUL 02
Original Version.
Change load cap value on VDD and VDDPLL.
Correct expanded bus timing from 20MHz to 25 MHz.
01.01
01.02
22 NOV 02
15 JAN 03
Move ATD interrupt vector from $ffd0 to $ffd2.
Change PWeh and tDSW parameter in external bus timing.
01.03
01.04
13 JUN 03
18 JUN 03
Expand to a K-Family SoC Guide and include 9S12KT256.
Replace 16-channel ATD with two 8-channel ATDs for 9S12KT256.
Changed to a Device User Guide and added Document number.
Updated Table A-17 Oscillator Characteristics.
Replaced XCLKS with PE7 for Clock Selection diagrams.
Added CTRL to Table 2-1 Signal Properties.
Replaced Burst programming with Row Programming in NVM
electricals.
01.05
14 NOV 03
Changed Digital logic to Internal Logic.
Added LRAE bootloader information.
Changed PWEL, PWEH, tDSW, tACCE, tNAD, tNAV, tRWV, tLSV, tNOV
,
tP0V and tP1V in the external bus timing.
Added voltage regulator characteristics.
01.06
01.07
10 FEB 04
13 MAY 04
Updated Table A-7 3.3V I/O Characteristics.
Updated Table A-16 NVM Timing Characteristics.
Corrected A.6.1.2 Row Programming time tbwpgm equation
Expanded K-family to include 9S12KC128, 9S12KC64, 9S12KL128
and 9S12KL64.
01.08
01.09
20 JUL 04
9 SEP 04
Updated osciilator start up time and supply current characteristics.
Added ATDCTL0 and ATDCTL1 register bits to Sec 1.7.
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Table of Contents
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MC9S12KG(L)(C)128(64)(32) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MC9S12KT(G)256 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . 61
PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]. . . . . . . . . . . . . . . . . . . . . . . . 61
PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 61
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 62
2.3.11 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.12 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.13 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.14 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.15 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.16 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.17 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.18 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.19 PH7 / KWH7 / SS2 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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Device User Guide — 9S12KT256DGV1/D V01.09
2.3.20 PH6 / KWH6 / SCK2 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.21 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.22 PH4 / KWH4 / MISO2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.23 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.24 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.25 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.26 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.27 PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.28 PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . 65
2.3.29 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.30 PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.31 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.3.32 PM7 / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.3.33 PM6 / RXCAN4 — Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.3.34 PM5 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . 66
2.3.35 PM4 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . 66
2.3.36 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . 67
2.3.37 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . 67
2.3.38 PM1 / TXCAN0 — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.39 PM0 / RXCAN0 — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.40 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.41 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.42 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.43 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.44 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.45 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.46 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.47 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.48 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.49 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.50 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.51 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.52 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.53 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.54 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.55 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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Device User Guide — 9S12KT256DGV1/D V01.09
2.3.56 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.4
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
VDDX,VSSX — Power Supply Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . 70
VDDR, VSSR — Power Supply Pins for I/O Drivers & for Internal Voltage Regulator
2.4.1
2.4.2
70
2.4.3
2.4.4
2.4.5
2.4.6
VDD1, VDD2, VSS1, VSS2 — Power Supply Pins for Internal Logic . . . . . . . . . 70
VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 70
VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 70
VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 70
Section 3 System Clock Description
Section 4 Modes of Operation
4.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
Section 5 Resets and Interrupts
5.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2
5.2.1
5.3
5.3.1
Section 6 HCS12 Core Block Description
6.1
6.2
6.3
6.4
CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
HCS12 Background Debug Module (BDM) Block Description . . . . . . . . . . . . . . . . . 78
HCS12 Debug (DBG) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Device User Guide — 9S12KT256DGV1/D V01.09
6.5
6.6
HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . 79
HCS12 Module Mapping Control (MMC) Block Description. . . . . . . . . . . . . . . . . . . 79
Section 7 Analog to Digital Converter (ATD) Block Description
Section 8 Clock Reset Generator (CRG) Block Description
8.1
Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Section 9 EEPROM Block Description
Section 10 Flash EEPROM Block Description
Section 11 IIC Block Description
Section 12 MSCAN Block Description
Section 13 OSC Block Description
Section 14 Port Integration Module (PIM) Block Description
Section 15 Pulse Width Modulator (PWM) Block Description
Section 16 Serial Communications Interface (SCI) Block Description
Section 17 Serial Peripheral Interface (SPI) Block Description
Section 18 Timer (TIM) Block Description
Section 19 Voltage Regulator (VREG) Block Description
19.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
19.1.1 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.1
A.1.2
A.1.3
A.1.4
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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Device User Guide — 9S12KT256DGV1/D V01.09
A.1.5
A.1.6
A.1.7
A.1.8
A.1.9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
A.2 Voltage Regulator (VREG_3V3) Operating Characteristics . . . . . . . . . . . . . . . . . . . 94
A.3 Chip Power-up and LVI/LVR graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.4 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.4.1
A.4.2
Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
A.5 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.5.1
A.5.2
A.5.3
ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.6 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
A.6.1
A.6.2
NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
A.7 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
A.7.1
A.7.2
A.7.3
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.8 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
A.9.1
A.9.2
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
A.10 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
A.10.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Appendix B Package Information
B.1 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
B.2 100-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
B.3 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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Device User Guide — 9S12KT256DGV1/D V01.09
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Device User Guide — 9S12KT256DGV1/D V01.09
List of Figures
Figure 0-1 Order Part number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 1-1 MC9S12KG(L)(C)128(64)(32) Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 1-2 MC9S12KT(G)256 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 1-3 MC9S12KT256 and MC9S12KG256 Memory Map. . . . . . . . . . . . . . . . . . . . 23
Figure 1-4 MC9S12KG128, MC9S12KL128 and MC9S12KC128 Memory Map . . . . . . 24
Figure 1-5 MC9S12KG64, MC9S12KL64 and MC9S12KC64 Memory Map . . . . . . . . . 25
Figure 1-6 MC9S12KG32 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2-1 Pin assignments for 112 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 2-2 Pin assignments for 100 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-3 Pin assignments for 80 QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 2-5 Loop Controlled Pierce Oscillator Connections (PE7=1). . . . . . . . . . . . . . . . 62
Figure 2-6 Full Swing Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . 63
Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure A-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 95
Figure A-2 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure A-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure A-4 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure A-5 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure A-6 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure A-7 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure A-8 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure A-9 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure B-1 80-pin QFP Mechanical Dimensions (case no. 841B). . . . . . . . . . . . . . . . 122
Figure B-2 100-pin LQFP Mechanical Dimensions (case no. 983) . . . . . . . . . . . . . . . 123
Figure B-3 112-pin LQFP Mechanical Dimensions (case no. 987) . . . . . . . . . . . . . . . 124
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Device User Guide — 9S12KT256DGV1/D V01.09
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Device User Guide — 9S12KT256DGV1/D V01.09
List of Tables
Table 0-1 List of MC9S12K-Family members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 0-2 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 1-1 MC9S12KT(G)256 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-2 MC9S12KG(L)(C)128(64)(32) Device Memory Map . . . . . . . . . . . . . . . . . . . . 22
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 43
Table 1-4 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 1-5 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 2-2 Power and Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 2-3 Clock selection based on PE7 during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 5-2 Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 86
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table A-7 3.3V I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table A-8 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table A-9 VREG_3V3 - Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table A-10 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table A-11 5V ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table A-12 3.3V ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table A-13 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table A-14 5V ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table A-15 3.3V ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table A-16 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table A-17 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table A-18 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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Table A-19 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table A-20 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table A-21 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table A-22 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table A-23 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table A-24 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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Device User Guide — 9S12KT256DGV1/D V01.09
Preface
The Device User Guide provides information about the MC9S12K-Family devices made up of standard
HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A
complete set of device manuals also includes all the individual Block Guides of the implemented modules.
In a effort to reduce redundancy all module specific information is located only in the respective Block
Guide. If applicable, special implementation details of the module are given in the block description
sections of this document.
Table 0-1 shows a feature overview of the MC9S12K-Family members.
Table 0-1 List of MC9S12K-Family members
Temp Options1 A/D2 PWM2 TIM2 I/O3
Package CAN SCI SPI IIC
Flash RAM EEPROM
Device
256K 12K
4K
MC9S12KT256
C, V, M
112 LQFP
112 LQFP
80 QFP
3
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
16
8
8
8
7
8
7
7
8
7
7
8
7
7
8
7
8
7
7
8
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
91
91
59
91
79
59
91
59
59
91
79
59
91
59
91
79
59
91
59
256K 12K
4K
MC9S12KG256
C, V, M
C, V, M
112 LQFP
100 LQFP
80 QFP
16
13
8
128K 8K
2K
MC9S12KG128
112 LQFP
80 QFP
16
8
64K
32K
4K
2K
1K
1K
MC9S12KG64
MC9S12KG32
C, V, M
C, V, M
80 QFP
8
112 LQFP
100 LQFP
80 QFP
16
13
8
128K 6K
2K
1K
MC9S12KL128
MC9S12KL64
MC9S12KC128
MC9S12KC64
C, V, M
C, V, M
C, V, M
C, V, M
112 LQFP
80 QFP
16
8
64K
4K
112 LQFP
100 LQFP
80 QFP
16
13
8
128K 6K
None
None
112 LQFP
80 QFP
16
8
64K
4K
NOTES:
1. C: TA = 85˚C, f = 25MHz. V: TA=105˚C, f = 25MHz. M: TA= 125˚C, f = 25MHz
2. Number of channels
3. I/O is the sum of ports capable to act as digital input or output.
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Device User Guide — 9S12KT256DGV1/D V01.09
Figure 0-1 shows the part number coding based on the package and temperature options for the
MC9S12K-Family.
Temperature Options
MC9S12 KT256 C FU
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Package Option
Temperature Option
Package Options
PV = 112LQFP
PU = 100LQFP
FU = 80QFP
Device Title
Controller Family
Figure 0-1 Order Part number Coding
Table 0-2 shows names and versions of the referenced documents throughout the Device User Guide.
Table 0-2 Document References
User Guide
Version Document Order Number
CPU12 Reference Manual
V02
V04
V01
V01
V03
V04
S12CPUV2/D
S12BDMV4/D
S12DBGV1/D
S12INTV1/D
HCS12 Background Debug (BDM) Block Guide
HCS12 Debug (DBG) Block Guide
HCS12 Interrupt (INT) Block Guide
HCS12 Multiplexed Expanded Bus Interface (MEBI) Block Guide
HCS12 Module Mapping Control (MMC) Block Guide
S12MEBIV3/D
S12MMCV4/D
S12ATD10B16CV3/D1
Analog to Digital Converter: 10-Bit, 16 Channels (ATD_10B16C) Block Guide
V03
S12ATD10B8CV3/D2
S12CRGV4/D
Analog to Digital Converter: 10-Bit, 8 Channels (ATD_10B8C) Block Guide
Clock and Reset Generator (CRG) Block Guide
V03
V04
V01
V02
V01
S12EETS2KV1/D(1)
S12EETS4KV2/D(2)
FTS128K1ECCV1/D(1)
2K Byte EEPROM (EETS2K) Block Guide
4K Byte EEPROM (EETS4K) Block Guide
128K Byte Flash with Error Code Correction (FTS128K1ECC) Block Guide
FTS256K2ECCV1/D(2)
S12IICV2/D
256K Byte Flash with Error Code Correction (FTS256K2ECC) Block Guide
Inter IC Bus (IIC) Block Guide
V01
V02
V02
V01
V01
Motorola Scalable CAN (MSCAN) Block Guide
S12MSCANV2/D
S12OSCLCPV1/D
S12KG128PIMV1/D
Oscillator Loop Control Pierce (OSC_LCP) Block Guide
Port Integration Module(1) (PIM_9KG128) Block Guide
Port Integration Module(2) (PIM_9KT256) Block Guide
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block Guide
Serial Communications Interface (SCI) Block Guide
Serial Peripheral Interface (SPI) Block Guide
V01
V01
V02
V03
V01
V01
S12KT256PIMV1/D
S12PWM8B6CV1/D
S12SCIV2/D
S12SPIV3/D
Timer: 16-Bit, 8 Channels (TIM_16B8C) Block Guide
Voltage Regulator (VREG_3V3) Block Guide
S12TIM16B8CV1/D
S12VREG3V3V1/D
NOTES:
1. Block Guide for MC9S12K-Family except MC9S12KT256 and MC9S12KG256.
2. Block Guide for MC9S12KT256 and MC9S12KG256 only.
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Device User Guide — 9S12KT256DGV1/D V01.09
Section 1 Introduction
1.1 Overview
The MC9S12K-Family is a 112/100/80 pin 16-bit Flash-based microcontroller family targeted for high
reliability systems. Members of the MC9S12K-Family have an increased performance in reliability over
the life of the product due to a built-in Error Checking and Correction Code (ECC) in the Flash memory.
The program and erase operations automatically generate six parity bits per word making ECC transparent
to the user.
All members of the MC9S12K-Family are comprised of standard on-chip peripherals including a 16-bit
central processing unit (CPU12), up to 256K bytes of Flash EEPROM, up to 4K bytes of EEPROM, up to
12K bytes of RAM, up to two asynchronous serial communications interface (SCI), up to three serial
peripheral interface (SPI), IIC-bus, an 8-channel IC/OC timer, 16-channel or two 8-channel 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), up to three CAN 2.0 A,
B software compatible modules, 29 discrete digital I/O channels (Port A, Port B, Port E and Port K), and
20 discrete digital I/O lines with interrupt and wakeup capability. The MC9S12K-Family has full 16-bit
data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide
memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power
consumption and performance to be adjusted to suit operational requirements.
1.2 Features
•
HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Memory Map and Interface)
– INT (Interrupt Controller)
– DBG (Debugger)
– BDM (Background Debug Mode)
Oscillator
•
– 4Mhz to 16Mhz frequency range
– Pierce with amplitude loop control
– Clock monitor
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Device User Guide — 9S12KT256DGV1/D V01.09
•
Clock and Reset Generator (CRG)
– Phase-locked loop clock frequency multiplier
– Self Clock mode in absence of external clock
– COP watchdog
– Real Time interrupt (RTI)
•
Memory
– 32K, 64K, 128K or 256K Byte Flash EEPROM
i. Internal program/erase voltage generation
ii. Security and Block Protect bits
iii. Hamming Error Correction Coding (ECC)
– 1K, 2K or 4K Byte EEPROM
– 2K, 4K, 6K, 8K or 12K Byte static RAM
Single-cycle misaligned word accesses without wait states
Analog-to-Digital Converter(s) (ADC)
•
•
– One 16-channel module with 10-bit resolution except for MC9S12KT256 and MC9S12KG256
– Two 8-channel module with 10-bit resolution for MC9S12KT256 and MC9S12KG256
– External conversion trigger capability
8-channel Timer (TIM)
– Programmable input capture or output compare channels
– Simple PWM mode
– Counter Modulo Reset
– External Event Counting
– Gated Time Accumulation
•
•
8-channel Pulse Width Modulator (PWM)
– Programmable period and duty cycle per channel
– 8-bit 8-channel or 16-bit 4-channel
– Edge and center aligned PWM signals
– Emergency shutdown input
Two or Three 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
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Device User Guide — 9S12KT256DGV1/D V01.09
– Low-pass filter wake-up function
– Loop-back for self test operation
Serial interfaces
•
•
•
– Two asynchronous serial communication interface (SCI)
– Three synchronous serial peripheral interface (SPI)
– Inter-IC Bus (IIC)
Internal 2.5V Regulator
– Input voltage range from 3.15V to 5.5V
– Low power mode capability
– Low Voltage Reset (LVR) and Low Voltage Interrupt (LVI)
20 key wake up inputs
– Rising or falling edge triggered interrupt capability
– Digital filter to prevent short pulses from triggering interrupts
– Programmable pull ups and pull downs
•
•
Operating frequency for ambient temperatures (T -40°C to 125°C)
A
– 50MHz equivalent to 25MHz Bus Speed
112-Pin LQFP, 100-Pin LQFP, or 80-Pin QFP package
– I/O lines with 3.3V/5V input and drive capability
– 3.3V/5V A/D converter inputs
1.3 Modes of Operation
•
Normal modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
Special Operating Modes
•
•
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Motorola use only)
– Special Peripheral Mode (Motorola use only)
Each of the above modes of operation can be configured for three Low power submodes
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Device User Guide — 9S12KT256DGV1/D V01.09
– Stop Mode
– Pseudo Stop Mode
– Wait Mode
•
Secure operation, preventing the unauthorized read and write of the memory contents.
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Device User Guide — 9S12KT256DGV1/D V01.09
1.4 MC9S12KG(L)(C)128(64)(32) Block Diagram
VRH
VRL
VRH
VRL
128K Byte Flash EEPROM
ATD
VDDA
VSSA
VDDA
VSSA
2K Byte EEPROM
8K Byte RAM
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
PAD07
PAD15
Voltage Regulator
PIX0
PK0 XADDR14
PK1 XADDR15
PK2
PK3 XADDR17
PK4 XADDR18
PK5 XADDR19
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
PPAGE
XADDR16
Single-wire BDM
BKGD
XTAL
EXTAL
Periodic Interrupt
COP Watchdog
Clock Monitor
OSC
PLL
CPU12
PK7
ECS
VSSPLL
VDDPLL
XFC
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PT0
PT1
PT2
PT3
PT4
PT5
CRG
RESET
TIM
Breakpoints
Debugger
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ
PT6
PT7
R/W
LSTRB
ECLK
MODA
MODB
NOACC/XCLKS
System
Integration
Module
(SIM)
RXD
TXD
RXD
TXD
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
SCI0
SCI1
SPI0
MISO
MOSI
SCK
SS
TEST
Multiplexed Address/Data Bus
RxCAN
TxCAN
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
CAN0
CAN4
DDRA
PTA
DDRB
PTB
RxCAN
TxCAN
KWJ0
KWJ1
KWJ6
KWJ7
PJ0
PJ1
PJ6
PJ7
Multiplexed
Wide Bus
SDA
SCL
IIC
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
PP0
PP1
PP2
PP3
PP4
PP5
Multiplexed
Narrow Bus
PWM
I/O Driver 3.3V/5V OSC/PLL 2.5V
Internal Logic 2.5V
VDD1,2
VSS1,2
PP6
PP7
VDDX
VSSX
V
DDPLL
VSSPLL
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
PH0
PH1
PH2
PH3
PH4
PH5
SPI1
SPI2
A/D Converter 3.3V/5V
Voltage Reference
Voltage Regulator 3.3V/5V
VDDR
VSSR
VDDA
VSSA
PH6
PH7
Figure 1-1 MC9S12KG(L)(C)128(64)(32) Block Diagram
Freescale Semiconductor
19
Device User Guide — 9S12KT256DGV1/D V01.09
1.5 MC9S12KT(G)256 Block Diagram
VRH
VRH
VRL
VDDA
VSSA
VRH
VRL
VDDA
VSSA
VRH
VRL
VDDA
VSSA
256K Byte Flash EEPROM
4K Byte EEPROM
12K Byte RAM
ATD0
VRL
VDDA
VSSA
ATD1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
AN0
PAD08
PAD09
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PAD10
PAD11
PAD12
PAD13
PAD14
VDDR
VSSR
PAD07
PAD15
VREGEN
VDD1,2
VSS1,2
Voltage Regulator
PIX0
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
PK0 XADDR14
PK1 XADDR15
PPAGE
PK2
XADDR16
PK3 XADDR17
PK4 XADDR18
PK5 XADDR19
Single-wire BDM
BKGD
XTAL
EXTAL
Periodic Interrupt
COP Watchdog
Clock Monitor
OSC
PLL
CPU12
PK7
ECS
VSSPLL
VDDPLL
XFC
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PT0
PT1
PT2
PT3
PT4
PT5
CRG
RESET
TIM
Breakpoints
Debugger
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ
R/W
LSTRB
ECLK
MODA
MODB
NOACC/XCLKS
PT6
PT7
System
Integration
Module
(SIM)
RXD
TXD
RXD
TXD
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
SCI0
SCI1
SPI0
MISO
MOSI
SCK
SS
TEST
Multiplexed Address/Data Bus
RxCAN
TxCAN
RxCAN
TxCAN
RxCAN
TxCAN
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
CAN0
CAN1
CAN4
DDRA
PTA
DDRB
PTB
KWJ0
KWJ1
KWJ6
KWJ7
PJ0
PJ1
PJ6
PJ7
Multiplexed
Wide Bus
SDA
SCL
IIC
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
PP0
PP1
PP2
PP3
PP4
PP5
Multiplexed
Narrow Bus
PWM
I/O Driver 3.3V/5V OSC/PLL 2.5V
Internal Logic 2.5V
VDD1,2
VSS1,2
PP6
PP7
VDDX
VSSX
V
DDPLL
VSSPLL
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
PH0
PH1
PH2
PH3
PH4
PH5
SPI1
SPI2
A/D Converter 3.3V/5V
Voltage Reference
Voltage Regulator 3.3V/5V
VDDR
VSSR
VDDA
VSSA
PH6
PH7
Figure 1-2 MC9S12KT(G)256 Block Diagram
Freescale Semiconductor
20
Device User Guide — 9S12KT256DGV1/D V01.09
1.6 Device Memory Map
Table 1-1 shows the device register map of the MC9S12KT256 and MC9S12KG256 after reset. Table
1-2 shows the device register map of the MC9S12KG128(64)(32), MC9S12KL128(64) and
MC9S12KC128(64) after reset.
Table 1-1 MC9S12KT(G)256 Device Memory Map
Address
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Reserved
Size
$000 - $017
24
1
$018
$019
Voltage Regulator (VREG)
1
$01A - $01B
$01C - $01F
$020 - $02F
$030 - $033
$034 - $03F
$040 - $06F
$070 - $07F
$080 - $09F
$0A0 - $0C7
$0C8 - $0CF
$0D0 - $0D7
$0D8 - $0DF
$0E0 - $0E7
$0E8 - $0EF
$0F0 - $0F7
$0F8 - $0FF
$100- $10F
$110- $11B
$11C - $11F
$120 - $13F
$140 - $17F
$180 - $1BF
$1C0 - $23F
$240 - $27F
$280 - $2BF
$2C0 - $2E7
$2E8 - $3FF
Device ID register (PARTID)
CORE (MEMSIZ, IRQ, HPRIO)
CORE (DBG)
2
4
16
4
CORE (PPAGE, Port K)
Clock and Reset Generator (PLL, RTI, COP)
Standard Timer 16-bit 8 channels (TIM)
Reserved
12
48
16
32
40
8
Analog to Digital Converter 10-bit 8 channels (ATD0)
Reserved
Serial Communications Interface 0 (SCI0)
Serial Communications Interface 1 (SCI1)
Serial Peripheral Interface 0 (SPI0)
Inter Integrated Circuit Bus (IIC)
Reserved
8
8
8
8
Serial Peripheral Interface 1 (SPI1)
Serial Peripheral Interface 2 (SPI2)
Flash Control Register
8
8
16
12
4
EEPROM Control Register
Reserved
Analog to Digital Converter 10-bit 8 channels (ATD1)
Motorola Scalable Controller Area Network 0 (CAN0)
Motorola Scalable Controller Area Network 1 (CAN1)
Reserved
32
64
64
128
64
64
40
280
Port Integration Module (PIM)
Motorola Scalable Controller Area Network 4 (CAN4)
Pulse Width Modulator 8-bit 8 channels (PWM)
Reserved
Freescale Semiconductor
21
Device User Guide — 9S12KT256DGV1/D V01.09
Table 1-2 MC9S12KG(L)(C)128(64)(32) Device Memory Map
Address
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Reserved
Size
$000 - $017
24
1
$018
$019
Voltage Regulator (VREG)
Device ID register (PARTID)
CORE (MEMSIZ, IRQ, HPRIO)
CORE (DBG)
1
$01A - $01B
$01C - $01F
$020 - $02F
$030 - $033
$034 - $03F
$040 - $06F
$070 - $07F
$080 - $0AF
$0B0 - $0C7
$0C8 - $0CF
$0D0 - $0D7
$0D8 - $0DF
$0E0 - $0E7
$0E8 - $0EF
$0F0 - $0F7
$0F8 - $0FF
$100- $10F
$110- $11B
$11C - $13F
$140 - $17F
$180 - $23F
$240 - $27F
$280 - $2BF
$2C0 - $2E7
$2E8 - $3FF
2
4
16
4
CORE (PPAGE, Port K)
Clock and Reset Generator (PLL, RTI, COP)
Standard Timer 16-bit 8 channels (TIM)
Reserved
12
48
16
48
24
8
Analog to Digital Converter 10-bit 16 channels (ATD)
Reserved
Serial Communications Interface 0 (SCI0)
Serial Communications Interface 1 (SCI1)
Serial Peripheral Interface 0 (SPI0)
Inter Integrated Circuit Bus (IIC)
Reserved
8
8
8
8
Serial Peripheral Interface 1 (SPI1)
Serial Peripheral Interface 2 (SPI2)
Flash Control Register
8
8
16
12
36
64
192
64
64
40
280
EEPROM Control Register
Reserved
Motorola Scalable Controller Area Network 0 (CAN0)
Reserved
Port Integration Module (PIM)
Motorola Scalable Controller Area Network 4 (CAN4)
Pulse Width Modulator 8-bit 8 channels (PWM)
Reserved
Freescale Semiconductor
22
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-4 illustrates the full user configurable device memory map of MC9S12KT256 and
MC9S12KG256.
$0000
1K Register Space
$03FF
$0000
Mappable to any 2K Boundary
4K Bytes EEPROM
$0000
$0400
$1000
$0FFF
$1000
$3FFF
$4000
Mappable to any 4K Boundary
12K Bytes RAM
Mappable to any 16K Boundary
and alignable to top or bottom
$4000
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
$8000
16K Page Window
sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
$FF00
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
VECTORS
VECTORS
VECTORS
$FFFF
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$1000 - $3FFF: 12K RAM
$0000 - $0FFF: 4K EEPROM (1K hidden behind Register Space)
Figure 1-3 MC9S12KT256 and MC9S12KG256 Memory Map
Freescale Semiconductor
23
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-4 illustrates the full user configurable device memory map of MC9S12KG128, MC9S12KL128
and MC9S12KC128.
$0000
1K Register Space
$03FF
$0800
Mappable to any 2K Boundary
2K Bytes EEPROM
$0000
$0400
$0800
$1000
$2000
$0FFF
$2000
$3FFF
$4000
Mappable to any 2K Boundary
8K Bytes RAM
Mappable to any 8K Boundary
$4000
$8000
$C000
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
16K Page Window
eight * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $1FFF: 8K RAM (1K RAM hidden behind Register Space)
$0000 - $07FF: 2K EEPROM (not visible)
Figure 1-4 MC9S12KG128, MC9S12KL128 and MC9S12KC128 Memory Map
Freescale Semiconductor
24
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-5 illustrates the full user configurable device memory map of MC9S12KG64, MC9S12KL64
and MC9S12KC64.
$0000
1K Register Space
$03FF
$0800
Mappable to any 2K Boundary
1K Bytes EEPROM
Mappable to any 2K Boundary
(1K mapped two times in 2K space)
$0000
$0400
$0800
$1000
$0FFF
$3000
$3FFF
$4000
4K Bytes RAM
$3000
Mappable to any 4K Boundary
$4000
$8000
$C000
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
16K Page Window
four * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (1K RAM hidden behind Register Space)
$0000 - $03FF: 1K EEPROM (not visible)
Figure 1-5 MC9S12KG64, MC9S12KL64 and MC9S12KC64 Memory Map
Freescale Semiconductor
25
Device User Guide — 9S12KT256DGV1/D V01.09
Figure 1-6 illustrates the full user configurable device memory map of MC9S12KG32.
$0000
1K Register Space
$03FF
$0800
Mappable to any 2K Boundary
1K Bytes EEPROM
Mappable to any 2K Boundary
(1K mapped two times in 2K space)
$0000
$0400
$0800
$1000
$0FFF
$3800
$3FFF
2K Bytes RAM
$3800
Mappable to any 2K Boundary
$4000
$8000
$8000
EXT
32K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $07FF: 2K RAM (1K RAM hidden behind Register Space)
$0000 - $03FF: 1K EEPROM (not visible)
Figure 1-6 MC9S12KG32 Memory Map
Freescale Semiconductor
26
Device User Guide — 9S12KT256DGV1/D V01.09
1.7 Detailed Register Map
The following tables show the detailed register map of the MC9S12K-Family.
$0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Address
$0000
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PORTA
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
PORTB
DDRA
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
DDRB
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Reserved
Reserved
Reserved
Reserved
PORTE
DDRE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 1
0
Bit 0
0
Bit 7
Bit 7
6
5
5
4
4
3
3
2
6
0
Bit 2
0
0
PEAR
NOACCE
MODC
PUPKE
PIPOE
NECLK
0
LSTRE
RDWE
0
MODE
MODB
0
MODA
0
IVIS
0
EMK
EME
0
0
0
0
PUCR
PUPEE
PUPBE PUPAE
0
0
0
0
0
0
0
0
0
RDRIV
RDPK
0
RDPE
0
RDPB
0
RDPA
EBICTL
Reserved
ESTR
0
0
0
0
$0010 - $0014
MMC map 1 of 4 (HCS12 Module Mapping Control)
Address
$0010
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
0
Bit 0
RAMHAL
0
Read:
Write:
Read:
Write:
INITRM
RAM15 RAM14 RAM13 RAM12 RAM11
0
0
0
$0011
INITRG
REG14
REG13
REG12
REG11
Freescale Semiconductor
27
Device User Guide — 9S12KT256DGV1/D V01.09
$0010 - $0014
MMC map 1 of 4 (HCS12 Module Mapping Control)
Address
$0012
Name
Bit 7
EE15
0
Bit 6
EE14
0
Bit 5
EE13
0
Bit 4
EE12
0
Bit 3
Bit 2
0
Bit 1
0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
INITEE
EE11
EEON
$0013
$0014
MISC
EXSTR1 EXSTR0 ROMHM ROMON
0
0
0
0
0
0
0
0
Reserved
$0015 - $0016
INT map 1 of 2 (HCS12 Interrupt)
Address
$0015
Name
ITCR
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
WRINT
ADR3
ADR2
ADR1
ADR0
$0016
ITEST
INTE
INTC
INTA
INT8
INT6
INT4
INT2
INT0
$0017 - $0017
MMC map 2 of 4 (HCS12 Module Mapping Control)
Address
$0017
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Reserved
$0018 - $0018
Miscellaneous Peripherals (Device Guide)
Address
$0018
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Reserved
$0019 - $0019
VREG3V3 (Voltage Regulator)
Address
$0019
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
LVDS
Bit 1
LVIE
Bit 0
LVIF
Read:
Write:
VREGCTRL
$001A - $001B
Miscellaneous Peripherals (Device Guide)
Address
$001A
Name
Bit 7
ID15
Bit 6
ID14
Bit 5
ID13
Bit 4
ID12
Bit 3
ID11
Bit 2
ID10
Bit 1
ID9
Bit 0
ID8
Read:
Write:
Read:
Write:
PARTIDH
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
$001B
PARTIDL
Freescale Semiconductor
28
Device User Guide — 9S12KT256DGV1/D V01.09
$001C - $001D
Guide)
MMC map 3 of 4 (HCS12 Module Mapping Control, Device
Address
Name
Bit 7
Read: reg_sw0
Write:
Read: rom_sw1 rom_sw0
Write:
Bit 6
0
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
eep_sw1 eep_sw0
ram_sw2 ram_sw1 ram_sw0
$001C
$001D
MEMSIZ0
0
0
0
0
pag_sw1 pag_sw0
MEMSIZ1
$001E - $001E
MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Address
$001E
Name
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
INTCR
IRQE
IRQEN
$001F - $001F
INT map 2 of 2 (HCS12 Interrupt)
Address
$001F
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Read:
Write:
HPRIO
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
$0020 - $002F
DBG (including BKP) map 1of 1 (HCS12 Debug)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
Bit 0
DBGC1
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
DBGEN
AF
ARM
BF
TRGSEL BEGIN DBGBRK
CAPMOD
$0020
-
CF
0
DBGSC
TRG
$0021
-
DBGTBH
Bit 15
Bit 14
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
$0022
-
DBGTBL
Bit 7
TBF
Bit 6
0
$0023
-
DBGCNT
CNT
$0024
-
DBGCCX
$0025
PAGSEL
EXTCMP
-
DBGCCH
$0026
Bit 15
Bit 7
14
6
13
5
12
4
11
10
2
9
1
Bit 8
Bit 0
RWC
DBGCCL
$0027
-
3
DBGC2
$0028
BKABEN
FULL
BDM
TAGAB BKCEN
TAGC
RWCEN
RWBEN
BKPCT0
DBGC3
$0029
BKAMBH BKAMBL BKBMBH BKBMBL RWAEN
PAGSEL
Bit 15 14
RWA
RWB
BKPCT1
DBGCAX
$002A
EXTCMP
BKP0X
DBGCAH
$002B
13
12
11
10
9
Bit 8
BKP0H
Freescale Semiconductor
29
Device User Guide — 9S12KT256DGV1/D V01.09
$0020 - $002F
DBG (including BKP) map 1of 1 (HCS12 Debug)
Addres
Name
s
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
DBGCAL
BKP0L
read
write
read
write
read
write
read
write
$002C
DBGCBX
BKP1X
$002D
PAGSEL
EXTCMP
DBGCBH
BKP1H
$002E
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
DBGCBL
BKP1L
$002F
$0030 - $0031
MMC map 4 of 4 (HCS12 Module Mapping Control)
Address
$0030
Name
Bit 7
0
Bit 6
0
Bit 5
PIX5
0
Bit 4
PIX4
0
Bit 3
PIX3
0
Bit 2
PIX2
0
Bit 1
PIX1
0
Bit 0
PIX0
0
Read:
Write:
Read:
Write:
PPAGE
0
0
$0031
Reserved
$0032 - $0033
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Address
$0032
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
PORTK
$0033
DDRK
Bit 7
6
5
4
3
2
1
Bit 0
$0034 - $003F
CRG (Clock and Reset Generator)
Address
$0034
Name
SYNR
Bit 7
0
Bit 6
0
Bit 5
SYN5
0
Bit 4
SYN4
0
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
SYN3
SYN2
SYN1
SYN0
0
0
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
REFDV
REFDV3 REFDV2 REFDV1 REFDV0
Read: TOUT7
Write:
TOUT6
TOUT5
TOUT4
TOUT3
LOCK
0
TOUT2
TRACK
0
TOUT1
TOUT0
SCM
0
CTFLG
TEST ONLY
Read:
Write:
Read:
Write:
Read:
Write:
0
0
CRGFLG
CRGINT
CLKSEL
PLLCTL
RTICTL
RTIF
PROF
0
LOCKIF
LOCKIE
SCMIF
SCMIE
RTIE
PLLSEL
PSTP
PLLON
RTR6
SYSWAI ROAWAI PLLWAI
0
CWAI
PRE
RTIWAI COPWAI
Read:
CME
AUTO
ACQ
PCE
RTR1
CR1
SCME
RTR0
CR0
Write:
Read:
Write:
Read:
Write:
0
RTR5
0
RTR4
0
RTR3
0
RTR2
CR2
COPCTL
WCOP
RSBCK
Freescale Semiconductor
30
Device User Guide — 9S12KT256DGV1/D V01.09
$0034 - $003F
CRG (Clock and Reset Generator)
Address
$003D
Name
Bit 7
Bit 6
Bit 5
0
Bit 4
Bit 3
0
Bit 2
0
Bit 1
FCM
Bit 0
0
Read:
Write:
FORBYP
TEST ONLY
RTIBYP COPBYP
PLLBYP
TCTL4
Read: TCTL7
Write:
TCTL6
TCTL5
TCLT3
TCTL2
TCTL1
TCTL0
CTCTL
TEST ONLY
$003E
$003F
Read:
Write:
0
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
ARMCOP
$0040 - $006F
TIM (Timer 16 Bit 8 Channels)
Address
$0040
Name
TIOS
Bit 7
IOS7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
0
0
0
0
0
0
$0041
$0042
$0043
$0044
$0045
$0046
$0047
$0048
$0049
$004A
$004B
$004C
$004D
$004E
$004F
$0050
$0051
$0052
$0053
CFORC
OC7M
Write: FOC7
Read:
FOC6
FOC5
FOC4
FOC3
FOC2
FOC1
FOC0
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
Write:
Read:
Write:
OC7D
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
9
1
0
Bit 8
Bit 0
0
TCNT (hi)
TCNT (lo)
TSCR1
TTOV
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
0
TEN
TOV7
OM7
OM3
TSWAI
TOV6
OL7
TSFRZ
TOV5
OM6
TFFCA
TOV4
OL6
TOV3
OM5
OM1
TOV2
OL5
TOV1
OM4
OM0
TOV0
OL4
TCTL1
TCTL2
TCTL3
TCTL4
TIE
OL3
OM2
OL2
OL1
OL0
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
C7I
TOI
C6I
0
C5I
0
C4I
0
C3I
C2I
C1I
C0I
TSCR2
TFLG1
TFLG2
TC0 (hi)
TC0 (lo)
TC1 (hi)
TC1 (lo)
TCRE
PR2
PR1
PR0
C7F
C6F
0
C5F
0
C4F
0
C3F
0
C2F
0
C1F
0
C0F
0
TOF
Bit 15
Bit 7
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
Bit 8
Bit 0
Bit 8
Bit 0
14
6
13
5
12
4
11
3
10
2
Freescale Semiconductor
31
Device User Guide — 9S12KT256DGV1/D V01.09
$0040 - $006F
TIM (Timer 16 Bit 8 Channels)
Address
$0054
Name
Bit 7
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit 8
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
TC2 (hi)
Bit 15
$0055
$0056
$0057
$0058
$0059
$005A
$005B
$005C
$005D
$005E
$005F
$0060
$0061
$0062
$0063
$0064
$0065
$0066
$0067
$0068
$0069
$006A
$006B
$006C
TC2 (lo)
TC3 (hi)
TC3 (lo)
TC4 (hi)
TC4 (lo)
TC5 (hi)
TC5 (lo)
TC6 (hi)
TC6 (lo)
TC7 (hi)
TC7 (lo)
PACTL
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PAI
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
14
6
13
5
12
4
11
3
10
2
9
1
Bit 7
0
PAEN
0
PAMOD PEDGE
CLK1
0
CLK0
0
PAOVI
PAOVF
1
0
0
0
PAFLG
PAIF
Bit 0
PACNT (hi)
PACNT (lo)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
6
5
4
3
2
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Freescale Semiconductor
32
Device User Guide — 9S12KT256DGV1/D V01.09
$0040 - $006F
TIM (Timer 16 Bit 8 Channels)
Address
$006D
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$006E
$006F
Reserved
Reserved
$0070 - $007F
Reserved space
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$0070
- $007F
Reserved
1
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Address
$0080
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ATDCTL0
WRAP3 WRAP2 WRAP1 WRAP0
0
0
0
ETRIGSEL
ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
$0081
$0082
$0083
$0084
$0085
$0086
$0087
$0088
$0089
$008A
$008B
$008C
$008D
$008E
$008F
ATDCTL1
ATDCTL2
ATDCTL3
ATDCTL4
ATDCTL5
ATDSTAT0
Reserved
ATDTEST0
ATDTEST1
ATDSTAT0
ATDSTAT1
ATDDIEN1
ATDDIEN0
PORTAD1
PORTAD0
ASCIF
ADPU
0
AFFC
S8C
AWAI ETRIGLE ETRIGP ETRIG
ASCIE
FRZ1
PRS1
S4C
S2C
PRS4
MULT
S1C
FIFO
FRZ0
PRS0
SRES8
DJM
SMP1
SMP0
SCAN
PRS3
0
PRS2
DSGN
0
CC
CB
CA
0
CC2
CC1
CC0
SCF
0
ETORF
0
FIFOR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SC
Read: CCF15
Write:
Read: CCF7
Write:
Read:
IEN15
Write:
CCF14
CCF6
CCF13
CCF5
CCF12
CCF4
CCF11
CCF3
CCF10
CCF2
CCF9
CCF1
CCF8
CCF0
IEN8
IEN14
IEN6
IEN13
IEN5
IEN12
IEN4
IEN11
IEN3
IEN10
IEN2
IEN9
IEN1
Read:
Write:
IEN7
IEN0
Read: PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9
Write:
Read: PTAD7
Write:
PTAD8
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
Freescale Semiconductor
33
Device User Guide — 9S12KT256DGV1/D V01.09
1
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Address
$0090
Name
Bit 7
Read: Bit15
Write:
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit8
ATDDR0H
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Bit7
Bit6
14
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
Bit8
0
$0091
$0092
$0093
$0094
$0095
$0096
$0097
$0098
$0099
$009A
$009B
$009C
$009D
$009E
$009F
$00A0
$00A1
$00A2
$00A3
$00A4
$00A5
$00A6
$00A7
$00A8
ATDDR0L
ATDDR1H
ATDDR1L
ATDDR2H
ATDDR2L
ATDDR3H
ATDDR3L
ATDDR4H
ATDDR4L
ATDDR5H
ATDDR5L
ATDDR6H
ATDDR6L
ATDDR7H
ATDDR7L
ATDDR8H
ATDDR8L
ATDDR9H
ATDDR9L
ATDDR10H
ATDDR10L
ATDDR11H
ATDDR11L
ATDDR12H
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
12
11
10
Bit8
Freescale Semiconductor
34
Device User Guide — 9S12KT256DGV1/D V01.09
1
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Address
$00A9
Name
Bit 7
Bit7
Bit 6
Bit6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
ATDDR12L
Read: Bit15
Write:
14
Bit6
14
13
0
12
0
11
0
10
0
9
0
9
0
9
0
Bit8
0
$00AA
$00AB
$00AC
$00AD
$00AE
ATDDR13H
ATDDR13L
ATDDR14H
ATDDR14L
ATDDR15H
ATDDR15L
Read:
Write:
Bit7
Read: Bit15
Write:
13
0
12
0
11
0
10
0
Bit8
0
Read:
Write:
Bit7
Bit6
14
Read: Bit15
Write:
13
0
12
0
11
0
10
0
Bit8
0
Read:
Write:
Bit7
Bit6
$00AF
NOTES:
1. Registers only available on MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64)
1
$00B0 - $00C7
Reserved space
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$00B0
- $00C7
Reserved
NOTES:
1. Reserved space for MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64)
1
$0080 - $009F
ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address
$0080
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ATD0CTL0
WRAP2 WRAP1 WRAP0
0
0
0
0
ETRIGSEL
ETRIGCH2 ETRIGCH1 ETRIGCH0
$0081
$0082
$0083
$0084
$0085
$0086
$0087
$0088
$0089
ATD0CTL1
ATD0CTL2
ATD0CTL3
ATD0CTL4
ATD0CTL5
ATD0STAT0
Reserved
ASCIF
ADPU
0
AFFC
S8C
AWAI ETRIGLE ETRIGP ETRIG
ASCIE
FRZ1
PRS1
S4C
S2C
PRS4
MULT
S1C
FIFO
FRZ0
PRS0
SRES8
DJM
SMP1
SMP0
SCAN
PRS3
0
PRS2
DSGN
0
CC
CB
CA
0
0
0
0
CC2
CC1
CC0
SCF
0
ETORF
0
FIFOR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ATD0TEST0
ATD0TEST1
0
SC
Freescale Semiconductor
35
Device User Guide — 9S12KT256DGV1/D V01.09
1
$0080 - $009F
ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address
$008A
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Reserved
Read: CCF7
Write:
CCF6
0
CCF5
0
CCF4
0
CCF3
0
CCF2
0
CCF1
0
CCF0
0
$008B
$008C
$008D
$008E
$008F
$0090
$0091
$0092
$0093
$0094
$0095
$0096
$0097
$0098
$0099
$009A
$009B
$009C
$009D
$009E
ATD0STAT1
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
0
ATD0DIEN
Reserved
IEN7
0
IEN6
0
IEN5
0
IEN4
0
IEN3
0
IEN2
0
IEN1
0
IEN0
0
Read: PTAD7
Write:
Read: Bit15
Write:
PTAD6
14
PTAD5
13
0
PTAD4
12
0
PTAD3
11
0
PTAD2
10
0
PTAD1
PTAD0
Bit8
0
PORTAD0
ATD0DR0H
ATD0DR0L
ATD0DR1H
ATD0DR1L
ATD0DR2H
ATD0DR2L
ATD0DR3H
ATD0DR3L
ATD0DR4H
ATD0DR4L
ATD0DR5H
ATD0DR5L
ATD0DR6H
ATD0DR6L
ATD0DR7H
ATD0DR7L
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
Read:
Write:
Bit7
Bit6
14
Read: Bit15
Write:
13
0
12
0
11
0
10
0
Bit8
0
Read:
Write:
Bit7
Bit6
14
Read: Bit15
Write:
13
0
12
0
11
0
10
0
Bit8
0
Read:
Write:
Bit7
Bit6
14
Read: Bit15
Write:
13
0
12
0
11
0
10
0
Bit8
0
Read:
Write:
Bit7
Bit6
14
Read: Bit15
Write:
13
0
12
0
11
0
10
0
Bit8
0
Read:
Write:
Bit7
Bit6
14
Read: Bit15
Write:
13
0
12
0
11
0
10
0
Bit8
0
Read:
Write:
Bit7
Bit6
14
Read: Bit15
Write:
13
0
12
0
11
0
10
0
Bit8
0
Read:
Write:
Bit7
Bit6
14
Read: Bit15
Write:
13
0
12
0
11
0
10
0
Bit8
0
Read:
Write:
Bit7
Bit6
$009F
NOTES:
1. Registers only available on MC9S12KT256 and MC9S12KG256
Freescale Semiconductor
36
Device User Guide — 9S12KT256DGV1/D V01.09
1
$00A0 - $00C7
Reserved space
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$00A0
- $00C7
Reserved
NOTES:
1. Reserved space for MC9S12KT256 and MC9S12KG256
$00C8 - $00CF
SCI0 (Asynchronous Serial Interface)
Address
$00C8
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SCI0BDH
SBR12
SBR11
SBR10
SBR9
SBR8
$00C9
$00CA
$00CB
$00CC
$00CD
$00CE
$00CF
SCI0BDL
SCI0CR1
SCI0CR2
SCI0SR1
SCI0SR2
SCI0DRH
SCI0DRL
SBR7
SBR6
SBR5
SBR4
M
SBR3
SBR2
ILT
SBR1
PE
SBR0
PT
LOOPS SCISWAI RSRC
WAKE
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
Read: TDRE
Write:
RDRF
IDLE
OR
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
0
0
RAF
0
BRK13
0
TXDIR
0
R8
T8
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
$00D0 - $00D7
SCI1 (Asynchronous Serial Interface)
Address
$00D0
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SCI1BDH
SBR12
SBR11
SBR10
SBR9
SBR8
$00D1
$00D2
$00D3
$00D4
$00D5
$00D6
$00D7
SCI1BDL
SCI1CR1
SCI1CR2
SCI1SR1
SCI1SR2
SCI1DRH
SCI1DRL
SBR7
SBR6
SBR5
SBR4
M
SBR3
SBR2
ILT
SBR1
PE
SBR0
PT
LOOPS SCISWAI RSRC
WAKE
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
Read: TDRE
Write:
RDRF
IDLE
OR
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
0
0
RAF
0
BRK13
0
TXDIR
0
R8
T8
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
Freescale Semiconductor
37
Device User Guide — 9S12KT256DGV1/D V01.09
$00D8 - $00DF
SPI0 (Serial Peripheral Interface)
Address
$00D8
Name
Bit 7
SPIE
0
Bit 6
SPE
0
Bit 5
SPTIE
0
Bit 4
Bit 3
Bit 2
CPHA
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SPI0CR1
MSTR
CPOL
SSOE
LSBFE
$00D9
$00DA
$00DB
$00DC
$00DD
$00DE
$00DF
SPI0CR2
SPI0BR
MODFEN BIDIROE
SPISWAI SPC0
0
SPIF
0
0
SPPR2
0
SPPR1
SPTEF
SPPR0
SPR2
0
SPR1
0
SPR0
0
MODF
0
0
0
SPI0SR
0
0
0
0
0
Reserved
SPI0DR
Reserved
Reserved
Bit7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit0
0
0
0
0
0
0
0
0
0
$00E0 - $00E7
IIC (Inter IC Bus)
Address
$00E0
Name
IBAD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
$00E1
$00E2
$00E3
$00E4
$00E5
$00E6
$00E7
IBFD
IBCR
IBC7
IBC6
IBC5
IBC4
TX/RX
IBAL
IBC3
IBC2
IBC1
0
IBC0
0
IBEN
TCF
IBIE
MS/SL
IBB
TXAK
0
IBSWAI
RXAK
RSTA
SRW
IAAS
IBSR
IBIF
IBDR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D 0
0
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$00E8 - $00EF
Reserved space
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$00E8
- $00EF
Reserved
Freescale Semiconductor
38
Device User Guide — 9S12KT256DGV1/D V01.09
$00F0 - $00F7
SPI1 (Serial Peripheral Interface)
Address
$00F0
Name
Bit 7
SPIE
0
Bit 6
SPE
0
Bit 5
SPTIE
0
Bit 4
Bit 3
Bit 2
CPHA
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SPI1CR1
MSTR
CPOL
SSOE
LSBFE
$00F1
$00F2
$00F3
$00F4
$00F5
$00F6
$00F7
SPI1CR2
SPI1BR
MODFEN BIDIROE
SPISWAI SPC0
0
SPIF
0
0
SPPR2
0
SPPR1
SPTEF
SPPR0
SPR2
0
SPR1
0
SPR0
0
MODF
0
0
0
SPI1SR
0
0
0
0
0
Reserved
SPI1DR
Reserved
Reserved
Bit7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit0
0
0
0
0
0
0
0
0
0
$00F8 - $00FF
SPI2 (Serial Peripheral Interface)
Address
$00F8
Name
Bit 7
SPIE
0
Bit 6
SPE
0
Bit 5
SPTIE
0
Bit 4
Bit 3
Bit 2
CPHA
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SPI2CR1
MSTR
CPOL
SSOE
LSBFE
$00F9
$00FA
$00FB
$00FC
$00FD
$00FE
$00FF
SPI2CR2
SPI2BR
MODFEN BIDIROE
SPISWAI SPC0
0
SPIF
0
0
SPPR2
0
SPPR1
SPTEF
SPPR0
SPR2
0
SPR1
0
SPR0
0
MODF
0
0
0
SPI2SR
0
0
0
0
0
Reserved
SPI2DR
Reserved
Reserved
Bit7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit0
0
0
0
0
0
0
0
0
0
$0100 - $010F
Flash Control Register
Address
$0100
Name
Bit 7
Read: FDIVLD
Write:
Bit 6
Bit 5
FDIV5
RNV5
Bit 4
FDIV4
RNV4
Bit 3
FDIV3
RNV3
Bit 2
FDIV2
RNV2
Bit 1
Bit 0
FCLKDIV
PRDIV8
FDIV1
FDIV0
Read:
Write:
Read:
Write:
Read:
Write:
KEYEN
SEC
$0101
$0102
$0103
FSEC
FTSTMOD
FCNFG
0
0
0
0
0
0
0
0
WRALL1
0
FDFD
BKSEL(1)
CBEIE
CCIE
KEYACC
DFDIE
Freescale Semiconductor
39
Device User Guide — 9S12KT256DGV1/D V01.09
$0100 - $010F
Flash Control Register
Address
$0104
Name
Bit 7
Bit 6
RNV6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
FPROT
FPOPEN
FPHDIS
FPHS
FPLDIS
BLANK
FPLS
CCIF
NV6
$0105
$0106
$0107
$0108
$0109
$010A
$010B
$010C
$010D
$010E
FSTAT
FCMD
CBEIF
0
PVIOL ACCERR DFDIF
CMDB
NV7
NV5
NV4
NV3
NV2
NV1
NV0
FCTL2
FADDRHI
FADDRHI
FADDRLO
FDATAHI
FDATALO
FADDRLO
FDATAHI
FDATALO
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$010F
NOTES:
1. Bit only available on MC9S12KT256 and MC9S12KG256.
2. Register only available on MC9S12KT256 and MC9S12KG256.
$0110 - $011B
EEPROM Control Register
Address
$0110
Name
Bit 7
Read: EDIVLD
Write:
Bit 6
PRDIV8
0
Bit 5
EDIV5
0
Bit 4
EDIV4
0
Bit 3
EDIV3
0
Bit 2
EDIV2
0
Bit 1
Bit 0
EDIV0
0
ECLKDIV
EDIV1
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
$0111
$0112
$0113
$0114
$0115
$0116
$0117
$0118
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved for
Factory Test
ECNFG
EPROT
ESTAT
ECMD
CBEIE
CCIE
NV6
NV5
NV4
EPOPEN
EPDIS
0
EP2
EP1
0
EP0
0
CCIF
CBEIF
0
PVIOL ACCERR
0
BLANK
0
0
0
0
0
CMDB6 CMDB5
CMDB2
0
CMDB0
0
0
0
0
0
0
0
0
0
Reserved for
Factory Test
EADDRHI
10
9
Bit 8
Freescale Semiconductor
40
Device User Guide — 9S12KT256DGV1/D V01.09
$0110 - $011B
EEPROM Control Register
Address
$0119
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
EADDRLO
$011A
$011B
EDATAHI
EDATALO
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$011C - $011F
Reserved space
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$011C
- $011F
Reserved
1
$0120 - $013F
ATD1 (Analog to Digital Converter 10 Bit 8 Channel)
Address
$0120
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ATD1CTL0
WRAP2 WRAP1 WRAP0
0
0
0
0
ETRIGSEL
ETRIGCH2 ETRIGCH1 ETRIGCH0
$0121
$0122
$0123
$0124
$0125
$0126
$0127
$0128
$0129
$012A
$012B
$012C
$012D
$012E
$012F
ATD1CTL1
ATD1CTL2
ATD1CTL3
ATD1CTL4
ATD1CTL5
ATD1STAT0
Reserved
ASCIF
ADPU
0
AFFC
S8C
AWAI ETRIGLE ETRIGP ETRIG
ASCIE
FRZ1
PRS1
S4C
S2C
PRS4
MULT
S1C
FIFO
FRZ0
PRS0
SRES8
DJM
SMP1
SMP0
SCAN
PRS3
0
PRS2
DSGN
0
CC
CB
CA
0
CC2
CC1
CC0
SCF
0
ETORF
0
FIFOR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ATD1TEST0
ATD1TEST1
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
SC
0
Read: CCF7
Write:
CCF6
0
CCF5
0
CCF4
0
CCF3
0
CCF2
0
CCF1
0
CCF0
0
ATD1STAT1
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
0
ATD1DIEN
Reserved
IEN7
0
IEN6
0
IEN5
0
IEN4
0
IEN3
0
IEN2
0
IEN1
0
IEN0
0
Read: PTAD7
Write:
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
PORTAD1
Freescale Semiconductor
41
Device User Guide — 9S12KT256DGV1/D V01.09
1
$0120 - $013F
ATD1 (Analog to Digital Converter 10 Bit 8 Channel)
Address
$0130
Name
Bit 7
Read: Bit15
Write:
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit8
ATD1DR0H
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Read: Bit15
Write:
Read:
Write:
Bit7
Bit6
14
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
0
Bit8
0
$0131
$0132
$0133
$0134
$0135
$0136
$0137
$0138
$0139
$013A
$013B
$013C
$013D
$013E
ATD1DR0L
ATD1DR1H
ATD1DR1L
ATD1DR2H
ATD1DR2L
ATD1DR3H
ATD1DR3L
ATD1DR4H
ATD1DR4L
ATD1DR5H
ATD1DR5L
ATD1DR6H
ATD1DR6L
ATD1DR7H
ATD1DR7L
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
14
13
0
12
0
11
0
10
0
Bit8
0
Bit7
Bit6
$013F
NOTES:
1. Registers only available on MC9S12KT256 and MC9S12KG256. Reserved space for MC9S12KG128(64)(32),
MC9S12KL128(64) and MC9S12KC128(64).
$0140 - $017F
CAN0 (Motorola Scalable CAN - MSCAN)
Address
$0140
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN0CTL0
RXFRM
CSWAI
WUPE
SLPRQ INITRQ
SLPAK
BRP1
INITAK
BRP0
$0141
$0142
$0143
$0144
CAN0CTL1
CAN0BTR0
CAN0BTR1
CAN0RFLG
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4
WUPM
BRP2
BRP3
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
Freescale Semiconductor
42
Device User Guide — 9S12KT256DGV1/D V01.09
$0140 - $017F
CAN0 (Motorola Scalable CAN - MSCAN)
Address
$0145
Name
Bit 7
WUPIE
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN0RIER
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
RXFIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$0146
$0147
$0148
$0149
$014A
$014B
$014C
$014D
$014E
$014F
CAN0TFLG
CAN0TIER
CAN0TARQ
CAN0TAAK
CAN0TBSEL
CAN0IDAC
Reserved
TXE2
TXE1
TXE0
0
0
0
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2 ABTAK1 ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
0
0
0
0
0
0
0
0
Reserved
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
CAN0RXERR
CAN0TXERR
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Read:
$0150 - CAN0IDAR0 -
$0153 CAN0IDAR3
$0154 - CAN0IDMR0 -
$0157 CAN0IDMR3
$0158 - CAN0IDAR4 -
$015B CAN0IDAR7
$015C - CAN0IDMR4 -
AC7
AM7
AC7
AM7
AC6
AM6
AC6
AM6
AC5
AM5
AC5
AM5
AC4
AM4
AC4
AM4
AC3
AM3
AC3
AM3
AC2
AM2
AC2
AM2
AC1
AM1
AC1
AM1
AC0
AM0
AC0
AM0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$015F
CAN0IDMR7
FOREGROUND RECEIVE BUFFER see (Table 1-3)
$0160 -
$016F
CAN0RXFG
$0170 -
$017F
CAN0TXFG
FOREGROUND TRANSMIT BUFFER see (Table 1-3)
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
$xxx0
Name
Bit 7
ID28
ID10
Bit 6
ID27
ID9
Bit 5
ID26
ID8
Bit 4
ID25
ID7
Bit 3
ID24
ID6
Bit 2
ID23
ID5
Bit 1
ID22
ID4
Bit 0
ID21
ID3
Extended ID Read:
Standard ID Read:
CANxRIDR0 Write:
Extended ID Read:
Standard ID Read:
CANxRIDR1 Write:
Extended ID Read:
Standard ID Read:
CANxRIDR2 Write:
Extended ID Read:
Standard ID Read:
CANxRIDR3 Write:
ID20
ID2
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID9
ID16
ID8
ID15
ID7
$xxx1
$xxx2
$xxx3
ID14
ID6
ID13
ID5
ID12
ID4
ID11
ID3
ID10
ID2
ID1
ID0
RTR
Freescale Semiconductor
43
Device User Guide — 9S12KT256DGV1/D V01.09
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
Name
Bit 7
DB7
Bit 6
DB6
Bit 5
DB5
Bit 4
DB4
Bit 3
DB3
Bit 2
DB2
Bit 1
DB1
Bit 0
DB0
Read:
Write:
Read:
Write:
Read:
Write:
$xxx4- CANxRDSR0 -
$xxxB
$xxxC
CANxRDSR7
CANRxDLR
DLC3
DLC2
DLC1
DLC0
$xxxD
$xxxE
$xxxF
Reserved
Read: TSR15
Write:
Read: TSR7
Write:
TSR14
TSR6
TSR13
TSR5
TSR12
TSR4
TSR11
TSR3
TSR10
TSR2
TSR9
TSR1
TSR8
TSR0
CANxRTSRH
CANxRTSRL
Extended ID Read:
CANxTIDR0 Write:
Standard ID Read:
Write:
Extended ID Read:
CANxTIDR1 Write:
Standard ID Read:
Write:
Extended ID Read:
CANxTIDR2 Write:
Standard ID Read:
Write:
Extended ID Read:
CANxTIDR3 Write:
Standard ID Read:
Write:
ID28
ID10
ID20
ID2
ID27
ID9
ID26
ID8
ID25
ID7
ID24
ID6
ID23
ID5
ID22
ID4
ID21
ID3
$xx10
$xx10
$xx12
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID10
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID9
ID1
ID8
ID0
ID7
ID6
DB7
ID5
ID4
ID3
ID2
RTR
$xx13
Read:
Write:
Read:
Write:
Read:
Write:
Read: TSR15
Write:
Read: TSR7
Write:
$xx14- CANxTDSR0 -
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$xx1B
CANxTDSR7
$xx1C
CANxTDLR
DLC3
DLC2
DLC1
DLC0
$xx1D
$xx1E
$xx1F
CONxTTBPR
CANxTTSRH
CANxTTSRL
PRIO7
PRIO6
TSR14
PRIO5
TSR13
PRIO4
TSR12
PRIO3
TSR11
PRIO2
TSR10
PRIO1
TSR9
PRIO0
TSR8
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
1
$0180 - $01BF
CAN1 (Motorola Scalable CAN - MSCAN)
Address
$0180
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN1CTL0
RXFRM
CSWAI
WUPE
SLPRQ INITRQ
SLPAK
BRP1
INITAK
BRP0
$0181
$0182
$0183
CAN1CTL1
CAN1BTR0
CAN1BTR1
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4
WUPM
BRP2
BRP3
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Freescale Semiconductor
44
Device User Guide — 9S12KT256DGV1/D V01.09
1
$0180 - $01BF
CAN1 (Motorola Scalable CAN - MSCAN)
Address
$0184
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXF
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
RSTAT1 RSTAT0 TSTAT1 TSTAT0
CAN1RFLG
WUPIF
CSCIF
OVRIF
$0185
$0186
$0187
$0188
$0189
$018A
$018B
$018C
$018D
$018E
$018F
$0190
$0191
$0192
$0193
$0194
$0195
$0196
$0197
$0198
$0199
$019A
$019B
$019C
CAN1RIER
CAN1TFLG
CAN1TIER
WUPIE
0
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
RXFIE
TXE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE2
TXE1
0
0
0
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
CAN1TARQ
CAN1TAAK
CAN1TBSEL
CAN1IDAC
Reserved
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2 ABTAK1 ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
0
0
0
0
0
0
0
0
Reserved
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
CAN1RXERR
CAN1TXERR
CAN1IDAR0
CAN1IDAR1
CAN1IDAR2
CAN1IDAR3
CAN1IDMR0
CAN1IDMR1
CAN1IDMR2
CAN1IDMR3
CAN1IDAR4
CAN1IDAR5
CAN1IDAR6
CAN1IDAR7
CAN1IDMR4
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Read:
AC7
AC7
AC7
AC7
AM7
AM7
AM7
AM7
AC7
AC7
AC7
AC7
AM7
AC6
AC6
AC6
AC6
AM6
AM6
AM6
AM6
AC6
AC6
AC6
AC6
AM6
AC5
AC5
AC5
AC5
AM5
AM5
AM5
AM5
AC5
AC5
AC5
AC5
AM5
AC4
AC4
AC4
AC4
AM4
AM4
AM4
AM4
AC4
AC4
AC4
AC4
AM4
AC3
AC3
AC3
AC3
AM3
AM3
AM3
AM3
AC3
AC3
AC3
AC3
AM3
AC2
AC2
AC2
AC2
AM2
AM2
AM2
AM2
AC2
AC2
AC2
AC2
AM2
AC1
AC1
AC1
AC1
AM1
AM1
AM1
AM1
AC1
AC1
AC1
AC1
AM1
AC0
AC0
AC0
AC0
AM0
AM0
AM0
AM0
AC0
AC0
AC0
AC0
AM0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Freescale Semiconductor
45
Device User Guide — 9S12KT256DGV1/D V01.09
1
$0180 - $01BF
CAN1 (Motorola Scalable CAN - MSCAN)
Address
$019D
Name
Bit 7
AM7
Bit 6
AM6
Bit 5
AM5
Bit 4
AM4
Bit 3
AM3
Bit 2
AM2
Bit 1
AM1
Bit 0
AM0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN1IDMR5
$019E
$019F
CAN1IDMR6
CAN1IDMR7
CAN1RXFG
CAN1TXFG
AM7
AM7
AM6
AM6
AM5
AM5
AM4
AM4
AM3
AM3
AM2
AM2
AM1
AM1
AM0
AM0
FOREGROUND RECEIVE BUFFER see (Table 1-3)
$01A0 -
$01AF
$01B0 -
$01BF
FOREGROUND TRANSMIT BUFFER see (Table 1-3)
NOTES:
1. Registers only available on MC9S12KT256. Reserved space for MC9S12KG256(128)(64)(32), MC9S12KL128(64)
and MC9S12KC128(64).
$01C0 - $023F
Reserved space
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$01C0
- $023F
Reserved
$0240 - $027F
PIM (Port Integration Module)
Address
$0240
Name
PTT
Bit 7
Bit 6
PTT6
PTIT6
Bit 5
PTT5
PTIT5
Bit 4
PTT4
PTIT4
Bit 3
PTT3
PTIT3
Bit 2
PTT2
PTIT2
Bit 1
PTT1
PTIT1
Bit 0
PTT0
PTIT0
Read:
Write:
PTT7
Read: PTIT7
Write:
$0241
$0242
$0243
$0244
$0245
$0246
$0247
$0248
$0249
$024A
$024B
PTIT
DDRT
RDRT
PERT
Read:
DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
PPST
PPST7
0
PPST6
0
PPST5
0
PPST4
0
PPST3
0
PPST2
0
PPST1
0
PPST0
0
Reserved
Reserved
PTS
0
0
0
0
0
0
0
0
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
Read: PTIS7
Write:
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
PTIS
Read:
DDRS
RDRS
DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
Write:
Read:
Write:
Freescale Semiconductor
46
Device User Guide — 9S12KT256DGV1/D V01.09
$0240 - $027F
PIM (Port Integration Module)
Address
$024C
Name
PERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERS7
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0
$024D
$024E
$024F
$0250
$0251
$0252
$0253
$0254
$0255
$0256
$0257
$0258
$0259
$025A
$025B
$025C
$025D
$025E
$025F
$0260
$0261
$0262
$0263
$0264
PPSS
WOMS
Reserved
PTM
PPSS7
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
0
0
0
0
0
0
0
0
PTM7
PTM6
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
Read: PTIM7
Write:
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
PTIM
Read:
DDRM
RDRM
PERM
PPSM
WOMM
MODRR
PTP
DDRM7 DDRM7 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
Read: PTIP7
Write:
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
PTIP
Read:
DDRP
RDRP
PERP
PPSP
PIEP
DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERP7
PPSP7
PIEP7
PIFP7
PTH7
PERP6
PPSP6
PIEP6
PIFP6
PERP5
PPSP5
PIEP5
PIFP5
PERP4
PPSP4
PIEP4
PIFP4
PERP3
PPSP3
PIEP3
PIFP3
PERP2
PPSP2
PIEP2
PIFP2
PERP1
PPSP1
PIEP1
PIFP1
PERP0
PPSS0
PIEP0
PIFP0
PIFP
PTH
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
Read: PTIH7
Write:
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
PTIH
Read:
DDRH
RDRH
PERH
DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
Write:
Read:
Write:
Read:
Write:
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
$0240 - $027F
PIM (Port Integration Module)
Address
$0265
Name
PPSH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PPSH7
PPSH6
PPSH5
PPSH4
PPSH3
PPSH2
PPSH1
PPSH0
$0266
$0267
$0268
$0269
$026A
$026B
$026C
$026D
$026E
$026F
PIEH
PIFH
PIEH7
PIFH7
PTJ7
PIEH6
PIFH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIFH1
PIEH0
PIFH0
PIFH5
0
PIFH4
0
PIFH3
0
PIFH2
0
PTJ
PTJ6
PTJ1
PTJ0
Read: PTIJ7
Write:
Read:
DDRJ7
Write:
Read:
RDRJ7
Write:
Read:
PERJ7
Write:
Read:
PPSJ7
Write:
Read:
PIEJ7
Write:
Read:
PIFJ7
Write:
PTIJ6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTIJ1
PTIJ0
PTIJ
DDRJ
RDRJ
PERJ
PPSJ
PIEJ
DDRJ7
RDRJ6
PERJ6
PPSJ6
PIEJ6
DDRJ1
RDRJ1
PERJ1
PPSJ1
PIEJ1
DDRJ0
RDRJ0
PERJ0
PPSJ0
PIEJ0
PIFJ
PIFJ6
PIFJ1
PIFJ0
$0270 -
$027F
Reserved
Read:
$0280 - $02BF
CAN4 (Motorola Scalable CAN - MSCAN)
Address
$0280
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN4CTL0
RXFRM
CSWAI
WUPE
SLPRQ INITRQ
SLPAK
INITAK
$0281
$0282
$0283
$0284
$0285
$0286
$0287
$0288
$0289
$028A
CAN4CTL1
CAN4BTR0
CAN4BTR1
CAN4RFLG
CAN4RIER
CAN4TFLG
CAN4TIER
CAN4TARQ
CAN4TAAK
CAN4TBSEL
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4
WUPM
BRP2
BRP3
BRP1
BRP0
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
RXFIE
TXE0
WUPIE
0
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE2
TXE1
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2 ABTAK1 ABTAK0
TX2
TX1
TX0
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
$0280 - $02BF
CAN4 (Motorola Scalable CAN - MSCAN)
Address
$028B
Name
Bit 7
0
Bit 6
0
Bit 5
IDAM1
0
Bit 4
IDAM0
0
Bit 3
0
Bit 2
IDHIT2
Bit 1
IDHIT1
Bit 0
IDHIT0
Read:
Write:
Read:
Write:
Read:
Write:
CAN4IDAC
0
0
0
0
0
0
0
0
0
0
0
0
$028C
$028D
$028E
$028F
$0290
$0291
$0292
$0293
$0294
$0295
$0296
$0297
$0298
$0299
$029A
$029B
$029C
$029D
$029E
$029F
Reserved
Reserved
0
0
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
CAN4RXERR
CAN4TXERR
CAN4IDAR0
CAN4IDAR1
CAN4IDAR2
CAN4IDAR3
CAN4IDMR0
CAN4IDMR1
CAN4IDMR2
CAN4IDMR3
CAN4IDAR4
CAN4IDAR5
CAN4IDAR6
CAN4IDAR7
CAN4IDMR4
CAN4IDMR5
CAN4IDMR6
CAN4IDMR7
CAN4RXFG
CAN4TXFG
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Read:
AC7
AC7
AC7
AC7
AM7
AM7
AM7
AM7
AC7
AC7
AC7
AC7
AM7
AM7
AM7
AM7
AC6
AC6
AC6
AC6
AM6
AM6
AM6
AM6
AC6
AC6
AC6
AC6
AM6
AM6
AM6
AM6
AC5
AC5
AC5
AC5
AM5
AM5
AM5
AM5
AC5
AC5
AC5
AC5
AM5
AM5
AM5
AM5
AC4
AC4
AC4
AC4
AM4
AM4
AM4
AM4
AC4
AC4
AC4
AC4
AM4
AM4
AM4
AM4
AC3
AC3
AC3
AC3
AM3
AM3
AM3
AM3
AC3
AC3
AC3
AC3
AM3
AM3
AM3
AM3
AC2
AC2
AC2
AC2
AM2
AM2
AM2
AM2
AC2
AC2
AC2
AC2
AM2
AM2
AM2
AM2
AC1
AC1
AC1
AC1
AM1
AM1
AM1
AM1
AC1
AC1
AC1
AC1
AM1
AM1
AM1
AM1
AC0
AC0
AC0
AC0
AM0
AM0
AM0
AM0
AC0
AC0
AC0
AC0
AM0
AM0
AM0
AM0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
FOREGROUND RECEIVE BUFFER see (Table 1-3)
$02A0 -
$02AF
$02B0 -
$02BF
FOREGROUND TRANSMIT BUFFER see (Table 1-3)
Freescale Semiconductor
49
Device User Guide — 9S12KT256DGV1/D V01.09
$02C0 - $02E7
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Address
$02C0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PWME
PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
$02C1
$02C2
$02C3
$02C4
$02C5
$02C6
$02C7
$02C8
$02C9
$02CA
$02CB
$02CC
$02CD
$02CE
$02CF
$02D0
$02D1
$02D2
$02D3
$02D4
$02D5
$02D6
$02D7
$02D8
PWMPOL
PWMCLK
PWMPRCLK
PWMCAE
PWMCTL
PPOL7
PPOL6
PCLK6
PCKB2
CAE6
PPOL5
PCLK5
PCKB1
CAE5
PPOL4
PCLK4
PCKB0
CAE4
PPOL3
PPOL2
PCLK2
PCKA2
CAE2
PPOL1
PCLK1
PCKA1
PPOL0
PCLK0
PCKA0
PCLK7
0
PCLK3
0
CAE7
CAE3
CAE1
0
CAE0
0
CON67 CON45 CON23 CON01
PSWAI
0
PFRZ
0
0
0
0
0
0
0
0
0
0
0
0
0
PWMTST
Test Only
0
3
0
2
PWMPRSC
PWMSCLA
PWMSCLB
PWMSCNTA
PWMSCNTB
PWMCNT0
PWMCNT1
PWMCNT2
PWMCNT3
PWMCNT4
PWMCNT5
PWMCNT6
PWMCNT7
PWMPER0
PWMPER1
PWMPER2
PWMPER3
PWMPER4
Bit 7
6
5
4
1
Bit 0
Bit 7
0
6
5
4
3
0
2
0
1
0
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
6
5
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
6
6
6
6
5
5
5
5
4
4
4
4
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
$02C0 - $02E7
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Address
$02D9
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PWMPER5
$02DA
$02DB
$02DC
$02DD
$02DE
$02DF
$02E0
$02E1
$02E2
$02E3
$02E4
$02E5
$02E6
$02E7
PWMPER6
PWMPER7
PWMDTY0
PWMDTY1
PWMDTY2
PWMDTY3
PWMDTY4
PWMDTY5
PWMDTY6
PWMDTY7
PWMSDN
Reserved
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
3
0
PWMRS
TRT
PWM7IN PWM7E
PWMIF PWMIE
PWMLVL
0
PWM7IN
0
L
NA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
$02E8 - $03FF
Reserved space
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$02E8
- $03FF
Reserved
1.8 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
reset. The read-only value is a unique part ID for each revision of the chip. Table 1-4 Assigned Part
ID Numbers shows the assigned part ID number.
Freescale Semiconductor
51
Device User Guide — 9S12KT256DGV1/D V01.09
Table 1-4 Assigned Part ID Numbers
1
Device
Mask Set Number
0L33V
Part ID
$7000
$7100
MC9S12KT256
MC9S12KG128
0L74N
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-5 shows the read-only values of these registers. Refer to HCS12 Module
Mapping and Control (MMC) Block Guide for further details.
Table 1-5 Memory size registers
Device
Register name
MEMSIZ0
Value
$25
MC9S12KT256
MC9S12KT256
MC9S12KG128
MC9S12KG128
MEMSIZ1
$81
MEMSIZ0
$13
MEMSIZ1
$80
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Section 2 Signal Description
2.1 Device Pinout
The MC9S12K-Family and its derivatives are available in a 112-pin low profile quad flat pack (LQFP), a
100-pin low profile quad flat pack (LQFP), and a 80-pin quad flat pack (QFP). Most pins perform two or
more functions, as described in the Signal Descriptions. Figure 2-1, Figure 2-2 and Figure 2-3 show
the pin assignments for different packages.
Freescale Semiconductor
53
Device User Guide — 9S12KT256DGV1/D V01.09
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
XADDR17/PK3
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
1
2
3
4
5
6
7
8
VRH
VDDA
PAD15/AN15
PAD07/AN07
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
9
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MC9S12K-Family
112LQFP
IOC6/PT6
IOC7/PT7
XADDR19/PK5
XADDR18/PK4
KWJ1/PJ1
KWJ0/PJ0
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Signals shown in Bold are not available on the 80 Pin Package
Signals shown in Italic are only available in MC9S12KT256
Figure 2-1 Pin assignments for 112 LQFP
Freescale Semiconductor
54
Device User Guide — 9S12KT256DGV1/D V01.09
75
74
73
72
71
70
69
68
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
1
2
3
4
5
6
7
8
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
67
IOC1/PT1
9
PAD03/AN03
66
65
64
63
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
KWJ1/PJ1
KWJ0/PJ0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
MC9S12K-Family
100LQFP
62
61
60
59
58
57
56
55
54
53
52
51
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Signals shown in Bold are not available on the 80 Pin Package
Signals shown in Italic are only available in MC9S12KT256
Figure 2-2 Pin assignments for 100 LQFP
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PWM3/KWP3/PP3
PWM2/KWP2/PP2
PWM1/KWP1/PP1
PWM0/KWP0/PP0
IOC0/PT0
1
2
3
4
5
6
7
8
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
MC9S12K-Family
80 QFP
9
10
11
12
13
14
15
16
17
18
19
20
IOC6/PT6
IOC7/PT7
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Signals shown in Italic are only available in MC9S12KT256
Figure 2-3 Pin assignments for 80 QFP
Freescale Semiconductor
56
Device User Guide — 9S12KT256DGV1/D V01.09
2.2 Signal Properties Summary
(Table 2-1) summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
package. (Table 2-2) summarizes the power and ground pins.
Table 2-1 Signal Properties
Internal Pull
Resistor
Pin Name
Pin Name
Pin Name Pin Name Powered
Description
Function 1 Function 2 Function 3 Function 4
by
Reset
CTRL
State
EXTAL
XTAL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDPLL
VDDPLL
VDDR
NA
NA
NA
NA
Oscillator Pins
NA
RESET
TEST
None
NA
None
NA
External Reset
Test Input
VREGEN
XFC
VDDX
NA
NA
Voltage Regulator Enable Input
PLL Loop Filter
VDDPLL
NA
NA
Always
Up
Background Debug, Tag High, Mode
Input
BKGD
TAGHI
MODC
—
VDDR
Up
Port AD Input, Analog Inputs of ATD
in MC9S12KG128(64)(32),
MC9S12KL128(64) and
MC9S12KC128(64); Analog Inputs of
ATD1 in MC9S12KT256 and
MC9S12KG256
AN1[7:0]1
PAD[15:8]
AN[15:8]
—
VDDA
None
None
Port AD Input, Analog Inputs of ATD in
MC9S12KG128(64)(32),
MC9S12KL128(64) and
AN0[7:0]1
PAD[7:0]
PA[7:0]
AN[7:0]
—
—
VDDA
VDDR
None
None
MC9S12KC128(64); Analog Inputs of
ATD0 in MC9S12KT256 and
MC9S12KG256
ADDR[15:8]/
DATA[15:8]
—
PUCR Disabled Port A I/O, Multiplexed Address/Data
PUCR Disabled Port B I/O, Multiplexed Address/Data
ADDR[7:0]/
DATA[7:0]
PB[7:0]
PE7
—
—
—
VDDR
VDDR
NOACC
XCLKS
PUCR
Up
Port E I/O, Access, Clock Select
Port E I/O, Pipe Status, Mode Input
While RESET
pin is low:
PE6
PE5
IPIPE1
MODB
MODA
—
—
VDDR
VDDR
Down
While RESET
pin is low:
IPIPE0
Port E I/O, Pipe Status, Mode Input
Down
PE4
PE3
PE2
PE1
PE0
ECLK
LSTRB
R/W
—
TAGLO
—
—
—
—
—
—
VDDR
VDDR
VDDR
VDDR
VDDR
PUCR
Up
Up
Up
Port E I/O, Bus Clock Output
PUCR
PUCR
Port E I/O, Byte Strobe, Tag Low
Port E I/O, R/W in expanded modes
Port E Input, Maskable Interrupt
Port E Input, Non Maskable Interrupt
IRQ
—
Always Up
XIRQ
—
PERH/
PPSH
PH7
KWH7
SS2
—
VDDR
Disabled Port H I/O, Interrupt, SS of SPI2
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Internal Pull
Resistor
Pin Name
Pin Name
Pin Name Pin Name Powered
Description
Function 1 Function 2 Function 3 Function 4
by
Reset
CTRL
State
PERH/ Disabled
PPSH
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PJ7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
KWJ7
SCK2
MOSI2
MISO2
SS1
—
—
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDX
VDDX
VDDX
Port H I/O, Interrupt, SCK of SPI2
Port H I/O, Interrupt, MOSI of SPI2
Port H I/O, Interrupt, MISO of SPI2
Port H I/O, Interrupt, SS of SPI1
Port H I/O, Interrupt, SCK of SPI1
Port H I/O, Interrupt, MOSI of SPI1
Port H I/O, Interrupt, MISO of SPI1
PERH/ Disabled
PPSH
PERH/ Disabled
PPSH
—
PERH/ Disabled
PPSH
—
PERH/ Disabled
PPSH
SCK1
—
PERH/ Disabled
PPSH
MOSI1
MISO1
TXCAN4
RXCAN4
—
—
PERH/ Disabled
PPSH
—
PERJ/
Up
Port J I/O, Interrupt, TX of CAN4,
SCL of IIC
SCL
SDA
—
PPSJ
PERJ/
Up
Port J I/O, Interrupt, RX of CAN4,
SDA of IIC
PJ6
KWJ6
PPSJ
PERJ/
Up
PJ[1:0]
KWJ[1:0]
Port J I/O, Interrupts
PPSJ
Port K I/O, Emulation Chip Select,
ROM On Enable
PK7
PK[5:0]
PM7
ECS
ROMCTL
—
—
—
VDDX
VDDX
VDDX
PUCR
PUCR
Up
Up
XADDR[19:14]
TXCAN4
—
—
Port K I/O, Extended Addresses
PERM/
PPSM
Disabled Port M I/O, CAN4 TX
Disabled Port M I/O, CAN4 RX
PERM/
PPSM
PM6
PM5
PM4
PM3
PM2
PM1
PM0
PP7
PP6
PP5
PP4
RXCAN4
TXCAN0
RXCAN0
—
—
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
PERM/
PPSM
Port M I/O, CAN0 TX, CAN4 TX,
SPI0 SCK
TXCAN4
RXCAN4
TXCAN0
RXCAN0
—
SCK0
MOSI0
SS0
Disabled
Disabled
Disabled
Disabled
PERM/
PPSM
Port M I/O, CAN0 RX, CAN4 RX,
SPI0 MOSI
PERM/
PPSM
Port M I/O, CAN1 TX, CAN0 TX, SPI0
SS
TXCAN11
RXCAN11
TXCAN0
RXCAN0
KWP7
PERM/
PPSM
Port M I/O, CAN1 RX, CAN0 RX, SPI0
MISO
MISO0
—
PERM/
PPSM
Disabled Port M I/O, CAN0 TX
Disabled Port M I/O, CAN0 RX
PERM/
PPSM
—
—
PERP/
PPSP
Port P I/O, Interrupt, PWM Channel 7,
SCK of SPI2
PWM7
PWM6
PWM5
PWM4
SCK2
SS2
Disabled
Disabled
Disabled
Disabled
PERP/
PPSP
Port P I/O, Interrupt, PWM Channel 6,
SPI2 SS
KWP6
PERP/
PPSP
Port P I/O, Interrupt, PWM Channel 5,
SPI2 MOSI
KWP5
MOSI2
MISO2
PERP/
PPSP
Port P I/O, Interrupt, PWM Channel 4,
SPI2 MISO
KWP4
Freescale Semiconductor
58
Device User Guide — 9S12KT256DGV1/D V01.09
Internal Pull
Resistor
Pin Name
Pin Name
Pin Name Pin Name Powered
Description
Function 1 Function 2 Function 3 Function 4
by
Reset
CTRL
State
PERP/
PPSP
Port P I/O, Interrupt, PWM Channel 3,
SPI1 SS
PP3
PP2
PP1
PP0
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
KWP3
KWP2
KWP1
KWP0
SS0
PWM3
PWM2
PWM1
PWM0
—
SS1
SCK1
MOSI1
MISO1
—
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
Disabled
Disabled
Disabled
Disabled
Up
PERP/
PPSP
Port P I/O, Interrupt, PWM Channel 2,
SPI1 SCK
PERP/
PPSP
Port P I/O, Interrupt, PWM Channel 1,
SPI1 MOSI
PERP/
PPSP
Port P I/O, Interrupt, PWM Channel 0,
SPI1 MISO
PERS/
PPSS
Port S I/O, SPI0 SS
Port S I/O, SPI0 SCK
Port S I/O, SPI0 MOSI
Port S I/O, SPI0 MISO
Port S I/O, SCI1TXD
Port S I/O, SCI1RXD
Port S I/O, SCI0 TXD
Port S I/O, SCI0 RXD
PERS/
PPSS
SCK0
MOSI0
MISO0
TXD1
—
—
Up
PERS/
PPSS
—
—
Up
PERS/
PPSS
—
—
Up
PERS/
PPSS
—
—
Up
PERS/
PPSS
RXD1
TXD0
—
—
Up
PERS/
PPSS
—
—
Up
PERS/
PPSS
RXD0
IOC[7:0]
—
—
Up
Up or
Down
PT[7:0]
—
—
Disabled Port T I/O, Timer channels
NOTES:
1. Only available on MC9S12KT256.
Table 2-2 Power and Ground
Nominal
Voltage
Mnemonic
Description
VDD1
VDD2
2.5 V
Internal power and ground generated by internal regulator. These also
allow an external source to supply the core VDD/VSS voltages and
bypass the internal voltage regulator.
VSS1
VSS2
0V
VDDR
VSSR
VDDX
VSSX
VDDA
3.3/5.0 V
0 V
External power and ground, supply to pin drivers and internal voltage
regulator.
3.3/5.0 V
0 V
External power and ground, supply to pin drivers.
3.3/5.0 V Operating voltage and ground for the analog-to-digital converter and
the reference for the internal voltage regulator, allows the supply
VSSA
0 V
voltage to the A/D to be bypassed independently.
VRH
VRL
3.3/5.0 V Reference voltage high for the ATD converter.
0 V
Reference voltage low for the ATD converter.
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Nominal
Mnemonic
Description
Voltage
VDDPLL
VSSPLL
2.5 V
Provides operating voltage and ground for the Phased-Locked Loop.
This allows the supply voltage to the PLL to be bypassed
independently. Internal power and ground generated by internal
regulator.
0 V
NOTE: All VSS pins must be connected together in the application. Because fast signal
transitions place high, short-duration current demands on the power supply, use
bypass capacitors with high-frequency characteristics and place them as close to
the MCU as possible. Bypass requirements depend on MCU pin load.
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE: The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
2.3.5 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC
R
C
P
MCU
C
S
VDDPLL
VDDPLL
Figure 2-4 PLL Loop Filter Connections
2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
2.3.7 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]
PAD15 - PAD8 are general purpose input pins and analog inputs of the single analog to digital converter
with 16 channels on MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). PAD15 -
PAD8 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels
(ATD1) on MC9S12KT256 and MC9S12KG256.
2.3.8 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]
PAD7 - PAD0 are general purpose input pins and analog inputs of the single analog to digital converter
with 16 channels on MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). PAD7 -
PAD0 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels
(ATD0) on MC9S12KT256 and MC9S12KG256.
2.3.9 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
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2.3.10 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.11 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Loop
Controlled Pierce (low power) oscillator is used or whether Full Swing Pierce oscillator/external clock
circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the
EXTAL pin is configured for an external clock drive or Full Swing Pierce Oscillator. If input is a logic
high a Loop Controlled Pierce oscillator circuit is configured on EXTAL and XTAL. Since this pin is an
input with a pull-up device during reset, if the pin is left floating, the default configuration is a Loop
Controlled Pierce oscillator circuit on EXTAL and XTAL.
Table 2-3 Clock selection based on PE7 during reset
PE7
Description
1
0
Loop Controlled Pierce Oscillator selected
Full Swing Pierce Oscillator or external clock selected
EXTAL
C
7
MCU
Crystal or
ceramic resonator
XTAL
C
8
VSSPLL
Figure 2-5 Loop Controlled Pierce Oscillator Connections (PE7=1)
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EXTAL
C
7
MCU
RB
Crystal or
ceramic resonator
*
RS
XTAL
C
8
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
Figure 2-6 Full Swing Pierce Oscillator Connections (PE7=0)
EXTAL
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
(VDDPLL-Level)
MCU
XTAL
not connected
Figure 2-7 External Clock Connections (PE7=0)
2.3.12 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1.
2.3.13 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0.
2.3.14 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
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2.3.15 PE3 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used
for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on,
TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
2.3.16 PE2 / R/W — Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.17 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.18 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.19 PH7 / KWH7 / SS2 — Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface
2 (SPI2).
2.3.20 PH6 / KWH6 / SCK2 — Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
2 (SPI2).
2.3.21 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
2.3.22 PH4 / KWH4 / MISO2 — Port H I/O Pin 2
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
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2.3.23 PH3 / KWH3 / SS1 — Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface
1 (SPI1).
2.3.24 PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
1 (SPI1).
2.3.25 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.26 PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.27 PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable
Controller Area Network controller 4 (CAN4) or the serial clock pin SCL of the IIC module.
2.3.28 PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable
Controller Area Network controller 4 (CAN4) or the serial data pin SDA of the IIC module.
2.3.29 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt
causing the MCU to exit STOP or WAIT mode.
2.3.30 PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used
as the emulation chip select output (ECS). During MCU expanded modes of operation, this pin is used to
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enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit.For all other modes the reset state of the ROMON bit is as
follows:
special single : ROMCTL = 1
normal single : ROMCTL = 1
emulation expanded wide : ROMCTL = 0
emulation expanded narrow : ROMCTL = 0
special test : ROMCTL = 0
peripheral test : ROMCTL = 1
2.3.31 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address XADDR[19:14] for the external bus.
2.3.32 PM7 / TXCAN4 — Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 4 (CAN4).
2.3.33 PM6 / RXCAN4 — Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 4 (CAN4).
2.3.34 PM5 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as
the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.35 PM4 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as
the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial
Peripheral Interface 0 (SPI0).
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2.3.36 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as
the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.37 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as
the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial
Peripheral Interface 0 (SPI0).
2.3.38 PM1 / TXCAN0 — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0).
2.3.39 PM0 / RXCAN0 — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0).
2.3.40 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
2.3.41 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
2.3.42 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 2 (SPI2).
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2.3.43 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 2 (SPI2).
2.3.44 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
2.3.45 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.46 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 1 (SPI1).
2.3.47 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 1 (SPI1).
2.3.48 PS7 / SS0 — Port S I/O Pin 7
PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).
2.3.49 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
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2.3.50 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.51 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.52 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).
2.3.53 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
2.3.54 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
2.3.55 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
2.3.56 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Timer (TIM).
2.4 Power Supply Pins
MC9S12K-Family power and ground pins are described below.
NOTE: All VSS pins must be connected together in the application.
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2.4.1 VDDX,VSSX — Power Supply Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
2.4.2 VDDR, VSSR — Power Supply Pins for I/O Drivers & for Internal Voltage
Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
2.4.3 VDD1, VDD2, VSS1, VSS2 — Power Supply Pins for Internal Logic
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.
NOTE: No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converter. It also provides the reference for the internal voltage regulator. This allows the supply
voltage to the ATD and the reference voltage to be bypassed independently.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by
the internal voltage regulator.
NOTE: No load allowed except for bypass capacitors.
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Section 3 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block Guide for
details on clock generation.
HCS12 CORE
BDM
CPU
Core Clock
MEBI
INT
MMC
DBG
Flash
RAM
EEPROM
TIM
ATD
PWM
EXTAL
XTAL
Bus Clock
OSC
CRG
SCI0, SCI1
Oscillator Clock
SPI0, SPI1, SPI2
CAN0, CAN1, CAN4
IIC
PIM
Figure 3-1 Clock Connections
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12K-Family. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
4.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset ((Table 4-1)). The MODC, MODB, and MODA bits in the MODE register show the current
operating mode and provide limited mode switching during operation. The states of the MODC, MODB,
and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal
allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is
visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the
ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
Table 4-1 Mode Selection
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
ROMON
Bit
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
0
0
0
X
1
0
1
1
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
X
0
0
1
1
0
X
1
0
1
0
1
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
1
1
1
1
0
1
X
1
0
1
0
1
Normal Expanded Wide, BDM allowed
For further explanation on the modes refer to the HCS12 MEBI Block Guide.
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Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
Description
1
0
Loop Controlled Pierce Oscillator selected
Full Swing Pierce Oscillator or external clock selected
Table 4-3 Voltage Regulator VREGEN
VREGEN
Description
1
Internal Voltage Regulator enabled
Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V
0
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•
•
•
•
Protection of the contents of FLASH,
Protection of the contents of EEPROM,
Operation in single-chip mode,
Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block Guide for more details on the security configuration.
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4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator Guide (CRG).
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
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4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. Both local masking and CCR masking are included as listed in Table 5-1. System resets can
be generated through external control of the RESET pin, through the clock and reset generator module
CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG
and VREG Block Guides for detailed information on reset generation.
5.2 Vectors
5.2.1 Vector Table
(Table 5-1) lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
CCR
Mask
HPRIO Value
to Elevate
Vector Address
Interrupt Source
Local Enable
External Reset, Power On Reset or Low
$FFFE, $FFFF
Voltage Reset (see CRG Flags Register None
to determine reset source)
None
–
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
Clock Monitor fail reset
COP failure reset
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
PLLCTL (CME, FCME)
COP rate select
None
–
–
Unimplemented instruction trap
SWI
–
None
–
XIRQ
None
–
IRQ
IRQCR (IRQEN)
CRGINT (RTIE)
TIE (C0I)
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
Real Time Interrupt
Standard Timer channel 0
Standard Timer channel 1
Standard Timer channel 2
Standard Timer channel 3
Standard Timer channel 4
Standard Timer channel 5
Standard Timer channel 6
Standard Timer channel 7
Standard Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI0
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
TSCR2 (TOI)
PACTL (PAOVI)
PACTL (PAI)
SPICR1 (SPIE, SPTIE)
SCICR2
(TIE, TCIE, RIE, ILIE)
$FFD6, $FFD7
SCI0
I-Bit
$D6
SCICR2
(TIE, TCIE, RIE, ILIE)
$FFD4, $FFD5
$FFD2, $FFD3
SCI1
ATD0
I-Bit
I-Bit
$D4
$D2
ATDCTL2 (ASCIE)
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ATDCTL2 (ASCIE)1
$FFD0, $FFD1
$FFCE, $FFCF
ATD1
Port J
Port H
I-Bit
I-Bit
$D0
$CE
PIEJ
(PIEJ7, PIEJ6, PIEJ1, PIEJ0)
$FFCC, $FFCD
$FFCA, $FFCB
$FFC8, $FFC9
$FFC6, $FFC7
$FFC4, $FFC5
$FFC2, $FFC3
$FFC0, $FFC1
$FFBE, $FFBF
$FFBC, $FFBD
$FFBA, $FFBB
$FFB8, $FFB9
$FFB6, $FFB7
$FFB4, $FFB5
$FFB2, $FFB3
$FFB0, $FFB1
$FFAE, $FFAF
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
PIEH (PIEH7-0)
$CC
$CA
$C8
$C6
$C4
$C2
$C0
$BE
$BC
$BA
$B8
$B6
$B4
$B2
$B0
$AE
Reserved
Reserved
CRG PLL lock
CRG Self Clock Mode
FLASH Double Fault Detect
IIC Bus
CRGINT (LOCKIE)
CRGINT (SCMIE)
FCNFG (DFDIE)
IBCR (IBIE)
SPI1
SPICR1 (SPIE, SPTIE)
SPICR1 (SPIE, SPTIE)
ECNFG (CCIE, CBEIE)
FCNFG (CCIE, CBEIE)
CAN0RIER (WUPIE)
CAN0RIER (CSCIE, OVRIE)
CAN0RIER (RXFIE)
SPI2
EEPROM command
FLASH command
CAN0 wake-up
CAN0 errors
CAN0 receive
CAN0 transmit
CAN1 wake-up
I-Bit CAN0TIER (TXEIE2 - TXEIE0)
CAN1RIER (WUPIE)1
I-Bit
CAN1RIER (CSCIE, OVRIE)1
I-Bit
$FFAC, $FFAD
$FFAA, $FFAB
CAN1 errors
CAN1 receive
CAN1 transmit
$AC
$AA
CAN1RIER (RXFIE)1
I-Bit
CAN1TIER (TXEIE2 - TXEIE0)1
I-Bit
$FFA8, $FFA9
$FFA6, $FFA7
$FFA4, $FFA5
$FFA2, $FFA3
$FFA0, $FFA1
$FF9E, $FF9F
$FF9C, $FF9D
$FF9A, $FF9B
$FF98, $FF99
$FF96, $FF97
$FF94, $FF95
$FF92, $FF93
$FF90, $FF91
$FF8E, $FF8F
$FF8C, $FF8D
$FF8A, $FF8B
$FF80 to $FF89
$A8
$A6
$A4
$A2
$A0
$9E
$9C
$9A
$98
$96
$94
$92
$90
$8E
$8C
$8A
I-Bit
I-Bit
I-Bit
I-Bit
Reserved
Reserved
I-Bit
I-Bit
I-Bit
I-Bit
CAN4 wake-up
CAN4 errors
I-Bit
I-Bit
I-Bit
CAN4RIER (WUPIE)
CAN4RIER (CSCIE, OVRIE)
CAN4RIER (RXFIE)
CAN4 receive
CAN4 transmit
I-Bit CAN4TIER (TXEIE2 - TXEIE0)
Port P
I-Bit
I-Bit
I-Bit
PIEP (PIEP7-0)
PWMSDN (PWMIE)
CTRL0 (LVIE)
PWM Emergency Shutdown
VREG Low Voltage Interrupt
Reserved
NOTES:
1. Interrupt vector is only available on MC9S12KT256. Otherwise it is reserved.
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5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a
system reset are summarized in Table 5-2.
Table 5-2 Reset Summary
Reset
Priority
Source
Vector
$FFFE, $FFFF
$FFFE, $FFFF
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
Power-on Reset
1
1
1
2
3
CRG Module
RESET pin
External Reset
Low Voltage Reset
Clock Monitor Reset
COP Watchdog Reset
VREG Module
CRG Module
CRG Module
5.3.1 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states. Refer to the HCS12 MEBI Block Guide for mode
dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
Refer to Table 1-2(Table 1-2) for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the CPU12 Reference Manual for information about the Central Processing Unit.
When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock periods.
So 1 cycle is equivalent to 1 Bus Clock period.
6.2 HCS12 Background Debug Module (BDM) Block Description
Consult the HCS12 BDM Block Guide for information about the Background Debug Module.
When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock.
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6.3 HCS12 Debug (DBG) Block Description
Consult the HCS12 DBG Block Guide for information about the Debug module.
6.4 HCS12 Interrupt (INT) Block Description
Consult the HCS12 INT Block Guide for information about the Interrupt module.
6.5 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the HCS12 MEBI Block Guide for information about the Multiplexed External Bus Interface
module.
6.6 HCS12 Module Mapping Control (MMC) Block Description
Consult the HCS12 MMC Block Guide for information about the Module Mapping Control module.
Section 7 Analog to Digital Converter (ATD) Block
Description
Consult the ATD_10B16C Block Guide for further information about the A/D Converter module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). When the ATD_10B16C Block
Guide refers to freeze mode this is equivalent to active BDM mode.
Consult the ATD_10B8C Block Guide for further information about the A/D Converter module for the
MC9S12KT256 and MC9S12KG256. When the ATD_10B8C Block Guide refers to freeze mode this is
equivalent to active BDM mode.
Section 8 Clock Reset Generator (CRG) Block Description
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
8.1 Device-specific information
The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the
VREG Block Guide for voltage level specifications.
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Section 9 EEPROM Block Description
Consult the EETS2K Block Guide for information about the EEPROM module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64).
Consult the EETS4K Block Guide for information about the EEPROM module for the MC9S12KT256
and MC9S12KG256.
Section 10 Flash EEPROM Block Description
Consult the FTS128K1ECC Block Guide for information about the flash module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64).
Consult the FTS256K2ECC Block Guide for information about the flash module for the MC9S12KT256
and MC9S12KG256.
The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into
the flash memory of this device during manufacture. This LRAE program will provide greater
programming flexibility to the end users by allowing the device to be programmed directly using SCI after
it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if not
required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and its
implementation, please see the S12 LREA Application Note (AN2546/D) .
It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE
programmed in the Flash . Exact details of the changeover (ie blank to programmed) for each product will
be communicated in advance via GPCN and will be traceable by the customer via datecode marking on
the device.
Please contact Motorola SPS Sales if you have any additional questions.
Section 11 IIC Block Description
Consult the IIC Block Guide for information about the Inter-IC Bus module.
Section 12 MSCAN Block Description
There are three MSCAN modules (CAN4, CAN1 and CAN0) implemented on the MC9S12KT256. There
are only two MSCAN modules (CAN4 and CAN0) implemented on the MC9S12KG128(64)(32). There
is only one MSCAN module (CAN0) implemented on the MC9S12KL128(64) and MC9S12KC128(64).
Consult the MSCAN Block Guide for information about the Motorola Scalable CAN Module.
Section 13 OSC Block Description
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Consult the OSC_LCP Block Guide for information about the Oscillator module.
Section 14 Port Integration Module (PIM) Block Description
Consult the PIM_9KG128 Block Guide for information about the Port Integration Module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64).
Consult the PIM_9KT256 Block Guide for information about the Port Integration Module for the
MC9S12KT256 and MC9S12KG256.
Section 15 Pulse Width Modulator (PWM) Block
Description
Consult the PWM_8B8C Block Guide for information about the Pulse Width Modulator Module. When
the PWM_8B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 16 Serial Communications Interface (SCI) Block
Description
There are two Serial Communications Interface modules (SCI1 and SCI0). Consult the SCI Block Guide
for information about the Serial Communications Interface module.
Section 17 Serial Peripheral Interface (SPI) Block
Description
There are three Serial Peripheral Interfaces (SPI2, SPI1 and SPI0) implemented on MC9S12K-Family.
Consult the SPI Block Guide for information about each Serial Peripheral Interface module.
Section 18 Timer (TIM) Block Description
Consult the TIM_16B8C Block Guide for information about the Timer module. When the TIM_16B8C
Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 19 Voltage Regulator (VREG) Block Description
Consult the VREG_3V3 Block Guide for information about the dual output linear voltage regulator.
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19.1 Device-specific information
19.1.1 VDD1, VDD2, VSS1, VSS2
In all package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2 sides of the
device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected together
internally. VSS1 and VSS2 are connected together internally. This allows systems to employ better supply
routing and further decoupling.
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Appendix A Electrical Characteristics
A.1 General
NOTE: The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Motorola and are subject to
change without notice.
This supplement contains the most accurate electrical information for the MC9S12K-Family of
microcontrollers available at the time of publication. The information should be considered
PRELIMINARY and is subject to change.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE: This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations. They are regularly verified by production monitors.
T:
Those parameters are achieved by design characterization on a small sample size from typical
devices. All values shown in the typical column are within this category.
D:
Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12K-Family utilizes several pins to supply power to the I/O ports, A/D converter, oscillator,
PLL and internal logic.
The VDDA, VSSA pair supplies the A/D converter.
The VDDX, VSSX pair supplies the I/O pins
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The VDDR, VSSR pair supplies the internal voltage regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic.
VDDPLL, VSSPLL supply the oscillator and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDD1 and VDD2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the
sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used
for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is
used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 3.3V/5V I/O pins
Those I/O pins have a nominal level of 3.3V or 5V depending on the application operating point. This
group of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs.The
internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for
the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently.
A.1.3.2 Analog Reference
This group of pins is comprised of the VRH and VRL pins.
A.1.3.3 Oscillator
The pins EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by
VDDPLL.
A.1.3.4 PLL
The pin XFC dedicated to the oscillator have a nominal 2.5V level. It is supplied by VDDPLL.
A.1.3.5 TEST
This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating V
or V range during instantaneous and
DD
DD5
operating maximum current conditions. If positive injection current (V > V
) is greater than I
, the
in
DD5
DD5
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
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Insure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V
or V
).
SS5
DD5
Table A-1 Absolute Maximum Ratings
Num
Rating
Symbol
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Max
6.5
3.0
3.0
0.3
0.3
6.5
6.5
3.0
10.0
Unit
V
VDD5
1
2
3
4
5
6
7
8
9
I/O, Regulator and Analog Supply Voltage
Internal Logic Supply Voltage1
VDD
V
PLL Supply Voltage (1)
VDDPLL
V
∆
Voltage difference VDDX to VDDR and VDDA
Voltage difference VSSX to VSSR and VSSA
Digital I/O Input Voltage
V
VDDX
∆
V
VSSX
VIN
VRH, VRL
VILV
V
Analog Reference
V
XFC, EXTAL, XTAL inputs
TEST input
V
VTEST
V
Instantaneous Maximum Current
Single pin limit for all digital I/O pins 2
ID
10
11
12
-25
-25
+25
+25
0
mA
mA
mA
Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL3
IDL
Instantaneous Maximum Current
Single pin limit for TEST4
IDT
TA
-0.25
13
14
Operating Temperature Range (packaged)
Operating Temperature Range (junction)
Storage Temperature Range
– 40
– 40
– 65
125
140
155
°C
°C
°C
TJ
Tstg
15
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
2. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA
.
3. These pins are internally clamped to VSSPLL and VDDPLL
4. This pin is clamped low to VSSR, but not clamped high. This pin must be tied low in applications.
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
1500
100
Unit
Ohm
pF
Series Resistance
R1
C
Storage Capacitance
Human Body
Number of Pulse per pin
positive
negative
-
3
3
-
Series Resistance
R1
C
0
Ohm
pF
Storage Capacitance
200
Machine
Latch-up
Number of Pulse per pin
positive
negative
-
3
3
-
Minimum input voltage limit
Maximum input voltage limit
-2.5
7.5
V
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num
C
C
C
C
Rating
Symbol
VHBM
Min
2000
200
Max
Unit
V
1
2
3
Human Body Model (HBM)
-
-
-
VMM
Machine Model (MM)
V
VCDM
Charge Device Model (CDM)
500
V
Latch-up Current at 125°C
positive
negative
ILAT
4
5
C
C
+100
-100
-
-
mA
mA
Latch-up Current at 27°C
positive
negative
ILAT
+200
-200
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
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NOTE: Instead of specifying ambient temperature all parameters are specified for the more
meaningful silicon junction temperature. For power dissipation calculations refer
to Section A.1.8 Power Dissipation and Thermal Characteristics.
Table A-4 Operating Conditions
Rating
Symbol
Min
3.15
2.35
2.35
-0.1
-0.1
0.5
Typ
Max
5.5
Unit
V
VDD5
I/O, Regulator and Analog Supply Voltage
3.3/5
Internal Logic Supply Voltage1
VDD
2.5
2.5
0
2.75
2.75
0.1
V
PLL Supply Voltage (1)
VDDPLL
V
∆
Voltage Difference VDDX to VDDA
Voltage Difference VSSX to VSSR and VSSA
Oscillator
V
VDDX
∆
0
0.1
V
VSSX
fosc
fbus
-
16
MHz
MHz
Bus Frequency
0.5
-
25
MC9S12K-FamilyC/MC9S12KT256C
Operating Junction Temperature Range
TJ
TA
-40
-40
-
100
85
°C
°C
Operating Ambient Temperature Range 2
MC9S12K-FamilyV/MC9S12KT256V
27
TJ
TA
Operating Junction Temperature Range
-40
-40
-
120
105
°C
°C
Operating Ambient Temperature Range (2)
MC9S12K-FamilyM/MC9S12KT256M
27
TJ
TA
Operating Junction Temperature Range
-40
-40
-
140
125
°C
°C
Operating Ambient Temperature Range (2)
27
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
absolute maximum ratings apply when this regulator is disabled and the device is powered from an external
source.
2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the rela-
tion between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (T ) in °C can be
J
obtained from:
T = T + (P • Θ
)
J
A
D
JA
T = Junction Temperature, [°C]
J
T
= Ambient Temperature, [°C]
A
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Device User Guide — 9S12KT256DGV1/D V01.09
P
= Total Chip Power Dissipation, [W]
D
Θ
= Package Thermal Resistance, [°C/W]
JA
The total power dissipation can be calculated from:
= P
P
+ P
D
INT
IO
P
= Chip Internal Power Dissipation, [W]
INT
Two cases with internal voltage regulator enabled and disabled must be considered:
1. Internal Voltage Regulator disabled
P
= I
V
+ I
V
+ I
V
INT
DD DD DDPLL DDPLL DDA DDA
2
P
=
R
I
∑
IO
DSON IO
i
i
P is the sum of all output currents on I/O ports associated with VDDX and VDDR.
IO
For R
is valid:
DSON
V
OL
R
= ------------ ;for outputs driven low
DSON
V
I
OL
respectively
– V
DD5
OH
R
= ----------------------------------- ;for outputs driven high
DSON
I
OH
2. Internal voltage regulator enabled
= I
P
V
+ I
V
INT
DDR DDR DDA DDA
I
is the current shown in Table A-8 and not the overall current flowing into VDDR, which
DDR
additionally contains the current flowing into the external loads with output high.
2
P
=
R
I
∑
IO
DSON IO
i
i
P is the sum of all output currents on I/O ports associated with VDDX and VDDR.
IO
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1
Table A-5 Thermal Package Characteristics
Num
C
Rating
Symbol
Min
Typ
Max
Unit
Thermal Resistance LQFP112, single sided PCB2
oC/W
θJA
1
T
-
-
54
Thermal Resistance LQFP112, double sided PCB
with 2 internal planes3
oC/W
oC/W
oC/W
θJA
θJA
θJA
2
T
T
T
-
-
-
-
-
-
41
51
41
3
Thermal Resistance QFP 80, single sided PCB
Thermal Resistance QFP 80, double sided PCB with
2 internal planes
4
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 3.3V/5V I/O pins. All parameters are not always applicable,
e.g. not all pins feature pull up/down resistances.
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Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
Rating
Symbol
Min
Typ
Max
Unit
VIH
0.65*VDD5
VDD5 + 0.3
1
P
Input High Voltage
Input Low Voltage
Input Hysteresis
-
V
VIL
VSS5 - 0.3
0.35*VDD5
2
3
P
C
-
V
VHYS
250
mV
Input Leakage Current (pins in high impedance input
mode)
Vin = VDD5 or VSS5
Iin
4
5
P
P
–2.5
-
-
2.5
-
µA
Output High Voltage (pins in output mode)
Partial Drive I
= –2.0mA
= –10.0mA
VOH
VDD5 – 0.8
OH
V
Full Drive I
OH
Output Low Voltage (pins in output mode)
Partial Drive I = +2.0mA
VOL
6
P
OL
= +10.0mA
-
-
0.8
V
Full Drive I
OL
Internal Pull Up Device Current,
tested at VIL Max.
IPUL
IPUH
IPDH
7
8
9
P
P
P
-
-10
-
-
-
-
–130
-
µA
µA
µA
Internal Pull Up Device Current,
tested at VIH Min.
Internal Pull Down Device Current,
tested at VIH Min.
130
Internal Pull Down Device Current,
tested at VIL Max.
IPDL
Cin
10
11
P
D
10
-
-
-
µA
Input Capacitance
7
pF
Injection current1
Single Pin limit
Total Device Limit. Sum of all injected currents
IICS
IICP
12
T
-2.5
-25
-
2.5
25
mA
Port H, J, P Interrupt Input Pulse filtered2
Port H, J, P Interrupt Input Pulse passed(2)
tpign
tpval
13
P
P
3
µs
µs
14
10
NOTES:
1. Refer to Section A.1.4 Current Injection, for more details
2. Parameter only applies in STOP or Pseudo STOP mode.
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Table A-7 3.3V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
VIH
VIL
0.65*VDD5
VSS5 - 0.3
VDD5 + 0.3
1
2
3
P
P
C
Input High Voltage
Input Low Voltage
Input Hysteresis
-
V
0.35*VDD5
-
V
VHYS
250
mV
Input Leakage Current (pins in high impedance input
mode)
Vin = VDD5 or VSS5
Iin
4
5
P
P
–1
-
-
1
-
µA
Output High Voltage (pins in output mode)
Partial Drive I
= –0.75mA
= –4.5mA
VOH
VDD5 – 0.4
OH
V
Full Drive I
OH
Output Low Voltage (pins in output mode)
Partial Drive I = +0.9mA
VOL
6
P
OL
= +5.5mA
-
-
0.4
V
Full Drive I
OL
Internal Pull Up Device Current,
tested at VIL Max.
IPUL
IPUH
IPDH
7
8
9
P
P
P
-
-6
-
-
-
-
–60
-
µA
µA
µA
Internal Pull Up Device Current,
tested at VIH Min.
Internal Pull Down Device Current,
tested at VIH Min.
60
Internal Pull Down Device Current,
tested at VIL Max.
IPDL
Cin
10
11
P
D
6
-
-
-
µA
Input Capacitance
7
pF
Injection current1
Single Pin limit
Total Device Limit. Sum of all injected currents
IICS
IICP
12
T
-2.5
-25
-
2.5
25
mA
Port P, J Interrupt Input Pulse filtered2
Port P, J Interrupt Input Pulse passed(2)
tPULSE
tPULSE
13
14
P
P
3
µs
µs
10
NOTES:
1. Refer to Section A.1.4 Current Injection, for more details
2. Parameter only applies in STOP or Pseudo STOP mode.
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
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A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
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Table A-8 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
Rating
Symbol
Min
Typ
Max
Unit
Run supply currents
Single Chip, Internal regulator enabled
1
mA
IDD5
65
Wait Supply current
All modules enabled
only RTI enabled1
IDDW
2
3
40
5
mA
Pseudo Stop Current (RTI and COP enabled)1,2
90
130
155
180
250
295
470
520
1000
350
-40°C
27°C
70°C
85°C
IDDPS
µA
1200
2400
5000
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
Pseudo Stop Current (RTI and COP disabled)1,2
40
200
-40°C
80
27°C
70°C
85°C
105
130
200
245
420
470
800
IDDPS
4
µA
1000
2000
5000
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
Stop Current2
20
60
85
100
-40°C
27°C
70°C
110
180
225
400
450
600
85°C
IDDS
5
µA
800
1800
5000
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
NOTES:
1. PLL off
2. All those low power dissipation levels TJ = TA can be assumed.
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A.2 Voltage Regulator (VREG_3V3) Operating Characteristics
This section describes the characteristics of the on chip voltage regulator.
Table A-9 VREG_3V3 - Operating Conditions
Num
C
Characteristic
Symbol
Min
Typical
Max
Unit
VVDDR,A
1
P
Input Voltages
3.15
—
5.5
V
Regulator Current
Reduced Power Mode
Shutdown Mode
IREG
2
3
P
P
—
—
20
12
50
40
µA
µA
Output Voltage Core
Full Performance Mode
Reduced Power Mode
Shutdown Mode1
2.35
1.7
2.5
2.5
2.75
2.75
V
V
V
VDD
—
—
—
Output Voltage PLL
Full Performance Mode
2.5
2.5
2.75
2.75
—
2.35
1.7
—
V
V
V
VDDPLL
4
P
Reduced Power Mode2
Shutdown Mode(1)
—
Low Voltage Interrupt3
Assert Level
Deassert Level
VLVIA
VLVID
5
5
P
P
C
4.1
4.25
4.37
4.52
V
V
4.66
4.77
Low Voltage Reset4
Assert Level
Deassert Level
VLVRA
VLVRD
2.25
—
—
—
—
2.55
V
V
Power-on Reset5
Assert Level
Deassert Level
VPORA
VPORD
7
0.97
—
---
---
—
2.05
V
V
NOTES:
1. High Impedance Output
2. Current IDDPLL = 500µA
3. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to
low supply voltage.
4. Monitors VDD, active only in Full Performance Mode. VLVRA and VPORD must overlap
5. Monitors VDD. Active in all modes.
NOTE: The electrical characteristics given in this section are preliminary and
should be used as a guide only. Values in this section cannot be
guaranteed by Motorola and are subject to change without notice.
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A.3 Chip Power-up and LVI/LVR graphical explanation
Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage
reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-1.
Figure A-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)
V
VDDA
VLVID
VLVIA
VDD
VLVRD
VLVRA
VPORD
t
LVI
LVI enabled
LVI disabled due to LVR
POR
LVR
A.4 Output Loads
A.4.1 Resistive Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no
external DC loads.
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A.4.2 Capacitive Loads
The capacitive loads are specified in Table A-10. Ceramic capacitors with X7R dielectricum are required.
Table A-10 Voltage Regulator - Capacitive Loads
Num
Characteristic
VDD external capacitive load
VDDPLL external capacitive load
Symbol
CDDext
Min
200
90
Typical
440
Max
12000
5000
Unit
nF
1
2
CDDPLLext
220
nF
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A.5 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.5.1 ATD Operating Characteristics
The Table A-11 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
Table A-11 5V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
Reference Potential
1
D
Low
High
VRL
VRH
VSSA
VDDA/2
VDDA/2
VDDA
V
V
Differential Reference Voltage1
2
3
C
VRH-VRL
4.75
0.5
5.0
5.25
2.0
V
D ATD Clock Frequency
f
MHz
ATDCLK
ATD 10-Bit Conversion Period
Clock Cycles2
N
T
T
14
7
3.5
28
14
7
Cycles
µs
µs
CONV10
CONV10
CONV10
4
5
D
Conv, Time at 2.0MHz ATD Clock fATDCLK
Conv, Time at 4.0MHz3 ATD Clock fATDCLK
ATD 8-Bit Conversion Period
Clock Cycles(1)
D
D
N
T
12
6
26
13
Cycles
µs
CONV8
CONV8
Conv, Time at 2.0MHz ATD Clock fATDCLK
Stop Recovery Time (VDDA=5.0 Volts)
6
7
8
t
20
µs
SR
P Reference Supply current (two ATD modules)
P Reference Supply current (one ATD module)
I
0.750
0.375
mA
mA
REF
REF
I
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
3. Reduced accuracy see Table A-14 and Table A-15.
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Table A-12 3.3V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10%
Num C
Rating
Symbol
Min
Typ
Max
/2
Unit
Reference Potential
1
D
Low
High
V
V
V
V
V
RL
SSA
DDA
V
V
/2
V
RH
DDA
DDA
2
3
C Differential Reference Voltage
D ATD Clock Frequency
V
-V
3.0
3.3
3.6
2.0
V
RH RL
f
0.5
MHz
ATDCLK
ATD 10-Bit Conversion Period
Clock Cycles1
N
T
T
14
7
3.5
28
14
7
Cycles
µs
µs
CONV10
CONV10
CONV10
4
5
D
Conv, Time at 2.0MHz ATD Clock fATDCLK
Conv, Time at 4.0MHz2 ATD Clock fATDCLK
ATD 8-Bit Conversion Period
Clock Cycles(1)
D
N
T
12
6
26
13
Cycles
µs
CONV8
CONV8
Conv, Time at 2.0MHz ATD Clock fATDCLK
Recovery Time (VDDA=3.3 Volts)
6
7
8
D
P
P
t
20
µs
REC
Reference Supply current (two ATD modules)
Reference Supply current (one ATD module)
I
I
0.500
0.250
mA
mA
REF
REF
NOTES:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
2. Reduced accuracy see Table A-14 and Table A-15.
A.5.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.5.2.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 and Table A-7in conjunction with the
source resistance there will be a voltage drop from the signal source to the ATD input. The maximum
source resistance R specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage
S
current. If device or operating conditions are less than worst case or leakage-induced error is acceptable,
larger values of source resistance are allowed.
A.5.2.2 Source capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, C ≥ 1024 * (C - C ).
f
INS
INN
A.5.2.3 Current injection
There are two cases to consider.
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1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less
than VRL unless the current is higher than specified as disruptive conditions.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as V
= K * R *
ERR
S
I
, with I being the sum of the currents injected into the two pins adjacent to the converted
INJ
INJ
channel.
Table A-13 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
Rating
Symbol
Min
Typ
Max
Unit
RS
1
Max input Source Resistance
-
-
1
KΩ
Total Input Capacitance
Non Sampling
Sampling
CINN
CINS
2
10
22
pF
INA
Kp
Kn
3
4
5
Disruptive Analog Input Current
-2.5
2.5
10-4
10-2
mA
A/A
A/A
Coupling Ratio positive current injection
Coupling Ratio negative current injection
A.5.3 ATD accuracy
Table A-14 and Table A-15 specify the ATD conversion performance excluding any errors due to
current injection, input capacitance and source resistance.
Table A-14 5V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
f
= 2.0MHz
ATDCLK
Num
C
Rating
Symbol
LSB
Min
Typ
Max
Unit
mV
1
2
3
4
P 10-Bit Resolution
5
P 10-Bit Differential Nonlinearity
P 10-Bit Integral Nonlinearity
DNL
INL
–1
–2.5
-3
1
2.5
3
Counts
Counts
Counts
±1.5
±2.0
±7.0
20
10-Bit Absolute Error1
P
AE
10-Bit Absolute Error at fATDCLK= 4MHz
5
6
7
8
9
C
AE
LSB
DNL
INL
AE
Counts
mV
P 8-Bit Resolution
P 8-Bit Differential Nonlinearity
P 8-Bit Integral Nonlinearity
–0.5
–1.0
-1.5
0.5
1.0
1.5
Counts
Counts
Counts
±0.5
±1.0
8-Bit Absolute Error(1)
P
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NOTES:
1. These values include quantization error which is inherently 1/2 count for any A/D converter.
Table A-15 3.3V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
f
= 2.0MHz
ATDCLK
Num C
Rating
Symbol
LSB
Min
Typ
Max
Unit
mV
1
2
3
4
P 10-Bit Resolution
3.25
P 10-Bit Differential Nonlinearity
P 10-Bit Integral Nonlinearity
DNL
INL
–1.5
–3.5
-5
1.5
3.5
5
Counts
Counts
Counts
±1.5
±2.5
±7.0
13
10-Bit Absolute Error1
P
AE
10-Bit Absolute Error at fATDCLK= 4MHz
5
6
7
8
9
C
AE
LSB
DNL
INL
AE
Counts
mV
P 8-Bit Resolution
P 8-Bit Differential Nonlinearity
P 8-Bit Integral Nonlinearity
–0.5
–1.5
-2.0
0.5
1.5
2.0
Counts
Counts
Counts
±0.1
±1.5
8-Bit Absolute Error(1)
P
NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-2.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
V – V
i
i – 1
DNL(i) =
– 1
------------------------
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
V – V
n
0
-------------------
1LSB
INL(n) =
DNL(i) =
– n
∑
i = 1
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DNL
10-Bit Absolute Error Boundary
LSB
V
V
i
i-1
$3FF
$3FE
$3FD
$3FC
$3FB
$3FA
$3F9
$3F8
$3F7
$3F6
$3F5
$3F4
$3F3
8-Bit Absolute Error Boundary
$FF
$FE
$FD
2
9
8
7
6
5
4
3
2
1
0
Ideal Transfer Curve
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5
10
15
20
25
30
35
40
50
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV
Figure A-2 ATD Accuracy Definitions
NOTE:Figure A-2 shows only definitions, for specification values refer to Table A-14 and Table
A-15 .
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A.6 NVM, Flash and EEPROM
NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.
A.6.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency f
is required for performing program or erase operations. The NVM modules
NVMOSC
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as f
.
NVMOP
The minimum program and erase times shown in Table A-16 are calculated for maximum f
and
NVMOP
maximum f . The maximum times are calculated for minimum f
and a f of 2MHz.
bus
NVMOP
bus
A.6.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency f and can be calculated according to the following formula.
NVMOP
1
1
t
= 9
+ 25
---------------------
----------
swpgm
f
f
NVMOP
bus
A.6.1.2 Row Programming
Flash programming where up to 64 words in a row can be programmed consecutively by keeping the
command pipeline filled. The time to program a consecutive word can be calculated as:
1
1
t
= 4
+ 9
---------------------
----------
bwpgm
f
f
NVMOP
bus
The time to program a whole row is:
t
= t
+ 63 t
brpgm
swpgm
bwpgm
Row programming is more than 2 times faster than single word programming.
A.6.1.3 Sector Erase
Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
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1
t
≈ 4000
---------------------
era
f
NVMOP
The setup time can be ignored for this operation.
A.6.1.4 Mass Erase
Erasing a NVM block takes:
1
t
≈ 20000
---------------------
mass
f
NVMOP
The setup time can be ignored for this operation.
A.6.1.5 Blank Check
The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the
first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup
of the command.
t
≈ location t
+ 10 t
check
cyc
cyc
Table A-16 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
fNVMOSC
fNVMBUS
fNVMOP
tswpgm
Min
0.5
1
Typ
Max
Unit
MHz
MHz
kHz
µs
50 1
1
2
3
4
5
6
7
8
9
D External Oscillator Clock
D Bus frequency for Programming or Erase Operations
D Operating Frequency
150
200
74.5 3
46 2
20.4 (2)
1331.2 (2)
20 5
P Single Word Programming Time
Flash Burst Programming consecutive word 4
D
31 (3)
tbwpgm
tbrpgm
tera
µs
Flash Burst Programming Time for 64 Words (4)
D
2027.5 (3)
26.7 (3)
133 (3)
65546 7
2058(7)
µs
P Sector Erase Time
ms
100 (5)
11 6
tmass
tcheck
tcheck
P Mass Erase Time
ms
tcyc
tcyc
D Blank Check Time Flash per block
11 (6)
10 D Blank Check Time EEPROM per block
NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency
fbus
.
3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus
Refer to formula in Sections Section A.6.1.1 Single Word Programming- Section A.6.1.4 Mass Erase for guidance.
4. Burst Programming operations are not applicable to EEPROM
.
5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP
.
6. Minimum time, if first word in the array is not blank
7. Maximum time to complete check on an erased block
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A.6.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
NOTE: All values shown in Table A-17 are target values and subject to further extensive
characterization.
Table A-17 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
tNVMRET
nFLPE
Min
15
Typ
Max
Unit
Years
Cycles
Data Retention at an average junction temperature of
1
2
3
C
T
Javg = 70°C
C Flash number of Program/Erase cycles
EEPROM number of Program/Erase cycles
1000
10,000
nEEPE
C
10,000
Cycles
Cycles
(–40°C ≤ TJ ≤ 0°C)
EEPROM number of Program/Erase cycles
nEEPE
4
C
100,000
(0°C < TJ ≤ 140°C)
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
A.7 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.7.1 Startup
Table A-18 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-18 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
VPORR
VPORA
PWRSTL
nRST
Min
Typ
Max
Unit
V
1
2
3
4
5
6
T POR release level
T POR assert level
2.07
0.97
2
V
tosc
nosc
D Reset input pulse width, minimum input time
D Startup from Reset
192
20
196
14
PWIRQ
tWRS
D Interrupt pulse width, IRQ edge-sensitive mode
D Wait recovery startup time
ns
tcyc
A.7.1.1 POR
The release level V
and the assert level V
are derived from the V Supply. They are also valid
PORA DD
PORR
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t no valid oscillation is detected, the MCU will start using the internal self
CQOUT
clock. The fastest startup time possible is given by n
.
uposc
A.7.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.7.1.3 External Reset
When external reset is asserted for a time greater than PW
the CRG module generates an internal
RSTL
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.7.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
A.7.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t the CPU starts
wrs
fetching the interrupt vector.
A.7.2 Oscillator
The device features an internal low-power loop controlled Pierce oscillator and a full swing Pierce
oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset. Full swing Pierce
oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. t
specifies the maximum time before switching to the internal self clock mode after
CQOUT
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscillator start-up time t . The device also features a clock monitor. A Clock Monitor Failure is
UPOSC
asserted if the frequency of the incoming clock signal is below the Assert Frequency f
CMFA
Table A-19 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
4.0
Typ
Max
16
Unit
MHz
MHz
µA
ms
s
fOSC
1a C Crystal oscillator range (loop controlled Pierce)
Crystal oscillator range (full swing Pierce) 1,2
fOSC
iOSC
1b
2
C
0.5
40
P Startup Current
100
33
504
2.5
200
50
tUPOSC
tCQOUT
fCMFA
fEXT
3
C Oscillator start-up time (loop controlled Pierce)
D Clock Quality check time-out
4
0.45
50
5
P Clock Monitor Failure Assert Frequency
100
KHz
MHz
ns
External square wave input frequency 2
P
6
0.5
9.5
9.5
tEXTL
tEXTH
tEXTR
tEXTF
CIN
7
D External square wave pulse width low
D External square wave pulse width high
D External square wave rise time
8
ns
9
1
1
ns
10 D External square wave fall time
ns
11 D Input Capacitance (EXTAL, XTAL pins)
7
pF
V
VIH,EXTAL 0.7*VDDPLL
VIH,EXTAL
12
P EXTAL Pin Input High Voltage
T EXTAL Pin Input High Voltage
P EXTAL Pin Input Low Voltage
T EXTAL Pin Input Low Voltage
VDDPLL + 0.3
0.3*VDDPLL
V
VIL,EXTAL
13
V
VIL,EXTAL VSSPLL - 0.3
VHYS,EXTAL
V
14 C EXTAL Pin Input Hysteresis
250
mV
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
2. Only valid if full swing Pierce oscillator/external clock mode is selected
3. fOSC = 4MHz, C = 22pF.
4. Maximum value is for extreme cases using high Q, low frequency crystals
A.7.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.7.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
C
p
VDDPLL
R
C
XFC Pin
s
Phase
VCO
f
f
vco
f
1
ref
osc
∆
K
K
Φ
V
refdv+1
Detector
f
cmp
Loop Divider
1
1
2
synr+1
Figure A-3 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K , f and i from Table A-20.
1
1
ch
The grey boxes show the calculation for f
= 50MHz and f = 1MHz. E.g., these frequencies are used
ref
VCO
for f
= 4MHz and a 25MHz bus clock.
OSC
The VCO Gain at the desired VCO frequency is approximated by:
(f1 – fvco
-----------------------
K1 1V
)
(60 – 50)
-----------------------
–100
K = K e
= -90.48MHz/V
= –100 e
V
1
The phase detector relationship is given by:
Freescale Semiconductor
107
Device User Guide — 9S12KT256DGV1/D V01.09
K = – i
K
= 316.7Hz/Ω
Φ
ch
V
i is the current in tracking mode.
ch
The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
C
typical values are 50. ζ = 0.9 ensures a good transient response.
2 ζ f
f
ref
1
ref
f < ------------------------------------------
→ f < ------------- ;(ζ = 0.9)
------
10
C
C
4 10
fC < 25kHz
2
π ζ + 1 + ζ
And finally the frequency relationship is defined as
f
VCO
n = ------------- = 2 (s y n r + 1 )
= 50
f
ref
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f =10kHz:
C
2 π n f
C
= 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ
R = ----------------------------
K
Φ
The capacitance C can now be calculated as:
s
2
0.516
≈ --------------;(ζ = 0.9)
2 ζ
= 5.19nF =~ 4.7nF
C =
---------------------
π f
s
f
R
R
C
C
The capacitance C should be chosen in the range of:
p
C ⁄ 20 ≤ C ≤ C ⁄ 10
Cp = 470pF
s
p
s
A.7.3.2 Jitter Information
NOTE: This section is under construction
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock f , the
cmp
deviation from the reference clock f is measured and input voltage to the VCO is adjusted
ref
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
1
2
3
N-1
N
0
t
min1
t
nom
t
max1
t
minN
t
maxN
Figure A-4 Jitter Definitions
is at its maximum for one clock period, and decreases towards zero for larger
The relative deviation of t
nom
number of clock periods (N).
Defining the jitter as:
t
(N)
t
(N)
max
min
J(N) = max 1 –
, 1 –
--------------------
---------------------
N t
N t
nom
nom
NOTE: From the evaluation data a formula for t = f(N), resp. t = f(N) should be
max
min
derived.
Assuming no long term drift of the reference clock, the following will hold
lim J(N) = 0
N → ∞
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Table A-20 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
fSCM
Min
1
Typ
Max
5.5
Unit
MHz
MHz
1
2
P
D
Self Clock Mode frequency
fVCO
VCO locking range
8
50
Lock Detector transition from Acquisition to Tracking
mode
4%1
∆
3
D
3%
—
trk
1.5%(1)
2.5%(1)
∆
4
5
D
D
Lock Detection
0%
—
—
Lock
∆
Un-Lock Detection
0.5%
unl
Lock Detector transition from Tracking to Acquisition
mode
8%(1)
∆
6
D
6%
—
unt
PLLON Total Stabilization delay2
tstab
tacq
tal
7
C
D
D
D
D
D
D
C
C
0.5
0.3
ms
ms
PLLON Acquisition mode stabilization delay(2)
8
PLLON Tracking mode stabilization delay(2)
Fitting parameter VCO loop gain
9
0.2
ms
K1
f1
10
11
12
13
14
15
-100
60
MHz/V
MHz
µA
Fitting parameter VCO loop frequency
Charge pump current acquisition mode
Charge pump current tracking mode
ich
ich
j1
-38.5
-3.5
µA
Jitter fit parameter 1(2)
Jitter fit parameter 2(2)
1.1
%
j2
0.13
%
NOTES:
1. % deviation from target frequency
2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs =
10KΩ.
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
A.8 MSCAN
Table A-21 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
tWUP
Min
Typ
Max
Unit
µs
1
2
P MSCAN Wake-up dominant pulse filtered
P MSCAN Wake-up dominant pulse pass
2
tWUP
5
µs
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
A.9 SPI
A.9.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-22.
SS1
(OUTPUT)
2
1
11
12
3
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
LSB IN
BIT 6 . . . 1
9
9
10
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-5 SPI Master Timing (CPHA = 0)
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
SS1
(OUTPUT)
1
12
11
11
12
3
2
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
10
BIT 6 . . . 1
9
MOSI
(OUTPUT)
MASTER MSB OUT2
PORT DATA
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-6 SPI Master Timing (CPHA =1)
Table A-22 SPI Master Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num
1
C
P
P
D
D
D
D
D
D
D
D
D
Rating
Symbol
Min
DC
Typ
Max
1/4
Unit
fbus
tbus
tsck
fop
tsck
tlead
tlag
twsck
tsu
thi
Operating Frequency
1
SCK Period
4
2048
—
2
Enable Lead Time
1/2
tsck
3
Enable Lag Time
1/2
t
bus − 30
1024 tbus
4
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid (after SCK Edge)
Data Hold Time (Outputs)
Rise Time Inputs and Outputs
Fall Time Inputs and Outputs
ns
ns
ns
ns
ns
ns
ns
5
25
0
6
tv
9
25
tho
tr
10
11
12
0
25
25
tf
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
A.9.2 Slave Mode
Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-23.
SS
(INPUT)
1
12
11
11
12
3
SCK
(CPOL = 0)
(INPUT)
4
4
2
SCK
(CPOL = 1)
(INPUT)
8
7
9
10
10
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
6
SLAVE
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined but normally MSB of character just received.
Figure A-7 SPI Slave Timing (CPHA = 0)
SS
(INPUT)
3
1
12
11
12
2
SCK
(CPOL = 0)
(INPUT)
4
4
11
10
SCK
(CPOL = 1)
(INPUT)
8
9
MISO
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE MSB OUT
(OUTPUT)
NOTE
7
5
6
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE: Not defined but normally LSB of character just received.
Figure A-8 SPI Slave Timing (CPHA =1)
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Table A-23 SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num
1
C
P
P
D
D
D
D
D
D
D
D
D
D
D
Rating
Symbol
fop
Min
Typ
Max
1/4
Unit
fbus
tbus
tcyc
Operating Frequency
DC
tsck
tlead
tlag
twsck
tsu
1
SCK Period
4
2048
2
Enable Lead Time
1
1
tcyc
3
Enable Lag Time
t
cyc − 30
4
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Slave Access Time
ns
ns
5
25
25
thi
6
ns
ta
tcyc
tcyc
7
1
1
tdis
tv
8
Slave MISO Disable Time
Data Valid (after SCK Edge)
Data Hold Time (Outputs)
Rise Time Inputs and Outputs
Fall Time Inputs and Outputs
9
25
ns
ns
ns
ns
tho
10
11
12
0
tr
25
25
tf
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
A.10 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing
values shown on table Table A-24. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.10.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
1, 2
3
4
ECLK
PE4
5
6
16
10
9
15
11
Addr/Data
(read)
PA, PB
data
data
data
addr
7
8
12
14
data
13
Addr/Data
(write)
PA, PB
addr
17
19
23
26
18
Non-Multiplexed
Addresses
PK5:0
20
21
22
ECS
PK7
24
27
25
28
R/W
PE2
29
32
LSTRB
PE3
31
34
30
33
NOACC
PE7
35
36
PIPO0
PIPO1, PE6,5
Figure A-9 General External Bus Timing
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Table A-24 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num
1
C
P
P
D
D
D
D
D
D
D
D
D
D
D
Rating
Frequency of operation (E-clock)
Cycle time
Symbol
fo
Min
0
Typ
Max
Unit
1
25.0
tcyc
2
40
17
17
2
PWEL
3
Pulse width, E low
3
Pulse width, E high1
PWEH
tAD
4
4
5
Address delay time
8
5
Address valid time to E rise (PWEL–tAD
)
tAV
6
11
2
6
tMAH
tAHDS
tDHA
tDSR
tDHR
tDDW
tDHW
tDSW
7
Muxed address hold time
Address hold to data valid
Data hold to address
Read data setup time
Read data hold time
Write data delay time
Write data hold time
7
8
7
8
9
2
9
10
11
12
13
13
0
10
11
12
13
7
2
10
19
4
Write data setup time(1) (PWEH–tDDW
)
14
15
D
D
14
15
Address access time(1) (tcyc–tAD–tDSR
E high access time(1) (PWEH–tDSR
)
tACCA
tACCE
tNAD
tNAV
tNAH
tCSD
tACCS
tCSH
tCSN
tRWD
tRWV
tRWH
tLSD
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
)
Non-multiplexed address delay time
7
Non-muxed address valid to E rise (PWEL–tNAD
Non-multiplexed address hold time
Chip select delay time
)
10
2
16
Chip select access time(1) (tcyc–tCSD–tDSR
Chip select hold time
)
11
2
Chip select negated time
8
Read/write delay time
7
7
7
Read/write valid time to E rise (PWEL–tRWD
)
10
2
Read/write hold time
Low strobe delay time
Low strobe valid time to E rise (PWEL–tLSD
)
tLSV
10
2
tLSH
Low strobe hold time
tNOD
tNOV
NOACC strobe delay time
NOACC valid time to E rise (PWEL–tLSD
)
10
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Table A-24 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
tNOH
tP0D
tP0V
tP1D
tP1V
32
33
34
35
D
D
D
D
D
NOACC hold time
2
2
32
33
34
35
36
PIPO0 delay time
7
7
PIPO0 valid time to E rise (PWEL–tP0D
)
10
2
PIPO1 delay time(1) (PWEH-tP1V
PIPO1 valid time to E fall
)
36
10
NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
Freescale Semiconductor
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Device User Guide — 9S12KT256DGV1/D V01.09
Freescale Semiconductor
120
Device User Guide — 9S12KT256DGV1/D V01.09
Appendix B Package Information
This section provides the physical dimensions of the MC9S12K-Family packages.
Freescale Semiconductor
121
Device User Guide — 9S12KT256DGV1/D V01.09
B.1 80-pin QFP package
L
60
61
41
40
B
B
P
-A-
L
-B-
V
B
-A-,-B-,-D-
DETAIL A
DETAIL A
21
80
F
1
20
-D-
A
M
S
S
S
0.20
H A-B
D
D
0.05 A-B
J
N
S
M
S
0.20
C A-B
D
M
E
DETAIL C
M
S
S
0.20
C A-B
D
SECTION B-B
VIEW ROTATED 90
C
DATUM
PLANE
-H-
°
-C-
SEATING
PLANE
0.10
H
M
G
NOTES:
MILLIMETERS
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
DIM MIN
MAX
13.90 14.10
13.90 14.10
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
A
B
C
D
E
F
G
H
J
2.15
0.22
2.00
0.22
2.45
0.38
2.40
0.33
U
T
0.65 BSC
DATUM
PLANE
---
0.13
0.65
0.25
0.23
0.95
-H-
R
K
L
12.35 REF
10
M
N
P
Q
R
S
T
U
V
W
X
5
°
°
0.13
0.17
0.325 BSC
K
0
0.13
7
0.30
Q
°
°
W
16.95 17.45
X
0.13
---
---
DETAIL C
0
°
16.95 17.45
0.35 0.45
1.6 REF
Figure B-1 80-pin QFP Mechanical Dimensions (case no. 841B)
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B.2 100-pin LQFP package
4X
0.2
T
L–M
N
G
0.2
T
L–M N
4X 25 TIPS
76
100
C
L
X
1
AB
AB
75
X = L, M OR N
VIEW Y
L
M
B
V
BASE METAL
F
3X
VIEW Y
V1
B1
J
U
D
25
51
PLATING
M
0.08
T
L–M N
26
50
N
A1
S1
SECTION AB–AB
ROTATED 90 CLOCKWISE
A
S
NOTES:
1. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT THE
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
PER SIDE. DIMENSIONS A AND B INCLUDE MOLD
MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.35.
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTRUSION 0.07.
4X
2
3
C
100X
0.08
T
SEATING
PLANE
T
4X
VIEW AA
MILLIMETERS
DIM
A
MIN
14.00 BSC
MAX
A1
B
B1
C
C1
C2
D
E
F
G
7.00 BSC
14.00 BSC
7.00 BSC
0.05
–––
0.05
1.30
0.10
0.45
0.15
1.70
(W)
0.20
1.50
0.30
0.75
0.23
1
2X R R1
0.25
C2
0.50 BSC
J
0.07
0.20
K
0.50 REF
GAGE PLANE
R1
S
S1
U
0.08
0.20
16.00 BSC
8.00 BSC
0.09 0.16
16.00 BSC
8.00 BSC
0.20 REF
1.00 REF
(K)
E
C1
V
(Z)
VIEW AA
V1
W
Z
0
0
7
–––
1
2
3
12 REF
12 REF
CASE 983–02
ISSUE E
DATE 01/30/96
Figure B-2 100-pin LQFP Mechanical Dimensions (case no. 983)
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123
Device User Guide — 9S12KT256DGV1/D V01.09
B.3 112-pin LQFP package
4X
0.20 T L-M N
4X 28 TIPS
0.20 T L-M N
4X
P
J1
J1
PIN 1
IDENT
112
85
C
1
84
L
VIEW Y
X
108X
G
X=L, M OR N
VIEW Y
V
B
L
M
AA
J
B1
V1
28
57
BASE
METAL
F
D
29
56
M
0.13
T L-M N
N
SECTION J1-J1
A1
S1
ROTATED 90 COUNTERCLOCKWISE
°
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMSL, MANDNTOBEDETERMINEDAT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED
AT
A
S
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE.
DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE
DAMBAR
C2
VIEW AB
0.10 T
θ2
θ3
C
0.050
112X
SEATING
PLANE
MILLIMETERS
DIM MIN
MAX
A
A1
B
B1
C
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
--- 1.600
T
C1 0.050 0.150
C2 1.350 1.450
θ
D
E
F
G
J
0.270 0.370
0.450 0.750
0.270 0.330
0.650 BSC
0.090 0.170
0.500 REF
R R2
K
P
0.325 BSC
R1 0.100 0.200
R2 0.100 0.200
0.25
R R1
S
S1
V
V1
Y
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
GAGE PLANE
Z
(K)
E
C1
θ1
AA 0.090 0.160
8 °
3 ° 7 °
13 °
11 ° 13 °
0 °
θ
θ1
θ2
θ3
(Y)
(Z)
11 °
VIEW AB
Figure B-3 112-pin LQFP Mechanical Dimensions (case no. 987)
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Device User Guide — 9S12KT256DGV1/D V01.09
Freescale Semiconductor
125
FINAL PAGE OF
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