MCF51MM256CLL [FREESCALE]
low-cost, low-power, high-performance ColdFire® V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering devices.; 低成本，低功耗，高性能的ColdFire® V1系列专为手持式计量设备的32位微控制器（MCU ） 。
| 型号： | MCF51MM256CLL |
| 厂家： | 
Freescale |
| 描述： | low-cost, low-power, high-performance ColdFire® V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering devices. |
| 文件： | 总52页 (文件大小：1485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advanced Information
Document Number: MCF51MM256
Rev. 3, 04/2010
An Energy-Efficient Solution from Freescale
MCF51MM256/128
MCF51MM256/128
The MCF51MM256 series devices are members of the
low-cost, low-power, high-performance ColdFire® V1 family of
32-bit microcontrollers (MCUs) designed for handheld
metering devices.
Not all features are available in all devices or packages; see
Table 2 for a comparison of features by device.
80-LQFP
12mm x 12mm
100-LQFP
14mm x 14mm
81-BGA
10mm x 10mm
104-BGA
10mm x 10mm
help save system cost, fully compliant with USB Specification 2.0. Allows
control, bulk, interrupt and isochronous transfers.
32-Bit ColdFire V1 Central Processor Unit (CPU)
•
Up to 50.33-MHz ColdFire CPU above 2.4 V and 40 MHz CPU above
2.1 V and 20 MHz CPU above 1.8 V across temperature range of -40°C to
105°C.
ColdFire Instruction Set Revision C (ISA_C).
32-bit multiply and accumulate (MAC) supports signed or unsigned integer
or signed fractional inputs.
•
•
•
•
•
•
•
•
SCIx — Two serial communications interfaces with optional 13-bit break;
option to connect Rx input to PRACMP output on SCI1 and SCI2; High
current drive on Tx on SCI1 and SCI2; wake-up from stop3 on Rx edge.
SPI1 — Serial peripheral interface with 64-bit FIFO buffer; 16-bit or 8-bit
data transfers; full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first shifting.
SPI2 — Serial peripheral interface with full-duplex or single-wire
bidirectional; Double-buffered transmit and receive; Master or Slave
mode; MSB-first or LSB-first shifting.
•
•
On-Chip Memory
•
256 K Flash comprised of two independent 128 K flash arrays;
read/program/erase over full operating voltage and temperature; allows
interrupt processing while programming.
32 Kbytes System Random-access memory (RAM).
Security circuitry to prevent unauthorized access to RAM and Flash
contents.
IIC — Up to 100 kbps with maximum bus loading; Multi-master operation;
Programmable slave address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 11-bit addressing.
CMT — Carrier Modulator timer for remote control communications.
Carrier generator, modulator and driver for dedicated infrared out (IRO).
Can be used as an output compare timer.
TPMx — Two 4-channel Timer/PWM Module; Selectable input capture,
output compare, or buffered edge- or center-aligned PWM on each
channel; external clock input/pulse accumulator.
Mini-FlexBus — Multi-function external bus interface with user
programmable chip selects and the option to multiplex address and data
lines.
PRACMP — Analog comparator with selectable interrupt; compare option
to programmable internal reference voltage; operation in stop3.
•
•
Power-Saving Modes
•
•
•
Two ultra-low power stop modes. Peripheral clock enable register can
disable clocks to unused modules to reduce currents.
Time of Day (TOD) — Ultra low-power 1/4 sec counter with up to 64s
timeout.
Ultra-low power external oscillator that can be used in stop modes to
provide accurate clock source to the TOD. 6 usec typical wake up time
from stop3 mode.
Clock Source Options
•
•
•
Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz crystal or
Measurement Engine
ceramic resonator dedicated for TOD operation.
•
ADC16 — 16-bit successive approximation ADC with up to 4 dedicated
Oscillator (XOSC2) for high frequency crystal input for MCG reference to
be used for system clock and USB operations.
Multipurpose Clock Generator (MCG) — PLL and FLL; precision trimming
of internal reference allows 0.2% resolution and 2% deviation over
temperature and voltage; supports CPU frequencies from 4 kHz to
50 MHz.
differential channels and 8 single-ended channels; range compare
function; 1.7 mV/°C temperature sensor; internal bandgap reference
channel; operation in stop3; fully functional from 3.6 V to 1.8 V,
Configurable hardware trigger for 8 Channel select and result registers.
PDB — Programmable delay block with 16-bit counter and modulus and
prescale to set reference clock to bus divided by 1 to bus divided by 2048;
8 trigger outputs for ADC module provides periodic coordination of ADC
sampling sequence with sequence completion interrupt; Back-to-Back
mode and Timed mode.
•
System Protection
•
Watchdog computer operating properly (COP) reset with option to run from
dedicated 1 kHz internal clock source or bus clock.
•
Low-voltage detection with reset or interrupt; selectable trip points;
separate low voltage warning with optional interrupt; selectable trip points.
Illegal opcode and illegal address detection with reset.
Flash block protection for each array to prevent accidental write/erasure.
Hardware CRC to support fast cyclic redundancy checks.
•
•
•
DAC — 12-bit resolution; 16-word data buffers with configurable
watermark.
•
•
•
OPAMPx — 2 flexible operational amplifiers configurable for general
operations; Low offset and temperature drift.
TRIAMPx — 2 trans-impedance amplifiers dedicated for converting
current inputs into voltages.
Development Support
•
Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM
connection supports same electrical interface used by the S08 family
debug modules.
•
•
Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1
data).
On-chip trace buffer provides programmable start/stop recording
conditions.
Peripherals
•
USB — Dual-role USB On-The-Go (OTG) device, supports USB in either
device, host or OTG configuration. On-chip transceiver and 3.3V regulator
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Table of Contents
Figure 7. Offset at Half Scale vs Temperature . . . . . . . . . . . . . 27
List of Topics
Figure 9. ADC Input Impedance Equivalency Diagram (MM256
16-BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 9. Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . 37
Figure 10. Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . 37
Figure 11. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 14. Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . 40
Figure 15. SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . 41
Figure 16. SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . 42
Figure 17. SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 42
Figure 18. SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 43
2 Pinouts and Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . .7
2.1 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.2 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.4 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . .15
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .15
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.4 ESD Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . .18
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . .22
3.7 PRACMP Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.8 12-bit DAC Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.10 MCG and External Oscillator (XOSC) Characteristics . . . .33
3.11 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . . . . . .36
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.13 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.15 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.16 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .45
3.17 TRIAMP Electrical Parameters . . . . . . . . . . . . . . . . . . . . . .47
3.18 OPAMP Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . .48
List of Tables
Table 2. MCF51MM256/128 Functional Units . . . . . . . . . . . . . . 5
Table 2. Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . 16
Table 6. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 18
Table 8. ESD and Latch-Up Protection Characteristics . . . . . . 18
Table 9. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Supply Current Characteristics . . . . . . . . . . . . . . . . . 22
Table 11. Typical Stop Mode Adders . . . . . . . . . . . . . . . . . . . . 24
Table 12. PRACMP Electrical Specifications . . . . . . . . . . . . . . 22
Table 13. DAC12LV Specifications . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. DAC 12LV Operating Requirements . . . . . . . . . . . . . 26
Table 14. DAC 12-Bit Operating Behaviors . . . . . . . . . . . . . . . 27
Table 16. 16-bit ADC Operating Conditions . . . . . . . . . . . . . . . 25
Table 17. MCG (Temperature Range = –40 to 105°C Ambient) 33
Table 18. XOSC (Temperature Range = –40 to 105°C Ambient) 35
Table 19. Mini-FlexBus AC Timing Specifications . . . . . . . . . . 36
Table 21. TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 22. SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 23. Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24. Internal USB 3.3 V Voltage Regulator Characteristics 44
Table 31. VREVREF Electrical Specifications . . . . . . . . . . . . . 59
Table 28. TRIAMP Characteristics 1.8-3.6 V, -40°C~105°C . . . 47
Table 29. OPAMP Characteristics 1.8-3.6 V . . . . . . . . . . . . . . . 48
Table 26. Orderable Part Number Summary . . . . . . . . . . . . . . 39
Table 31. Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 32. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.2 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.3 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.4 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
List of Figures
Figure 1. MCF51MM256/128 Block Diagran . . . . . . . . . . . . . . . .3
Figure 2. 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 3. 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 4. 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 5. 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6. Typical INL Error vs Digital Code . . . . . . . . . . . . . . . .24
2
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Figure 1. MCF51MM256/128 Block Diagran
Freescale Semiconductor
3
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Features
1
Features
The following table provides a cross-comparison of the features of the MCF51MM256/128 according to
package.
Table 1. MCF51MM256/128 Features by MCU and Package
Feature
MCF51MM256
MCF51MM128
FLASH Size (bytes)
RAM Size (bytes)
Pin Quantity
262144
32K
131072
32K
104
yes
yes
yes
yes
yes
16
100
yes
yes
yes
yes
yes
16
81
80
yes
yes
yes
yes
yes
16
81
yes
yes
yes
yes
yes
16
80
yes
yes
yes
yes
yes
16
Programmable Analog Comparator (PRACMP)
Debug Module (DBG)
yes
yes
yes
yes
yes
16
Multipurpose Clock Generator (MCG)
Inter-Integrated Communication (IIC)
Interrupt Request Pin (IRQ)
Keyboard Interrupt (KBI)
Digital General Purpose I/O1
Dedicated Analog Input Pins
Power and Ground Pins
Time Of Day (TOD)
69
65
48
47
48
47
14
14
14
14
14
14
8
8
8
8
8
8
yes
yes
yes
yes
yes
yes
yes
4
yes
yes
yes
yes
yes
yes
yes
4
yes
yes
yes
yes
yes
yes
yes
4
yes
yes
yes
yes
yes
yes
yes
4
yes
yes
yes
yes
yes
yes
yes
4
yes
yes
yes
yes
yes
yes
yes
4
Serial Communications (SCI1)
Serial Communications (SCI2)
Serial Peripheral Interface (SPI1(FIFO))
Serial Peripheral Interface(SPI2)
Carrier Modulator Timer Pin (IRO)
TPM Input Clock Pin (TPMCLK)
TPM1 Channels
TPM2 Channels
4
4
4
4
4
4
XOSC1
yes
yes
yes
yes
16
yes
yes
yes
yes
16
yes
yes
yes
DATA
9
yes
yes
yes
DATA
9
yes
yes
yes
DATA
9
yes
yes
yes
DATA
9
XOSC2
USB On-the-Go
Mini-FlexBus
Rapid GPIO
MEASUREMENT ENGINE
Programmable Delay Block (PDB)
yes
4
yes
4
yes
4
yes
4
yes
4
yes
4
16-Bit SAR ADC Differential Channels2
16-Bit SAR ADC Single-Ended Channels
DAC Ouput Pin (DACO)
8
8
8
8
8
8
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Voltage Reference Output Pin (VREFO)
General Purpose Operational Amplifier (OPAMP)
Trans-Impedance Amplifier (TRIAMP)
1
Port I/O count does not include BLMS, BKGD and IRQ. BLMS and BKGD are Output only, IRQ is input only.
Each differential channel is comprised of 2 pin inputs.
2
4
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Features
The following table describes the functional units of the MCF51MM256/128.
Table 2. MCF51MM256/128 Functional Units
Unit
Function
DAC (digital to analog converter) — Used to output voltage levels.
16-BIT SAR ADC (analog-to-digital converter) — Measures analog
voltages at up to 16 bits of resolution. The ADC has up to four differential
and 8 single-ended inputs.
OPAMP — General purpose op amp used for signal filtering or
amplification.
Measurement Engine
TRIAMP —- Transimpedance amplifier optimized for converting small
currents into voltages.
Measurement Engine PDB — The measurement engine PDB is used to
precisely trigger the DAC and the ADC modules to complete sensor
biasing and measuring.
Mini-FlexBus
Provides expansion capability for off-chip memory and peripherals.
Supports the USB On-the-Go dual-role controller.
USB On-the-Go
CMT (Carrier Modulator Timer)
Infrared output used for the Remote Controller operation.
Provides clocking options for the device, including a phase-locked loop
(PLL) and frequency-locked loop (FLL) for multiplying slower reference
clock sources.
MCG (Multipurpose Clock Generator)
BDM (Background Debug Module)
CF1 CORE (V1 ColdFire Core)
Provides single pin debugging interface (part of the V1 ColdFire core).
Executes programs and interrupt handlers.
Analog comparators for comparing external analog signals against
each other, or a variety of reference levels.
PRACMP
COP (Computer Operating Properly)
IRQ (Interrupt Request)
Software Watchdog.
Single-pin high-priority interrupt (part of the V1 ColdFire core).
High-speed CRC calculation.
CRC (Cyclic Redundancy Check)
Provides debugging and emulation capabilities (part of the V1 ColdFire.
core)
DBG (Debug)
FLASH (Flash Memory)
IIC (Inter-integrated Circuits)
INTC (Interrupt Controller)
KBI1 & KBI2
Provides storage for program code, constants, and variables.
Supports standard IIC communications protocol and SMBus.
Controls and prioritizes all device interrupts.
Keyboard Interfaces 1 and 2.
Provides an interrupt to theColdFire V1 CORE in the event that the
supply voltage drops below a critical value. The LVD can also be
programmed to reset the device upon a low voltage event.
LVD (Low-voltage Detect)
VREF (Voltage Reference)
The Voltage Reference output is available for both on- and off-chip use.
Provides stack and variable storage.
RAM (Random-Access Memory)
RGPIO (Rapid General-purpose
Input/output)
Allows for I/O port access at CPU clock speeds. RGPIO is used to
implement GPIO functionality.
Freescale Semiconductor
5
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Features
Table 2. MCF51MM256/128 Functional Units (continued)
Function
Unit
SCI1, SCI2 (Serial Communications
Interfaces)
Serial communications UARTs capable of supporting RS-232 and LIN
protocols.
SIM (system integration unit)
SPI1 (FIFO), SPI2 (Serial Peripheral
Interfaces)
SPI1 and SPI2 provide standard master/slave capability. SPI contains a
FIFO buffer in order to increase the throughput for this peripheral.
Timer/PWM module can be used for a variety of generic timer
operations as well as pulse-width modulation.
TPM1, TPM2 (Timer/PWM Module)
VREG (Voltage Regulator)
Controls power management across the device.
These devices incorporate redundant crystal oscillators. One is
XOSC1 and XOSC2 (Crystal Oscillators) intended primarily for use by the TOD, and the other by the CPU and
other peripherals.
6
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Pinouts and Pin Assignments
2
Pinouts and Pin Assignments
2.1
104-Pin MAPBGA
The following figure shows the 104-pin MAPBGA pinout configuration.
1
2
3
4
5
6
7
8
9
10
11
PTF6
PTF7
USB_DP USB_DM VUSB33
PTF4
PTF3
FB_AD12
PTJ7
PTJ5
PTJ4
A
B
C
D
E
A
B
C
D
E
F
PTG0
IRO
PTA0
PTG4
PTA4
PTG3
PTA6
VBUS
PTG2
VDD1
PTF5
PTG6
PTJ6
PTG5
VDD2
PTH0
PTG7
PTE5
PTH1
VDD3
PTF0
PTE4
PTA1
PTA2
PTJ2
PTD5
PTD4
PTC2
PTC4
PTF1
PTE6
PTE3
PTJ3
PTJ0
PTD7
PTD3
PTC0
PTC5
PTF2
PTE7
PTE2
PTE1
PTJ1
PTE0
PTD2
PTC1
PTC6
PTA5
PTB1
PTB0
INP2-
OUT2
PTA3
VSSA
PTA7
VREFL
TRIOUT1
VINP1
DADP0
VINP2
INP1-
OUT1
VINN1
DADM0
VINN2
PTG1
PTC7
F
G
G
H
J
H
VSS1
PTH6
PTH5
VSS2
PTH3
PTB7
VSS3
PTD6
PTD1
PTH7
DADP1
PTH4
PTB6
PTH2
PTC3
J
K
L
K
L
TRIOUT2
DACO
DADM1
VREFO
VREFH
VDDA
PTB3
PTB2
PTD0
PTB5
PTB4
1
2
3
4
5
6
7
8
9
10
11
Figure 2. 104-Pin MAPBGA
Freescale Semiconductor
7
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Pinouts and Pin Assignments
2.2
100-Pin LQFP
The following figure shows the 100-pin LQFP pinout configuration.
PTE4/CMPP3/TPMCLK/IRQ
PTA0/FB_D2/SS1
IRO
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTJ3/RGPIOP12/FB_AD5
PTJ2/FB_AD4
2
3
PTG5/FB_RW
4
PTG6/FB_AD19
PTG7/FB_AD18
PTH0/FB_OE
5
6
7
PTH1/FB_D0
PTJ1/FB_AD3
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
8
PTJ0/FB_AD2
PTE0/KBI2P3/FB_ALE/FB_CS1
9
PTD7/USB_PULLUP(D+)/RX1
PTA3/KBI1P2/FB_D6/ADP5
PTA4/INP1+
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PTD6/USB_ALTCLK/TX1
PTA5
PTA6
PTA7/INP2+
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
100 LQFP
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTB0
PTB1/BLMS
VSSA
PTD1/CMPP2/RESET
PTD0/BKGD/MS
VREFL
INP1-
OUT1
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
TRIOUT1/DADP2-
VINP1
VINN1/DADM2
INP2-
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE/FB_CS0
OUT2
Figure 3. 100-Pin LQFP
8
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Pinouts and Pin Assignments
2.3
81-Pin MAPBGA
The following figure shows the 81-pin MAPBGA pinout configuration.
1
2
3
4
5
6
7
8
9
IRO
PTG0
PTF6
USB_DP
VBUS
VUSB33
PTF4
PTF3
PTE4
A
B
C
D
E
F
A
B
C
D
E
F
PTF7
PTA4
PTA0
PTA5
PTG1
PTA6
USB_DM
PTA1
PTF5
PTF2
PTE7
PTE6
PTA3
VDD1
VSS1
PTB6
PTC4
PTF1
PTE5
PTD5
PTD2
PTB7
PTC0
PTD0
PTF0
PTE2
PTD7
PTD3
PTC7
PTC1
PTC5
PTE3
PTE1
PTE0
PTD6
PTD4
PTC2
PTC6
INP1-
PTA7
PTB0
PTB1
PTA2
OUT1
VINP1
DADP0
DADM0
VINN1
TRIOUT1
DACO
DADM1
OUT2
VDD2
VSS2
VDD3
VSS3
VREFO
PTC3
INP2-
TRIOUT2
DADP1
VINN2
VINP2
G
H
J
G
H
J
VSSA
VREFL
VREFH
VDDA
PTB2
PTB3
PTD1
PTB4
PTB5
1
2
3
4
5
6
7
8
9
Figure 4. 81-Pin MAPBGA
Freescale Semiconductor
9
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Pinouts and Pin Assignments
2.4
80-Pin LQFP
The following figure shows the 80-pin LQFP pinout configuration.
PTA0/FB_D2/SS1
IRO
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTE4/CMPP3/TPMCLK/IRQ
PTE3/KBI2P6/FB_AD8
2
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4/INP1+
3
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
4
5
6
PTA5
PTA6
PTA7/INP2+
7
8
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
9
PTB0
PTB1/BLMS
VSSA
10
11
12
13
14
15
16
17
18
19
20
80-Pin LQFP
VREFL
PTD0/BKGD/MS
INP1-
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
OUT1
TRIOUT1/DADP2-
VINP1
VINN1DADM2
INP2-
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
OUT2
Figure 5. 80-Pin LQFP
10
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Pinouts and Pin Assignments
2.5
Pin Assignments
Table 3. Package Pin Assignments
Package
Default
Function
Alternate
Alternate Alternate
Composite Pin Name
1
2
3
B2
C1
C6
C5
C7
B7
C8
D9
E9
H3
D2
D1
C3
E2
E3
D3
E1
F1
F2
1
2
B2
A1
—
1
PTA0
IRO
FB_D2
—
SS1
—
—
—
PTA0/FB_D2/SS1
IRO
2
3
—
—
—
—
—
3
PTG5
PTG6
PTG7
PTH0
PTH1
PTA1
FB_RW
FB_AD19
FB_AD18
FB_OE
FB_D0
KBI1P0
KBI1P1
KBI1P2
INP1+
—
—
—
PTG5/FB_RW
PTG6/FB_AD19
PTG7/FB_AD18
PTH0/FB_OE
PTH1/FB_D0
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4/INP1+
PTA5
4
—
—
—
5
—
—
—
6
—
—
—
7
—
—
—
8
C4
D5
D6
C1
C2
C3
D2
D3
D4
J1
TX1
RX1
FB_D6
—
FB_D1
ADP4
ADP5
—
9
4
PTA2
10
11
12
13
14
15
16
17
18
19
5
PTA3
6
PTA4
7
PTA5
—
—
8
PTA6
—
—
—
PTA6
9
PTA7
INP2+
—
—
—
PTA7/INP2+
PTB0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PTB0
PTB1
VSSA
VREFL
INP1-
OUT1
DADP2
VINP1
DADM2
INP2-
OUT2
DACO
DADP3
VINP2
DADM3
—
—
BLMS
—
—
—
PTB1/BLMS
VSSA
—
—
J2
—
—
—
VREFL
D1
E1
F2
F1
E2
F3
E3
G2
G3
H4
G4
—
—
—
INP1-
G2 20
G1 21
—
—
—
OUT1
TRIOUT1
—
—
—
DADP2/TRIOUT1
VINP1
H1
H2
F3
22
23
24
—
—
VINN1
—
—
—
DADM2/VINN1
INP2-
—
—
G3 25
—
—
—
OUT2
L2
L1
K1
K2
26
27
28
29
—
—
—
DACO
TRIOUT2
—
—
—
DADP3/TRIOUT2
VINP2
—
—
VINN2
—
—
DADM3/VINN2
Freescale Semiconductor
11
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Pinouts and Pin Assignments
Package
Table 3. Package Pin Assignments
Default
Function
Alternate
Alternate Alternate
Composite Pin Name
1
2
3
J1
J2
L4
K3
L3
L5
L6
H6
L8
L7
D6
30
31
32
33
34
35
36
37
38
39
40
G1
H1
G5
H3
H2
J3
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
—
—
—
—
—
—
40
41
42
43
44
45
46
47
48
49
DADP0
DADM0
VREFO
DADP1
DADM1
VREFH
VDDA
VSS2
PTB2
PTB3
VDD2
PTB4
PTB5
PTB6
PTB7
PTH2
PTH3
PTH4
PTH5
PTH6
PTH7
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTD0
PTD1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DADP0
DADM0
—
VREFO
—
DADP1
—
DADM1
—
VREFH
J4
—
VDDA
F4
J5
—
VSS2
EXTAL1
XTAL1
—
PTB2/EXTAL1
J6
PTB3/XTAL1
E4
J8
VDD2
L11 41
L10 42
EXTAL2
XTAL2
KBI1P3
KBI1P4
RGPIOP2
RGPIOP3
RGPIOP4
RGPIOP5
RGPIOP6
RGPIOP7
MOSI2
MISO2
KBI1P5
KBI1P6
KBI1P7
KBI2P0
KBI2P1
KBI2P2
BKGD
CMPP2
PTB4/EXTAL2
J9
PTB5/XTAL2
K5
K6
J7
J6
J5
K4
J4
J3
43
44
45
46
47
48
49
50
G6
F7
—
RGPIOP0 FB_AD17
RGPIOP1 FB_AD0
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTH2/RGPIOP2/FB_D7
PTH3/RGPIOP3/FB_D6
PTH4/RGPIOP4/FB_D5
PTH5/RGPIOP5/FB_D4
PTH6/RGPIOP6/FB_D3
PTH7/RGPIOP7/FB_D2
PTC0/MOSI2/FB_OE/FB_CS0
PTC1/MISO2/FB_D0/FB_AD1
PTC2/KBI1P5/SPSCK2/ADP6
PTC3/KBI1P6/SS2/ADP7
PTC4/KBI1P7/CMPP0/ADP8
PTC5/KBI2P0/CMPP1/ADP9
PTC6/KBI2P1/PRACMPO/ADP10
PTC7/KBI2P2/CLKOUT/ADP11
PTD0/BKGD/MS
FB_D7
FB_D6
FB_D5
FB_D4
FB_D3
FB_D2
FB_OE
FB_D0
SPSCK2
SS2
—
—
—
—
—
—
—
—
—
—
—
J10 51
J11 52
G7
G8
G9
H5
H6
H8
H9
F8
H7
J7
FB_CS0
FB_AD1
ADP6
ADP7
ADP8
ADP9
J9
K7
K9
53
54
55
CMPP0
CMPP1
K10 56
K11 57
PRACMPO ADP10
F8
L9
K8
58
59
60
CLKOUT
MS
ADP11
—
RESET
—
PTD1/CMPP2/RESET
12
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Pinouts and Pin Assignments
Table 3. Package Pin Assignments
Package
Default
Function
Alternate
Alternate Alternate
Composite Pin Name
1
2
3
H11 61
H10 62
E7
E8
50
51
PTD2
PTD3
USB_ALTCLK RGPIOP8 TPM1CH0
USB_PULLUP
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
RGPIOP9 TPM1CH1 PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
(D+)
H9
G9 64
J8 65
63
F9
D7
E9
52
53
54
PTD4
PTD5
PTD6
SDA
RGPIOP10 TPM1CH2
RGPIOP11 TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD5/SCL/RGPIOP11/TPM1CH3
PTD6/USB_ALTCLK/TX1
SCL
USB_ALTCLK
TX1
RX1
—
—
USB_PULLUP
(D+)
G10 66
D8
55
PTD7
PTD7/USB_PULLUP(D+) /RX1
G11 67
F10 68
F11 69
D9
—
56
—
—
—
—
57
58
59
60
61
62
PTE0
PTJ0
PTJ1
PTJ2
PTJ3
PTE1
PTE2
PTE3
PTE4
VSS3
VDD3
KBI2P3
FB_AD2
FB_AD3
FB_AD4
RGPIOP12
KBI2P4
KBI2P5
KBI2P6
CMPP3
—
FB_ALE
—
FB_CS1
PTE0/KBI2P3/FB_ALE/FB_CS1
PTJ0/FB_AD2
—
—
—
—
—
—
PTJ1/FB_AD3
F9
70
—
—
PTJ2/FB_AD4
E10 71
E11 72
D11 73
D10 74
—
FB_AD5
PTJ3/RGPIOP12/FB_AD5
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE3/KBI2P6/FB_AD8
PTE4/CMPP3/TPMCLK/IRQ
VSS3
C9
C8
B9
A9
F5
E5
RGPIOP13 FB_AD6
RGPIOP14 FB_AD7
FB_AD8
TPMCLK
—
—
IRQ
—
C9
H8
D8
75
76
77
—
—
—
VDD3
USB_
SESSVLD
B8
78
C7
C6
63
64
PTE5
PTE6
FB_D7
TX2
RX2
PTE5/FB_D7/USB_SESSVLD/TX2
PTE6/FB_RW/USB_SESSEND/RX2
USB_
SESSEND
C10 79
C11 80
FB_RW
USB_
VBUSVLD
B6
B8
B7
65
66
67
PTE7
PTF0
PTF1
TPM2CH3
TPM2CH2
—
—
PTE7/USB_VBUSVLD/TPM2CH3
PTF0/USB_ID/TPM2CH2
B9
81
USB_ID
RX2
USB_DP_D
OWN
B10 82
B11 83
TPM2CH1
PTF1/RX2/USB_DP_DOWN/TPM2CH1
USB_DM_
DOWN
C5
68
PTF2
TX2
TPM2CH0
PTF2/TX2/USB_DM_DOWN/TPM2CH0
A11 84
A10 85
—
—
—
—
—
—
—
—
PTJ4
PTJ5
PTJ6
PTJ7
RGPIOP15
FB_AD15
FB_AD14
FB_AD13
FB_AD16
—
—
—
—
PTJ4/RGPIOP15/FB_AD16
PTJ5/FB_AD15
—
—
—
B6
A9
86
87
PTJ6/FB_AD14
PTJ7/FB_AD13
Freescale Semiconductor
13
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Pinouts and Pin Assignments
Package
Table 3. Package Pin Assignments
Default
Function
Alternate
Alternate Alternate
Composite Pin Name
1
2
3
A8
A7
A6
B5
A5
A4
A3
B4
H4
D4
A1
A2
88
89
90
91
92
93
94
95
96
97
98
99
—
A8
A7
B5
A6
B4
A4
A5
F6
E6
A3
B1
—
69
70
71
72
FB_AD12
PTF3
—
SCL
SDA
KBI2P7
—
—
FB_D5
FB_D4
FB_D3
—
—
FB_AD12
PTF3/SCL/FB_D5/FB_AD11
PTF4/SDA/FB_D4/FB_AD10
PTF5/KBI2P7/FB_D3/FB_AD9
VUSB33
FB_AD11
PTF4
FB_AD10
PTF5
FB_AD9
VUSB33
—
—
—
—
—
—
—
—
—
73 USB_DM
—
—
USB_DM
74
75
76
77
78
79
80
USB_DP
VBUS
VSS1
VDD1
PTF6
—
—
USB_DP
—
—
VBUS
—
—
VSS1
—
—
VDD1
MOSI1
MISO1
SPSCK1
—
PTF6/MOSI1
PTF7
—
PTF7/MISO1
B1 100 A2
PTG0
—
PTG0/SPSCK1
USB_
SESSEND
F4
C4
—
—
A1
—
—
—
PTG1
PTG2
—
—
—
—
PTG1/USB_SESSEND
PTG2/USB_DM_DOWN
USB_DM_
DOWN
USB_DP_
DOWN
B3
C2
—
—
—
—
—
—
PTG3
PTG4
—
—
—
—
PTG3/USB_DP_DOWN
PTG4/USB_SESSVLD
USB_SESSVLD
14
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
3
Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the
MCF51MM256/128 microcontroller, including detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These
specifications will, however, be met for production silicon. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
3.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 4. Parameter Classifications
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the remaining tables in this
section.
Freescale Semiconductor
15
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 5. Absolute Maximum Ratings
#
Rating
Symbol
Value
Unit
1
2
3
Supply voltage
VDD
IDD
VIn
–0.3 to +3.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
Instantaneous maximum current
4
5
ID
± 25
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
°C
1
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two
resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of
VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current
greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power.
Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either V or V ).
SS
DD
3.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take
P
into account in power calculations, determine the difference between actual pin voltage and V or
I/O
SS
V
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy
DD
loads), the difference between pin voltage and V or V will be very small.
SS
DD
16
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 6. Thermal Characteristics
Rating
#
Symbol
Value
Unit
Operating temperature range (packaged):
1
TA
°C
MCF51MM256
MCF51MM128
–40 to 105
–40 to 105
150
2
3
TJM
Maximum junction temperature
°C
Thermal resistance1,2,3,4
Single-layer board — 1s
θJA
°C/W
104-pin MBGA
100-pin LQFP
81-pin MBGA
80-pin LQFP
67
53
67
53
Thermal resistance1, 2, 3, 4
Four-layer board — 2s2p
4
θJA
°C/W
104-pin MBGA
100-pin LQFP
81-pin MBGA
80-pin LQFP
39
41
39
39
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2
3
4
Junction to Ambient Natural Convection
1s — Single layer board, one signal layer
2s2p — Four layer board, 2 signal and 2 power layers
The average chip-junction temperature (T ) in °C can be obtained from:
J
T = T + (P × θ )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P = P + P
D
int
I/O
P
P
= I × V , Watts — chip internal power
DD DD
= Power dissipation on input and output pins — user determined
int
I/O
For most applications, P << P and can be neglected. An approximate relationship between P and T
I/O
int
D
J
(if P is neglected) is:
I/O
P = K ÷ (T + 273°C)
Eqn. 2
D
J
Freescale Semiconductor
17
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Solving Equation 1 and Equation 2 for K gives:
2
K = P × (T + 273°C) + θ × (P )
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by
D
A
D
J
solving Equation 1 and Equation 2 iteratively for any value of T .
A
3.4
ESD Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS
circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification
tests are performed to ensure that these devices can withstand exposure to reasonable levels of static
without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade
Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the
device specification requirements. Complete dc parametric and functional testing is performed per the
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
Table 7. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Series Resistance
R1
C
1500
100
3
Ω
pF
—
Ω
Human Body
Storage Capacitance
Number of Pulse per pin
Series Resistance
—
R1
C
0
Machine
Latch-up
Storage Capacitance
200
3
pF
—
V
Number of Pulse per pin
Minimum input voltage limit
Maximum input voltage limit
—
—
—
–2.5
7.5
V
Table 8. ESD and Latch-Up Protection Characteristics
#
Rating
Symbol
Min
Max
Unit
C
1
2
3
4
Human Body Model (HBM)
Machine Model (MM)
VHBM
VMM
VCDM
ILAT
±2000
±200
±500
±100
—
—
—
—
V
V
T
T
T
T
Charge Device Model (CDM)
Latch-up Current at TA = 125°C
V
mA
18
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
3.5
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
Table 9. DC Characteristics
Num
Symbol
Characteristic
Operating Voltage
Condition
Min
Typ1
Max
Unit
C
1
2
—
—
1.82
—
3.6
V
—
VOH
Output high voltage
All I/O pins, low-drive strength
1.8 V, ILoad VDD
= –600 μA 0.5
–
—
—
V
C
All I/O pins, high-drive strength
2.7 V, ILoad VDD
= –10 mA 0.5
–
–
–
—
—
—
—
—
—
V
V
V
P
T
2.3 V, ILoad VDD
= –6 mA
0.5
1.8V, ILoad
–3 mA
=
VDD
0.5
C
3
4
IOHT
Output high current
Output low voltage
Max total IOH for all ports
—
—
—
—
—
100
0.5
mA
V
D
C
VOL
All I/O pins, low-drive strength
1.8 V, ILoad
= 600 μA
All I/O pins, high-drive strength
2.7 V, ILoad
= 10 mA
—
—
—
—
—
—
—
—
0.5
0.5
0.5
100
V
V
P
T
2.3 V, ILoad
= 6 mA
1.8 V, ILoad
= 3 mA
V
C
D
Max total IOL for all
ports
5
6
IOLT
VIH
Output low current
Input high voltage
—
mA
all digital inputs
0.70 x
VDD
VDD > 2.7 V
VDD > 1.8 V
—
—
—
—
V
V
P
C
0.85 x
VDD
Freescale Semiconductor
19
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 9. DC Characteristics (continued)
Num
Symbol
Characteristic
all digital inputs
Condition
Min
Typ1
Max
Unit
C
7
VIL
Input low voltage
0.35 x
VDD
VDD > 2.7 V
VDD >1.8 V
—
—
—
—
—
—
—
—
V
V
P
C
C
P
P
P
0.30 x
VDD
0.06 x
VDD
8
9
Vhys
|IIn|
Input hysteresis
all digital inputs
—
mV
μA
μA
all input only pins VIn = VDD or
(Per pin) VSS
0.25
(TBD)
Input leakage current
—
—
Hi-Z (off-state) leakage
current
all input/output VIn = VDD or
(per pin) VSS
10
|IOZ|
0.25
0.5
Leakage current for analog
output pins (DACO, VREFO,
and OUTx, TRIOUTx)
all input/output VIn = VDD or
11
12
|IOZ|
—
—
μA
(per pin)
VSS
all digital inputs,
when enabled
RPU
Pull-up resistors
—
—
17.5
17.5
—
—
52.5
52.5
kΩ
kΩ
P
P
13
14
RPD
IIC
Internal pull-down resistors3
DC injection current 4, 5, 6
Single pin limit
V
SS > VIN
VDD
>
–0.2
—
0.2
5
mA
D
Total MCU limit, includes sum of all stressed pins
VSS > VIN
>
–5
—
mA
D
VDD
15
16
17
18
CIn
Input Capacitance, all pins
RAM retention voltage
POR re-arm voltage7
POR re-arm time
—
—
—
—
—
—
—
0.6
1.4
—
8
pF
V
C
C
C
D
VRAM
VPOR
tPOR
1.0
1.79
—
0.9
10
V
μs
Low-voltage detection
threshold —
8
19
VLVDH
VDD falling
VDD rising
VDD falling
VDD rising
high range9
—
—
2.11
2.16
2.16
2.21
2.22
2.27
V
V
P
P
Low-voltage detection
threshold —
20
VLVDL
low range14
—
—
1.80
1.86
1.82
1.90
1.91
1.99
V
V
P
P
20
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 9. DC Characteristics (continued)
Num
Symbol
Characteristic
Condition
Min
Typ1
Max
Unit
C
Low-voltage warning
21
VLVWH threshold —
high range14
VDD falling
—
—
2.36
2.36
2.46
2.46
2.56
2.56
V
V
P
P
VDD rising
VDD falling
Low-voltage warning
22
VLVWL threshold —
low range14
—
2.11
2.16
2.22
V
P
VDD rising
—
—
—
2.16
—
2.21
50
2.27
—
V
mV
V
P
C
P
23
24
Vhys
VBG
Low-voltage inhibit reset/recover hysteresis14
Bandgap Voltage Reference10
1.145
1.17
1.195
1
2
3
Typical values are measured at 25°C. Characterized, not tested
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL
.
Measured with VIn = VDD
.
4
5
All functional non-supply pins are internally clamped to VSS and VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values
for positive and negative clamp voltages, then use the larger of the two values.
6
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive
injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of
regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is
not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption).
Maximum is highest voltage that POR is guaranteed.
7
8
Run at 1 MHz bus frequency
9
Low voltage detection and warning limits measured at 1 MHz bus frequency.
Factory trimmed at VDD = 3.0 V, Temp = 25°C
10
Freescale Semiconductor
21
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
3.6
Supply Current Characteristics
Table 10. Supply Current Characteristics
Bus
Freq
Temp
(°C)
#
Symbol
Parameter
VDD (V)
Typ1
Max
Unit
C
Run
supply
current
FEI mode
All modules ON
1
RIDD
25.165
MHz
–40 to
25
3
3
3
3
3
43
43
48
48
—
—
—
mA
mA
mA
mA
mA
P
P
T
T
T
25.165
MHz
105
–40 to
105
20 MHz
8 MHz
1 MHz
31.6
15.4
2.9
–40 to
105
–40 to
105
Run
2
RIDD
supply
current
FEI mode; All modules OFF
25.165
MHz
–40 to
105
3
3
3
3
28.1
23.2
12.3
2.4
29.6
—
mA
mA
mA
mA
C
T
T
T
–40 to
105
20 MHz
8 MHz
1 MHz
–40 to
105
—
–40 to
105
—
Run
3
RIDD
supply
current
LPS=0; All modules OFF
16 kHz
FBILP
–40 to
105
3
3
TBD
TBD
—
—
μA
μA
T
T
16 kHz
FBELP
–40 to
105
Run
RIDD
4
supply
current
LPS=1, all modules OFF
16 kHz
FBELP
3
3
TBD
TBD
—
—
μA
μA
0 to 70
T
T
16 kHz
FBELP
–40 to
105
22
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 10. Supply Current Characteristics (continued)
Bus
Freq
Temp
(°C)
#
Symbol
Parameter
VDD (V)
Typ1
Max
Unit
C
Waitmode
supply
FEI mode, all modules OFF
WIDD
5
current
25.165
MHz
–40 to
105
3
3
3
3
5
—
—
—
—
mA
mA
mA
mA
C
T
T
T
–40 to
105
20 MHz
8 MHz
1 MHz
TBD
TBD
TBD
–40 to
105
–40 to
105
Stop2
mode
supply
current
S2IDD
6
–40 to
25
N/A
3
0.410
0.640
µA
P
N/A
N/A
N/A
3
3
3
3.5
10
21
10
20
µA
µA
µA
70
85
C
C
P
31.5
105
–40 to
25
N/A
2
0.410
0.640
µA
C
N/A
N/A
N/A
2
2
2
3.4
9.5
20
9
µA
µA
µA
70
85
C
C
C
18
30
105
Stop3
mode
supply
current
S3IDD
7
No clocks active
–40 to
25
N/A
3
0.650
1.2
µA
P
N/A
N/A
N/A
3
3
3
7.1
20
37
18
28
63
µA
µA
µA
70
85
C
C
P
105
–40 to
25
N/A
2
0.400
0.900
µA
C
N/A
N/A
N/A
2
2
2
7.1
18
33
16
26
59
µA
µA
µA
70
85
C
C
C
105
Freescale Semiconductor
23
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Table 11. Typical Stop Mode Adders
Temperature (°C)
#
Parameter
Condition
Units
C
-40
25
70
85
105
1
2
LPO
—
50
75
100
750
150
850
250
nA
nA
D
D
600
650
1000
EREFSTEN
RANGE = HGO = 0
(TBD) (TBD) (TBD) (TBD) (TBD)
3
4
5
6
IREFSTEN1
TOD
—
68
50
70
75
77
100
123
23
86
150
135
33
120
250
170
65
µA
nA
µA
µA
T
D
T
T
Does not include clock source current
LVDSE = 1
LVD1
114
18
115
20
ACMP1
Not using the bandgap (BGBE = 0)
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0)
7
8
ADC1
DAC1
75
85
100
500
115
500
165
500
µA
µA
T
T
High power mode; no load on DACO
500
500
1
Not available in stop2 mode.
24
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Figure 6. Stop IDD versus Temperature
3.7
PRACMP Electricals
Table 12. PRACMP Electrical Specifications
#
Characteristic
Supply voltage
Symbol
Min
Typical
Max
Unit
C
1
2
3
VPWR
IDDACT1
IDDACT2
1.8
—
—
—
—
3.6
60
40
V
P
C
C
Supply current (active) (PRG enabled)
Supply current (active) (PRG disabled)
μA
μA
—
Supply current (ACMP and PRG all
disabled)
4
IDDDIS
—
—
2
nA
D
5
6
7
8
9
Analog input voltage
VAIN
VAIO
VH
VSS – 0.3
—
5
VDD
40
V
—
T
Analog input offset voltage
Analog comparator hysteresis
Analog input leakage current
Analog comparator initialization delay
—
3.0
—
mV
mV
nA
μs
—
—
—
20.0
1
T
IALKG
tAINIT
D
T
—
1.0
Freescale Semiconductor
25
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 12. PRACMP Electrical Specifications
#
Characteristic
Symbol
Min
Typical
Max
Unit
C
10 Programmable reference generator inputs
VIn2(VDD25
)
1.8
—
2.75
V
—
Programmable reference generator setup
delay
11
tPRGST
Vstep
—
1
1
—
0.25
Vin
µs
LSB
V
D
D
P
Programmable reference generator step
size
12
–0.25
VIn/32
Programmable reference generator voltage
range
13
Vprgout
—
3.8
12-bit DAC Electricals
Table 13. DAC 12LV Operating Requirements
#
Characteristic
Supply voltage
Symbol
Min
Max
Unit
C
Notes
1
2
3
VDDA
VDACR
TA
1.8
1.15
–40
3.6
3.6
105
V
V
P
C
C
Reference voltage
Temperature
°C
A small load capaci-
tance (47 pF) can
improve the band-
width performance of
the DAC.
4
5
Output load capacitance
Output load current
CL
—
—
100
1
pF
C
C
IL
mA
26
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 14. DAC 12-Bit Operating Behaviors
#
Characteristic
Resolution
Symbol
Min
Max
Unit
C
Notes
1
N
C
12
12
bit
µA
2
3
Supply current low-power mode
Supply current high-power mode
IDDA_DACLP
IDDA_DACHP
50
100
C
C
500
(TBD)
120
µA
µs
Full-scale Settling time
(±0.5 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
low-power mode
200
(TBD)
4
5
TsFSLP
—
—
C
C
Full-scale Settling time
(±0.5 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
high-power mode
TsFSHP
TsC-CLP
30
5
µs
µs
Code-to-code Settling time
(±0.5 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
6
7
—
C
C
low-power mode
Code-to-code Settling time
(±0.5 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
TsC-CHP
1
—
µs
(TBD)
high-power mode
DAC output voltage range low
(high-power mode, no load, DAC
set to 0)
100
8
9
Vdacoutl
—
mV
mV
C
C
(TBD)
DAC output voltage range high
(high-power mode, no load, DAC
set to 0x0FFF)
Vdacouth
V
DAC
—
-100
R
10
11
Integral non-linearity error
INL
C
C
—
—
± 10
± 1
LSB
LSB
Differential non-linearity error
VDACR is > 2.4 V
DNL
%FS
R
12
13
14
Offset error
Gain error
EO
EG
—
—
C
C
C
± 0.5
± 0.5
(TBD)
%FS
R
Power supply rejection ratio
VDD ≥ 2.4 V
PSRR
—
60
dB
Temperature drift of offset voltage
(DAC set to 0x0800)
See Typical
Drift figure
that follows.
15
16
Tco
Ac
—
—
C
C
2(TBD)
TBD
mV
Offset aging coefficient
µV/yr
Figure 7. Offset at Half Scale vs Temperature
Freescale Semiconductor
27
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
3.9
ADC Characteristics
Table 15. 16-bit ADC Operating Conditions
#
Symb
Characteristic
Conditions
Min
Typ1
Max
Unit
C
Comment
1
VDDAD Supply voltage Absolute
1.8
—
3.6
V
D
Delta to VDD
2
3
ΔVDDAD
-100
-100
0
0
+100
+100
mV
mV
D
D
2
(VDD-VDDAD
)
Delta to VSS
(VSS-VSSAD
ΔVSSAD Ground voltage
2
)
4
5
6
VREFH Ref Voltage High
VREFL Ref Voltage Low
1.13
VDDAD VDDAD
VSSAD VSSAD
V
V
V
D
D
D
VSSAD
VREFL
VADIN
CADIN
Input Voltage
—
VREFH
Input
Capacitance
16-bit modes
8/10/12-bit modes
8
4
10
5
7
8
—
—
pF
C
C
RADIN Input Resistance
2
5
kΩ
28
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 15. 16-bit ADC Operating Conditions (continued)
#
Symb
Characteristic
Conditions
Min
Typ1
Max
Unit
C
Comment
External to
MCU
Assumes
ADLSMP=0
Analog Source
Resistance
9
RAS
16-bit mode
ADCK > 8 MHz
C
—
—
0.5
kΩ
f
4 MHz < fADCK < 8
MHz
—
—
—
—
—
—
1
2
1
kΩ
kΩ
kΩ
C
C
C
fADCK < 4 MHz
13/12-bit mode
fADCK > 8 MHz
4 MHz < fADCK < 8
MHz
—
—
—
—
—
—
2
5
2
kΩ
kΩ
kΩ
C
C
C
f
ADCK < 4 MHz
11/10-bit mode
fADCK > 8 MHz
4 MHz < fADCK < 8
MHz
—
—
—
—
—
—
—
—
5
10
5
kΩ
kΩ
kΩ
kΩ
C
C
C
C
fADCK < 4 MHz
9/8-bit mode
f
ADCK > 4 MHz
fADCK < 4 MHz
10
High Speed
(ADLPC=0,
ADHSC=1)
ADCConversion
Clock Freq.
10
fADCK
1.0
1.0
1.0
—
—
—
8.0
5.0
2.5
MHz
MHz
MHz
D
D
D
High Speed
(ADLPC=0,
ADHSC=0)
Low Power
(ADLPC=1,
ADHSC=1)
1
2
Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and
are not tested in production.
DC potential difference.
Freescale Semiconductor
29
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z
ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
Z
AS
leakage
due to
input
ADC SAR
ENGINE
R
R
AS
ADIN
protection
+
V
ADIN
–
C
AS
V
+
AS
–
R
R
R
ADIN
ADIN
ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C
ADIN
Figure 8. ADC Input Impedance Equivalency Diagram
30
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 16. 16-bit SAR ADC Characteristics full operating range
(V = V , > 1.8, V = V ≤ 8 MHz)
REFH
DDAD
REFL
SSAD
Characteristic
Conditions1
Symb
Min
Typ2
Max
Unit
C
Comment
ADLPC=1, ADHSC=0
—
—
—
—
—
—
—
215
470
610
0.01
2.4
—
—
—
—
—
—
—
Supply Current ADLPC=0, ADHSC=0
ADLPC=0, ADHSC=1
ADLSMP=0
ADCO=1
IDDAD
IDDAD
μA
μA
T
Supply Current Stop, Reset, Module Off
C
ADLPC=1, ADHSC=0
ADC
Asynchronous
Clock Source
ADLPC=0, ADHSC=0
5.2
tADACK
1/fADACK
=
fADACK
MHz
P
ADLPC=0, ADHSC=1
6.2
Sample Time
See Block Guide for sample times
Conversion
Time
See Block Guide for conversion times
32x
Total
Unadjusted
Error
Hardware
Averaging
(AVGE = %1
AVGS = %11)
16-bit differential mode
TUE
—
—
±16
±20
+48/-40
+56/-28
LSB3
T
16-bit single-ended mode
13-bit differential mode
12-bit single-ended mode
—
—
±1.5
±1.75
±3.0
±3.5
T
T
T
T
T
T
T
T
T
T
T
11-bit differential mode
10-bit single-ended mode
—
—
±0.7
±0.8
±1.5
±1.5
9-bit differential mode
8-bit single-ended mode
—
—
±0.5
±0.5
±1.0
±1.0
Differential
Non-Linearity
16-bit differential mode
DNL
—
—
±2.5
±2.5
+5/-3
+5/-3
LSB2
16-bit single-ended mode
13-bit differential mode
12-bit single-ended mode
—
—
±0.7
±0.7
±1
±1
11-bit differential mode
10-bit single-ended mode
—
—
±0.5
±0.5
±0.75
±0.75
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
Integral
Non-Linearity
16-bit differential mode
INL
—
—
±6.0
±10.0
±16.0
±20.0
LSB2
16-bit single-ended mode
13-bit differential mode
12-bit single-ended mode
—
—
±1.0
±1.0
±2.5
±2.5
11-bit differential mode
10-bit single-ended mode
—
—
±0.5
±0.5
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
—
—
±0.3
±0.3
±0.5
±0.5
Freescale Semiconductor
31
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 16. 16-bit SAR ADC Characteristics full operating range
(V = V , > 1.8, V = V ≤ 8 MHz) (continued)
REFH
DDAD
REFL
SSAD
Characteristic
Conditions1
Symb
Min
Typ2
Max
Unit
C
Comment
Zero-Scale
Error
16-bit differential mode
16-bit single-ended mode
—
—
±4.0
±4.0
+32/-24
+24/-16
EZS
LSB2
T
VADIN = VSSAD
13-bit differential mode
12-bit single-ended mode
—
—
±0.7
±0.7
±2.5
±2.0
T
T
T
T
T
T
T
11-bit differential mode
10-bit single-ended mode
—
—
±0.4
±0.4
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
Full-Scale
Error
16-bit differential mode
16-bit single-ended mode
—
—
+10/0
+14/0
+42/-2
+46/-2
EFS
LSB2
VADIN = VDDAD
13-bit differential mode
12-bit single-ended mode
—
—
±1.0
±1.0
±3.5
±3.5
11-bit differential mode
10-bit single-ended mode
—
—
±0.4
±0.4
±1.5
±1.5
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
Quantization
Error
16-bit modes
EQ
—
—
-1 to 0
—
—
LSB2
D
C
<13-bit modes
±0.5
16-bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
12.8
12.7
12.6
12.5
11.9
14.2
13.8
13.6
13.3
12.5
—
—
—
—
—
Avg=1
Effective
Number of Bits
Fin
=
ENOB
Bits
Fsample/100
16-bit single-ended mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
—
—
—
—
—
13.2
12.8
12.6
12.3
11.5
—
—
—
—
—
D
Signal to Noise
plus Distortion
SINAD = 6.02 ⋅ ENOB + 1.76
See ENOB
SINAD
THD
dB
dB
16-bit differential mode
Avg=32
C
D
—
—
-91.5
-85.5
-74.3
—
Total Harmonic
Distortion
Fin
=
Fsample/100
16-bit single-ended mode
Avg=32
32
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 16. 16-bit SAR ADC Characteristics full operating range
(V = V , > 1.8, V = V ≤ 8 MHz) (continued)
REFH
DDAD
REFL
SSAD
Characteristic
Conditions1
Symb
Min
Typ2
Max
Unit
C
Comment
16-bit differential mode
Avg=32
C
Spurious Free
Dynamic
Range
75.0
—
92.2
86.2
—
—
Fin
sample/100
=
SFDR
dB
F
16-bit single-ended mode
Avg=32
D
D
I
In = leakage
current
(refer to DC
characteristics
)
Input Leakage
Error
all modes
EIL
IIn * RAS
mV
—
—
—
1.646
1.769
701.2
—
—
—
Temp Sensor
Slope
mV/×
C
–40°C – 25°C
25°C – 125°C
m
C
C
Temp Sensor
Voltage
25°C
VTEMP25
mV
1
2
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference only
and are not tested in production.
1 LSB = (VREFH - VREFL)/2N
3
3.10 MCG and External Oscillator (XOSC) Characteristics
Table 17. MCG (Temperature Range = –40 to 105°C Ambient)
#
Rating
Internal reference startup time
Symbol
Min
Typical
Max
Unit
C
tirefst
1
—
55
100
μs
D
factory trimmed at
VDD=3.0 V and
temp=25°C
—
31.25
—
C
Average internal reference
frequency
fint_ft
2
3
kHz
user trimmed
31.25
16
—
—
—
39.0625
20
C
C
C
Low range (DRS=00)
DCO output frequency range -
trimmed
fdco_t
MHz
Mid range (DRS=01)
32
40
High range1
(DRS=10)
40
—
60
C
Resolution of trimmed DCO output with FTRIM
frequency at fixed voltage and
—
—
± 0.1
± 0.2
± 0.2
± 0.4
C
C
Δfdco_res_t
%fdco
4
without FTRIM
temperature
over voltage and
temperature
—
—
±1.0
± 2
± 1
p
Total deviation of trimmed DCO
output frequency over voltage and
temperature
Δfdco_t
%fdco
5
6
over fixed voltage
and temp range
of 0 - 70 °C
± 0.5
C
FLL2
PLL3
—
—
—
—
1
1
C
D
tfll_acquire
tpll_acquire
Acquisition time
ms
Freescale Semiconductor
33
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 17. MCG (Temperature Range = –40 to 105°C Ambient) (continued)
#
Rating
Symbol
Min
Typical
Max
Unit
C
Long term Jitter of DCO output clock (averaged over 2mS
interval) 4
CJitter
%fdco
7
—
0.02
0.2
C
fvco
8
9
VCO operating frequency
7.0
1.0
—
—
55.0
2.0
MHz
MHz
D
D
fpll_ref
PLL reference frequency range
Jitter of PLL output clock measured
Long term
fpll_jitter_625
0.5664
%fpll
%
10
—
—
D
over 625ns 5
ns
Entry6
Exit7
± 1.49
± 4.47
—
—
± 2.98
± 5.97
D
D
Dlock
Dunl
11 Lock frequency tolerance
12 Lock time
tfll_acquire+
1075(1/fint_t)
tfll_lock
FLL
—
—
—
D
s
tpll_acquire+
tpll_lock
floc_low
floc_high
PLL
—
—
—
D
D
D
1075(1/fpll_ref)
(3/5) x
fint_t
Loss of external clock minimum frequency - RANGE = 0
Loss of external clock minimum frequency - RANGE = 1
13
14
—
—
kHz
kHz
(16/5) x
fint_t
1
2
This should not exceed the maximum CPU frequency for this device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is
changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is
being used as the reference, this specification assumes it is already running.
3
4
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI)
to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are
made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via
VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
625 ns represents 5 time quanta for CAN applications, under worst-case conditions of 8 MHz CAN bus clock, 1 Mbps CAN Bus speed, and
8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the sample point of a bit
using 8 time quanta per bit.
5
6
7
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already
in lock, then the MCG may stay in lock.
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
34
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 18. XOSC (Temperature Range = –40 to 105°C Ambient)
#
Characteristic
• Low range (RANGE = 0)
Symbol
Min
Typ1
Max
Unit
flo
32
1
—
—
38.4
5
kHz
• High range (RANGE = 1),
• FEE or FBE mode 2
fhi
MHz
Oscillator crystal or resonator
(EREFS = 1, ERCLKEN = 1)
• High range (RANGE = 1),
• High gain (HGO = 1),
• FBELP mode
1
fhi
fhi
1
1
—
—
16
8
MHz
MHz
• High range (RANGE = 1),
• Low power (HGO = 0),
• FBELP mode
C1
C2
2
3
Load capacitors
See Note 3
Low range
(32 kHz to 38.4 kHz)
Feedback resistor
RF
—
—
—
—
—
10
1
MΩ
kΩ
High range
(1 MHz to 16 MHz)
Series resistor — Low range
Series resistor — High range
Low Gain (HGO = 0)
High Gain (HGO = 1)
• Low Gain (HGO = 0)
• High Gain (HGO = 1)
≥ 8 MHz
—
—
0
—
—
4
5
RS
100
RS
—
—
—
0
0
0
0
kΩ
4 MHz
10
20
1 MHz
Low range, low gain (RANGE = 0,
HGO = 0)
—
—
—
—
—
—
—
—
200
400
t
CSTL
Low range, high gain (RANGE =
0, HGO = 1)
6
Crystal start-up time 4, 5
ms
High range, low gain (RANGE = 1,
HGO = 0)
5
tCSTH
High range, high gain (RANGE =
1, HGO = 1)
15
1
2
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to
39.0625 kHz.
3
4
See crystal or resonator manufacturer’s recommendation.
This parameter is characterized and not tested on each device.
Proper PC board layout procedures must be followed to achieve specifications.
5
o
Freescale Semiconductor
35
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
3.11 Mini-FlexBus Timing Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to
interface to slave-only devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected
to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or
other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple
chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect
to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus
frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the
Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values.
Table 19. Mini-FlexBus AC Timing Specifications
Num
C
Characteristic
Frequency of Operation
Min
Max
Unit
Notes
—
—
D
T
—
39.73
—
25.1666
MHz
ns
—
MB1
MB2
MB3
MB4
MB5
Clock Period
Output Valid
Output Hold
Input Setup
Input Hold
—
20
—
—
—
—
1
ns
1
2
2
D
T
1.0
22
ns
ns
D
10
ns
1
2
Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.
Specification is valid for all MB_D[7:0].
36
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
S0
S1
S2
S3
S0
FB_CLK
MB1
MB3
FB_A[19:16]
ADDR[19:0]
MB2
ADDR[31:24]
MB5
8-bit Non-Mux’d Bus
16-bit Mux’d Bus
DATA[7:0]
FB_D[7:0]
MB4
ADDR[19:16]
FB_AD[19:16]
FB_AD[15:0]
ADDR[15:0]
DATA[15:0]
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 9. Mini-FlexBus Read Timing
S0
S1
S2
S3
S0
FB_CLK
MB1
MB3
ADDR[19:8]
FB_AD[19:8]
MB2
8-bit Non-Mux’d Bus
16-bit Mux’d Bus
ADDR[7:0]
FB_AD[7:0]
DATA[7:0]
ADDR[19:16]
FB_AD[19:16]
ADDR[15:0]
DATA[15:0]
FB_AD[15:0]
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 10. Mini-FlexBus Write Timing
3.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
Freescale Semiconductor
37
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
3.12.1 Control Timing
Table 20. Control Timing
#
Symbol
Parameter
Min
Typical1
Max
C
Unit
fBus
1
Bus frequency (tcyc = 1/fBus
)
MHz
VDD ≥ 1.8 V
DD > 2.1 V
VDD > 2.4 V
dc
dc
—
—
10
20
D
D
V
25.165
D
D
dc
—
Internal low-power oscillator
period
990
(TBD)
2
tLPO
800
1500
μs
External reset pulse width2
3
4
5
textrst
trstdrv
tMSSU
100
66 x tcyc
500
—
—
—
—
—
—
D
D
D
ns
ns
ns
(tcyc = 1/fSelf_reset
)
Reset low drive
Active background debug
mode latch setup time
Active background debug
mode latch hold time
6
7
tMSH
100
—
—
—
—
—
—
D
D
ns
ns
IRQ pulse width
•
•
Asynchronous path2
Synchronous path3
100
1.5 x tcyc
t
ILIH, tIHIL
KBIPx pulse width
8
9
•
•
Asynchronous path2
Synchronous path3
100
1.5 x tcyc
D
tILIH, IHIL
t
ns
ns
tRise, tFall
Port rise and fall time (load = 50 pF)4, Low Drive
Slew rate control
disabled (PTxSE = 0)
—
—
—
—
11
35
40
75
—
—
—
—
D
D
D
D
Slew rate control
enabled (PTxSE = 1)
Slew rate control
disabled (PTxSE = 0)
Slew rate control
enabled (PTxSE = 1)
1
2
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may
not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 105 °C.
38
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
textrst
RESET PIN
Figure 11. Reset Timing
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 12. IRQ/KBIPx Timing
3.12.2 TPM Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 21. TPM Input Timing
#
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
—
—
D
External clock frequency
External clock period
fTPMext
tTPMext
tclkh
dc
4
fBus/4
—
MHz
tcyc
tcyc
tcyc
tcyc
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
D
tclkl
—
D
tICPW
—
tTPMext
tclkh
TPMxCLK
tclkl
Figure 13. Timer External Clock
Freescale Semiconductor
39
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure 14. Timer Input Capture Pulse
3.13 SPI Characteristics
Table 22 and Figure 15 through Figure 18 describe the timing requirements for the SPI system.
Table 22. SPI Timing
No.1
Characteristic2
Operating frequency
Symbol
Min
Max
Unit
C
1
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
Hz
D
SPSCK period
2
3
4
5
6
7
Master
Slave
tSPSCK
2
4
2048
—
tcyc
tcyc
D
D
D
D
D
D
Enable lead time
Master
Slave
tLead
1/2
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
tLag
1/2
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
tSU
tSU
Master
Slave
15
15
—
—
ns
ns
tHI
tHI
Master
Slave
0
25
—
—
ns
ns
8
9
Slave access time3
ta
—
—
1
1
tcyc
tcyc
D
D
Slave MISO disable time4
tdis
40
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Table 22. SPI Timing (continued)
No.1
Characteristic2
Symbol
Min
Max
Unit
C
Data valid (after SPSCK edge)
10
Master
Slave
tv
—
—
25
25
ns
ns
D
Data hold time (outputs)
Rise time
11
12
13
Master
Slave
tHO
0
0
—
—
ns
ns
D
D
D
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
1
2
Numbers in this column identify elements in Figure 15 through Figure 18.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew
rate control disabled and high drive strength enabled for SPI output pins.
Time to data active from high-impedance state.
3
4
Hold time to high-impedance state.
SS1
(OUTPUT)
2
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
4
5
SCK
(CPOL = 1)
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN2
11
BIT 6 . . . 1
11
LSB IN
12
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 15. SPI Master Timing (CPHA = 0)
Freescale Semiconductor
41
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
SS(1)
(OUTPUT)
2
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
5
6
SCK
(CPOL = 1)
(OUTPUT)
4
7
MISO
(INPUT)
MSB IN(2)
BIT 6 . . . 1
12
BIT 6 . . . 1
LSB IN
11
MOSI
(OUTPUT)
MSB OUT(2)
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 16. SPI Master Timing (CPHA = 1)
SS
(INPUT)
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
2
SCK
(CPOL = 1)
5
4
(INPUT)
9
8
12
11
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
7
SLAVE
6
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined, but normally MSB of character just received
Figure 17. SPI Slave Timing (CPHA = 0)
42
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
SS
(INPUT)
2
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
4
5
SCK
(CPOL = 1)
(INPUT)
11
SLAVE MSB OUT
12
9
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
6
7
8
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined, but normally LSB of character just received
Figure 18. SPI Slave Timing (CPHA = 1)
3.14 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash
memory.
Program and erase operations do not require any special power sources other than the normal V supply.
DD
For more detailed information about program/erase operations, see the Memory chapter in the Reference
Manual for this device (MCF51MM256RM).
Table 23. Flash Characteristics
#
Characteristic
Symbol
Min
Typical
Max
Unit
C
Supply voltage for program/erase
-40°C to 105°C
1
—
D
Vprog/erase
VRead
fFCLK
tFcyc
1.8
1.8
150
5
3.6
3.6
V
2
3
4
5
6
7
8
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time2
—
—
V
D
D
D
P
P
P
P
200
6.67
kHz
μs
—
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
tBurst
4
tPage
4000
20,000
Mass erase time2
tMass
Program/erase endurance3
TL to TH = –40°C to + 105°C
T = 25°C
9
10,000
—
—
100,000
—
—
C
C
cycles
years
10
Data retention4
tD_ret
15
100
—
1
The frequency of this clock is controlled by a software setting.
Freescale Semiconductor
43
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
2
3
4
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating
approximate time to program and erase.
Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines
typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the
Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical
Data Retention for Nonvolatile Memory.
3.15 USB Electricals
The USB electricals for the USB On-the-Go module conform to the standards documented by the
Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.
If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the
standard or require additional information, this space would be used to communicate that information.
Table 24. Internal USB 3.3 V Voltage Regulator Characteristics
#
Characteristic
Symbol
Min
Typ
Max
Unit
C
1
2
Regulator operating voltage
VREG output
Vregin
3.9
3
—
5.5
3.6
V
V
C
P
Vregout
3.3
VUSB33 input with internal VREG
disabled
3
4
Vusb33in
IVRQ
3
3.3
0.5
3.6
—
V
C
C
VREG Quiescent Current
—
mA
44
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
3.16 VREF Electrical Specifications
Table 25. VREF Electrical Specifications
Num
Characteristic
Supply voltage
Symbol
Min
Max
Unit
C
1
2
3
4
VDDA
TA
1.80
–40
—
3.6
105
100
10
V
°C
nf
C
C
D
Temperature
Output Load Capacitance
Maximum Load
CL
—
—
mA
—
P
Voltage Reference Output with Factory
Trim. VDD = 3 V.
1.148
1.152
5
Vout
V
Temperature Drift (Vmin - Vmax across
the full temperature range)
10
(TBD)
6
7
8
Tdrift
—
—
—
mV1
ppm/year
µA
T
Aging Coefficient
Ac
I
TBD
0.10
C
C
Powered down Current (Off Mode,
VREFEN=0, VRSTEN=0)
9
Bandgap only (MODE_LV[1:0] = 00)
Low-Power buffer (MODE_LV[1:0] = 01)
I
I
—
—
75
µA
µA
T
T
10
125
Tight-Regulation buffer (MODE_LV[1:0]
= 10)
11
I
—
1.1
mA
T
12
13
14
Load Regulation MODE_LV = 10
—
DC
AC
—
—
100
TBD
—
µV/mA
mV
C
Line Regulation (Power Supply
Rejection)
C
TBD
dB
1
See typical chart below.
Table 26. VREF Limited Range Operating Requirements
#
Characteristic
Temperature
Symbol
Min
Max
Unit
C
Notes
1
TA
0
50
°C
C
Table 27. VREF Limited Range Operating Behaviors
#
Characteristic
Symbol
Min
Max
Unit
µA
C
Notes
Voltage Reference Output with
Factory Trim
1
Vout
TBD
TBD
C
Freescale Semiconductor
45
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Figure 19. Typical Output vs. Temperature
TBD
Figure 20. Typical Output vs. V
DD
46
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
3.17 TRIAMP Electrical Parameters
Table 28. TRIAMP Characteristics 1.8-3.6 V, -40°C~105°C
#
Characteristic1
Operating Voltage
Symbol
Min
Typ2
Max
Unit
C
VDD
1
1.8
—
3.6
V
C
Supply Current (IOUT=0mA, CL=0)
Low-power mode
ISUPPLY
ISUPPLY
VOS
2
3
4
—
—
—
80
TBD
TBD
± 10
μA
μA
P
P
C
Supply Current (IOUT=0mA, CL=0)
High-speed mode
350
±
Input Offset Voltage
mV
3(TBD)
Input Offset Voltage Temperature
Coefficient
αVOS
IOS
5
6
7
—
—
—
TBD
—
μV/C
pA
C
C
C
Input Offset Current
±270
TBD
±300
(TBD)
±500
(TBD)
IBIAS
Input Bias Current (0 ~ 50°C)
pA
IBIAS
VCML
VCMH
RIN
8
Input Bias Current (-40 ~ 105°C)
Input Common Mode Voltage Low
Input Common Mode Voltage High
Input Resistance
—
0
TBD
—
TBD
—
pA
V
C
D
C
Τ
T
Τ
9
VDD–1.4
10
11
12
13
—
500
—
—
—
V
—
—
5
MΩ
pF
MΩ
CIN
Input Capacitances
—
AC Input Impedance (fIN=100kHz)
50
—
|XIN|
14
15
Input Common Mode Rejection Ratio
Power Supply Rejection Ration
CMRR
PSRR
60
60
70
70
—
—
dB
dB
C
C
Slew Rate (ΔVIN=100mV) Low-power
mode
16
SR
SR
—
0.1
—
V/μs
C
Slew Rate (ΔVIN=100mV) High-speed
mode
17
18
19
—
0.15
—
1
0.5
2
—
—
—
V/μs
MHz
MHz
C
C
C
Unity Gain Bandwidth (Low-power mode)
50pF
GBW
Unity Gain Bandwidth (High-speed mode)
50pF
GBW
AV
20
21
22
DC Open Loop Voltage Gain (RL = 20 KΩ)
Load Capacitance Driving Capability
Output Resistance
—
—
—
80
—
—
50
—
dB
pF
Ω
C
C
C
CL(max)
ROUT
TBD
VDD
–
23
Output Voltage Range
triout
IOUT
0.15
—
V
C
0.15
24
25
26
Output Drive Capability
Gain Margin
—
20
45
± 1.0
—
—
mA
dB
C
T
GM
PM
—
Phase Margin
55
—
deg
C
1
All parameters are measured at 3.3 V, CL= 47 pF across temperature -40 to + 105 °C unless specified.
Freescale Semiconductor
47
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
2
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
3.18 OPAMP Electrical Parameters
Table 29. OPAMP Characteristics 1.8-3.6 V
#
Characteristics1
Symbol
Min
Typ2
Max
Unit
C
1
Operating Voltage
VDD
1.8
—
3.6
V
C
Supply Current (IOUT=0mA, CL=0) Low-power
mode
55
(TBD)
2
3
ISUPPLY
ISUPPLY
—
—
40
μA
μA
P
P
Supply Current (IOUT=0mA, CL=0)
High-speed mode
420
(TBD)
450
(TBD)
4
Input Offset Voltage
Input Offset Voltage Temperature Coefficient
Input Offset Current
VOS
αVOS
IOS
—
—
±3
1
±10
—
mV
μV/C
pA
C
C
C
C
C
T
5
6
—
± TBD
± TBD
—
± TBD
± TBD
—
7
Input Bias Current
IBIAS
VCML
VCMH
RIN
—
pA
8
Input Common Mode Voltage Low
Input Common Mode Voltage High
Input Resistance
0.1
—
V
9
—
VDD+0.1
—
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
500
—
—
MΩ
pF
T
Input Capacitances
CIN
—
10
T
AC Input Impedance (fIN=100kHz)
Input Common Mode Rejection Ratio
Power Supply Rejection Ration
Slew Rate (ΔVIN=100mV) Low-power mode
Slew Rate (ΔVIN=100mV) High speed mode
Unity Gain Bandwidth Low-power mode
Unity Gain Bandwidth High Speed mode
DC Open Loop Voltage Gain
Load Capacitance Driving Capability
Output Resistance
|XIN|
CMRR
PSRR
SR
—
TBD
65
—
MΩ
dB
T
55
60
0.1
1
—
C
C
C
C
C
C
C
C
C
C
C
T
65
—
dB
—
—
V/μs
V/μs
MHz
MHz
dB
SR
—
—
GBW
GBW
AV
0.2
1
—
—
—
—
80
—
90
—
CL(max)
ROUT
VOUT
IOUT
GM
—
100
1500
VDD-0.15
—
pF
—
—
Ω
Output Voltage Range
0.15
±0.5
20
45
—
V
Output Drive Capability
±1.0
—
mA
dB
Gain Margin
—
Phase Margin
PM
55
—
deg
C
GPAMP settling time (low-power mode)
(To < 0.1%, Vin = 2Vp-p, CL = 25pF, RL = 2k)
26
27
28
29
Tstartup
Tstartup
Tstartup
Tstartup
—
—
—
—
TBD
TBD
TBD
TBD
—
—
—
—
uS
uS
uS
uS
C
C
C
C
GPAMP settling time (low-power mode)
GPAMP settling time (high-speed mode)
(To < 0.1%, Vin = 2Vp-p, CL = 25pF, RL = 2k)
GPAMP settling time (high-speed mode)
1
All parameters are measured at 3.3 V, CL =4 7 pF across temperature -40 to + 105°C unless specified.
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
2
48
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Freescale Semiconductor
49
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Ordering Information
4
Ordering Information
This section contains ordering information for the device numbering system. See Table 2 for feature
summary by package information.
4.1
4.2
Device Numbering System
Part Numbers
Table 30. Orderable Part Number Summary
Freescale Part
Flash / SRAM
(Kbytes)
Description
Package
Temperature
Number
MCF51MM256VML
MCF51MM256VLL
MCF51MM256VMB
MCF51MM256VLK
MCF51MM128VMB
MCF51MM128VLK
MCF51MM256CML
MCF51MM256CLL
MCF51MM256CMB
MCF51MM256CLK
MCF51MM128CMB
MCF51MM128CLK
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM128 ColdFire Microcontroller
MCF51MM128 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM256 ColdFire Microcontroller
MCF51MM128 ColdFire Microcontroller
MCF51MM128 ColdFire Microcontroller
256K/32K
256K/32K
256K/32K
256K/32K
128K/32K
128K/32K
256K/32K
256K/32K
256K/32K
256K/32K
128K/32K
128K/32K
104 MAPBGA
100 LQFP
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
81 MAPBGA
80 LQFP
81 MAPBGA
80 LQFP
104 MAPBGA
100 LQFP
81 MAPBGA
80 LQFP
81 MAPBGA
80 LQFP
4.3
Package Information
Table 31. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
100
80
Low Quad Flat Package
Low Quad Flat Package
MAPBGA Package
LQFP
LQFP
LL
LK
983-03
1418
98ASS23308W
98ASS23174W
98ARH98267A
98ASA10670D
104
81
MAPBGA
MAPBGA
ML
MB
1285-02
1662-01
MAPBGA Package
4.4
Mechanical Drawings
Table 31 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MCF51MM256/128 Product Summary pages at
http://www.freescale.com.
50
Freescale Semiconductor
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Revision History
To view the latest drawing, either:
•
•
Click on the appropriate link in Table 31, or
Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate
document number (from Table 31) in the “Enter Keyword” search box at the top of the page.
®
5
Revision History
This section lists major changes between versions of the MCF51MM256 Data Sheet.
Table 32. Revision History
Revision
Date
Description
0
March/April 09 Initial Draft
• Revised to follow standard template.
• Removed extraneous headings from the TOC.
• Corrected units for Monotoncity to be blank in for the DAC specification.
• Updated ADC characteristic tables to include 16-Bit SAR in headings.
1
2
July 09
July 09
• Changed MCG (XOSC) Electricals Table - Row 2, Average Internal Reference
Frequency typical value from 32.768 to 31.25.
• Updated Thermal Characteristics table. Reinserted the 81 and 104 MapBGA devices.
• Revised the ESD and Latch-Up Protection Characeristic description to read: Latch-up
Current at TA = 125°C.
• Changed Table . DC Characteristics rows 2 and 4, to 1.8 V, ILoad = -600 mA
conditions to 1.8 V, ILoad = 600μA respectively.
• Corrected the 16-bit SAR ADC Operating Condition table Ref Voltage High Min value
to be 1.13 instead of 1.15.
• Updated the ADC electricals.
3
April 10
• Inserted the Mini-FlexBus Timing Specifications.
• Added a Temp Drift parameter to the VREF Electrical Specifications.
• Removed the S08 Naming Convention diagram.
• Updated the Orderable Part Number Summary to include the Freescale Part Number
suffixes.
• Completed the Package Description table values.
• Changed the 80LQFP package drawing from 98ARL10530D to 98ASS23174W.
MM256 uses 80LQFP12x12.
• Updated electrical characteristic data.
Freescale Semiconductor
51
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
Semiconductor was negligent regarding the design or manufacture of the part.
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.
Beijing 100022
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2009-2010. All rights reserved.
China
+86 10 5879 8000
support.asia@freescale.com
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or +1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Document Number: MCF51MM256
Rev. 3
04/2010
Non-Disclosure Agreement Required
Preliminary — Subject to Change
相关型号：
MCF51MM256CMB
low-cost, low-power, high-performance ColdFire® V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering devices.
FREESCALE
MCF51MM256CML
low-cost, low-power, high-performance ColdFire® V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering devices.
FREESCALE
MCF51MM256VLK
low-cost, low-power, high-performance ColdFire® V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering devices.
FREESCALE
MCF51MM256VLL
low-cost, low-power, high-performance ColdFire® V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering devices.
FREESCALE
MCF51MM256VMB
low-cost, low-power, high-performance ColdFire® V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering devices.
FREESCALE
MCF51MM256VML
low-cost, low-power, high-performance ColdFire® V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering devices.
FREESCALE
©2020 ICPDF网 联系我们和版权申明