MCF5208CVM166_技术文档

MCF5208EC

Rev. 0.5, 3/2006

Freescale Semiconductor

Data Sheet: Advance Information

MCF5208 ColdFire^®

Microprocessor Data Sheet

Supports MCF5207 & MCF5208

by: Microcontroller Division

Table of Contents

The MCF5207 and MCF5208 devices are

1

2

3

4

5

6

MCF5207/8 Device Configurations......................2

Ordering Information ...........................................3

Signal Descriptions..............................................3

Mechanicals and Pinouts ....................................8

Preliminary Electrical Characteristics................18

Revision History ................................................43

highly-integrated 32-bit microprocessors based on the

version 2 ColdFire microarchitecture. Both devices

contain a 16-Kbyte internal SRAM, an 8-Kbyte

configurable cache, a 2-bank SDR/DDR SDRAM

controller, a 16-channel DMA controller, up to three

UARTs, a queued SPI, a low-power management

modeule, and other peripherals that enable the MCF5207

and MCF5208 for use in industrial control and

connectivity applications. The MCF5208 device also

features a 10/100 Mbps fast ethernet controller.

This document provides detailed information on power

considerations, DC/AC electrical characteristics, and AC

timing specifications of the MCF5207 and MCF5208

microprocessors. It was written from the perspective of

the MCF5208 device. See the following section for a

summary of differences between the two devices.

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

• Preliminary

MCF5207/8 Device Configurations

1 MCF5207/8 Device Configurations

The following table compares the two devices described in this document:

Table 1. MCF5207 & MCF5208 Configurations

Module

MCF5207

MCF5208

Version 2 ColdFire Core with EMAC

(Enhanced Multiply-Accumulate Unit)

x

Core (System) Clock

up to 166.67 MHz

Peripheral and External Bus Clock

up to 83.33 MHz

(Core clock ÷ 2)

Performance (Dhrystone/2.1 MIPS)

Instruction/Data Cache

Static RAM (SRAM)

up to 159

8 Kbytes

16 Kbytes

SDR/DDR SDRAM Controller

Fast Ethernet Controller (FEC)

Low-Power Management Module

UARTs

x

—

x

3

I²C

x

QSPI

x

32-bit DMA Timers

4

Watchdog Timer (WDT)

Periodic Interrupt Timers (PIT)

Edge Port Module (EPORT)

Interrupt Controllers (INTC)

16-channel Direct Memory Access (DMA)

FlexBus External Interface

General Purpose I/O Module (GPIO)

JTAG - IEEE^®1149.1 Test Access Port

Package

x

4

x

1

x

144 LQFP

160 QFP

144 MAPBGA 196 MAPBGA

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

2

Freescale Semiconductor

Ordering Information

2 Ordering Information

Table 2. Orderable Part Numbers

Freescale Part

Number

Description

Speed

Temperature

MCF5207CAG166

MCF5207CVM166

MCF5208CAB166

MCF5208CVM166

MCF5207 RISC Microprocessor, 144 LQFP

MCF5207 RISC Microprocessor, 144 MAPBGA

MCF5208 RISC Microprocessor, 160 QFP

MCF5208 RISC Microprocessor, 196 MAPBGA

166.67 MHz

–40° to +85° C

3 Signal Descriptions

The following table lists all the MCF5208 pins grouped by function. The “Dir” column is the direction for

the primary function of the pin only. Refer to Section 4, “Mechanicals and Pinouts,” for package diagrams.

For a more detailed discussion of the MCF5208 signals, consult the MCF5208 Reference Manual

(MCF5208RM).

NOTE

In this table and throughout this document a single signal within a group is

designated without square brackets (i.e., A23), while designations for

multiple signals within a group use brackets (i.e., A[23:21]) and is meant to

include all signals within the two bracketed numbers when these numbers

are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality.

Pins that are muxed with GPIO will default to their GPIO functionality.

Table 3. MCF5207/8 Signal Information and Muxing

MCF5207

144

MCF5207

144

MCF5208

160

MCF5208

196

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

LQFP

MAPBGA

QFP

MAPBGA

Reset

RESET²

RSTOUT

—

I

82

74

J10

90

82

J14

O

M12

N14

Clock

EXTAL

XTAL

—

I

78

80

34

K12

J12

L1

86

88

40

L14

K14

N1

O

FB_CLK

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

3

Signal Descriptions

Signal Name

Table 3. MCF5207/8 Signal Information and Muxing (continued)

MCF5207

144

MCF5207

144

MCF5208

160

MCF5208

196

GPIO

Alternate 1

Alternate 2 Dir.¹

LQFP

MAPBGA

QFP

MAPBGA

Mode Selection

RCON²

—

I

144

79

C4

160

87

C3

DRAMSEL

H10

K11

FlexBus

A[23:22]

A[21:16]

—

FB_CS[5:4]

—

O

118, 117

B9, A10

126, 125

B11, A11

116–114,

112, 108,

107

C9, A11,

B10, A12,

C11, B11

124, 123,

122, 120,

116, 115

B12, A12,

A13, B13,

B14, C13

A[15:14]

A[13:11]

—

SD_BA[1:0]

SD_A[13:11]

—

O

106, 105

104–102

B12, C12

114, 113

C14, D12

D11, E10,

D12

112, 111,

110

D13, D14,

E11

A10

—

O

101

C10

109

E12

A[9:0]

SD_A[9:0]

100–91

E11, D9,

E12, F10,

F11, E9,

F12, G10,

G12, F9

108–99

E13, E14,

F11–F14,

G11–G14

D[31:16]

D[15:0]

—

SD_D[31:16]³

FB_D[31:16]³

SD_DQM[3:0]

—

O

21–28,

40–47

F1, F2, G1,

G2, G4, G3,

H1, H2, K3,

L2, L3, K2,

M3, J4, M4,

K4

27–34,

46–53

J4–J1,

K4–K1, M3,

N3, M4, N4,

P4, L5, M5,

N5

8–15, 51–58 B2, B1, C2,

C1, D2, D1,

E2, E1, L5,

16–23,

57–64

F3–F1,

G4–G1, H1,

N6, P6, L7,

M7, N7, P7,

N8, P8

K5, L6, J6,

M6, J7, L7,

K7

BE/BWE[3:0]

PBE[3:0]

20, 48, 18, F4, L4, E3, 26, 54, 24, H2, P5, H4,

50

60

90

59

4

J5

56

66

98

65

12

M6

M8

H14

L8

OE

TA²

R/W

TS

PBUSCTL3

PBUSCTL2

PBUSCTL1

PBUSCTL0

—

O

I

J8

G11

K6

—

O

DACK0

B3

E3

Chip Selects

FB_CS[3:2]

FB_CS1

PCS[3:2]

PCS1

—

SD_CS1

—

O

119, 120

121

D7, A9

C8

—

C11, A10

B10

127

128

FB_CS0

122

B8

C10

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

4

Freescale Semiconductor

Signal Descriptions

Table 3. MCF5207/8 Signal Information and Muxing (continued)

MCF5207

144

MCF5207

144

MCF5208

196

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

160

LQFP

MAPBGA

QFP

MAPBGA

SDRAM Controller

SD_A10

SD_CKE

—

O

37

6

M1

C3

43

14

N2

E1

SD_CLK

31

32

7

J1

37

L1

SD_CLK

K1

38

M1

F4

SD_CS0

A1

15

SD_DQS[3:2]

SD_SCAS

SD_SRAS

SD_SDR_DQS

SD_WE

19, 49

38

39

29

5

F3, M5

M2

J2

25, 55

44

H3, L6

P2

45

P3

H3

35

L3

D3

13

E2

External Interrupts Port⁴

IRQ7²

IRQ4²

IRQ1²

PIRQ7²

PIRQ4²

PIRQ1²

—

DREQ0²

—

I

134

133

132

A5

C6

B6

142

141

140

C7

D7

D8

FEC

FEC_MDC

FEC_MDIO

FEC_TXCLK

FEC_TXEN

FEC_TXD0

FEC_COL

PFECI2C3

PFECI2C2

PFECH7

PFECH6

PFECH5

PFECH4

PFECH3

PFECH2

PFECH1

PFECH0

I2C_SCL²

U2TXD

U2RXD

—

O

—

148

147

157

158

3

D6

I2C_SDA²

I/O

I

C6

—

B3

—

O

I

A2

—

B1

—

7

D3

FEC_RXCLK

FEC_RXDV

FEC_RXD0

FEC_CRS

—

I

154

153

152

8

B4

A4

—

I

—

I

D5

—

I

D2

FEC_TXD[3:1] PFECL[7:5]

FEC_TXER PFECL4

FEC_RXD[3:1] PFECL[3:1]

—

O

I

6–4

156

149–151

155

C1, C2, B2

A3

—

A5, B5, C5

C4

FEC_RXER

PFECL0

—

I

I²C

I2C_SDA²

PFECI2C0²

U2RXD²

—

I/O

—

D1

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

5

Signal Descriptions

Signal Name

Table 3. MCF5207/8 Signal Information and Muxing (continued)

MCF5207

144

MCF5207

144

MCF5208

160

MCF5208

196

MAPBGA

GPIO

PFECI2C1²

Alternate 1

Alternate 2 Dir.¹

LQFP

MAPBGA

QFP

I2C_SCL²

U2TXD²

—

I/O

DMA

—

E4

DACK0 and DREQ0 do not have a dedicated bond pads. Please refer to the following pins for muxing:

TS and QSPI_CS2 for DACK0, IRQ4 and QSPI_DIN for DREQ0.

QSPI

QSPI_CS2

QSPI_CLK

QSPI_DOUT

QSPI_DIN

PQSPI3

PQSPI0

PQSPI1

PQSPI2

DACK0

I2C_SCL²

I2C_SDA²

DREQ0²

U2RTS

—

O

I

126

127

128

129

A8

C7

A7

B7

132

133

134

135

D10

A9

—

B9

U2CTS

C9

Note: The QSPI_CS1 and QSPI_CS0 signals are available on the U1CTS, U1RTS, U0CTS, or U0RTS pins for the 196 and

160-pin packages.

UARTs

U1CTS

U1RTS

U1CTS

U1RTS

U1TXD

U1RXD

U0CTS

U0RTS

U0CTS

U0RTS

U0TXD

U0RXD

PUARTL7

PUARTL6

PUARTL7

PUARTL6

PUARTL5

PUARTL4

PUARTL3

PUARTL2

PUARTL3

PUARTL2

PUARTL1

PUARTL0

—

I

O

I

139

142

—

B4

A2

—

DT1IN

DT1OUT

—

QSPI_CS1

136

137

139

138

—

D9

C8

A8

QSPI_CS1

O

I

—

131

130

140

141

—

A6

D6

E4

D5

—

B8

—

I

—

QSPI_CS0

—

O

I

—

DT0IN

DT0OUT

—

76

N12

P12

P13

N13

O

I

—

77

71

L10

M10

79

—

70

78

Note: The UART2 signals are multiplexed on the DMA Timers, QSPI, FEC, and I2C pins.

DMA Timers

DT3IN

DT2IN

DT1IN

DT0IN

PTIMER3

PTIMER2

PTIMER1

PTIMER0

DT3OUT

DT2OUT

DT1OUT

DT0OUT

U2CTS

U2RTS

U2RXD

U2TXD

I

135

136

137

138

B5

C5

A4

A3

143

144

145

146

B7

A7

A6

B6

BDM/JTAG⁵

JTAG_EN⁶

DSCLK

—

I

83

76

J11

91

84

J13

L12

TRST²

—

K11

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

6

Freescale Semiconductor

Signal Descriptions

Table 3. MCF5207/8 Signal Information and Muxing (continued)

MCF5207

144

MCF5207

144

MCF5208

196

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

160

LQFP

MAPBGA

QFP

MAPBGA

PSTCLK

BKPT

—

TCLK²

TMS²

TDI²

TDO

—

O

I

64

75

77

69

—

M7

L12

H9

70

83

85

75

—

P9

M14

K12

M12

DSI

I

DSO

O

M9

DDATA[3:0]

K9, L9, M11,

M8

P11, N11,

M11, P10

PST[3:0]

ALLPST

—

O

—

L11, L8,

K10, K8

—

N10, M10,

L10, L9

67

—

73

—

Test

TEST⁶

—

I

109

—

C12

M13

PLL_TEST

Power Supplies

EVDD

IVDD

—

1, 63, 66, 72, E5–E6, F5, 2, 9, 69, 72, E5–E7, F5,

81, 87, 125

G8–G9,

H7–H8

80, 89, 95, F6, G5, H10,

131

J9, J10,

K8–K10,

K13, M9

—

30, 68, 84, D4, D8, H4, 36, 74, 92,

J12, D4,

D11, H11,

L4, L11,

113, 143

H11, J9

121, 159

PLL_VDD

SD_VDD

—

86

H12

94

H13

3, 17, 33, 35, E7–E8, F8, 11, 39, 41, E8–E10, F9,

61, 89, 110, G5, H5–H6, 67, 97, 118, F10, G10,

123

J3

129

H5, J5, J6,

K5–K7, L2

VSS

—

2, 16, 36, 62, D10, F6–F7, 1, 10, 42, 68,

A1, A14,

F7–F8,

G6–G9,

H6–H9,

65, 73, 88,

111, 124

G6–G7

71, 81, 96,

117, 119,

130

J7–J8, L13,

M2, N9, P1,

P14

PLL_VSS

—

85

—

93

H12

NOTES:

1

2

3

Refers to pin’s primary function.

Pull-up enabled internally on this signal for this mode.

Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating

the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.

GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate

functions.

4

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Freescale Semiconductor

7

Preliminary

Mechanicals and Pinouts

5

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for

assigning these pins.

Pull-down enabled internally on this signal for this mode.

6

4 Mechanicals and Pinouts

This section contains drawings showing the pinout and the packaging and mechanical characteristics of

the MCF5207 and MCF5208 devices.

NOTE

The mechanical drawings are the latest revisions at the time of publication

of this document. The most up-to-date mechanical drawings can be found at

the product summary page located at http://www.freescale.com/coldfire.

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

8

Freescale Semiconductor

Preliminary

Mechanicals and Pinouts

4.1 Pinout—144 LQFP

Figure 1 shows a pinout of the MCF5207CAG166 device.

•

1

EVDD

EVSS

SD_VDD

TS

108

107

106

105

104

103

102

101

100

99

A17

2

A16

3

A15

4

A14

SD_WE

SD_CKE

SD_CS

D15

5

A13

6

A12

7

A11

8

A10

D14

9

A9

D13

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

A8

D12

98

A7

D11

D10

97

A6

96

A5

D9

D8

95

A4

94

A3

EVSS

93

A2

SD_VDD

BE/BWE1

SD_DQS1/3

BE/BWE3

92

A1

91

A0

90

TA

89

SD_VDD

VSS

D31

D30

88

87

EVDD

PLL_VDD

PLL_VSS

IVDD

JTAG_EN

RESET

EVDD

XTAL

DRAMSEL

EXTAL

TDI/DSI

TRST/DSCLK

TMS/BKPT

RSTOUT

VSS

D29

86

D28

85

D27

84

D26

83

D25

82

D24

81

SD_SDR_DQS

IVDD

80

79

SD_CLK

SD_VDD

FB_CLK

SD_VDD

VSS

78

77

76

75

74

73

Figure 1. MCF5207CAG166 Pinout Top View (144 LQFP)

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

9

Mechanicals and Pinouts

4.2 Package Dimensions—144 LQFP

Figure 2 and Figure 3 show MCF5207CAB166 package dimensions.

Figure 2. MCF5207CAB166 Package Dimensions (Sheet 1 of 2)

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

10

Freescale Semiconductor

Mechanicals and Pinouts

View A

Section A-A

Rotated 90× CW

144 Places

View B

Figure 3. MCF5207CAB166 Package Dimensions (Sheet 2 of 2)

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

11

Mechanicals and Pinouts

4.3 Pinout—144 MAPBGA

The pinout of the MCF5207CVM166 device is shown below.

1

2

3

4

5

6

7

8

9

10

11

12

QSPI_

DOUT

A

B

C

D

E

F

SD_CS

U1RTS

DT0IN

DT1IN

IRQ7

U1TXD

QSPI_CS2 FB_CS2

A22

A20

A18

A

B

C

D

E

F

D14

D12

D10

D8

D15

D13

D11

D9

TS

U1CTS

RCON

IVDD

DT3IN

DT2IN

IRQ1

IRQ4

U1RXD

EVDD

VSS

QSPI_DIN FB_CS0

A23

A21

A19

A10

VSS

A12

A6

A16

A17

A15

A14

QSPI_

FB_CS1

CLK

SD_CKE

SD_WE

BE/BWE1

U0RTS

EVDD

FB_CS3

IVDD

A8

A13

A11

U0CTS

SD_VDD SD_VDD

A4

A9

A7

D31

D29

D25

D30

D28

D24

SD_DQS1 BE/BWE3

EVDD

VSS

EVDD

D2

SD_VDD

EVDD

OE

A0

A5

A3

G

H

J

D26

D27

IVDD

SD_VDD

VSS

EVDD

TDI/DSI

IVDD

DDATA3

DDATA2

A2

TA

A1

G

H

J

SD_SDR_

DQS

DRAM

SEL

SD_VDD SD_VDD

IVDD

JTAG_EN

PLL_VDD

XTAL

EXTAL

SD_CLK SD_RAS SD_VDD

D18

BE/BWE0

D6

D4

R/W

D5

RESET

PST1

TRST/

DSCLK

K

L

SD_CLK

FB_CLK

D20

D22

D23

D21

D16

D0

PST0

PST2

K

L

TMS/

BKPT

BE/BWE2

D7

D1

U0TXD

PST3

TCLK/

PSTCLK

M

SD_A10 SD_CAS

D19

3

D17

4

SD_DQS0

5

D3

6

DDATA0 TDO/DSO

U0RXD

10

DDATA1 RSTOUT

M

1

2

7

8

9

11

12

Figure 4. MCF5207CVM166 Pinout Top View (144 MAPBGA)

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

12

Freescale Semiconductor

Mechanicals and Pinouts

4.4 Package Dimensions—144 MAPBGA

Figure 5 shows the MCF5207CAB166 package dimensions.

Figure 5. MCF5207CAB166 Package Dimensions (144 MAPBGA)

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

13

Mechanicals and Pinouts

4.5 Pinout—160 QFP

Figure 6 shows a pinout of the MCF5208CAB166 device.

•

1

VSS

EVDD

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

A18

2

VSS

FEC_TXD0

FEC_TXD1

FEC_TXD2

FEC_TXD3

FEC_COL

FEC_CRS

EVDD

3

SD_VDD

VSS

4

5

A17

6

A16

7

A15

8

A14

9

A13

VSS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

A12

SD_VDD

A11

TS

A10

SD_WE

A9

SD_CKE

SD_CS

D15

A8

A7

A6

D14

A5

D13

A4

D12

A3

D11

A2

D10

A1

D9

A0

D8

98

TA

BE/BWE1

SD_DQS1/3

BE/BWE3

D31

97

SD_VDD

VSS

96

95

EVDD

PLL_VDD

PLL_VSS

IVDD

JTAG_EN

RESET

EVDD

XTAL

DRAMSEL

EXTAL

TDI/DSI

TRST/DSCLK

TMS/BKPT

RSTOUT

VSS

94

D30

93

D29

92

D28

91

D27

90

D26

89

D25

88

D24

87

SD_SDR_DQS

IVDD

86

85

SD_CLK

SD_VDD

FB_CLK

84

83

82

81

Figure 6. MCF5208CAB166 Pinout Top View (160 QFP)

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

14

Freescale Semiconductor

Mechanicals and Pinouts

4.6 Package Dimensions—160 QFP

The package dimensions of the MCF5208CAB166 device are shown in the figures below.

Top View

Figure 7. MCF5208CAB166 Package Dimensions (Sheet 1 of 2)

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

15

Mechanicals and Pinouts

SECTION B-B

DETAIL A

Figure 8. MCF5208CAB166 Package Dimensions (Sheet 2 of 2)

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

16

Freescale Semiconductor

Mechanicals and Pinouts

4.7 Pinout—196 MAPBGA

Figure 6 shows a pinout of the MCF5208CVM166 device.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

FEC_

TXEN

FEC_

TXER

FEC_

RXDV

FEC_

RXD3

QSPI_

CLK

A

B

C

D

E

F

VSS

DT1IN

DT2IN

U1TXD

FB_CS2

A22

A20

A19

VSS

A

B

C

D

E

F

FEC_

TXD0

FEC_

TXD1

FEC_

TXCLK

FEC_

RXCLK

FEC_

RXD2

QSPI_

DOUT

DT0IN

DT3IN

IRQ7

IRQ4

EVDD

VSS

U1RXD

U1RTS

IRQ1

FB_CS1

A23

A21

TEST

A14

A10

A6

A18

A16

A13

A9

A17

A15

FEC_

TXD3

FEC_

TXD2

FEC_

RXER

FEC_

RXD1

FEC_

MDIO

QSPI_

DIN

RCON

FB_CS0 FB_CS3

FEC_

CRS

FEC_

COL

FEC_

RXD0

FEC_

MDC

QSPI_

IVDD

CS2

I2C_SDA

IVDD

I2C_SCL

SD_CS

D12

U1CTS

A12

SD_CKE SD_WE

TS

EVDD

VSS

SD_VDD SD_VDD SD_VDD

A11

A7

A8

D13

D9

D14

D10

D15

D11

VSS

EVDD

R/W

OE

SD_VDD SD_VDD

A5

A4

G

H

J

EVDD

VSS

SD_VDD

EVDD

PST1

A3

A2

A1

A0

G

H

J

BE/

BWE3

SD_

DQS1

BE/

BWE1

PLL_

VSS

PLL_

VDD

D8

SD_VDD

VSS

IVDD

NC

TA

JTAG_

EN

D28

D24

D29

D25

D30

D26

D31

D27

IVDD

D21

D20

SD_VDD SD_VDD

VSS

EVDD

PST0

EVDD

VSS

IVDD

RESET

XTAL

EXTAL

DRAM

SEL

TDI/

DSI

K

L

SD_VDD SD_VDD SD_VDD

SD_

EVDD

VSS

K

L

SD_DR_

DQS

TRST/

DSCLK

SD_CLK SD_VDD

D18

D17

D16

D5

D4

D3

IVDD

DQS0

BE/

BWE0

TDO/

DSO

PLL_

TEST

TMS/

BKPT

M

N

P

SD_CLK

VSS

D23

D22

PST2

DDATA1

DDATA2

M

N

P

FB_CLK SD_A10

D7

D1

PST3

U0CTS

U0RXD RSTOUT

BE/

BWE2

TCLK/

PSTCLK

VSS

1

SD_CAS SD_RAS

D19

4

D6

6

D2

7

D0

8

DDATA0 DDATA3

U0RTS

12

U0TXD

13

VSS

14

2

3

5

9

10

11

Figure 9. MCF5208CVM166 Pinout Top View (196 MAPBGA)

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

17

Preliminary Electrical Characteristics

4.8 Package Dimensions—196 MAPBGA

The package dimensions for the MCF5208CVM166 device is shown below.

Top View

Bottom View

Figure 10. MCF5208CVM166 Package Dimensions (196 MAPBGA)

5 Preliminary Electrical Characteristics

The following electrical specifications are preliminary and are from previous designs or design

simulations. These specifications may not be fully tested or guaranteed at this early stage of the product

life cycle, however for production silicon these specifications will be met. Finalized specifications will be

published after complete characterization and device qualifications have been completed.

5.1 Maximum Ratings

1, 2

Table 4. Absolute Maximum Ratings

Rating

Core Supply Voltage

Symbol

Value

Unit

IV_DD

EV_DD

– 0.5 to +2.0

– 0.3 to +4.0

– 0.3 to +2.0

V

CMOS Pad Supply Voltage

DDR/Memory Pad Supply Voltage

PLL Supply Voltage

SDV_DD

PLLV_DD

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

18

Freescale Semiconductor

Preliminary Electrical Characteristics

(continued)

1, 2

Table 4. Absolute Maximum Ratings

Digital Input Voltage ³

V_IN

I_D

– 0.3 to +3.6

25

V

Instantaneous Maximum Current

mA

Single pin limit (applies to all pins) ^{3, 4, 5}

Operating Temperature Range (Packaged)

Storage Temperature Range

T_A

(T_L- T_H)

– 40 to 85

°C

T_stg

– 55 to 150

NOTES:

1

Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.”

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is

not guaranteed. Continued operation at these levels may affect device reliability or cause

permanent damage to the device.

2

3

This device contains circuitry protecting against damage due to high static voltage or

electrical fields; however, it is advised that normal precautions be taken to avoid application of

any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of

operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,

either V_SSor EV_DD).

Input must be current limited to the value specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive and negative clamp voltages,

then use the larger of the two values.

4

5

All functional non-supply pins are internally clamped to V_SSand EV_DD

.

Power supply must maintain regulation within operating EV_DDrange during instantaneous

and operating maximum current conditions. If positive injection current (V_in> EV_DDis greater

than I_DD, the injection current may flow out of EV_DDand could result in external power supply

going out of regulation. Insure external EV_DDload will shunt current greater than maximum

injection current. This will be the greatest risk when the MCU is not consuming power (ex; no

clock). Power supply must maintain regulation within operating EV_DDrange during

instantaneous and operating maximum current conditions.

5.2 Thermal Characteristics

Table 5 lists thermal resistance values

Table 5. Thermal Characteristics

Characteristic

Symbol

196MBGA

160QFP

Unit

Junction to ambient, natural convection

Four layer board

(2s2p)

θ_JMA

32^1,2

40^1,2

°C/W

Junction to ambient (@200 ft/min)

Four layer board

(2s2p)

θ_JMA

29^1,2

36^1,2

°C/W

Junction to board

θ_JB

θ_JC

Ψ_jt

T_j

20³

10⁴

2^1,5

105

25³

10⁴

2^1,5

105

°C/W

^oC

Junction to case

Junction to top of package

Maximum operating junction temperature

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

19

Preliminary Electrical Characteristics

N₁OTES:

θ

_JMAand Ψ_jtparameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.

Freescale recommends the use of θ_JmAand power dissipation specifications in the system design to prevent

device junction temperatures from exceeding the rated specification. System designers should be aware that

device junction temperatures can be significantly influenced by board layout and surrounding devices.

Conformance to the device junction temperature specification can be verified by physical measurement in the

customer’s system using the Ψ_jtparameter, the device power dissipation, and the method described in

EIA/JESD Standard 51-2.

2

3

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

4

5

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization

parameter is written in conformance with Psi-JT.

The average chip-junction temperature (T ) in °C can be obtained from:

J

T_J= T_A+ (P_D× Θ_JMA

)

Eqn. 1

Where:

T

= Ambient Temperature, °C

= Package Thermal Resistance, Junction-to-Ambient, ×C/W

= P + P

A

Q

JMA

P

D

INT

I/O

P

= I × IV , Watts - Chip Internal Power

DD DD

INT

P

= Power Dissipation on Input and Output Pins — User Determined

I/O

For most applications P < P

and can be ignored. An approximate relationship between P and T (if

I/O

INT

D

J

P

is neglected) is:

I/O

K

--------------------------------

P_D

=

Eqn. 2

(T_J+ 273°C)

Solving equations 1 and 2 for K gives:

K = P_D× (T_A× 273°C) + Q_JMA× P²_D

Eqn. 3

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring

P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by

D

A

D

J

solving Equation 1 and Equation 2 iteratively for any value of T .

A

5.3 ESD Protection

1, 2

Table 6. ESD Protection Characteristics

Characteristics

Symbol

Value

Units

ESD Target for Human Body Model

HBM

2000

V

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

20

Freescale Semiconductor

Preliminary Electrical Characteristics

N₁OTES:

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for

Automotive Grade Integrated Circuits.

2

A device is defined as a failure if after exposure to ESD pulses the device no longer meets

the device specification requirements. Complete DC parametric and functional testing is

performed per applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

5.4 DC Electrical Specifications

Table 7. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Core Supply Voltage

PLL Supply Voltage

IV_DD

PLLV_DD

EV_DD

1.4

1.6

V

CMOS Pad Supply Voltage

3.0

3.6

Mobile DDR/Bus Pad Supply Voltage

DDR/Bus Pad Supply Voltage

SDR/Bus Pad Supply Voltage

CMOS Input High Voltage

SDV_DD

EV_IH

1.65

2.25

3.0

1.95

2.75

3.6

2

EV_DD+ 0.05

0.8

CMOS Input Low Voltage

EV_IL

-0.05

TBD

Mobile DDR/Bus Input High Voltage

SDV_IH

SDV_DD+ 0.

05

Mobile DDR/Bus Input Low Voltage

DDR/Bus Input High Voltage

SDV_IL

SDV_IH

-0.05

2

TBD

V

SDV_DD+ 0.

05

DDR/Bus Input Low Voltage

SDV_IL

I_in

-0.05

–1.0

0.8

1.0

V

Input Leakage Current

µA

V_in= IV_DDor V_SS, Input-only pins

CMOS Output High Voltage

I_OH= –5.0 mA

EV_OH

EV_OL

EV_DD- 0.4

—

0.4

V

CMOS Output Low Voltage

I_OL= 5.0 mA

—

SDV_DD- 0.4

—

DDR/Bus Output High Voltage

I_OH= –5.0 mA

SDV_OH

SDV_OL

I_APU

—

V

DDR/Bus Output Low Voltage

I_OL= 5.0 mA

0.4

V

Weak Internal Pull Up Device Current, tested at V_ILMax.¹

-10

- 130

µA

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

21

Preliminary Electrical Characteristics

Table 7. DC Electrical Specifications (continued)

Characteristic

Symbol

Min

Max

Unit

Input Capacitance ²

C_in

pF

All input-only pins

All input/output (three-state) pins

—

7

Core Operating Supply Current ³

Master Mode

I_DD

—

170

TBD

1

mA

LIMP mode

STOP mode

Low Power mode

TBD

NOTES:

1

Refer to the signals section for pins having weak internal pull-up devices.

This parameter is characterized before qualification rather than 100% tested.

Current measured at maximum system clock frequency, all modules active, and default drive strength with

matching load.

2

3

5.4.1 PLL Power Filtering

To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins.

DD

The filter shown in Figure 11 should be connected between the board V and the PLLV pins. The

DD

resistor and capacitors should be placed as close to the dedicated PLLV pin as possible.

DD

10 Ω

Board V_DD

PLL V_DDPin

10 µF

0.1 µF

GND

Figure 11. System PLL V Power Filter

DD

5.4.2 Supply Voltage Sequencing and Separation Cautions

Figure 12 shows situations in sequencing the I/O V (EV ), SDRAM V (SDV ), PLL V

DD

(PLLV ), and Core V (IV ).

DD

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

22

Freescale Semiconductor

Preliminary Electrical Characteristics

EV_DD, SDV_DD

3.3V

Supplies Stable

2.5V

SDV_DD(2.5V/1.8V)

IV_DD, PLLV_DD

1.5V

1

2

0

Time

Notes:

1. IV_DDshould not exceed EV_DD, SDV_DDor PLLV_DDby more than

0.4 V at any time, including power-up.

2. Recommended that IV_DD/PLLV_DDshould track EV_DD/SDV_DDup to

0.9 V, then separate for completion of ramps.

3. Input voltage must not be greater than the supply voltage (EV_DD, SDV_DD

,

IV_DD, or PLLV_DD) by more than 0.5 V at any time, including during power-up.

4. Use 1 µs or slower rise time for all supplies.

Figure 12. Supply Voltage Sequencing and Separation Cautions

The relationship between SDV and EV is non-critical during power-up and power-down sequences.

DD

Both SDV (2.5V or 3.3V) and EV are specified relative to IV .

DD

5.4.2.1 Power Up Sequence

If EV /SDV are powered up with IV at 0 V, then the sense circuits in the I/O pads will cause all

DD

pad output drivers connected to the EV /SDV to be in a high impedance state. There is no limit on

DD

how long after EV /SDV powers up before IV must powered up. IV should not lead the EV ,

DD

SDV or PLLV by more than 0.4 V during power ramp-up, or there will be high current in the internal

DD

ESD protection diodes. The rise times on the power supplies should be slower than 1 µs to avoid turning

on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1 µs or slower rise time for all supplies.

2. IV /PLLV and EV /SDV should track up to 0.9 V, then separate for the completion of

DD

ramps with EV /SD V going to the higher external voltages. One way to accomplish this is to

DD

use a low drop-out voltage regulator.

5.4.2.2 Power Down Sequence

If IV /PLLV are powered down first, then sense circuits in the I/O pads will cause all output drivers

DD

to be in a high impedance state. There is no limit on how long after IV and PLLV power down before

DD

EV or SDV must power down. IV should not lag EV , SDV , or PLLV going low by more

DD

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

23

Preliminary Electrical Characteristics

than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There

are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IV /PLLV to 0 V.

DD

2. Drop EV /SDV supplies.

DD

5.5 Oscillator and PLL Electrical Characteristics

Table 8. PLL Electrical Characteristics

Min.

Value

Max.

Value

Num

Characteristic

Symbol

Unit

1

PLL Reference Frequency Range

Crystal reference

f_{ref_crystal}

f_{ref_ext}

TBD

16

MHz

External reference

2

Core frequency

f_sys

f_sys/2

TBD

166.67

83.33

MHz

MHZ

CLKOUT Frequency ¹

t

3

4

Crystal Start-up Time ^{2, 3}

—

10

ms

cst

EXTAL Input High Voltage

Crystal Mode⁴

All other modes (External, Limp)

V_IHEXT

TBD

V

5

EXTAL Input Low Voltage

Crystal Mode⁴

V_ILEXT

TBD

V

All other modes (External, Limp)

6

XTAL Load Capacitance²

PLL Lock Time ^2,5

5

30

1

pF

ms

%

11

t_lpll

t_dc

—

40

14

Duty Cycle of reference²

60

N₁OTES:

All internal registers retain data at 0 Hz.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

2

3

4

This parameter is guaranteed by design rather than 100% tested.

5.6 External Interface Timing Characteristics

Table 9 lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and

output delay with respect to the rising edge of a reference clock. The

reference clock is the FB_CLK output.

All other timing relationships can be derived from these values.Timings

listed in Table 9 are shown in Figure 14 & Figure 15.

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

24

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

* The timings are also valid for inputs sampled on the negative clock edge.

1.5V

FB_CLK(75MHz)

T_SETUP

T_HOLD

Invalid

1.5V Valid 1.5V

Invalid

Input Setup And Hold

Input Rise Time

t_rise

V_h= V_IH

V = V

l

IL

t_fall

V_h= V_IH

V_l= V_IL

Input Fall Time

FB4

FB_CLK

Inputs

FB5

Figure 13. General Input Timing Requirements

5.6.1 FlexBus

A multi-function external bus interface called FlexBus is provided to interface to slave-only devices up to

a maximum bus frequency of 83.33 MHz. It can be directly connected to asynchronous or synchronous

devices such as external boot ROMs, Flash memories, gate-array logic, or other simple target (slave)

devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface

can be used. The FlexBus interface has six general purpose chip-selects (FB_CS[5:0]) which can be

configured to be distributed between the FlexBus or SDRAM memory interfaces. Chip-select FB_CS[0]

can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or

longword (32 bits) wide. Control signal timing is compatible with common ROM/Flash memories.

5.6.1.1 FlexBus AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative

to the system clock.

Table 9. FlexBus AC Timing Specifications

Num

Characteristic

Frequency of Operation

Clock Period (FB_CLK)

Symbol

Min

Max

Unit

Notes

83.33

12

Mhz

ns

f_sys/2

t_cyc

FB1

t_FBCK

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

25

Preliminary Electrical Characteristics

Table 9. FlexBus AC Timing Specifications

Num

Characteristic

Symbol

Min

Max

Unit

Notes

1

FB2

Data, and Control Output Valid (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)

t_FBCHDCV

—

7.0

ns

1, 2

FB3

Data, and Control Output Hold ((A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)

t_FBCHDCI

1

—

ns

FB4

FB5

FB6

FB7

FB8

FB9

Data Input Setup

t_DVFBCH

t_DIFBCH

t_CVFBCH

t_CIFBCH

t_FBCHAV

t_FBCHAI

3.5

0

—

6.0

—

ns

Data Input Hold

Transfer Acknowledge (TA) Input Setup

Transfer Acknowledge (TA) Input Hold

Address Output Valid (A[23:0])

Address Output Hold (A[23:0])

4

0

3

—

1.0

NOTES:

1

Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7, "SDRAM BUS” for SD_CS[1:0]

timing.

2

3

The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for

more information.

These specs are used when the A[23:0] signals are configured as 23-bit, non-muxed FlexBus address signals.

FB_CLK

FB1

FB9

A[23:0]

D[31:0]

R/W

A[23:0]

FB8

FB5

DATA

FB2

FB4

TS

FB_CSn, BE/BWEn

FB7

OE

TA

FB6

Figure 14. FlexBus Read Timing

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

26

Freescale Semiconductor

Preliminary Electrical Characteristics

FB_CLK

FB1

FB9

FB3

A[23:0]

FB8

D[31:0]

FB2

R/W

TS

FB_CSn, BE/BWEn

FB7

OE

TA

FB6

Figure 15. Flexbus Write Timing

5.7 SDRAM Bus

The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports

either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.

The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable

for either Class I or Class II drive strength.

5.7.1 SDR SDRAM AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative

to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read

cycles. The SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to

support DDR, a DQS pulse must still be supplied to the device for each data beat of an SDR read. The

ColdFire processor accomplishes this by asserting a signal called SD_DQS during read cycles. Care must

be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS

signal and its usage.

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Freescale Semiconductor

27

Preliminary

Preliminary Electrical Characteristics

Table 10. SDR Timing Specifications

Symbol

Characteristic

Symbol

Min

Max

Unit

Notes

1

Frequency of Operation

Clock Period (t_CK

Clock Skew (t_SK

Pulse Width High (t_CKH

Pulse Width Low (t_CKL

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

—

7.52

—

83.33

12

MHz

ns

2

SD1

SD2

SD3

SD4

SD5

)

t_SDCK

t_SDSK

)

TBD

0.55

3

)

t_SDCKH

t_SDCKL

t_SDCHACV

0.45

—

SD_CLK

ns

)

0.5 × SD_CLK

SD_BA, SD_CS[1:0] - Output Valid (t_CMV

)

+ 1.0

SD6

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

t_SDCHACI

2.0

—

ns

SD_BA, SD_CS[1:0] - Output Hold (t_CMH

SD_SDR_DQS Output Valid (t_DQSOV

)

4

5

6

7

SD7

SD8

)

t_DQSOV

—

Self timed

ns

SD_DQS[3:0] input setup relative to SD_CLK (t_DQSIS) t_DQVSDCH0.25 × SD_CLK 0.40 × SD_CLK

SD9

SD_DQS[3:2] input hold relative to SD_CLK (t_DQSIH

)

t_DQISDCHDoes not apply. 0.5 SD_CLK fixed width.

SD10

Data (D[31:0]) Input Setup relative to SD_CLK

t_DVSDCH0.25 × SD_CLK

—

ns

(reference only) (t_DIS

)

SD11

SD12

Data Input Hold relative to SD_CLK (reference only)

t_DISDCH

1.0

—

(t_DIH

)

Data (D[31:0]) and Data Mask(SD_DQM[3:0])

t_SDCHDMV

0.75 × SD_CLK

Output Valid (t_DV

)

+ 0.5

SD13

Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output t_SDCHDMI

1.5

—

Hold (t_DH

)

N₁OTES:

The device supports the same frequency of operation for both FlexBus and SDRAM as that of the internal bus clock. Please see

the PLL chapter of the MCF5208 Reference Manual for more information on setting the SDRAM clock rate.

2

3

4

SD_CLK is one SDRAM clock in (ns).

Pulse width high plus pulse width low cannot exceed min and max clock period.

SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from

this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat.

5

6

7

SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle

variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data beat.

The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does

not affect the memory controller.

Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be centered

1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is just

provided as guidance.

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

28

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

SD1

SD3

SD2

SD_CLK0

SD_CLK1

SD2

SD4

SD6

SD_CSn,

SD_RAS,

SD_CAS

SD_WE,

CMD

SD5

A[23:0],

SD_BA[1:0]

ROW

COL

SD12

SDDM

D[31:0]

SD13

WD1

WD2

WD3

WD4

Figure 16. SDR Write Timing

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

29

Preliminary Electrical Characteristics

SD1

SD2

SD_CLK0

SD_CLK1

SD2

SD6

SD_CSn,

SD_RAS,

SD_CAS,

SD_WE

CMD

3/4 MCLK

Reference

SD5

A[23:0],

SD_BA[1:0]

ROW

COL

tDQS

SDDM

SD7

SD_DQS (Measured at Output Pin)

SD_DDQS (Measured at Input Pin)

Board Delay

SD9

SD8

Delayed

SD_CLK

SD10

D[31:0]

form

Memories

WD1

WD2

WD3

WD4

NOTE: Data driven from memories relative

to delayed memory clock.

SD11

Figure 17. SDR Read Timing

5.7.2 DDR SDRAM AC Timing Characteristics

When using the SDRAM controller in DDR mode, the following timing numbers must be followed to

properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte

lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early

board design. Please contact your local Freescale representative if questions develop.

Table 11. DDR Timing Specifications

Num

Characteristic

Frequency of Operation

Symbol

Min

Max

Unit

Notes

1

83.33

TBD

0.45

—

TBD

12

Mhz

ns

2

3

4

DD1

DD2

DD3

DD4

Clock Period (SD_CLK)

Pulse Width High

t_DDCK

t_DDCKH

t_DDCKL

0.55

SD_CLK

ns

Pulse Width Low

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Valid

t_SDCHACV

0.5 × SD_CLK

+ 1.0

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

30

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 11. DDR Timing Specifications (continued)

Num

Characteristic

Symbol

Min

Max

Unit

Notes

DD5

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Hold

t_SDCHACI

2.0

—

ns

DD6

DD7

Write Command to first DQS Latching Transition

t_CMDVDQ

t_DQDMV

1.25

—

SD_CLK

ns

5

6

Data and Data Mask Output Setup (DQ-->DQS)

Relative to DQS (DDR Write Mode)

1.5

1.0

—

7

DD8

Data and Data Mask Output Hold (DQS-->DQ)

Relative to DQS (DDR Write Mode)

t_DQDMI

—

ns

8

9

DD9

Input Data Skew Relative to DQS (Input Setup)

t_DVDQ

t_DIDQ

1

ns

DD10 Input Data Hold Relative to DQS.

0.25 × SD_CLK

—

+ 0.5ns

DD11 DQS falling edge from SDCLK rising (output hold time) t_DQLSDCH

0.5

0.9

—

1.1

0.6

—

ns

DD12 DQS input read preamble width (t_RPRE

DD13 DQS input read postamble width (t_RPST

DD14 DQS output write preamble width (t_WPRE

DD15 DQS output write postamble width (t_WPST

)

t_DQRPRE

t_DQRPST

t_DQWPRE

t_DQWPST

SD_CLK

)

0.4

)

0.25

0.4

)

0.6

NOTES:

1

The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the same

frequency as the internal bus clock.

SD_CLK is one SDRAM clock in (ns).

Pulse width high plus pulse width low cannot exceed min and max clock period.

Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and

voltage variations.

2

3

4

5

This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger

than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.

MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to

MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].

The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats will

be valid for each subsequent DQS edge.

This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],

MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative

MEM_DQS[0].

6

7

8

9

Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes

valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors).

Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes

invalid.

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Freescale Semiconductor

31

Preliminary

Preliminary Electrical Characteristics

DD1

DD2

SD_CLK

DD3

SD_CLK

DD5

SD_CSn, SD_WE,

SD_RAS, SD_CAS

CMD

DD4

DD6

A[13:0]

ROW

COL

DD7

DM3/DM2

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

DD8

DD7

WD1 WD2 WD3 WD4

DD8

Figure 18. DDR Write Timing

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

32

Freescale Semiconductor

Preliminary Electrical Characteristics

DD1

DD2

SD_CLK

DD3

SD_CLK

DD5

CL=2

SD_CSn, SD_WE,

SD_RAS, SD_CAS

CMD

ROW

DD4

CL=2.5

A[13:0]

COL

DD9

DQS Read

Postamble

DQS Read

Preamble

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

DD10

WD1 WD2 WD3 WD4

DQS Read

Preamble

DQS Read

Postamble

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

WD1 WD2 WD3 WD4

Figure 19. DDR Read Timing

Figure 20 shows the DDR clock crossover specifications.

SD_CLK

V_IX

V_ID

V_MP

V_IX

SD_CLK

Figure 20. DDR Clock Crossover Timing

5.8 General Purpose I/O Timing

1

Table 12. GPIO Timing

Num

Characteristic

FB_CLK High to GPIO Output Valid

Symbol

Min

Max

Unit

G1

G2

G3

G4

t_CHPOV

t_CHPOI

t_PVCH

t_CHPI

—

1.5

8

ns

FB_CLK High to GPIO Output Invalid

GPIO Input Valid to FB_CLK High

FB_CLK High to GPIO Input Invalid

—

1.5

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

33

Preliminary Electrical Characteristics

N₁OTES:

GPIO spec cover: IRQn, UART and Timer pins.

FB_CLK

G2

G1

GPIO Outputs

G3

G4

GPIO Inputs

Figure 21. GPIO Timing

5.9 Reset and Configuration Override Timing

Table 13. Reset and Configuration Override Timing

Num

Characteristic

Symbol

Min

Max

Unit

R1

R2

R3

R4

R5

R6

R7

RESET Input valid to FB_CLK High

t_RVCH

t_CHRI

9

1.5

5

—

10

—

1

ns

FB_CLK High to RESET Input invalid

RESET Input valid Time ¹

t_RIVT

t_CYC

ns

FB_CLK High to RSTOUT Valid

t_CHROV

t_ROVCV

t_COS

—

0

RSTOUT valid to Config. Overrides valid

Configuration Override Setup Time to RSTOUT invalid

Configuration Override Hold Time after RSTOUT invalid

RSTOUT invalid to Configuration Override High Impedance

ns

20

0

t_CYC

ns

t_COH

R8

t_ROICZ

—

t_CYC

N₁OTES:

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to

the system. Thus, RESET must be held a minimum of 100 ns.

FB_CLK

R1

R2

R3

RESET

R4

RSTOUT

R8

R5

R6

R7

Configuration Overrides*:

(RCON, Override pins)

Figure 22. RESET and Configuration Override Timing

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

34

Freescale Semiconductor

Preliminary Electrical Characteristics

NOTE

Refer to the MCF5208 Reference Manual for more information.

5.10 I²C Input/Output Timing Specifications

2

Table 14 and Table 15 list specifications for the I C input and output timing parameters.

2

Table 14. I C Input Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

I1

I2

I3

I4

I5

I6

I7

I8

I9

2

8

—

1

t_cyc

ms

ns

Clock low period

I2C_SCL/I2C_SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

—

0

—

1

I2C_SCL/I2C_SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

4

ms

t_cyc

ns

—

Data setup time

0

Start condition setup time (for repeated start condition only)

Stop condition setup time

2

t_cyc

2

Table 15. I C Output Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

I1¹

6

—

3

t_cyc

µs

1.

I2

Clock low period

10

—

7

I3 ²

I2C_SCL/I2C_SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

1.

I4

t_cyc

ns

I5 ³

I2C_SCL/I2C_SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

10

2

1.

I6

—

t_cyc

1.

I7

Data setup time

1.

I8

Start condition setup time (for repeated start condition only)

Stop condition setup time

20

10

1.

I9

N₁OTES:

Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the

maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table A-16. The I²C

interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low

period. The actual position is affected by the prescale and division values programmed into the IFDR;

however, the numbers given in Table A-16 are minimum values.

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively

drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal

capacitance and pull-up resistor values.

2

3

Specified at a nominal 50-pF load.

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Freescale Semiconductor

35

Preliminary

Preliminary Electrical Characteristics

I2

I6

I5

I2C_SCL

I1

I3

I4

I8

I9

I7

I2C_SDA

2

Figure 23. I C Input/Output Timings

5.11 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

5.11.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV,

FEC_RXER, and FEC_RXCLK)

The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

FEC_RXCLK frequency.

Table 16 lists MII receive channel timings.

Table 16. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

M1

FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK

setup

5

—

ns

M2

M3

M4

FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold

FEC_RXCLK pulse width high

5

—

ns

35%

65% FEC_RXCLK period

FEC_RXCLK pulse width low

Figure 24 shows MII receive signal timings listed in Table 16.

M3

FEC_RXCLK (input)

M4

FEC_RXD[3:0] (inputs)

FEC_RXDV

FEC_RXER

M1

M2

Figure 24. MII Receive Signal Timing Diagram

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

36

Freescale Semiconductor

Preliminary Electrical Characteristics

5.11.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN,

FEC_TXER, FEC_TXCLK)

Table 17 lists MII transmit channel timings.

The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. There is

no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

FEC_TXCLK frequency.

The transmit outputs (FEC_TXD[3:0], FEC_TXEN, FEC_TXER) can be programmed to transition from

either the rising or falling edge of FEC_TXCLK, and the timing is the same in either case. This options

allows the use of non-compliant MII PHYs.

Refer to the Ethernet chapter for details of this option and how to enable it.

Table 17. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

M5

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER

invalid

5

—

ns

M6

M7

M8

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid

FEC_TXCLK pulse width high

—

25

ns

35%

65%

FEC_TXCLK period

FEC_TXCLK pulse width low

Figure 25 shows MII transmit signal timings listed in Table 17.

M7

FEC_TXCLK (input)

M5

M8

FEC_TXD[3:0] (outputs)

FEC_TXEN

FEC_TXER

M6

Figure 25. MII Transmit Signal Timing Diagram

5.11.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 18 lists MII asynchronous inputs signal timing.

Table 18. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

M9

FEC_CRS, FEC_COL minimum pulse width

1.5

—

FEC_TXCLK period

Figure 26 shows MII asynchronous input timings listed in Table 18.

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

37

Preliminary Electrical Characteristics

FEC_CRS

FEC_COL

M9

Figure 26. MII Async Inputs Timing Diagram

5.11.4 MII Serial Management Channel Timing (FEC_MDIO and

FEC_MDC)

Table 19 lists MII serial management channel timings. The FEC functions correctly with a maximum

MDC frequency of 2.5 MHz.

Table 19. MII Serial Management Channel Timing

Num

Characteristic

Min Max

Unit

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum

propagation delay)

0

—

ns

M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay)

M12 FEC_MDIO (input) to FEC_MDC rising edge setup

M13 FEC_MDIO (input) to FEC_MDC rising edge hold

M14 FEC_MDC pulse width high

—

10

0

25

—

ns

40% 60% FEC_MDC period

M15 FEC_MDC pulse width low

Figure 27 shows MII serial management channel timings listed in Table 19.

M14

M15

FEC_MDC (output)

FEC_MDIO (output)

M10

M11

FEC_MDIO (input)

M12

M13

Figure 27. MII Serial Management Channel Timing Diagram

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

38

Freescale Semiconductor

Preliminary Electrical Characteristics

5.12 32-Bit Timer Module AC Timing Specifications

Table 20 lists timer module AC timings.

Table 20. Timer Module AC Timing Specifications

Name

Characteristic

Unit

Min

Max

T1

T2

DT0IN / DT1IN / DT2IN / DT3IN cycle time

DT0IN / DT1IN / DT2IN / DT3IN pulse width

3

1

—

t_CYC

5.13 QSPI Electrical Specifications

Table 21 lists QSPI timings.

Table 21. QSPI Modules AC Timing Specifications

Name

Characteristic

Min

Max

Unit

QS1

QS2

QS3

QS4

QS5

QSPI_CS[3:0] to QSPI_CLK

1

—

1.5

9

510

10

—

tcyc

ns

QSPI_CLK high to QSPI_DOUT valid.

QSPI_CLK high to QSPI_DOUT invalid. (Output hold)

QSPI_DIN to QSPI_CLK (Input setup)

QSPI_DIN to QSPI_CLK (Input hold)

ns

—

ns

9

—

ns

The values in Table 21 correspond to Figure 28.

QS1

QSPI_CS[3:0]

QSPI_CLK

QS2

QSPI_DOUT

QS3

QS4

QS5

QSPI_DIN

Figure 28. QSPI Timing

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

39

Preliminary Electrical Characteristics

5.14 JTAG and Boundary Scan Timing

Table 22. JTAG and Boundary Scan Timing

Num

Characteristics¹

TCLK Frequency of Operation

Symbol

Min

Max

Unit

J1

J2

J3

J4

J5

J6

J7

J8

J9

f_JCYC

t_JCYC

DC

4

1/4

—

3

f_sys/2

t_CYC

ns

TCLK Cycle Period

TCLK Clock Pulse Width

t_JCW

26

0

TCLK Rise and Fall Times

t_JCRF

ns

Boundary Scan Input Data Setup Time to TCLK Rise

Boundary Scan Input Data Hold Time after TCLK Rise

TCLK Low to Boundary Scan Output Data Valid

TCLK Low to Boundary Scan Output High Z

TMS, TDI Input Data Setup Time to TCLK Rise

t_BSDST

t_BSDHT

t_BSDV

4

—

33

—

26

8

ns

26

0

ns

t_BSDZ

0

ns

t_TAPBST

t_TAPBHT

t_TDODV

t_TDODZ

t_TRSTAT

t_TRSTST

4

ns

J10 TMS, TDI Input Data Hold Time after TCLK Rise

J11 TCLK Low to TDO Data Valid

10

0

ns

J12 TCLK Low to TDO High Z

0

ns

J13 TRST Assert Time

100

10

—

ns

J14 TRST Setup Time (Negation) to TCLK High

ns

N₁OTES:

JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

J2

J3

V

IH

TCLK

(input)

V

IL

J4

Figure 29. Test Clock Input Timing

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

40

Freescale Semiconductor

Preliminary Electrical Characteristics

TCLK

V

IL

IH

J5

Input Data Valid

J6

Data Inputs

J7

J8

Data Outputs

Output Data Valid

Data Outputs

J7

Output Data Valid

Figure 30. Boundary Scan (JTAG) Timing

TCLK

V

IL

IH

J9

Input Data Valid

J10

TDI

TMS

J11

TDO

Output Data Valid

J12

J11

TDO

Output Data Valid

Figure 31. Test Access Port Timing

TCLK

TRST

J14

J13

Figure 32. TRST Timing

5.15 Debug AC Timing Specifications

Table 23 lists specifications for the debug AC timing parameters shown in Figure 33 & Figure 34.

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Freescale Semiconductor

41

Preliminary

Preliminary Electrical Characteristics

Table 23. Debug AC Timing Specification

Num

Characteristic

Units

Min

Max

DE0

DE1

DE2

DE3

DE4

DE5 ¹

DE6

PSTCLK cycle time

—

2

1

5

1

4

0

0.5

—

t_cyc

ns

PST valid to PSTCLK high

PSTCLK high to PST invalid

DSCLK cycle time

ns

t_cyc

ns

DSI valid to DSCLK high

DSCLK high to DSO invalid

BKPT input data setup time to FB_CLK high

FB_CLK high to BKPT invalid

DE7

ns

N₁OTES:

DSCLK and DSI are synchronized internally. DE4 is measured from the synchronized DSCLK input

relative to the rising edge of FB_CLK.

Figure 33 shows real-time trace timing for the values in Table 23.

PSTCLK

DE0

DE1

DE2

PST[3:0]

DDATA[3:0]

Figure 33. Real-Time Trace AC Timing

Figure 34 shows BDM serial port AC timing and BKPT pin timing for the values in Table 23.

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

42

Freescale Semiconductor

Preliminary

Revision History

FB_CLK

BKPT

DE6

DE7

DE5

DSCLK

DE3

DSI

Current

Past

DSO

Current

Figure 34. BDM Serial Port AC Timing

6 Revision History

Table 24. Revision History

Revision

Number

Date

Substantive Changes

0

5/23/2005

6/16/2005

• Initial Release

0.1

• Corrected 144QFP pinout in Figure 1. Pins 139-142 incorrectly showed

FEC functionality, which are actually UART 0/1 clear-to-send and

request-to-send signals.

• Changed maximum core frequency in Table 8, spec #2, from 240MHz to

166.67MHz. Also, changed symbols in table: f_core-> f_sysand f_sys-> f_sys/2

for consistency throughout document and reference manual.

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

43

Revision History

Table 24. Revision History (continued)

Substantive Changes

Revision

Number

Date

0.2

8/26/2005

• Changed ball M9 from SD_VDD to EVDD in Figure 9.

• Table 3: Pin 33 for 144 LQFP package should be EVDD instead of

SD_VDD. BE/BWE[3:0] for 144 LQFP should be “20, 48, 18, 50“ instead

of “18, 20, 48, 50”

Cleaned up various electrical specifications:

• Table 4: Added DDR/Memory pad supply voltage spec, changed “clock

synthesizer supply voltage” to “PLL supply voltage”, changed min PLLV_DD

from -0.5 to -0.3, changed max V_INfrom 4.0 to 3.6, changed minimum T_stg

from -65 to -55,

• Table 5: Changed TBD values in T_jentry to 105°C.

• Table 7: Changed minimum core supply voltage from 1.35 to 1.4 and

maximum from 1.65 to 1.6, added PLL supply voltage entry, added pad

supply entries for mobile-DDR, DDR, and SDR, changed minimum input

high voltage from 0.7xEV_DDto 2 and maximum from 3.65 to EV_DD+0.05,

changed minimum input low voltage from VSS-0.3 to -0.05 and maximum

from 0.35xEV_DDto 0.8, added input high/low voltage entries for DDR and

mobile-DDR, removed high impedance leakage current entry, changed

minimum output high voltage from EV_DD-0.5 to EV_DD-0.4, added DDR/bus

output high/low voltage entries, removed load capacitance and DC

injection current entries.

• Added filtering circuits and voltage sequencing sections: Section 5.4.1,

“PLL Power Filtering,” and Section 5.4.2, “Supply Voltage Sequencing and

Separation Cautions.”

• Removed “Operating Conditions” table from Section 5.5, “Oscillator and

PLL Electrical Characteristics,” since it is redundant with Table 7.

• Table 9: Changed minimum core frequency to TBD, removed external

reference and on-chip PLL frequency specs to have only a CLKOUT

frequency spec of TBD to 83.33MHz, removed loss of reference frequency

and self-clocked mode frequency entries, in EXTAL input high/low voltage

entries changed “All other modes (Dual controller (1:1), Bypass, External)”

to “All other modes (External, Limp)”, removed XTAL output high/low

voltage entries, removed power-up to lock time entry, removed last 5

entries (frequency un-lock range, frequency lock range, CLKOUT period

jitter, frequency modulation range limit, and ICO frequency)

0.3

0.4

0.5

9/07/2005

10/10/2005

3/29/2006

• Corrected DRAMSEL footnote #3 in Table 3.

• Updated Table 3 with 144MAPBGA pin locations.

• Added 144MAPBGA ballmap to Section 4.3, “Pinout—144 MAPBGA.”

• Changed J12 from PLL_VDD to IVDD in Figure 9.

• Figure 1 and Table 3: Changed pin 33 from EVDD to SD_VDD

• Figure 4 and Table 3: Changed ball D10 from TEST to VSS

• Figure 6 and Table 3: Changed pin 39 from EVDD to SD_VDD and pin 117

from TEST to VSS

• Added “top view” and “bottom view” labels where appropriate to

mechanical drawings and pinouts.

• Updated mechanical drawings to latest available, and added note to

Section 4, “Mechanicals and Pinouts.”

MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

44

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MCF5208 ColdFire^®Microprocessor Data Sheet, Rev. 0.5

Preliminary

Freescale Semiconductor

45

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MCF5208EC

Rev. 0.5

3/2006


型号：	MCF5208CVM166
厂家：	Freescale
描述：	Microprocessor Data Sheet 微处理器数据表微处理器
文件：	总46页 (文件大小：979K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCF5208CVM166 [FREESCALE]

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