MCF5213_技术文档

MCF5213EC

Rev. 1.2, 01/2006

Freescale Semiconductor

Data Sheet: Advance Information

MCF5213 Microcontroller Family

Hardware Specification

®

Table of Contents

MCF5213 Family Configurations.........................2

The MCF5213 is a member of the ColdFire family of

1

reduced

instruction

set

computing

(RISC)

1.1 Block Diagram ...................................................3

1.2 Features.............................................................4

1.3 Part Numbers and Packaging..........................14

1.4 Package Pinouts..............................................15

1.5 Reset Signals ..................................................22

1.6 PLL and Clock Signals ....................................22

1.7 Mode Selection................................................22

1.8 External Interrupt Signals................................23

1.9 Queued Serial Peripheral Interface (QSPI) .....23

1.10 I²C I/O Signals.................................................24

1.11 UART Module Signals .....................................24

1.12 DMA Timer Signals..........................................24

1.15 Pulse Width Modulator Signals........................25

1.16 Debug Support Signals....................................25

1.17 EzPort Signal Descriptions..............................27

1.18 Power and Ground Pins...................................27

microprocessors. This document provides an overview

of the 32-bit MCF5213 microcontroller, focusing on its

highly integrated and diverse feature set. Freescale

reserves the right to change or discontinue this product

without notice. Specifications and information herein are

subject to change without notice.

This 32-bit device is based on the Version 2 ColdFire

core operating at a frequency up to 80 MHz, offering

high performance and low power consumption. On-chip

memories connected tightly to the processor core include

256 Kbytes of Flash and 32 Kbytes of static random

access memory (SRAM). On-chip modules include the

following:

2

3

Preliminary Electrical Characteristics................27

Mechanical Outline Drawings............................44

•

V2 ColdFire core delivering 76 MIPS

(Dhrystone 2.1) at 80 MHz running from

internal Flash with Multiply Accumulate (MAC)

Unit and hardware divider

•

FlexCAN controller area network (CAN)

module

Three universal asynchronous/synchronous

receiver/transmitters (UARTs)

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

• Preliminary

MCF5213 Family Configurations

•

Inter-integrated circuit (I²C™) bus controller

Queued serial peripheral interface (QSPI) module

Eight-channel 12-bit fast analog-to-digital converter (ADC)

Four-channel direct memory access (DMA) controller

Four 32-bit input capture/output compare timers with DMA support (DTIM)

Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width

modulation (PWM), and pulse accumulation

•

Eight-channel/Four-channel, 8-bit/16-bit pulse width modulation timer

Two 16-bit periodic interrupt timers (PITs)

Programmable software watchdog timer

Interrupt controller capable of handling 57 sources

Clock module with 8 MHz on-chip relaxation oscillator and integrated phase locked loop (PLL)

Test access/debug port (JTAG, BDM)

1 MCF5213 Family Configurations

Table 1. MCF5213 Family Configurations

Module

5211

5212

5213

ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit)

System Clock

x

66 MHz

66, 80 MHz

up to 76

Performance (Dhrystone 2.1 MIPS)

Flash / Static RAM (SRAM)

Interrupt Controller (INTC)

Fast Analog-to-Digital Converter (ADC)

FlexCAN 2.0B Module

63

128/16 Kbytes

256/32 Kbytes

x

2

x

4

x

3

x

—

x

—

x

Four-channel Direct-Memory Access (DMA)

Software Watchdog Timer (WDT)

Programmable Interrupt Timer

Four-Channel General Purpose Timer

32-bit DMA Timers

x

2

x

2

x

4

x

4

x

QSPI

UART(s)

3

x

3

x

I²C

Eight/Four-channel 8/16-bit PWM Timer

General Purpose I/O Module (GPIO)

x

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

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Freescale Semiconductor

MCF5213 Family Configurations

Table 1. MCF5213 Family Configurations (continued)

Module

5211

5212

5213

Chip Configuration and Reset Controller Module

Background Debug Mode (BDM)

JTAG - IEEE 1149.1 Test Access Port¹

Package

x

64 LQFP

64 QFN

64 LQFP

81 MAPBGA

100 LQFP

81 MAPBGA

NOTES:

1

The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on

smaller packages.

1.1 Block Diagram

Figure 1 shows a top-level block diagram of the MCF5213. Package options for this family are described

later in this document.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

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3

Preliminary

MCF5213 Family Configurations

EzPCK

EzPCS

EzPD

EzPQ

EzPort

Arbiter

GPTn

QSPI_DIN,

QSPI_DOUT

Interrupt

Controller

QSPI_SCK,

QSPI_PCSn

UnTXD

UART

0

UART

1

UART

2

UnRXD

I²C

4 CH DMA

QSPI

UnRTS

UnCTS

DTINn/DTOUTn

CANRX

CANTX

DTIM

0

DTIM

1

DTIM

2

DTIM

3

SWT

To/From PADI

PWMn

JTAG_EN

MUX

V2 ColdFire CPU

OEP MAC

IFP

PMM

CIM

JTAG

TAP

32 Kbytes

SRAM

256 Kbytes

RSTI

PORTS

(GPIO)

AN[7:0]

ADC

Flash

RSTO

(4Kx16)x4

(32Kx16)x4

V_RHV_RL

V_STBY

Edge

Port

PLL OCO

CLKGEN

FlexCAN

PIT0

PIT1

GPT

PWM

EXTAL XTAL CLKOUT

CLKMOD0 CLKMOD1

To/From Interrupt Controller

Figure 1. MCF5213 Block Diagram

1.2 Features

The MCF5213 family includes the following features:

•

Version 2 ColdFire variable-length RISC processor core

— Static operation

— 32-bit address and data paths on-chip

— Up to 80 MHz processor core frequency

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

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MCF5213 Family Configurations

— Sixteen general-purpose, 32-bit data and address registers

— Implements ColdFire ISA_A with extensions to support the user stack pointer register and

four new instructions for improved bit processing (ISA_A+)

— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16 × 16 → 32 or

32 × 32 → 32 operations

— Illegal instruction decode that allows for 68K emulation support

System debug support

•

— Real time trace for determining dynamic execution path

— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)

— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can

be configured into a 1- or 2-level trigger

•

On-chip memories

— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with

standby power supply support

— 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses

Power management

— Fully static operation with processor sleep and whole chip stop modes

— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)

— Clock enable/disable for each peripheral when not used

FlexCAN 2.0B module

•

— Based on and includes all existing features of the Freescale TouCAN module

— Full implementation of the CAN protocol specification version 2.0B

– Standard Data and Remote Frames (up to 109 bits long)

– Extended Data and Remote Frames (up to 127 bits long)

– 0–8 bytes data length

– Programmable bit rate up to 1 Mbit/sec

— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length

each, configurable as Rx or Tx, all supporting standard and extended messages

— Unused MB space can be used as general purpose RAM space

— Listen only mode capability

— Content-related addressing

— No read/write semaphores

— Three programmable mask registers: global for MBs 0-13, special for MB14, and special for

MB15

— Programmable transmit-first scheme: lowest ID or lowest buffer number

— “Time stamp” based on 16-bit free-running timer

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

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Preliminary

MCF5213 Family Configurations

— Global network time, synchronized by a specific message

— Maskable interrupts

•

Three universal asynchronous/synchronous receiver transmitters (UARTs)

— 16-bit divider for clock generation

— Interrupt control logic with maskable interrupts

— DMA support

— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity

— Up to 2 stop bits in 1/16 increments

— Error-detection capabilities

— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs

— Transmit and receive FIFO buffers

•

I²C module

— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads

— Fully compatible with industry-standard I²C bus

— Master and slave modes support multiple masters

— Automatic interrupt generation with programmable level

Queued serial peripheral interface (QSPI)

— Full-duplex, three-wire synchronous transfers

— Up to four chip selects available

— Master mode operation only

— Programmable bit rates up to half the CPU clock frequency

— Up to 16 pre-programmed transfers

•

Fast analog-to-digital converter (ADC)

— Eight analog input channels

— 12-bit resolution

— Minimum 1.125 µs conversion time

— Simultaneous sampling of two channels for motor control applications

— Single-scan or continuous operation

— Optional interrupts on conversion complete, zero crossing (sign change), or under/over

low/high limit

— Unused analog channels can be used as digital I/O

Four 32-bit DMA timers

•

— 12.5-ns resolution at 80 MHz

— Programmable sources for clock input, including an external clock option

— Programmable prescaler

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

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Preliminary

MCF5213 Family Configurations

— Input capture capability with programmable trigger edge on input pin

— Output compare with programmable mode for the output pin

— Free run and restart modes

— Maskable interrupts on input capture or output compare

— DMA trigger capability on input capture or output compare

Four-channel general purpose timer

•

— 16-bit architecture

— Programmable prescaler

— Output pulse widths variable from microseconds to seconds

— Single 16-bit input pulse accumulator

— Toggle-on-overflow feature for pulse-width modulator (PWM) generation

— One dual-mode pulse accumulation channel

Pulse-width modulation timer

•

— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution

— Programmable period and duty cycle

— Programmable enable/disable for each channel

— Software selectable polarity for each channel

— Period and duty cycle are double buffered. Change takes effect when the end of the current

period is reached (PWM counter reaches zero) or when the channel is disabled.

— Programmable center or left aligned outputs on individual channels

— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies

— Emergency shutdown

•

Two periodic interrupt timers (PITs)

— 16-bit counter

— Selectable as free running or count down

Software watchdog timer

— 32-bit counter

— Low power mode support

Clock generation features

— 1 to 16 MHz crystal, 8 MHz on-chip relaxation oscillator, or external oscillator reference

options

— Trimmed relaxation oscillator

— 2 to 10 MHz reference frequency for normal PLL mode

— System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator

— Low power modes supported

n

— 2 (n ≤ 0 ≤ 15) low-power divider for extremely low frequency operation

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

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Preliminary

MCF5213 Family Configurations

•

Interrupt controller

— Uniquely programmable vectors for all interrupt sources

— Fully programmable level and priority for all peripheral interrupt sources

— Seven external interrupt signals with fixed level and priority

— Unique vector number for each interrupt source

— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

— Support for hardware and software interrupt acknowledge (IACK) cycles

— Combinatorial path to provide wake-up from low power modes

DMA controller

•

— Four fully programmable channels

— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for

16-byte (4 x 32-bit) burst transfers

— Source/destination address pointers that can increment or remain constant

— 24-bit byte transfer counter per channel

— Auto-alignment transfers supported for efficient block movement

— Bursting and cycle steal support

— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)

Reset

•

— Separate reset in and reset out signals

— Seven sources of reset:

– Power-on reset (POR)

– External

– Software

– Watchdog

– Loss of clock

– Loss of lock

– Low-voltage detection (LVD)

— Status flag indication of source of last reset

Chip integration module (CIM)

•

— System configuration during reset

— Selects one of six clock modes

— Configures output pad drive strength

— Unique part identification number and part revision number

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

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Preliminary

MCF5213 Family Configurations

•

General purpose I/O interface

— Up to 56 bits of general purpose I/O

— Bit manipulation supported via set/clear functions

— Programmable drive strengths

— Unused peripheral pins may be used as extra GPIO

JTAG support for system level board testing

1.2.1 V2 Core Overview

The version 2 ColdFire processor core is comprised of two separate pipelines that are decoupled by an

instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address

generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds

prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes

two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage

(AGEX) performs instruction execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a

separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the

MCF5213 core includes the multiply-accumulate (MAC) unit for improved signal processing capabilities.

The MAC implements a three-stage arithmetic pipeline, optimized for 16 x 16 bit operations, with support

for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers,

signed fractional operands, and a complete set of instructions to process these data types. The MAC

provides support for execution of DSP operations within the context of a single processor at a minimal

hardware cost.

1.2.2 Integrated Debug Module

The ColdFire processor core debug interface is provided to support system debugging in conjunction with

low-cost debug and emulator development tools. Through a standard debug interface, users can access

debug information and real-time tracing capability is provided on 100-lead packages. This allows the

processor and system to be debugged at full speed without the need for costly in-circuit emulators.

The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an

address mask register, a data and a data mask register, four PC registers, and one PC mask register. These

registers can be accessed through the dedicated debug serial communication channel or from the

processor’s supervisor mode programming model. The breakpoint registers can be configured to generate

triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions.

The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.

The MCF5213 implements revision B+ of the coldfire Debug Architecture.

The MCF5213’s interrupt servicing options during emulator mode allow real-time critical interrupt service

routines to be serviced while processing a debug interrupt event, thereby ensuring that the system

continues to operate even during debugging.

To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data

(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

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9

Preliminary

MCF5213 Family Configurations

data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF5213

includes a new debug signal, ALLPST. This signal is the logical ‘AND’ of the processor status (PST[3:0])

signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).

The full debug/trace interface is available only on the 100-pin packages. However, every product features

the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.

1.2.3 JTAG

The MCF5213 supports circuit board test strategies based on the Test Technology Committee of IEEE and

the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state

controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan

register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register.

Test logic, implemented using static logic design, is independent of the device system logic.

The MCF5213 implementation can do the following:

•

Perform boundary-scan operations to test circuit board electrical continuity

Sample MCF5213 system pins during operation and transparently shift out the result in the

boundary scan register

•

Bypass the MCF5213 for a given circuit board test by effectively reducing the boundary-scan

register to a single bit

•

Disable the output drive to pins during circuit-board testing

Drive output pins to stable levels

1.2.4 On-Chip Memories

1.2.4.1 SRAM

The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access

in a single cycle. The location of the memory block can be set to any 32-Kbyte boundary within the

4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the

system stack. Because the SRAM module is physically connected to the processor's high-speed local bus,

it can quickly service core-initiated accesses or memory-referencing commands from the debug module.

The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal

for implementing applications with double-buffer schemes, where the processor and a DMA device

operate in alternate regions of the SRAM to maximize system performance.

1.2.4.2 Flash

The ColdFire Flash module (CFM) is a non-volatile memory (NVM) module that connects to the

processor’s high-speed local bus. The CFM is constructed with four banks of 32K x 16-bit Flash arrays to

generate 256 Kbytes of 32-bit Flash memory. These arrays serve as electrically erasable and

programmable, non-volatile program and data memory. The Flash memory is ideal for program and data

storage for single-chip applications, allowing for field reprogramming without requiring an external high

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

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Preliminary

MCF5213 Family Configurations

voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory

controller which supports interleaved accesses from the 2-cycle Flash arrays. A backdoor mapping of the

Flash memory is used for all program, erase, and verify operations, as well as providing a read datapath

for the DMA. Flash memory may also be programmed via the EzPort, which is a serial Flash programming

interface that allows the Flash to be read, erased and programmed by an external controller in a format

compatible with most SPI bus Flash memory chips.

1.2.5 Power Management

The MCF5213 incorporates several low power modes of operation which are entered under program

control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors

the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD)

monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the

LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip

falls below the standby battery voltage.

1.2.6 FlexCAN

The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts

A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific

requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of

FlexCAN has 16 message buffers.

1.2.7 UARTs

The MCF5213 has three full-duplex UARTs that function independently. The three UARTs can be clocked

by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third

UART is multiplexed with other digital I/O functions.

2

1.2.8 I C Bus

The I²C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange

and minimizes the interconnection between devices. This bus is suitable for applications requiring

occasional communications over a short distance between many devices.

1.2.9 QSPI

The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with

queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU

intervention between transfers.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

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11

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MCF5213 Family Configurations

1.2.10 Fast ADC

The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold

(S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible

buffers for further processing.

The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or

perform a programmed scan sequence repeatedly until manually stopped.

The ADC can be configured for either sequential or simultaneous conversion. When configured for

sequential conversions, up to eight channels can be sampled and stored in any order specified by the

channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.

During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same

time. This configuration requires that a single channel may not be sampled by both S/H circuits

simultaneously.

Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures

below the low threshold limit or above the high threshold limit set in the limit registers) or at several

different zero crossing conditions.

1.2.11 DMA Timers (DTIM0–DTIM3)

There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3)

on the MCF5213. Each module incorporates a 32-bit timer with a separate register set for configuration

and control. The timers can be configured to operate from the system clock or from an external clock

source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The

input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter

register (TCRn). Each of these timers can be configured for input capture or reference (output) compare

mode. Timer events may optionally cause interrupt requests or DMA transfers.

1.2.12 General Purpose Timer (GPT)

The general purpose timer (GPT) is a 4-channel timer module consisting of a 16-bit programmable counter

driven by a 7-stage programmable prescaler. Each of the four channels can be configured for input capture

or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse accumulator.

A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit

range of the counter. The input capture and output compare functions allow simultaneous input waveform

measurements and output waveform generation. The input capture function can capture the time of a

selected transition edge. The output compare function can generate output waveforms and timer software

delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.

1.2.13 Periodic Interrupt Timers (PIT0 and PIT1)

The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular

intervals with minimal processor intervention. Each timer can either count down from the value written in

its PIT modulus register, or it can be a free-running down-counter.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

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1.2.14 Pulse Width Modulation Timers

The MCF5213 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty

cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms

with software-selectable duty rates from 0% to 100%. The PWM outputs have programmable polarity, and

can be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycle

resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a

single 16-bit channel. The module can thus be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit

channels.

1.2.15 Software Watchdog Timer

The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter

is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must

periodically restart the countdown.

1.2.16 Phase Locked Loop (PLL)

The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked

loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control

logic. In order to improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their

own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply

pins, VDD and VSS.

1.2.17 Interrupt Controller (INTC)

The MCF5213 has a single interrupt controller that supports up to 63 interrupt sources. There are 56

programmable sources, 49 of which are assigned to unique peripheral interrupt requests. The remaining 7

sources are unassigned and may be used for software interrupt requests.

1.2.18 DMA Controller

The direct memory access (DMA) controller provides an efficient way to move blocks of data with

minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line

transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the

occurrence of certain UART or DMA timer events.

1.2.19 Reset

The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and

keeps track of what caused the last reset. There are seven sources of reset:

•

External reset input

Power-on reset (POR)

Watchdog timer

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

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13

MCF5213 Family Configurations

•

Phase locked-loop (PLL) loss of lock

PLL loss of clock

Software

Low-voltage detector (LVD)

Control of the LVD and its associated reset and interrupt are handled by the reset controller. Other registers

provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO

pin.

1.2.20 GPIO

Nearly all pins on the MCF5213 have general purpose I/O capability and are grouped into 8-bit ports.

Some ports do not use all 8 bits. Each port has registers that configure, monitor, and control the port pins.

1.3 Part Numbers and Packaging

This product is RoHS-compliant. Refer to the product page at freescale.com or contact your sales office

for up-to-date RoHS information.

Table 2. Part Number Summary

Part Number

Flash / SRAM

Key Features

Package

Speed

MCF5211

128 Kbytes / 16 Kbytes

3 UARTs, I²C, QSPI, A/D

16-/32-bit/PWM Timers

64 LQFP

81 MAPBGA

64 QFN

66 MHz

66, 80 MHz

66 MHz

MCF5212

MCF5213

256 Kbytes / 32 Kbytes

3 UARTs, I²C, QSPI, A/D

16-/32-bit/PWM Timers

64 LQFP

81 MAPBGA

66 MHz

66, 80 MHz

3 UARTs, I²C, QSPI, A/D

16-/32-bit/PWM Timers, CAN

81 MAPBGA

100 LQFP

66, 80 MHz

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

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MCF5213 Family Configurations

1.4 Package Pinouts

Figure 2 shows the pinout configuration for the 100 LQFP.

V

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DD

SS

DD

DDPLL

V

EXTAL

XTAL

V

SS

URTS1

TEST

SSPLL

UCTS0

URXD0

UTXD0

URTS0

SCL

PST3

PST2

V

DD

9

SS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PST1

PST0

SDA

QSPI_CS3

QSPI_CS2

PSTCLK

PWM7

GPT3

GPT2

PWM5

GPT1

GPT0

100 LQFP

V

DD

V

SS

QSPI-DIN

QSPI_DOUT

QSPI_CLK

QSPI_CS1

QSPI_CS0

RCON

V

DD

V

SS

STBY

V

DD

AN4

AN5

AN6

AN7

V

DD

V

SS

V

SS

Figure 2. 100 LQFP Pin Assignments

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

15

MCF5213 Family Configurations

Figure 3 shows the pinout configuration for the 81 MAPBGA.

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

VSS

UTXD1

RSTI

IRQ5

IRQ3

ALLPST

TDO

TMS

VSS

URTS1

UCTS0

URXD0

SCL

URXD1

TEST

RSTO

UCTS1

URTS0

VDD

IRQ6

IRQ7

VSS

IRQ2

IRQ4

TRST

IRQ1

VSS

VDD

VSS

AN2

AN1

AN0

TDI

TCLK

PWM7

VDD

VDDPLL

VSSPLL

GPT3

EXTAL

XTAL

GPT2

GPT1

AN4

UTXD0

SDA

VDD

PWM5

VSTBY

AN5

QSPI_CS3

QSPI_CS2

QSPI_DIN

RCON

DTIN3

VSS

VDD

GPT0

AN3

G

H

J

QSPI_DOUT QSPI_CLK

DTIN1

DTIN0

PWM3

CLKMOD0

CLKMOD1

PWM1

AN6

QSPI_CS0

VSS

QSPI_CS1

JTAG_EN

VSSA

VRL

VDDA

VRH

AN7

DTIN2

VSSA

Figure 3. 81 MAPBGA Pin Assignments

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

16

Freescale Semiconductor

MCF5213 Family Configurations

Figure 4 shows the pinout configuration for the 64 LQFP and 64 QFN.

V

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DD

DDPLL

URTS1

TEST

EXTAL

XTAL

V

PSTCLK

GPT3

GPT2

GPT1

GPT0

UCTS0

URXD0

UTXD0

URTS0

SCL

SSPLL

SDA

9

64-Pin Packages

V

10

11

12

13

14

15

16

V

AN4

AN5

AN6

AN7

DD

V

SS

QSPI_DIN

QSPI_DOUT

QSPI_CLK

QSPI_CS0

RCON

STBY

Figure 4. 64 LQFP and 64 QFN Pin Assignments

Table 3 shows the pin functions by primary and alternate purpose, and illustrates which packages contain

each pin.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Freescale Semiconductor

17

Preliminary

MCF5213 Family Configurations

1.5 Reset Signals

Table 4 describes signals that are used to either reset the chip or as a reset indication.

Table 4. Reset Signals

Signal Name

Abbreviation

Function

I/O

Reset In

RSTI

Primary reset input to the device. Asserting RSTI immediately resets

the CPU and peripherals.

I

Reset Out

RSTO

Driven low for 512 CPU clocks after the reset source has deasserted.

O

1.6 PLL and Clock Signals

Table 5 describes signals that are used to support the on-chip clock generation circuitry.

Table 5. PLL and Clock Signals

Signal Name

Abbreviation

Function

I/O

External Clock In

EXTAL

Crystal oscillator or external clock input except when the on-chip

relaxation oscillator is used.

I

Crystal

XTAL

Crystal oscillator output except when CLKMOD1=1, then sampled as

part of the clockmode selection mechanism.

O

Clock Out

CLKOUT

This output signal reflects the internal system clock.

1.7 Mode Selection

Table 6 describes signals used in mode selection, Table 7 describes particular clocking modes.

Table 6. Mode Selection Signals

Signal Name

Abbreviation

Function

I/O

Clock Mode Selection CLKMOD[1:0] Selects the clock boot mode.

I

Reset Configuration

Test

RCON

TEST

The Serial Flash Programming mode is entered by asserting the

RCON pin (with the TEST pin negated) as the chip comes out of

reset. During this mode, the EzPort has access to the Flash memory

which can be programmed from an external device.

Reserved for factory testing only and in normal modes of operation

should be connected to VSS to prevent unintentional activation of

test functions.

I

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

22

Freescale Semiconductor

MCF5213 Family Configurations

Table 7. Clocking Modes

CLKMOD[1:0]

XTAL

0

Configure the clock mode.

00

01

10

11

PLL disabled, clock driven by external oscillator

PLL disabled, clock driven by on-chip oscillator

PLL disabled, clock driven by crystal

1

N/A

0

PLL in normal mode, clock driven by external oscillator

PLL in normal mode, clock driven by on-chip oscillator

PLL in normal mode, clock driven by crystal

1

N/A

1.8 External Interrupt Signals

Table 8 describes the external interrupt signals.

Table 8. External Interrupt Signals

Signal Name

Abbreviation

Function

I/O

External Interrupts

IRQ[7:1]

External interrupt sources.

I

1.9 Queued Serial Peripheral Interface (QSPI)

Table 9 describes QSPI signals.

Table 9. Queued Serial Peripheral Interface (QSPI) Signals

Signal Name

Abbreviation

Function

I/O

QSPI Synchronous

Serial Output

QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be

driven on the rising or falling edge of QSPI_CLK.

O

QSPI Synchronous

Serial Data Input

QSPI_DIN Provides the serial data to the QSPI and can be programmed to be

sampled on the rising or falling edge of QSPI_CLK.

I

QSPI Serial Clock

QSPI_CLK Provides the serial clock from the QSPI. The polarity and phase of

QSPI_CLK are programmable.

O

SynchronousPeripheral QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active

Chip Selects

high or low.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

23

MCF5213 Family Configurations

1.10 I²C I/O Signals

2

Table 10 describes the I C serial interface module signals.

2

Table 10. I C I/O Signals

Signal Name

Abbreviation

Function

I/O

Serial Clock

SCL

Open-drain clock signal for the for the I²C interface. Either it is driven

by the I²C module when the bus is in master mode or it becomes the

clock input when the I²C is in slave mode.

I/O

Serial Data

SDA

Open-drain signal that serves as the data input/output for the I²C

interface.

I/O

1.11 UART Module Signals

Table 11 describes the UART module signals.

Table 11. UART Module Signals

Signal Name

Abbreviation

Function

I/O

Transmit Serial Data

Output

UTXDn

Transmitter serial data outputs for the UART modules. The output is

held high (mark condition) when the transmitter is disabled, idle, or in

the local loopback mode. Data is shifted out, LSB first, on this pin at

the falling edge of the serial clock source.

O

Receive Serial Data

Input

URXDn

Receiver serial data inputs for the UART modules. Data is received on

this pin LSB first. When the UART clock is stopped for power-down

mode, any transition on this pin restarts it.

I

Clear-to-Send

UCTSn

URTSn

Indicate to the UART modules that they can begin data transmission.

I

Request-to-Send

Automatic request-to-send outputs from the UART modules. This

signal can also be configured to be asserted and negated as a

function of the RxFIFO level.

O

1.12 DMA Timer Signals

Table 12 describes the signals of the four DMA timer modules.

Table 12. DMA Timer Signals

Signal Name

Abbreviation

Function

I/O

DMA Timer Input

DTIN

Event input to the DMA timer modules.

I

DMA Timer Output

DTOUT

Programmable output from the DMA timer modules.

O

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

24

Freescale Semiconductor

MCF5213 Family Configurations

1.13 ADC Signals

Table 13 describes the signals of the Analog-to-Digital Converter.

Table 13. ADC Signals

Signal Name

Analog Inputs

Abbreviation

Function

Inputs to the A-to-D converter.

Reference voltage high and low inputs.

I/O

AN[7:0]

V_RH

I

Analog Reference

V_RL

Analog Supply

V_DDA

V_SSA

Isolate the ADC circuitry from power supply noise

—

1.14 General Purpose Timer Signals

Table 14 describes the General Purpose Timer Signals.

Table 14. GPT Signals

Signal Name

Abbreviation

Function

I/O

General Purpose Timer

Input/Output

GPT[3:0]

Inputs to or outputs from the general purpose timer module

I/O

1.15 Pulse Width Modulator Signals

Table 15 describes the PWM signals.

Table 15. PWM Signals

Signal Name

Abbreviation

Function

I/O

PWM Output Channels

PWM[7:0]

Pulse width modulated output for PWM channels

O

1.16 Debug Support Signals

These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM

logic.

Table 16. Debug Support Signals

Signal Name

Abbreviation

Function

I/O

JTAG Enable

Test Reset

JTAG_EN

TRST

Select between debug module and JTAG signals at reset

I

This active-low signal is used to initialize the JTAG logic

asynchronously.

Test Clock

TCLK

TMS

Used to synchronize the JTAG logic.

I

Test Mode Select

Used to sequence the JTAG state machine. TMS is sampled on the

rising edge of TCLK.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

25

MCF5213 Family Configurations

Table 16. Debug Support Signals (continued)

Function

Signal Name

Abbreviation

TDI

I/O

Test Data Input

Serial input for test instructions and data. TDI is sampled on the rising

edge of TCLK.

I

Test Data Output

TDO

Serial output for test instructions and data. TDO is tri-stateable and is

actively driven in the shift-IR and shift-DR controller states. TDO

changes on the falling edge of TCLK.

O

I

Development Serial

Clock

DSCLK

Development Serial Clock-Internally synchronized input. (The logic

level on DSCLK is validated if it has the same value on two

consecutive rising bus clock edges.) Clocks the serial communication

port to the debug module during packet transfers. Maximum frequency

is PSTCLK/5. At the synchronized rising edge of DSCLK, the data

input on DSI is sampled and DSO changes state.

Breakpoint

BKPT

Breakpoint - Input used to request a manual breakpoint. Assertion of

BKPT puts the processor into a halted state after the current

instruction completes. Halt status is reflected on processor

status/debug data signals (PST[3:0]PSTDDATA[7:0]) as the value 0xF.

If CSR[BKD] is set (disabling normal BKPT functionality), asserting

BKPT generates a debug interrupt exception in the processor.

I

Development Serial

Input

DSI

Development Serial Input -Internally synchronized input that provides

data input for the serial communication port to the debug module,

once the DSCLK has been seen as high (logic 1).

I

Development Serial

Output

DSO

Development Serial Output -Provides serial output communication for

debug module responses. DSO is registered internally. The output is

delayed from the validation of DSCLK high.

O

Debug Data

DDATA[3:0] Display captured processor data and breakpoint status. The CLKOUT

signal can be used by the development system to know when to

sample DDATA[3:0].

Processor Status Clock

PSTCLK

Processor Status Clock - Delayed version of the processor clock. Its

rising edge appears in the center of valid PST and DDATA output.

PSTCLK indicates when the development system should sample PST

and DDATA values.

If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and

PST and DDATA outputs from toggling without disabling triggers.

Non-quiescent operation can be reenabled by clearing CSR[PCD],

although the external development systems must resynchronize with

the PST and DDATA outputs.

PSTCLK starts clocking only when the first non-zero PST value (0xC,

0xD, or 0xF) occurs during system reset exception processing.

Processor Status

Outputs

PST[3:0]

ALLPST

Indicate core status. Debug mode timing is synchronous with the

processor clock; status is unrelated to the current bus transfer. The

CLKOUT signal can be used by the development system to know

when to sample PST[3:0].

O

All Processor Status

Outputs

Logical “AND” of PST[3.0]

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

26

Freescale Semiconductor

Preliminary Electrical Characteristics

1.17 EzPort Signal Descriptions

Table 17 contains a list of EzPort external signals

Table 17. EzPort Signal Descriptions

Abbreviation Function

EZPCK

Signal Name

I/O

EzPort Clock

Shift clock for EzPort transfers

I

EzPort Chip Select

EZPCS

EZPD

EZPQ

Chip select for signalling the start and end

of serial transfers

EzPort Serial Data In

EzPort Serial Data Out

EZPD is sampled on the rising edge of

EZPCK

I

EZPQ transitions on the falling edge of

EZPCK

O

1.18 Power and Ground Pins

The pins described in Table 18 provide system power and ground to the chip. Multiple pins are provided

for adequate current capability. All power supply pins must have adequate bypass capacitance for

high-frequency noise suppression.

Table 18. Power and Ground Pins

Signal Name

Abbreviation

Function

I/O

PLL Analog Supply

VDDPLL,

VSSPLL

Dedicated power supply signals to isolate the sensitive PLL analog

circuitry from the normal levels of noise present on the digital power

supply.

I

Positive Supply

Ground

VDD

VSS

These pins supply positive power to the core logic.

This pin is the negative supply (ground) to the chip.

I

2 Preliminary Electrical Characteristics

This section contains electrical specification tables and reference timing diagrams for the MCF5213

microcontroller unit. This section contains detailed information on power considerations, DC/AC

electrical characteristics, and AC timing specifications of MCF5213.

The electrical specifications are preliminary and are from previous designs or design simulations. These

specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however

for production silicon these specifications will be met. Finalized specifications will be published after

complete characterization and device qualifications have been completed.

NOTE

The parameters specified in this appendix supersede any values found in the

module specifications.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Freescale Semiconductor

27

Preliminary

Preliminary Electrical Characteristics

2.1 Maximum Ratings

1, 2

Table 19. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Supply Voltage

V_DD

V_DDPLL

V_STBY

V_IN

– 0.3 to +4.0

– 0.3 to + 4.0

0 to 3.3

V

Clock Synthesizer Supply Voltage

RAM Memory Standby Supply Voltage

Digital Input Voltage ³

EXTAL pin voltage

V_EXTAL

V_XTAL

XTAL pin voltage

0 to 3.3

Instantaneous Maximum Current

I_DD

25

mA

Single pin limit (applies to all pins) ^{4, 5}

Operating Temperature Range (Packaged)

T_A

– 40 to 85

°C

(T_L- T_H)

Storage Temperature Range

N₁OTES:

T_stg

– 65 to 150

°C

Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum

Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress

beyond those listed may affect device reliability or cause permanent damage to the device.

This device contains circuitry protecting against damage due to high static voltage or electrical

fields; however, it is advised that normal precautions be taken to avoid application of any voltages

higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is

enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either V_SSor V_DD).

Input must be current limited to the I_DDvalue specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then

use the larger of the two values.

2

3

4

5

All functional non-supply pins are internally clamped to V_SSand V_DD

.

Power supply must maintain regulation within operating V_DDrange during instantaneous and

operating maximum current conditions. If positive injection current (V_in> V_DD) is greater than I_DD

the injection current may flow out of V_DDand could result in external power supply going out of

regulation. Insure external V_DDload will shunt current greater than maximum injection current. This

will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must

maintain regulation within operating V_DDrange during instantaneous and operating maximum

current conditions.

,

2.2 Current Consumption

1,2

Table 20. Current Consumption in Low-Power Mode

Mode

8MHz (Typ)³16MHz (Typ)²64MHz (Typ)²80MHz (Typ)²80MHz (Peak)⁴

Units

Stop Mode 3 (Stop 11)⁵

Stop Mode 2 (Stop 10)⁵

Stop Mode 1 (Stop 01)^5,6

Stop Mode 0 (Stop 00)⁵

Wait / Doze

0.13

2.29

TBD

mA

2.80

3.08

4.76

5.38

5.39

11.12

12.40

20.23

22.74

30.17

39.92

33.36

45.47

Run

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

28

Freescale Semiconductor

Preliminary Electrical Characteristics

NOTES:

1

All values are measured with a 3.30V power supply

2

3

Refer to the Power Management chapter in the MCF5213 Reference Manual for more information on low-power modes.

CLKOUT and all peripheral clocks except UART0 and CFM off before entering low power mode. CLKOUT is disabled. All

code executed from FLASH. Code run from SRAM reduces power consumption further. Tests performed at room

temperature.

CLKOUT and all peripheral clocks on before entering low power mode. All code is executed from FLASH. All code is

executed at 80MHz clock.

See the description of the Low-Power Control Register (LCPR) in the MCF5213 Reference Manual for more information

on Stop modes 0–3.

Results are identical to STOP 00 for typical values since they only differ by CLKOUT power consumption. CLKOUT is

already disabled in this instance prior to entering low power mode.

4

5

6

50.00

45.00

40.00

35.00

30.00

25.00

20.00

15.00

10.00

5.00

Stop 0 - Flash

Stop 1 - Flash

Stop 2 - Flash

Stop 3 - Flash

Wait/Doze - Flash

Run - Flash

0.00

0

8

16

24

32

40

48

56

64

72

80

System Clock (MHz)

Typical Current Consumption in Low-Power Modes

Table 21. Typical Active Current Consumption Specifications

Typical¹

Active

Typical¹

Active

Characteristic

Symbol

Peak²

Unit

(SRAM)

(Flash)

• 1 MHz core & I/O

• 8 MHz core & I/O

• 16 MHz core & I/O

• 64 MHz core & I/O

• 80 MHz core & I/O

I_DD

TBD

7.28

3.48

TBD

19.02

35.66

85.01

100.03

mA

13.37

25.08

54.62

64.09

12.08

40.14

49.2

RAM Memory Standby Supply Current

I_STBY

Normal Operation: V_DD> V_STBY- 0.3 V

Transient Condition: V_STBY- 0.3 V > V_DD> V_SS+ 0.5 V

Standby Operation: V_DD< V_SS+ 0.5 V

0

TBD

µA

mA

µA

Analog Supply Current

Normal Operation

Low-Power Stop

I_DDA

—

TBD

mA

µA

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

29

Preliminary Electrical Characteristics

N₁OTES:

Tested at room temperature with CPU polling a status register. All clocks were off except the UART and CFM (when

running from Flash).

2

Peak current measured with all modules active, and default drive strength with matching load.

2.3 Thermal Characteristics

Table 22 lists thermal resistance values.

Table 22. Thermal Characteristics

Characteristic

Symbol

Value

Unit

100 LQFP

Junction to ambient, natural convection

Junction to ambient, (@200 ft/min)

Junction to board

Single Layer board (1s)

Four layer board (2s2p)

Single Layer board (1s)

Four layer board (2s2p)

θ_JA

θ_JMA

θ_JB

θ_JC

Ψ_jt

53^1,2

39^1,3

42^1,3

33^1,3

25⁴

°C/W

^oC

Junction to case

9⁵

Junction to top of package

Natural convection

2⁶

Maximum operating junction temperature

T_j

105

61^1,2

35^2,3

50^2,3

31^2,3

20⁴

81 MAPBGA Junction to ambient, natural convection

Junction to ambient, natural convection

Junction to ambient, (@200 ft/min)

Junction to board

Single Layer board (1s)

Four layer board (2s2p)

Single Layer board (1s)

Four layer board (2s2p)

θ_JA

θ_JMA

θ_JB

θ_JC

Ψ_jt

°C/W

^oC

Junction to case

12⁵

Junction to top of package

Natural convection

2⁶

Maximum operating junction temperature

T_j

105

62^1,2

43^1,3

50^1,3

36^1,3

26⁴

64 LQFP

Junction to ambient, natural convection

Junction to ambient (@200 ft/min)

Junction to board

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

θ_JA

θ_JMA

θ_JB

θ_JC

Ψ_jt

°C/W

^oC

Junction to case

9⁵

Junction to top of package

Natural convection

2⁶

Maximum operating junction temperature

T_j

105

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

30

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 22. Thermal Characteristics (continued)

Characteristic

Symbol

Value

Unit

64 QFN

Junction to ambient, natural convection

Junction to ambient (@200 ft/min)

Junction to board

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

θ_JA

θ_JMA

θ_JB

θ_JC

Ψ_jt

68^1,2

24^1,3

55^1,3

19^1,3

8⁴

°C/W

^oC

Junction to case (bottom)

0.6⁵

3⁶

Junction to top of package

Natural convection

Maximum operating junction temperature

T_j

105

NOTES:

1

θ

_JAand Ψ_jtparameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale

recommends the use of θ_JAand power dissipation specifications in the system design to prevent device junction

temperatures from exceeding the rated specification. System designers should be aware that device junction

temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device

junction temperature specification can be verified by physical measurement in the customer’s system using the Ψ_jt

parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.

Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.

Per JEDEC JESD51-6 with the board JESD51-7) horizontal.

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is

written in conformance with Psi-JT.

2

3

4

5

6

The average chip-junction temperature (T_J) in °C can be obtained from:

(1)

T_J= T_A+ (P_D× Θ_JMA

)

Where:

T_A

= Ambient Temperature, °C

Θ_JA

P_D

= Package Thermal Resistance, Junction-to-Ambient, °C/W

= P_INT+ P_I/O

P_INT

P_I/O

= I_DD× V_DD, Watts - Chip Internal Power

= Power Dissipation on Input and Output Pins — User Determined

For most applications P_I/O< P_INTand can be ignored. An approximate relationship between P_Dand T_J(if P_I/Ois neglected) is:

P_D= K ÷ (T_J+ 273°C)

(2)

Solving equations 1 and 2 for K gives:

K = P_D× (T_A+ 273 °C) + Θ_JMA× P_D

2

(3)

where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P_D(at equilibrium)

for a known T_A. Using this value of K, the values of P_Dand T_Jcan be obtained by solving equations (1) and (2) iteratively for

any value of T_A.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Freescale Semiconductor

31

Preliminary

Preliminary Electrical Characteristics

2.4 Flash Memory Characteristics

The Flash memory characteristics are shown in Table 23 and Table 24.

Table 23. SGFM Flash Program and Erase Characteristics

(V_DDF= 2.7 to 3.6 V)

Parameter

System clock (read only)

Symbol

Min

Typ

Max

Unit

f_sys(R)

0

—

80

MHz

System clock (program/erase)¹

NOTES:

f_sys(P/E)

0.15

1

Refer to the Flash section for more information

Table 24. SGFM Flash Module Life Characteristics

(V_DDF= 2.7 to 3.6 V)

Parameter

Symbol

Value

Unit

Maximum number of guaranteed program/erase cycles¹before failure

Data retention at average operating temperature of 85°C

NOTES:

P/E

10,000²

10

Cycles

Years

Retention

1

A program/erase cycle is defined as switching the bits from 1 → 0 → 1.

2

Reprogramming of a Flash array block prior to erase is not required.

2.5 ESD Protection

1, 2

Table 25. ESD Protection Characteristics

Characteristics

Symbol

Value

Units

ESD Target for Human Body Model

ESD Target for Machine Model

HBM Circuit Description

HBM

MM

2000

200

1500

100

0

V

R_series

C

ohms

pF

MM Circuit Description

R_series

C

ohms

pF

200

Number of pulses per pin (HBM)

positive pulses

negative pulses

—

1

Number of pulses per pin (MM)

positive pulses

negative pulses

—

3

Interval of Pulses

N₁OTES:

—

1

sec

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for

Automotive Grade Integrated Circuits.

2

A device is defined as a failure if after exposure to ESD pulses the device no longer meets

the device specification requirements. Complete DC parametric and functional testing is

performed per applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

32

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

2.6 DC Electrical Specifications

1

Table 26. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Supply Voltage

V_DD

V_IH

3.0

3.6

4.0

V

Input High Voltage

Input Low Voltage

Input Hysteresis

0.7 x V_DD

V_SS– 0.3

0.06 x V_DD

–1.0

V_IL

0.35 x V_DD

—

V

V_HYS

I_in

mV

µA

Input Leakage Current

1.0

V_in= V_DDor V_SS, digital pins

Output High Voltage (All input/output and all output pins)

I_OH= –2.0 mA

V_OH

V_OL

V_OH

V_OL

V_OH

V_OL

OV_DD- 0.5

__

0.5

__

V

Output Low Voltage (All input/output and all output pins)

I_OL= 2.0mA

Output High Voltage (High Drive)

I_OH= TBD

OV_DD- 0.5

__

Output Low Voltage (High Drive)

I_OL= TBD

0.5

__

Output High Voltage (Low Drive)

I_OH= TBD

OV_DD- 0.5

__

Output Low Voltage (Low Drive)

I_OL= TBD

Weak Internal Pull Up Device Current, tested at V_ILMax.²

0.5

- 130

I_APU

C_in

-10

µA

Input Capacitance ³

pF

All input-only pins

All input/output (three-state) pins

—

7

N₁OTES:

Refer to Table 27 for additional PLL specifications.

Refer to the MCF5213 signals chapter for pins having weak internal pull-up devices.

This parameter is characterized before qualification rather than 100% tested.

2

3

2.7 Clock Source Electrical Specifications

Table 27. PLL Electrical Specifications

(V_DDand V_DDPLL= 2.7 to 3.6 V, V_SS= V_SSPLL= 0 V)

Characteristic

Symbol

Min

Max

Unit

PLL Reference Frequency Range

Crystal reference

MHz

f_{ref_crystal}

f_{ref_ext}

2

10.0

External reference

System Frequency ¹

External Clock Mode

On-Chip PLL Frequency

f_sys

MHz

0

80

f_ref/ 32

Loss of Reference Frequency ^{2, 4}

Self Clocked Mode Frequency ^{3, 4}

Crystal Start-up Time ^{4, 5}

f_LOR

f_SCM

t_cst

100

1

1000

5

kHz

MHz

ms

—

10

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

33

Preliminary Electrical Characteristics

Table 27. PLL Electrical Specifications (continued)

(V_DDand V_DDPLL= 2.7 to 3.6 V, V_SS= V_SSPLL= 0 V)

Characteristic

Symbol

Min

Max

Unit

EXTAL Input High Voltage

External reference

V_IHEXT

V

2.0

V_DD

EXTAL Input Low Voltage

External reference

V_ILEXT

V

V_SS

—

0.8

500

60

PLL Lock Time^4,6

t_lpll

t_dc

µs

Duty Cycle of reference ⁴

Frequency un-LOCK Range

Frequency LOCK Range

40

% f_ref

f_UL

- 1.5

- 0.75

1.5

f_LCK

C_jitter

0.75

CLKOUT Period Jitter ^{4, 5, 7, 7,8}, Measured at f_SYSMax

Peak-to-peak Jitter (Clock edge to clock edge)

Long Term Jitter (Averaged over 2 ms interval)

—

10

.01

% f_sys

MHz

On-chip oscillator frequency

f_oco

7.84

8.16

NOTES:

1

All internal registers retain data at 0 Hz.

“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self

clocked mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below

f_LORwith default MFD/RFD settings.

This parameter is characterized before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits

in the synthesizer control register (SYNCR).

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum

f_sys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock

signal. Noise injected into the PLL circuitry via V_DDPLLand V_SSPLLand variation in crystal oscillator frequency

increase the Cjitter percentage for a given interval

2

3

4

5

6

7

8

Based on slow system clock of 40 MHz measured at f_sysmax.

2.8 General Purpose I/O Timing

GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1,

Interrupts and USB interfaces. When in GPIO mode, the timing specification for these pins is given in

Table 28 and Figure 5.

Table 28. GPIO Timing

NUM

Characteristic

Symbol

Min

Max

Unit

G1

G2

G3

G4

CLKOUT High to GPIO Output Valid

CLKOUT High to GPIO Output Invalid

GPIO Input Valid to CLKOUT High

CLKOUT High to GPIO Input Invalid

t_CHPOV

t_CHPOI

t_PVCH

t_CHPI

-

10

-

ns

1.5

9

-

1.5

-

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

34

Freescale Semiconductor

Preliminary Electrical Characteristics

CLKOUT

G2

G1

GPIO Outputs

G3

G4

GPIO Inputs

Figure 5. GPIO Timing

2.9 Reset Timing

Table 29. Reset and Configuration Override Timing

(V_DD= 2.7 to 3.6 V, V_SS= 0 V, T_A= T_Lto T_H)¹

NUM

Characteristic

Symbol

Min

Max

Unit

R1 RSTI Input valid to CLKOUT High

R2 CLKOUT High to RSTI Input invalid

R3 RSTI Input valid Time ²

t_RVCH

t_CHRI

9

1.5

5

-

ns

t_RIVT

-

t_CYC

ns

R4 CLKOUT High to RSTO Valid

t_CHROV

-

10

N₁OTES:

All AC timing is shown with respect to 50% O V_DDlevels unless otherwise noted.

During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to

the system. Thus, RSTI must be held a minimum of 100 ns.

2

CLKOUT

1R1

R2

R3

RSTI

R4

RSTO

Figure 6. RSTI and Configuration Override Timing

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

35

Preliminary Electrical Characteristics

2.10 I²C Input/Output Timing Specifications

2

Table 30 lists specifications for the I C input timing parameters shown in Figure 7.

2

Table 30. I C Input Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

11

I2

I3

I4

I5

I6

I7

I8

I9

2 x t_CYC

8 x t_CYC

—

1

ns

Clock low period

SCL/SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

mS

ns

0

—

1

SCL/SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

mS

ns

4 x t_CYC

0

—

Data setup time

ns

Start condition setup time (for repeated start condition only)

Stop condition setup time

2 x t_CYC

ns

2

Table 31 lists specifications for the I C output timing parameters shown in Figure 7.

2

Table 31. I C Output Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

11¹

I2¹

I3²

6 x t_CYC

10 x t_CYC

—

ns

µS

Clock low period

I2C_SCL/I2C_SDA rise time

(V_IL= 0.5 V to V_IH= 2.4 V)

I4¹

I5³

Data hold time

7 x t_CYC

—

3

ns

I2C_SCL/I2C_SDA fall time

(V_IH= 2.4 V to V_IL= 0.5 V)

I6¹

I7¹

I8¹

Clock high time

Data setup time

10 x t_CYC

2 x t_CYC

—

ns

Start condition setup time (for repeated start

condition only)

20 x t_CYC

I9¹

Stop condition setup time

10 x t_CYC

—

ns

N₁OTES:

Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with

the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 31. The

I²C interface is designed to scale the actual data transition time to move it to the middle of the SCL

low period. The actual position is affected by the prescale and division values programmed into the

IFDR; however, the numbers given in Table 31 are minimum values.

Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive

low, the time SCL or SDA take to reach a high level depends on external signal capacitance and

pull-up resistor values.

2

3

Specified at a nominal 50-pF load.

Figure 7 shows timing for the values in Table 30 and Table 31.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

36

Freescale Semiconductor

Preliminary Electrical Characteristics

I2

I6

I5

SCL

SDA

I3

I1

I4

I8

I9

I7

2

Figure 7. I C Input/Output Timings

2.11 Analog-to-Digital Converter (ADC) Parameters

Table 32 lists specifications for the analog-to-digital converter.

1

Table 32. ADC Parameters

Name

Characteristic

Low reference voltage

Min

Typical

Max

Unit

V_REFL

V_REFH

V_DDA

V_ADIN

R_ES

V_SS

V_REFL

3.0

—

V_REFH

V_DDA

3.6

V

High reference voltage

ADC analog supply voltage

Input voltages

—

3.3

V

V_REFL

12

—

V_REFH

12

V

Resolution

—

2.5

Bits

LSB³

LSB

INL

Integral Non-Linearity (Full input signal range)²

Integral Non-Linearity (10% to 90% input signal range)⁴

Differential Non-Linearity

Monotonicity

—

3

INL

—

2.5

3

DNL

—

-1 < DNL < +1

<+1

GUARANTEED

f_ADIC

R_AD

ADC internal clock

0.1

V_REFL

—

5.0

V_REFH

13

MHz

Conversion Range

—

V

t_ADPU

t_REC

t_ADC

t_ADS

C_ADI

X_IN

ADC power-up time⁵

Recovery from auto standby

Conversion time

6

t_AICcycles⁶

—

0

1

t_AICcycles

—

6

—

t_AICcycles

Sample time

—

1

—

t_AICcycles

Input capacitance

—

See Figure 8

—

pF

Ω

Input impedance

See Figure 8

I_ADI

Input injection current⁷, per pin

—

3

mA

µ

I_VREFH

V_REFHcurrent

0

—

V_OFFSETOffset voltage internal reference

E_GAINGain Error (transfer path)

V_OFFSETOffset voltage external reference

—

8

15

mV

—

.99

—

1

3

1.01

TBD

mV

dB

SNR

Signal-to-Noise ratio

TBD

62 to 66

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

37

Preliminary Electrical Characteristics

1

Table 32. ADC Parameters (continued)

Name

Characteristic

Total Harmonic Distortion

Min

Typical

Max

Unit

THD

SFDR

SINAD

ENOB

TBD

-75

dB

Spurious Free Dynamic Range

Signal-to-Noise plus Distortion

Effective Number OF Bits

TBD

9.1

67 to 70.3

61 to 63.9

10.6

dB

Bits

NOTES:

1

All measurements are preliminary pending full characterization, and were made at V_DD= 3.3V, V_REFH= 3.3V, and V_REFL

=

ground

2

3

4

5

6

7

INL measured from V_IN= V_REFLto V_IN= V_REFH

LSB = Least Significant Bit

INL measured from V_IN= 0.1V_REFHto V_IN= 0.9V_REFH

Includes power-up of ADC and V_REF

ADC clock cycles

The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the

ADC

2.11.1 Equivalent Circuit for ADC Inputs

Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at

the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and

hold circuit moves to (V_REFH-V_REFL)/2, while the other charges to the analog input voltage. When the

switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended

analog input is switched to a differential voltage centered about (V_REFH-V_REFL)/2. The switches switch on

every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there are

additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the

S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is

that there is an on-going input current, which is a function of the analog input voltage, V_REFand the ADC

clock frequency.

125Ω ESD Resistor

8pF noise damping capacitor

3

4

Analog Input

S1

C1

C2

S/H

S3

S2

(V_REFH- V_{REFL )}/ 2

2

1

C1 = C2 = 1pF

1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF

3. Equivalent resistance for the channel select mux; 100 ohms

4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only

connected to it at sampling time; 1.4pF

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

38

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

1

5. Equivalent input impedance, when the input is selected =

(ADC Clock Rate) x 1.4 x 10^-12

Figure 8. Equivalent Circuit for A/D Loading

2.12 DMA Timers Timing Specifications

Table 33 lists timer module AC timings.

Table 33. Timer Module AC Timing Specifications

Name

Characteristic¹

Min

Max

Unit

T1

T2

DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time

DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width

3 x t_CYC

1 x t_CYC

—

ns

N₁OTES:

All timing references to CLKOUT are given to its rising edge.

2.13 QSPI Electrical Specifications

Table 34 lists QSPI timings.

Table 34. QSPI Modules AC Timing Specifications

Name

Characteristic

Min

Max

Unit

QS1

QS2

QS3

QS4

QS5

QSPI_CS[3:0] to QSPI_CLK

1

—

2

510

10

—

t_CYC

ns

QSPI_CLK high to QSPI_DOUT valid.

QSPI_CLK high to QSPI_DOUT invalid (Output hold)

QSPI_DIN to QSPI_CLK (Input setup)

QSPI_DIN to QSPI_CLK (Input hold)

ns

9

—

ns

9

—

ns

The values in Table 34 correspond to Figure 9.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

39

Preliminary Electrical Characteristics

QS1

QSPI_CS[3:0]

QSPI_CLK

QS2

QSPI_DOUT

QS3

QS4

QS5

QSPI_DIN

Figure 9. QSPI Timing

2.14 JTAG and Boundary Scan Timing

Table 35. JTAG and Boundary Scan Timing

Num

Characteristics¹

TCLK Frequency of Operation

Symbol

Min

Max

Unit

J1

J2

f_JCYC

t_JCYC

DC

1/4

-

f_sys/2

ns

TCLK Cycle Period

4 x t_CYC

J3

TCLK Clock Pulse Width

t_JCW

26

0

-

J4

TCLK Rise and Fall Times

t_JCRF

3

-

J5

Boundary Scan Input Data Setup Time to TCLK Rise

Boundary Scan Input Data Hold Time after TCLK Rise

TCLK Low to Boundary Scan Output Data Valid

TCLK Low to Boundary Scan Output High Z

TMS, TDI Input Data Setup Time to TCLK Rise

TMS, TDI Input Data Hold Time after TCLK Rise

TCLK Low to TDO Data Valid

t_BSDST

t_BSDHT

t_BSDV

4

J6

26

0

-

J7

33

-

J8

t_BSDZ

0

J9

t_TAPBST

t_TAPBHT

t_TDODV

t_TDODZ

t_TRSTAT

t_TRSTST

4

J10

J11

J12

J13

10

0

-

26

8

-

TCLK Low to TDO High Z

0

TRST Assert Time

100

10

J14

TRST Setup Time (Negation) to TCLK High

-

N₁OTES:

JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

40

Freescale Semiconductor

Preliminary Electrical Characteristics

J2

J3

V_IH

TCLK

(input)

V_IL

J4

Figure 10. Test Clock Input Timing

TCLK

V_IL

V_IH

J5

J6

Data Inputs

Input Data Valid

J7

J8

Data Outputs

Output Data Valid

Data Outputs

J7

Output Data Valid

Figure 11. Boundary Scan (JTAG) Timing

TCLK

V_IL

V_IH

J9

Input Data Valid

J10

TDI

TMS

J11

TDO

Output Data Valid

J12

J11

TDO

Output Data Valid

Figure 12. Test Access Port Timing

TCLK

TRST

14

13

Figure 13. TRST Timing

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

41

Preliminary Electrical Characteristics

2.15 Debug AC Timing Specifications

Table 36 lists specifications for the debug AC timing parameters shown in Figure 15.

Table 36. Debug AC Timing Specification

166 MHz

Num

Characteristic

Units

Min

Max

D0

D1

PSTCLK cycle time

0.5

t_CYC

ns

PST, DDATA to CLKOUT setup

CLKOUT to PST, DDATA hold

DSI-to-DSCLK setup

4

1.5

D2

D3

1 x t_CYC

4 x t_CYC

5 x t_CYC

4

D4¹

DSCLK-to-DSO hold

D5

DSCLK cycle time

D6

BKPT input data setup time to CLKOUT Rise

BKPT input data hold time to CLKOUT Rise

CLKOUT high to BKPT high Z

D7

1.5

D8

0.0

10.0

N₁OTES:

DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative

to the rising edge of CLKOUT.

Figure 14 shows real-time trace timing for the values in Table 36.

CLKOUT

D1

D2

PST[3:0]

DDATA[3:0]

Figure 14. Real-Time Trace AC Timing

Figure 15 shows BDM serial port AC timing for the values in Table 36.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

42

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

CLKOUT

DSCLK

DSI

D5

D3

Current

Past

DSO

Current

Figure 15. BDM Serial Port AC Timing

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

43

Mechanical Outline Drawings

3 Mechanical Outline Drawings

This section describes the physical properties of the MCF5213 and its derivatives.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

44

Freescale Semiconductor

Preliminary

Mechanical Outline Drawings

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

45

Mechanical Outline Drawings

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

46

Freescale Semiconductor

Mechanical Outline Drawings

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

47

Mechanical Outline Drawings

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

48

Freescale Semiconductor

Mechanical Outline Drawings

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

49

Mechanical Outline Drawings

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

50

Freescale Semiconductor

Mechanical Outline Drawings

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

51

Mechanical Outline Drawings

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

52

Freescale Semiconductor

Mechanical Outline Drawings

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

53

Mechanical Outline Drawings

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

54

Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Preliminary

Freescale Semiconductor

55

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MCF5213EC

Rev. 1.2, 01/2006


型号：	MCF5213
厂家：	Freescale
描述：	Microcontroller Family Hardware Specification 单片机系列硬件规格微控制器
文件：	总56页 (文件大小：865K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCF5213 [FREESCALE]

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MCF5213CAF66R

MCF5213CAF80

MCF5213CAF80

MCF5213LCVM66

MCF5213LCVM66

MCF5213LCVM66J

MCF5213LCVM80

MCF5213LCVM80

MCF5213LCVM80J

MCF5213_07