MCF5372_技术文档

MCF5373DS

Rev. 0.3, 04/2006

Freescale Semiconductor

Data Sheet: Advance Information

MCF5373 ColdFire^®

Microprocessor Data Sheet

Supports MCF5372L, MCF5372, MCF5373L, & MCF5373

by: Microcontroller Division

Table of Contents

The MCF537x devices are a family of highly-integrated

32-bit microprocessors based on the Version 3 ColdFire

microarchitecture. All MCF537x devices contain a

32-Kbyte internal SRAM, a Fast Ethernet controller, a

2-bank SDR/DDR SDRAM controller, a 16-channel

DMA controller, up to three UARTs, a queued SPI, as

well as other peripherals that enable the MCF537x

family for use in general purpose industrial control

applications. Optional peripherals include USB host and

On-the-Go controllers and cryptography hardware

accelerators.

1

2

3

4

5

6

MCF537x Family Configurations .........................2

Ordering Information ...........................................3

Signal Descriptions..............................................3

Mechanicals and Pinouts ....................................8

Preliminary Electrical Characteristics................14

Revision History ................................................40

This document provides an overview of the MCF537x

microprocessor family, focusing on its highly diverse

feature set. It was written from the perspective of the

MCF5373L device. However, it also pertains to the

MCF5372L, MCF5372, and MCF5373. See the

following section for a summary of differences between

the various devices of the MCF537x family.

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

• Preliminary

MCF537x Family Configurations

1 MCF537x Family Configurations

The following table compares the various device derivatives available within the MCF537x family.

Table 1. MCF537x Family Configurations

Module

MCF5372 MCF5372L MCF5373 MCF5373L

ColdFire Version 3 Core with EMAC

(Enhanced Multiply-Accumulate Unit)

x

Core (System) Clock

up to

180 MHz

240 MHz

180 MHz

240 MHz

Peripheral and External Bus Clock

up to

(Core clock ÷ 3)

60 MHz

80 MHz

60 MHz

80 MHz

Performance (Dhrystone/2.1 MIPS)

Instruction/Data Cache

Static RAM (SRAM)

up to 158 up to 211 up to 158 up to 211

16 Kbytes

32 Kbytes

SDR/DDR SDRAM Controller

USB 2.0 Host

x

—

x

—

x

USB 2.0 On-the-Go

—

x

—

x

Synchronous Serial Interface (SSI)

Fast Ethernet Controller (FEC)

Cryptography Hardware Accelerators

UARTs

x

—

x

3

I²C

x

QSPI

x

PWM Module

—

x

—

x

Real Time Clock

x

32-bit DMA Timers

4

Watchdog Timer (WDT)

Periodic Interrupt Timers (PIT)

Edge Port Module (EPORT)

Interrupt Controllers (INTC)

16-channel Direct Memory Access (DMA)

FlexBus External Interface

General Purpose I/O (GPIO)

JTAG - IEEE^®1149.1 Test Access Port

Package

x

4

x

2

x

up to 62

x

up to 62

x

up to 46

x

up to 46

x

160 QFP

196

160 QFP

196

MAPBGA

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

2

Freescale Semiconductor

Ordering Information

2 Ordering Information

Table 2. Orderable Part Numbers

Freescale Part

Number

Description

Speed

Temperature

MCF5372CAB180

MCF5372LCVM240

MCF5373CAB180

MCF5373LCVM240

MCF5372 RISC Microprocessor, 160 QFP

MCF5372 RISC Microprocessor, 196 MAPBGA

MCF5373 RISC Microprocessor, 160 QFP

MCF5373 RISC Microprocessor, 256 MAPBGA

180 MHz

240 MHz

180 MHz

240 MHz

–40° to +85° C

3 Signal Descriptions

The following table lists all the MCF537x pins grouped by function. The “Dir” column is the direction for

the primary function of the pin only. Refer to Section 4, “Mechanicals and Pinouts,” for package diagrams.

For a more detailed discussion of the MCF537x signals, consult the MCF5373 Reference Manual

(MCF5373RM).

NOTE

In this table and throughout this document a single signal within a group is

designated without square brackets (i.e., A23), while designations for

multiple signals within a group use brackets (i.e., A[23:21]) and is meant to

include all signals within the two bracketed numbers when these numbers

are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality.

Pins that are muxed with GPIO will default to their GPIO functionality.

Table 3. MCF5372/3 Signal Information and Muxing

MCF5372

MCF5373

160 QFP

MCF5372L

MCF5373L

196 MAPBGA

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

Reset

RESET²

RSTOUT

—

I

95

86

K13

L12

O

Clock

EXTAL

XTAL²

—

I

91

93

—

L14

K14

P13

N13

O

I

EXTAL32K

XTAL32K

O

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

3

Signal Descriptions

Table 3. MCF5372/3 Signal Information and Muxing (continued)

MCF5372

MCF5372L

MCF5373L

196 MAPBGA

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

MCF5373

160 QFP

FB_CLK

—

O

40

N1

Mode Selection

RCON²

—

I

72

92

P8

DRAMSEL

J11

FlexBus

A[23:22]

A[21:16]

—

FB_CS[5:4]

—

O

134, 133

132–127

A9, B9

C9, D9, A10,

B10, C10, D10

A[15:14]

A[13:11]

A10

—

SD_BA[1:0]

SD_A[13:11]

—

O

126, 123

120–118

11

A11, B11

C11, A12, B12

A13

A[9:0]

SD_A[9:0]

116–107

A14, B14, B13,

C12, D11, C14,

C13, D14–D12

D[31:16]

D[15:1]

—

SD_D[31:16]³

FB_D[31:17]³

—

O

27–34, 46–53

16–23, 57–63

J2, J1, K4–K1,

L4, L3, N2, P1,

P2, N3, L5, P3,

N4, P4

F2, F1, G4–G1,

H4, H3, L6, M6,

N6, P6, L7, M7,

N7

D0²

BE/BWE[3:0]

OE

—

FB_D[16]³

—

O

I

64

P7

PBE[3:0]

SD_DQM[3:0]

26, 54, 24, 56

J3, M5, H2, P5

PBUSCTL3

PBUSCTL2

PBUSCTL1

PBUSCTL0

—

66

106

65

M8

E14

L8

TA²

R/W

—

O

TS

DACK0

12

E2

Chip Selects

FB_CS[5:4]

FB_CS[3:2]

FB_CS1

PCS[5:4]

PCS[3:2]

PCS1

—

O

—

D8, C8

B8, A8

D7

135

136

FB_CS0

—

C7

SDRAM Controller

SD_A10

SD_CKE

—

O

43

14

M2

F4

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

4

Freescale Semiconductor

Signal Descriptions

Table 3. MCF5372/3 Signal Information and Muxing (continued)

MCF5372

MCF5372L

MCF5373L

196 MAPBGA

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

MCF5373

160 QFP

SD_CLK

—

O

37

38

15

25

55

44

45

35

13

L1

M1

F3

H1

N5

M3

M4

L2

SD_CS0

SD_DQS3

SD_DQS2

SD_SCAS

SD_SRAS

SD_SDR_DQS

SD_WE

E1

External Interrupts Port⁴

IRQ7²

IRQ6²

PIRQ7²

PIRQ6²

—

I

102

—

F13

F12

USBHOST_

VBUS_EN²

IRQ5²

PIRQ5²

USBHOST_

VBUS_OC²

—

I

—

F11

IRQ4²

IRQ3²

IRQ2²

IRQ1²

PIRQ4²

PIRQ3²

PIRQ2²

PIRQ1²

SSI_MCLK²

—

I

101

—

G14

G13

G12

G11

—

USB_CLKIN²

DREQ1²

—

SSI_CLKIN

100

FEC

FEC_MDC

FEC_MDIO

FEC_COL

PFECI2C3

PFECI2C2

PFECH7

PFECH6

PFECH5

PFECH4

PFECH[3:0]

PFECL7

I2C_SCL²

—

O

I/O

I

4

3

B1

I2C_SDA²

A1

—

144

B6

FEC_CRS

I

145

A6

FEC_RXCLK

FEC_RXDV

FEC_RXD[3:0]

FEC_RXER

FEC_TXCLK

FEC_TXEN

FEC_TXER

FEC_TXD[3:0]

I

146

A5

I

147

B5

I

148–151

152

C5, D5, A4, B4

I

C4

PFECL6

I

153

A3

PFECL5

O

154

B3

A2

PFECL4

155

PFECL[3:0]

157, 158, 1, 2

D4, C3, B2, C2

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

5

Signal Descriptions

Signal Name

Table 3. MCF5372/3 Signal Information and Muxing (continued)

MCF5372

MCF5372L

MCF5373L

196 MAPBGA

GPIO

Alternate 1

Alternate 2 Dir.¹

MCF5373

160 QFP

USB Host & USB On-the-Go

USBOTG_M

USBOTG_P

USBHOST_M

USBHOST_P

—

I/O

—

H14

H13

J13

J12

PWM

PWM7

PWM5

PWM3

PWM1

PPWM7

PPWM5

PPWM3

PPWM1

—

I/O

—

E13

E12

E11

F14

—

DT3OUT

DT2OUT

DT3IN

DT2IN

SSI

The SSI signals do not have dedicated bond pads. Please refer to the following pins for muxing: IRQ4 for SSI_MCLK,

IRQ1 for SSI_CLKIN, U1CTS for SSI_BCLK, U1RTS for SSI_FS, U1RXD for SSI_RXD, and U1TXD for SSI_TXD

I²C

I2C_SCL²

I2C_SDA²

PFECI2C1

PFECI2C0

—

U2TXD

U2RXD

I/O

—

E3

E4

DMA

DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:

TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.

QSPI

QSPI_CS2

QSPI_CS1

PQSPI5

PQSPI4

U2RTS

PWM7

—

O

78

—

N12

M12

USBOTG_

PU_EN

QSPI_CS0

QSPI_CLK

QSPI_DIN

PQSPI3

PQSPI2

PQSPI1

PQSPI0

PWM5

I2C_SCL²

U2CTS

—

O

I

—

77

75

76

M11

P12

P11

N11

QSPI_DOUT

I2C_SDA²

O

UARTs

U1CTS

U1RTS

U1TXD

U1RXD

U0CTS

PUARTL7

PUARTL6

PUARTL5

PUARTL4

PUARTL3

SSI_BCLK

SSI_FS

SSI_TXD²

SSI_RXD²

—

I

O

I

143

142

141

140

85

C6

D6

A7

B7

I

M14

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

6

Freescale Semiconductor

Signal Descriptions

Table 3. MCF5372/3 Signal Information and Muxing (continued)

MCF5372

MCF5372L

MCF5373L

196 MAPBGA

Signal Name

GPIO

Alternate 1

Alternate 2 Dir.¹

MCF5373

160 QFP

U0RTS

U0TXD

U0RXD

PUARTL2

PUARTL1

PUARTL0

—

O

I

84

83

80

M13

N14

P14

Note: The UART2 signals are multiplexed on the QSPI, DMA Timers, and I2C pins.

DMA Timers

DT3IN

DT2IN

DT1IN

DT0IN

PTIMER3

PTIMER2

PTIMER1

PTIMER0

DT3OUT

DT2OUT

DT1OUT

DT0OUT

U2RXD

U2TXD

DACK1

DREQ0²

I

8

7

6

5

D1

C1

D2

D3

BDM/JTAG⁵

JTAG_EN⁶

DSCLK

PSTCLK

BKPT

—

TRST²

TCLK²

TMS²

TDI²

TDO

—

I

96

88

70

87

90

74

—

G10

K11

O

I

N8

L13

DSI

I

K12

DSO

O

L11

DDATA[3:0]

PST[3:0]

L9, M9, N9, P9

—

L10, M10, N10,

P10

ALLPST

TEST⁶

EVDD

IVDD

—

O

I

73

—

Test

—

124

E10

Power Supplies

—

9, 69, 71, 81, 94, E6, E7, F5–F7,

103, 139, 160

G5, H10, J8,

K8–K9

—

36, 79, 97, 125, E5, J9, K5, K10

156

PLL_VDD

SD_VDD

—

99

J10

11, 39, 41, 67, E8–E9, F8–F10,

105, 121, 137

J4–J7, H5, K6,

K7

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

7

Mechanicals and Pinouts

Signal Name

Table 3. MCF5372/3 Signal Information and Muxing (continued)

MCF5372

MCF5372L

MCF5373L

196 MAPBGA

GPIO

Alternate 1

Alternate 2 Dir.¹

MCF5373

160 QFP

USBOTG_VDD

VSS

—

H12

10, 42, 68, 82, G6–G9, H6–H9

89, 104, 122,

138, 159

PLL_VSS

—

98

—

H11

J14

USBHOST_VSS

NOTES:

1

Refers to pin’s primary function.

Pull-up enabled internally on this signal for this mode.

2

3

Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by

negating the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.

GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the

alternate functions.

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for

assigning these pins.

4

5

6

Pull-down enabled internally on this signal for this mode.

4 Mechanicals and Pinouts

This section contains drawings showing the pinout and the packaging and mechanical characteristics of

the MCF537x devices.

NOTE

The mechanical drawings are the latest revisions at the time of publication

of this document. The most up-to-date mechanical drawings can be found at

the product summary page located at http://www.freescale.com/coldfire.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

8

Freescale Semiconductor

Preliminary

Mechanicals and Pinouts

4.1 Pinout—196 MAPBGA

The pinout for the MCF5373LCVM240 and MCF5372LCVM240 packages are shown below.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

FEC_

MDIO

FEC_

TXER

FEC_

TXCLK

FEC_

RXD1

FEC_

RXCLK

FEC_

CRS

A

B

C

D

E

F

U1TXD FB_CS2

U1RXD FB_CS3

A23

A19

A15

A12

A10

A9

A

B

C

D

E

F

FEC_

MDC

FEC_

TXD1

FEC_

TXEN

FEC_

RXD0

FEC_

RXDV

FEC_

COL

A22/

A21

A20

A18

A17

A14

A13

A11

A6

A7

A3

A8

A4

FEC_

TXD0

FEC_

TXD2

FEC_

RXER

FEC_

RXD3

DT2IN

DT3IN

SD_WE

D14

U1CTS FB_CS0 FB_CS4

U1RTS FB_CS1 FB_CS5

FEC_

TXD3

FEC_

RXD2

DT1IN

TS

DT0IN

A16

A5

A0

A1

A2

I2C_SCL I2C_SDA IVDD

SD_CS0 SD_CKE EVDD

EVDD

VSS

EVDD SD_VDD SD_VDD

TEST

PWM3

PWM5

IRQ6

IRQ2

PWM7

IRQ7

IRQ3

TA

D15

D11

EVDD SD_VDD SD_VDD SD_VDD IRQ5

JTAG_

PWM1

IRQ4

G

H

J

D10

D12

D8

D13

D9

EVDD

VSS

IRQ1

G

H

J

EN

SD_

DQS3

BE/

BWE1

PLL_ USBOTG

VSS

USB

OTG_P

USB

OTG_M

SD_VDD

VSS

EVDD

_VDD

BE/

BWE3

PLL_

VDD

DRAM

SEL

USB

USBHOST

_VSS

D30

D26

D31

D27

SD_VDD SD_VDD SD_VDD SD_VDD EVDD

IVDD

HOST_P HOST_M

TRST/

DSCLK

K

L

D28

D24

D29

D25

IVDD SD_VDD SD_VDD EVDD

EVDD

IVDD

PST3

PST2

PST1

TDI/DSI RESET

XTAL

EXTAL

U0CTS

U0TXD

K

L

SD_DR_

DQS

TDO/

DSO

TMS/

RSTOUT

SD_CLK

D19

D7

D6

D5

D3

D2

D1

R/W

OE

DDATA3

DDATA2

DDATA1

BKPT

BE/

BWE2

QSPI_

CS0

QSPI_

U0RTS

CS1

M

N

P

SD_CLK SD_A10 SD_CAS SD_RAS

M

N

P

SD_

DQS2

TCLK/

PSTCLK

QSPI_

DOUT

QSPI_

CS2

XTAL

32K

FB_CLK

D23

D20

D17

BE/

BWE0

QSPI_

DIN

QSPI_

CLK

EXTAL

32K

D22

1

D21

2

D18

3

D16

4

D4

6

D0

7

RCON DDATA0

PST0

10

U0RXD

14

5

8

9

11

12

13

Figure 1. MCF5373LCVM240 Pinout Top View (196 MAPBGA)

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

9

Mechanicals and Pinouts

4.2 Package Dimensions—196 MAPBGA

Figure 2 shows the MCF5373LCVM240 and MCF5372LCVM240 package dimensions.

NOTES:

D

X

Y

1. Dimensions are in millimeters.

2. Interpretdimensionsandtolerances

per ASME Y14.5M, 1994.

Laser mark for pin 1

identification in

this area

3. Dimension B is measured at the

maximum solder ball diameter,

parallel to datum plane Z.

4. Datum Z (seating plane) is defined

bythesphericalcrownsofthesolder

balls.

M

K

5. Parallelism measurement shall

exclude any effect of mark on top

surface of package.

Millimeters

DIM Min Max

A 1.32 1.75

A1 0.27 0.47

A2 1.18 REF

E

b

D

E

e

0.35 0.65

15.00 BSC

1.00 BSC

0.50 BSC

S

M

Top View

0.20

13X e

S

Metalized mark for

pin 1 identification

in this area

14 13 12 11 10

9

6

5

4

3

2

1

A

B

C

D

E

F

5

S

0.30 Z

13X e

A2

A

G

H

J

A1

0.15 Z

4

Z

K

L

Detail K

Rotated 90 Clockwise

°

M

N

P

3

196X

b

Bottom View

0.30 Z X Y

0.10 Z

View M-M

Figure 2. 196 MAPBGA Package Dimensions (Case No. 1128A-01)

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

10

Freescale Semiconductor

Mechanicals and Pinouts

4.3 Pinout—160 QFP

The pinout for the MCF5372CAB180 and MCF5373CAB180 packages is shown below.

•

FEC_TXD1

FEC_TXD0

FEC_MDIO

FEC_MDC

DT0IN

DT1IN

DT2IN

DT3IN

EVDD

VSS 10

SD_VDD 11

TS 12

1

2

3

4

5

6

7

8

9

120 A13

119 A12

118 A11

117 A10

116 A9

115 A8

114 A7

113 A6

112 A5

111 A4

110 A3

109 A2

108 A1

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

SD_WE

SD_CKE

SD_CS0

D15

107 A0

106 TA

105 SD_VDD

104 VSS

D14

103 EVDD

102 IRQ7

101 IRQ4

100 IRQ1

99 PLL_VDD

98 PLL_VSS

97 IVDD

D13

D12

D11

D10

D9

D8

BE/BWE1

SD_DQS1/3

BE/BWE3

D31

96 JTAG_EN

95 RESET

94 EVDD

93 XTAL

D30

92 DRAMSEL

91 EXTAL

90 TDI/DSI

89 VSS

D29

D28

D27

D26

88 TRST/DSCLK

87 TMS/BKPT

86 RSTOUT

85 U0CTS

84 U0RTS

83 U0TXD

82 VSS

D25

D24

SD_DR_DQS

IVDD

SD_CLK

SD_VDD

FB_CLK

81 EVDD

Figure 3. MCF5372CAB180 and MCF5373CAB180 Pinout Top View (160 QFP)

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

11

Mechanicals and Pinouts

4.4 Package Dimensions—160 QFP

Figure 4 and Figure 5 show the MCF5372CAB180 and MCF5373CAB180 package dimensions.

Top View

Figure 4. 160QFP Package Dimensions (Sheet 1 of 2)

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

12

Freescale Semiconductor

Mechanicals and Pinouts

Figure 5. 160QFP Package Dimensions (Sheet 2 of 2)

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

13

Preliminary Electrical Characteristics

5 Preliminary Electrical Characteristics

This document contains electrical specification tables and reference timing diagrams for the MCF5373

microcontroller unit. This section contains detailed information on power considerations, DC/AC

electrical characteristics, and AC timing specifications of MCF5373.

The electrical specifications are preliminary and are from previous designs or design simulations. These

specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however

for production silicon these specifications will be met. Finalized specifications will be published after

complete characterization and device qualifications have been completed.

NOTE

The parameters specified in this MCU document supersede any values

found in the module specifications.

5.1 Maximum Ratings

1, 2

Table 4. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Core Supply Voltage

IV_DD

EV_DD

SDV_DD

PLLV_DD

V_IN

– 0.5 to +2.0

– 0.3 to +4.0

– 0.3 to +2.0

– 0.3 to +3.6

25

V

CMOS Pad Supply Voltage

DDR/Memory Pad Supply Voltage

PLL Supply Voltage

V

Digital Input Voltage ³

V

Instantaneous Maximum Current

I_D

mA

Single pin limit (applies to all pins) ^{3, 4, 5}

Operating Temperature Range (Packaged)

T_A

(T_L- T_H)

– 40 to +85

°C

Storage Temperature Range

N₁OTES:

T_stg

– 55 to +150

Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.”

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is

not guaranteed. Continued operation at these levels may affect device reliability or cause

permanent damage to the device.

This device contains circuitry protecting against damage due to high static voltage or

electrical fields; however, it is advised that normal precautions be taken to avoid application of

any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of

operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,

either V_SSor EV_DD).

2

3

4

Input must be current limited to the value specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive and negative clamp voltages,

then use the larger of the two values.

All functional non-supply pins are internally clamped to V_SSand EV_DD

.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

14

Freescale Semiconductor

Preliminary Electrical Characteristics

Power supply must maintain regulation within operating EV_DDrange during instantaneous

5

and operating maximum current conditions. If positive injection current (V_in> EV_DD) is greater

than I_DD, the injection current may flow out of EV_DDand could result in external power supply

going out of regulation. Insure external EV_DDload will shunt current greater than maximum

injection current. This will be the greatest risk when the MCU is not consuming power (ex; no

clock). Power supply must maintain regulation within operating EV_DDrange during

instantaneous and operating maximum current conditions.

5.2 Thermal Characteristics

Table 5. Thermal Characteristics

Characteristic

Symbol

256MBGA 196MBGA

160QFP

Unit

Junction to ambient, natural convection

Four layer board

(2s2p)

θ_JMA

26^1,2

32^1,2

40^1,2

°C/W

Junction to ambient (@200 ft/min)

Four layer board

(2s2p)

θ_JMA

23^1,2

29^1,2

36^1,2

°C/W

Junction to board

θ_JB

θ_JC

Ψ_jt

T_j

15³

10⁴

2^1,5

105

20³

10⁴

2^1,5

105

25³

10⁴

2^1,5

105

°C/W

^oC

Junction to case

Junction to top of package

Maximum operating junction temperature

N₁OTES:

θ

_JMAand Ψ_jtparameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale

recommends the use of θ_JmAand power dissipation specifications in the system design to prevent device junction

temperatures from exceeding the rated specification. System designers should be aware that device junction

temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device

junction temperature specification can be verified by physical measurement in the customer’s system using the Ψ_jt

parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

2

3

4

5

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is

written in conformance with Psi-JT.

The average chip-junction temperature (T ) in °C can be obtained from:

J

T_J= T_A+ (P_D× Θ_JMA

)

Eqn. 1

Where:

T

= Ambient Temperature, °C

= Package Thermal Resistance, Junction-to-Ambient, °C/W

= P + P

A

Q

JMA

P

D

INT

I/O

P

= I × IV , Watts - Chip Internal Power

DD DD

INT

P

= Power Dissipation on Input and Output Pins — User Determined

I/O

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Freescale Semiconductor

15

Preliminary

Preliminary Electrical Characteristics

For most applications P < P

and can be ignored. An approximate relationship between P and T (if

I/O

INT

D

J

P

is neglected) is:

I/O

K

--------------------------------

P_D

=

Eqn. 2

(T_J+ 273°C)

Solving equations 1 and 2 for K gives:

K = P_D× (T_A× 273°C) + Q_JMA× P²_D

Eqn. 3

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring

P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by

D

A

D

J

solving Equation 1 and Equation 2 iteratively for any value of T .

A

5.3 ESD Protection

1, 2

Table 6. ESD Protection Characteristics

Characteristics

Symbol

Value

Units

ESD Target for Human Body Model

N₁OTES:

HBM

2000

V

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for

Automotive Grade Integrated Circuits.

2

A device is defined as a failure if after exposure to ESD pulses the device no longer meets

the device specification requirements. Complete DC parametric and functional testing is

performed per applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

5.4 DC Electrical Specifications

Table 7. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Core Supply Voltage

PLL Supply Voltage

IV_DD

PLLV_DD

EV_DD

1.4

1.6

V

1.6

CMOS Pad Supply Voltage

3.0

3.6

1.95

Mobile DDR/Bus Pad Supply Voltage

DDR/Bus Pad Supply Voltage

SDR/Bus Pad Supply Voltage

USB Supply Voltage

SDV_DD

USBV_DD

EV_IH

1.65

2.25

3.0

2.75

3.6

3.0

3.6

CMOS Input High Voltage

2

EV_DD+ 0.05

0.8

CMOS Input Low Voltage

EV_IL

-0.05

TBD

-0.05

2

Mobile DDR/Bus Input High Voltage

Mobile DDR/Bus Input Low Voltage

DDR/Bus Input High Voltage

DDR/Bus Input Low Voltage

SDV_IH

SDV_IL

SDV_IH

SDV_IL

SDV_DD+ 0.05

TBD

SDV_DD+ 0.05

0.8

-0.05

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

16

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 7. DC Electrical Specifications (continued)

Characteristic

Symbol

Min

Max

Unit

Input Leakage Current

I_in

-1.0

1.0

µA

V_in= V_DDor V_SS, Input-only pins

CMOS Output High Voltage

EV_OH

EV_OL

EV_DD- 0.4

—

0.4

—

V

I_OH= –5.0 mA

CMOS Output Low Voltage

—

SDV_DD- 0.4

—

I_OL= 5.0 mA

DDR/Bus Output High Voltage

I_OH= –5.0 mA

SDV_OH

SDV_OL

DDR/Bus Output Low Voltage

0.4

-130

I_OL= 5.0 mA

Weak Internal Pull-Up Device Current, tested at V_ILMax.¹

I_APU

C_in

-10

µA

Input Capacitance ²

pF

All input-only pins

All input/output (three-state) pins

—

7

NOTES:

1

Refer to the signals section for pins having weak internal pull-up devices.

This parameter is characterized before qualification rather than 100% tested.

2

5.4.1 PLL Power Filtering

To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins.

DD

The filter shown in Figure 6 should be connected between the board V and the PLLV pins. The

DD

resistor and capacitors should be placed as close to the dedicated PLLV pin as possible.

DD

10 Ω

Board V_DD

PLL V_DDPin

10 µF

0.1 µF

GND

Figure 6. System PLL V Power Filter

DD

5.4.2 USB Power Filtering

To minimize noise, external filters are required for each of the USB power pins. The filter shown in

Figure 7 should be connected between the board EV or IV and each of the USBV pins. The

DD

resistor and capacitors should be placed as close to the dedicated USBV pin as possible.

DD

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Freescale Semiconductor

17

Preliminary

Preliminary Electrical Characteristics

0 Ω

Board EV_DD/IV_DD

USB V_DDPin

10 µF

0.1 µF

GND

Figure 7. USB V Power Filter

DD

NOTE

In addition to the above filter circuitry, a 0.01 F capacitor is also

recommended in parallel with those shown.

5.4.3 Supply Voltage Sequencing and Separation Cautions

Figure 8 shows situations in sequencing the I/O V (EV ), SDRAM V (SDV ), PLL V

DD

(PLLV ), and Core V (IV ).

DD

EV_DD, SDV_DD, USBV_DD

SDV_DD(2.5V/1.8V)

3.3V

2.5V

Supplies Stable

IV_DD, PLLV_DD

1.5V

1

2

0

Time

Notes:

1. IVDD should not exceed EVDD, SDVDD or PLLVDD by more than

0.4 V at any time, including power-up.

2. Recommended that IVDD/PLLVDD should track EVDD/SDVDD up to

0.9 V, then separate for completion of ramps.

3. Input voltage must not be greater than the supply voltage (EVDD, SDVDD,

IVDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.

4. Use 1 ms or slower rise time for all supplies.

Figure 8. Supply Voltage Sequencing and Separation Cautions

The relationship between SDV and EV is non-critical during power-up and power-down sequences.

DD

Both SDV (2.5V or 3.3V) and EV are specified relative to IV .

DD

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

18

Freescale Semiconductor

Preliminary Electrical Characteristics

5.4.3.1 Power Up Sequence

If EV /SDV are powered up with IV at 0 V, then the sense circuits in the I/O pads will cause all

DD

pad output drivers connected to the EV /SDV to be in a high impedance state. There is no limit on

DD

how long after EV /SDV powers up before IV must powered up. IV should not lead the EV ,

DD

SDV or PLLV by more than 0.4 V during power ramp-up, or there will be high current in the internal

DD

ESD protection diodes. The rise times on the power supplies should be slower than 1 µs to avoid turning

on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1 µs or slower rise time for all supplies.

2. IV /PLLV and EV /SDV should track up to 0.9 V, then separate for the completion of

DD

ramps with EV /SD V going to the higher external voltages. One way to accomplish this is to

DD

use a low drop-out voltage regulator.

5.4.3.2 Power Down Sequence

If IV /PLLV are powered down first, then sense circuits in the I/O pads will cause all output drivers

DD

to be in a high impedance state. There is no limit on how long after IV and PLLV power down before

DD

EV or SDV must power down. IV should not lag EV , SDV , or PLLV going low by more

DD

than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There

are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IV /PLLV to 0 V.

DD

2. Drop EV /SDV supplies.

DD

5.5 Power Consumption Specifications

Estimated maximum RUN mode power consumption measurements are shown in the below figure.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Freescale Semiconductor

19

Preliminary

Preliminary Electrical Characteristics

Estimated Power Consumption vs. Core Frequency

300

250

200

150

100

50

0

40

80

120

160

200

240

Core Frequency (MHz)

Figure 9. Estimated Maximum RUN Mode Power Consumption

Table 8 lists estimated maximum power and current consumption for the device in various operating

modes.

Table 8. Estimated Maximum Power Consumption Specifications

Characteristic

Symbol Typical

Max

Unit

Run Mode - Total Power Dissipation

—

250

5.74

244

mW

Static

Dynamic

Core Operating Supply Current ¹

Run Mode

I_DD

EI_DD

—

TBD

mA

Pad Operating Supply Current

Run Mode (application dependent)

Wait Mode

—

144

96

1

mA

Stop Mode

NOTES:

1

Current measured at maximum system clock frequency, all modules active, and default drive

strength with matching load.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

20

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

5.6 Oscillator and PLL Electrical Characteristics

Table 9. PLL Electrical Characteristics

Min.

Value

Max.

Value

Num

Characteristic

Symbol

Unit

1

PLL Reference Frequency Range

Crystal reference

f_{ref_crystal}

f_{ref_ext}

TBD

16

MHz

External reference

2

Core frequency

f_sys

f_sys/3

TBD

240

80

MHz

CLKOUT Frequency¹

3

4

Crystal Start-up Time^{2, 3}

t_cst

—

10

ms

EXTAL Input High Voltage

Crystal Mode⁴

All other modes (External, Limp)

V_IHEXT

TBD

V

5

EXTAL Input Low Voltage

Crystal Mode⁴

V_ILEXT

TBD

V

All other modes (External, Limp)

6

XTAL Load Capacitance²

PLL Lock Time ^{2, 5}

5

30

1

pF

ms

%

7

8

t_lpll

t_dc

—

40

Duty Cycle of reference ²

60

N₁OTES:

All internal registers retain data at 0 Hz.

2

3

4

5

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

This parameter is guaranteed by design rather than 100% tested.

This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in

the synthesizer control register (SYNCR).

5.7 External Interface Timing Characteristics

Table 10 lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and

output delay with respect to the rising edge of a reference clock. The

reference clock is the FB_CLK output.

All other timing relationships can be derived from these values. Timings

listed in Table 10 are shown in Figure 11 and Figure 12.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Freescale Semiconductor

21

Preliminary

Preliminary Electrical Characteristics

* The timings are also valid for inputs sampled on the negative clock edge.

1.5V

FB_CLK (80MHz)

TSETUP

THOLD

Invalid

1.5V Valid 1.5V

Invalid

Input Setup And Hold

Input Rise Time

Input Fall Time

t

rise

V

= V

IH

h

V = V

l

IL

fall

V

= V

IH

h

V = V

l

IL

FB_CLK

B4

B5

Inputs

Figure 10. General Input Timing Requirements

5.7.1 FlexBus

A multi-function external bus interface called FlexBus is provided with basic functionality to interface to

slave-only devices up to a maximum bus frequency of 80MHz. It can be directly connected to

asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or

other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple

chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects

(FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory

interfaces. Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte

(8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common

ROM/flash memories.

5.7.1.1 FlexBus AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative

to the system clock.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

22

Freescale Semiconductor

Preliminary

Preliminary Electrical Characteristics

Table 10. FlexBus AC Timing Specifications

Num

Characteristic

Symbol

Min

Max

Unit Notes

Frequency of Operation

FB1 Clock Period (FB_CLK)

—

80

12.5

7.0

Mhz

ns

f_sys/3

t_FBCK

t_cyc

1

FB2 Address, Data, and Control Output Valid (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)

t_FBCHDCV

ns

1, 2

FB3 Address, Data, and Control Output Hold (A[23:0], D[31:0],

FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)

t_FBCHDCI

1

—

ns

FB4 Data Input Setup

t_DVFBCH

t_DIFBCH

t_CVFBCH

t_CIFBCH

t_FBCHAV

t_FBCHAI

3.5

0

—

6.0

—

ns

FB5 Data Input Hold

FB6 Transfer Acknowledge (TA) Input Setup

FB7 Transfer Acknowledge (TA) Input Hold

FB8 Address Output Valid (A[23:0])

FB9 Address Output Hold (A[23:0])

4

0

3

—

1

N₁OTES:

Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.8.2, “DDR SDRAM AC Timing

Characteristics” for SD_CS[3:0] timing.

2

3

The FlexBus supports programming an extension of the address hold. Please consult the MCF5373 Reference

Manual for more information.

These specs are used when the A[23:0] signals are configured as 23-bit, non-muxed FlexBus address signals.

FB_CLK

FB1

FB3

A[23:0]

D[31:0]

R/W

A[23:0]

FB2

FB5

DATA

FB4

TS

FB_CSn

BE/BWEn

FB7

OE

TA

FB6

Figure 11. FlexBus Read Timing.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

23

Preliminary Electrical Characteristics

FB_CLK

FB1

FB3

A[23:0]

D[31:0]

R/W

FB2

TS

FB_CSn

BE/BWEn

FB7

OE

TA

FB6

Figure 12. Flexbus Write Timing

5.8 SDRAM Bus

The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports

either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.

5.8.1 SDR SDRAM AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative

to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read

cycles. The device’s SDRAM controller is a DDR controller that has an SDR mode. Because it is designed

to support DDR, a DQS pulse must still be supplied to device for each data beat of an SDR read. Te

processor accomplishes this by asserting a signal named SD_DQS during read cycles. Care must be taken

during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal

and its usage.

Table 11. SDR Timing Specifications

Symbol

Characteristic

Frequency of Operation

Symbol

Min

Max

Unit

Notes

1

TBD

12.5

—

80

Mhz

ns

2

3

SD1 Clock Period

SD2 Clock Skew

t_SDCK

t_SDSK

TBD

0.55

SD3 Pulse Width High

t_SDCKH

0.45

SD_CLK

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

24

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 11. SDR Timing Specifications (continued)

Symbol

Characteristic

Symbol

Min

Max

Unit

Notes

4

SD4 Pulse Width Low

t_SDCKH

0.45

—

0.55

SD_CLK

ns

SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,

SD_CS[1:0] - Output Valid

t_SDCHACV

0.5 × SD_CLK

+ 1.0

SD6 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,

SD_CS[1:0] - Output Hold

t_SDCHACI

2.0

—

ns

5

6

SD7 SD_SDR_DQS Output Valid

t_DQSOV

Self timed

ns

SD8 SD_DQS[3:0] input setup relative to SD_CLK

t_DQVSDCH

0.25 ×

0.40 × SD_CLK

SD_CLK

7

8

SD9 SD_DQS[3:2] input hold relative to SD_CLK

t_DQISDCH

t_DVSDCH

t_DISDCH

Does not apply. 0.5×SD_CLK fixed

width.

SD10 Data (D[31:0]) Input Setup relative to SD_CLK (reference

only)

0.25 ×

—

ns

SD_CLK

SD11 Data Input Hold relative to SD_CLK (reference only)

1.0

—

ns

SD12 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid t_SDCHDMV

0.75 × SD_CLK

+ 0.5

SD13 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold t_SDCHDMI

1.5

—

ns

NOTES:

1

The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.

Please see the PLL chapter of the MCF5373 Reference Manual for more information on setting the SDRAM clock rate.

SD_CLK is one SDRAM clock in (ns).

Pulse width high plus pulse width low cannot exceed min and max clock period.

SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation

from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat.

SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle

variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data

beat.

2

3

4

5

6

7

8

The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does

not affect the memory controller.

Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be

centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup

spec is just provided as guidance.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Freescale Semiconductor

25

Preliminary

Preliminary Electrical Characteristics

SD1

SD3

SD2

SD_CLK0

SD2

SD4

SD_CLK1

SD6

SD_CSn

SD_RAS

SD_CAS

SD_WE

CMD

SD5

A[23:0]

SD_BA[1:0]

ROW

COL

SD12

SDDM

D[31:0]

SD13

WD1

WD2

WD3

WD4

Figure 13. SDR Write Timing

SD1

SD2

SD_CLK0

SD_CLK1

SD6

SD_CSn,

SD_RAS,

SD_CAS,

SD_WE

CMD

3/4 MCLK

Reference

SD5

A[23:0],

SD_BA[1:0]

ROW

COL

tDQS

SDDM

SD7

SD_DQS (Measured at Output Pin)

SD_DDQS (Measured at Input Pin)

Board Delay

SD9

Board Delay

SD8

Delayed

SD_CLK

SD10

D[31:0]

from

WD1

WD2

WD3

WD4

Memories

NOTE: Data driven from memories relative

to delayed memory clock.

SD11

Figure 14. SDR Read Timing

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

26

Freescale Semiconductor

Preliminary Electrical Characteristics

5.8.2 DDR SDRAM AC Timing Characteristics

When using the SDRAM controller in DDR mode, the following timing numbers must be followed to

properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte

lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early

board design. Please contact your local Freescale representative if questions develop.

Table 12. DDR Timing Specifications

Num

Characteristic

Frequency of Operation

Symbol

Min

Max

Unit

Notes

1

t_DDCK

t_DDSK

80

TBD

0.45

—

TBD

12.5

0.55

Mhz

ns

2

3

4

DD1 Clock Period

DD2 Pulse Width High

DD3 Pulse Width Low

t_DDCKH

t_DDCKL

t_SDCHACV

SD_CLK

ns

DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Valid

0.5 × SD_CLK

+ 1.0

DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Hold

t_SDCHACI

2.0

—

ns

DD6 Write Command to first DQS Latching Transition

t_CMDVDQ

t_DQDMV

—

1.25

—

SD_CLK

ns

5

6

DD7 Data and Data Mask Output Setup (DQ-->DQS)

Relative to DQS (DDR Write Mode)

1.5

7

DD8 Data and Data Mask Output Hold (DQS-->DQ)

Relative to DQS (DDR Write Mode)

t_DQDMI

1.0

—

ns

8

9

DD9 Input Data Skew Relative to DQS (Input Setup)

DD10 Input Data Hold Relative to DQS.

t_DVDQ

t_DIDQ

—

1

ns

0.25 × SD_CLK

—

+ 0.5ns

DD11 DQS falling edge from SDCLK rising (output hold time) t_DQLSDCH

0.5

0.9

—

ns

DD12 DQS input read preamble width

DD13 DQS input read postamble width

DD14 DQS output write preamble width

DD15 DQS output write postamble width

N₁OTES:

t_DQRPRE

t_DQRPST

t_DQWPRE

t_DQWPST

1.1

0.6

SD_CLK

0.4

0.25

0.4

0.6

The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the

same frequency as the internal bus clock.

2

3

4

SD_CLK is one SDRAM clock in (ns).

Pulse width high plus pulse width low cannot exceed min and max clock period.

Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process,

temperature, and voltage variations.

This specification relates to the required input setup time of today’s DDR memories. Rigoletto’s output setup should be larger

than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.

MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to

MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].

The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data

beats will be valid for each subsequent DQS edge.

This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],

MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative

MEM_DQS[0].

5

6

7

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Freescale Semiconductor

27

Preliminary

Preliminary Electrical Characteristics

8

Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line

becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other

factors).

⁹Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line

becomes invalid.

SD_CLK

V_IX

V_ID

V_MP

V_IX

SD_CLK

Figure 15. SD_CLK and SD_CLK crossover timing

DD1

DD2

SD_CLK

DD3

SD_CLK

DD5

SD_CSn,SD_WE,

SD_RAS, SD_CAS

CMD

ROW

DD4

DD6

A[13:0]

COL

DD7

DM3/DM2

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

DD8

DD7

WD1 WD2 WD3 WD4

DD8

Figure 16. DDR Write Timing

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

28

Freescale Semiconductor

Preliminary Electrical Characteristics

DD1

DD2

SD_CLK

DD3

SD_CLK

DD5

CL=2

SD_CSn,SD_WE,

SD_RAS, SD_CAS

CMD

ROW

DD4

CL=2.5

A[13:0]

COL

DD9

DQS Read

Postamble

DQS Read

Preamble

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

DD10

WD1 WD2 WD3 WD4

DQS Read

Preamble

DQS Read

Postamble

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

WD1 WD2 WD3 WD4

Figure 17. DDR Read Timing

5.9 General Purpose I/O Timing

1

Table 13. GPIO Timing

Num

Characteristic

Symbol

Min

Max

Unit

G1 FB_CLK High to GPIO Output Valid

G2 FB_CLK High to GPIO Output Invalid

G3 GPIO Input Valid to FB_CLK High

G4 FB_CLK High to GPIO Input Invalid

t_CHPOV

t_CHPOI

t_PVCH

t_CHPI

—

1.5

9

10

—

ns

1.5

N₁OTES:

GPIO pins include: IRQn, PWM, UART, and Timer pins.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

29

Preliminary Electrical Characteristics

FB_CLK

G2

G1

GPIO Outputs

GPIO Inputs

G3

G4

Figure 18. GPIO Timing

5.10 Reset and Configuration Override Timing

Table 14. Reset and Configuration Override Timing

Num

Characteristic

Symbol

Min

Max

Unit

R1 RESET Input valid to FB_CLK High

t_RVCH

t_CHRI

9

1.5

5

—

10

—

1

ns

R2 FB_CLK High to RESET Input invalid

R3 RESET Input valid Time ¹

t_RIVT

t_CYC

ns

R4 FB_CLK High to RSTOUT Valid

t_CHROV

t_ROVCV

t_COS

—

0

R5 RSTOUT valid to Config. Overrides valid

R6 Configuration Override Setup Time to RSTOUT invalid

R7 Configuration Override Hold Time after RSTOUT invalid

R8 RSTOUT invalid to Configuration Override High Impedance

ns

20

0

t_CYC

ns

t_COH

t_ROICZ

—

t_CYC

N₁OTES:

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to

the system. Thus, RESET must be held a minimum of 100 ns.

FB_CLK

R1

R2

R3

RESET

R4

RSTOUT

R8

R5

R6

R7

Configuration Overrides*:

(RCON, Override pins])

Figure 19. RESET and Configuration Override Timing

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

30

Freescale Semiconductor

Preliminary Electrical Characteristics

NOTE

Refer to the CCM chapter of the MCF5373 Reference Manual for more

information.

5.11 USB On-The-Go

The MCF5373 device is compliant with industry standard USB 2.0 specification.

5.12 SSI Timing Specifications

The following figure and table lists the specifications for the SSI module.

S1

S2

S3

SSI_BCLK

S4

S5

SSI_MCLK

STFS

S6

S7

SSI_TXD (Output)

STFS

S6

SSI_RXD (Input)

Note: SSI External. Continous clock Synchronous mode only

Figure 20. SSI External Continous Clock Timing Diagram

Table 15. SSI Timing

1.8 +/- 0.10V

Num

Description

Unit

Minimum

Maximum

S1

S2

S3

SSI_BCLK clock period

SSI_BCK high-level time

SSI_BCK low-level time

1/(64f_s)¹

35

49

—

ns

35

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

31

Preliminary Electrical Characteristics

Table 15. SSI Timing (continued)

Description

1.8 +/- 0.10V

Num

Unit

Minimum

Maximum

S4

S5

SSI_BCK rising edge to SSI_MCLK edge

SSI_MCLK edge to SSI_BCLK rising edge

10

—

ns

S6

SSI_TXD/SSI_RXD data set-up time

SSI_TXD/SSI_RXD data hold time

S7

NOTES:

¹f_{s is the sampling frequency. SSI_BCLK can be operated upto 512 times the sampling frequency to a max frequency of 49.152MHz}

5.13 I²C Input/Output Timing Specifications

2

Table 16 lists specifications for the I C input timing parameters shown in Figure 21.

2

Table 16. I C Input Timing Specifications between SCL and SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

I1

I2

I3

I4

I5

I6

I7

I8

I9

2

8

—

1

t_cyc

ms

ns

Clock low period

I2C_SCL/I2C_SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

—

0

—

1

I2C_SCL/I2C_SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

4

ms

t_cyc

ns

—

Data setup time

0

Start condition setup time (for repeated start condition only)

Stop condition setup time

2

t_cyc

2

Table 17 lists specifications for the I C output timing parameters shown in Figure 21.

2

Table 17. I C Output Timing Specifications between SCL and SDA

Num

I1¹Start condition hold time

I2 ¹Clock low period

Characteristic

Min

Max

Units

6

—

3

t_cyc

µs

10

—

7

I3 ²I2C_SCL/I2C_SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

I4 ¹Data hold time

t_cyc

ns

I5 ³I2C_SCL/I2C_SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

I6 ¹Clock high time

—

10

2

—

t_cyc

I7 ¹Data setup time

I8 ¹Start condition setup time (for repeated start condition only)

I9 ¹Stop condition setup time

20

10

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

32

Freescale Semiconductor

Preliminary Electrical Characteristics

N₁OTES:

Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum

frequency (IFDR = 0x20) results in minimum output timings as shown in Table 17. The I²C interface is

designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual

position is affected by the prescale and division values programmed into the IFDR; however, the numbers

given in Table 17 are minimum values.

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively

drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance

and pull-up resistor values.

2

3

Specified at a nominal 50-pF load.

Figure 21 shows timing for the values in Table 17 and Table 16.

I5

I6

I2

I2C_SCL

I2C_SDA

I7

I8

I1

I9

I4

I3

2

Figure 21. I C Input/Output Timings

5.14 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

5.14.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV,

FEC_RXER, and FEC_RXCLK)

The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

FEC_RXCLK frequency.

Table 18 lists MII receive channel timings.

Table 18. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

M1

M2

M3

M4

FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup

FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold

FEC_RXCLK pulse width high

5

—

ns

5

ns

35%

65%

FEC_RXCLK period

FEC_RXCLK pulse width low

Figure 22 shows MII receive signal timings listed in Table 18.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

33

Preliminary Electrical Characteristics

M3

FEC_RXCLK (input)

M4

FEC_RXD[3:0] (inputs)

FEC_RXDV

FEC_RXER

M1

M2

Figure 22. MII Receive Signal Timing Diagram

5.14.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN,

FEC_TXER, FEC_TXCLK)

Table 19 lists MII transmit channel timings.

The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. There is

no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

FEC_TXCLK frequency.

The transmit outputs (FEC_TXD[3:0], FEC_TXEN, FEC_TXER) can be programmed to transition from

either the rising or falling edge of FEC_TXCLK, and the timing is the same in either case. This options

allows the use of non-compliant MII PHYs.

Refer to the Ethernet chapter for details of this option and how to enable it.

Table 19. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

M5

M6

M7

M8

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid

FEC_TXCLK pulse width high

5

—

25

ns

—

ns

35%

65%

FEC_TXCLK period

FEC_TXCLK pulse width low

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

34

Freescale Semiconductor

Preliminary Electrical Characteristics

Figure 23 shows MII transmit signal timings listed in Table 19.

M7

FEC_TXCLK (input)

M5

M8

FEC_TXD[3:0] (outputs)

FEC_TXEN

FEC_TXER

M6

Figure 23. MII Transmit Signal Timing Diagram

5.14.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 20 lists MII asynchronous inputs signal timing.

Table 20. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

M9

FEC_CRS, FEC_COL minimum pulse width

1.5

—

FEC_TXCLK period

Figure 24 shows MII asynchronous input timings listed in Table 20.

FEC_CRS

FEC_COL

M9

Figure 24. MII Async Inputs Timing Diagram

5.14.4 MII Serial Management Channel Timing (FEC_MDIO and

FEC_MDC)

Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum

MDC frequency of 2.5 MHz.

Table 21. MII Serial Management Channel Timing

Num

Characteristic

Min Max

Unit

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum

propagation delay)

0

—

ns

M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay)

M12 FEC_MDIO (input) to FEC_MDC rising edge setup

M13 FEC_MDIO (input) to FEC_MDC rising edge hold

—

10

0

25

—

ns

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

35

Preliminary Electrical Characteristics

Table 21. MII Serial Management Channel Timing (continued)

Characteristic Min Max

Num

Unit

M14 FEC_MDC pulse width high

M15 FEC_MDC pulse width low

40% 60% FEC_MDC period

Figure 25 shows MII serial management channel timings listed in Table 21.

M14

M15

FEC_MDC (output)

FEC_MDIO (output)

M10

M11

FEC_MDIO (input)

M12

M13

Figure 25. MII Serial Management Channel Timing Diagram

5.15 32-Bit Timer Module Timing Specifications

Table 22 lists timer module AC timings.

Table 22. Timer Module AC Timing Specifications

Name

Characteristic

Unit

Min

Max

T1

T2

DT0IN / DT1IN / DT2IN / DT3IN cycle time

DT0IN / DT1IN / DT2IN / DT3IN pulse width

3

1

—

t_CYC

5.16 QSPI Electrical Specifications

Table 23 lists QSPI timings.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

36

Freescale Semiconductor

Preliminary Electrical Characteristics

Table 23. QSPI Modules AC Timing Specifications

Characteristic

Name

Min

Max

Unit

QS1

QS2

QS3

QS4

QS5

QSPI_CS[3:0] to QSPI_CLK

1

—

2

510

10

—

t_CYC

ns

QSPI_CLK high to QSPI_DOUT valid.

QSPI_CLK high to QSPI_DOUT invalid. (Output hold)

QSPI_DIN to QSPI_CLK (Input setup)

QSPI_DIN to QSPI_CLK (Input hold)

ns

9

—

ns

9

—

ns

The values in Table 23 correspond to Figure 26.

QS1

QSPI_CS[3:0]

QSPI_CLK

QS2

QSPI_DOUT

QS3

QS4

QS5

QSPI_DIN

Figure 26. QSPI Timing

5.17 JTAG and Boundary Scan Timing

Table 24. JTAG and Boundary Scan Timing

Num

Characteristics¹

TCLK Frequency of Operation

Symbol

Min

Max

Unit

J1

J2

J3

J4

J5

J6

J7

J8

J9

f_JCYC

t_JCYC

DC

4

1/4

—

3

f_sys/3

t_CYC

ns

TCLK Cycle Period

TCLK Clock Pulse Width

t_JCW

26

0

TCLK Rise and Fall Times

t_JCRF

ns

Boundary Scan Input Data Setup Time to TCLK Rise

Boundary Scan Input Data Hold Time after TCLK Rise

TCLK Low to Boundary Scan Output Data Valid

TCLK Low to Boundary Scan Output High Z

TMS, TDI Input Data Setup Time to TCLK Rise

t_BSDST

t_BSDHT

t_BSDV

4

—

33

—

ns

26

0

ns

t_BSDZ

0

ns

t_TAPBST

t_TAPBHT

4

ns

J10 TMS, TDI Input Data Hold Time after TCLK Rise

10

ns

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

37

Preliminary Electrical Characteristics

Table 24. JTAG and Boundary Scan Timing (continued)

Num

Characteristics¹

Symbol

Min

Max

Unit

J11 TCLK Low to TDO Data Valid

J12 TCLK Low to TDO High Z

t_TDODV

t_TDODZ

t_TRSTAT

t_TRSTST

0

26

8

ns

J13 TRST Assert Time

100

10

—

J14 TRST Setup Time (Negation) to TCLK High

NOTES:

1

JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

J2

J3

V_IH

TCLK

(input)

V_IL

J4

Figure 27. Test Clock Input Timing

TCLK

V_IL

V_IH

J5

J6

Data Inputs

Input Data Valid

J7

J8

Data Outputs

Output Data Valid

Data Outputs

J7

Output Data Valid

Figure 28. Boundary Scan (JTAG) Timing

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

38

Freescale Semiconductor

Preliminary Electrical Characteristics

TCLK

V_IL

V_IH

J9

Input Data Valid

J10

TDI

TMS

J11

TDO

Output Data Valid

J12

J11

TDO

Output Data Valid

Figure 29. Test Access Port Timing

TCLK

J14

TRST

J13

Figure 30. TRST Timing

5.18 Debug AC Timing Specifications

Table 25 lists specifications for the debug AC timing parameters shown in Figure 32.

Table 25. Debug AC Timing Specification

Num

Characteristic

Units

Min

Max

DE0

DE1

DE2

DE3

DE4

PSTCLK cycle time

—

4

0.3

—

t_cyc

ns

PST valid to PSTCLK high

PSTCLK high to PST invalid

DSCLK cycle time

1.5

5

ns

t_cyc

ns

DSI valid to DSCLK high

1

DE5¹DSCLK high to DSO invalid

4

DE6

DE7

BKPT input data setup time to FB_CLK high

FB_CLK high to BKPT invalid

4

0

ns

N₁OTES:

DSCLK and DSI are synchronized internally. DE4 is measured from the synchronized DSCLK input

relative to the rising edge of FB_CLK.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Freescale Semiconductor

39

Preliminary

Revision History

Figure 31 shows real-time trace timing for the values in Table 25.

PSTCLK

DE0

DE1

DE2

PST[3:0]

DDATA[3:0]

Figure 31. Real-Time Trace AC Timing

Figure 32 shows BDM serial port AC timing and BKPT pin timing for the values in Table 25.

FB_CLK

DE6

BKPT

DE7

DE5

DSCLK

DSI

DE3

Current

Past

DSO

Current

Figure 32. BDM Serial Port AC Timing

6 Revision History

Table 26. MCF5373DS Document Revision History

Rev. No.

Substantive Changes

Date of Release

0

• Initial release.

11/2005

12/2005

0.1

• Swapped pin locations PLL_VSS (J11->H11) and DRAMSEL

(H11->J11) in Table 3. Figure 1 is correct.

0.2

0.3

• Added not to Section 4, “Mechanicals and Pinouts.”

• Added “top view” and “bottom view” where appropriate in mechanical

drawings and pinout figures.

3/2006

• Figure 10: Corrected “FB_CLK (75MHz)” label to “FB_CLK (80MHz)”

• Changed 160QFP pinouts in Figure 3 and Table 3: Removed IRQ3

pin, shifted pins 89–99 up one pin to 90–100. Pin 89 is now VSS.

• Table 3: Rearranged GPIO signal names for FEC pins.

4/2006

• Removed ULPI specifications as the device does not support ULPI.

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

40

Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

MCF5373 ColdFire^®Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

41

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MCF5373DS

Rev. 0.3

04/2006


型号：	MCF5372
厂家：	Freescale
描述：	Microprocessor Data Sheet 微处理器数据表微处理器
文件：	总42页 (文件大小：844K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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