MCIMX31VKN5 [FREESCALE]

Multimedia Applications Processors; 多媒体应用处理器


型号：	MCIMX31VKN5
厂家：	Freescale
描述：	Multimedia Applications Processors 多媒体应用处理器外围集成电路时钟
文件：	总170页 (文件大小：1637K)
中文：	中文翻译
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Document Number: MCIMX31

Rev. 1.4, 04/2006

Freescale Semiconductor

Advance Information

MCIMX31 and

MCIMX31L

Package Information

Plastic Package

Case 1581-01 14 x 14 mm, 0.5 P

i.MX31 and i.MX31L

Multimedia Applications

Processors

Ordering Information

Operating

Temperature Range

Device

Package

MCIMX31VKN5

MCIMX31LVKN5

0°C to +70°C

MAPBGA–457

Contents

1 Introduction

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 2

The i.MX31 (MCIMX31) and i.MX31L (MCIMX31L)

are multimedia applications processors that represent the

next step in low-power, high-performance application

processors. Unless otherwise specified, the material in

this data sheet is applicable to both the i.MX31 and

i.MX31L processors.

Based on an ARM11^™microprocessor core, the

i.MX31 and i.MX31L provide the performance with

low power consumption required by modern digital

devices such as:

2 Functional Description and Application

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 ARM11 Microprocessor Core . . . . . . . . . . . 3

2.2 Module Inventory . . . . . . . . . . . . . . . . . . . . 5

2.3 Module Descriptions . . . . . . . . . . . . . . . . . . 8

3 Signal Descriptions . . . . . . . . . . . . . . . . . . . 23

3.1 i.MX31 and i.MX31L I/O Pad Signal

Settings . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Electrical Characteristics . . . . . . . . . . . . . . 60

4.1 i.MX31 and i.MX31L

Chip-Level Conditions . . . . . . . . . . . . . . . 60

4.2 Supply Power-Up Requirements and

Restrictions . . . . . . . . . . . . . . . . . . . . . . . 65

4.3 Module-Level Electrical Specifications . . . 66

•

Feature-rich cellular phones

Portable media players and mobile gaming

machines

5 Package Information and Pinout . . . . . . . 152

5.1 MAPBGA Production Package

•

Personal digital assistants (PDAs) and Wireless

PDAs

457 14 x 14 mm, 0.5 P . . . . . . . . . . . . . . 153

6 Product Documentation . . . . . . . . . . . . . . . 167

6.1 Revision History . . . . . . . . . . . . . . . . . . . 167

•

Portable DVD players

Digital cameras

The i.MX31 and i.MX31L take advantage of the

ARM1136JF-S^™core running at typical speeds of

532 MHz, and is optimized for minimal power

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Preliminary

Introduction

consumption using the most advanced techniques for power saving (DPTC, DVFS, power gating, clock

gating). With 90 nm technology and dual-Vt transistors (two threshold voltages), the i.MX31 and

i.MX31L provide the optimal performance versus leakage current balance.

The performance of the i.MX31 and i.MX31L is boosted by a multi-level cache system, and features

peripheral devices such as an MPEG-4 Hardware Encoder (VGA, 30 fps), an Autonomous Image

Processing Unit, a Vector Floating Point (VFP11) co-processor, and a RISC-based SDMA controller.

The i.MX31 and i.MX31L support connections to various types of external memories, such as 266 MHz

DDR, NAND Flash, NOR Flash, SDRAM, and SRAM. The i.MX31 and i.MX31L can be connected to a

variety of external devices using technology, such as high-speed USB2.0 OTG, ATA, MMC/SDIO, and

compact flash.

1.1

Features

The i.MX31 and i.MX31L are designed for the high-tier and mid-tier smartphone markets. They provide

low-power solutions for high-performance demanding multimedia and graphics applications.

The i.MX31 and i.MX31L are built around the ARM11 MCU core and implemented in the 90 nm

technology.

The systems include the following features:

•

Multimedia and floating-point hardware acceleration supporting:

— MPEG-4 real-time encode of up to VGA at 30 fps

— MPEG-4 real-time video post-processing of up to VGA at 30 fps

— Video conference call of up to QCIF-30 fps (decoder in software), 128 kbps

— Video streaming (playback) of up to VGA-30 fps, 384 kbps

— 3D graphics and other applications acceleration with the ARM tightly-coupled Vector

Floating Point co-processor

— On-the-fly video processing that reduces system memory load (for example, the

power-efficient viewfinder application with no involvement of either the memory system or the

ARM CPU)

•

Advanced power management

— Dynamic voltage and frequency scaling

— Multiple clock and power domains

— Independent gating of power domains

Multiple communication and expansion ports including a fast parallel interface to an external

graphic accelerator (supporting major graphic accelerator vendors)

1.2

Block Diagram

Figure 1 shows the i.MX31 and i.MX31L simplified interface block diagram.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Functional Description and Application Information

SDRAM

DDR

SRAM, PSRAM,

NOR Flash

NAND Flash,

SmartMedia

Camera

Sensor (2)

Parallel

Display (2)

Serial

LCD

Tamper

Detection

Mouse

Keyboard

AP Peripherals

AUDMUX

SSI (2)

External Memory

Interface (EMI)

MPEG-4

Video Encoder

Image Processing Unit (IPU)

Inversion and Rotation

Camera Interface

Power

Management

UART (5)

Blending

SDMA

I2C (3)

FIR

Display/TV Ctl

Pre & Post Processing

CSPI (3)

PWM

Internal

Memory

Expansion

SDHC (2)

PCMCIA/CF

Mem Stick (2)

SIM

Timers

RTC

WDOG

GPT

USB Host (2)

USB-OTG

KPP

8 x 8

Keypad

ARM11 Platform

EPIT (2)

GPIO

CCM

ARM1136JF-S

ATA

I-Cache

D-Cache

L2-Cache

Serial

EPROM

1-WIRE

IIM

Security

SCC

RTIC

Debug

ECT

GPU

MAX

ROMPATCH

VFP

RNGA

SJC

GPS

ETM

* GPU unavailable for i.MX31L

ATA

Hard Drive

Fast

IrDA

USB

Host/Device

Card

Bluetooth

Baseband

WLAN

Figure 1. i.MX31/i.MX31L Simplified Interface Block Diagram

Table 1 provides additional details on the i.MX31 and i.MX31L orderable parts.

Table 1. Orderable Part Details

Operating Temp.

Range (T_A)

RoHS

Compliant

MSL

Level

Solder

Temp.

Device

Package

Pb-Free

MCIMX31VKN5

–0°C to +70°C

457-lead MAPBGA

0.5 mm, 14 mm x 14 mm

Yes

260°C

MCIMX31LVKN5

–0°C to +70°C

457-lead MAPBGA

0.5 mm, 14 mm x 14 mm

Yes

2 Functional Description and Application Information

2.1

ARM11 Microprocessor Core

The CPU of the i.MX31 and i.MX31L is the ARM1136JF-S core based on the ARM v6 architecture. It

supports the ARM Thumb instruction sets, features Jazelle technology (which enables direct execution

of Java byte codes), and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in

32-bit registers.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Functional Description and Application Information

The ARM1136JF-S processor core features:

™

•

Integer unit with integral EmbeddedICE logic

Eight-stage pipeline

Branch prediction with return stack

Low-interrupt latency

Instruction and data memory management units (MMUs), managed using micro TLB structures

backed by a unified main TLB

•

Instruction and data L1 caches, including a non-blocking data cache with Hit-Under-Miss

Virtually indexed/physically addressed L1 caches

64-bit interface to both L1 caches

Write buffer (bypassable)

™

High-speed Advanced Micro Bus Architecture (AMBA) L2 interface

Vector Floating Point co-processor (VFP) for 3D graphics and other floating-point applications

hardware acceleration

™

•

ETM and JTAG-based debug support

2.1.1

Performance

ARM1136JF-S operating frequency in C90LP process:

•

532 MHz (4 × 133 MHz) (wcs)

2.1.2

Memory System

The ARM1136JF-S complex includes 16 KB Instruction and 16 KB Data L1 caches. It connects to the

i.MX31 and i.MX31L L2 unified cache through 64-bit instruction (read-only), 64-bit data read/write

(bi-directional), and 64-bit data write interfaces.

The embedded 16K SRAM can be used for audio streaming data to avoid external memory accesses for

the Low Power Audio Playback, for Security, or for other applications. There is also a 32-KB ROM for

bootstrap code and other frequently-used code and data.

A ROM patch module provides the ability to patch the internal ROM. It can also initiate an external boot

by overriding the boot reset sequence by a jump to a configurable address.

Table 2 shows information about the i.MX31 and i.MX31L core in tabular form.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Functional Description and Application Information

Table 2. i.MX31/i.MX31L Core

Brief Description

Core

Acronym

Core

Name

Integrated Memory

Includes

ARM11 or ARM1136 The ARM1136™ Platform consists of the ARM1136JF-S core, the ETM

• 16 Kbyte

ARM1136 Platform

real-time debug modules, a 6 x 5 multi-layer AHB crossbar switch (MAX), and a

Vector Floating Processor (VFP).

Instruction Cache

• 16 Kbyte Data

Cache

• 128 Kbyte L2

Cache

The i.MX31/i.MX31L provide a high-performance ARM11 microprocessor core

and highly integrated system functions. The ARM Application Processor (AP)

and other subsystems address the needs of the personal, wireless, and portable

product market with integrated peripherals, advanced processor core, and

power management capabilities.

• 32 Kbyte ROM

• 16 Kbyte RAM

2.2

Module Inventory

Table 3 shows an alphabetical listing of the modules in the multimedia applications processor. A

cross-reference is provided directly to each module description for more information.

Table 3. Digital and Analog Modules

Block

Mnemonic

Functional

Grouping

Section/

Page

Block Name

Brief Description3

1-Wire®

1-Wire Interface Connectivity

Peripheral

The 1-Wire module provides bi-directional communication between 2.3.1/8

the ARM11 core and the Add-Only-Memory EPROM (DS2502).

The 1-Kbit EPROM is used to hold information about battery and

communicates with the ARM11 platform using the IP interface.

ATA

Advanced

Technology (AT) Peripheral

Attachment

Connectivity

The ATA block is an AT attachment host interface. It is designed to

interface with IDE hard disc drives and ATAPI optical disc drives.

2.3.2/8

AUDMUX Digital Audio

Multiplexer

Multimedia

Peripheral

The AUDMUX interconnections allow multiple, simultaneous

audio/voice/data flows between the ports in point-to-point or

point-to-multipoint configurations.

2.3.3/9

CCM

CSPI

Clock Control

Module

Clock

The CCM provides clock, reset, and power management control for 2.3.4/9

the i.MX31 and i.MX31L.

Configurable

SerialPeripheral Peripheral

Interface (x 3)

Connectivity

The CSPI is equipped with data FIFOs and is a master/slave

configurable serial peripheral interface module, capable of

interfacing to both SPI master and slave devices.

2.3.5/10

ECT

EMI

Embedded

Cross Trigger

Debug

The ECT is composed of three CTIs (Cross Trigger Interface) and 2.3.6/10

one CTM (Cross Trigger Matrix—key in the multi-core and multi-IP

debug strategy.

External

Memory

Interface

Memory

The EMI includes

2.3.7/11

Interface (EMI) • Multi-Master Memory Interface (M3IF)

• Enhanced SDRAM/MDDR memory controller (SDRAMC)

• NAND Flash Controller (NFC)

• Wireless External Interface Module (WEIM)

EPIT

Enhanced

Periodic

Interrupt Timer

Timer

Peripheral

The EPIT is a 32-bit “set and forget” timer which starts counting

after the EPIT is enabled by software. It is capable of providing

precise interrupts at regular intervals with minimal processor

intervention.

2.3.8/12

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Functional Description and Application Information

Table 3. Digital and Analog Modules (continued)

Functional

Block

Section/

Page

Block Name

Brief Description3

Mnemonic

Grouping

FIR

Fast InfraRed

Interface

Connectivity

Peripheral

This FIR is capable of establishing a 0.576 Mbit/s, 1.152 Mbit/s or 4 2.3.9/12

Mbit/s half duplex link via a LED and IR detector. It supports 0.576

Mbit/s, 1.152 Mbit/s medium infrared (MIR) physical layer protocol

and 4Mbit/s fast infrared (FIR) physical layer protocol defined by

IrDA, version 1.4.

GPIO

General

Purpose I/O

Module

Pins

The GPIO provides 32 bits of bidirectional, general purpose I/O.

This peripheral provides dedicated general-purpose pins that can

be configured as either inputs or outputs.

2.3.10/12

GPT

GPU

I2C

General

Purpose Timer Peripheral

Timer

The GPT is a multipurpose module used to measure intervals or

generate periodic output.

2.3.11/12

Graphics Multimedia

The GPU provides hardware acceleration for 2D and 3D graphics 2.3.12/13

algorithms.

Processing Unit Peripheral

Inter IC Connectivity

The I2C provides serial interface for controlling the Sensor Interface 2.3.13/13

and other external devices. Data rates of up to 100 Kbits/s are

supported.

Communication Peripheral

IIM

IC Identification Security

Module

The IIM provides an interface for reading—and in some cases,

programming, and overriding identification and control information

stored in on-chip fuse elements.

2.3.14/13

2.3.15/14

2.3.16/15

IPU

KPP

Image

Multimedia

The IPU supports video and graphics processing functions in the

i.MX31 and i.MX31L and interfaces to video, still image sensors,

and displays.

Processing Unit Peripheral

Keypad Port

Connectivity

Peripheral

The KPP is used for key pad matrix scanning or as a general

purpose I/O. This peripheral simplifies the software task of scanning

a keypad matrix.

MPEG-4

PCMCIA

PWM

MPEG-4 Video Multimedia

The MPEG-4 encoder accelerates video compression, following the 2.3.17/15

MPEG-4 standard

Encoder

Peripherals

PCM

Connectivity

Peripheral

The PCMCIA Host Adapter provides the control logic for PCMCIA 2.3.19/16

socket interfaces.

Pulse-Width

Modulator

Timer

Peripheral

The PWM has a 16-bit counter and is optimized to generate sound 2.3.20/16

from stored sample audio images. It can also generate tones.

RNGA

Random

Number

Generator

Accelerator

Security

The RNGA module is a digital integrated circuit capable of

generating 32-bit random numbers. It is designed to comply with

FIPS-140 standards for randomness and non-determinism.

2.3.21/16

2.3.22/16

RTC

Real Time Clock Timer

Peripheral

The RTC module provides a current stamp of seconds, minutes,

hours, and days. Alarm and timer functions are also available for

programming. The RTC support dates from the year 1980 to 2050.

RTIC

Run-Time

Integrity

Security

The RTIC ensures the integrity of the peripheral memory contents 2.3.23/17

and assists with boot authentication.

Checkers

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Functional Description and Application Information

Table 3. Digital and Analog Modules (continued)

Block

Mnemonic

Functional

Grouping

Section/

Page

Block Name

Brief Description3

SCC

Security

Controller

Module

Security

The SCC is a hardware component composed of two blocks—the 2.3.24/17

Secure RAM module, and the Security Monitor. The Secure RAM

provides a way of securely storing sensitive information. The

Security Monitor implements the security policy, checking algorithm

sequencing, and controlling the Secure State.

SDHC

SDMA

SIM

Secured Digital Connectivity

Host Controller Peripheral

The SDHC controls the MMC (MultiMediaCard), SD (Secure

Digital) memory, and I/O cards by sending commands to cards and

performing data accesses to and from the cards.

2.3.25/18

SDMA

System

The SDMA controller maximizes the system’s performance by

relieving the ARM core of the task of bulk data transfer from memory

to memory or between memory and on-chip peripherals.

2.3.26/18

Control

Peripheral

Subscriber

Identification

Module

Connectivity

Peripheral

The SIM interfaces to an external Subscriber Identification Card. It 2.3.27/20

is an asynchronous serial interface adapted for Smart Card

communication for e-commerce applications.

SJC

Secure JTAG

Controller

Debug

The SJC provides debug and test control with maximum security

and provides a flexible architecture for future derivatives or future

multi-cores architecture.

2.3.28/20

SSI

Synchronous

Serial Interface Peripheral

Multimedia

The SSI is a full-duplex, serial port that allows the chip to

communicate with a variety of serial devices, such as standard

codecs, Digital Signal Processors (DSPs), microprocessors,

peripherals, and popular industry audio codecs that implement the

inter-IC sound bus standard (I2S) and Intel AC97 standard.

2.3.29/20

UART

USB

Universal

Connectivity

Peripheral

The UART provides serial communication capability with external 2.3.30/21

devices through an RS-232 cable or through use of external

circuitry that converts infrared signals to electrical signals (for

reception) or transforms electrical signals to signals that drive an

infrared LED (for transmission) to provide low speed IrDA

compatibility.

Asynchronous

Receiver/Trans

mitter

Universal Serial Connectivity

Bus—

2 Host

Controllers and

1 OTG

• USB Host 1 is designed to support transceiverless connection to 2.3.31/21

the on-board peripherals in Low Speed and Full Speed mode,

and connection to the ULPI (UTMI+ Low-Pin Count) and Legacy

Full Speed transceivers.

• USB Host 2 is designed to support transceiverless connection to

the Cellular Modem Baseband Processor.

Peripherals

(On-The-Go)

• The USB-OTG controller offers HS/FS/LS capabilities in Host

mode and HS/FS in device mode. In Host mode, the controller

supports direct connection of a FS/LS device (without external

hub). In device (bypass) mode, the OTG port functions as

gateway between the Host 1 Port and the OTG transceiver.

WDOG

WatchdogTimer Timer

Module Peripheral

The WDOG module protects against system failures by providing a 2.3.32/23

method for the system to recover from unexpected events or

programming errors.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Functional Description and Application Information

2.3

Module Descriptions

This section provides a brief text description of all the modules included in the i.MX31 and i.MX31L,

arranged in alphabetical order.

2.3.1

1-Wire

The 1-Wire module provides bi-directional communication between the ARM11 core and the

Add-Only-Memory EPROM (DS2502). The 1-Kbit EPROM is used to hold information about battery and

communicates with the ARM11 platform using the IP interface. The ARM11 (through the 1-Wire

interface) acts as the bus master and the DS2502 device is the slave. The 1-Wire peripheral does not trigger

interrupts; hence it is necessary for the ARM11 to poll of the 1-Wire to manage the module. The 1-Wire

uses an external pin(to connect to the DS2502. Timing requirements are met in hardware with the help of

a 1 MHz clock. The clock divider generates a 1 MHz clock that is used as time reference by the state

machine. Timing requirements are crucial for proper operation, and the 1-Wire state machine and the

internal clock provide the necessary signal. The clock must configured to approximately 1 MHz. You can

then set the 1-Wire register to send and receive bits over the 1-Wire bus.

2.3.2

Advanced Technology Attachment (ATA)

The ATA block provides an AT attachment host interface for the i.MX31 and i.MX31L. Its main use is to

provide an interface with IDE hard disc drives and ATAPI optical disc drives. It interfaces with the ATA

device using industry standard ATA signals. The ATA interface is compliant to the ATA standard, and

supports following ATA standard protocols:

•

PIO modes 0, 1, 2, 3, and 4

Multiword DMA modes 0, 1, and 2

Ultra DMA modes 0, 1, 2, 3, and 4 with a bus clock of 50 MHz or higher

Ultra DMA mode 5 with bus clock of 80 MHz or higher

The ATA interface has two busses connected to it. The CPU bus provides communication with the ARM11

host processor and the DMA bus provides communication between the ATA module and the host DMA

unit. All internal ATA registers are visible from both busses, allowing enhanced DMA access to program

the interface.

There are basically two protocols that can be active at the same time on the ATA bus. The first and simplest

protocol (PIO mode access) can be started at any time by either the ARM11 or the host-enhanced DMA to

the ATA bus. The PIO mode is a slow protocol, mainly intended to be used to program an ATA disc drive,

but also possible to use to transfer data to/from the disc drive.

The second protocol is the DMA mode access. DMA mode is started by the ATA interface after receiving

a DMA request from the drive, and only if the ATA interface has been programmed to accept the DMA

request. In DMA mode, either multiword DMA or ultra DMA protocol is used on the ATA bus. All

transfers between FIFO and host IP or DMA IP bus are zero wait states transfer, so high speed transfer

between FIFO and DMA/host bus is possible.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Functional Description and Application Information

2.3.3

Digital Audio Mux (AUDMUX)

The AUDMUX provides programmable interconnecting for voice, audio, and synchronous data routing

between host serial interfaces (i.e. SSI, SAP) and peripheral serial interfaces (i.e. audio and voice codecs).

The AUDMUX allows audio system connectivity to be modified through programming (as opposed to

altering the design of the system into which the chip is designed). The design of the AUDMUX allows

multiple simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint

configurations.

Included in the AUDMUX are two types of interfaces. The internal ports connect to the processor serial

interfaces and external ports connect to off-chip audio devices and serial interfaces of other processors. A

desired connectivity is achieved by configuring the appropriate internal and external ports.

The module includes full 6-wire SSI interfaces for asynchronous receive and transmit as well as a

configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interface The AUDMUX allows

each host interface to be connected to any other host or peripheral interface in a point-to-point or

point-to-multipoint (network mode).

2.3.4

Clock Control Module (CCM)

The CCM controls the system frequency, distributes clocks to various parts of the chip, controls the reset

mechanism of the chip, and provides an advanced low-power management capability of the i.MX31 and

i.MX31L.

The CCM utilizes multiple clock sources to generate the clock signals in the i.MX31 and i.MX31L. The

external low frequency clock (CKIL) can use either a 32 kHz, 32.768 kHz or a 38.4 kHz crystal as its

source. For applications that require a high frequency clock source the CCM has a CKIH pin to which an

external high frequency clock can be connected.

The CCM provides a large number of clock outputs used to supply clocks to the MCU and the peripherals.

The i.MX31 and i.MX31L are partitioned into two asynchronous clock domains: MCU and USB, as there

are different functionality and frequency requirements from these clocks. The main clock of the MCU

clock domain is mcu_main_clk and is generated by MCU clock switch unit. The MCU clock domain is

partitioned into four synchronous clocks and two sub-domains. The main clock of this domain is called

mcu_main_clk, and it is the output of the MCU clock switch unit. The main clock of the USB clock domain

is usb_main_clk and is generated by the USB clock switch unit.

Another part of the CCM is the low-power clock gating (LPCG). The LPCG block distributes clocks to all

modules from the subdomain clocks and gates off clocks in low-power mode. Clock gating for each

module is carried out based on the specific low-power mode and the relevant bits in the MCGR register.

The power management portion of the i.MX31 and i.MX31L is controlled by the CCM. To this end, the

i.MX31 and i.MX31L are partitioned into four power domains. The i.MX31 and i.MX31L support a

versatile definition of power modes, including power and clock domains status and applied power

techniques. The power modes are Run, Wait, Doze, State Retention, Deep Sleep, and Hibernate. The CCM

supports several power management techniques that reduce active and static power consumption:

•

Dynamic Voltage Frequency Scaling (DVFS) reduces active power consumption by scaling voltage

and frequency accordingly to required MIPs.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Functional Description and Application Information

•

Dynamic Process Temperature Compensation (DPTC) reduces active power consumption by

adjusting supply voltage accordingly specific process cases, the manner in which the chip was

fabricated, and the ambient temperature.

•

State Retention Voltage (SRV) reduces static power consumption by decreasing supply voltage to

minimum State Retention level. Chip is not functional in this mode.

Active Well Bias (AWB) reduces static power consumption by applying back bias on transistors.

AWB can be applied on ARM11P. ARM11P is not functional when AWB is applied.

•

L2 Cache Power Gating—Reduces static power consumption by eliminating L2 Cache leakage.

ARM11P Power Gating—Reduces static power consumption by eliminating ARM11P leakage.

2.3.5

Configurable Serial Peripheral Interface (CSPI)

The CSPI is used for fast data communication with fewer software interrupts. There are three identical

CSPI modules in the i.MX31 and i.MX31L that provide full-duplex synchronous serial interface. It is

master/slave configurable and includes four chip selects to support multiple peripherals. In addition, the

transfer continuation function of the CSPI allows unlimited length data transfers using 32-bit wide by 8

entry FIFO for both TX and RX data DMA support. The CSPI is equipped with data FIFOs and is a

master/slave configurable serial peripheral interface module, capable of interfacing to both SPI master and

slave devices. The CSPI Ready (SPI_RDY) and Chip Select (SS) control signals enable fast data

communication with fewer software interrupts. When the CSPI module is configured as a master, it uses a

serial link to transfer data between the CSPI and an external device. A chip-enable signal and a clock signal

are used to transfer data between these two devices. When the CSPI module is configured as a slave, the

user can configure the CSPI Control register to match the external SPI master’s timing.

2.3.6

Embedded Cross Trigger (ECT)

The ECT scheme is based on the ECT debugging hardware from ARM Ltd. The ECT is composed of three

CTIs (Cross Trigger Interface) and one CTM (Cross Trigger Matrix). The ECT is key in the multi-core and

multi-IP debug strategy. The outcome is a SW-controlled debug signal matrix that receives many signals

from various sources (i.e. cores and peripherals) and propagates/routes them to the different debug

resources of the SoC. As seen in previous sections, those debug resources can include profiling

capabilities, real-time trace (trace enabled or disabled), triggers, SOC level multiplexing, and debug

interrupts.

The main advantages of using the ECT are that it provides a standardized debug scheme, in line with ARM

RealView debugger, simplifies integration with ARM debug tools. Another advantage is that within a

single debug domain, all the IPs can share the same debug resources and there is no need to duplicates

counters or real-time trace resources. One trace port can be used with one tool to track the activity of the

core and its peripherals. Since ECT should only be used during debug sessions, it is off (disabled) by

default.

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Functional Description and Application Information

2.3.7

External Memory Interface (EMI)

The EMI controls all memory accesses external to the i.MX31 and i.MX31L (read/write/erase/program)

from all the masters in the system. This is done by using two port interfaces MPG (AHB 32 bit) and

MPG64 (AHB 64 bit) toward different external memories.

The EMI includes interface elements, and controllers of external memories, as shown in the list below:

•

M3IF—Multi Master Memory Interface.

ESDCTL/MDDRC—Enhanced SDRAM/MDDR memory controller.

PCMCIA—PCMCIA memory controller.

NFC—NAND Flash memory controller.

WEIM—SRAM/PSRAM/FLASH memory controller.

All accesses via the EMI are arbitrated by the Multi Master Memory Interface (M3IF) and controlled by

the respective memory controller. The M3IF - ESDCTL/MDDRC interface is designed to reduce access

latency by generating multiple accesses through the dedicated ESDCTL/MDDRC arbitration (MAB)

module, which controls the access towards/from the Enhanced SDRAM/MDDR memory controller. For

the other memory interfaces (PCMCIA, NFC, WEIM), the M3IF only arbitrates and forwards the masters

requests received through the Master Port Gasket (MPG/MPG64) interface.

The M3IF - Multi Master Memory Interface controls memory accesses (read/write/erase/program)

from one or more masters through different port interfaces toward different external memory controllers.

The masters arrive from the ARM Platform, the SDMA, the MPEG-4 encoder, or the IPU. The controllers

are: ESDCTL/MDDRC, PCMCIA, NANDFLASH and WEIM. The interface between the M3IF and the

controllers can be divided into two different types: M3IF-ESDCTL, and M3IF-all others. For the other port

interfaces, the M3IF arbitrates and forwards the masters’ requests received through the Master Port Gasket

(MPG) interfaces and the M3IF arbitration (M3A) module toward the respective memory controller.

The Enhanced SDRAM Controller consists of 10 major blocks, including the SDRAM command state

machine controller, bank register (page and bank address comparators), Row/Column Address Multiplexer

& decoder, configuration registers, refresh request sequencer, command sequencer, size logic (splitting

access), data path (data aligner/multiplexer), MDDR interface, and the Power Down timer. Since up to two

SDRAMs can be connected to the ESDCTL, and each SDRAM has 4 banks, there are a total of 8 bank

controllers. The bank controllers can also be used as comparators for timing parameters.

The NAND Flash Controller (NFC) interfaces standard NAND Flash devices to the i.MX31 and

i.MX31L and hides the complexities of accessing the NAND Flash. It provides a glueless interface to both

8-bits and 16-bits NAND Flash parts with page sizes of 512 Bytes or 2 Kilobytes. It addressing scheme

allows it to accesses flash devices of almost limitless capacities. The 2 kilobyte RAM buffer of the NAND

Flash is used as the boot RAM during a cold reset (if the i.MX31 and i.MX31L are configured for a boot

to be carried out from the NAND Flash device). After the boot procedure completes, the RAM is available

as buffer RAM. In addition, the NAND Flash controller provides an X16 bit and X32 bit interface to the

AHB bus on the chip side, and an X8/X16 interface to the NAND Flash device on the external side.

The Wireless External Interface Module (WEIM) handles the interface to devices external to chip,

including generation of chip selects, clocks and controls for external peripherals and memory. It provides

asynchronous and synchronous access to devices with SRAM-like interface.The WEIM includes six chip

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selects for external devices, with two CS signals covering a range of 128Mbytes, and the other four each

covering a range of 32Mbytes.The 128 Mbyte range can be increased to 256Mbytes when combined with

combining the two signals. The WEIM offers selectable protection for each chip select as well as

programmable data port size. There is a programmable wait-state generator for each chip select and

support for Big Endian and Little Endian modes of operation per access.

2.3.8

Enhanced Periodic Interrupt Timer (EPIT)

The EPIT is a 32-bit “set and forget” timer which starts counting after the EPIT is enabled by software and

can generate an interrupt generation when counter reaches the Compare value. It is capable of providing

precise interrupts at regular intervals with minimal processor intervention.The EPIT is based on a 32-bit

down counter with selectable clock. It also has a 12-bit prescaler for division of input clock frequency. The

counter value can be programmed on the fly and can also be programmed to be active in both low power

and debug modes.

2.3.9

Fast InfraRed Interface (FIR)

The Fast InfraRed Interface module (FIR) is capable of establishing a 0.576 Mbit/s, 1.152 Mbit/s or 4

Mbit/s half duplex link via a LED and IR detector. It supports 0.576 Mbit/s, 1.152 Mbit/s Medium InfraRed

(MIR) physical layer protocol and 4Mbit/s Fast InfraRed (FIR) physical layer protocol defined by IrDA,

version 1.4. In addition, the Serial InfraRed (SIR) protocol, which supports data rate 115.2kbps or lower,

is implemented in UART module. The FIR interface signals are multiplexed with the UART counterpart

signals via GPIO configuration for a complete InfraRed Interface supporting SIR, MIR and FIR modes.

2.3.10 General Purpose I/O Module (GPIO)

The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be

configured as either inputs or outputs. When configured as an output, you can write to an internal register

to control the state driven on the output pin. When configured as an input, you can detect the state of the

input by reading the state of an internal register. The GPIO includes all of the general purpose input/output

logic necessary to drive a specific data to the pad and control the direction of the pad using registers in the

GPIO module. The ARM11 is able to sample the status of the corresponding pads by reading the

appropriate status register. The GPIO supports up to 32 interrupts and has the ability to identify interrupt

edges as well as generate three active high interrupts.

2.3.11 General Purpose Timer (GPT)

The General purpose timer (GPT) has a 32 bit up-counter. The timer counter value can be captured in a

falling edge. The GPT can also generate an event on ipp_do_cmpout pins and an interrupt when the timer

reaches a programmed value. It has a 12-bit prescaler providing a programmable clock frequency derived

from multiple clock sources. The GPT has one 32 bit up-counter with clock source selection, including

external clock, two input capture channels with programmable trigger edge, and three output compare

channels with programmable output mode. The GPT can perform a forced compare and can configured to

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be programmed to be active in low power and debug modes Interrupt generation can be programmed for

capture, compare, rollover events and the timers offers both restart or free-run modes of operation.

2.3.12 Graphics Processing Unit (GPU)

The GPU provides hardware acceleration for 2D and 3D graphics algorithms. The quality is sufficient for

running desk-top quality interactive graphics applications on displays whose resolution is equivalent to

VGA (and above) and whose color representation is up to 32 bits per pixel. The i.MX31 and i.MX31L’s

GPU is built around an ARM MBX R-S graphics accelerator.

The GPU operates on 3D scene data (sent as batches of triangles) that are transformed and lit by the VGP.

Triangles are written directly to the TA on a First In First Out (FIFO) basis so that the CPU is not stalled.

In addition, the SDMA can be used to perform batch transfers with very low CPU involvement. The TA

performs advanced culling on triangle data by writing the tiled non-culled triangles to the external memory.

The event manager uses SmartBuffer technology for control. As a result, any level of scene complexity is

handled in a fixed display list buffer size. The HSR engine reads the tiled data and implements per-pixel

HSR with full Z-accuracy. The resulting visible pixels are textured and shaded in Internal True Color (ITC,

24 bit per pixel) before rendering the final image for display buffer.

NOTE

The GPU is not available on the i.MX31L.

2.3.13 Inter IC Communication (I²C)

I C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,

minimizing the interconnection between devices. This bus is suitable for applications requiring occasional

communications over a short distance between many devices. The flexible I C allows additional devices

to be connected to the bus for expansion and system development.

The I C operates up to 400 kbps but it depends on the pad loading and timing (for pad requirement details

please refer to Philips I C Bus Specification, Version 2.1). The I C system is a true multiple-master bus

including arbitration and collision detection that prevents data corruption if multiple devices attempt to

control the bus simultaneously. This feature supports complex applications with multiprocessor control

and can be used for rapid testing and alignment of end products through external connections to an

assembly-line computer.

2.3.14 IC Identification Module (IIM)

The IIM provides an interface for reading and in some cases programming and/or overriding identification

and control information stored in on-chip fuse elements. The module supports laser fuses (L-Fuses) or

electrically-programmable poly fuses (e-Fuses) or both kinds.

The IIM also provides a set of volatile software-accessible signals which can be used for software control

of hardware elements, not requiring non-volatility. The IIM provides the primary user-visible mechanism

for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask

revision numbers, cryptographic keys, and various control signals requiring permanent non-volatility. The

IIM also provides up to 28 volatile control signals and a means to generate a second 168-bit SCC key.

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The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold

the values of signals visible outside the module. Up to eight arrays of fuses (L-Fuses and/or e-Fuses) are

associated with the IIM, but are instantiated outside it.

The IIM is accessible via an 8-bit IP bus interface. An 8-bit interface is used because it matches the natural

width of the fuse arrays. All registers are 32-bit aligned, to allow the module to be instantiated on IP buses

supporting only 32-bit peripherals. A subset of fuses, as well as the software-controlled volatile signals,

are capable of driving top-level nets within the SoC. These signals are hereinafter referred to as

Hardware-Visible Signals, or HW-Visible Signals. These signals are intended for feature enablement and

disablement and similar uses within the device.

Laser fuses can only be blown during chip manufacturing (at the wafer level). The e-Fuses may be blown

under software or JTAG control during IC final test, at the customer factory or in the field. They include a

mechanism to inhibit further blowing of fuses (write-protect), to support secure computing environments.

The fuse values may also be overridden by software without modifying the fuse element. Similar to the

write-protect functionality, the override functionality can also be permanently disabled. Fuse banks may

also be scan-inhibited on a per-bank basis to prevent reading and programming of fuses through the JTAG

interface.

2.3.15 Image Processing Unit (IPU)

The IPU is designed to support video and graphics processing functions in the i.MX31 and i.MX31L and

to interface to video/still image sensors and displays. The IPU can capture image data from a camera

sensor or from a TV decoder. The captured image can be sent to preprocessing or stored in an external

system memory for additional processing on the ARM11 platform. Preprocessing of data can be

programmed from the sensor or from the external system memory. There are two preprocessing channels

determined by the data destination - an encoder or a display (viewfinder mode). Preprocessing includes

downsizing with independent integer horizontal and vertical ratios, resizing with independent fractional

horizontal and vertical ratios, color space conversion, combining a video plane with a graphics plane

(blending on graphics on top of video plane),

Data postprocessing from the external system memory. The MCU can invoke a number of postprocessing

channels sequentially by re-programming the IPU after finish of previous channel frame processing.

Postprocessing includes downsizing with independent integer horizontal and vertical ratios, resizing with

independent fractional horizontal and vertical ratios, color space conversion and combining a video plane

with a graphics plane (blending on graphics on top of video plane). It also provides 90 degree rotation,

up/down and left/right flipping of the image. Post-filtering of data from the system memory with support

of the MPEG-4 (both deblocking and deringing) and H.264 post-filtering algorithms.

The IPU provides for the display of video and graphics on a synchronous (dump or memoryless) display

by displaying video and graphics on an asynchronous (smart) display. There are two mechanisms to

support smart display or graphic accelerator functionality: interleaving data and commands from a

command buffer prepared by the MCU or automatic commands generation according to a prepared

template. The data can be sent to the smart display from the system memory, internal IPU processing

modules or directly from the MCU or the system DMA controller.

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2.3.16 Keypad Port (KPP)

The Keypad Port is designed to interface with keypad matrix with 2-contact or 3-point contact keys. The

Keypad Port is designed to simplify the software task of scanning a keypad matrix. With appropriate

software support, the KPP is capable of detecting, debouncing and decoding one or multiple keys pressed

simultaneously in the keypad. The KPP supports up to 8 x 8 external key pad matrix. Its port pins can be

used as general purpose I/O. Using an open drain design the KPP includes glitch suppression circuit

design, multiple keys, long key, and standby key detection.

2.3.17 MPEG-4 Video Encoder (MPEG-4)

The MPEG-4 encoder in the i.MX31 and i.MX31L accelerates video compression, in compliance with the

MPEG-4 standard. The encoder provides several levels of compression formats including MPEG-4 simple

profile (all levels) and H.263 baseline. The encoder can encode at a pixel rate up to VGA @ 30 fps and

compressed bit-rates up to 4 Mbps. The MPEG-4 encoder provides what is essentially the complete video

processing chain, generating a Huffman-coded stream with the exception of the formation of the final

MPEG-4 stream which is the only burden put on the ARM11 processor. Additional processing provided

by the MPEG-4 encoder includes picture smoothening (low-pass filter) and camera movement

stabilization. Support for enhanced conference call format in the form of additional information inserted

within the MPEG stream, used by a MPEG-4 decoder to improve performance.

2.3.18 Memory Stick Host Controller (MSHC)

The MSHC is located between the AIPS and the Sony Memory Stick and provides support for data

transfers between the i.MX31/i.MX31L and the Memory Stick (MS). The memory stick host controller

consists of two sub modules; the MSHC gasket and the Sony Memory Stick Host Controller (SMSC). The

SMSC module, which is the actual memory stick host controller, is compatible with Sony Memory Stick

Ver 1.x and Memory Stick PRO. The gasket connects the AIPS IP bus to the SMSC interface to allow

communication and data transfers via the IP Bus.

The MSHC gasket uses a reduced IP Bus interface that supports the IP bus read/write transfers that include

a back-to-back read or write {mshc_rd_wr_data,back_to_back_rw, back_to_back_complex}. DMA

transfers also take place via the IP Bus interface.{mshc_sdma}.

A transfer can be initiated by the SDMA or the host (through AIPS) in response to an MSHC DMA request

or interrupt. The SMSC has two SDMA address modes—a single address mode and a dual address mode.

The MSHC is set to dual address mode for transfers with the SDMA. In dual address mode, when the

MSHC requests a transfer with the DMA request (XDRQ), the SDMA will initiate a transfer to the MSHC.

NOTE

All details regarding the operation of the SMSC module can be found

separately in “Memory Stick/Memory Stick PRO Host Controller IP

Specification 1.3”.

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2.3.19 PCMCIA Host Adapter (PCMCIA)

The PCMCIA Host Adapter provides the control logic for PCMCIA socket interfaces, and requires some

additional external analog power switching logic and buffering. The PCMCIA host adapter module is fully

compliant with the PCMCIA standard release 2.1 (PC Card -16) and supports one PCMCIA socket. The

adapter supports hot-insertion, card detection and removal, CompactFlash , and ATA emulation in

TrueIDE mode. The PCMCIA maps to common memory space, attribute memory space and I/O space.

Each space can be up to 64Mbyte in size. As part of the EMI complex the PCMCIA shares its pins with

the WEIM, SDRAMC, and NFC.

2.3.20 Pulse-Width Accelerator (PWM)

The PWM has a 16-bit counter and is optimized to generate sounds from stored sample audio images and

it can also generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound. The following

features characterize the PWM. the 16-bit up-counter has a source selectable clock with 4 x 16 FIFO to

minimize interrupt overhead. Clock in frequency is controlled by a12-bit prescaler for division of clock.

Capable of sound and melody generation the PWM has an active high or active low configurable output

and can be programmed to be active in low power and debug modes. The PWM can be programmed to

generate interrupts at compare and rollover events.

2.3.21 Random Number Generator Accelerator (RNGA)

The RNGA module is a digital integrated circuit capable of generating 32-bit random numbers. The

RNGA is designed to comply with FIPS-140 standards for randomness and non-determinism. The random

bits are generated by clocking shift registers with clocks derived from ring oscillators. The configuration

of the shift registers ensures statistically good data (that is, data that looks random). The oscillators with

their unknown frequencies provide the required entropy needed to create random data.

It is important to note that there is no known cryptographic proof showing that this is a secure method of

generating random data. In fact, there may be an attack against the random number generator described in

this document if its output is used directly in a cryptographic application (the attack is based on the

linearity of the internal shift registers). Due to lack of a secure method and the potential for attacks,

Freescale Semiconductor recommends that the random data produced by this module be used as an input

seed to a NIST approved (based on DES or SHA-1) or cryptographically secure (RSA Generator or BBS

Generator) random number generation algorithm. It is also recommended that other sources of entropy be

used along with the RNGA to generate the seed to the pseudo-random algorithm. But this is optional. The

more random sources combined to create the seed the better.

The RNGA uses a 32-bit IP Bus slave interface and contains a 16 × 32 FIFO. It provides a Secure mode

or operations as well as a power saving mode

2.3.22 Real Time Clock (RTC)

The RTC module maintains the system clock, provides stopwatch, alarm, and interrupt functions, and

supports the following features.

•

Full clock—days, hours, minutes, seconds

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•

Minute countdown timer with interrupt

Programmable daily alarm with interrupt

Sampling timer with interrupt

Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts

Operation at 32.768 kHz, 32 kHz, or 38.4 kHz (determined by reference clock crystal)

The prescaler converts the incoming crystal reference clock to a 1 Hz signal which is used to increment

the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC

interrupts when the TOD settings reach programmed values. The sampling timer generates

fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on very small

boundaries.

2.3.23 Run-TIme Integrity Checker (RTIC)

The RTIC is one of the security components in the i.MX31 and i.MX31L. Its purpose is to ensure the

integrity of the peripheral memory contents and assist with boot authentication. The RTIC has the ability

to verify the memory contents during system boot and during run-time execution. If the memory contents

at runtime fail to match the hash signature, an error in the security monitor is triggered.

The RTIC provides SHA-1 message authentication and receives input via the DMA (AMBA-AHB Lite bus

master) interface. It uses segmented data gathering to support non-contiguous data blocks in memory (up

to two segments per block) and works during and with High Assurance Boot (HAB) process. It provides

Secure-scan DFT security and support for up to four independent memory blocks. The RTIC has both a

programmable DMA bus duty cycle timer and its own watchdog timer.

The RTIC operates in two primary modes: One time hash mode and continuous hash mode.

The One time hash mode is used during HAB for code authentication or one time integrity checking during

which it stores the hash result internally and signals the ARM11 using an interrupt. In Continuous hash

mode the RTIC is used continuously to verify integrity of memory contents by checking re-generated hash

against internally stored values and interrupts host only if error occurs.

2.3.24 Security Controller Module (SCC)

Security and security services, in an embedded or data processing platform, refer to the i.MX31 and

i.MX31L processor’s ability to provide mandatory and optional information protection services.

Information in this context refers to all embedded data, both program store and data load. Therefore, a

secure platform is intended to protect information/data from unauthorized access in the form of inspection

(read), modification (write) or execution (use). Security assurance refers to the degree of confidence that

security claims are actually met and is therefore associated with the resources available to, and the integrity

of, a given security design.

The SCC is a hardware security component composed of two subblocks, the Secure RAM and the Security

Monitor Overall its primary functionality is associated with establishing a centralized security state

controller and hardware security state with a hardware configured, unalterable security policy. It also

provides an uninterruptedly hardware mechanism to detect and respond to threat detection signals

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(specifically platform test access signals). It also serves as a device unique data protection/encryption

resource to enable off chip storage of security sensitive data and an internal storage resource which

automatically and irrevocably destroys plain text security sensitive data upon threat detection.

2.3.25 Secure Digital Host Controller (SDHC)

The MultiMediaCard (MMC), is a universal low cost data storage and communication media that is

designed to cover a wide area of applications as electronic toys, organizers, PDAs and smart phones etc.

The MMC communication is based on an advanced 7 pin serial bus designed to operate in a low voltage

range. The Secure Digital Card (SD), is an evolution of MMC technology, with two additional pins in the

form factor. It is specifically designed to meet the security, capacity, performance, and environment

requirement inherent in newly emerging audio and video consumer electronic devices. The physical form

factor, pin assignment and data transfer protocol are forward compatible with the MultiMediaCard with

some additions. Under SD, it can be categorized into Memory and I/O. The memory card invokes a

provide the capability for a higher memory capacity. The I/O card provides high-speed data I/O with low

power consumption for mobile electronic devices.

The SDHC controls the MMC, SD memory, and I/O cards by sending commands to cards and performing

data accesses to/from the cards.The Multimedia Card/Secure Digital Host module (MMC/SD) integrates

both MMC support along with SD memory and I/O functions. The SDHC is fully compatible with the

MMC System Specification Version 3.0 as well as compatible with the SD Memory Card Specification

1.0, and SD I/O Specification 1.0 with 1/4 channel(s). The maximum data rate in 4-bit mode is 100 Mbps.

The SDHC uses a built-in programmable frequency counter for SDHC bus and provides a maskable

hardware interrupt for SDIO Interrupt, Internal status & FIFO status and it has a 32x16-bit data FIFO

buffer built-in.

2.3.26 SDMA

The SDMA architecture offers highly-competitive DMA Controller features combined with

software-based virtual-DMA flexibility. Furthermore, it enables data transfers between peripheral I/O

devices and internal/external memories.

The Smart Direct Memory Access (SDMA) controller is a critical piece of hardware in a highly integrated

IC like a 3G Baseband chip or a Multimedia SoC. It helps maximizing system performance by off-loading

the CPU in dynamic data routing. It contains a custom RISC core along with its RAM, ROM, the three

DMA units, the CRC unit, and the scheduler.

The SDMA is used to execute short routines that perform DMA transfers; these routines or programs are

called scripts hereafter. The Instruction-Set is composed of single cycle instructions with the exception of

Load/Store instructions to the internal memory (RAM, ROM and memory mapped registers), to the

registers of the DMA and CRC units, and Branch instructions that may require several cycles to execute.

The SDMA core is interfaced to its own memory via the SDMA System Bus. The SDMA System Bus

supports a 32-bit data path and a 16-bit address bus. DMA units are interfaced to the CORE via the

Functional Unit Bus and use dedicated registers to perform DMA transfers.

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The SDMA memory is constituted of a ROM and a RAM. The ROM contains startup scripts (for example,

boot code) and other common utilities which are referenced by the scripts that reside in the RAM. The

internal RAM is divided into a context area and a script area.

Every transfer channel requires one context area to keep the contents of all the CORE and units registers

while it is inactive. Channel scripts are downloaded into the internal RAM by the SDMA using a dedicated

channel that is started during the boot sequence. Downloads are invoked using command and pointers

provided by the MCU or DSP. Every channel contains a corresponding channel script that is located in

RAM and/or ROM; and it can be reconfigured independently on an “as needed” basis. This permits a wide

range of SDMA functionality while using the lowest internal memory footprint possible. Channel scripts

can be stored in an external, large capacity, FLASH memory and downloaded when needed. The SDMA

can be configured with any mixture of scripts to enable an endless combination of supported services.

The scheduler is responsible for monitoring and detecting DMA requests, mapping them to channels and

mapping individual channels to a pre-configured priority. At any point in time, the scheduler will present

the highest priority channel requiring service to the SDMA core. A special SDMA core instruction is used

to “conditionally yield” the current channel being executed to an eligible channel that requires service. If,

and only if, an eligible channel is pending will the current execution of a channel be pre-empted. There are

two “yield” instructions that differently determine the eligible channels: in the first version, eligible

channels are pending channels with a strictly higher priority than the current channel priority; in the second

version (“yieldage”), eligible channels are pending channels with a priority that is greater or equal to the

current channel priority. The scheduler detects devices needing service through its 32 DMA request inputs.

After a request is detected, the scheduler determines the channel(s) that is (are) triggered by this request

and marks it (them) as pending in the “Channel Pending (EP)” register. The priorities of all the pending

channels are combined and continuously evaluated in order to update the highest pending priority. The

channel pending flag is cleared by the channel script when the transfer has completed.

The MCU Control module contains the control registers which are used to configure the 32 individual

channels. There are 32 Channel Enable Registers: every register is used to map one DMA request to any

desired combination of channels. The 32 Priority Registers are used to assign a programmable 1-of-7 level

priority to every possible channel. This module also contains all other control registers that can be accessed

by the MCU.

The DSP Control module, when available, contains a restricted set of registers that enable the DSP to

control the channels that have been allocated by the MCU approximately the same set of registers as the

MCU Control module. The SDMA is either owned by the MCU or the DSP, never by both at the same time

for security reasons. The master (MCU or DSP) that owns the SDMA is able to allocate channels to the

other master; the latter that is not controlling the SDMA has a limited access to its control registers.

The 32 DMA requests that are connected to the scheduler come from a variety of sources. The “receive

examples of DMA requests that can be connected to the SDMA. These requests can be used to trigger a

specific SDMA channel, or several channels. This feature can be used to realize a “just-in-time” data

exchange between the two processors to relax the requirement to meet critical deadlines.

The embedded nature of the SDMA requires on-chip debug capability to assure product quality and

reliability and to realize the full performance capabilities of the core. The OnCE compatible debug port

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includes support for setting breakpoints, Single-Step & Trace and register dump capability. In addition, all

memory locations are accessible from the debug port.

2.3.27 Subscriber Identification Module (SIM)

The SIM Interface Module (SIM) is designed to facilitate communication to SIM cards or Eurochip

pre-paid phone cards. The SIM module has two ports that can be used to interface with the various cards.

The interface with the MCU is via a 16-bit connection, The SIM module I/O interface can be operated in

one of three modes of operation.

Two wire interface. In this mode both the IC pin RX and IC pin TX are used to interface to the smartcard.

This is activated by resetting the 3volt bit in the port control register to a “0”.

External one wire interface. In this mode the IC pins RX and TX are tied together external to the IC and

routed to the smartcard. The 3volt bit in the port control register is reset to a “0” and the OD bit in the

OD_CONFIG register is set to a “1”. For this interface to work properly the IC pin (RX-TX) must be pulled

high by a resistor. The value should be selected small enough to give a fast enough rise time.

Internal one wire interface. In this mode the IC pin TX is routed to the smartcard. The receive pin RX is

connected to the TX pin internal to the IC. The 3volt bit in the port control register is reset to a “1” and the

OD bit in the OD_CONFIG register is set to a “1”. For this interface to work properly the IC pin TX must

be pulled high by a resistor. The value should be selected small enough to give a fast enough rise time.

2.3.28 Secure JTAG Controller (SJC)

The IEEE1149.1 JTAG test access port (TAP) supports IEEE1149.1 v2001 standard features, access to

OnCE and ICE of each Core, debug features to improve controllability and absorbability of the Cores for

debug purposes, manufacturing test features (special test modes, PLL bypass, memory BIST and

Burn-in...). The SJC provides debug and test control with the maximum security and provide a flexible

architecture for future derivatives or future multi-cores architecture (how to add-remove a Core, software

and hardware implications). JTAG pins can be muxed to the PCS bus connectors.

The SJC operates at maximum 1/8 the slowest frequency of the accessed OnCE/ICE. For example in

normal operation (no core in low-power mode), this frequency will be 1/8 of the SDMA frequency if this

core is present in the TDI-TDO chain (serially connected with other cores or standalone). User needs also

to take into account the 25MHz frequency limitation on the CE bus.

In addition, secure JTAG options are provided to protect debug resources from attacks by unauthorized

users. The secure JTAG design prevents the debug architecture from compromising security.

2.3.29 Synchronous Serial Interface (SSI)

The SSI is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices.

These serial devices can be standard codecs, Digital Signal Processors (DSPs), microprocessors,

peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S) and

Intel AC97 standard.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Functional Description and Application Information

SSI is typically used to transfer samples in a periodic manner. The SSI consists of independent transmitter

and receiver sections with independent clock generation and frame synchronization.

The SSI contains independent (asynchronous) or shared (synchronous) transmit and receive sections with

separate or shared internal/external clocks and frame syncs, operating in Master or Slave mode. The SSI

can work in normal mode operation using frame sync and in Network mode operation allowing multiple

devices to share the port with as many as thirty-two time slots. The SSI provides 2 sets of Transmit and

Receive FIFOs. Each of the four FIFOs is 8x24 bits. The two sets of Tx/Rx FIFOs can be used in Network

mode to provide 2 independent channels for transmission and reception. It also has programmable data

interface modes such like I2S, LSB, MSB aligned and programmable word lengths. Other program options

include frame sync and clock generation and programmable I2S modes (Master, Slave or Normal).

Oversampling clock, ccm_ssi_clk available as output from SRCK in I2S Master mode.

In addition to AC97 support the SSI has completely separate clock and frame sync selections for the

receive and transmit sections. In AC97 standard, the clock is taken from an external source and frame sync

is generated internally. the SSI also has a programmable internal clock divider and Time Slot Mask

Registers for reduced CPU overhead (for Tx and Rx both).

2.3.30 Universal Asynchronous Receiver/Transmitter (UART)

The i.MX31 and i.MX31L contain five UART modules, Each UART module is capable of standard

RS-232 non-return-to-zero (NRZ) encoding format and IrDA-compatible infrared modes. The UART

provides serial communication capability with external devices through an RS-232 cable or through use

of external circuitry that converts infrared signals to electrical signals (for reception) or transforms

electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA

compatibility.

The UART transmits and receives characters containing either 7 or 8 bits (program selectable). To

transmit, data is written from the IP data bus (Sky-Blue line interface) to a 32-byte transmitter FIFO

(TxFIFO). This data is passed to the shift register and shifted serially out on the transmitter pin (TXD). To

receive, data is received serially from the receiver pin (RXD) and stored in a 32-half-words-deep receiver

FIFO (RxFIFO). The received data is retrieved from the RxFIFO on the IP data bus. The RxFIFO and

TxFIFO generate maskable interrupts as well as DMA Requests when the data level in each of the FIFO

reaches a programmed threshold level.

The UART generates baud rates based on a dedicated input clock and its programmable divisor. The

UART also contains programmable auto baud detection circuitry to receive 1 or 2 stop bits as well as odd,

even, or no parity. The receiver detects framing errors, idle conditions, BREAK characters, parity errors,

and overrun errors.

2.3.31 Universal Serial Bus (USB)

The i.MX31 and i.MX31L provides three USB ports. The USB module provides high performance USB

On-The-Go (OTG) functionality, compliant with the USB 2.0 specification, the OTG supplement and the

ULPI 1.0 Low Pin Count specification. The module consists of 3 independent USB cores, each controlling

1 USB port.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Functional Description and Application Information

In addition to the USB cores, the module provides for a Transceiverless Link (TLL) operation on host ports

1 and 2 and allows for routing the OTG transceiver interface to HOST port 1 such that this transceiver can

be used to communicate with a USB peripheral connected to host port 1.

The USB module has 2 connections to the CPU bus. One IP-bus connection for register accesses and one

AHB-bus connection for DMA transfer of data to and from the FIFOs.The USB module includes the

following features:

•

Full Speed / Low speed Host only core (HOST 1)

Transceiverless Link Logic (TLL) for on board connection to a FS/LS USB peripheral.

Bypass mode to route Host Port 1 signals to OTG I/O port

High Speed / Full Speed / Low Speed Host Only core (HOST2)

Full Speed / Low Speed interface for Serial transceiver.

TLL function for direct connection to USB peripheral in FS/LS (serial) operation

High speed OTG core

The USB module has 2 main modes of operation; Normal mode and Bypass mode. Furthermore, the USB

interfaces can be configured for High Speed operation (480 Mbps) and/or Full/Low speed operation

(12/1.5 Mbps). In normal mode, each USB core controls its corresponding PORT. Each port can work in

1 or more modes PHY mode: In this mode, an external serial transceiver is connected to the port. This is

used for off-board USB connections. TLL mode: In TLL mode, internal logic is enabled to emulate the

functionality of 2 back-to-back connected transceivers. This mode is typically used for on-board USB

connections to USB-capable peripherals. Host Port 2 supports ULPI and Serial Transceivers.

The OTG port requires a transceiver and is intended for off-board USB connections.

Serial Interface mode–In serial mode, a serial OTG transceiver must be connected. The port does not

support dedicated signals for OTG signaling. Instead, a transceiver with built-in OTG registers must be

used. Typically, the Transceiver registers are accessible over an I2C or SPI interface.

ULPI Mode–It this mode, a ULPI transceiver is connected to the port pins to support High-speed off board

USB connections. ULPI mode is activated by writing the following:

Bypass mode–Bypass mode affects the operation of the OTG port and HOST port 1. This mode is only

available when a serial transceiver is used on the OTG port, and the peripheral device on port 1 is using a

TLL connection.

Bypass mode is activated by setting the bypass bit in the USBCONTROL register. In this mode, the USB

OTG port connections are internally routed to the USB HOST 1 port, such that the transceiver on the OTG

port connects to a peripheral USB device on HOST port 1. The OTG core and the HOST 1 core are

disconnected from their ports when bypass is active.

Low Power mode–Each of the 3 USB cores has an associated power control module that is controlled by

the USB core and clocked on a 32 kHz clock. When a USB bus is idle, the tranceiver can be placed in low

power mode (suspend), after which the clocks to the USB core can be stopped. The 32 kHz low power

clock must remain active as it is needed for wakeup detection.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

2.3.32 Watchdog Module (WDOG)

The Watchdog (WDOG) timer module protects against system failures by providing a method of escaping

from unexpected events or programming errors. Once the WDOG module is activated, it must be serviced

by software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the

WDOG Timer module either asserts the wdog signal or a system reset signal wdog_rst depending on

software configuration. The WDOG Timer module also generates a system reset via a software write to

the Watchdog Control Register (WCR), a detection of a clock monitor event, an external reset, an external

JTAG reset signal, or if a power-on-reset has occurred.

3 Signal Descriptions

This section:

•

Identifies and defines all device signals in text, tables, and (as appropriate) figures. Signals can be

organized by group, as applicable.

Contains pin-assignment/contact-connection diagrams, if the sequence of information in the data

sheet requires them to be included here. Otherwise, these figures appear in Section 5, “Package

Information and Pinout.”

3.1

i.MX31 and i.MX31L I/O Pad Signal Settings

This section identifies and defines all device signals in Table 4 on page 23, Table 6 on page 39, and Table 7

on page 56.

3.1.1

Functional Multiplexing

Table 4 shows functional multiplexing information. Functional multiplexing allows the user to select the

function of each pin by configuring the appropriate GPIO registers when those pins are multiplexed to

provide different functions.

Table 4. Functional Multiplexing

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Pin Name Group

Description

Mode Mode Mode Mode Mode Mode GPIO

CAPTURE

Timer

Timer input Capture or

Timer1 input clock. GPIO

user for Memstick1 Card

detect

ATA_DATA14

–

sw_mux_ctl_

capture

–

CMP2

–

MCU1_

[6:0]

COMPARE

Timer Timer Output Compare for ATA_DATA15

timers 1 2 3. GPIO used

–

sw_mux_ctl_ CAP2

compare

CMP3

–

ipp_epit ipp_epit

–

MCU1_

for Memstick2 card detect

[6:0]

WATCHDOG

_RST

WTDG

watchdog reset.

–

sw_mux_ctl_

watchdog_rs

t[6:0]

–

IPU_FL

ASH_S

TROBE

–

PWMO

PWM

PWM output.

ATA_IORDY

–

sw_mux_ctl_ PC_SP

pwmo[6:0] KOUT

–

MCU1_

GPIO1_0

GPIO1

GPIO reserved for IRQs

sw_mux_ctl_ EXTDM

–

MCU1_

gpio1_0

[6:0]

A_0

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Pin Name Group

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Description

Mode Mode Mode Mode Mode Mode GPIO

GPIO1_1

GPIO1_2

GPIO1_3

GPIO1_4

GPIO1_5

GPIO1_6

GPIO3_0

GPIO3_1

SCLK0

GPIO1 GPIO reserved for IRQs &

DMA events

–

sw_mux_ctl_ EXTDM

–

MCU1_

gpio1_1

[6:0]

A_1

GPIO1 GPIO reserved for IRQs &

DMA events

sw_mux_ctl_ EXTDM

–

MCU1_

gpio1_2

[6:0]

A_2

GPIO1

GPIO reserved for IRQs

GPIO used by USBH1

sw_mux_ctl_

gpio1_3

[6:0]

–

MCU1_

sw_mux_ctl_ USBH1

MCU1_

gpio1_4

[6:0]

_SUSP

END

GPIO reserved for PMIC

IRQ

sw_mux_ctl_

gpio1_5

[6:0]

–

MCU1_

GPIO1 GPIO reserved for Tamper TAMPER_DE

sw_mux_ctl_

gpio1_6

[6:0]

MCU1_

detect

TECT

GPIO3

SIM

GPIO used as IPU CSI

chip select3

SPLL_BYPA

SS_CLK

sw_mux_ctl_

gpio3_0

[6:0]

MCU3_

GPIO used as IPU CSI

chip select4

UPLL_BYPA

SS_CLK

sw_mux_ctl_

gpio3_1

[6:0]

MCU3_

SIM Port 0

–

sw_mux_ctl_ CTI_TRI DISPB_ obs_int_

MCU3_

sclk0[6:0]

G_IN_1 D2_CS

SRST0

SIM

sw_mux_ctl_

srst0[6:0]

–

DISPB_ obs_int_

D12_VS

YNC

MCU3_

SVEN0

SIM

sw_mux_ctl_ CTI_TRI

sven0[6:0] G_IN_1

–

obs_int_

MCU2_

STX0

SIM

sw_mux_ctl_ CTI_TRI

–

obs_int_

MCU2_

stx0[6:0]

G_IN_1

SRX0

SIM

SIM Port 0

–

sw_mux_ctl_

srx0[6:0]

–

obs_int_

–

MCU2_

SIMPD0

sw_mux_ctl_

simpd0

–

MCU2_

[6:0]

CKIH

RESET_IN

POR

Clock & 13-20 MHz clk input Osc

Reset&

–

input

Clock &

Reset&

Master Reset from

external power mgt chip

No MUX allowed

RESET_IN

sw_mux_ctl_

reset_in_b

[6:0]

Clock &

Reset&

Power On Reset

Clock out signal

Boot Mode 0

–

CLKO

Clock &

Reset&

BOOT_MODE Clock &

Reset&

BOOT_MODE Clock &

Boot Mode 1

Reset&

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Pin Name Group

Description

Mode Mode Mode Mode Mode Mode GPIO

BOOT_MODE Clock &

Boot Mode 2

–

Reset&

BOOT_MODE Clock &

Boot Mode 3

Boot Mode 4

–

Reset&

BOOT_MODE Clock &

Reset&

CKIL

Clock &

Reset&

32 kHz clk input

power shut-off input

POWER_FAIL Clock &

Reset&

VSTBY

DVFS0

DVFS1

VPG0

Clock & Power management State

Reset&

sw_mux_ctl_

vstby[6:0]

retention

Clock &

Reset&

Power management

voltage change

sw_mux_ctl_

dvfs0[6:0]

Clock &

Reset&

Power management

voltage change

sw_mux_ctl_

dvfs1[6:0]

Clock &

Reset&

Power management

power gating

sw_mux_ctl_

vpg0[6:0]

VPG1

Clock &

Reset&

Power management

power gating

sw_mux_ctl_

vpg1[6:0]

EMI

EIM address 0

EIM address 1

EIM address 2

EIM address 3

EIM address 4

EIM address 5

EIM address 6

EIM address 7

EIM address 8

EIM address 9

EIM address 10

–

sw_mux_ctl_

a0[6:0]

–

sw_mux_ctl_

a1[6:0]

sw_mux_ctl_

a2[6:0]

sw_mux_ctl_

a3[6:0]

sw_mux_ctl_

a4[6:0]

sw_mux_ctl_

a5[6:0]

sw_mux_ctl_

a6[6:0]

sw_mux_ctl_

a7[6:0]

sw_mux_ctl_

a8[6:0]

sw_mux_ctl_

a9[6:0]

A10

MA10

A11

A12

sw_mux_ctl_

a10[6:0]

sw_mux_ctl_

ma10[6:0]

EIM address 11

EIM address 12

sw_mux_ctl_

a11[6:0]

sw_mux_ctl_

a12[6:0]

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Pin Name Group

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Description

Mode Mode Mode Mode Mode Mode GPIO

A13

A14

EMI

EIM address 13

EIM address 14

EIM address 15

EIM address 16

EIM address 17

EIM address 18

EIM address 19

EIM address 20

EIM address 21

EIM address 22

EIM address 23

EIM address 24

EIM address 25

EIM Bank Address

–

sw_mux_ctl_

a13[6:0]

–

sw_mux_ctl_

a14[6:0]

–

A15

sw_mux_ctl_

a15[6:0]

A16

sw_mux_ctl_

a16[6:0]

A17

sw_mux_ctl_

a17[6:0]

A18

sw_mux_ctl_

a18[6:0]

A19

sw_mux_ctl_

a19[6:0]

A20

sw_mux_ctl_

a20[6:0]

A21

sw_mux_ctl_

a21[6:0]

A22

sw_mux_ctl_

a22[6:0]

A23

sw_mux_ctl_

a23[6:0]

A24

sw_mux_ctl_

a24[6:0]

A25

sw_mux_ctl_

a25[6:0]

SDBA1

SDBA0

sw_mux_ctl_

sdba1[6:0]

sw_mux_ctl_

sdba0[6:0]

SD0

SD1

EMI

DDR/SDRAM Data 0

DDR/SDRAM Data 1

DDR/SDRAM Data 2

DDR/SDRAM Data 3

DDR/SDRAM Data 4

DDR/SDRAM Data 5

DDR/SDRAM Data 6

DDR/SDRAM Data 7

DDR/SDRAM Data 8

DDR/SDRAM Data 9

DDR/SDRAM Data 10

DDR/SDRAM Data 11

DDR/SDRAM Data 12

DDR/SDRAM Data 13

DDR/SDRAM Data 14

DDR/SDRAM Data 15

DDR/SDRAM Data 16

DDR/SDRAM Data 17

DDR/SDRAM Data 18

DDR/SDRAM Data 19

DDR/SDRAM Data 20

DDR/SDRAM Data 21

DDR/SDRAM Data 22

–

SD2

SD3

SD4

SD5

SD6

SD7

SD8

SD9

SD10

SD11

SD12

SD13

SD14

SD15

SD16

SD17

SD18

SD19

SD20

SD21

SD22

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Pin Name Group

Description

Mode Mode Mode Mode Mode Mode GPIO

SD23

SD24

SD25

SD26

SD27

SD28

SD29

SD30

SD31

DQM0

EMI

DDR/SDRAM Data 23

DDR/SDRAM Data 24

DDR/SDRAM Data 25

DDR/SDRAM Data 26

DDR/SDRAM Data 27

DDR/SDRAM Data 28

DDR/SDRAM Data 29

DDR/SDRAM Data 30

DDR/SDRAM Data 31

–

Byte strobe DDR data

enable

sw_mux_ctl_

dqm0[6:0]

DQM1

DQM2

DQM3

EB0

EMI

Byte strobe DDR data

enable

–

sw_mux_ctl_

dqm1[6:0]

–

Byte strobe DDR data

enable

sw_mux_ctl_

dqm2[6:0]

Byte strobe DDR data

enable

sw_mux_ctl_

dqm3[6:0]

LSB Byte strobe WEIM

data enable; Controls

D[7:0]

sw_mux_ctl_

eb0[6:0]

EB1

EMI

LSB Byte strobe WEIM

data enable Controls

D[15:8]

–

sw_mux_ctl_

eb1[6:0]

–

EMI

Memory Output enable

–

sw_mux_ctl_

oe[6:0]

–

CS0

CS1

CS2

CS3

CS4

CS5

Chip select 0

sw_mux_ctl_

cs0[6:0]

Chip select 1

sw_mux_ctl_

cs1[6:0]

Chip select 2/ SDRAM

Sync Flash chip select

sw_mux_ctl_

cs2[6:0]

Chip select 3/ SDRAM

Sync Flash chip select

sw_mux_ctl_

cs3[6:0]

Chip select 4

sw_mux_ctl_

cs4[6:0]

Chip select 5

sw_mux_ctl_

cs5[6:0]

ECB

LBA

EMI

End Current Burst

Load Base Address

–

sw_mux_ctl_

lba[6:0]

BCLK

EMI

used by Flash for burst

mode

–

sw_mux_ctl_

bclk[6:0]

–

read/write signal or WE for

external DRAM

sw_mux_ctl_

rw[6:0]

RAS

SDRAM row address

select

sw_mux_ctl_

ras[6:0]

CAS

SDRAM column address

select

sw_mux_ctl_

cas[6:0]

SDWE

SDCKE0

SDCKE1

SDCLK

SDRAM write enable

SDRAM clock enable0

SDRAM clock enable1

sw_mux_ctl_

sdwe[6:0]

sw_mux_ctl_

sdcke0[6:0]

sw_mux_ctl_

sdcke1[6:0]

SDRAM clock DDR clock

pad

sw_mux_ctl_

sdclk[6:0]

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Pin Name Group

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Description

Mode Mode Mode Mode Mode Mode GPIO

SDCLK

SDQS0

SDQS1

SDQS2

SDQS3

NFWE

DDR

EMI

False pad DDR_CLK

DDR sample strobe

NANDF

–

ATA_DATA7 ATA_IN sw_mux_ctl_

TRQ nfwe_b[6:0]

USBH2

_DATA2

TRACE

DATA_0

MCU1_

NFRE

EMI

NANDF

ATA_DATA8 ATA_BU sw_mux_ctl_

–

USBH2

_DATA3

–

TRACE

DATA_1

–

MCU1_

FFER_E nfre_b[6:0]

NFALE

NFCLE

NFWP

NFCE

NFRB

D15

D14

D13

D12

D11

D10

EMI

NANDF

ATA_DATA9 ATA_DM sw_mux_ctl_

–

USBH2

_DATA4

–

TRACE

DATA_2

–

MCU1_

ARQ

ATA_DATA10 ATA_DA sw_mux_ctl_

nfcle[6:0]

nfale[6:0]

USBH2

_DATA5

TRACE

DATA_3

MCU1_

ATA_DATA11 ATA_DA sw_mux_ctl_ NFWP USBH2

TRACE

DATA_4

MCU1_

nfwp_b[6:0]

_DATA6

ATA_DATA12 ATA_DA sw_mux_ctl_

–

USBH2

_DATA7

TRACE

DATA_5

MCU1_

–

nfce_b[6:0]

ATA_DATA13

sw_mux_ctl_

nfrb[6:0]

–

TRACE

DATA_6

MCU1_

PCMCIA/WEIM/NANDF

Data

–

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PCMCIA/WEIM/NANDF

Data

PC_CD1

PCMCIA

sw_mux_ctl_ SD2_ MSHC2

pc_cd1_b

CMD

_SCLK

[6:0]

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Pin Name Group

Description

Mode Mode Mode Mode Mode Mode GPIO

PC_CD2

PC_WAIT

EMI

PCMCIA

–

sw_mux_ctl_ SD2_CL MSHC2

–

pc_cd2_b[6:

_BS

PCMCIA

sw_mux_ctl_ SD2_DA MSHC2

–

pc_wait_b[6:

TA0

_SDIO_

DATA0

PC_READY

PC_PWRON

sw_mux_ctl_ SD2_DA MSHC2

pc_ready[6:0

TA1

_DATA1

]

sw_mux_ctl_ SD2_DA MSHC2

pc_pwron[6:

TA3

_DATA2

PC_VS1

PC_VS2

PC_BVD1

PC_BVD2

PC_RST

IOIS16

EMI

PCMCIA

–

sw_mux_ctl_ SD2_DA MSHC2

pc_vs1[6:0] TA2 _DATA3

–

sw_mux_ctl_ USBH2 UART5_

pc_vs2[6:0] _DATA2 RTS

sw_mux_ctl_ USBH2 UART5_

pc_bvd1[6:0] _DATA3 RXD

sw_mux_ctl_ USBH2 UART5_

pc_bvd2[6:0] _DATA4 TXD

sw_mux_ctl_ USBH2 UART5_

pc_rst[6:0] _DATA5

CTS

sw_mux_ctl_ USBH2

iois16[6:0] _DATA6

–

PC_RW

sw_mux_ctl_ USBH2

pc_rw_b[6:0] _DATA7

–

PC_POE

sw_mux_ctl_

pc_poe[6:0]

–

M_REQUEST

M_GRANT

CSI_D4

EMI

EMI sharing

–

IPU (CSI) GPIO used as IPU CSI

chip select1

sw_mux_ctl_

csi_d4[6:0]

CTI_TRI MCU3_

G_OUT

_1_2

CSI_D5

CSI_D6

CSI_D7

IPU (CSI) GPIO used as IPU CSI

chip select2

–

sw_mux_ctl_

csi_d5[6:0]

–

CTI_TRI MCU3_

G_OUT

_1_3

IPU (CSI) Sensor Port Data 0 (bit 6) ATA_DATA0

IPU (CSI) Sensor Port Data 1 (bit 7) ATA_DATA1

sw_mux_ctl_

csi_d6[6:0]

CTI_TRI MCU3_

G_OUT

_1_4

sw_mux_ctl_

csi_d7[6:0]

CTI_TRI MCU3_

G_OUT

_1_5

CSI_D8

CSI_D9

IPU (CSI) Sensor Port Data 2 (bit 8) ATA_DATA2

IPU (CSI) Sensor Port Data 3 (bit 9) ATA_DATA3

IPU (CSI) Sensor Port Data 4 (bit 10) ATA_DATA4

IPU (CSI) Sensor Port Data 5 (bit 11) ATA_DATA5

IPU (CSI) Sensor Port Data 6 (bit 12) ATA_DATA6

IPU (CSI) Sensor Port Data 7 (bit 13) ATA_DATA7

IPU (CSI) Sensor Port Data 8 (bit 14) ATA_DATA8

IPU (CSI) Sensor Port Data 9 (bit 15) ATA_DATA9

–

sw_mux_ctl_

csi_d8[6:0]

–

MCU3_

sw_mux_ctl_

csi_d9[6:0]

MCU3_

CSI_D10

CSI_D11

CSI_D12

CSI_D13

CSI_D14

CSI_D15

sw_mux_ctl_

csi_d10[6:0]

MCU3_

sw_mux_ctl_

csi_d11[6:0]

MCU3_

sw_mux_ctl_

csi_d12[6:0]

MCU3_

sw_mux_ctl_

csi_d13[6:0]

MCU3_

sw_mux_ctl_

csi_d14[6:0]

MCU3_

sw_mux_ctl_

csi_d15[6:0]

MCU3_

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Pin Name Group

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Description

Mode Mode Mode Mode Mode Mode GPIO

CSI_MCLK IPU (CSI) Sensor Port master Clock ATA_DATA10

CSI_VSYNC IPU (CSI) Sensor port vertical sync ATA_DATA11

–

sw_mux_ctl_

csi_mclk[6:0]

–

MCU3_

–

sw_mux_ctl_

csi_vsync[6:

–

MCU3_

CSI_HSYNC IPU (CSI)

CSI_PIXCLK IPU (CSI)

Sensor port horizontal

Sync

ATA_DATA12

ATA_DATA13

–

sw_mux_ctl_

csi_hsync[6:

MCU3_

Sensor port data latch

clock

sw_mux_ctl_

csi_pixclk[6:

MCU3_

I2C_CLK

I2C_DAT

STXD3

I2C

I2C clock

I2C data

TxD

ATA_DATA14

ATA_DATA15

–

sw_mux_ctl_

i2c_clk[6:0]

–

IPU_DI

AGB[0]

–

IPU_DI

AGB[1]

AudioPort

3-BB

ATA_DATA7 USBH2 sw_mux_ctl_

_DATA2 stxd3[6:0]

IPU_DI TRACE EVNTB EMI_DE MCU1_

AGB[2] DATA_7 US_0 BUG0 17

(HP3)

SRXD3

SCK3

AudioPort

3-BB

(HP3)

RxD

Tx Serial Clock

Tx Frame Sync

TxD

ATA_DATA8 USBH2 sw_mux_ctl_

_DATA3 srxd3[6:0]

–

IPU_DI TRACE EVNTB EMI_DE MCU1_

AGB[3] DATA_8 US_1

BUG1

AudioPort

3-BB

(HP3)

ATA_DATA9 USBH2 sw_mux_ctl_

IPU_DI TRACE EVNTB EMI_DE

AGB[4] DATA_9 US_2 BUG2

–

_DATA4

sck3[6:0]

SFS3

AudioPort

3-BB

(HP3)

ATA_DATA10 USBH2 sw_mux_ctl_

IPU_DI TRACE EVNTB EMI_DE

–

_DATA5

–

sfs3[6:0]

AGB[5] DATA_

US_3

BUG3

STXD4

SRXD4

SCK4

AudioPort

4-PM_NB

(PP1)

–

sw_mux_ctl_ RXFS3

stxd4[6:0]

IPU_DI

AGB[6]

–

EVNTB EMI_DE MCU1_

US_4 BUG4 19

AudioPort

4-PM_NB

(PP1)

RxD

–

sw_mux_ctl_ RXCLK

srxd4[6:0]

IPU_DI

AGB[7]

EVNTB ARM_C MCU1_

US_5 OREASI

AudioPort

4-PM_NB

(PP1)

Tx Serial Clock

Tx Frame Sync

TxD

sw_mux_ctl_ RXFS5

sck4[6:0]

IPU_DI

AGB[8]

EVNTB ARM_C

US_6 OREASI

–

SFS4

AudioPort

4-PM_NB

(PP1)

sw_mux_ctl_ RXCLK

sfs4[6:0]

IPU_DI

AGB[9]

EVNTB ARM_C

US_7 OREASI

–

STXD5

SRXD5

SCK5

AudioPort

5-PM_W

B (PP2)

sw_mux_ctl_

stxd5[6:0]

–

IPU_DI

AGB[10]

EVNTB ARM_C MCU1_

US_8 OREASI

AudioPort

5-PM_W

B (PP2)

RxD

sw_mux_ctl_

srxd5[6:0]

–

IPU_DI

AGB[11]

EVNTB ARM_C MCU1_

US_9 OREASI

AudioPort

5-PM_W

B (PP2)

Tx Serial Clock

Tx Frame Sync

TxD

sw_mux_ctl_

sck5[6:0]

IPU_DI

AGB[12]

EVNTB ARM_C

US_10 OREASI

–

SFS5

AudioPort

5-PM_W

B (PP2)

sw_mux_ctl_

sfs5[6:0]

IPU_DI

AGB[13]

EVNTB ARM_C

US_11 OREASI

–

STXD6

SRXD6

AudioPort

6-BT

(PP3)

ATA_DATA11 USBH2 sw_mux_ctl_

_DATA6 stxd6[6:0]

IPU_DI TRACE EVNTB ARM_C MCU1_

AGB[14] DATA_ US_12 OREASI 23

11 D7

AudioPort

6-BT

RxD

ATA_DATA12 USBH2 sw_mux_ctl_

_DATA7 srxd6[6:0]

IPU_DI TRACE EVNTB M3IF_C MCU1_

AGB[15] DATA_ US_13 HOSEN 24

(PP3)

_MAST

ER_0

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Pin Name Group

Description

Mode Mode Mode Mode Mode Mode GPIO

SCK6

AudioPort

6-BT

Tx Serial Clock

ATA_DATA13

–

sw_mux_ctl_

sck6[6:0]

–

IPU_DI TRACE EVNTB M3IF_C MCU1_

AGB[16] DATA_ US_14 HOSEN 25

(PP3)

_MAST

ER_1

SFS6

AudioPort

6-BT

(PP3)

Tx Frame Sync

USBH1_SUS

PEND

–

sw_mux_ctl_

sfs6[6:0]

–

IPU_DI TRACE EVNTB M3IF_C MCU1_

AGB[17] DATA_ US_15 HOSEN

–

_MAST

ER_2

CSPI1_MOSI CSPI1_

Master Out/Slave In.

Slave In/Master Out.

ATA_DATA0 ATA_IN sw_mux_ctl_ USBH1 RXD3 IPU_DI TRACE

–

TRQ cspi1_mosi[6 _RXDM

:0]

AGB[18] DATA_

CSPI1_MISO CSPI1_

ATA_DATA1 ATA_BU sw_mux_ctl_ USBH1 TXD3

FFER_E cspi1_miso[6 _RXDP

IPU_DI TRACE

AGB[19] DATA_

:0]

CSPI1_SS0

CSPI1_SS1

CSPI1_SS2

CSPI1_ Slave Select (Selectable ATA_DATA2 ATA_DM sw_mux_ctl_ USBH1 CSPI3_ IPU_DI TRACE

polarity).

ARQ

cspi1_ss0[6: _TXDM

SS2

AGB[20] DATA_

CSPI1_ Slave Select (Selectable ATA_DATA3 ATA_DA sw_mux_ctl_ USBH1 CSPI2_ IPU_DI TRACE

polarity).

cspi1_ss1[6: _TXDP

SS3

AGB[21] DATA_

CSPI1_ Slave Select (Selectable ATA_DATA4 ATA_DA sw_mux_ctl_ USBH1 CSPI3_ IPU_DI TRACE

polarity).

cspi1_ss2[6: _RCV

SS3

AGB[22] DATA_

CSPI1_SCLK CSPI1_

Serial Clock.

ATA_DATA5 ATA_DA sw_mux_ctl_ USBH1

RTS3

IPU_DI

AGB[23]

–

cspi1_sclk[6: _OEB

CSPI1_SPI_

RDY

CSPI1_

Serial Data Ready.

Master Out/Slave In.

Slave In/Master Out.

ATA_DATA6

–

sw_mux_ctl_ USBH1 CTS3

cspi1_spi_rd

y[6:0]

IPU_DI

AGB[24]

_FS

CSPI2_MOSI CSPI2_

–

sw_mux_ctl_ I2C2_S

cspi2_mosi

[6:0]

–

CSPI2_MISO CSPI2_

–

sw_mux_ctl_ I2C2_S

cspi2_miso

[6:0]

CSPI2_SS0

CSPI2_SS1

CSPI2_SS2

CSPI2_ Slave Select (Selectable

PM polarity).

–

sw_mux_ctl_ CSPI3_

cspi2_ss0

[6:0]

SS0

CSPI2_ Slave Select (Selectable

PM polarity).

–

sw_mux_ctl_ CSPI3_ CSPI1_

cspi2_ss1

[6:0]

SS1

SS3

CSPI2_ Slave Select (Selectable

–

sw_mux_ctl_ I2C3_S IPU_FL

cspi2_ss2

[6:0]

polarity).

ASH_S

TROBE

CSPI2_SCLK CSPI2_

Serial Clock.

sw_mux_ctl_ I2C3_S

cspi2_sclk

–

[6:0]

CSPI2_SPI_

RDY

CSPI2_

–

sw_mux_ctl_

cspi2_spi_

rdy[6:0]

–

RXD1

TXD1

UART1_

GPS

Rx Data. (+CE Bus 12)

TRSTB

TCK

sw_mux_ctl_ USBOT PP4_TX

rxd1[6:0]

DSR_

DCE1

MCU2_

G_DATA

DAT/

STDA

UART1_ Tx Data. + (CE Bus 10)

GPS

sw_mux_ctl_ USBOT PP4_TX

txd1[6:0]

RI_DCE

MCU2_

G_DATA CLK/

SCK

RTS1

CTS1

UART1_ Request to send. + (CE

–

sw_mux_ctl_

rts1[6:0]

–

PP4_TX

FS/FS

–

DCD_D

CE1

–

MCU2_

GPS

Bus 9)

UART1_ Clear to send. + CE Bus 8)

GPS

sw_mux_ctl_

cts1[6:0]

–

MCU2_

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Pin Name Group

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Description

Mode Mode Mode Mode Mode Mode GPIO

DTR_DCE1

DSR_DCE1

RI_DCE1

UART1_

GPS

CE Bus 11

TMS

TDO

TDI

–

sw_mux_ctl_

dtr_dce1[6:0]

–

PP4_RX

DAT/SR

–

MCU2_

Full

UART IF

Full UART IF + CE Bus 4

Full UART IF + CE Bus 5

USBOT sw_mux_ctl_ CSPI1_ TXD1 DSR_D

G_DATA dsr_dce1[6:0 SCLK CE2

–

MCU2_

]

Full

UART IF

USBOT sw_mux_ctl_ CSPI1_ RXD1 RI_DCE

G_DATA ri_dce1[6:0] SPI_RD

MCU2_

DCD_DCE1

Full

UART IF

Full UART IF + CE Bus 6 RESET_IN USBOT sw_mux_ctl_ CSPI1_ RTS1 DCD_D USB_P

MCU2_

G_DATA dcd_dce1

SS3

–

CE2

[6:0]

DTR_DTE1

DSR_DTE1

RI_DTE1

Full

UART IF

–

CSPI1_MOSI

CSPI1_MISO

CSPI1_SS0

CSPI1_SS1

–

sw_mux_ctl_

dtr_dte1[6:0]

–

DTR_D

TE2

–

EVNTB

US_16

–

MCU2_

Full

UART IF

–

sw_mux_ctl_ DSR_D

dsr_dte1[6:0] TE2

–

EVNTB

US_17

MCU2_

Full

UART IF

sw_mux_ctl_ RI_DTE I2C2_S IPU_DI

ri_dte1[6:0] CL AGB[25]

–

EVNTB

US_18

MCU2_

DCD_DTE1

Full

UART IF

sw_mux_ctl_ DCD_ I2C2_S IPU_DI

dcd_dte1

[6:0]

–

EVNTB

US_19

MCU2_

DTE2

AGB[26]

DTR_DCE2

RXD2

Full

UART IF

–

CSPI1_SS2

–

sw_mux_ctl_

dtr_dce2[6:0]

–

IPU_DI

AGB[27]

–

MCU2_

UART2_

Tx Data.

ipp_ind_firi_

rxd

sw_mux_ctl_

rxd2[6:0]

–

IPU_DI

AGB[28]

MCU1_

TXD2

UART2_

Tx Data.

ipp_do_firi_

txd

sw_mux_ctl_

txd2[6:0]

–

IPU_DI

AGB[29]

MCU1_

RTS2

UART2_

Request to send.

Clear to send.

One Wire Data

keypad row sense 0

ipp_ind_firi_

rxd

sw_mux_ctl_

rts2[6:0]

–

IPU_DI

AGB[30]

–

CTS2

UART2_

ipp_do_firi_

txd

sw_mux_ctl_

cts2[6:0]

–

IPU_DI

AGB[31]

–

BATT_LINE

KEY_ROW0

1-Wire

–

sw_mux_ctl_

batt_line[6:0]

–

MCU2_

Keypad

–

sw_mux_ctl_

key_row0

[6:0]

–

KEY_ROW1

KEY_ROW2

KEY_ROW3

KEY_ROW4

KEY_ROW5

KEY_ROW6

KEY_ROW7

KEY_COL0

Keypad

keypad row sense 1

keypad row sense 2

keypad row sense 3

keypad row sense 4

keypad row sense 5

keypad row sense 6

keypad row sense 7

keypad column driver 0

–

sw_mux_ctl_

key_row1

[6:0]

–

sw_mux_ctl_

key_row2

[6:0]

–

sw_mux_ctl_

key_row3

[6:0]

TRACE

CTL

–

sw_mux_ctl_

key_row4

[6:0]

TRACE

CLK

MCU2_

–

sw_mux_ctl_

key_row5

[6:0]

TRACE

DATA_0

MCU2_

ATA_INTRQ

sw_mux_ctl_

key_row6

[6:0]

TRACE

DATA_1

MCU2_

ATA_

BUFFER_EN

sw_mux_ctl_

key_row7

[6:0]

TRACE

DATA_2

MCU2_

–

sw_mux_ctl_

key_col0

[6:0]

–

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Pin Name Group

Description

Mode Mode Mode Mode Mode Mode GPIO

KEY_COL1

KEY_COL2

KEY_COL3

KEY_COL4

KEY_COL5

KEY_COL6

KEY_COL7

Keypad

keypad column driver 1

–

sw_mux_ctl_

key_col1

[6:0]

–

keypad column driver 2

keypad column driver 3

sw_mux_ctl_

key_col2

[6:0]

–

sw_mux_ctl_

key_col3

[6:0]

TRACE

DATA_3

keypad column driver 4 ATA_DMARQ

sw_mux_ctl_

key_col4

[6:0]

TRACE

DATA_4

MCU2_

keypad column driver 5

keypad column driver 6

keypad column driver 7

ARM Debug Test Clock

ATA_DA0

ATA_DA1

ATA_DA2

sw_mux_ctl_

key_col5

[6:0]

TRACE

DATA_5

MCU2_

sw_mux_ctl_

key_col6

[6:0]

TRACE

DATA_6

MCU2_

sw_mux_ctl_

key_col7

[6:0]

TRACE

DATA_7

MCU2_

RTCK

TCK

JTAG

–

JTAG TAP clock No MUX

allowed

sw_mux_ctl_

tck[6:0]

TMS

TDI

JTAG

JTAG TAP mode select No

MUX allowed

–

sw_mux_ctl_

tms[6:0]

–

JTAG Tap Data In No MUX

allowed

sw_mux_ctl_

tdi[6:0]

TDO

JTAG

JTAG TAP data out

–

TRSTB

JTAG TAP reset No MUX

allowed

sw_mux_ctl_

trstb[6:0]

JTAG

JTAG Debug Enable No

MUX allowed

–

sw_mux_ctl_

de_b[6:0]

–

SJC_MOD

USB_PWR

JTAG

JTAG Mode

–

USB

GEN

USB Generic

sw_mux_ctl_

usb_pwr[6:0]

MAX1_ MCU1_

HMAST

ER_0

USB_OC

USB

GEN

USB Generic

–

sw_mux_ctl_

usb_oc[6:0]

–

MAX1_ MCU1_

HMAST

ER_1

USB_BYP

USB

GEN

sw_mux_ctl_

usb_byp[6:0]

MAX1_ MCU1_

HMAST

ER_2

USBOTG_

CLK

USBOTG USB OTG FS/ULPI Port

sw_mux_ctl_

usbotg_clk

[6:0]

MAX1_

HMAST

ER_3

–

USBOTG_DIR USBOTG USB OTG FS/ULPI Port

sw_mux_ctl_

usbotg_dir

[6:0]

MAX0_

HMAST

ER_0

–

USBOTG_

STP

USBOTG USB OTG FS/ULPI Port

sw_mux_ctl_

usbotg_stp

[6:0]

MAX0_

HMAST

ER_1

USBOTG_

NXT

sw_mux_ctl_

usbotg_nxt

[6:0]

MAX0_

HMAST

ER_2

USBOTG_

DATA0

USBOTG USB OTG FS/ULPI Port +

CE Bus

sw_mux_ctl_

usbotg_

data0[6:0]

UART4_

CTS

MAX0_

HMAST

ER_3

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Pin Name Group

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Description

Mode Mode Mode Mode Mode Mode GPIO

USBOTG_

DATA1

USBOTG USB OTG FS/ULPI Port

–

sw_mux_ctl_

usbotg_data

1[6:0]

–

USBOTG_

DATA2

USBOTG USB OTG FS/ULPI Port +

CE Bus

–

sw_mux_ctl_

usbotg_data

2[6:0]

–

USBOTG_

DATA3

USBOTG USB OTG FS/ULPI Port

–

sw_mux_ctl_

usbotg_data

3[6:0]

UART4_

RXD

USBOTG_

DATA4

–

sw_mux_ctl_

usbotg_data

4[6:0]

UART4_

TXD

USBOTG_

DATA5

–

sw_mux_ctl_

usbotg_data

5[6:0]

UART4_

RTS

USBOTG_

DATA6

–

sw_mux_ctl_

usbotg_data

6[6:0]

–

USBOTG_

DATA7

–

sw_mux_ctl_

usbotg_data

7[6:0]

USBH2_CLK

USBH2_DIR

USBH2_STP

USBH2

USB Host2 FS/ULPI

ATA_INTRQ

sw_mux_ctl_ UART5_

usbh2_

clk[6:0]

TRACE

DATA_2

RTS

USB Host2 FS/ULPI

ATA_BUFFE

R_EN

sw_mux_ctl_ UART5_

usbh2_

dir[6:0]

TRACE

DATA_2

RXD

USB Host2 FS/ULPI

ATA_DMARQ

sw_mux_ctl_ UART5_

usbh2_

stp[6:0]

TRACE

DATA_2

TXD

USBH2_NXT USBH2

USB Host2 FS/ULPI

ATA_DA0

sw_mux_ctl_ UART5_

usbh2_

nxt[6:0]

TRACE

DATA_2

CTS

USBH2_

DATA0

USBH2

USB Host2 FS/ULPI

ATA_DA1

sw_mux_ctl_

usbh2_data0

[6:0]

–

TRACE

CTL

USBH2_

DATA1

USB Host2 FS/ULPI

ATA_DA2

sw_mux_ctl_

usbh2_data1

[6:0]

–

TRACE

CLK

LD0

LD1

LD2

LD3

LD4

LD5

LD6

IPU

(LCD)

–

sw_mux_ctl_

ld0[6:0]

–

SDMA_

DEBUG

_PC_0

IPU

(LCD)

sw_mux_ctl_

ld1[6:0]

SDMA_

DEBUG

_PC_1

IPU

(LCD)

sw_mux_ctl_

ld2[6:0]

SDMA_

DEBUG

_PC_2

IPU

(LCD)

sw_mux_ctl_

ld3[6:0]

SDMA_

DEBUG

_PC_3

IPU

(LCD)

sw_mux_ctl_

ld4[6:0]

SDMA_

DEBUG

_PC_4

IPU

(LCD)

sw_mux_ctl_

ld5[6:0]

SDMA_

DEBUG

_PC_5

IPU

sw_mux_ctl_

ld6[6:0]

SDMA_

DEBUG

_PC_6

(LCD)

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Pin Name Group

Description

Mode Mode Mode Mode Mode Mode GPIO

LD7

LD8

IPU

(LCD)

–

sw_mux_ctl_

ld7[6:0]

–

SDMA_

DEBUG

_PC_7

–

IPU

(LCD)

–

sw_mux_ctl_

ld8[6:0]

–

SDMA_

DEBUG

_PC_8

LD9

IPU

(LCD)

sw_mux_ctl_

ld9[6:0]

SDMA_

DEBUG

_PC_9

LD10

LD11

LD12

LD13

LD14

IPU

(LCD)

sw_mux_ctl_

ld10[6:0]

SDMA_

DEBUG

_PC_10

IPU

(LCD)

sw_mux_ctl_

ld11[6:0]

SDMA_

DEBUG

_PC_11

IPU

(LCD)

sw_mux_ctl_

ld12[6:0]

SDMA_

DEBUG

_PC_12

IPU

(LCD)

sw_mux_ctl_

ld13[6:0]

SDMA_

DEBUG

_PC_13

IPU

(LCD)

sw_mux_ctl_

ld14[6:0]

SDMA_

DEBUG

_EVEN

T_CHA

NNEL_0

LD15

LD16

IPU

(LCD)

–

sw_mux_ctl_

ld15[6:0]

–

SDMA_

DEBUG

_EVEN

T_CHA

NNEL_1

–

IPU

(LCD)

sw_mux_ctl_

ld16[6:0]

SDMA_

DEBUG

_EVEN

T_CHA

NNEL_2

LD17

IPU

(LCD)

–

sw_mux_ctl_

ld17[6:0]

SDMA_

DEBUG

_EVEN

T_CHA

NNEL_3

VSYNC0

HSYNC

FPSHIFT

DRDY0

IPU

(LCD)

frame sync

line sync

shift

sw_mux_ctl_

vsync0[6:0]

SDMA_

DEBUG

_EVEN

T_CHA

NNEL_4

IPU

(LCD)

sw_mux_ctl_

hsync[6:0]

SDMA_

DEBUG

_EVEN

T_CHA

NNEL_5

IPU

(LCD)

sw_mux_ctl_ DISPB_

fpshift[6:0]

SDMA_

DEBUG

_CORE

_STATU

S_0

BCLK

IPU

(LCD)

DRDY/VLD

sw_mux_ctl_

drdy0[6:0]

–

SDMA_

DEBUG

_CORE

_STATU

S_1

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Pin Name Group

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Description

Mode Mode Mode Mode Mode Mode GPIO

SD_D_I

SD_D_IO

SD_D_CLK

IPU

(LCD)

Data in for Serial Display

–

sw_mux_ctl_

sd_d_i[6:0]

–

SD_D_I

–

SDMA_ MCU3_

DEBUG

_CORE

_STATU

S_2

IPU

(LCD)

Data in/out for Serial

Display

sw_mux_ctl_

sd_d_io[6:0]

–

SDMA_ MCU3_

DEBUG

_CORE

_STATU

S_3

IPU

(LCD)

Serial Display clock

sw_mux_ctl_

sd_d_clk[6:0

]

–

MCU3_

LCS0

LCS1

IPU

(LCD)

Asynch. Port chip select

–

sw_mux_ctl_ DISPB_

–

MCU3_

lcs0[6:0]

BCLK

IPU

(LCD)

sw_mux_ctl_

lcs1[6:0]

–

MCU3_

SER_RS

PAR_RS

WRITE

IPU

(LCD)

Asynch. Serial Port

data/comm

sw_mux_ctl_

ser_rs[6:0]

–

MCU3_

IPU

(LCD)

Asynch.Parallel Port

data/comm

sw_mux_ctl_

par_rs[6:0]

–

IPU

(LCD)

Asynch. Port write

sw_mux_ctl_

write[6:0]

READ

IPU

(LCD)

Asynch. Port read

sw_mux_ctl_

read[6:0]

VSYNC3

CONTRAST

D3_REV

D3_CLS

D3_SPL

SD1_CMD

IPU

(LCD)

vsync

sw_mux_ctl_

vsync3[6:0]

IPU

(LCD)

–

sw_mux_ctl_

contrast[6:0]

IPU

(LCD)

sw_mux_ctl_

d3_rev[6:0]

IPU

(LCD)

sw_mux_ctl_

d3_cls[6:0]

IPU

(LCD)

sw_mux_ctl_

d3_spl[6:0]

SD/MMC

sw_mux_ctl_ MSHC1

TRACE

DATA_0

MCU2_

sd1_

_SCLK

cmd[6:0]

SD1_CLK

SD/MMC

–

sw_mux_ctl_ MSHC1

sd1_clk[6:0] _BS

–

TRACE

DATA_1

–

MCU2_

SD1_DATA0 SD/MMC

sw_mux_ctl_ MSHC1

TRACE

DATA_2

MCU2_

sd1_

_SDIO_

data0[6:0]

DATA0

SD1_DATA1 SD/MMC

–

sw_mux_ctl_ MSHC1

–

TRACE

DATA_3

–

MCU2_

sd1_

_DATA1

data1[6:0]

SD1_DATA2 SD/MMC

sw_mux_ctl_ MSHC1

TRACE

DATA_4

MCU2_

sd1_

_DATA2

data2[6:0]

SD1_DATA3 SD/MMC

sw_mux_ctl_ MSHC1 CTI_TRI

TRACE obs_int_

DATA_5

MCU2_

sd1_

_DATA3 G_IN_1

data3[6:0]

ATA_CS0

ATA_CS1

ATA_DIOR

ATA

–

sw_mux_ctl_ UART4_ CSI_D0 SD_D_ TRACE

ata_cs0[6:0] RXD CLK DATA_6

–

MCU3_

sw_mux_ctl_ UART4_ CSI_D1 LCS1 TRACE obs_int_

ata_cs1[6:0] RTS DATA_7

sw_mux_ctl_ UART4_ CSI_D2 SER_R TRACE obs_int_

ata_dior[6:0] TXD CTL

MCU3_

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Pin Name Group

Description

Mode Mode Mode Mode Mode Mode GPIO

ATA_DIOW

ATA_DMACK

ATA_RESET

ATA

–

sw_mux_ctl_ UART4_ CSI_D3

–

TRACE obs_int_

–

MCU3_

ata_

CTS

CLK

diow[6:0]

–

sw_mux_ctl_ SD_D_

–

obs_int_

–

MCU3_

ata_

dmack[6:0]

sw_mux_ctl_ SD_D

ata_

–

MCU3_

reset_b[6:0]

CE_

CONTROL

–

CLKSS

Clock &

Reset&

Clock Source Select at

reset

CSPI3_MOSI CSPI3_

Master Out/Slave In.

Slave In/Master Out.

Serial Clock.

–

sw_mux_ctl_ RXD3

cspi3_

mosi[6:0]

–

CSPI3_MISO CSPI3_

sw_mux_ctl_ TXD3

cspi3_

miso[6:0]

CSPI3_SCLK CSPI3_

sw_mux_ctl_ RTS3

cspi3_

sclk[6:0]

CSPI3_SPI_

RDY

CSPI3_

Serial Data Ready.

sw_mux_ctl_ CTS3

cspi3_spi_

rdy[6:0]

TTM_PAD

TTM_

PAD

Special TTM pad

–

IOQVDD

MVCC

QVDD

PLL's

Noisy

–

MGND

UVCC

UGND

FVCC

FGND

SVCC

SGND

NVCC1

NVCC2

NVCC3

NVCC4

NVCC5

NVCC6

NVCC7

NVCC8

NVCC9

NVCC10

NVCC21

NVCC22

NGND1

NGND2

NGND3

NGND4

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Pin Name Group

Table 4. Functional Multiplexing (continued)

Mode

SW_

MUX_

Alt

Hardware

Mode 1

Description

Mode Mode Mode Mode Mode Mode GPIO

NGND5

NGND6

NGND7

NGND8

NGND9

NGND10

NGND21

NGND22

QVCC

Noisy

Quiet

–

QVCC1

The special TTM pad (at U20) is used by Freescale internally and must be connected to GND on the customer’s production board.

3.1.2

Pad Settings

Table 5 shows the legend for the pin settings. Table 6 defines all the settings of each pad. If a pad’s settings

is configurable by software, then the bit controlling this setting is described in that table.

Table 5. Pad Settings Legend

Term

Description

Slew Rate

Loopback

Defines the speed of the pad (fast or slow).

Enables the input buffer when the output buffer is enabled.

Drive Strength Control Defines the driving strength of the pad.

Pull Value

Pull/Keep Select

Pull/Keep Enable

Open Drain

Resistor value on the pad.

The capability selected—pull or keeper. The signal has no meaning if pull/keeper enable is not enabled.

Pull or keeper enabled or not.

The signal that enables the open drain capability of the pad.

The signal that enables the Schmidt trigger capability of the pad.

The supply that the pad is connected to.

Schmitt Trigger

Supply Group

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Table 6. Pad Settings

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

Pad

Slew Rate

value reset

Loopback

Pull Value

Schmitt Trigger

value

reset

GND

value

GND

reset

value

GND

reset value reset

GND pu100 pu100

value

reset

value

reset

value

reset

GND

value

GND

reset

CAPTURE regular sw_pad_ct slow

GND

pull

pull sw_pad_ct VCC

GND

GND NVCC1

l_capture[

COMPARE regular sw_pad_ct slow

GND

GND pu100 pu100

pull

VCC

GND

l_compare

[0]

WATCHDOG_ regular

RST

slow

GND

GND pu100 pu100

pull

VCC

GND

PWMO

regular sw_pad_ct slow

l_pwmo[0]

pull sw_pad_ct GND

l_pwmo[8]

GND sw_pad_ct VCC NVCC3

l_pwmo[4]

GPIO1_0

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1

l_gpio1_0

[0]

l_gpio1_0

[2]

l_gpio1_0

[1]

l_gpio1_0

[7]

l_gpio1_0

[8]

l_gpio1_0

[3]

l_gpio1_0

[4]

GPIO1_1

GPIO1_2

GPIO1_3

GPIO1_4

GPIO1_5

GPIO1_6

GPIO3_0

GPIO3_1

regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1

l_gpio1_1

[0]

l_gpio1_1

[2]

l_gpio1_1

[1]

l_gpio1_1

[7]

l_gpio1_1

[8]

l_gpio1_1

[3]

l_gpio1_1

[4]

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1

l_gpio1_2

[0]

l_gpio1_2

[2]

l_gpio1_2

[1]

l_gpio1_2

[7]

l_gpio1_2

[8]

l_gpio1_2

[3]

l_gpio1_2

[4]

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1

l_gpio1_3

[0]

l_gpio1_3

[2]

l_gpio1_3

[1]

l_gpio1_3

[7]

l_gpio1_3

[8]

l_gpio1_3

[3]

l_gpio1_3

[4]

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1

l_gpio1_4

[0]

l_gpio1_4

[2]

l_gpio1_4

[1]

l_gpio1_4

[7]

l_gpio1_4

[8]

l_gpio1_4

[3]

l_gpio1_4

[4]

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1

l_gpio1_5

[0]

l_gpio1_5

[2]

l_gpio1_5

[1]

l_gpio1_5

[7]

l_gpio1_5

[8]

l_gpio1_5

[3]

l_gpio1_5

[4]

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC1

l_gpio1_6

[0]

l_gpio1_6

[2]

l_gpio1_6

[1]

l_gpio1_6

[7]

l_gpio1_6

[8]

l_gpio1_6

[3]

l_gpio1_6

[4]

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC4

l_gpio3_0

[0]

[2]

[1]

[7]

[8]

[3]

[4]

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100 sw_pad_ct pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND NVCC4

l_gpio3_1

[0]

[2]

[1]

[7]

[8]

[3]

[4]

SCLK0

SRST0

SVEN0

STX0

regular sw_pad_ct slow sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC

l_sclk0[8]

GND

GND NVCC9

l_sclk0[0]

l_sclk0[9]

l_sclk0[2]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_srst0[2] l_srst0[1]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_sven0[2] l_sven0[1]

l_sclk0[1]

regular sw_pad_ct slow

l_srst0[0]

GND

pull sw_pad_ct VCC

l_srst0[8]

regular sw_pad_ct slow

l_sven0[0]

GND

pull sw_pad_ct VCC

l_sven0[8]

regular sw_pad_ct slow sw_pad_ct VCC sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_stx0[8]

l_stx0[0]

l_stx0[9]

l_stx0[2]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_srx0[2] l_srx0[1]

l_stx0[1]

SRX0

regular sw_pad_ct slow

l_srx0[0]

GND

pull sw_pad_ct VCC

l_srx0[8]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

GND

SIMPD0

regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC

GND

GND NVCC9

l_simpd0

[0]

l_simpd0

[2]

l_simpd0

[1]

l_simpd0

[8]

CKIH

regular

slow

GND

GND pu100 pu100

pull

GND

GND sw_pad_ct VCC NVCC1

l_ckih[4]

RESET_IN regular

slow

fast

slow

fast

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND pu100 pu100

VCC pu100 pu100

GND pu100 pu100

GND pd100 pd100

GND pu100 pu100

VCC pu100 pu100

pull

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC NVCC1

GND NVCC1

VCC NVCC1

GND NVCC1

GND NVCC22

POR

regular

ddr

CLKO

BOOT_MODE0 regular

BOOT_MODE1 regular

BOOT_MODE2 regular

BOOT_MODE3 regular

BOOT_MODE4 regular

slow

fast

slow

fast

CKIL

regular

POWER_FAIL regular

VSTBY

DVFS0

DVFS1

VPG0

VPG1

regular

GND sw_pad_ct VCC

l_a0[2]

regular

fast

GND

GND sw_pad_ct VCC

l_a1[2]

VCC

VCC pu100 pu100

pull

GND

GND NVCC22

GND NVCC2

GND NVCC22

GND sw_pad_ct VCC

l_a2[2]

GND sw_pad_ct VCC

l_a3[2]

GND sw_pad_ct VCC

l_a4[2]

GND sw_pad_ct VCC

l_a5[2]

GND sw_pad_ct VCC

l_a6[2]

GND sw_pad_ct VCC

l_a7[2]

GND sw_pad_ct VCC

l_a8[2]

GND sw_pad_ct VCC

l_a9[2]

A10

MA10

A11

GND sw_pad_ct VCC

l_a10[2]

GND sw_pad_ct VCC

l_ma10[2]

GND sw_pad_ct VCC

l_a11[2]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

Pad

Slew Rate

fast

Loopback

Pull Value

Schmitt Trigger

regular

fast

GND

GND sw_pad_ct VCC

l_a12[2]

VCC

VCC pu100 pu100

pull

GND

GND NVCC22

GND NVCC21

GND NVCC22

fast

GND sw_pad_ct VCC

l_a13[2]

pull

GND

GND sw_pad_ct VCC

l_a14[2]

GND sw_pad_ct VCC

l_a15[2]

GND sw_pad_ct VCC

l_a16[2]

GND sw_pad_ct VCC

l_a17[2]

GND sw_pad_ct VCC

l_a18[2]

GND sw_pad_ct VCC

l_a19[2]

GND sw_pad_ct VCC

l_a20[2]

GND sw_pad_ct VCC

l_a21[2]

GND sw_pad_ct VCC

l_a22[2]

GND sw_pad_ct VCC

l_a23[2]

GND sw_pad_ct VCC

l_a24[2]

GND sw_pad_ct VCC

l_a25[2]

SDBA1

SDBA0

SD0

regular

ddr

fast

GND

VCC

GND pu100 pu100

VCC pu100 pu100

pull

GND

VCC

GND

VCC

GND

GND NVCC22

GND NVCC21

GND sw_pad_ct VCC

l_sd0[2]

keep

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD8

ddr

fast

GND

GND sw_pad_ct VCC

l_sd1[2]

VCC

VCC pu100 pu100

keep

VCC

GND

GND NVCC21

GND sw_pad_ct VCC

l_sd2[2]

GND sw_pad_ct VCC

l_sd3[2]

GND sw_pad_ct VCC

l_sd4[2]

GND sw_pad_ct VCC

l_sd5[2]

GND sw_pad_ct VCC

l_sd6[2]

GND sw_pad_ct VCC

l_sd7[2]

GND sw_pad_ct VCC

l_sd8[2]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

SD9

Pad

ddr

Slew Rate

fast

Loopback

Pull Value

Schmitt Trigger

fast

GND

GND sw_pad_ct VCC

l_sd9[2]

VCC

VCC pu100 pu100

keep

VCC

GND

GND NVCC21

GND NVCC22

GND NVCC2

SD10

SD11

SD12

SD13

SD14

SD15

SD16

SD17

SD18

SD19

SD20

SD21

SD22

SD23

SD24

SD25

SD26

SD27

SD28

SD29

SD30

SD31

DQM0

fast

GND sw_pad_ct VCC

l_sd10[2]

keep

VCC

GND

GND sw_pad_ct VCC

l_sd11[2]

GND sw_pad_ct VCC

l_sd12[2]

GND sw_pad_ct VCC

l_sd13[2]

GND sw_pad_ct VCC

l_sd14[2]

GND sw_pad_ct VCC

l_sd15[2]

GND sw_pad_ct VCC

l_sd16[2]

GND sw_pad_ct VCC

l_sd17[2]

GND sw_pad_ct VCC

l_sd18[2]

GND sw_pad_ct VCC

l_sd19[2]

GND sw_pad_ct VCC

l_sd20[2]

GND sw_pad_ct VCC

l_sd21[2]

GND sw_pad_ct VCC

l_sd22[2]

GND sw_pad_ct VCC

l_sd23[2]

GND sw_pad_ct VCC

l_sd24[2]

GND sw_pad_ct VCC

l_sd25[2]

GND sw_pad_ct VCC

l_sd26[2]

GND sw_pad_ct VCC

l_sd27[2]

GND sw_pad_ct VCC

l_sd28[2]

GND sw_pad_ct VCC

l_sd29[2]

GND sw_pad_ct VCC

l_sd30[2]

GND sw_pad_ct VCC

l_sd31[2]

GND sw_pad_ct VCC

l_dqm0[2]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

DQM1

DQM2

DQM3

EB0

Pad

Slew Rate

fast

Loopback

Pull Value

Schmitt Trigger

ddr

fast

GND

VCC

GND

GND sw_pad_ct VCC

l_dqm1[2]

VCC

VCC pu100 pu100

keep

pull

VCC

GND

VCC

GND

VCC

GND

VCC

GND

GND NVCC2

GND NVCC21

GND NVCC2

ddr

fast

GND sw_pad_ct VCC

l_dqm2[2]

keep

pull

VCC

GND

VCC

GND

VCC

GND

VCC

GND

ddr

GND sw_pad_ct VCC

l_dqm3[2]

regular

GND sw_pad_ct GND

l_eb0[2]

EB1

GND sw_pad_ct GND

l_eb1[2]

pull

GND sw_pad_ct GND

l_oe[2]

pull

CS0

GND sw_pad_ct GND

l_cs0[2]

pull

CS1

GND sw_pad_ct GND

l_cs1[2]

pull

CS2

GND sw_pad_ct VCC

l_cs2[2]

keep

pull

keep

pull

CS3

GND sw_pad_ct VCC

l_cs3[2]

CS4

GND sw_pad_ct GND

l_cs4[2]

CS5

GND sw_pad_ct GND

l_cs5[2]

pull

ECB

LBA

GND sw_pad_ct GND

l_ecb[2]

pull

GND sw_pad_ct GND

l_lba[2]

pull

BCLK

VCC sw_pad_ct GND

l_bclk[2]

pull

GND sw_pad_ct GND

l_rw[2]

pull

RAS

CAS

GND sw_pad_ct VCC

l_ras[2]

keep

GND sw_pad_ct VCC

l_cas[2]

SDWE

SDCKE0

SDCKE1

SDCLK

regular

ddr

fast

GND

VCC

GND

VCC

GND pu100 pu100

VCC pu100 pu100

keep

pull

keep

pull

VCC

GND

VCC

GND

GND NVCC2

VCC sw_pad_ct VCC

l_sdclk[2]

SDCLK

ddr

fast

VCC

VCC sw_pad_ct VCC

l_sdclk[2]

VCC

VCC pu100 pu100

pull

GND

GND NVCC2

SDQS0

SDQS1

SDQS2

SDQS3

ddr

fast

GND

GND pd100 pd100

pull

VCC

GND

GND NVCC21

GND NVCC22

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

NFWE

regular sw_pad_ct fast

GND

GND sw_pad_ct GND sw_pad_ct VCC pd100 pd100

pull

pull sw_pad_ct VCC

GND

GND NVCC10

l_nfwe_b

[0]

l_nfwe_b

[2]

l_nfwe_b

[1]

l_nfwe_b

[8]

NFRE

NFALE

NFCLE

NFWP

regular sw_pad_ct fast

l_nfre_b[0]

GND

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100

l_nfre_b[2] l_nfre_b[1]

pull

pull sw_pad_ct VCC

l_nfre_b[8]

GND

GND NVCC10

regular sw_pad_ct fast

l_nfale[0]

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100

l_nfale[2] l_nfale[1]

pull sw_pad_ct VCC

l_nfale[8]

regular sw_pad_ct fast

l_nfcle[0]

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100

l_nfcle[2] l_nfcle[1]

pull sw_pad_ct VCC

l_nfcle[8]

regular sw_pad_ct fast

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100

pull sw_pad_ct VCC

l_nfwp_b

[0]

l_nfwp_b

[2]

l_nfwp_b

[1]

l_nfwp_b

[8]

NFCE

regular sw_pad_ct fast

GND

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100

pull

pull sw_pad_ct VCC

GND

GND NVCC10

l_nfce_b

[0]

l_nfce_b

[2]

l_nfce_b

[1]

l_nfce_b

[8]

NFRB

D15

D14

D13

D12

D11

D10

regular sw_pad_ct fast

l_nfrb[0]

GND

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100

pull

pull sw_pad_ct VCC

l_nfrb[8]

GND

GND NVCC10

l_nfrb[2]

l_nfrb[1]

regular

fast

GND sw_pad_ct VCC

l_d15[2]

VCC

VCC pu100 pu100

keep

VCC

GND sw_pad_ct VCC

l_d14[2]

VCC

GND sw_pad_ct VCC

l_d13[2]

GND sw_pad_ct VCC

l_d12[2]

GND sw_pad_ct VCC

l_d11[2]

GND sw_pad_ct VCC

l_d10[2]

GND sw_pad_ct VCC

l_d9[2]

GND sw_pad_ct VCC

l_d8[2]

GND sw_pad_ct VCC

l_d7[2]

GND sw_pad_ct VCC

l_d6[2]

GND sw_pad_ct VCC

l_d5[2]

GND sw_pad_ct VCC

l_d4[2]

GND sw_pad_ct VCC

l_d3[2]

GND sw_pad_ct VCC

l_d2[2]

GND sw_pad_ct VCC

l_d1[2]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

Pad

Slew Rate

Loopback

GND

Pull Value

Schmitt Trigger

GND

regular

fast

GND sw_pad_ct VCC

l_d0[2]

VCC

VCC pu100 pu100

keep

VCC

GND

GND NVCC10

PC_CD1

slow

slow sw_pad_ct GND

GND

pull

pull sw_pad_ct VCC

l_pc_cd1_

GND

GND sw_pad_ct GND NVCC3

l_pc_cd1_

b[9]

l_pc_cd1_

b[4]

b[8]

PC_CD2

regular

slow

GND

VCC

VCC pu100 pu100

VCC pd100 pd100

VCC pu100 pu100

pull sw_pad_ct VCC

l_pc_cd2_

GND

GND NVCC3

b[8]

PC_WAIT

slow sw_pad_ct GND

l_pc_wait_

pull sw_pad_ct VCC

l_pc_wait_

b[9]

b[8]

PC_READY regular

PC_PWRON regular

slow sw_pad_ct GND

pull sw_pad_ct VCC

l_pc_read

y[9]

l_pc_read

y[8]

slow sw_pad_ct GND

pull sw_pad_ct VCC

l_pc_pwro

n[9]

n[8]

PC_VS1

PC_VS2

regular

slow sw_pad_ct GND

pull sw_pad_ct VCC

l_pc_vs1[9

]

l_pc_vs1[8

]

slow

GND

pull sw_pad_ct VCC

l_pc_vs2[8

]

PC_BVD1 regular

PC_BVD2 regular

pull sw_pad_ct VCC

l_pc_bvd1[

pull sw_pad_ct VCC

l_pc_bvd2[

PC_RST

IOIS16

regular

slow

GND

VCC

VCC pu100 pu100

pull

pull sw_pad_ct VCC

l_pc_rst[8]

GND

GND NVCC3

pull sw_pad_ct VCC

l_iois16[8]

PC_RW

pull sw_pad_ct VCC

l_pc_rw_b[

PC_POE

regular

slow

GND

VCC

GND

VCC pu100 pu100

GND pu100 pu100

pull

GND

VCC

GND

VCC

GND

GND NVCC3

GND NVCC2

GND NVCC4

M_REQUEST regular

M_GRANT regular

CSI_D4

CSI_D5

CSI_D6

CSI_D7

CSI_D8

regular sw_pad_ct fast

l_csi_d4[0]

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_d4[2] l_csi_d4[1] l_csi_d4[7] l_csi_d4[8]

regular sw_pad_ct fast

l_csi_d5[0]

GND

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_d5[2] l_csi_d5[1] l_csi_d5[7] l_csi_d5[8]

GND

GND NVCC4

regular sw_pad_ct fast

l_csi_d6[0]

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_d6[2] l_csi_d6[1] l_csi_d6[7] l_csi_d6[8]

regular sw_pad_ct fast

l_csi_d7[0]

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_d7[2] l_csi_d7[1] l_csi_d7[7] l_csi_d7[8]

regular sw_pad_ct fast

l_csi_d8[0]

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_d8[2] l_csi_d8[1] l_csi_d8[7] l_csi_d8[8]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

CSI_D9

CSI_D10

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

regular sw_pad_ct fast

l_csi_d9[0]

GND

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_d9[2] l_csi_d9[1] l_csi_d9[7] l_csi_d9[8]

GND

GND NVCC4

regular sw_pad_ct fast

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

GND

l_csi_d10

[0]

l_csi_d10

[2]

l_csi_d10

[1]

l_csi_d10[

l_csi_d10

[8]

CSI_D11

CSI_D12

CSI_D13

CSI_D14

CSI_D15

regular sw_pad_ct fast

GND

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

GND

GND NVCC4

l_csi_d11

[0]

l_csi_d11

[2]

l_csi_d11

[1]

l_csi_d11[

l_csi_d11

[8]

regular sw_pad_ct fast

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_d12

[0]

l_csi_d12

[2]

l_csi_d12

[1]

l_csi_d12[

l_csi_d12

[8]

regular sw_pad_ct fast

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_d13

[0]

l_csi_d13

[2]

l_csi_d13

[1]

l_csi_d13[

l_csi_d13

[8]

regular sw_pad_ct fast

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_d14

[0]

l_csi_d14

[2]

l_csi_d14

[1]

l_csi_d14[

l_csi_d14

[8]

regular sw_pad_ct fast

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_d15

[0]

l_csi_d15

[2]

l_csi_d15

[1]

l_csi_d15[

l_csi_d15

[8]

CSI_MCLK regular sw_pad_ct fast

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_mclk

[0]

l_csi_mclk

[2]

l_csi_mclk

[1]

l_csi_mclk

[7]

l_csi_mclk

[8]

CSI_VSYNC regular sw_pad_ct fast

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_vsyn

c[0]

l_csi_vsyn

c[2]

l_csi_vsyn

c[1]

l_csi_vsyn

c[7]

l_csi_vsyn

c[8]

CSI_HSYNC regular sw_pad_ct fast

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

l_csi_hsyn

c[0]

l_csi_hsyn

c[2]

l_csi_hsyn

c[1]

l_csi_hsyn

c[7]

l_csi_hsyn

c[8]

CSI_PIXCLK regular sw_pad_ct fast

GND sw_pad_ct GND sw_pad_ct VCC pu100 pu100 sw_pad_ct keep sw_pad_ct VCC

GND sw_pad_ct VCC NVCC4

l_csi_pixcl

k[0]

l_csi_pixcl

k[2]

l_csi_pixcl

k[1]

l_csi_pixcl

k[7]

l_csi_pixcl

k[8]

l_csi_pixcl

k[4]

I2C_CLK

I2C_DAT

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct VCC NVCC4

l_i2c_clk

[0]

l_i2c_clk

[2]

l_i2c_clk

[1]

l_i2c_clk

[8]

l_i2c_clk

[3]

l_i2c_clk

[4]

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC sw_pad_ct GND

VCC

VCC NVCC4

l_i2c_dat

[0]

l_i2c_dat

[2]

l_i2c_dat

[1]

l_i2c_dat

[8]

l_i2c_dat

[3]

STXD3

SRXD3

SCK3

regular sw_pad_ct slow

l_stxd3[0]

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_stxd3[2] l_stxd3[1]

pull

pull sw_pad_ct VCC

l_stxd3[8]

GND

GND NVCC10

regular sw_pad_ct slow

l_srxd3[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_srxd3[2] l_srxd3[1]

pull sw_pad_ct VCC

l_srxd3[8]

regular sw_pad_ct slow

l_sck3[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_sck3[2] l_sck3[1]

pull sw_pad_ct VCC

l_sck3[8]

GND sw_pad_ct VCC NVCC10

l_sck3[4]

SFS3

regular sw_pad_ct slow

l_sfs3[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_sfs3[2] l_sfs3[1]

pull sw_pad_ct VCC

l_sfs3[8]

GND

GND NVCC10

STXD4

SRXD4

regular sw_pad_ct slow

l_stxd4[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_stxd4[2] l_stxd4[1]

pull sw_pad_ct VCC

l_stxd4[8]

GND

GND NVCC5

regular sw_pad_ct slow

l_srxd4[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_srxd4[2] l_srxd4[1]

pull sw_pad_ct VCC

l_srxd4[8]

GND sw_pad_ct GND NVCC5

l_srxd4[4]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

SCK4

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

regular sw_pad_ct slow

l_sck4[0]

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_sck4[2] l_sck4[1]

pull

pull sw_pad_ct VCC

l_sck4[8]

GND

GND sw_pad_ct VCC NVCC5

l_sck4[4]

SFS4

regular sw_pad_ct slow

l_sfs4[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_sfs4[2] l_sfs4[1]

pull

pull sw_pad_ct VCC

l_sfs4[8]

GND

GND sw_pad_ct GND NVCC5

l_sfs4[4]

STXD5

SRXD5

SCK5

regular sw_pad_ct slow

l_stxd5[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_stxd5[2] l_stxd5[1]

pull sw_pad_ct VCC

l_stxd5[8]

GND

GND NVCC5

regular sw_pad_ct slow

l_srxd5[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_srxd5[2] l_srxd5[1]

pull sw_pad_ct VCC

l_srxd5[8]

GND

GND NVCC5

regular sw_pad_ct slow

l_sck5[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_sck5[2] l_sck5[1]

pull sw_pad_ct VCC

l_sck5[8]

GND sw_pad_ct VCC NVCC5

l_sck5[4]

SFS5

regular sw_pad_ct slow

l_sfs5[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_sfs5[2] l_sfs5[1]

pull sw_pad_ct VCC

l_sfs5[8]

GND

GND NVCC5

GND NVCC10

STXD6

SRXD6

SCK6

regular sw_pad_ct slow

l_stxd6[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_stxd6[2] l_stxd6[1]

pull sw_pad_ct VCC

l_stxd6[8]

regular sw_pad_ct slow

l_srxd6[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_srxd6[2] l_srxd6[1]

pull sw_pad_ct VCC

l_srxd6[8]

regular sw_pad_ct slow

l_sck6[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_sck6[2] l_sck6[1]

pull sw_pad_ct VCC

l_sck6[8]

GND sw_pad_ct VCC NVCC10

l_sck6[4]

SFS6

regular sw_pad_ct slow

l_sfs6[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_sfs6[2] l_sfs6[1]

pull sw_pad_ct VCC

l_sfs6[8]

GND

GND NVCC10

CSPI1_MOSI regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi1_m

GND

GND NVCC10

l_cspi1_m

osi[0]

l_cspi1_m

osi[2]

l_cspi1_m

osi[1]

osi[8]

CSPI1_MISO regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC

l_cspi1_mi

GND

GND NVCC10

l_cspi1_mi

so[0]

l_cspi1_mi

so[2]

l_cspi1_mi

so[1]

so[8]

CSPI1_SS0 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi1_ss

0[0]

l_cspi1_ss

0[2]

l_cspi1_ss

0[1]

0[8]

CSPI1_SS1 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi1_ss

1[0]

l_cspi1_ss

1[2]

l_cspi1_ss

1[1]

1[8]

CSPI1_SS2 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi1_ss

2[0]

l_cspi1_ss

2[2]

l_cspi1_ss

2[1]

2[8]

CSPI1_SCLK regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi1_sc

GND sw_pad_ct VCC NVCC10

l_cspi1_sc

lk[0]

l_cspi1_sc

lk[2]

l_cspi1_sc

lk[1]

l_cspi1_sc

lk[4]

lk[8]

CSPI1_SPI_R regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi1_sp

GND

VCC

GND

GND NVCC10

VCC NVCC5

GND NVCC5

l_cspi1_sp

i_rdy[0]

l_cspi1_sp

i_rdy[2]

l_cspi1_sp

i_rdy[1]

i_rdy[8]

CSPI2_MOSI regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC sw_pad_ct GND

l_cspi2_m

osi[0]

l_cspi2_m

osi[2]

l_cspi2_m

osi[1]

l_cspi2_m

osi[8]

l_cspi2_m

osi[3]

CSPI2_MISO regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC sw_pad_ct GND

l_cspi2_mi

so[0]

l_cspi2_mi

so[2]

l_cspi2_mi

so[1]

l_cspi2_mi

so[8]

l_cspi2_mi

so[3]

CSPI2_SS0 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi2_ss

GND

l_cspi2_ss

0[0]

l_cspi2_ss

0[2]

l_cspi2_ss

0[1]

0[8]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

CSPI2_SS1 regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC

l_cspi2_ss

GND

VCC

GND NVCC5

VCC NVCC5

l_cspi2_ss

1[0]

l_cspi2_ss

1[2]

l_cspi2_ss

1[1]

1[8]

CSPI2_SS2 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC sw_pad_ct GND

l_cspi2_ss

2[0]

l_cspi2_ss

2[2]

l_cspi2_ss

2[1]

l_cspi2_ss

2[8]

l_cspi2_ss

2[3]

CSPI2_SCLK regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC sw_pad_ct GND sw_pad_ct VCC NVCC5

l_cspi2_sc

lk[0]

l_cspi2_sc

lk[2]

l_cspi2_sc

lk[1]

l_cspi2_sc

lk[8]

l_cspi2_sc

lk[3]

l_cspi2_sc

lk[4]

CSPI2_SPI_R regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi2_sp

GND

GND NVCC5

GND NVCC8

l_cspi2_sp

i_rdy[0]

l_cspi2_sp

i_rdy[2]

l_cspi2_sp

i_rdy[1]

i_rdy[8]

RXD1

TXD1

RTS1

CTS1

regular sw_pad_ct slow

l_rxd1[0]

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_rxd1[2] l_rxd1[1]

pull

pull sw_pad_ct VCC

l_rxd1[8]

GND

regular sw_pad_ct slow

l_txd1[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_txd1[2] l_txd1[1]

pull sw_pad_ct VCC

l_txd1[8]

GND sw_pad_ct GND NVCC8

l_txd1[4]

regular sw_pad_ct slow

l_rts1[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_rts1[2] l_rts1[1]

pull sw_pad_ct VCC

l_rts1[8]

GND

GND NVCC8

regular sw_pad_ct slow

l_cts1[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_cts1[2] l_cts1[1]

pull sw_pad_ct VCC

l_cts1[8]

DTR_DCE1 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_dtr_dce1

[0]

l_dtr_dce1

[2]

l_dtr_dce1

[1]

l_dtr_dce1

[8]

DSR_DCE1 regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC

GND

GND sw_pad_ct GND NVCC8

l_dsr_dce

1[0]

l_dsr_dce

1[2]

l_dsr_dce

1[1]

l_dsr_dce

1[8]

l_dsr_dce

1[4]

RI_DCE1

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

GND

VCC

GND

VCC

GND

GND NVCC8

VCC NVCC8

GND NVCC8

VCC NVCC8

GND NVCC8

l_ri_dce1

[0]

l_ri_dce1

[2]

l_ri_dce1

[1]

l_ri_dce1[

DCD_DCE1 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_dcd_dce

1[0]

l_dcd_dce

1[2]

l_dcd_dce

1[1]

1[8]

DTR_DTE1 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_dtr_dte1[

l_dtr_dte1

[2]

l_dtr_dte1

[1]

l_dtr_dte1[

DSR_DTE1 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_dsr_dte1

[0]

l_dsr_dte1

[2]

l_dsr_dte1

[1]

l_dsr_dte1

[8]

RI_DTE1

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC sw_pad_ct GND

l_ri_dte1

[0]

l_ri_dte1

[2]

l_ri_dte1

[1]

l_ri_dte1[8

]

l_ri_dte1[3

]

DCD_DTE1 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC sw_pad_ct GND

l_dcd_dte

1[0]

l_dcd_dte

1[2]

l_dcd_dte

1[1]

l_dcd_dte

1[8]

l_dcd_dte

1[3]

DTR_DCE2 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

GND

l_dtr_dce2

[0]

l_dtr_dce2

[2]

l_dtr_dce2

[1]

l_dtr_dce2

[8]

RXD2

regular sw_pad_ct slow

l_rxd2[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_rxd2[2] l_rxd2[1]

pull sw_pad_ct VCC

l_rxd2[8]

GND

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

TXD2

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

regular sw_pad_ct slow

l_txd2[0]

GND

VCC

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_txd2[2] l_txd2[1]

pull

pull sw_pad_ct VCC

l_txd2[8]

GND

VCC

GND

GND NVCC8

GND NVCC5

RTS2

regular sw_pad_ct slow

l_rts2[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_rts2[2] l_rts2[1]

pull

pull sw_pad_ct VCC

l_rts2[8]

GND

VCC

CTS2

regular sw_pad_ct slow

l_cts2[0]

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cts2[8]

l_cts2[2]

l_cts2[1]

BATT_LINE regular

slow

VCC

GND

GND pu100 pu100

pull sw_pad_ct VCC

l_batt_line[

KEY_ROW0 regular sw_pad_ct slow

GND

pull

pull sw_pad_ct VCC

l_key_row

GND

GND NVCC6

l_key_row

0[0]

0[8]

KEY_ROW1 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_key_row

1[0]

l_key_row

1[2]

l_key_row

1[1]

1[8]

KEY_ROW2 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_key_row

2[0]

l_key_row

2[2]

l_key_row

2[1]

2[8]

KEY_ROW3 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_key_row

3[0]

l_key_row

3[2]

l_key_row

3[1]

3[8]

KEY_ROW4 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_key_row

4[0]

l_key_row

4[2]

l_key_row

4[1]

4[8]

KEY_ROW5 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_key_row

5[0]

l_key_row

5[2]

l_key_row

5[1]

5[8]

KEY_ROW6 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_key_row

6[0]

l_key_row

6[2]

l_key_row

6[1]

6[8]

KEY_ROW7 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_key_row

7[0]

l_key_row

7[2]

l_key_row

7[1]

7[8]

KEY_COL0 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC ipp_ode_c GND

l_key_col0

ol[0]

[0]

[2]

[1]

[8]

KEY_COL1 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC ipp_ode_c GND

l_key_col1

ol[1]

[0]

[2]

[1]

[8]

KEY_COL2 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC ipp_ode_c GND

l_key_col2

ol[2]

[0]

[2]

[1]

[8]

KEY_COL3 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC ipp_ode_c GND

l_key_col3

ol[3]

[0]

[2]

[1]

[8]

KEY_COL4 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC ipp_ode_c GND

l_key_col4

ol[4]

[0]

[2]

[1]

[8]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

KEY_COL5 regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC ipp_ode_c GND

GND

GND NVCC6

l_key_col5

[0]

l_key_col5

[2]

l_key_col5

[1]

l_key_col5

[8]

ol[5]

KEY_COL6 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC ipp_ode_c GND

l_key_col6

[0]

l_key_col6

[2]

l_key_col6

[1]

l_key_col6

[8]

ol[6]

KEY_COL7 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC ipp_ode_c GND

l_key_col7

[0]

l_key_col7

[2]

l_key_col7

[1]

l_key_col7

[8]

ol[7]

RTCK

TCK

regular

fast

slow

fast

slow

fast

GND

VCC

GND

VCC

GND

VCC pd100 pd100

GND pd100 pd100

GND pu100 pu100

VCC pu100 pu100

GND pu100 pu100

pull

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

GND NVCC6

VCC NVCC6

GND NVCC6

TMS

TDI

TDO

TRSTB

slow

SJC_MOD regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

l_sjc_mod

[0]

[2]

[1]

USB_PWR regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC

GND

GND NVCC5

l_usb_pwr

[0]

[2]

[1]

[8]

USB_OC

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usb_oc

[0]

[2]

[1]

[8]

USB_BYP regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usb_byp[

USBOTG_CLK regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbotg_c

GND sw_pad_ct VCC NVCC5

l_usbotg_c

lk[0]

lk[2]

lk[1]

lk[8]

lk[4]

USBOTG_DIR regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbotg_

GND

GND NVCC5

l_usbotg_

dir[0]

l_usbotg_

dir[2]

l_usbotg_

dir[1]

dir[8]

USBOTG_STP regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbotg_s

tp[0]

l_usbotg_s

tp[2]

l_usbotg_s

tp[1]

tp[8]

USBOTG_NXT regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbotg_

nxt[0]

l_usbotg_

nxt[2]

l_usbotg_

nxt[1]

nxt[8]

USBOTG_DAT regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbotg_

data0[0]

l_usbotg_

data0[2]

l_usbotg_

data0[1]

data0[8]

USBOTG_DAT regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbotg_

data1[0]

l_usbotg_

data1[2]

l_usbotg_

data1[1]

data1[8]

USBOTG_DAT regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbotg_

data2[0]

l_usbotg_

data2[2]

l_usbotg_

data2[1]

data2[8]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

USBOTG_DAT regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC

l_usbotg_

GND

GND NVCC5

l_usbotg_

data3[0]

l_usbotg_

data3[2]

l_usbotg_

data3[1]

data3[8]

USBOTG_DAT regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC

l_usbotg_

GND

l_usbotg_

data4[0]

l_usbotg_

data4[2]

l_usbotg_

data4[1]

data4[8]

USBOTG_DAT regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbotg_

data5[0]

l_usbotg_

data5[2]

l_usbotg_

data5[1]

data5[8]

USBOTG_DAT regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbotg_

data6[0]

l_usbotg_

data6[2]

l_usbotg_

data6[1]

data6[8]

USBOTG_DAT regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbotg_

data7[0]

l_usbotg_

data7[2]

l_usbotg_

data7[1]

data7[8]

USBH2_CLK regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbh2_cl

GND sw_pad_ct VCC NVCC10

l_usbh2_cl

k[0]

l_usbh2_cl

k[2]

l_usbh2_cl

k[1]

l_usbh2_cl

k[4]

k[8]

USBH2_DIR regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

GND

GND NVCC10

l_usbh2_di

r[0]

l_usbh2_di

r[2]

l_usbh2_di

r[1]

l_usbh2_di

r[8]

USBH2_STP regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbh2_st

p[0]

l_usbh2_st

p[2]

l_usbh2_st

p[1]

p[8]

USBH2_NXT regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbh2_n

xt[0]

l_usbh2_n

xt[2]

l_usbh2_n

xt[1]

xt[8]

USBH2_DATA0 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbh2_d

ata0[0]

l_usbh2_d

ata0[2]

l_usbh2_d

ata0[1]

ata0[8]

USBH2_DATA1 regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_usbh2_d

ata1[0]

l_usbh2_d

ata1[2]

l_usbh2_d

ata1[1]

ata1[8]

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

regular

fast

GND

GND sw_pad_ct GND

l_ld0[2]

VCC

VCC pu100 pu100 sw_pad_ct pull

l_ld0[7]

VCC

GND

GND NVCC7

GND sw_pad_ct GND

l_ld1[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld1[7]

GND sw_pad_ct GND

l_ld2[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld2[7]

GND sw_pad_ct GND

l_ld3[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld3[7]

GND sw_pad_ct GND

l_ld4[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld4[7]

GND sw_pad_ct GND

l_ld5[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld5[7]

GND sw_pad_ct GND

l_ld6[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld6[7]

GND sw_pad_ct GND

l_ld7[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld7[7]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

LD8

Pad

Slew Rate

fast

Loopback

Pull Value

Schmitt Trigger

regular

fast

GND

GND sw_pad_ct GND

l_ld8[2]

VCC

VCC pu100 pu100 sw_pad_ct pull

l_ld8[7]

VCC

GND

GND NVCC7

LD9

fast

GND sw_pad_ct GND

l_ld9[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld9[7]

VCC

GND

LD10

LD11

LD12

LD13

LD14

LD15

LD16

LD17

VSYNC0

GND sw_pad_ct GND

l_ld10[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld10[7]

GND sw_pad_ct GND

l_ld11[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld11[7]

GND sw_pad_ct GND

l_ld12[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld12[7]

GND sw_pad_ct GND

l_ld13[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld13[7]

GND sw_pad_ct GND

l_ld14[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld14[7]

GND sw_pad_ct GND

l_ld15[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld15[7]

GND sw_pad_ct GND

l_ld16[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld16[7]

GND sw_pad_ct GND

l_ld17[2]

VCC pu100 pu100 sw_pad_ct pull

l_ld17[7]

GND sw_pad_ct GND

VCC pu100 pu100 sw_pad_ct pull

l_vsync0

[2]

l_vsync0

[7]

HSYNC

FPSHIFT

DRDY0

regular

fast

GND

GND sw_pad_ct GND

l_hsync[2]

VCC

VCC pu100 pu100

pull

GND

GND NVCC7

GND sw_pad_ct GND

l_fpshift[2]

GND sw_pad_ct GND

l_drdy0[2]

SD_D_I

SD_D_IO

GND sw_pad_ct GND

l_sd_d_i[2]

GND sw_pad_ct GND

l_sd_d_io

[2]

SD_D_CLK regular

fast

GND

GND sw_pad_ct GND

VCC

VCC pu100 pu100

pull

GND

GND NVCC7

l_sd_d_clk

[2]

LCS0

LCS1

regular

fast

GND

GND sw_pad_ct GND

l_lcs0[2]

VCC

VCC pu100 pu100

pull

GND

GND NVCC7

GND sw_pad_ct GND

l_lcs1[2]

SER_RS

PAR_RS

WRITE

GND sw_pad_ct GND

l_ser_rs[2]

GND sw_pad_ct GND

l_par_rs[2]

GND sw_pad_ct GND

l_write[2]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

READ

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

regular

fast

GND

GND sw_pad_ct GND

l_read[2]

VCC

VCC pu100 pu100

pull

GND

VCC

GND

GND NVCC7

VSYNC3

fast

GND sw_pad_ct GND

VCC pu100 pu100 sw_pad_ct pull

VCC

GND

l_vsync3

[2]

l_vsync3

[7]

CONTRAST regular

fast

GND

GND sw_pad_ct GND

VCC

VCC pu100 pu100

pull

GND

GND NVCC7

l_contrast

[2]

D3_REV

regular

GND sw_pad_ct GND

pull

l_d3_rev

[2]

D3_CLS

D3_SPL

regular

fast

GND

GND sw_pad_ct GND

l_d3_cls[2]

VCC

VCC pu100 pu100

pull

GND

GND NVCC7

GND sw_pad_ct GND

l_d3_spl[2]

SD1_CMD regular sw_pad_ct fast sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

GND sw_pad_ct GND NVCC3

l_sd1_cmd

[0]

l_sd1_cmd

[9]

l_sd1_cmd

[2]

l_sd1_cmd

[1]

l_sd1_cmd

[4]

SD1_CLK

regular sw_pad_ct fast

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

GND

GND NVCC3

l_sd1_clk

[0]

l_sd1_clk

[2]

l_sd1_clk[

SD1_DATA0 regular sw_pad_ct fast sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct GND

l_sd1_dat

a0[0]

l_sd1_dat

a0[9]

l_sd1_dat

a0[2]

l_sd1_dat

a0[1]

a0[8]

SD1_DATA1 regular sw_pad_ct fast sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct GND

l_sd1_dat

a1[0]

l_sd1_dat

a1[9]

l_sd1_dat

a1[2]

l_sd1_dat

a1[1]

a1[8]

SD1_DATA2 regular sw_pad_ct fast sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct GND

l_sd1_dat

a2[0]

l_sd1_dat

a2[9]

l_sd1_dat

a2[2]

l_sd1_dat

a2[1]

a2[8]

SD1_DATA3 regular sw_pad_ct fast sw_pad_ct GND sw_pad_ct GND sw_pad_ct GND pd100 pd100

pull sw_pad_ct GND

l_sd1_dat

a3[0]

l_sd1_dat

a3[9]

l_sd1_dat

a3[2]

l_sd1_dat

a3[1]

a3[8]

ATA_CS0

ATA_CS1

regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

GND

l_ata_cs0

[0]

[2]

[1]

regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

GND

l_ata_cs1

[0]

[2]

[1]

ATA_DIOR regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_ata_dior[

l_ata_dior

l_ata_dior[

[1]

ATA_DIOW regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_ata_diow

[0]

[2]

[1]

[8]

ATA_DMACK regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_ata_dma

ck[0]

ck[2]

ck[1]

ck[8]

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

ATA_RESET regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC

l_ata_rese

GND

GND NVCC3

l_ata_rese

t_b[0]

l_ata_rese

t_b[2]

l_ata_rese

t_b[1]

t_b[8]

CE_CONTROL regular

CLKSS regular

fast

GND

GND pd100 pd100

GND pu100 pu100

pull

GND

GND NVCC8

GND NVCC1

GND NVCC3

CSPI3_MOSI regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi3_m

osi[0]

l_cspi3_m

osi[2]

l_cspi3_m

osi[1]

osi[8]

CSPI3_MISO regular sw_pad_ct slow

GND

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull

pull sw_pad_ct VCC

l_cspi3_mi

GND

GND NVCC3

l_cspi3_mi

so[0]

l_cspi3_mi

so[2]

l_cspi3_mi

so[1]

so[8]

CSPI3_SCLK regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi3_sc

GND sw_pad_ct VCC NVCC3

l_cspi3_sc

lk[0]

l_cspi3_sc

lk[2]

l_cspi3_sc

lk[1]

l_cspi3_sc

lk[4]

lk[8]

CSPI3_SPI_R regular sw_pad_ct slow

GND sw_pad_ct GND sw_pad_ct GND pu100 pu100

pull sw_pad_ct VCC

l_cspi3_sp

GND

GND NVCC3

l_cspi3_sp

i_rdy[0]

l_cspi3_sp

i_rdy[2]

l_cspi3_sp

i_rdy[1]

i_rdy[8]

TTM_PAD regular

slow

GND

GND pu100 pu100

pull

–

pull

–

GND

GND NVCC7

IOQVDD

MVCC

–

NVCC22

–

mvcc_vd

MGND

–

mvcc_vd

UVCC

UGND

FVCC

FGND

SVCC

–

NVCC7

NVCC2

svcc_vd

SGND

–

svcc_vd

NVCC1

NVCC2

NVCC3

NVCC4

NVCC5

NVCC6

NVCC7

NVCC8

NVCC9

NVCC10

NVCC21

NVCC22

NGND1

–

Table 6. Pad Settings (continued)

Drive Strength

Enable0 (High/

Normal)

Pull/

Keep

Select

Supply

Group

Value

After

Reset

Drive Strength

Enable (Max)

Pull/

Keep Enable

Open

Drain

Pin Name

Pad

Slew Rate

Loopback

Pull Value

Schmitt Trigger

NGND2

NGND3

NGND4

NGND5

NGND6

NGND7

NGND8

NGND9

NGND10

NGND21

NGND22

QVCC

–

QVCC1

QVCC4

Signal Descriptions

3.1.3

EMI Pins Multiplexing

This section discusses the multiplexing of EMI signals. The EMI signals’ multiplexing is done inside the

EMI. Table 7 lists the i.MX31 and i.MX31L pin names, pad types, and the memory devices’ equivalent pin

names.

Table 7. EMI Multiplexing

Pin Name

Pad Type

WEIM

SDRAM

PCMCIA

DDR

NFC

regular

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

–

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

–

A10

MA10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

SDBA1

SDBA0

A10

–

A10

–

MA10

MA11

MA12

MA13

–

MA10

MA11

MA12

MA13

–

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

SDBA1

SDBA0

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

CE1

CE2

–

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

NFC

Table 7. EMI Multiplexing (continued)

Pin Name

Pad Type

WEIM

SDRAM

PCMCIA

DDR

SD0

SD1

ddr

–

SD0

SD1

–

SD2

SD3

SD4

SD5

SD6

SD7

SD8

SD9

SD10

SD11

SD12

SD13

SD14

SD15

SD16

SD17

SD18

SD19

SD20

SD21

SD22

SD23

SD24

SD25

SD26

SD27

SD28

SD29

SD30

SD31

DQM0

SD10

SD11

SD12

SD13

SD14

SD15

SD16

SD17

SD18

SD19

SD20

SD21

SD22

SD23

SD24

SD25

SD26

SD27

SD28

SD29

SD30

SD31

DQM0

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

Pin Name

Table 7. EMI Multiplexing (continued)

Pad Type

WEIM

SDRAM

PCMCIA

DDR

NFC

DQM1

DQM2

DQM3

EB0

ddr

–

DQM1

–

ddr

DQM2

–

ddr

–

DQM3

–

regular

ddr

EB0

EB1

CS0

CS1

CS2

CS3

CS4

CS5

ECB

LBA

BCLK

–

REG

–

EB1

–

IORD

–

IOWR

–

CS0

–

CS1

–

CS2

CSD0

–

CS3

CSD1

–

CS4

–

CS5

–

ECB

–

LBA

–

BCLK

–

RAS

–

CAS

–

CAS

–

SDWE

SDCKE0

SDCKE1

SDCLK

SDQS0

SDQS1

SDQS2

SDQS3

NFWE

NFRE

NFALE

NFCLE

NFWP

NFCE

–

SDWE

–

SDCKE0

–

SDCKE1

–

SDCLK

–

ddr

–

SDCLK

–

ddr

–

SDQS0

–

ddr

–

SDQS1

–

ddr

–

SDQS2

–

ddr

–

SDQS3

–

regular

–

ALE

CLE

–

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Signal Descriptions

NFC

Table 7. EMI Multiplexing (continued)

Pin Name

Pad Type

WEIM

SDRAM

PCMCIA

DDR

NFRB

D15

regular

–

D15

D14

D13

D12

D11

D10

–

D15

D14

D13

D12

D11

D10

–

R/B

D15

D14

D13

D12

D11

D10

–

D14

D13

D12

D11

D10

PC_CD1

PC_CD2

PC_WAIT

PC_READY

PC_PWRON

PC_VS1

PC_VS2

PC_BVD1

PC_BVD2

PC_RST

IOIS16

PC_RW

PC_POE

M_REQUEST

M_GRANT

CD1

CD2

WAIT

READY

PC_PWRON

VS1

VS2

BVD1

BVD2

RST

IOIS16/WP

–

POE

–

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

4 Electrical Characteristics

This section provides the chip-level and module-level electrical characteristics for the i.MX31 and

i.MX31L:

•

Section 4.1, “i.MX31 and i.MX31L Chip-Level Conditions” on page 60

— Section 4.1.1, “Power Specifications” on page 63

•

Section 4.2, “Supply Power-Up Requirements and Restrictions” on page 66

Section 4.3, “Module-Level Electrical Specifications” on page 66

— Section 4.3.1, “I/O Pad (PADIO) Electrical Specifications” on page 66

— Section 4.3.3, “Clock Amplifier Module (CAMP) Electrical Characteristics” on page 70

— Section 4.3.4, “1-Wire Electrical Specifications” on page 70

— Section 4.3.5, “ATA Electrical Specifications (ATA Bus, Bus Buffers)” on page 72

— Section 4.3.6, “AUDMUX Electrical Specifications” on page 80

— Section 4.3.7, “CSPI Electrical Specifications” on page 80

— Section 4.3.8, “DPLL Electrical Specifications” on page 82

— Section 4.3.9, “EMI Electrical Specifications” on page 83

– Section 4.3.9.1, “NAND Flash Controller Interface (NFC)” on page 83

– Section 4.3.9.2, “Wireless External Interface Module (WEIM)” on page 88

– Section 4.3.9.3, “SDRAM (DDR and SDR) Memory Controller” on page 93

— Section 4.3.11, “FIR Electrical Specifications” on page 101

— Section 4.3.12, “Fusebox Electrical Specifications” on page 101

— Section 4.3.13, “I2C Electrical Specifications” on page 102

— Section 4.3.14, “IPU—Sensor Interfaces” on page 106

— Section 4.3.15, “IPU—Display Interfaces” on page 106

— Section 4.3.16, “Memory Stick Host Controller (MSHC)” on page 131

— Section 4.3.17, “Personal Computer Memory Card International Association (PCMCIA)” on

page 133

— Section 4.3.18, “PWM Electrical Specifications” on page 135

— Section 4.3.19, “SDHC Electrical Specifications” on page 137

— Section 4.3.20, “SIM Electrical Specifications” on page 138

— Section 4.3.21, “SJC Electrical Specifications” on page 141

— Section 4.3.22, “SSI Electrical Specifications” on page 143

— Section 4.3.23, “USB Electrical Specifications” on page 151

4.1

i.MX31 and i.MX31L Chip-Level Conditions

This section provides the chip-level electrical characteristics for the IC. See Table 8 for a quick reference

to the individual tables and sections.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 8. i.MX31/i.MX31L Chip-Level Conditions

For these characteristics, …

Topic appears …

Table 9, “DC Recommended Operating Conditions”

on page 61

on page 62

on page 63

Table 10, “Voltage versus Core Frequency”

Table 11, “Interface Frequency”

Table 12, “DC Absolute Maximum Operating Conditions”

Section 4.1.1, “Power Specifications”

Table 9 provides the DC recommended operating conditions.

NOTE

The use of the terms OVDD and OVSS in this section refers to VDD/VSS

Power rails of I/O pads, which are supplied by the nearest noisy (V

DDIOL/H

and V

) supply pads, and are in the range of 1.75 to 3.1 V.

DD_DDR

Table 9. DC Recommended Operating Conditions

Parameter

Symbol

Min

Max

Units

Core Supply Voltage^{1, 2}

(QVCC, QVCC1, QVCC4)

V_DD

1.22

1.65³

State Retention (SR) Operating Voltage⁴

V_SR

0.95

1.75

–

I/O Supply Voltage

V_DDIOL

1.9

NVCC1, NVCC3, NVCC4-10

I/O Supply Voltage

NVCC1, NVCC3, NVCC4-10

V_DDIOH

2.7⁵

1.75

3.1^6,7,8

1.95

Supply Voltage (DDR Output Drive Supply)

NVCC2, NVCC21, NVCC22

V_{DD_DDR}

PLL/FPM supplies: FVCC, MVCC, SVCC, UVCC⁹

Fusebox read Supply Voltage on the VDD_FUSE pin

Fusebox Program Supply Voltage on the VDD_FUSE pin¹⁰

Operating Ambient Temperature

V_PLL

V_FUSE

V_{FUSE_PGM}

T_A

1.3

1.65

3.0

1.6

1.95

3.3

^oC

Measured at supply pins, including peripherals, ARM, and L2 cache supplies (QVCC, QVCC1, QVCC4, respectively).

Min voltage listed is for the lower frequency. See Table 10 for correlation of voltage range and associated frequencies.

Core voltage supply is considered “Overdrive” for 1.45–1.65 V range. Duty cycles in core overdrive—whether switching or

not—must be limited to a cumulative duration of 1.25 years or less (25% duty cycle for a 5-year rated part) to sustain a

maximum core VDD operating voltage of 1.65 V without significant device degradation.

The SR voltage (Quiet supplies QVCC, QVCC1, QVCC4), is applied after IC is put in SR mode. NOTE: Applying low voltage

point is dependent on noisy (NVCC) supplies being less than or equal to 1.95 V.

The range—1.9 V to 2.7 V—is a valid voltage range; however, the voltage ranges given in this table align to more common

industry voltage ranges.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Recommended maximum OVDD operating voltage is 3.1 V for GPIO in either slow or fast mode. Switching duty cycles must

be limited to a cumulative duration of 1 year or less (20% duty cycle for a 5yr rated part) to sustain a MAX OVDD operating

voltage of 3.3V without significant device degradation. A switching cycle is defined as the period of time that the pad is powered

to OVDD and actively switching. Switching cycles exceeding this limit may affect device performance or cause permanent

damage to the device.

The performance at 1.8 V of GPIO devices that are operated at 3.3 V over an extended period of time (for example. 2 years or

longer at a 20% duty cycle) is not guaranteed. Reliability degradation may render the device too slow or inoperable.

Overshoot and undershoot conditions (transitions above OVDD and below OVSS) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.

Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

For normal operating conditions, PLLs’ and core supplies must maintain the following relation: PLL ≥ Core – 100 mV. In other

words, for a 1.6 V core supply, PLL supplies must be set to 1.5 V or higher.

¹⁰Providing a voltage that is lower than specified does not prevent the fuses from being blown if attempting to program a fuse.

Table 10 gives details of the applied voltages to the i.MX31/i.MX31L Core Supply I/O versus the

frequencies of the ARM11 core.

Table 10. Voltage versus Core Frequency

Core

Symbol

Min (V)

Max (V)

Frequency (MHz)

ARM11 (V_DD

)

f_ARM

1.22¹

1.55³

1.65^{1, 2}

1.65³

0–400

401–532

As measured at the ball. Recommended settings for PMIC (Power Management IC) is 1.275 V.

All overdrive/25% duty-cycles restrictions apply, as specified in Table 9.

As measured at the ball. Recommended voltage settings for PMIC is 1.6 V.

Table 11 provides information for interface frequency limits. For more details about clocks characteristics,

see Section 4.3.8, “DPLL Electrical Specifications” on page 82.

Table 11. Interface Frequency

Parameter

JTAG TCK Frequency

Symbol

Min

Typ

Max

Units

f_JTAG

f_CKIL

f_CKIH

MHz

kHz

CKIL Frequency

CKIH Frequency

32.768

38.4

100

MHz

Table 12 provides the DC absolute maximum operating conditions.

CAUTION

Stresses beyond those listed under “DC Absolute Maximum Operating

Conditions,” (Table 12) may cause permanent damage to the device. These

are stress ratings only. Functional operation of the device at these or any

other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions

for extended periods may affect device reliability.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 12. DC Absolute Maximum Operating Conditions

Ref. Num

Parameter

Symbol

Min

Max

Units

Supply Voltage

V_DDmax

V_DDIOmax

V_Imax

-0.5

-40

–

1.65

3.3

Supply Voltage (Level Shift I/O)

Input Voltage Range

V_DDIOH+0.3

125

Storage Temperature

T_storage

V_esd

^oC

Absolute Maximum HBM (Human Body Model) ESD stress

voltage.

2500

Absolute Maximum offset voltage allowed in run mode

between core supplies.

V_{coers_offset}

–

+15

The offset is any difference between all core voltages for supply pads—QVCC, QVCC1, and QVCC4.

4.1.1

Power Specifications

Table 13 shows the power consumption for the i.MX31 and i.MX31L.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 13. Power Consumption (Typical Values)

Peripheral

ARM

PLL

Mode

Conditions

Current¹

Total Power

Current²Current

State Retention • Core VDD (QVCC) = 0.95 V

• ARM supply QVCC1 = QVCC = 0.95 V

200 µA

150 µA

40 µA

0.4 mW

• ARM in well bias

• L2 caches are power gated (QVCC4 = 0 V)

• All PLLs are Off

• FPM is off

• 32 kHz Input on

• CKIH input is off

• CAMP is off

• TCK input is off

• All the modules are off

• No external resistive loads

• RNGA oscillator is off

• T_A= 25ºC

Doze

• All Vdds = 1.2 V (QVCC=QVCC1= QVCC4 = 1.2 V)

• ARM in wait for interrupt mode

• ARM is in well bias

7 mA

1.0 mA 3 mA for

13.0 mW

each

PLL

• MAX is stopped

• L2 cache is stopped but powered

• MCU PLL is on (532 MHz)

• USB PLL and SPLL are off

• FPM is on

• CKIH input is off

• CAMP is off

• 32 kHz Input on

• All the modules are off (by programming CGR[2:0]

registers)

• RNGA oscillator is off

• No external resistive loads

• T_A= 25ºC

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 13. Power Consumption (Typical Values) (continued)

Peripheral

Current¹

ARM

PLL

Mode

Conditions

Total Power

Current²Current

WAIT (all clocks • All Vdds = 1.2 V (QVCC=QVCC1=QVCC4 = 1.2 V)

7 mA

3 mA

3 mA for

each

PLL

15.0 mW

gated off)

• ARM in wait for interrupt mode

• MAX is active

• L2 cache is stopped but powered

• MCU PLL is on (532 MHz)

• USB PLL and SPLL are off

• FPM is on

• CKIH input is off

• CAMP is off

• 32 kHz Input on

• All the modules are off (by programming CGR[2:0]

registers)

• RNGA oscillator is off

• No external resistive loads

• T_A= 25ºC

Deep Sleep

• Core VDD (QVCC) = 0.95 V

• ARM (QVCC1) & L2 caches (QVCC4) are power gate

• All PLLs are off

200 µA

0 µA

40 µA

0.22 mW

• FPM is off

• 32 kHz Input on

• CKIH input is off

• CAMP is off

• TCK input is off

• All the modules are off

• No external resistive loads

• RNGA oscillator is off

• T_A= 25ºC

QVCC supply.

QVCC1 supply.

4.2

Supply Power-Up Requirements and Restrictions

Any i.MX31/i.MX31L board design must comply with the power-up sequence guideline, as described in

this section, to guarantee proper power-up of the device. Any deviation from this sequence may result in

any or all of the following situations:

•

Cause excessive current.

Prevent the device from booting.

Cause irreversible damage to the i.MX31/i.MX31L (worst-case scenario).

The Power On Reset (POR) pin must be kept asserted (low) throughout the power up sequence. Power up

logic must guarantee that all power sources must be on prior to the release (de-assertion) of POR. Figure 2

depicts the power supply power up sequence. (Power management logic should guarantee 90% supply

before transitional to the next state.) The sequence is as follows:

1. Quiet supplies—QVCC, QVCC1, QVCC4 (peripherals, ARM, L2 cache)

2. NVCC1 and IOQVDD—for assuring reset signals are propagating into core

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

3. Powering up of the remainder of noisy and PLL supplies, which can be done simultaneously. The

order within the noisy supplies must be maintained, as follows:

a) Remainder of noisy supplies (all except for the NVCC2, 21,22, and NVCC1 supplies)

b) NVCC2, NVCC21, NVCC22.

4. FUSE_VDD—the last supply to be powered up

Hold POR Asserted

QVCC, QVCC1, QVCC4

NVCC1,

IOQVDD

Remainder of Noisy Supplies—

PLL’s

V_DDIOL/H

Supplies

NVCC2,

NVCC21, 22

FUSE_VDD

Release POR

Figure 2. Power-Up Sequence

4.3

Module-Level Electrical Specifications

This section contains the i.MX31 and i.MX31L electrical information including timing specifications,

arranged in alphabetical order by module name.

4.3.1

I/O Pad (PADIO) Electrical Specifications

This section specifies the AC/DC characterization of functional I/O pads of the i.MX31. There are two

main types of pads: regular and DDR. In this document, the “Regular” type is referred to as GPIO.

4.3.1.1

DC Electrical Characteristics

The i.MX31/i.MX31L pad I/O operating characteristics appear in Table 14 for GPIO pads and Table 15

for DDR (Double Data Rate) pads.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 14. GPIO Pads DC Electrical Parameters

Parameter

Symbol

Test Conditions

Min

Typ

Max

Units

High-level output voltage

V_OH

I_OH= –1 mA

OVDD

–0.15¹

–

_OH= spec’ed Drive

I_OL= 1 mA

0.8*OVDD

–

0.15

Low-level output voltage

V_OL

–

I_OL= spec’ed Drive

0.2*OVDD

–

High-level output current, slow slew rate²

I_{OH_S}

V_OH=0.8*OVDD

Std Drive

–2

–4

–8

High Drive

Max Drive

High-level output current, fast slew rate²

Low-level output current, slow slew rate²

Low-level output current, fast slew rate²

I_{OH_F}

I_{OL_S}

I_{OL_F}

V_OH=0.8*OVDD

Std Drive

–

–4

–6

–8

High Drive

Max Drive

V_OL=0.2*OVDD

Std Drive

High Drive

Max Drive

V_OL=0.2*OVDD

Std Drive

High Drive

Max Drive

High-Level DC input voltage³

Low-Level DC input voltage³

Input Hysteresis

V_IH

V_IL

–

0.7*OVDD

–

OVDD

0.3*VDD

–

V_HYS

V_T+

V_T-

R_PU

R_PD

I_IN

0.25

–

Schmitt trigger VT+^{1, 4}

0.5*VDD

–

Schmitt trigger VT-

–

0.5*VDD

268

Pull-up resistor (100 KΩ PU)

Pull-down resistor (100 KΩ PD)

Input current (no PU/PD)⁵

100

0.33

KΩ

343

V_I= 0

V_I= OVDD

250

100

Input current (100 KΩ PU)

Input current (100 KΩ PD)

Tri-state Hi-Z input current

I_IN

I_Z

V_I= 0

V_I= OVDD

–

0.1

µA

V_I= 0

V_I= OVDD

0.25

µA

V_I= OVDD or 0

µA

Power rail for output driver 1.75 - 3.1 V.

Tested per I/O pad.

V_IH, V_IL,V_T+and V_T-for the pads in supply groups NVCC3-NVCC10 are referenced to OVDD.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

Typ condition: typ model, 1.875 V and 25°C. Max condition: bcs model, 3.3 V and 105°C.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 15. DDR (Double Data Rate) I/O Pads DC Electrical Parameters

Parameter

Symbol

Test Conditions

Min

Typ

Max

Units

High-level output voltage¹

Low-level output voltage

High-level output current²

V_OH

I_OH= –1 mA

I_OH= spec’ed Drive

I_OL= 1 mA

OVDD –0.12

–

0.8*OVDD

–

0.08

V_OL

–

I_OL= spec’ed Drive

0.2*OVDD

–

I_OH

V_OH=0.8*OVDD

Std Drive

–3.6

–7.2

–10.8

–14.4

High Drive

Max Drive

DDR Drive

Low-level output current²

I_OL

V_OL=0.2*OVDD

Std Drive

High Drive

Max Drive

DDR Drive

–

3.6

7.2

10.8

14.4

High-Level DC input voltage of CMOS receiver

Low-Level DC input voltage of CMOS receiver

Low-level input current³

V_IH

V_IL

I_IL

–

0.7*OVDD OVDD OVDD+0.3

–0.3

–

0.3*OVDD

V_I= 0

–

900

140

µA

High-level input current

I_IH

I_Z

V_I= OVDD

V_I= OVDD or 0

Tri-state Hi-Z current

Max operating voltage for DDR pads with all drive strengths is 1.95 V.

Tested per I/O pad.

Input current conditions: Typical condition: typ model, 1.875 V and 25°C. Max condition: bcs model, 3.3 V and 105°C

4.3.2

AC Electrical Characteristics

Figure 3 depicts the load circuit for output pads. Figure 4 depicts the output pad transition time waveform.

The range of operating conditions appears in Table 16 for slow general I/O, Table 17 for fast general I/O,

and Table 18 for DDR I/O (unless otherwise noted).

From Output

Under Test

Test Point

CL includes package, probe and jig capacitance

Figure 3. Load Circuit for Output Pad

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

OVDD

80%

20%

80%

20%

PA1

Output (at pad)

PA1

Figure 4. Output Pad Transition Time Waveform

Table 16. AC Electrical Characteristics of Slow General I/O Pads

Test

Condition

Parameter

Symbol

Min

Typ

Max

Units

PA1 Output Pad Transition Times (Max Drive)

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Std Drive)

tpr

25 pF

50 pF

0.92

1.5

1.95

2.98

3.17

4.75

tpr

25 pF

50 pF

1.52

2.75

4.81

8.42

25 pF

50 pF

2.79

5.39

8.56

16.43

Fast/slow characteristic is selected per GPIO I/O pad (where available) by “slew rate” control. See Table 6.

Table 17. AC Electrical Characteristics of Fast General I/O Pads

Test

Condition

Parameter

Symbol

Min

Typ

Max

Units

PA1

Output Pad Transition Times (Max Drive)

tpr

25 pF

50 pF

0.68

1.34

1.33

2.6

2.07

4.06

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Std Drive)

tpr

25 pF

50 pF

.91

1.79

1.77

3.47

2.74

5.41

25 pF

50 pF

1.36

2.68

2.64

5.19

4.12

8.11

Fast/slow characteristic is selected per GPIO I/O pad (where available) by “slew rate” control. See Table 6.

Recommended max operating voltage for GPIO in fast mode with all drive strengths is 1.95 V. Absolute maximum is described

in Table 9.

Table 18. AC Electrical Characteristics of DDR I/O Pads

Test

Condition

Parameter

Symbol

Min

Typ

Max

Units

PA1

Output Pad Transition Times (DDR Drive)

tpr

25 pF

50 pF

0.51

0.97

0.82

1.58

1.28

2.46

Output Pad Transition Times (Max Drive)

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Std Drive)

tpr

25 pF

50 pF

0.67

1.29

1.08

2.1

1.69

3.27

25 pF

35 pF

.99

1.93

1.61

3.13

2.51

4.89

25 pF

50 pF

1.96

3.82

3.19

6.24

4.99

9.73

Absolute max operating voltage for DDR pads with all drive strengths is 1.95 V.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

4.3.3

Clock Amplifier Module (CAMP) Electrical Characteristics

This section outlines the Clock Amplifier Module (CAMP) specific electrical characteristics. Table 19

shows clock amplifier electrical characteristics.

Table 19. Clock Amplifier Electrical Characteristics

Parameter

Input Frequency

Min

Typ

Max

Units

8.0

–

34.0

0.3

MHz

VIL (for square input)

VIH (for square input)

Sinusoidal Input Amplitude

Duty Cycle

(VDD ¹- 0.25)

0.4 ²

–

VDD

Vp-p

VDD is the supply voltage of CAMP

This value of the sinusoidal input will be measured through characterization.

4.3.4

1-Wire Electrical Specifications

Figure 5 depicts the RPP timing, and Table 20 lists the RPP timing parameters.

OWIRE Tx

DS2502 Tx

“Presence Pulse”

“Reset Pulse”

OW2

1-Wire bus

(BATT_LINE)

OW3

OW1

OW4

Figure 5. Reset and Presence Pulses (RPP) Timing Diagram

Table 20. RPP Sequence Delay Comparisons Timing Parameters

Parameters

Symbol

Min

Typ

Max

Units

OW1

OW2

OW3

OW4

Reset Time Low

Presence Detect High

Presence Detect Low

Reset Time High

t_RSTL

t_PDH

t_PDL

480

511

–

240

–

µs

–

t_RSTH

480

512

Figure 6 depicts Write 0 Sequence timing, and Table 21 lists the timing parameters.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

OW6

1-Wire bus

(BATT_LINE)

OW5

Figure 6. Write 0 Sequence Timing Diagram

Table 21. WR0 Sequence Timing Parameters

Parameter

Symbol

Min

Typ

Max

Units

OW5

OW6

Write 0 Low Time

Transmission Time Slot

t_{WR0_low}

t_SLOT

100

117

120

µs

OW5

Figure 7 depicts Write 1 Sequence timing, Figure 8 depicts the Read Sequence timing, and Table 22 lists

the timing parameters.

OW8

1-Wire bus

(BATT_LINE)

OW7

Figure 7. Write 1 Sequence Timing Diagram

OW8

1-Wire bus

(BATT_LINE)

OW7

OW9

Figure 8. Read Sequence Timing Diagram

Table 22. WR1 /RD Timing Parameters

Parameter

Symbol

Min

Typ

Max

Units

OW7

OW8

OW9

Write 1 / Read Low Time

Transmission Time Slot

Release Time

t_LOW1

t_SLOT

117

–

120

µs

t_RELEASE

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

4.3.5

ATA Electrical Specifications (ATA Bus, Bus Buffers)

This section discusses ATA electricals and explains how to make sure the ATA interface meets timing. To

meet electrical spec on the ATA bus, several requirements must be met. For a detailed description, refer

to the ATA specification.

This electrical spec must be met for the pads used on the ATA I/Os if no bus buffers and bus transceivers

are used.

Alternative is to use bus buffers. This is the only way to operate the ATA interface if 3.3 Volt or 5.0 Volt

compatibility on the ATA bus is wanted, and no 3.3 Volt or 5.0 Volt tolerant pads on the device are

available.

The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors

make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast

UDMA mode operation is needed, this may not be compatible with bus buffers.

Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.

According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with

a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.

When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a

direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus

should drive from host to device. When its low, the bus should drive from device to host. Steering of the

signal is such that contention on the host and device tri-state busses is always avoided.

4.3.5.1

Timing Parameters

In the timing equations, some timing parameters are used. These parameters depend on the implementation

of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 23 shows ATA

timing parameters.

Table 23. ATA Timing Parameters

Value/

Name

Description

Contributing Factor¹

Bus clock period (ipg_clk_ata)

peripheral clock

frequency

ti_ds

ti_dh

tco

Set-up time ata_data to ata_iordy edge (UDMA-in only)

hold time ata_iordy edge to ata_data (UDMA-in only)

11 ns

6 ns

propagation delay bus clock L-to-H to

15 ns

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data, ata_buffer_en

tsu

tsui

thi

set-up time ata_data to bus clock L-to-H

set-up time ata_iordy to bus clock H-to-L

hold time ata_iordy to bus clock H to L

19 ns

9 ns

5 ns

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 23. ATA Timing Parameters (continued)

Description

Value/

Name

Contributing Factor¹

tskew1

Max difference in propagation delay bus clock L-to-H to any of following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data (write), ata_buffer_en

7 ns

tskew2

tskew3

Max difference in buffer propagation delay for any of following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data (write), ata_buffer_en

transceiver

Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data

transceiver

(read)

tbuf

Max buffer propagation delay

transceiver

cable

tcable1

tcable2

tskew4

tskew5

cable propagation delay for ata_data

cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack

Max difference in cable propagation delay between ata_iordy and ata_data (read)

cable

Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack)

and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)

cable

tskew6

Max difference in cable propagation delay without accounting for ground bounce

cable

Values provided where applicable.

4.3.5.2

PIO Mode Timing

Figure 9 shows timing for PIO read, and Table 24 lists the timing parameters for PIO read.

Figure 9. PIO Read Timing Diagram

Table 24. PIO Read Timing Parameters

ATA

Parameter

Controlling

Variable

Value

Parameter from Figure 9

t2r

t1 (min) = time_1 * T - (tskew1 + tskew2 + tskew5)

t2 min) = time_2r * T - (tskew1 + tskew2 + tskew5)

t9 (min) = time_9 * T - (tskew1 + tskew2 + tskew6)

time_1

time_2r

time_3

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 24. PIO Read Timing Parameters (continued)

ATA

Parameter

Controlling

Variable

Value

Parameter from Figure 9

t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

If not met, increase

time_2.

–

tA (min) = (1.5 + time_ax) * T - (tco + tsui + tcable2 + tcable2 + 2*tbuf)

time_ax

trd

trd1

trd1 (max) = (-trd) + (tskew3 + tskew4)

time_pio_rdx

trd1 (min) = (time_pio_rdx - 0.5)*T - (tsu + thi)

(time_pio_rdx - 0.5) * T > tsu + thi + tskew3 + tskew4

–

t0 (min) = (time_1 + time_2 + time_9) * T

time_1, time_2r, time_9

Figure 10 shows timing for PIO write, and Table 25 lists the timing parameters for PIO write.

Figure 10. Multiword DMA (MDMA) Timing

Table 25. PIO Write Timing Parameters

ATA

Parameter

Controlling

Variable

Value

Parameter from Figure 10

t2w

t1 (min) = time_1 * T - (tskew1 + tskew2 + tskew5)

t2 (min) = time_2w * T - (tskew1 + tskew2 + tskew5)

t9 (min) = time_9 * T - (tskew1 + tskew2 + tskew6)

t3 (min) = (time_2w - time_on)* T - (tskew1 + tskew2 +tskew5)

time_1

time_2w

time_9

–

If not met, increase

time_2w.

–

t4 (min) = time_4 * T - tskew1

time_4

tA = (1.5 + time_ax) * T - (tco + tsui + tcable2 + tcable2 + 2*tbuf)

t0(min) = (time_1 + time_2 + time_9) * T

time_ax

time_1, time_2r,

time_9

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 25. PIO Write Timing Parameters (continued)

Value

ATA

Parameter

Controlling

Variable

Parameter from Figure 10

–

Avoid bus contention when switching buffer on by making ton long

enough.

–

Avoid bus contention when switching buffer off by making toff long

enough.

Figure 11 shows timing for MDMA read, Figure 12 shows timing for MDMA write, and Table 26 lists the

timing parameters for MDMA read and write.

Figure 11. MDMA Read Timing Diagram

Figure 12. MDMA Write Timing Diagram

Table 26. MDMA Read and Write Timing Parameters

Parameter

from

Figure 11,

Figure 12

Controlling

Variable

ATA Parameter

Value

tm, ti

td, td1

tm (min) = ti (min) = time_m * T - (tskew1 + tskew2 + tskew5)

td1.(min) = td (min) = time_d * T - (tskew1 + tskew2 + tskew6)

tk.(min) = time_k * T - (tskew1 + tskew2 + tskew6)

time_m

time_d

time_k

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 26. MDMA Read and Write Timing Parameters (continued)

Parameter

from

Figure 11,

Figure 12

Controlling

Variable

ATA Parameter

Value

–

t0 (min) = (time_d + time_k) * T

time_d, time_k

time_d

tg(read)

tgr

tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

tgr.(min-drive) = td - te(drive)

tf(read)

tg(write)

tf(write)

tfr

–

tfr (min-drive) = 0

–

time_d

tg (min-write) = time_d * T - (tskew1 + tskew2 + tskew5)

tf (min-write) = time_k * T - (tskew1 + tskew2 + tskew6)

tL (max) = (time_d + time_k-2)*T - (tsu + tco + 2*tbuf + 2*tcable2)

tn= tj= tkjn = (max(time_k,. time_jn) * T - (tskew1 + tskew2 + tskew6)

–

time_k

–

time_d, time_k

time_jn

–

tn, tj

tkjn

–

ton

toff

ton = time_on * T - tskew1

toff = time_off * T - tskew1

4.3.5.3

UDMA In Timing

Figure 13 shows timing when the UDMA in transfer starts, Figure 14 shows timing when the UDMA in

host terminates transfer, Figure 15 shows timing when the UDMA in device terminates transfer, and

Table 27 lists the timing parameters for UDMA in burst.

Figure 13. UDMA In Transfer Starts Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

Preliminary

Freescale Semiconductor

Electrical Characteristics

Figure 14. UDMA In Host Terminates Transfer Timing Diagram

Figure 15. UDMA In Device Terminates Transfer Timing Diagram

Table 27. UDMA In Burst Timing Parameters

Parameter

from

ATA

Parameter

Figure 13,

Figure 14,

Figure 15

Description

Controlling Variable

tack

tenv

tack

tenv

tack (min) = (time_ack * T) - (tskew1 + tskew2)

time_ack

time_env

tenv (min) = (time_env * T) - (tskew1 + tskew2)

tenv (max) = (time_env * T) + (tskew1 + tskew2)

tds

tdh

tds1

tdh1

tds - (tskew3) - ti_ds > 0

tdh - (tskew3) -ti_dh > 0

tskew3, ti_ds, ti_dh

should be low enough

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 27. UDMA In Burst Timing Parameters (continued)

Parameter

from

Figure 13,

Figure 14,

Figure 15

ATA

Parameter

Description

Controlling Variable

tcyc

trp

tc1

trp

(tcyc - tskew) > T

T big enough

time_rp

trp (min) = time_rp * T - (tskew1 + tskew2 + tskew6)

(time_rp * T) - (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs (drive)

tmli1 (min) = (time_mlix + 0.4) * T

–

tx1¹

tmli1

tzah

tdzfs

tcvh

tmli

tzah

tdzfs

tcvh

–

time_mlix

time_zah

time_dzfs

time_cvh

–

tzah (min) = (time_zah + 0.4) * T

tdzfs = (time_dzfs * T) - (tskew1 + tskew2)

tcvh = (time_cvh *T) - (tskew1 + tskew2)

ton

toff

ton = time_on * T - tskew1

toff = time_off * T - tskew1

There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last

active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.

2. Make ton and toff big enough to avoid bus contention

4.3.5.4 UDMA Out Timing

Figure 16 shows timing when the UDMA out transfer starts, Figure 17 shows timing when the UDMA out

host terminates transfer, Figure 18 shows timing when the UDMA out device terminates transfer, and

Table 28 lists the timing parameters for UDMA out burst.

Figure 16. UDMA Out Transfer Starts Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Figure 17. UDMA Out Host Terminates Transfer Timing Diagram

Figure 18. UDMA Out Device Terminates Transfer Timing Diagram

Table 28. UDMA Out Burst Timing Parameters

Parameter

from

ATA

Parameter

Controlling

Variable

Figure 16,

Figure 17,

Figure 18

Value

tack

tenv

tack

tenv

tack (min) = (time_ack * T) - (tskew1 + tskew2)

time_ack

time_env

tenv (min) = (time_env * T) - (tskew1 + tskew2)

tenv (max) = (time_env * T) + (tskew1 + tskew2)

tdvs

tdvh

tcyc

tdvs

tdvh

tcyc

–

tdvs = (time_dvs * T) - (tskew1 + tskew2)

tdvs = (time_dvh * T) - (tskew1 + tskew2)

tcyc = time_cyc * T - (tskew1 + tskew2)

t2cyc = time_cyc * 2 * T

time_dvs

time_dvh

time_cyc

t2cyc

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 28. UDMA Out Burst Timing Parameters (continued)

Parameter

from

Figure 16,

Figure 17,

Figure 18

ATA

Parameter

Controlling

Variable

Value

trfs1

–

trfs

tdzfs

tss

trfs = 1.6 * T + tsui + tco + tbuf + tbuf

–

tdzfs = time_dzfs * T - (tskew1)

time_dzfs

tss

tmli

tli

tss = time_ss * T - (tskew1 + tskew2)

time_ss

tdzfs_mli

tli1

tdzfs_mli =max (time_dzfs, time_mli) * T - (tskew1 + tskew2)

–

tli1 > 0

–

tli

tli2

tli2 > 0

–

tli

tli3

tli3 > 0

–

time_cvh

–

tcvh

–

tcvh

tcvh = (time_cvh *T) - (tskew1 + tskew2)

ton

toff

ton = time_on * T - tskew1

toff = time_off * T - tskew1

4.3.6

AUDMUX Electrical Specifications

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between

internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is hence governed by the SSI module. Please refer to their respective electrical

specifications.

4.3.7

CSPI Electrical Specifications

This section describes the electrical information of the CSPI.

4.3.7.1 CSPI Timing

Figure 19 and Figure 20 depict the master mode and slave mode timings of CSPI, and Table 29 lists the

timing parameters.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

CSPIx_DRYN

CS11

CSPIx_CS_x

CSPIx_CLK

CS2

CS6

CS1

CS3

CS5

CS4

CS3

CS2

CS7

CS9

CS8

CSPIx_DO

CSPIx_DI

CS10

Figure 19. CSPI Master Mode Timing Diagram

NOTE

CSPI1_DRYN is connected to CSPI1_CS_1, CSPI2_DRYN is connected to

DAM2_T_CLK

CSPIx_CS_x

CSPIx_CLK

CS1

CS5

CS3

CS2

CS6

CS4

CS3

CS2

CS9

CS10

CSPIx_DI

CS8

CS7

CSPIx_DO

Figure 20. CSPI Slave Mode Timing Diagram

Table 29. CSPI Interface Timing Parameters

Parameter

Symbol

Min

Max

Units

CS1

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CSPIx_CLK Cycle Time

t_clk

t_SW

–

CSPIx_CLK High or Low Time

CSPIx_CLK Rise or Fall

t_RISE/FALL

t_CSLH

t_SCS

7.6

–

CSPIx_CS_x pulse width

CSPIx_CS_x Lead Time (CS setup time)

CSPIx_CS_x Lag Time (CS hold time)

CSPIx_DO Setup Time

–

t_HCS

–

t_Smosi

t_Hmosi

–

CSPIx_DO Hold Time

–

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 29. CSPI Interface Timing Parameters (continued)

Parameter

Symbol

Min

Max

Units

CS9

CS10

CS11

CSPIx_DI Setup Time

CSPIx_DI Hold Time

t_Smiso

t_Hmiso

t_SDRY

–

CSPIx_DRYN Setup Time

4.3.8

DPLL Electrical Specifications

The three PLL’s of the MX31/MX31L (MCU, USB, and Serial PLL) are all based on same DPLL design.

The characteristics provided herein apply to all of them, except where noted explicitly. The PLL

characteristics are provided based on measurements done for both sources—external clock source (CKIH),

and FPM (Frequency Pre-Multiplier) source.

4.3.8.1

Electrical Specifications

Table 30 lists the DPLL specification.

Table 30. DPLL Specifications

Parameter

Min

Typ

Max

Unit

Comments

CKIH reference frequency

100

–

MHz

–

CKIL referencer frequency (FPM

enable mode)

32; 32.768,

38.4

Predivision factor

–

PLL reference frequency range

after Predivider

MHz

µs

Maximum allowed reference clock

phase noise.

–

100

398

–

Frequency lock time

(FOL mode or non-integer MF)

µs

Cycles of divided reference

clock.

Phase lock time

–

1.4

–

100

1.6

4.4

µs

In addition to the frequency

PLL Power supply voltage

Single PLL current consumption

–

Maximum allowed PLL supply

voltage ripple

–

F_modulation< 50 kHz

Maximum allowed PLL supply

voltage ripple

–

F_modulation< 300 kHz

Maximum allowed PLL supply

voltage ripple

F_modulation< 300 kHz

PLL output clock phase jitter

–

5.2

Measured on CKO pin

420

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

4.3.9

EMI Electrical Specifications

This section provides electrical parametrics and timings for EMI module.

4.3.9.1

NAND Flash Controller Interface (NFC)

There are two modes of operations for the NFC—default and ONE_CYCLE.

Normal NFC mode—using two flash clock cycles for one access of RE and WE. AC parameters

calculation for this mode assume the flash clock cycle frequency is 22.5 MHz (as an example).

One-Cycle NFC mode—using one flash cycle for one access of RE and WE. AC parameters calculation

for this mode assume the flash clock cycle frequency that is 33.5 MHz (as an example).

4.3.9.1.1

Normal NFC Mode (Default)

The flash clock maximum frequency goes up to 50 MHz. Figure 21, Figure 22, Figure 23, and Figure 24

depict the relative timing requirements among different signals of the NFC at module level, for normal

mode, and Table 31 lists the timing parameters.

NFCLE

NF2

NF1

NF3

NF4

NFCE

NF5

NFWE

NFALE

NF6

NF7

NF8

NF9

Command

NFIO[7:0]

Figure 21. Command Latch Cycle Timing DIagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

NFCLE

NF1

NF3

NF4

NFCE

NF10

NF11

NF5

NF8

NFWE

NFALE

NF7

NF9

NF6

NFIO[7:0]

Address

Figure 22. Address Latch Cycle Timing DIagram

NFCLE

NFCE

NF1

NF3

NF10

NF11

NF5

NFWE

NFALE

NF7

NF6

NF8

NF9

NFIO[15:0]

Data to NF

Figure 23. Write Data Latch Cycle Timing DIagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

NFCLE

NFCE

NF14

NF13

NF15

NFRE

NFRB

NF17

NF16

NF12

NFIO[15:0]

Data from NF

Figure 24. Read Data Latch Cycle Timing DIagram

Table 31. NFC Target Timing Parameters

Relationship to NFC clock

Period (T)

Parameter

Symbol

Unit

Max

Min

Max

Min

NF1 NFCLE Setup Time

NF2 NFCLE Hold Time

NF3 NFCE Setup Time

NF4 NFCE Hold Time

NF5 NF_WP Pulse Width

NF6 NFALE Setup Time

NF7 NFALE Hold Time

NF8 Data Setup Time

NF9 Data Hold Time

tCLS

tCLH

tCS

–

tCH

tWP

tALS

tALH

tDS

tDH

NF10 Write Cycle Time

NF11 NFWE Hold Time

NF12 Ready to NFRE Low

NF13 NFRE Pulse Width

NF14 READ Cycle Time

NF15 NFRE High Hold Time

NF16 Data Setup on READ

NF17 Data Hold on READ

tWC

tWH

tRR

1.5T

0.5T

–

270

67.5

tRP

tRC

tREH

tDSR

tDHR

22.5

–

NOTE

High is defined as 80% of signal value and low is defined as 20% of signal

value.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

NOTE

Timing for HCLK is 133 MHz and internal LCLK (flash clock) is 22.5 MHz

(45 ns). All timings are listed according to this LCLK frequency (multiples

of LCLK phases) except NF16, which is not LCLK related.

4.3.9.1.2

One-Cycle NFC Mode

Figure 25, Figure 26, Figure 27, and Figure 28 depict the relative timing requirements among different

signals of the NFC at module level for one-cycle mode, and Table 32 lists the timing parameters.

NFCLE

NF2_one

NF4_one

NF1_one

NF3_one

NFCE

NF5_one

NFWE

NFALE

NF6_one

NF7_one

NF8_one

command

NF9_one

NFIO[7:0]

Figure 25. Command Latch Cycle Timing DIagram—One Flash Clock Cycle

NFCLE

NF1_one

NF4_one

NF3_one

NFCE

NF10_one

NF11_one

NF5_one

NFWE

NFALE

NF7_one

NF9_one

NF6_one

NF8_one

Address

NFIO[7:0]

Figure 26. Address Latch Cycle Timing DIagram—One Flash Clock Cycle

i.MX31/i.MX31L Advance Information, Rev. 1.4

Preliminary

Freescale Semiconductor

Electrical Characteristics

NFCLE

NFCE

NF1_one

NF3_one

NF10_one

NF11_one

NF5_one

NFWE

NFALE

NF7_one

NF6_one

NF8_one

NF9_one

NFIO[15:0]

Data to NF

Figure 27. Write Data Latch Cycle Timing DIagram—One Flash Clock Cycle

NFCLE

NFCE

NF14_one

NF15_one

NF13_one

NFRE

NF17_one

NF16_one

NFRB

NF12_one

NFIO[15:0]

Data from NF

Figure 28. Read Data Latch Cycle Timing DIagram—One Flash Clock Cycle

Table 32. NFC Target Timing Parameters—One Flash Clock Cycle

Parameter

Symbol

Min

Max

Unit

NF1_one NFCLE Setup Time

NF2_one NFCLE Hold Time

NF3_one NFCE Setup Time

NF4_one NFCE Hold Time

NF5_one NF_WP Pulse Width

tCLS

tCLH

tCS

–

tCH

tWP

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 32. NFC Target Timing Parameters—One Flash Clock Cycle (continued)

Parameter

Symbol

Min

Max

Unit

NF6_one NFALE Setup Time

NF7_one NFALE Hold Time

NF8_one Data Setup Time

NF9_one Data Hold Time

tALS

tALH

tDS

180

–

tDH

NF10_one Write Cycle Time

NF11_one NFWE Hold Time

NF12_one Ready to NFRE Low

NF13_one NFRE Pulse Width

NF14_one READ Cycle Time

NF15_one NFRE High Hold Time

NF16_one Data Setup on READ

NF17_one Data Hold on READ

tWC

tWH

tRR

tRP

tRC

tREH

tDSR

tDHR

NOTE

High is defined as 80% of signal value and low is defined as 20% of signal

value.

NOTE

Timing for HCLK is 133 MHz and internal LCLK (flash clock) is 33.25 MHz

(30 ns). All timings are listed according to this LCLK frequency.

4.3.9.2

Wireless External Interface Module (WEIM)

All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising

edge or falling edge according to corresponding assertion/negation control fields. Address always begins

related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according

to control register configuration. Output data begins related to BCLK rising edge except in muxed mode

where both rising and falling edge may be used according to control register configuration. Input data,

ECB and DTACK all captured according to BCLK rising edge time. Figure 29 depicts the timing of the

WEIM module, and Table 33 lists the timing parameters.

NOTE

ECB and DTACK signals mentioned in this section can be connected to one

input pad—ECB, although the WEIM design has those two signals as

individual inputs. In this case, this PAD will be connected to the 2 WEIM

inputs.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

WEIM Outputs Timing

WE22

WE23

WE21

BCLK (for rising edge timing)

BCLK (for falling edge timing)

...

WE1

WE2

Address

CS[x]

WE3

WE5

WE4

WE6

WE7

WE9

WE8

WE10

EB[x]

WE11

WE13

WE12

WE14

LBA

Output Data

WEIM Inputs timing

BCLK (for rising edge timing)

Input Data

WE16

WE15

WE17

WE18

WE20

ECB

DTACK

WE19

Figure 29. WEIM Bus Timing Diagram

Table 33. WEIM Bus Timing Parameters

1.8 V

Parameter

Unit

Max

Min

WE1 Clock fall to address valid

WE2 Clock rise/fall to address invalid

WE3 Clock rise/fall to CS[x] valid

–2

–3

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 33. WEIM Bus Timing Parameters (continued)

1.8 V

Parameter

Unit

Min

Max

WE4 Clock rise/fall to CS[x] invalid

WE5 Clock rise/fall to RW Valid

–3

–3.5

–2

–7

–2

–7

–2

–7

–2

–7

–

WE6 Clock rise/fall to RW Invalid

WE7 Clock rise/fall to OE Valid

WE8 Clock rise/fall to OE Invalid

WE9 Clock rise/fall to EB[x] Valid

WE10 Clock rise/fall to EB[x] Invalid

WE11 Clock rise/fall to LBA Valid

WE12 Clock rise/fall to LBA Invalid

WE13 Clock rise/fall to Output Data Valid

WE14 Clock rise to Output Data Invalid

WE15 Input Data Valid to Clock rise, FCE=0

WE16 Cloc/k rise to Input Data Invalid, FCE=0

WE15 Input Data Valid to Clock rise, FCE=1

WE16 Clock rise to Input Data Invalid, FCE=1

WE17 ECB setup time, FCE=0

WE18 ECB hold time, FCE=0

WE17 ECB setup time, FCE=1

WE18 ECB hold time, FCE=1

WE19 DTACK setup time¹

–

WE20 DTACK hold time

WE20 DTACK hold time (Level sensitive mode, EW=1

implies wsc < 111111)

WE21 BCLK High Level Width^{2, 3}

WE22 BCLK Low Level Width^{2, 3}

WE23 BCLK Cycle time²

–

Tcycle/

2-3

Tcycle/

2-3

Not required.

BCLK parameters are being measured from the 50% VDD.

The actual cycle time is derived from the AHB bus clock frequency.

NOTE

High is defined as 80% of signal value and low is defined as 20% of signal value.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

NOTE

Test conditions: pad voltage, 1.75 V-1.95 V; pad capacitance, 25 pF.

Recommended drive strength for all controls, address, and BCLK is Max drive.

Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, and Figure 35 depict some examples of

basic WEIM accesses to external memory devices with the timing parameters mentioned in

Table 33 for specific control parameter settings.

BCLK

WE2

WE1

WE3

Next Address

WE4

Last Valid Address

ADDR

CS[x]

WE11

WE12

WE8

LBA

WE7

WE9

WE10

WE16

EB[y]

WE15

DATA

BCLK

Figure 30. Asynchronous Memory Timing Diagram for Read Access—WSC=1

WE2

WE1

Last Valid Address

ADDR

CS[x]

Next Address

WE3

WE5

WE4

WE6

LBA

WE11

WE12

WE10

WE9

EB[y]

DATA

WE14

WE13

Figure 31. Asynchronous Memory Timing Diagram for Write Access—

WSC=1, EBWA=1, EBWN=1, LBN=1

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

BCLK

WE1

Last Valid Addr

WE3

WE2

Address V1

Address V2

ADDR

CS[x]

WE4

WE11

WE7

WE12

LBA

WE8

WE10

WE9

EB[y]

WE18

WE17

ECB

WE17

V1+2

WE16

WE15

Halfword

V2+2

Halfword

DATA

Halfword Halfword

WE15

Figure 32. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses—

WSC=2, SYNC=1, DOL=0

BCLK

WE2

WE4

WE6

WE1

ADDR

Last Valid Addr

Address V1

WE3

CS[x]

WE5

WE12

WE11

LBA

WE10

WE9

EB[y]

WE18

ECB

WE17

WE14

WE13

V1+4 V1+8 V1+12

DATA

WE13

Figure 33. Synchronous Memory TIming Diagram for Burst Write Access—

BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

BCLK

WE1

WE2

WE14

WE4

WE6

ADDR/

M_DATA

Last Valid Addr

Write Data

Address V1

WE13

WE3

CS[x]

WE5

Write

WE11

WE12

LBA

WE9

WE10

EB[y]

Figure 34. Muxed A/D Mode Timing Diagram for Asynchronous Write Access—

WSC=7, LBA=1, LBN=1, LAH=1

BCLK

WE16

WE1

Last Valid Addr

WE3

WE2

ADDR/

M_DATA

Address V1

Read Data

WE15

CS[x]

WE4

WE11

WE12

LBA

WE7

WE8

WE9

WE10

EB[y]

Figure 35. Muxed A/D Mode Timing Diagram for Asynchronous Read Access—

WSC=7, LBA=1, LBN=1, LAH=1, OEA=7

4.3.9.3

SDRAM (DDR and SDR) Memory Controller

Figure 36, Figure 37, Figure 38, Figure 39, Figure 40, and Figure 41 depict the timings pertaining to the

SDRAMC module, which interfaces Mobile DDR or SDR SDRAM. Table 34, Table 35, Table 36,

Table 37, Table 38, and Table 39 list the timing parameters.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

SD1

SDCLK

SD2

SD4

SD3

SD5

SD4

RAS

SD5

SD4

CAS

SD4

SD5

SD6

SD7

ADDR

ROW/BA

COL/BA

SD10

SD8

SD9

Data

SD4

DQM

Note: CKE is high during the read/write cycle.

Figure 36. SDRAM Read Cycle Timing Diagram

Table 34. DDR/SDR SDRAM Read Cycle Timing Parameters

SD5

Parameter

SDRAM clock high-level width

Symbol

Min

Max

Unit

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD8

tCH

tCL

3.4

7.5

2.0

1.8

2.0

1.8

–

4.1

–

SDRAM clock low-level width

SDRAM clock cycle time

tCK

CS, RAS, CAS, WE, DQM, CKE setup time

CS, RAS, CAS, WE, DQM, CKE hold time

Address output delay time

tCMS

tCMH

tAS

–

Address output hold time

tAH

–

SDRAM access time

tAC

6.47

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 34. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)

Parameter

Symbol

Min

Max

Unit

SD9

Data out hold time¹

Active to read/write command period

tOH

tRC

1.5

–

SD10

clock

Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see

Table 38 and Table 39.

NOTE

SDR SDRAM CLK parameters are being measured from the 50%

point–that is, high is defined as 50% of signal value and low is defined as

50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.

NOTE

The timing parameters similar to the ones used in the regular SDRAM data

sheet. All output signals are driven by the ESDCTL at the negative edge of

SDCLK and the parameters are measured at maximum memory frequency.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

SD1

SDCLK

SD2

SD4

SD3

RAS

CAS

SD5

SD11

SD4

SD5

SD4

SD5

SD12

SD7

SD6

ADDR

ROW / BA

COL/BA

DATA

SD13

SD14

DQM

Figure 37. SDR SDRAM Write Cycle Timing Diagram

Table 35. SDR SDRAM Write Timing Parameters

Parameter

Symbol

Min

Max

Unit

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD11

SD12

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

tCH

tCL

3.4

7.5

2.0

1.8

2.0

1.8

4.1

–

tCK

CS, RAS, CAS, WE, DQM, CKE setup time

CS, RAS, CAS, WE, DQM, CKE hold time

Address setup time

tCMS

tCMH

tAS

–

Address hold time

tAH

–

Precharge cycle period¹

tRP

clock

Active to read/write command delay¹

tRCD

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 35. SDR SDRAM Write Timing Parameters (continued)

Parameter

Symbol

Min

Max

Unit

SD13

SD14

Data setup time

Data hold time

tDS

tDH

2.0

1.3

–

SD11 and SD12 are determined by SDRAM controller register settings.

NOTE

SDR SDRAM CLK parameters are being measured from the 50%

point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value.

SD1

SDCLK

SD2

SD3

RAS

CAS

SD11

SD10

ADDR

SD7

SD6

ROW/BA

DQM

Figure 38. SDRAM Refresh Timing Diagram

Table 36. SDRAM Refresh Timing Parameters

Parameter

Symbol

Min

Max

Unit

SD1

SD2

SDRAM clock high-level width

SDRAM clock low-level width

tCH

tCL

3.4

4.1

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 36. SDRAM Refresh Timing Parameters (continued)

Parameter

SDRAM clock cycle time

Symbol

Min

Max

Unit

SD3

SD6

tCK

tAS

tAH

tRP

tRC

7.5

1.8

–

Address setup time

Address hold time

SD7

–

SD10

SD11

Precharge cycle period¹

clock

Auto precharge command period¹

SD10 and SD11 are determined by SDRAM controller register settings.

NOTE

SDR SDRAM CLK parameters are being measured from the 50%

point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value.

SDCLK

RAS

CAS

ADDR

CKE

SD16

Don’t care

Figure 39. SDRAM Self-Refresh Cycle Timing Diagram

NOTE

The clock will continue to run unless both CKEs are low. Then the clock will

be stopped in low state.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 37. SDRAM Self-Refresh Cycle Timing Parameters

Parameter

Symbol

Min

Max

Unit

SD16

CKE output delay time

tCKS

1.8

–

SDCLK

SD20

SD19

DQS (output)

DQ (output)

SD18

Data

SD17

Data

SD17

SD18

Data

DQM (output)

SD17

SD18

Figure 40. Mobile DDR SDRAM Write Cycle Timing Diagram

Table 38. Mobile DDR SDRAM Write Cycle Timing Parameters

Parameter

Symbol

Min

Max

Unit

SD17

SD18

SD19

DQ & DQM setup time to DQS

DQ & DQM hold time to DQS

tDS

tDH

1.2

1.8

–

Write cycle DQS falling edge to SDCLK output

delay time.

tDSS

SD20

Write cycle DQS falling edge to SDCLK output hold

time.

tDSH

1.8

–

NOTE

SDRAM CLK and DQS related parameters are being measured from the

50% point—that is, high is defined as 50% of signal value and low is defined

as 50% of signal value.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

Electrical Characteristics

SDCLK

SD23

DQS (input)

DQ (input)

SD22

Data

SD21

Data

Figure 41. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram

Table 39. Mobile DDR SDRAM Read Cycle Timing Parameters

Parameter

Symbol

Min

Max

Unit

SD21

DQS - DQ Skew (defines the Data valid window in

read cycles related to DQS).

tDQSQ

–

.85

SD22

SD23

DQS DQ HOLD time from DQS

tQH

2.3

–

DQS output access time from SDCLK posedge

tDQSCK

6.7

NOTE

SDRAM CLK and DQS related parameters are being measured from the

50% point—that is, high is defined as 50% of signal value and low is defined

as 50% of signal value.

4.3.10 ETM Electrical Specifications

ETM is an ARM protocol. There are no inherent restrictions on operating frequency, other than ASIC pad

technology and TPA limitations. ASIC designers must provide a TRACECLK as symmetrical as possible,

and with set-up and hold times as large as possible. TPA designers must conversely be able to support a

TRACECLK as asymmetrical as possible, and require set up and hold times as short as possible. The

timing specifications in this section are given as a guide for a TPA that supports TRACECLK frequencies

up to around 100 MHz.

NOTE

Actual processor clock frequencies vary according to application

requirements and the silicon process technologies used. The maximum

operating clock frequencies attained by ARM devices increases over time as

a result.

If a designer adheres to the timing described here, he or she can use any ARM-approved TPA. Figure 42

depicts the TRACECLK timings of ETM, and Table 40 lists the timing parameters.

i.MX31/i.MX31L Advance Information, Rev. 1.4

100

Freescale Semiconductor

Preliminary

Electrical Characteristics

Figure 42. ETM TRACECLK Timing Diagram

Table 40. ETM TRACECLK Timing Parameters

Parameter

Min

Max

Unit

T_cyc

Clock period

Frequency

dependent

–

T_wl

Low pulse width

High pulse width

–

T_wh

Clock and data rise time

Clock and data fall time

T_f

Figure 43 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and

Table 41 lists the timing parameters.

Figure 43. Trace Data Timing Diagram

Table 41. ETM Trace Data Timing Parameters

Parameter

Min

Max

Unit

T_s

T_h

Data setup

Data hold

–

4.3.10.1 Half-Rate Clocking Mode

When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling

edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 43.

4.3.11 FIR Electrical Specifications

FIR implements asynchronous infrared protocols (FIR, MIR) that are defined by IrDA (Infrared Data

Association). Refer to http://www.IrDA.org for details on FIR and MIR protocols.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

101

Preliminary

Electrical Characteristics

4.3.12 Fusebox Electrical Specifications

Table 42. Fusebox Supply Current Parameters

Description Symbol Minimum Typical Maximum Units

Ref.

Num

eFuse Program Current.¹

Current to program one eFuse bit

efuse_pgm = 3.0V

I_program

–

eFuse Read Current²

I_read

–

Current to read an 8-bit eFuse word

vdd_fusebox = 1.875V

The current I_programis during program time (t_program).

The current I_readis present for approximately 50nS of the read access to the 8 bit word

Table 43. Fusebox Timing Characteristics

Ref.

Description

Symbol

Minimum

Typical

Maximum

Units

µs

Num

Program time for eFuse¹

t_program

125

–

The program length is defined by the value defined in the epm_pgm_length[2:0] bits of the IIM module. The value to program

is based on a 32 kHz clock source (4 * 1/32 kHz = 125 µs)

4.3.13 I2C Electrical Specifications

This section describes the electrical information of the I2C Module.

4.3.13.1 I2C Module Timing

Figure 44 depicts the timing of I2C module. Table 44 lists the I2C module timing parameters where the

I/O supply is 2.7 V. 1

IC11

IC9

IC10

I2DAT

I2CLK

IC7

IC4

IC2

IC3

IC8

IC10

IC6

IC11

STOP

START

IC5

IC1

Figure 44. I2C Bus Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

102

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 44. I2C Module Timing Parameters—I2C Pin I/O Supply=2.7 V

Standard Mode Fast Mode

Parameter

Unit

Min

Max

Min

Max

IC1 I2CLK cycle time

4.0

0¹

–

2.5

0.6

–

µs

IC2 Hold time (repeated) START condition

IC3 Set-up time for STOP condition

IC4 Data hold time

–

0.6

–

3.45²

–

0¹

0.9²

–

IC5 HIGH Period of I2CLK Clock

4.0

4.7

250

4.7

–

0.6

IC6 LOW Period of the I2CLK Clock

IC7 Set-up time for a repeated START condition

IC8 Data set-up time

–

1.3

–

0.6

–

100³

1.3

–

IC9 Bus free time between a STOP and START condition

IC10 Rise time of both I2DAT and I2CLK signals

IC11 Fall time of both I2DAT and I2CLK signals

IC12 Capacitive load for each bus line (C_b)

–

1000

300

400

20+0.1C_b

–

300

400

–

A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the

falling edge of I2CLK.

The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.

A Fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.

If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time

(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)

before the I2CLK line is released.

C_b= total capacitance of one bus line in pF.

4.3.14 IPU—Sensor Interfaces

4.3.14.1 Supported Sensors

Table 45 lists the supported camera sensors by vendor and model.

Table 45. Supported Camera Sensors

Vendor

Model

Conexant

Agilant

CX11646, CX20490, CX20450

HDCP-2010, ADCS-1021, ADCS-1021

TC90A70

Toshiba

ICMedia

iMagic

ICM202A, ICM102

IM8801

Transchip

TC5600, TC5600J, TC5640, TC5700, TC6000

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

103

Preliminary

Electrical Characteristics

Vendor

Table 45. Supported Camera Sensors (continued)

Model

Fujitsu

MB86S02A

Micron

MI-SOC-0133

Matsushita

STMicro

OmniVision

Sharp

MN39980

W6411, W6500, W6501, W6600, W6552, STV0974

OV7620, OV6630

LZ0P3714 (CCD)

Motorola

MC30300 (Python), SCM20014, SCM20114, SCM22114, SCM20027

National Semiconductor

LM9618

4.3.14.2 Functional Description

There are three timing modes supported by the IPU.

4.3.14.2.1 Pseudo BT.656 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use

an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing

syntax is defined by the BT.656 standard.

This operation mode follows the recommendations of ITU BT.656 specifications. The only control signal

used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An

active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in

between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus

recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.

4.3.14.2.2 Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See

Figure 45.

i.MX31/i.MX31L Advance Information, Rev. 1.4

104

Freescale Semiconductor

Preliminary

Electrical Characteristics

Active Line

Start of Frame

nth frame

n+1th frame

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

SENSB_DATA[9:0]

invalid

1st byte

Figure 45. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the

corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid

as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.

SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops

receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the

SENSB_VSYNC timing repeats.

4.3.14.2.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.3.14.2.2, “Gated Clock Mode” on

page 104), except for the SENSB_HSYNC signal, which is not used. See Figure 46. All incoming pixel

clocks are valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is

inactive (states low) until valid data is going to be transmitted over the bus.

Start of Frame

nth frame

n+1th frame

SENSB_VSYNC

SENSB_PIX_CLK

invalid

SENSB_DATA[7:0]

1st byte

Figure 46. Non-Gated Clock Mode Timing Diagram

The timing described in Figure 46 is that of a Motorola sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;

active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

105

Preliminary

Electrical Characteristics

4.3.14.3 Electrical Characteristics

Figure 47 depicts the sensor interface timing, and Table 46 lists the timing parameters.

1/IP1

SENSB_MCLK

(Sensor Input)

SENSB_PIX_CLK

(Sensor Output)

1/IP4

IP2

IP3

SENSB_DATA,

SENSB_VSYNC,

SENSB_HSYNC

Figure 47. Sensor Interface Timing Diagram

Table 46. Sensor Interface Timing Parameters

Parameter

Symbol

Min.

Max.

Units

IP1

IP2

IP3

IP4

Sensor input clock frequency

Data and control setup time

Fmck

Tsu

0.01

133

–

MHz

Data and control holdup time

Sensor output (pixel) clock frequency

Thd

–

Fpck

0.01

133

MHz

4.3.15 IPU—Display Interfaces

4.3.15.1 Supported Displays

Table 47 lists the supported displays by type, vendor, and model.

Table 47. Supported Displays

Type

Vendor

Model

LQ035Q7 DB02, LM019LC1Sxx

TFT displays

(memory-less)

Sharp (HR-TFT Super

Mobile LCD family)

Samsung (QSIF and

QVGA TFT modules for

mobile phones)

LTS180S1-HF1, LTS180S3-HF1, LTS350Q1-PE1,

LTS350Q1-PD1, LTS220Q1-HE1

Toshiba (LTM series)

LTM022P806, LTM04C380K,

LTM018A02A, LTM020P332, LTM021P337, LTM019P334,

LTM022A783, LTM022A05ZZ

i.MX31/i.MX31L Advance Information, Rev. 1.4

Preliminary

106

Freescale Semiconductor

Electrical Characteristics

Table 47. Supported Displays (continued)

Vendor

Type

Model

Display controllers

Epson

S1D15xxx series, S1D19xxx series, S1D13713, S1D13715

SSD1301 (OLED), SSD1828 (LDCD)

HD66766, HD66772

Solomon Systech

Hitachi

ATI

W2300

Smart display modules

Epson

L1F10043 T, L1F10044 T, L1F10045 T, L2D22002, L2D20014,

L2F50032, L2D25001 T

Hitachi

120 160 65K/4096 C-STN (#3284 LTD-1398-2) based on HD 66766

controller

Densitron Europe LTD

All displays with MPU 80/68K series interface and serial peripheral

interface

Sharp

LM019LC1Sxx

ACX506AKM

ADV7174/7179

CS49xx series

FS453/4

Sony

Digital video encoders

(for TV)

Analog Devices

Crystal (Cirrus Logic)

Focus

4.3.15.2 Synchronous Interfaces

4.3.15.2.1 Interface to Active Matrix TFT LCD Panels, Functional Description

Figure 48 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure

signals are shown with negative polarity. The sequence of events for active matrix interface timing is:

•

DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is

selected). In active mode, DISPB_D3_CLK runs continuously. This signal frequency could be

from 5 to 10 MHz depending on the panel type.

•

DISPB_D3_HSYNC causes the panel to start a new line.

DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one

HSYNC pulse.

•

DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the

data to be shifted onto the display. When disabled, the data is invalid and the trace is off.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

107

Preliminary

Electrical Characteristics

DISPB_D3_VSYNC

DISPB_D3_HSYNC

LINE 1

LINE 2

LINE 3

LINE 4

LINE n-1

LINE n

DISPB_D3_HSYNC

DISPB_D3_DRDY

m-1

DISPB_D3_CLK

DISPB_D3_DATA

Figure 48. Interface Timing Diagram for TFT (Active Matrix) Panels

4.3.15.2.2 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics

Figure 49 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and

the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity

of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC

and DISPB_D3_DRDY signals.

IP7

IP6

IP9

IP10

IP8

IP5

Start of line

DISPB_D3_CLK

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_DATA

Figure 49. TFT Panels Timing Diagram—Horizontal Sync Pulse

Figure 50 depicts the vertical timing (timing of one frame). All figure parameters shown are

programmable.

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Freescale Semiconductor

Preliminary

Electrical Characteristics

End of frame

Start of frame

IP13

DISPB_D3_VSYNC

DISPB_D3_HSYNC

DISPB_D3_DRDY

IP15

IP11

IP14

IP12

Figure 50. TFT Panels Timing Diagram—Vertical Sync Pulse

Table 48 shows timing parameters of signals presented in Figure 49 and Figure 50.

Table 48. Synchronous Display Interface Timing Parameters—Pixel Level

Parameter

Symbol

Value

Units

IP5

IP6

Display interface clock period

Display pixel clock period

Screen width

Tdicp

Tdpcp

Tsw

(¹)

(DISP3_IF_CLK_CNT_D+1) * Tdicp

(SCREEN_WIDTH+1) * Tdpcp

(H_SYNC_WIDTH+1) * Tdpcp

BGXP * Tdpcp

IP7

IP8

HSYNC width

Thsw

Thbi1

Thbi2

Tsh

IP9

Horizontal blank interval 1

Horizontal blank interval 2

Screen height

IP10

IP12

IP13

(SCREEN_WIDTH - BGXP - FW) * Tdpcp

(SCREEN_HEIGHT+1) * Tsw

VSYNC width

Tvsw

if V_SYNC_WIDTH_L = 0 than

(V_SYNC_WIDTH+1) * Tdpcp

else

(V_SYNC_WIDTH+1) * Tsw

IP14

IP15

Vertical blank interval 1

Vertical blank interval 2

Tvbi1

Tvbi2

BGYP * Tsw

(SCREEN_HEIGHT - BGYP - FH) * Tsw

Display interface clock period immediate value.

⎧

⎪

⎨

⎪

⎩

DISP3_IF_CLK_PER_WR

-----------------------------------------------------------------

DISP3_IF_CLK_PER_WR

-----------------------------------------------------------------

⋅

for integer

HSP_CLK

HSP_CLK_PERIOD

Tdicp =

DISP3_IF_CLK_PER_WR

⎛

⎞

-----------------------------------------------------------------

⋅ floor

+ 0.5 0.5 ,

for fractional

HSP_CLK ⎝

⎠

HSP_CLK_PERIOD

Display interface clock period average value.

DISP3_IF_CLK_PER_WR

-----------------------------------------------------------------

⋅

Tdicp = T

HSP_CLK

HSP_CLK_PERIOD

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

109

Preliminary

Electrical Characteristics

The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and

V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF,

SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA

channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters

are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC

Registers.

Figure 51 depicts the synchronous display interface timing for access level, and Table 49 lists the timing

parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the

DI_DISP3_TIME_CONF Register.

IP20

DISPB_D3_VSYNC

DISPB_D3_HSYNC

DISPB_D3_DRDY

other controls

DISPB_D3_CLK

IP18

IP16

IP17

IP19

DISPB_DATA

Figure 51. Synchronous Display Interface Timing Diagram—Access Level

Table 49. Synchronous Display Interface Timing Parameters—Access Level

Parameter

Symbol

Min

Typ¹

Max

Units

IP16 Display interface clock

low time

Tckl

Tdicd-Tdicu-1.5

Tdicd²-Tdicu³

Tdicd-Tdicu+1.5

IP17 Display interface clock

high time

Tckh

Tdicp-Tdicd+Tdicu-1.5 Tdicp-Tdicd+Tdicu

Tdicp-Tdicd+Tdicu+1.5

–

IP18 Data setup time

IP19 Data holdup time

Tdsu

Tdhd

Tcsu

Tdicd-3.5

Tdicu

Tdicp-Tdicd-3.5

Tdicd-3.5

Tdicp-Tdicu

Tdicu

IP20 Control signals setup

time to display interface

clock

¹The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

Display interface clock down time

2 ⋅ DISP3_IF_CLK_DOWN_WR

--------------------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicd =

HSP_CLK_PERIOD

Display interface clock up time

2 ⋅ DISP3_IF_CLK_UP_WR

---------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicu =

HSP_CLK_PERIOD

where CEIL(X) rounds the elements of X to the nearest integers towards infinity.

i.MX31/i.MX31L Advance Information, Rev. 1.4

110

Freescale Semiconductor

Preliminary

Electrical Characteristics

4.3.15.3 Interface to Sharp HR-TFT Panels

Figure 52 depicts the Sharp HR-TFT panel interface timing, and Table 50 lists the timing parameters. The

CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,

REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and

SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to

Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics” on page 108.

The timing images correspond to straight polarity of the Sharp signals.

Horizontal timing

DISPB_D3_CLK

D1 D2

D320

DISPB_D3_DATA

DISPB_D3_SPL

IP21

1 DISPB_D3_CLK period

DISPB_D3_HSYNC

IP23

IP22

DISPB_D3_CLS

DISPB_D3_PS

IP24

IP25

IP26

DISPB_D3_REV

Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.

SPL pulse width is fixed and aligned to the first data of the line.

REV toggles every HSYNC period.

Figure 52. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level

Table 50. Sharp Synchronous Display Interface Timing Parameters—Pixel Level

Parameter

SPL rise time

Symbol

Value

Units

IP21

IP22

IP23

IP24

Tsplr

Tclsr

Tclsf

Tpsf

(BGXP - 1) * Tdpcp

CLS rise time

CLS_RISE_DELAY * Tdpcp

CLS_FALL_DELAY * Tdpcp

PS_FALL_DELAY * Tdpcp

CLS fall time

CLS rise and PS fall time

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

111

Preliminary

Electrical Characteristics

Table 50. Sharp Synchronous Display Interface Timing Parameters—Pixel Level (continued)

Parameter

Symbol

Value

Units

IP25

IP26

PS rise time

REV toggle time

Tpsr

Trev

PS_RISE_DELAY * Tdpcp

REV_TOGGLE_DELAY * Tdpcp

4.3.15.4 Synchronous Interface to Dual-Port Smart Displays

Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are

identical to parameters of the synchronous interface. See Section 4.3.15.2.2, “Interface to Active Matrix

TFT LCD Panels, Electrical Characteristics” on page 108.

4.3.15.4.1 Interface to a TV Encoder, Functional Description

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits

D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 53 depicts the

interface timing,

•

The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%).

The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.

The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It

remains low for a single clock cycle.

•

The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC

signal. It remains low for at least one clock cycle.

— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC

and DISPB_D3_HSYNC coincide.

— At a transition to an even field (of the same frame), they do not coincide.

•

The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC

signal being high.

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112

Freescale Semiconductor

Preliminary

Electrical Characteristics

DISPB_D3_CLK

DISPB_D3_HSYNC

DISPB_D3_VSYNC

DISPB_D3_DRDY

DISPB_DATA

Pixel Data Timing

523

524

525

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field

262 263

Odd Field

268 269

261

264

265

266

267

273

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field

Odd Field

Line and Field Timing - NTSC

621

622

623

624

625

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field

Odd Field

315

308

309

310

311

312

313

314

316

336

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field

Odd Field

Line and Field Timing - PAL

Figure 53. TV Encoder Interface Timing Diagram

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Freescale Semiconductor

113

Preliminary

Electrical Characteristics

4.3.15.4.2 Interface to a TV Encoder, Electrical Characteristics

The timing characteristics of the TV encoder interface are identical to the synchronous display

characteristics. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical

Characteristics” on page 108.

4.3.15.5 Asynchronous Interfaces

4.3.15.5.1 Parallel Interfaces, Functional Description

The IPU supports the following asynchronous parallel interfaces:

•

System 80 interface

— Type 1 (sampling with the chip select signal) with and without byte enable signals.

— Type 2 (sampling with the read and write signals) with and without byte enable signals.

System 68k interface

•

— Type 1 (sampling with the chip select signal) with or without byte enable signals.

— Type 2 (sampling with the read and write signals) with or without byte enable signals.

For each of four system interfaces, there are three burst modes:

1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters

of the IDMAC (when data is transferred from the system memory) of by the HBURST signal (when

the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type

1 interfaces, data is sampled by the CS signal and other control signals changes only when transfer

direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals

(system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during the whole

burst.

2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the

DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are

changed simultaneously with data when the bus state (read, write or wait) is altered. The CS

signals and other controls move to non-active state after burst has been completed.

3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The

data is sampled with CS or other controls according the interface type as described above. All

controls (including CS) become non-active for one display interface clock after each access. This

mode corresponds to the ATI single access mode.

Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 54,

Figure 55, Figure 56, and Figure 57. These timing images correspond to active-low DISPB_D#_CS,

DISPB_D#_WR and DISPB_D#_RD signals.

Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the

HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to

different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.

i.MX31/i.MX31L Advance Information, Rev. 1.4

114

Freescale Semiconductor

Preliminary

Electrical Characteristics

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by CS signal

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 54. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

Preliminary

Freescale Semiconductor

115

Electrical Characteristics

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by WR/RD signals

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 55. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

116

Freescale Semiconductor

Preliminary

Electrical Characteristics

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by CS signal

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 56. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

Preliminary

Freescale Semiconductor

117

Electrical Characteristics

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by ENABLE signal

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 57. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram

Display read operation can be performed with wait states when each read access takes up to 4 display

interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the

DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 Registers.

Figure 58 shows timing of the parallel interface with read wait states.

i.MX31/i.MX31L Advance Information, Rev. 1.4

118

Freescale Semiconductor

Preliminary

Electrical Characteristics

WRITE OPERATION

DISP0_RD_WAIT_ST=00

READ OPERATION

DISPB_D#_CS

DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

DISP0_RD_WAIT_ST=01

DISPB_D#_CS

DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

DISP0_RD_WAIT_ST=10

DISPB_D#_CS

DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

Figure 58. Parallel Interface Timing Diagram—Read Wait States

4.3.15.5.2 Parallel Interfaces, Electrical Characteristics

Figure 59, Figure 61, Figure 60, and Figure 62 depict timing of asynchronous parallel interfaces based on

the system 80 and system 68k interfaces. Table 51 lists the timing parameters at display access level. All

timing images are based on active low control signals (signals polarity is controlled via the

DI_DISP_SIG_POL Register).

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

119

Preliminary

Electrical Characteristics

IP28, IP27

DISPB_PAR_RS

DISPB_RD (READ_L)

DISPB_DATA[17]

(READ_H)

IP35, IP33

IP36, IP34

IP32, IP30

DISPB_D#_CS

DISPB_WR (WRITE_L)

DISPB_DATA[16]

(WRITE_H)

IP31, IP29

read point

IP38

IP37

DISPB_DATA

(Input)

Read Data

IP40

IP39

DISPB_DATA

(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 59. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

Preliminary

120

Freescale Semiconductor

Electrical Characteristics

IP28, IP27

DISPB_PAR_RS

DISPB_D#_CS

IP35, IP33

IP36, IP34

DISPB_RD (READ_L)

DISPB_DATA[17]

(READ_H)

DISPB_WR (WRITE_L)

DISPB_DATA[16]

(WRITE_H)

IP31, IP29

IP32, IP30

read point

IP38

IP37

DISPB_DATA

(Input)

Read Data

IP39

IP40

DISPB_DATA

(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 60. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

Preliminary

Freescale Semiconductor

121

Electrical Characteristics

IP28, IP27

DISPB_PAR_RS

DISPB_RD (ENABLE_L)

DISPB_DATA[17]

(ENABLE_H)

IP35,IP33

IP36, IP34

DISPB_D#_CS

DISPB_WR

(READ/WRITE)

IP31, IP29

IP32, IP30

read point

IP38

IP37

DISPB_DATA

(Input)

Read Data

IP39

IP40

DISPB_DATA

(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 61. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

Preliminary

122

Freescale Semiconductor

Electrical Characteristics

IP28, IP27

DISPB_PAR_RS

DISPB_D#_CS

IP35,IP33

IP36, IP34

DISPB_RD (ENABLE_L)

DISPB_DATA[17]

(ENABLE_H)

DISPB_WR

(READ/WRITE)

IP32, IP30

IP31, IP29

read point

IP38

IP37

DISPB_DATA

(Input)

Read Data

IP39

IP40

DISPB_DATA

(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 62. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram

Table 51. Asynchronous Parallel Interface Timing Parameters—Access Level

Parameter

Symbol

Min.

Typ.¹

Tdicpr²

Tdicpw³

Max.

Tdicpr+1.5

Units

IP27 Read system cycle time

IP28 Write system cycle time

IP29 Read low pulse width

IP30 Read high pulse width

Tcycr Tdicpr-1.5

Tcycw Tdicpw-1.5

Tdicpw+1.5

Trl

Tdicdr-Tdicur-1.5

Tdicdr⁴-Tdicur⁵

Tdicdr-Tdicur+1.5

Tdicpr-Tdicdr+Tdicur+1.5

Trh

Tdicpr-Tdicdr+Tdicur-1.5 Tdicpr-Tdicdr+

Tdicur

IP31 Write low pulse width

IP32 Write high pulse width

Twl

Tdicdw-Tdicuw-1.5

Tdicdw⁶-Tdicuw⁷Tdicdw-Tdicuw+1.5

Twh

Tdicpw-Tdicdw+

Tdicuw-1.5

Tdicpw-Tdicdw+ Tdicpw-Tdicdw+

Tdicuw

Tdicuw+1.5

IP33 Controls setup time for read

IP34 Controls hold time for read

Tdcsr Tdicur-1.5

Tdicur

–

Tdchr Tdicpr-Tdicdr-1.5

Tdicpr-Tdicdr

Tdicuw

IP35 Controls setup time for write Tdcsw Tdicuw-1.5

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

123

Preliminary

Electrical Characteristics

Table 51. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)

Parameter

Symbol

Min.

Typ.¹

Max.

Units

IP36 Controls hold time for write

IP37 Slave device data delay⁸

IP38 Slave device data hold time⁸

IP39 Write data setup time

IP40 Write data hold time

IP41 Read period²

IP42 Write period³

IP43 Read down time⁴

IP44 Read up time⁵

Tdchw Tdicpw-Tdicdw-1.5

Tdicpw-Tdicdw

–

Tdrp⁹-Tlbd¹⁰-Tdicur-1.5

Tdicpr-Tdicdr-1.5

–

Tracc

Troh

Tds

Tdrp-Tlbd-Tdicdr+1.5

Tdicdw-1.5

–

Tdicdw

Tdicpw-Tdicdw

Tdicpr

Tdh

Tdicpw-Tdicdw-1.5

–

Tdicpr Tdicpr-1.5

Tdicpw Tdicpw-1.5

Tdicdr Tdicdr-1.5

Tdicur Tdicur-1.5

Tdicdw Tdicdw-1.5

Tdicuw Tdicuw-1.5

Tdrp Tdrp-1.5

Tdicpr+1.5

Tdicpw+1.5

Tdicdr+1.5

Tdicur+1.5

Tdicdw+1.5

Tdicuw+1.5

Tdrp+1.5

Tdicpw

Tdicdr

Tdicur

IP45 Write down time⁶

IP46 Write up time⁷

IP47 Read time point⁹

Tdicdw

Tdicuw

Tdrp

¹The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

²Display interface clock period value for read:

DISP#_IF_CLK_PER_RD

HSP_CLK_PERIOD

----------------------------------------------------------------

⋅ ceil

Tdicpr = T

HSP_CLK

³Display interface clock period value for write:

DISP#_IF_CLK_PER_WR

HSP_CLK_PERIOD

-----------------------------------------------------------------

⋅ ceil

Tdicpw = T

HSP_CLK

⁴Display interface clock down time for read:

2 ⋅ DISP#_IF_CLK_DOWN_RD

-------------------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicdr =

HSP_CLK_PERIOD

⁵Display interface clock up time for read:

2 ⋅ DISP#_IF_CLK_UP_RD

--------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicur =

HSP_CLK_PERIOD

⁶Display interface clock down time for write:

2 ⋅ DISP#_IF_CLK_DOWN_WR

--------------------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicdw =

HSP_CLK_PERIOD

⁷Display interface clock up time for write:

2 ⋅ DISP#_IF_CLK_UP_WR

---------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicuw =

HSP_CLK_PERIOD

⁸This parameter is a requirement to the display connected to the IPU

⁹Data read point

DISP#_READ_EN

HSP_CLK_PERIOD

--------------------------------------------------

⋅ ceil

Tdrp = T

HSP_CLK

¹⁰Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a

chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.

i.MX31/i.MX31L Advance Information, Rev. 1.4

124

Freescale Semiconductor

Preliminary

Electrical Characteristics

The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD,

DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD,

DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the

DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.

4.3.15.5.3 Serial Interfaces, Functional Description

The IPU supports the following types of asynchronous serial interfaces:

•

3-wire (with bidirectional data line)

4-wire (with separate data input and output lines)

5-wire type 1 (with sampling RS by the serial clock)

5-wire type 2 (with sampling RS by the chip select signal)

Figure 63 depicts timing of the 3-wire serial interface. The timing images correspond to active-low

DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal.

For this interface, a bidirectional data line is used outside the chip. The IPU still uses separate input and

output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide

joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D

signal provided by the IPU.

Each data transfer can be preceded by an optional preamble with programmable length and contents. The

preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is

programmable. The RW bit can be disabled. The following data can consist of one word or of a whole

burst. The interface parameters are controlled by the DI_SER_DISP1_CONF and DI_SER_DISP2_CONF

Registers.

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

Input or output data

Preamble

Figure 63. 3-wire Serial Interface Timing Diagram

Figure 64 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output

data lines both inside and outside the chip.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

125

Preliminary

Electrical Characteristics

Write

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

Preamble

Output data

DISPB_SD_D

(Input)

Read

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

Preamble

DISPB_SD_D

(Input)

Input data

Figure 64. 4-wire Serial Interface Timing Diagram

Figure 65 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is

added. When a burst is transmitted within single active chip select interval, the RS can be changed at

boundaries of words.

i.MX31/i.MX31L Advance Information, Rev. 1.4

126

Freescale Semiconductor

Preliminary

Electrical Characteristics

Write

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

Preamble

Output data

DISPB_SD_D

(Input)

DISPB_SER_RS

Read

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

Preamble

DISPB_SD_D

(Input)

Input data

DISPB_SER_RS

Figure 65. 5-wire Serial Interface (Type 1) Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

127

Preliminary

Electrical Characteristics

Figure 66 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is

added. When a burst is transmitted within single active chip select interval, the RS can be changed at

boundaries of words.

Write

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

Output data

Preamble

DISPB_SD_D

(Input)

1 display IF

clock cycle

DISPB_SER_RS

Read

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

Preamble

DISPB_SD_D

(Input)

Input data

1 display IF

clock cycle

DISPB_SER_RS

Figure 66. 5-wire Serial Interface (Type 2) Timing Diagram

i.MX31/i.MX31L Advance Information, Rev. 1.4

128

Freescale Semiconductor

Preliminary

Electrical Characteristics

4.3.15.5.4 Serial Interfaces, Electrical Characteristics

Figure 67 depicts timing of the serial interface. Table 52 lists the timing parameters at display access level.

IP49, IP48

DISPB_SER_RS

IP56,IP54

IP57, IP55

DISPB_SD_D_CLK

IP51, IP53

IP50, IP52

read point

IP59

IP58

DISPB_DATA

(Input)

Read Data

IP60

IP61

DISPB_DATA

(Output)

IP67,IP65

IP47

IP64, IP66

IP62, IP63

Figure 67. Asynchronous Serial Interface Timing Diagram

Table 52. Asynchronous Serial Interface Timing Parameters—Access Level

Parameter

Symbol

Min.

Tdicpr-1.5

Typ.¹

Tdicpr²

Tdicpw³

Tdicdr⁴-Tdicur⁵

Max.

Tdicpr+1.5

Units

IP48 Read system cycle time

IP49 Write system cycle time

IP50 Read clock low pulse width

IP51 Read clock high pulse width

Tcycr

Tcycw Tdicpw-1.5

Tdicpw+1.5

Trl

Tdicdr-Tdicur-1.5

Tdicdr-Tdicur+1.5

Tdicpr-Tdicdr+Tdicur+1.5

Trh

Tdicpr-Tdicdr+Tdicur- Tdicpr-Tdicdr+

1.5

Tdicur

IP52 Write clock low pulse width

IP53 Write clock high pulse width

Twl

Tdicdw-Tdicuw-1.5

Tdicdw⁶-Tdicuw⁷

Tdicdw-Tdicuw+1.5

Twh

Tdicpw-Tdicdw+

Tdicuw-1.5

Tdicpw-Tdicdw+

Tdicuw

Tdicpw-Tdicdw+

Tdicuw+1.5

IP54 Controls setup time for read

IP55 Controls hold time for read

Tdcsr

Tdchr

Tdicur-1.5

Tdicur

–

Tdicpr-Tdicdr-1.5

Tdicpr-Tdicdr

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

129

Preliminary

Electrical Characteristics

Table 52. Asynchronous Serial Interface Timing Parameters—Access Level (continued)

Parameter

Symbol

Min.

Typ.¹

Max.

Units

IP56 Controls setup time for write

IP57 Controls hold time for write

IP58 Slave device data delay⁸

IP59 Slave device data hold time⁸

IP60 Write data setup time

IP61 Write data hold time

IP62 Read period²

IP63 Write period³

IP64 Read down time⁴

IP65 Read up time⁵

IP66 Write down time⁶

Tdcsw Tdicuw-1.5

Tdicuw

–

Tdchw Tdicpw-Tdicdw-1.5

Tdicpw-Tdicdw

–

Tracc

Troh

Tds

Tdrp⁹-Tlbd¹⁰-Tdicur-1.5

Tdicpr-Tdicdr-1.5

–

Tdrp-Tlbd-Tdicdr+1.5

Tdicdw-1.5

–

Tdicdw

Tdicpw-Tdicdw

Tdicpr

Tdh

Tdicpw-Tdicdw-1.5

–

Tdicpr Tdicpr-1.5

Tdicpw Tdicpw-1.5

Tdicdr Tdicdr-1.5

Tdicur Tdicur-1.5

Tdicdw Tdicdw-1.5

Tdicuw Tdicuw-1.5

Tdicpr+1.5

Tdicpw+1.5

Tdicdr+1.5

Tdicur+1.5

Tdicdw+1.5

Tdicuw+1.5

Tdrp+1.5

Tdicpw

Tdicdr

Tdicur

Tdicdw

Tdicuw

Tdrp

IP67 Write up time⁷

IP68 Read time point⁹

Tdrp

Tdrp-1.5

¹The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These

conditions may be chip specific.

²Display interface clock period value for read:

DISP#_IF_CLK_PER_RD

HSP_CLK_PERIOD

----------------------------------------------------------------

⋅ ceil

Tdicpr = T

HSP_CLK

³Display interface clock period value for write:

DISP#_IF_CLK_PER_WR

HSP_CLK_PERIOD

-----------------------------------------------------------------

⋅ ceil

Tdicpw = T

HSP_CLK

⁴Display interface clock down time for read:

2 ⋅ DISP#_IF_CLK_DOWN_RD

-------------------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicdr =

HSP_CLK_PERIOD

⁵Display interface clock up time for read:

2 ⋅ DISP#_IF_CLK_UP_RD

--------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicur =

HSP_CLK_PERIOD

⁶Display interface clock down time for write:

2 ⋅ DISP#_IF_CLK_DOWN_WR

--------------------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicdw =

HSP_CLK_PERIOD

⁷Display interface clock up time for write:

2 ⋅ DISP#_IF_CLK_UP_WR

---------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicuw =

HSP_CLK_PERIOD

⁸This parameter is a requirement to the display connected to the IPU.

⁹Data read point:

DISP#_READ_EN

HSP_CLK_PERIOD

--------------------------------------------------

⋅ ceil

Tdrp = T

HSP_CLK

¹⁰Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a

chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.

i.MX31/i.MX31L Advance Information, Rev. 1.4

130

Freescale Semiconductor

Preliminary

Electrical Characteristics

The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD,

DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD,

DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the

DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.

4.3.16 Memory Stick Host Controller (MSHC)

Figure 68, Figure 69, and Figure 70 depict the MSHC timings, and Table 53 and Table 54 list the timing

parameters.

tSCLKc

tSCLKwh

tSCLKwl

MSHC_SCLK

tSCLKr

tSCLKf

Figure 68. MSHC_CLK Timing Diagram

tSCLKc

MSHC_SCLK

tBSsu

tBSh

MSHC_BS

tDsu

tDh

MSHC_DATA

(Output)

tDd

MSHC_DATA

(Intput)

Figure 69. Transfer Operation Timing Diagram (Serial)

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

131

Preliminary

Electrical Characteristics

tSCLKc

MSHC_SCLK

MSHC_BS

tBSsu

tBSh

tDsu

tDh

MSHC_DATA

(Output)

tDd

MSHC_DATA

(Intput)

Figure 70. Transfer Operation Timing Diagram (Parallel)

NOTE

The Memory Stick Host Controller is designed to meet the timing

requirements per Sony's Memory Stick Pro Format Specifications document.

Tables in this section details the specifications requirements for parallel and

serial modes, and not the i.MX31/i.MX31L timing. The timing will be

provided once IC characterization is complete.

Table 53. Serial Interface Timing Parameters

Standards

Signal

Parameter

Symbol

Unit

Min.

Max.

Cycle

H pulse length

L pulse length

Rise time

tSCLKc

tSCLKwh

tSCLKwl

tSCLKr

tSCLKf

tBSsu

–

MSHC_SCLK

MSHC_BS

–

Fall time

–

Setup time

Hold time

tBSh

–

i.MX31/i.MX31L Advance Information, Rev. 1.4

132

Freescale Semiconductor

Preliminary

Electrical Characteristics

Table 53. Serial Interface Timing Parameters (continued)

Standards

Signal

Parameter

Symbol

Unit

Min.

Max.

Setup time

Hold time

tDsu

tDh

–

MSHC_DATA

Output delay time

tDd

Table 54. Parallel Interface Timing Parameters

Standards

Signal

Parameter

Symbol

Unit

Min

Max

Cycle

H pulse length

L pulse length

Rise time

tSCLKc

tSCLKwh

tSCLKwl

tSCLKr

tSCLKf

tBSsu

tBSh

–

MSHC_SCLK

–

Fall time

Setup time

Hold time

MSHC_BS

–

Setup time

Hold time

tDsu

–

MSHC_DATA

tDh

–

Output delay time

tDd

4.3.17 Personal Computer Memory Card International Association

(PCMCIA)

Figure 71 and Figure 72 depict the timings pertaining to the PCMCIA module, each of which is an

example of one clock of strobe set-up time and one clock of strobe hold time. Table 55 lists the timing

parameters.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

133

Preliminary

Electrical Characteristics

HCLK

HADDR

ADDR 1

CONTROL 1

CONTROL

HWDATA

HREADY

HRESP

DATA write 1

OKAY

ADDR 1

A[25:0]

DATA write 1

D[15:0]

WAIT

REG

OE/WE/IORD/IOWR

CE1/CE2

RD/WR

POE

PSHT

PSST

PSL

Figure 71. Write Accesses Timing Diagram—PSHT=1, PSST=1

i.MX31/i.MX31L Advance Information, Rev. 1.4

134

Freescale Semiconductor

Preliminary

Electrical Characteristics

HCLK

HADDR

ADDR 1

CONTROL 1

CONTROL

RWDATA

HREADY

HRESP

DATA read 1

OKAY

ADDR 1

A[25:0]

D[15:0]

WAIT

REG

OE/WE/IORD/IOWR

CE1/CE2

RD/WR

POE

PSHT

PSST

PSL

Figure 72. Read Accesses Timing Diagram—PSHT=1, PSST=1

Table 55. PCMCIA Write and Read Timing Parameters

Symbol

Parameter

Min

Max

Unit

PSHT

PSST

PSL

PCMCIA strobe hold time

clock

PCMCIA strobe set up time

PCMCIA strobe length

128

4.3.18 PWM Electrical Specifications

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

135

Preliminary

Electrical Characteristics

4.3.18.1 PWM Timing

Figure 73 depicts the timing of the PWM, and Table 56 lists the PWM timing characteristics.

System Clock

PWM Output

Figure 73. PWM Timing

Table 56. PWM Output Timing Parameters

Parameter

Min

Max

Unit

System CLK frequency¹

Clock high time

Clock low time

12.29

9.91

–

ipg_clk

–

MHz

–

Clock fall time

0.5

9.37

–

Clock rise time

–

Output delay time

Output setup time

–

8.71

CL of PWMO = 30 pF

i.MX31/i.MX31L Advance Information, Rev. 1.4

136

Freescale Semiconductor

Preliminary

Electrical Characteristics

4.3.19 SDHC Electrical Specifications

This section describes the electrical information of the SDHC.

4.3.19.1 SDHC Timing

Figure 74 depicts the timings of the SDHC, and Table 57 lists the timing parameters.

SD4

SD2

SD1

SD5

MMCx_CLK

SD3

SD7

SD6

MMCx_CMD

MMCx_DAT_0

MMCx_DAT_1

MMCx_DAT_2

MMCx_DAT_3

output from SDHC to card

SD8

MMCx_CMD

MMCx_DAT_0

input from card to SDHC MMCx_DAT_1

MMCx_DAT_2

MMCx_DAT_3

Figure 74. SDHC Timing Diagram

Table 57. SDHC Interface Timing Parameters

Parameter

Symbol

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency (Low Speed)

Clock Frequency (SD/SDIO Full Speed)

Clock Frequency (MMC Full Speed)

Clock Frequency (Identification Mode)

SD2 Clock Low Time

f_PP

400

–

kHz

MHz

kHz

f_PP

f_OD

100

–

t_WL

t_WH

t_TLH

t_THL

SD3 Clock High Time

–

SD4 Clock Rise Time

SD5 Clock Fall Time

–

SDHC output / Card Inputs CMD, DAT (Reference to CLK)

SD6 SDHC output / Card input Set-up Time

SD7 SDHC output / Card input Hold Time

t_ISU

t_IH

–

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

137

Preliminary

Electrical Characteristics

Table 57. SDHC Interface Timing Parameters (continued)

Parameter

Symbol

Min

Max

Unit

SDHC input / Card Outputs CMD, DAT (Reference to CLK)

SD8 Card Output Delay Time during Data Transfer

Mode

t_ODLY

Output Delay time during Identification Mode

t_ODLY

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz.

In normal data transfer mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz.

In card identification mode, card clock must be l100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V.

In identification mode, card output delay time should be less than 50 ns.

In data transfer mode, card output delay time should be less than 14 ns.

4.3.20 SIM Electrical Specifications

Each SIM card interface consist of a total of 12 pins (for 2 separate ports of 6 pins each. Mostly one port

with 5 pins is used).

The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides

a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the

TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins.

There is no timing relationship between the clock and the data. The clock that the SIM module provides

to the aim card will be used by the SIM card to recover the clock from the data much like a standard UART.

All six (or 5 in case bi directional TXRX is used) of the pins for each half of the SIM module are

asynchronous to each other.

There are no required timing relationships between the pads in normal mode, but there are some in two

specific cases: reset and power down sequences.

4.3.20.1 General Timing Requirements

Figure 75 shows the timing of the SIM module, and Figure 58 lists the timing parameters.

1/Sfreq

CLK

Sfall

Srise

Figure 75. SIM Clock Timing Diagram

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Preliminary

Electrical Characteristics

Table 58. SIM Timing Specification—High Drive Strength

Num

Description

Symbol

Min

Max

Unit

SIM Clock Frequency (CLK)¹

S_freq

0.01

5 (Some new cards

may reach 10)

MHz

SIM CLK Rise Time ²

S_rise

S_fall

–

SIM CLK Fall Time ³

SIM Input Transition Time (RX, SIMPD)

S_trans

50% duty cycle clock

With C = 50pF

4.3.20.2 Reset Sequence

4.3.20.2.1 Cards with Internal Reset

The sequence of reset for this kind of SIM Cards is as follows (see Figure 76):

•

After powerup, the clock signal is enabled on SGCLK (time T0)

After 200 clock cycles, RX must be high.

The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles

after T0.

SVEN

CLK

response

< 200 clock cycles

400 clock cycles <

< 40000 clock cycles

Figure 76. Internal-Reset Card Reset Sequence

4.3.20.2.2 Cards with Active Low Reset

The sequence of reset for this kind of card is as follows (see Figure 77):

1. After powerup, the clock signal is enabled on CLK (time T0)

2. After 200 clock cycles, RX must be high.

3. RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on

RX during those 40000 clock cycles)

4. RST is set High (time T1)

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Preliminary

Electrical Characteristics

5. RST must remain High for at least 40000 clock cycles after T1 and a response must be received

on RX between 400 and 40000 clock cycles after T1.

SVEN

RST

CLK

response

< 200 clock cycles

400 clock cycles <

< 40000 clock cycles

400000 clock cycles <

Figure 77. Active-Low-Reset Card Reset Sequence

4.3.20.3 Power Down Sequence

Power down sequence for SIM interface is as follows:

1. SIMPD port detects the removal of the SIM Card

2. RST goes Low

3. CLK goes Low

4. TX goes Low

5. VEN goes Low

Each of this steps is done in one CKIL period (usually 32 kHz). Power down can be started because of a

SIM Card removal detection or launched by the processor. Figure 78 and Table 59 show the usual timing

requirements for this sequence, with Fckil = CKIL frequency value.

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Preliminary

Electrical Characteristics

Spd2rst

SIMPD

RST

Srst2clk

CLK

Srst2dat

DATA_TX

Srst2ven

SVEN

Figure 78. SmartCard Interface Power Down AC Timing

Table 59. Timing Requirements for Power Down Sequence

Num

Description

Symbol

Min

Max

Unit

SIM reset to SIM clock stop

S_rst2clk

S_rst2dat

S_rst2ven

S_pd2rst

0.9*1/FCKIL

1.8*1/FCKIL

2.7*1/FCKIL

0.9*1/FCKIL

0.8

1.2

1.8

µs

SIM reset to SIM TX data low

SIM reset to SIM Voltage Enable Low

SIM Presence Detect to SIM reset Low

4.3.21 SJC Electrical Specifications

This section details the electrical characteristics for the SJC module. Figure 79 depicts the SJC test clock

input timing. Figure 80 depicts the SJC boundary scan timing, Figure 81 depicts the SJC test access port,

Figure 82 depicts the SJC TRST timing, and Table 60 lists the SJC timing parameters.

SJ1

SJ2

TCK

(Input)

VIH

VIL

SJ3

Figure 79. Test Clock Input Timing Diagram

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Preliminary

Electrical Characteristics

TCK

(Input)

VIH

VIL

SJ5

SJ4

Input Data Valid

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

SJ6

Data

Outputs

Data

Outputs

Output Data Valid

Figure 80. Boundary Scan (JTAG) Timing Diagram

TCK

(Input)

VIH

VIL

SJ8

SJ9

TDI

TMS

Input Data Valid

(Input)

SJ10

SJ11

SJ10

TDO

(Output)

Output Data Valid

TDO

(Output)

TDO

(Output)

Output Data Valid

Figure 81. Test Access Port Timing Diagram

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Preliminary

Electrical Characteristics

TCK

(Input)

SJ13

TRST

(Input)

SJ12

Figure 82. TRST Timing Diagram

Table 60. SJC Timing Parameters

Parameter¹

All Frequencies

Unit

Min

Max

SJ1 TCK cycle time

100.0

40.0

–

SJ2 TCK clock pulse width measured at V_M

SJ3 TCK rise and fall times

3.0

–

SJ4 Boundary scan input data set-up time

SJ5 Boundary scan input data hold time

SJ6 TCK low to output data valid

SJ7 TCK low to output high impedance

SJ8 TMS, TDI data set-up time

SJ9 TMS, TDI data hold time

10.0

50.0

–

40.0

–

10.0

50.0

–

SJ10 TCK low to TDO data valid

SJ11 TCK low to TDO high impedance

SJ12 TRST assert time

44.0

–

100.0

40.0

SJ13 TRST set-up time to TCK low

V_{M -}mid point voltage

–

4.3.22 SSI Electrical Specifications

This section describes the electrical information of SSI.

4.3.22.1 SSI Transmitter Timing with Internal Clock

Figure 83 depicts the SSI transmitter timing with internal clock, and Table 61 lists the timing parameters.

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Preliminary

Electrical Characteristics

SS1

SS5

SS4

SS3

SS2

AD1_TXC

(Output)

SS8

SS6

AD1_TXFS (bl)

(Output)

SS10

SS12

AD1_TXFS (wl)

(Output)

SS14

SS17

SS15

SS16

SS18

AD1_TXD

(Output)

SS43

SS42

SS19

AD1_RXD

(Input)

Note: SRXD Input in Synchronous mode only

SS1

SS3

SS5

SS4

SS2

DAM1_T_CLK

(Output)

SS8

SS6

DAM1_T_FS (bl)

(Output)

SS10

SS12

DAM1_T_FS (wl)

(Output)

SS14

SS17

SS15

SS18

SS16

DAM1_TXD

(Output)

SS43

SS42

SS19

DAM1_RXD

(Input)

Note: SRXD Input in Synchronous mode only

Figure 83. SSI Transmitter with Internal Clock Timing Diagram

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Preliminary

Electrical Characteristics

Table 61. SSI Transmitter with Internal Clock Timing Parameters

Parameter

Min

Max

Unit

Internal Clock Operation

SS1

SS2

SS3

SS4

SS5

SS6

SS8

(Tx/Rx) CK clock period

81.4

–

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

36.0

–

36.0

–

15.0

–

SS10 (Tx) CK high to FS (wl) high

SS12 (Tx) CK high to FS (wl) low

SS14 (Tx/Rx) Internal FS rise time

SS15 (Tx/Rx) Internal FS fall time

–

SS16 (Tx) CK high to STXD valid from high

impedance

–

15.0

SS17 (Tx) CK high to STXD high/low

SS18 (Tx) CK high to STXD high impedance

SS19 STXD rise/fall time

–

15.0

Synchronous Internal Clock Operation

SS42 SRXD setup before (Tx) CK falling

SS43 SRXD hold after (Tx) CK falling

SS52 Loading

10.0

–

•

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)

and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync

have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or

the frame sync STFS/SRFS shown in the tables and in the figures.

•

All timings are on AUDMUX pads when SSI is being used for data transfer.

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx

Data (for example, during AC97 mode of operation).

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Preliminary

Electrical Characteristics

4.3.22.2 SSI Receiver Timing with Internal Clock

Figure 84 depicts the SSI receiver timing with internal clock, and Table 62 lists the timing parameters.

SS1

SS3

SS5

SS4

SS2

AD1_TXC

(Output)

SS9

SS7

AD1_TXFS (bl)

(Output)

SS11

SS13

AD1_TXFS (wl)

(Output)

SS20

SS21

AD1_RXD

(Input)

SS51

SS50

SS47

SS49

SS48

AD1_RXC

(Output)

SS1

SS7

SS3

SS5

SS4

SS2

DAM1_T_CLK

(Output)

SS9

DAM1_T_FS (bl)

(Output)

SS11

SS13

DAM1_T_FS (wl)

(Output)

SS20

SS21

DAM1_RXD

(Input)

SS47

SS51

SS50

SS49

SS48

DAM1_R_CLK

(Output)

Figure 84. SSI Receiver with Internal Clock Timing Diagram

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Preliminary

Electrical Characteristics

Unit

Table 62. SSI Receiver with Internal Clock Timing Parameters

Parameter

Min

Max

Internal Clock Operation

SS1

SS2

SS3

SS4

SS5

SS7

SS9

(Tx/Rx) CK clock period

81.4

36.0

–

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

36.0

–

15.0

–

SS11 (Rx) CK high to FS (wl) high

SS13 (Rx) CK high to FS (wl) low

SS20 SRXD setup time before (Rx) CK low

SS21 SRXD hold time after (Rx) CK low

Oversampling Clock Operation

–

10.0

–

SS47 Oversampling clock period

SS48 Oversampling clock high period

SS49 Oversampling clock rise time

SS50 Oversampling clock low period

SS51 Oversampling clock fall time

15.04

–

NOTE

All the timings for the SSI are given for a non-inverted serial clock polarity

(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the

polarity of the clock and/or the frame sync have been inverted, all the timing

remains valid by inverting the clock signal STCK/SRCK and/or the frame

sync STFS/SRFS shown in the tables and in the figures.

NOTE

All timings are on AUDMUX pads when SSI is being used for data transfer.

NOTE

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

NOTE

For internal Frame Sync operation using external clock, the FS timing is the

same as that of Tx Data, for example, during the AC97 mode of operation.

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147

Preliminary

Electrical Characteristics

4.3.22.3 SSI Transmitter Timing with External Clock

Figure 85 depicts the SSI transmitter timing with external clock, and Table 63 lists the timing parameters.

SS22

SS23

SS25

SS26

SS24

AD1_TXC

(Input)

SS27

SS29

AD1_TXFS (bl)

(Input)

SS33

SS31

AD1_TXFS (wl)

(Input)

SS39

SS37

SS38

AD1_TXD

(Output)

SS45

SS44

AD1_RXD

(Input)

SS46

Note: SRXD Input in Synchronous mode only

SS22

SS26

SS25

SS24

SS23

DAM1_T_CLK

(Input)

SS29

SS27

DAM1_T_FS (bl)

(Input)

SS33

SS31

DAM1_T_FS (wl)

(Input)

SS39

SS37

SS38

DAM1_TXD

(Output)

SS45

SS44

DAM1_RXD

(Input)

SS46

Note: SRXD Input in Synchronous mode only

Figure 85. SSI Transmitter with External Clock Timing Diagram

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Preliminary

Electrical Characteristics

Table 63. SSI Transmitter with External Clock Timing Parameters

Parameter

Min

Max

Unit

External Clock Operation

SS22 (Tx/Rx) CK clock period

SS23 (Tx/Rx) CK clock high period

SS24 (Tx/Rx) CK clock rise time

SS25 (Tx/Rx) CK clock low period

SS26 (Tx/Rx) CK clock fall time

SS27 (Tx) CK high to FS (bl) high

SS29 (Tx) CK high to FS (bl) low

SS31 (Tx) CK high to FS (wl) high

SS33 (Tx) CK high to FS (wl) low

81.4

36.0

–

6.0

–

36.0

–

6.0

15.0

–

–10.0

10.0

–10.0

10.0

–

15.0

–

SS37 (Tx) CK high to STXD valid from high

impedance

15.0

SS38 (Tx) CK high to STXD high/low

SS39 (Tx) CK high to STXD high impedance

Synchronous External Clock Operation

SS44 SRXD setup before (Tx) CK falling

SS45 SRXD hold after (Tx) CK falling

SS46 SRXD rise/fall time

–

15.0

10.0

2.0

–

6.0

NOTE

All the timings for the SSI are given for a non-inverted serial clock polarity

(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the

polarity of the clock and/or the frame sync have been inverted, all the timing

remains valid by inverting the clock signal STCK/SRCK and/or the frame

sync STFS/SRFS shown in the tables and in the figures.

NOTE

All timings are on AUDMUX pads when the SSI is being used for data

transfer.

NOTE

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

NOTE

For internal Frame Sync operation using external clock, the FS timing will

be same as that of Tx Data, for example, during the AC97 mode of

operation.

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Preliminary

Electrical Characteristics

4.3.22.4 SSI Receiver Timing with External Clock

Figure 86 depicts the SSI receiver timing with external clock, and Table 64 lists the timing parameters.

SS22

SS26

SS25

SS24

SS23

AD1_TXC

(Input)

SS30

SS28

AD1_TXFS (bl)

(Input)

SS32

SS35

SS34

AD1_TXFS (wl)

(Input)

SS41

SS36

SS40

AD1_RXD

(Input)

SS22

SS24

SS26

SS25

SS23

DAM1_T_CLK

(Input)

SS30

SS28

DAM1_T_FS (bl)

(Input)

SS32

SS35

SS34

DAM1_T_FS (wl)

(Input)

SS41

SS36

SS40

DAM1_RXD

(Input)

Figure 86. SSI Receiver with External Clock Timing Diagram

Table 64. SSI Receiver with External Clock Timing Parameters

Parameter

Min

Max

Unit

External Clock Operation

SS22 (Tx/Rx) CK clock period

SS23 (Tx/Rx) CK clock high period

SS24 (Tx/Rx) CK clock rise time

81.4

36.0

–

6.0

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Preliminary

Electrical Characteristics

Table 64. SSI Receiver with External Clock Timing Parameters (continued)

Parameter

Min

Max

Unit

SS25 (Tx/Rx) CK clock low period

SS26 (Tx/Rx) CK clock fall time

36.0

–

6.0

15.0

–

SS28 (Rx) CK high to FS (bl) high

SS30 (Rx) CK high to FS (bl) low

SS32 (Rx) CK high to FS (wl) high

SS34 (Rx) CK high to FS (wl) low

SS35 (Tx/Rx) External FS rise time

SS36 (Tx/Rx) External FS fall time

SS40 SRXD setup time before (Rx) CK low

SS41 SRXD hold time after (Rx) CK low

–10.0

10.0

–10.0

10.0

–

15.0

–

6.0

–

10.0

2.0

–

NOTE

All the timings for the SSI are given for a non-inverted serial clock polarity

(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the

polarity of the clock and/or the frame sync have been inverted, all the timing

remains valid by inverting the clock signal STCK/SRCK and/or the frame

sync STFS/SRFS shown in the tables and in the figures.

NOTE

All timings are on AUDMUX pads when the SSI is being used for data

transfer.

NOTE

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

NOTE

For internal Frame Sync operation using external clock, the FS timing will

be same as that of Tx Data, for example, during the AC97 mode of

operation.

4.3.23 USB Electrical Specifications

This section describes the electrical information of the USBOTG port. The OTG port supports both serial

and parallel interfaces.

The high speed (HS) interface is supported via the ULPI (Ultra Low Pin Count Interface). Figure 87

depicts the USB ULPI timing diagram, and Table 65 lists the timing parameters.

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Preliminary

Package Information and Pinout

Clock

T_SC

T_HC

Control out (stp)

T_SD

T_HD

Data out

T_DC

Control in (dir, nxt)

T_DD

Data in

Figure 87. USB ULPI Interface Timing Diagram

Table 65. USB ULPI Interface Timing Specification

Parameter

Symbol

Min

Max

Units

Setup time (control in, 8-bit data in)

Hold time (control in, 8-bit data in)

TSC, TSD

THC, THD

TDC, TDD

6.0

0.0

9.0

Output delay (control out, 8-bit data

out)

Timing parameters are given as viewed by transceiver side.

5 Package Information and Pinout

This section includes the following:

•

Pin/contact assignment information—usually in the form of a pin-out or contact connection

diagram—for every applicable package, unless this information appears in Section 3, “Signal

Descriptions.”

NOTE:

Either pin or contact is used throughout the data sheet, as appropriate for the

device.

•

Mechanical package drawing for every applicable package

Ordering information (if this information isn’t included on page 1).

The i.MX31 and i.MX31L devices are available in the following package:

•

457 MAPBGA 14 x 14 mm 0.5 mm pitch package for production (Figure 88).

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Preliminary

Package Information and Pinout

5.1

MAPBGA Production Package 457 14 x 14 mm, 0.5 P

See Figure 88 for package drawings and dimensions of the production package.

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Preliminary

153

Package Information and Pinout

5.1.1

Production Package Outline Drawing

Figure 88. Production Package: Mechanical Drawing

i.MX31/i.MX31L Advance Information, Rev. 1.4

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Preliminary

Package Information and Pinout

5.1.2

MAPBGA Pinout for Production Package

Figure 89 shows the i.MX31/i.MX31L ball map of pad locations.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

Preliminary

155

SFS5 CSPI2 CSPI2_ USBOT USBOT USBOT USB_B RXD1 DSR_D DSR_D RXD2 CE_CO KEY_R KEY_R KEY_C KEY_C TDO

_MISO SS2 G_DAT G_DAT G_NXT YP CE1 TE1 NTROL OW3 OW7 OL3 OL7

A7 A3

STXD4 SRXD CSPI2_ CSPI2_ USBOT USBOT USBOT USB_P CTS1 DCD_D DCD_D RTS2 KEY_R KEY_R KEY_C KEY_C TCK

SS0 SPI_R G_DAT G_DAT G_DIR WR CE1 TE1 OW1 OW5 OL1 OL5

DY A5 A1

SRXD4 SCK4 STXD5 CSPI2_ CSPI2_ USBOT USBOT USB_O DTR_D DTR_D TXD2 KEY_R KEY_C KEY_C RTCK DE

GND

SJC_M SVEN0 CAPTU GPIO1_ WATCH GND

DOG_R

GND

TRSTB SRX0

SCLK0 GPIO1_ GPIO1_ GND

GND

SRST0 GPIO1 BOOT_ BOOT_ CLKO

GND

SS1

SCLK G_DAT G_STP C

CE1

TE1

OW2

OL0

OL4

MODE1 MODE3

CSPI3_ SCK5

MOSI

BOOT_ GND

MODE2

BOOT_

MODE4

CSPI3_ ATA_DI CSPI2_

SCLK OR MOSI

NVCC5

GND

DVFS0 POWER

_FAIL

ATA_D ATA_C SFS4

MACK S1

NVCC5 BATT_ USBOT USBOT TXD1 RI_DC DTR_D KEY_R KEY_R KEY_C TDI

STX0 GPIO1 GPIO1 BOOT_ GND

CKIH

GPIO1_ VSTBY

LINE

G_DAT G_DAT

A6 A0

USBOT USBOT RTS1 RI_DT CTS2 KEY_R KEY_C TMS

CE2

OW0

OW6

OL6

MODE

PWMO PC_R CSPI3_

CSPI3_ NVCC5

SIMPD COMP NVCC1

NVCC1

CKIL

DVFS1 VPG0

CLKSS

MISO

SPI_R

G_DAT G_CLK

OW4

OL2

ARE

PC_RS PC_BV ATA_R

D1 ESET

PC_VS PC_RE IOIS16

ADY

PC_CD SD1_D PC_P

ATA3 WRON

SD1_D SD1_C SD1_D

ATA1 MD ATA2

ATA_DI

POR

I2C_DA GPIO3_

ATA_C PC_PO

QVCC1 QVCC1 NVCC8 NVCC8 QVCC NVCC6 NVCC6 NVCC9

NVCC6

VPG1 RESET_

I2C_CL CSI_VS CSI_PIX

K YNC CLK

PC_BV PC_VS

PC_WA PC_CD

SD1_D SD1_C

ATA0 LK

QVCC1

NVCC3

QVCC4

NVCC1

CSI_H GPIO3_

CSI_MC CSI_D5 CSI_D7

SYNC

QVCC1 GND

GND GND

QVCC QVCC QVCC QVCC

NVCC4 NVCC4 CSI_D8 CSI_D4

CSI_D6 CSI_D9 CSI_D1

USBH2 USBH2 USBH2

_DATA0 _STP _DATA1

GND

QVCC

CSI_D1 CSI_D1

CSI_D1 CSI_D1 CSI_D1

USBH2 CSPI1_ CSPI1_

_CLK SCLK SPI_R

USBH2 USBH2

_NXT _DIR

NVCC3 GND

NVCC7

SD_D_I FPSHIF

VSYNC HSYNC DRDY0

CSPI1_ CSPI1_ CSPI1_

CSPI1_ CSPI1_

NVCC1

NVCC1 GND

GND

NVCC7

QVCC

READ LCS1

SD_D_ SD_D_I LCS0

SS1

MOSI SS0

SS2

MISO

CLK

STXD3 SCK3 SRXD3

STXD6 SCK6 SFS6

NFRB NFWP NFCLE

NFALE NFRE D13

SFS3 SRXD6

QVCC4

NVCC1 GND

D3_CL PAR_RS

CONTR WRITE VSYNC

AST

LD0

NFCE NFWE

NVCC1 GND

SGND MGND UGND

LD4

LD2

SER_R D3_REV

D15

D11

TTM_P LD8

LD6

D3_SPL LD1

QVCC QVCC QVCC QVCC SVCC MVCC UVCC GND

LD17 LD13

EB0

LD10

LD15

LD3

LD7

LD5

LD9

D14

D12

NVCC2

D10

IOQVD NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 M_GRA

EB1

LD11

LD14

LD12

LD16

BCLK

AA D6

AB D2

NVCC2 SD31 SD28 SD27 SD23 SD21 SD18 SD16 SD13 SD9

SD7

SD5

SD3

SD2

DQM2 SDCLK

FVCC

FGND OE

AC MA10 GND

A11

FUSE_V M_REQ GND

UEST

AD GND

GND

A12

A13

SDBA0 SDQS3 SD29 SD25 SDQS2 SD17 SD15 SD12 SD8

SDQS0 SD4

SD0

DQM1 CAS

SDCKE CS3

ECB

GND

AE GND

AF GND

GND

SDBA1 SD30 SD26 SD24 SD22 SD20 SD19 SDQS1 SD14 SD11 SD10 SD6

A1 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15

SD1

A14

DQM3 DQM0 SDCLK CS2

LBA

CS0

CS1

GND

CS4

GND

A10

RAS

SDWE SDCKE CS5

Figure 89. i.MX31/i.MX31L Ball Map

Package Information and Pinout

Figure 66 shows the signal color and signal name legend.

Table 66. Signal Color/Name Legend

Color

Name

None

Signal name as listed

GND

NVCC1

NVCC2

NVCC3

NVCC4

NVCC5

NVCC6

NVCC7

NVCC8

NVCC9

NVCC10

NVCC21

NVCC22

QVCC

QVCC1

QVCC4

Table 67 shows the device pin list, sorted by signal identification, excluding pad locations for ground and

power supply voltages.

Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location)

Signal ID

Pad Location

AD6

AF5

A10

A11

A12

A13

A14

A15

AF18

AC3

AD3

AD4

AF17

AF16

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Preliminary

Package Information and Pinout

Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued)

Signal ID

Pad Location

A16

A17

AF15

AF14

AF13

AF12

AB5

AF11

AF10

AF9

AF8

AF7

AF6

AE4

AA3

AF4

AB3

AE3

AD5

AF3

A18

A19

A20

A21

A22

A23

A24

A25

ATA_CS0

ATA_CS1

ATA_DIOR

ATA_DIOW

ATA_DMACK

ATA_RESET

BATT_LINE

BCLK

AB26

F20

C21

D24

C22

D26

A22

AD20

A14

F24

H21

C23

BOOT_MODE0

BOOT_MODE1

BOOT_MODE2

BOOT_MODE3

BOOT_MODE4

CAPTURE

CAS

CE_CONTROL

CKIH

CKIL

CLKO

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Package Information and Pinout

Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued)

Signal ID

Pad Location

CLKSS

COMPARE

CONTRAST

CS0

G26

G18

R24

AE23

AF23

AE21

AD22

AF24

AF22

M24

L26

M21

M25

M20

M26

L21

K25

L24

K26

L20

L25

K20

K24

J26

J25

CS1

CS2

CS3

CS4

CS5

CSI_D10

CSI_D11

CSI_D12

CSI_D13

CSI_D14

CSI_D15

CSI_D4

CSI_D5

CSI_D6

CSI_D7

CSI_D8

CSI_D9

CSI_HSYNC

CSI_MCLK

CSI_PIXCLK

CSI_VSYNC

CSPI1_MISO

CSPI1_MOSI

CSPI1_SCLK

CSPI1_SPI_RDY

CSPI1_SS0

CSPI1_SS1

CSPI1_SS2

CSPI2_MISO

CSPI2_MOSI

CSPI2_SCLK

CSPI2_SPI_RDY

CSPI2_SS0

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Preliminary

Package Information and Pinout

Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued)

Signal ID

Pad Location

CSPI2_SS1

CSPI2_SS2

CSPI3_MISO

CSPI3_MOSI

CSPI3_SCLK

CSPI3_SPI_RDY

CTS1

B11

G13

AB2

CTS2

D10

D11

D12

D13

D14

D15

AB1

D3_CLS

D3_REV

D3_SPL

R20

T26

U25

AA2

AA1

DCD_DCE1

DCD_DTE1

B12

B13

C18

AE19

AD19

AA20

AE18

N26

A11

A12

DQM0

DQM1

DQM2

DQM3

DRDY0

DSR_DCE1

DSR_DTE1

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Package Information and Pinout

Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued)

Signal ID

Pad Location

DTR_DCE1

DTR_DCE2

DTR_DTE1

DVFS0

C11

F12

C12

E25

G24

W21

Y24

AD23

AB24

N21

AC24

AA24

F18

B23

C20

F25

F19

B24

A23

K21

H26

N25

J24

DVFS1

EB0

EB1

ECB

FGND

FPSHIFT

FUSE_VDD

FVCC

GPIO1_0

GPIO1_1

GPIO1_2

GPIO1_3

GPIO1_4

GPIO1_5

GPIO1_6

GPIO3_0

GPIO3_1

HSYNC

I2C_CLK

I2C_DAT

IOIS16

H25

IOQVDD

KEY_COL0

KEY_COL1

KEY_COL2

KEY_COL3

KEY_COL4

KEY_COL5

KEY_COL6

KEY_COL7

KEY_ROW0

KEY_ROW1

KEY_ROW2

C15

B17

G15

A17

C16

B18

F15

A18

F13

B15

C14

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Preliminary

Package Information and Pinout

Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued)

Signal ID

Pad Location

KEY_ROW3

KEY_ROW4

KEY_ROW5

KEY_ROW6

KEY_ROW7

LBA

A15

G14

B16

F14

A16

AE22

P26

P21

T24

U26

V24

Y25

Y26

V21

AA25

W24

AA26

V20

T21

V25

T20

V26

U24

W25

U21

W26

Y21

AC25

AC1

T15

V15

LCS0

LCS1

LD0

LD1

LD10

LD11

LD12

LD13

LD14

LD15

LD16

LD17

LD2

LD3

LD4

LD5

LD6

LD7

LD8

LD9

M_GRANT

M_REQUEST

MA10

MGND

MVCC

NFALE

NFCE

NFCLE

NFRB

NFRE

NFWE

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Package Information and Pinout

Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued)

Signal ID

Pad Location

NFWP

NVCC9

J17

AB25

R21

PAR_RS

PC_BVD1

PC_BVD2

PC_CD1

PC_CD2

PC_POE

PC_PWRON

PC_READY

PC_RST

PC_RW

PC_VS1

PC_VS2

PC_WAIT

POR

H24

E26

POWER_FAIL

PWMO

RAS

AF19

P20

J21

F11

G12

C17

G11

B14

AB22

A10

A13

READ

RESET_IN

RI_DCE1

RI_DTE1

RTCK

RTS1

RTS2

RXD1

RXD2

SCK3

SCK4

SCK5

SCK6

SCLK0

B22

P24

N20

SD_D_CLK

SD_D_I

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Preliminary

Package Information and Pinout

Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued)

Signal ID

Pad Location

SD_D_IO

SD0

P25

AD18

AE17

SD1

SD1_CLK

SD1_CMD

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

SD10

AE15

AE14

AD14

AA14

AE13

AD13

AA13

AD12

AA12

AE11

AA19

AE10

AA11

AE9

SD11

SD12

SD13

SD14

SD15

SD16

SD17

SD18

SD19

SD2

SD20

SD21

SD22

SD23

AA10

AE8

SD24

SD25

AD10

AE7

SD26

SD27

AA9

SD28

AA8

SD29

AD9

AA18

AE6

SD3

SD30

SD31

AA7

SD4

AD17

AA17

AE16

AA16

SD5

SD6

SD7

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Preliminary

Package Information and Pinout

Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued)

Signal ID

Pad Location

SD8

SD9

AD15

AA15

AD7

AE5

AD21

AF21

AA21

AE20

AD16

AE12

AD11

AD8

AF20

T25

SDBA0

SDBA1

SDCKE0

SDCKE1

SDCLK

SDQS0

SDQS1

SDQS2

SDQS3

SDWE

SER_RS

SFS3

SFS4

SFS5

SFS6

SGND

SIMPD0

SJC_MOD

SRST0

SRX0

T14

G17

A20

C19

B21

SRXD3

SRXD4

SRXD5

SRXD6

STX0

F17

STXD3

STXD4

STXD5

STXD6

SVCC

V14

A21

B19

F16

A19

SVEN0

TCK

TDI

TDO

i.MX31/i.MX31L Advance Information, Rev. 1.4

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Preliminary

Package Information and Pinout

Table 67. i.MX31/i.MX31L 14 x 14 BGA (457 Signal ID by Pad Grid Location) (continued)

Signal ID

Pad Location

TMS

TRSTB

G16

B20

U20

F10

C13

V16

TTM_PAD

TXD1

TXD2

UVCC

USB_BYP

USB_OC

C10

B10

USB_PWR

USBH2_CLK

USBH2_DATA0

USBH2_DATA1

USBH2_DIR

USBH2_NXT

USBH2_STP

USBOTG_CLK

USBOTG_DATA0

USBOTG_DATA1

USBOTG_DATA2

USBOTG_DATA3

USBOTG_DATA4

USBOTG_DATA5

USBOTG_DATA6

USBOTG_DATA7

USBOTG_DIR

USBOTG_NXT

USBOTG_STP

UGND

G10

T16

G25

J20

F26

N24

R26

A24

R25

VPG0

VPG1

VSTBY

VSYNC0

VSYNC3

WATCHDOG_RST

WRITE

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Preliminary

Product Documentation

6 Product Documentation

This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data.

Definitions of these types are available at: http://www.freescale.com.

6.1

Revision History

Table 68 summarizes revisions to this document since the release of Rev. 1.2.

Table 68. Revision History

Location

Revision

Table 9, "DC Recommended Operating

Conditions," on page 61

Core Supply voltage—changed minimum voltage FROM 1.2 V TO 1.22 V.

Table 10, "Voltage versus Core Frequency," • Min (V) for 1st row—changed value FROM 1.2 V to 1.22 V.

on page 62

• Added footnotes.

Table 13, "Power Consumption (Typical

Values)," on page 64

Updated entire table.

Section 4.3.8, “DPLL Electrical

Specifications” starting on page 82

Updated DPLL section for content. Replaced HI/LO with content about external

clock source (CKIH) and FPM (Frequency Pre-Multiplier).

Table 34, "DDR/SDR SDRAM Read Cycle

• Changed SD4, SD6 min values FROM 1.8 V TO 2.0 V.

Timing Parameters," on page 94, Table 35, • Changed SD13 min value FROM 2.4 V TO 2.0 V.

"SDR SDRAM Write Timing Parameters," on

page 96

Section 4.3.10, “ETM Electrical

At ETM Trace Data Timing Parameters table: Changed Ts Setup value FROM 3

Specifications” on page 100, Table 41, "ETM TO 2, changed Th Hold value FROM 2 TO 1.

Trace Data Timing Parameters," on page

101.

Table 60, "SJC Timing Parameters," on

page 143

• SJ1 row—Removed “in Crystal mode“, changed min value FROM 45.0 ns TO

100.0 ns.

• Changed SJ2 min value FROM 22.5 ns TO 40.0 ns.

• Changed SJ4 min value FROM 5.0 ns TO 10.0 ns.

• Changed SJ5 min value FROM 24.0 ns TO 50.0 ns.

• Changed SJ8 min value FROM 5.0 ns TO 10.0 ns.

• Changed SJ9 min value FROM 25.0 ns TO 50.0 ns.

Section 4.3.2, “AC Electrical

Updated section for figure, table values.

Characteristics” starting on page 68

Section 2.1.1, “Performance” on page 4

Updated section.

Table 11, "Interface Frequency," on page 62 Updated.

Section 4.3.23, “USB Electrical

Specifications” on page 151

Revised section; added ULPI information.

Figure 89, "i.MX31/i.MX31L Ball Map," on

page 156

Revised for color, grid # ID.

i.MX31/i.MX31L Advance Information, Rev. 1.4

Freescale Semiconductor

167

Preliminary

Product Documentation

Location

Table 68. Revision History (continued)

Revision

Table 23, "ATA Timing Parameters," on page • Inserted the following values:

• ti_ds, 11 ns

• ti_dh, 6 ns

• tco, 15 ns

• tsu, 19 ns

• tsui, 9 ns

• thi, 5 ns

• Changed tskew1 value FROM 20 ns TO 7 ns.

Table 29, "CSPI Interface Timing

Parameters," on page 81

Changed CS4, CS5, CS6 min values FROM 30 ns TO 25 ns.

Table 33, "WEIM Bus Timing Parameters," Updated entire table.

on page 89

Table 49, "Synchronous Display Interface

Timing Parameters—Access Level," on

page 110

Changed IP18 min value FROM Tdicd-1.5 TO Tdicd-3.5.

Changed IP19 min value FROM Tdicp-Tdicd-1.5 TO Tdicp-Tdicd-3.5.

Changed IP20 min value FROM Tdicd-1.5 TO Tdicd-3.5.

Above Figure 30, "Asynchronous Memory

Timing Diagram for Read

Changed pad voltage FROM 1.7 V TO 1.75 V.

Access—WSC=1," on page 91

Section 4.1, “i.MX31 and i.MX31L

Chip-Level Conditions” starting on page 60

• Table 9, "DC Recommended Operating Conditions," on page 61—changed

Core Supply Voltage row max voltage FROM 1.6 V to 1.65 V, footnote value

FROM 1.6 V TO 1.65 V (2 plcs).

• Table 10, "Voltage versus Core Frequency," on page 62—changed both max

values FROM 1.6 V TO 1.65 V; PMIC value in footnote FROM 1.575 V to 1.6 V.

• Table 12, "DC Absolute Maximum Operating Conditions," on page

63—changed max value FROM 1.6 V to 1.65 V.

Section 4.3.9.3, “SDRAM (DDR and SDR) Removed duplicate notes about pad voltages and signal values.

Memory Controller” starting on page 93

Figure 89, "i.MX31/i.MX31L Ball Map," on

page 156

Corrected pad locations for area of rows E through N, columns 4 through 26.

i.MX31/i.MX31L Advance Information, Rev. 1.4

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Product Documentation

i.MX31/i.MX31L Advance Information, Rev. 1.4

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Document Number: MCIMX31

Rev. 1.4

04/2006

Preliminary

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