MK40DX128ZVMD10 [FREESCALE]
K40 Sub-Family Data Sheet; K40次系列数据手册型号: | MK40DX128ZVMD10 |
厂家: | Freescale |
描述: | K40 Sub-Family Data Sheet |
文件: | 总78页 (文件大小:1997K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: K40P144M100SF2
Rev. 6, 9/2011
Freescale Semiconductor
Data Sheet: Technical Data
K40P144M100SF2
K40 Sub-Family Data Sheet
Supports the following:
MK40DX128ZVLQ10,
MK40DX128ZVMD10,
MK40DX256ZVLQ10,
MK40DX256ZVMD10,
MK40DN512ZVLQ10,
MK40DN512ZVMD10
Features
Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
•
•
Operating Characteristics
•
•
•
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
– 128-bit unique identification (ID) number per chip
Human-machine interface
Performance
– Segment LCD controller supporting up to 40
frontplanes and 8 backplanes, or 44 frontplanes and
4 backplanes
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Memories and memory interfaces
– Up to 512 KB program flash memory on non-
FlexMemory devices
Analog modules
– Two 16-bit SAR ADCs
•
– Up to 256 KB program flash memory on
FlexMemory devices
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– Up to 256 KB FlexNVM on FlexMemory devices
– 4 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
– Two 12-bit DACs
– Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
Timers
•
Clocks
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two 2-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
•
•
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
System peripherals
– 10 low-power modes to provide power optimization
based on application requirements
– Memory protection unit with multi-master
protection
– 16-channel DMA controller, supporting up to 64
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2010–2011 Freescale Semiconductor, Inc.
Communication interfaces
•
– USB full-/low-speed On-the-Go controller with on-chip transceiver
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital host controller (SDHC)
– I2S module
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
2
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................5
5.4.2
Thermal attributes...............................................22
1.1 Determining valid orderable parts......................................5
2 Part identification......................................................................5
2.1 Description.........................................................................5
2.2 Format...............................................................................5
2.3 Fields.................................................................................5
2.4 Example............................................................................6
3 Terminology and guidelines......................................................6
3.1 Definition: Operating requirement......................................6
3.2 Definition: Operating behavior...........................................7
3.3 Definition: Attribute............................................................7
3.4 Definition: Rating...............................................................8
3.5 Result of exceeding a rating..............................................8
3.6 Relationship between ratings and operating
6 Peripheral operating requirements and behaviors....................23
6.1 Core modules....................................................................23
6.1.1
6.1.2
Debug trace timing specifications.......................23
JTAG electricals..................................................24
6.2 System modules................................................................27
6.3 Clock modules...................................................................27
6.3.1
6.3.2
6.3.3
MCG specifications.............................................27
Oscillator electrical specifications.......................29
32kHz Oscillator Electrical Characteristics.........31
6.4 Memories and memory interfaces.....................................32
6.4.1
6.4.2
6.4.3
Flash (FTFL) electrical specifications.................32
EzPort Switching Specifications.........................37
Flexbus Switching Specifications........................38
requirements......................................................................8
3.7 Guidelines for ratings and operating requirements............9
3.8 Definition: Typical value.....................................................9
3.9 Typical value conditions....................................................10
4 Ratings......................................................................................10
4.1 Thermal handling ratings...................................................11
4.2 Moisture handling ratings..................................................11
4.3 ESD handling ratings.........................................................11
4.4 Voltage and current operating ratings...............................11
5 General.....................................................................................12
5.1 AC electrical characteristics..............................................12
5.2 Nonswitching electrical specifications...............................12
6.5 Security and integrity modules..........................................41
6.6 Analog...............................................................................41
6.6.1
6.6.2
6.6.3
6.6.4
ADC electrical specifications..............................41
CMP and 6-bit DAC electrical specifications......49
12-bit DAC electrical characteristics...................52
Voltage reference electrical specifications..........55
6.7 Timers................................................................................56
6.8 Communication interfaces.................................................56
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
USB electrical specifications...............................56
USB DCD electrical specifications......................57
USB VREG electrical specifications...................57
CAN switching specifications..............................58
DSPI switching specifications (limited voltage
range).................................................................58
DSPI switching specifications (full voltage
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
Voltage and current operating requirements......13
LVD and POR operating requirements...............14
Voltage and current operating behaviors............14
Power mode transition operating behaviors.......15
Power consumption operating behaviors............16
EMC radiated emissions operating behaviors....19
Designing with radiated emissions in mind.........20
Capacitance attributes........................................20
6.8.6
range).................................................................59
I2C switching specifications................................61
UART switching specifications............................61
SDHC specifications...........................................61
6.8.7
6.8.8
6.8.9
6.8.10 I2S switching specifications................................62
6.9 Human-machine interfaces (HMI)......................................64
5.3 Switching specifications.....................................................20
5.3.1
5.3.2
Device clock specifications.................................20
General switching specifications.........................20
6.9.1
6.9.2
TSI electrical specifications................................64
LCD electrical characteristics.............................65
5.4 Thermal specifications.......................................................21
5.4.1 Thermal operating requirements.........................21
7 Dimensions...............................................................................67
7.1 Obtaining package dimensions.........................................67
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
3
8 Pinout........................................................................................67
8.1 K40 Signal Multiplexing and Pin Assignments..................67
8.2 K40 Pinouts.......................................................................73
9 Revision History........................................................................75
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
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Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to http://www.freescale.com and perform a part number
search for the following device numbers: PK40 and MK40.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
Kinetis family
Key attribute
• K40
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
5
Terminology and guidelines
Field
Description
Values
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• EX = 64 LQFN (9 mm x 9 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• MB = 81 MAPBGA (8 mm x 8 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MF = 196 MAPBGA (15 mm x 15 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK40DN512ZVMD10
3 Terminology and guidelines
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
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Freescale Semiconductor, Inc.
Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
7
Terminology and guidelines
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
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Freescale Semiconductor, Inc.
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
Fatal
range
Normal
operating
range
Fatal
range
- Probable permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- Probable permanent failure
Handling range
- No permanent failure
–∞
∞
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
9
Ratings
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
V
VDD
3.3 V supply voltage
3.3
4 Ratings
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
10
Freescale Semiconductor, Inc.
Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
2
TSDR
Solder temperature, lead-free
Solder temperature, leaded
—
—
260
245
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
ILAT
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
-500
-100
+500
+100
V
2
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
5.5
mA
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
11
General
Symbol
VAIO
ID
Description
Min.
Max.
Unit
Analog1, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to all
port pins)
–25
25
mA
VDDA
VUSB_DP
VUSB_DM
VREGIN
VBAT
Analog supply voltage
USB_DP input voltage
USB_DM input voltage
USB regulator input
VDD – 0.3
–0.3
VDD + 0.3
3.63
V
V
V
V
V
–0.3
3.63
–0.3
6.0
RTC battery supply voltage
–0.3
3.8
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
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Freescale Semiconductor, Inc.
General
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
–0.1
–0.1
1.71
3.6
0.1
0.1
3.6
V
V
V
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
VBAT
VIH
RTC battery supply voltage
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICDIO
Input hysteresis
0.06 × VDD
-5
—
—
V
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
3
mA
Analog2, EXTAL, and XTAL pin DC injection current
— single pin
IICAIO
mA
-5
—
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
—
+5
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
• Negative current injection
• Positive current injection
+25
VRAM
VDD voltage required to retain RAM
1.2
—
—
V
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
VPOR_VBAT
1. All 5 volt tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode
connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection
current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN
(=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is
calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
13
General
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
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Freescale Semiconductor, Inc.
General
Notes
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
—
100
mA
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
—
—
100
1
mA
μA
Input leakage current (per pin) for full temperature
range
1
1
IIN
Input leakage current (per pin) at 25°C
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
—
20
20
0.025
1
μA
μA
kΩ
kΩ
IOZ
RPU
RPD
50
2
3
Internal pulldown resistors
50
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
15
General
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
Max.
Unit
Notes
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
1
—
—
—
—
—
—
112
74
μs
μs
μs
μs
μs
μs
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
73
5.9
5.8
4.2
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
2
• @ 1.8V
• @ 3.0V
—
—
45
47
70
72
mA
mA
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C
—
61
85
mA
—
—
—
63
72
35
71
87
—
mA
mA
mA
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
2
5
6
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
—
15
—
—
mA
mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
N/A
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
16
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
N/A
—
mA
7
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
—
N/A
—
mA
8
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
0.59
2.26
5.94
1.4
7.9
mA
mA
mA
• @ 70°C
• @ 105°C
19.2
IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
93
435
2000
4000
μA
μA
μA
520
• @ 105°C
1350
IDD_LLS
Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
9
9
—
—
—
4.8
28
20
68
μA
μA
μA
• @ 70°C
• @ 105°C
126
270
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
3.1
17
82
8.9
35
μA
μA
μA
• @ 105°C
148
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
2.2
7.1
41
5.4
12.5
125
μA
μA
μA
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
2.1
6.2
30
7.6
13.5
46
μA
μA
μA
• @ 105°C
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
0.33
0.60
1.97
0.39
0.78
2.9
μA
μA
μA
• @ 105°C
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
17
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VBAT Average current when CPU is not accessing
RTC registers
10
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
—
—
—
0.71
1.01
2.82
0.81
1.3
μA
μA
μA
• @ 105°C
• @ 3.0V
4.3
• @ –40 to 25°C
• @ 70°C
—
—
—
0.84
1.17
3.16
0.94
1.5
μA
μA
μA
• @ 105°C
4.6
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.
6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. For
devices with 32 KB of RAM, power consumption is reduced by 3 μA.
10. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
18
Freescale Semiconductor, Inc.
General
Figure 2. Run mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 144LQFP
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
23
27
28
14
K
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
19
General
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
100
—
MHz
MHz
fSYS_USB
System and core clock when Full Speed USB in
operation
20
fBUS
FB_CLK
fFLASH
Bus clock
—
—
—
—
50
50
25
25
MHz
MHz
MHz
MHz
FlexBus clock
Flash clock
LPTMR clock
fLPTMR
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
20
Freescale Semiconductor, Inc.
General
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
16
—
—
ns
ns
ns
2
2
2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
100
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
3
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
12
6
ns
ns
• Slew enabled
—
—
36
24
ns
ns
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
Port rise and fall time (low drive strength)
• Slew disabled
4
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
12
6
ns
ns
• Slew enabled
—
—
36
24
ns
ns
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75pF load
4. 15pF load
5.4 Thermal specifications
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
21
General
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
5.4.2 Thermal attributes
Board type
Symbol
Description
144 LQFP
144
MAPBGA
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
45
48
29
38
25
16
°C/W
1
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
36
36
30
24
°C/W
°C/W
°C/W
°C/W
1
1
1
2
Single-layer
(1s)
RθJMA
RθJMA
RθJB
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
Four-layer
(2s2p)
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
—
Thermal
resistance,
junction to
board
—
—
RθJC
Thermal
resistance,
junction to case
9
2
9
2
°C/W
°C/W
3
4
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
2.
3.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Twh
Tr
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
ns
ns
ns
ns
ns
ns
—
—
3
Tf
3
Ts
—
—
Th
Data hold
2
Figure 3. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 4. Trace data specifications
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
20
10
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
25
25
—
—
17
17
—
—
J6
J7
—
—
8
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Table 14. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
TCLK cycle period
1/J1
—
ns
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J3
TCLK clock pulse width
• Boundary Scan
50
25
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
12.5
J4
J5
TCLK rise and fall times
—
20
0
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
—
—
8
25
25
—
J8
J9
J10
J11
J12
J13
J14
1.4
—
—
100
8
—
22.1
22.1
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 5. Test clock input timing
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 6. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 7. Test Access Port timing
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
TRST
J14
J13
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 15. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
fints_t
Iints
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Internal reference frequency (slow clock) — user
trimmed
31.25
—
38.2
kHz
Internal reference (slow clock) current
—
—
20
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
0.6
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
1.5
4.5
%fdco
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
Iintf
Internal reference (fast clock) current
—
25
—
—
—
µA
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
640 × ffll_ref
20.97
MHz
2, 3
frequency range
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
4, 5
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
6
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
7
7
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 48)
=
=
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
2.0
4.0
MHz
Jcyc_pll
PLL period jitter (RMS)
• fvco = 48 MHz
8
—
—
120
50
—
—
ps
ps
• fvco = 100 MHz
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
8
• fvco = 48 MHz
• fvco = 100 MHz
—
—
1350
600
—
—
ps
ps
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
%
%
s
150 × 10-6
+ 1075(1/
tpll_lock
9
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
Table 16. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Oscillator crystal or resonator frequency — low
32
—
40
kHz
frequency mode (MCG_C2[RANGE]=00)
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
8
—
—
8
MHz
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.3.3 32kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1 32kHz oscillator DC electrical specifications
Table 18. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
RF
Internal feedback resistor
—
100
—
MΩ
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 18. 32kHz oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
—
5
7
pF
Cload
Internal load capacitance (programmable)
Peak-to-peak amplitude of oscillation
—
—
15
—
—
pF
V
1
0.6
Vpp
1. The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to
any other devices.
6.3.3.2 32kHz oscillator frequency specifications
Table 19. 32kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
1. Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFL) electrical specifications
This section describes the electrical characteristics of the FTFL module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol Description
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
Min.
Typ.
Max.
Unit
Notes
—
7.5
18
μs
—
—
13
113
ms
ms
1
1
thversblk256k Erase Block high-voltage time for 256 KB
416
3616
1. Maximum time based on expectations at cycling end-of-life.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4.1.2 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
• 256 KB program/data flash
—
—
1.7
ms
trd1sec2k
tpgmchk
trdrsrc
Read 1s Section execution time (flash sector)
Program Check execution time
—
—
—
—
—
—
—
65
60
45
μs
μs
μs
μs
1
1
1
Read Resource execution time
30
tpgm4
Program Longword execution time
145
Erase Flash Block execution time
• 256 KB program/data flash
2
2
tersblk256k
tersscr
—
—
435
14
3700
114
ms
ms
Erase Flash Sector execution time
Program Section execution time
• 512 B flash
tpgmsec512
tpgmsec1k
tpgmsec2k
—
—
—
2.4
4.7
9.3
—
—
—
ms
ms
ms
• 1 KB flash
• 2 KB flash
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
1.8
25
ms
μs
μs
ms
μs
trdonce
1
tpgmonce Program Once execution time
65
870
—
—
tersall
Erase All Blocks execution time
7400
30
2
1
tvfykey
Verify Backdoor Access Key execution time
Swap Control execution time
• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08
tswapx01
tswapx02
tswapx04
tswapx08
—
—
—
—
200
70
70
—
—
150
150
30
μs
μs
μs
μs
Program Partition for EEPROM execution time
• 256 KB FlexNVM
tpgmpart256k
—
450
—
ms
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram32k
tsetram256k
—
—
—
70
0.8
4.5
—
μs
ms
ms
• 32 KB EEPROM backup
• 256 KB EEPROM backup
1.2
5.5
Byte-write to FlexRAM for EEPROM operation
teewr8bers Byte-write to erased FlexRAM location execution
time
—
175
260
μs
3
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
33
Peripheral operating requirements and behaviors
Table 21. Flash command timing specifications (continued)
Symbol Description
Byte-write to FlexRAM execution time:
Min.
Typ.
Max.
Unit
Notes
teewr8b32k
teewr8b64k
teewr8b128k
teewr8b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
385
475
1800
2000
2400
3200
μs
μs
μs
μs
650
1000
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
260
μs
Word-write to FlexRAM execution time:
teewr16b32k
teewr16b64k
teewr16b128k
teewr16b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
385
475
1800
2000
2400
3200
μs
μs
μs
μs
650
1000
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
540
μs
Longword-write to FlexRAM execution time:
teewr32b32k
teewr32b64k
teewr32b128k
teewr32b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
630
810
2050
2250
2675
3500
μs
μs
μs
μs
1200
1900
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash (FTFL) current and power specfications
Table 22. Flash (FTFL) current and power specfications
Symbol
Description
Typ.
Unit
mA
IDD_PGM
Worst case programming current in program flash
10
6.4.1.4 Reliability specifications
Table 23. NVM reliability specifications
Typ.1
Symbol Description
Min.
Program Flash
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
2
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 23. NVM reliability specifications (continued)
Typ.1
Symbol Description
Min.
10
Max.
—
Unit
years
years
cycles
Notes
tnvmretp1k Data retention after up to 1 K cycles
tnvmretp100 Data retention after up to 100 cycles
nnvmcycp Cycling endurance
100
2
2
3
15
100
—
10 K
35 K
—
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
tnvmretd100 Data retention after up to 100 cycles
nnvmcycd Cycling endurance
5
50
—
—
—
—
years
years
years
cycles
2
2
2
3
10
100
100
35 K
15
10 K
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
tnvmretee1 Data retention up to 1% of write endurance
Write endurance
5
50
—
—
—
years
years
years
2
2
2
4
10
15
100
100
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
nnvmwree32k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
35 K
315 K
1.27 M
10 M
175 K
1.6 M
6.4 M
50 M
—
—
—
—
—
writes
writes
writes
writes
writes
• EEPROM backup to FlexRAM ratio =
32,768
80 M
400 M
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
4. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
6.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFL to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that can
be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
EEPROM – 2 × EEESPLIT × EEESIZE
Writes_subsystem =
× Write_efficiency × nnvmcycd
EEESPLIT × EEESIZE
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition
command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycd — data flash cycling endurance
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 9. EEPROM backup writes to FlexRAM
6.4.2 EzPort Switching Specifications
Table 24. EzPort switching specifications
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
1.71
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
16
—
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
ns
—
12
ns
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
EZP_CK
EP3
EP4
EP2
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited voltage range switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
20
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
11.5
—
ns
1
1
2
2
0.5
8.5
0.5
ns
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 26. Flexbus full voltage range switching specifications
Num
Description
Min.
1.71
Max.
3.6
Unit
Notes
Operating voltage
V
Frequency of operation
—
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
Clock period
1/FB_CLK
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
0
13.5
—
ns
1
1
2
2
ns
13.7
0.5
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB3
FB5
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
Address
FB4
FB2
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 11. FlexBus read timing diagram
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB2
FB3
Address
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 12. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the
differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and
ADCx_DM3.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 29 and
Table 30.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Typ.1
Symbol Description
Conditions
Absolute
Min.
1.71
-100
Max.
3.6
Unit
V
Notes
VDDA
Supply voltage
Supply voltage
—
ΔVDDA
Delta to VDD (VDD
-
0
+100
mV
2
2
VDDA
)
ΔVSSA
Ground voltage
Delta to VSS (VSS
-
-100
0
+100
mV
VSSA
)
VREFH
ADC reference
voltage high
1.13
VSSA
VREFL
VDDA
VSSA
—
VDDA
V
V
VREFL
Reference
voltage low
VSSA
VADIN
CADIN
Input voltage
VREFH
V
Input
capacitance
• 16 bit modes
—
—
8
4
10
5
pF
• 8/10/12 bit
modes
RADIN
RAS
Input resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
13/12 bit modes
fADCK < 4MHz
3
—
fADCK
ADC conversion ≤ 13 bit modes
clock frequency
4
4
1.0
2.0
—
—
18.0
12.0
MHz
MHz
fADCK
ADC conversion 16 bit modes
clock frequency
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 27. 16-bit ADC operating conditions (continued)
Typ.1
Symbol Description
Conditions
Min.
Max.
Unit
Notes
Crate
ADC conversion ≤ 13 bit modes
5
rate
No ADC hardware
20.000
—
818.330
Ksps
averaging
Continuous
conversions enabled,
subsequent conversion
time
Crate
ADC conversion 16 bit modes
5
rate
No ADC hardware
37.037
—
461.467
Ksps
averaging
Continuous
conversions enabled,
subsequent conversion
time
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS
/
CAS time constant should be kept to <1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/
files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 13. ADC input impedance equivalency diagram
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
6.6.1.2 16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
IDDA_ADC Supply current
0.215
—
1.7
mA
3
ADC
asynchronous
clock source
• ADLPC=1, ADHSC=0
1.2
3.0
2.4
4.4
2.4
4.0
5.2
6.2
3.9
7.3
6.1
9.5
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
fADACK
Sample Time
See Reference Manual chapter for sample times
LSB4
LSB4
TUE
DNL
Total unadjusted
error
• 12 bit modes
• <12 bit modes
—
—
4
6.8
2.1
5
5
1.4
Differential non-
linearity
• 12 bit modes
—
0.7
-1.1 to
+1.9
-0.3 to 0.5
• <12 bit modes
• 12 bit modes
—
—
0.2
1.0
LSB4
INL
EFS
Integral non-
linearity
-2.7 to
+1.9
5
-0.7 to
+0.5
• <12 bit modes
—
0.5
LSB4
LSB4
Full-scale error
• 12 bit modes
• <12 bit modes
—
—
-4
-5.4
-1.8
VADIN =
VDDA
-1.4
5
EQ
Quantization
error
• 16 bit modes
• ≤13 bit modes
—
—
-1 to 0
—
—
0.5
ENOB
Effective number 16 bit differential mode
6
of bits
• Avg=32
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg=4
16 bit single-ended mode
• Avg=32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg=4
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16 bit differential mode
• Avg=32
7
—
—
–94
-85
—
—
dB
dB
16 bit single-ended mode
• Avg=32
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
44
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
SFDR
Spurious free
dynamic range
16 bit differential mode
• Avg=32
7
82
95
—
dB
16 bit single-ended mode
• Avg=32
78
90
—
dB
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
–40°C to 105°C
25°C
—
—
1.715
719
—
—
mV/°C
mV
VTEMP25 Temp sensor
voltage
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
1 LSB = (VREFH - VREFL)/2N
4.
5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
45
Peripheral operating requirements and behaviors
Figure 14. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Figure 15. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
46
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.1.3 16-bit ADC with PGA operating conditions
Table 29. 16-bit ADC with PGA operating conditions
Typ.1
Symbol Description
VDDA Supply voltage
VREFPGA PGA ref voltage
Conditions
Min.
Max.
Unit
V
Notes
Absolute
1.71
—
3.6
VREF_OU VREF_OU VREF_OU
V
2, 3
T
T
T
VADIN
VCM
Input voltage
VSSA
VSSA
—
—
VDDA
VDDA
V
V
Input Common
Mode range
IN+ to IN-4
RPGAD
Differential input Gain = 1, 2, 4, 8
—
—
—
—
128
64
—
—
—
—
kΩ
impedance
Gain = 16, 32
Gain = 64
32
RAS
TS
Analog source
resistance
100
Ω
µs
5
6
7
ADC sampling
time
1.25
—
—
—
Crate
ADC conversion ≤ 13 bit modes
18.484
450
Ksps
rate
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
16 bit modes
37.037
—
250
Ksps
8
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
47
Peripheral operating requirements and behaviors
6.6.1.4 16-bit ADC with PGA characteristics
Table 30. 16-bit ADC with PGA characteristics
Typ.1
Symbol
Description
Conditions
Min.
Max.
Unit
Notes
IDDA_PGA Supply current
Low power
—
420
644
μA
2
(ADC_PGA[PGALPb]=0)
IDC_PGA
Input DC current
A
3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
—
—
1.54
0.57
—
—
μA
μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
Gain4
G
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
0.95
1.9
1
2
1.05
2.1
R
AS < 100Ω
3.8
4
4.2
7.6
8
8.4
15.2
30.0
58.8
16
31.6
63.3
16.6
33.2
67.8
BW
Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
—
—
—
—
—
4
kHz
kHz
dB
40
—
PSRR
Power supply
rejection ratio
Gain=1
-84
VDDA= 3V
100mV,
fVDDA= 50Hz,
60Hz
CMRR
Common mode
rejection ratio
• Gain=1
—
—
-84
-85
—
—
dB
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
• Gain=64
VOFS
TGSW
EIL
Input offset
voltage
—
—
0.2
—
—
mV
µs
Output offset =
VOFS*(Gain+1)
Gain switching
settling time
10
5
Input leakage
error
All modes
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF
Maximum
V
6
differential input
signal swing
where VX = VREFPGA × 0.583
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
48
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 30. 16-bit ADC with PGA characteristics (continued)
Typ.1
90
Symbol
Description
Conditions
• Gain=1
Min.
80
Max.
—
Unit
dB
Notes
SNR
Signal-to-noise
ratio
16-bit
differential
mode,
• Gain=64
52
66
—
dB
Average=32
THD
SFDR
ENOB
Total harmonic
distortion
• Gain=1
85
49
100
95
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
• Gain=64
Spurious free
dynamic range
• Gain=1
85
53
105
88
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
• Gain=64
Effective number
of bits
• Gain=1, Average=4
• Gain=64, Average=4
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
11.6
7.2
13.4
9.6
—
—
—
—
—
—
—
—
—
bits
bits
bits
bits
bits
bits
bits
bits
bits
16-bit
differential
mode,fin=100H
z
12.8
11.0
7.9
14.5
14.3
13.8
13.1
12.5
11.5
10.6
7.3
6.8
6.8
7.5
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to and ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
Gain = 2PGAG
4.
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 31. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
49
Peripheral operating requirements and behaviors
Table 31. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
VAIO
VH
Analog input voltage
VSS – 0.3
—
—
—
VDD
20
V
Analog input offset voltage
mV
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
120
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
IDAC6b
INL
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
50
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
HYSTCTR
Setting
00
01
10
11
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
51
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 32. 12-bit DAC operating requirements
Symbol
Desciption
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
VDACR
TA
Reference voltage
Temperature
1.13
−40
—
3.6
105
100
1
V
1
°C
pF
mA
CL
Output load capacitance
Output load current
2
IL
—
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
52
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
150
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
μA
P
IDDA_DAC Supply current — high-speed mode
—
—
700
μA
HP
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
—
—
100
15
200
30
1
μs
μs
μs
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
0.7
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
EG
PSRR
TCO
TGE
Gain error
Power supply rejection ratio, VDDA > = 2.4 V
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance load = 3 kΩ
3.7
0.000421
—
—
μV/C
%FSR/C
Ω
6
—
Rop
SR
250
Slew rate -80h→ F7Fh→ 80h
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
0.05
0.12
)
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0+100mV to VDACR−100 mV
3. The DNL is measured for 0+100 mV to VDACR−100 mV
4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
5. Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
53
Peripheral operating requirements and behaviors
6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set
to 0x800, Temp range from -40C to 105C
Figure 18. Typical INL error vs. digital code
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
54
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 19. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 34. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
TA
CL
Temperature
−40
105
°C
nF
Output load capacitance
100
1
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
55
Peripheral operating requirements and behaviors
Table 35. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1965
1.2
1.2027
V
nominal VDDA and temperature=25C
Voltage reference output with— factory trim
Voltage reference trim step
Vout
Vstep
Vtdrift
1.1584
—
—
0.5
—
1.2376
—
V
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Itr
Bandgap only (MODE_LV = 00) current
—
—
—
—
80
µA
mA
mV
Tight-regulation buffer (MODE_LV =10) current
1.1
ΔVLOAD Load regulation (MODE_LV = 10)
• current = + 1.0 mA
1
—
—
2
5
—
—
• current = - 1.0 mA
Tstup
Buffer startup time
—
—
—
2
100
—
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range) (MODE_LV = 10, REGEN = 1)
mV
1. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 36. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
Notes
TA
Temperature
0
50
°C
Table 37. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Vout
Voltage reference output with factory trim
1.173
1.225
V
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
56
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
6.8.2 USB DCD electrical specifications
Table 38. USB DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
0.5
—
0.7
V
VLGC
Threshold voltage for logic high
USB_DP source current
USB_DM sink current
0.8
7
—
10
2.0
13
V
IDP_SRC
IDM_SINK
μA
μA
kΩ
V
50
100
—
150
24.8
0.4
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
0.33
6.8.3 USB VREG electrical specifications
Table 39. USB VREG electrical specifications
Typ.1
Symbol Description
Min.
2.7
—
Max.
5.5
Unit
Notes
VREGIN Input supply voltage
—
V
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
120
186
μA
Quiescent current — Standby mode, load
current equal zero
—
1.27
30
μA
Quiescent current — Shutdown mode
• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature
—
—
650
—
—
4
nA
μA
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.1
2.1
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
57
Peripheral operating requirements and behaviors
Table 39. USB VREG electrical specifications
(continued)
Typ.1
Symbol Description
Min.
1.76
1
Max.
8.16
100
Unit
μF
Notes
COUT
ESR
External output capacitor
2.2
External output capacitor equivalent series
resistance
—
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
6.8.4 CAN switching specifications
See General switching specifications.
6.8.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 40. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
25
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
ns
(tBUS x 2) −
2
—
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
−2
15
0
8.5
—
—
—
ns
ns
ns
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
58
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 20. DSPI classic SPI timing — master mode
Table 41. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
2.7
Frequency of operation
12.5
—
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
10
—
—
—
14
14
2
7
—
—
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 21. DSPI classic SPI timing — slave mode
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
59
Peripheral operating requirements and behaviors
6.8.6 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 42. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
12.5
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
(tSCK/2) - 4 (tSCK/2) + 4
ns
ns
(tBUS x 2) −
4
—
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-4.5
20.5
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 22. DSPI classic SPI timing — master mode
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
60
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 43. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Operating voltage
Frequency of operation
—
6.25
—
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
20
—
—
—
19
19
2
7
—
—
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 23. DSPI classic SPI timing — slave mode
I2C switching specifications
6.8.7
See General switching specifications.
6.8.8 UART switching specifications
See General switching specifications.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
61
Peripheral operating requirements and behaviors
6.8.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 44. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25
20
400
—
—
3
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed)
Clock frequency (MMC full speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
ns
Clock rise time
—
—
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 24. SDHC timing
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
62
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
I2S switching specifications
6.8.10
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
I2S master mode timing
Table 45.
Num
Description
Min.
Max.
Unit
V
Operating voltage
I2S_MCLK cycle time
2.7
2 x tSYS
45%
5 x tSYS
45%
—
3.6
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
ns
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
55%
—
MCLK period
ns
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
55%
15
BCLK period
ns
ns
ns
ns
ns
ns
-2.5
—
—
15
I2S_BCLK to I2S_TXD invalid
-3
—
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
20
—
0
—
S1
S2
S2
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S3
S4
S4
S5
S6
S10
S9
S7
S8
S7
S8
S9
S10
I2S_RXD
Figure 25. I2S timing — master mode
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
63
Peripheral operating requirements and behaviors
I2S slave mode timing
Table 46.
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
I2S_BCLK cycle time (input)
2.7
S11
S12
S13
S14
S15
S16
S17
S18
8 x tSYS
—
ns
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
45%
10
3
55%
—
MCLK period
ns
ns
ns
ns
ns
ns
—
—
0
20
—
10
2
—
I2S_RXD hold after I2S_BCLK
—
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S12
S15
S16
S13
S14
S15
S16
S15
S16
S17
S18
I2S_RXD
Figure 26. I2S timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 47. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE
fREFmax
fELEmax
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
Target electrode capacitance range
Reference oscillator frequency
Electrode oscillator frequency
1
20
5.5
0.5
500
12.7
4.0
pF
1
2
3
—
—
MHz
MHz
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
64
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 47. TSI electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
CREF
VDELTA
IREF
Internal reference capacitor
0.5
1
1.2
pF
Oscillator delta voltage
100
600
760
mV
μA
4
Reference oscillator current source base current
• 1uA setting (REFCHRG=0)
3, 5
—
—
1.133
36
1.5
50
• 32uA setting (REFCHRG=31)
IELE
Electrode oscillator current source base current
• 1uA setting (EXTCHRG=0)
μA
3,6
—
—
1.133
36
1.5
50
• 32uA setting (EXTCHRG=31)
Pres5
Electrode capacitance measurement precision
Electrode capacitance measurement precision
—
8.3333
8.3333
8.3333
12.5
—
38400
38400
38400
—
%
%
7
8
Pres20
—
Pres100 Electrode capacitance measurement precision
MaxSens Maximum sensitivity
—
%
9
0.003
—
fF/count
bits
μs
10
Res
Resolution
16
TCon20
Response time @ 20 pF
8
15
25
11
ITSI_RUN Current added in run mode
ITSI_LP Low power mode current adder
—
—
55
—
μA
1.3
2.5
μA
12
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. CAPTRM=7, DELVOL=7, and fixed external capacitance of 20 pF.
3. CAPTRM=0, DELVOL=2, and fixed external capacitance of 20 pF.
4. CAPTRM=0, EXTCHRG=9, and fixed external capacitance of 20 pF.
5. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
6. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
7. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
8. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
10. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref
* Iext)/( Iref * PS * NSCN). Sensitivity depends on the configuration used. The typical value listed is based on the following
configuration: Iext = 5 μA, EXTCHRG = 4, PS = 128, NSCN = 2, Iref = 16 μA, REFCHRG = 15, Cref = 1.0 pF. The
minimum sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best
sensitivity but is described as a minimum because it’s the smallest number). The minimum sensitivity parameter is based
on the following configuration: Iext = 1 μA, EXTCHRG = 0, PS = 128, NSCN = 32, Iref = 32 μA, REFCHRG = 31, Cref= 0.5
pF
11. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, DELVOL = 2, EXTCHRG = 15.
12. CAPTRM=7, DELVOL=2, REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and
fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
65
Peripheral operating requirements and behaviors
6.9.2 LCD electrical characteristics
Table 48. LCD electricals
Symbol Description
fFrame LCD frame frequency
CLCD
Min.
Typ.
Max.
Unit
Notes
28
30
58
Hz
LCD charge pump capacitance — nominal value
LCD bypass capacitance — nominal value
LCD glass capacitance
—
—
—
100
100
—
—
nF
nF
pF
1
1
2
3
CBYLCD
CGlass
VIREG
2000
8000
VIREG
—
—
—
1.11
1.01
0.91
—
—
—
V
V
V
• HREFSEL=0, RVTRIM=1111
• HREFSEL=0, RVTRIM=1000
• HREFSEL=0, RVTRIM=0000
—
—
—
1.84
1.69
1.54
—
—
—
V
V
V
• HREFSEL=1, RVTRIM=1111
• HREFSEL=1, RVTRIM=1000
• HREFSEL=1, RVTRIM=0000
ΔRTRIM
VIREG TRIM resolution
—
—
3.0
% VIREG
—
VIREG ripple
—
—
—
—
30
50
mV
mV
• HREFSEL = 0
• HREFSEL = 1
IVIREG
IRBIAS
VIREG current adder — RVEN = 1
RBIAS current adder
—
1
—
µA
4
—
—
10
1
—
—
µA
µA
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
RRBIAS
RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
—
—
0.28
2.98
—
—
MΩ
MΩ
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
VLL2
VLL3
VLL2 voltage
• HREFSEL = 0
• HREFSEL = 1
2.0 − 5%
3.3 − 5%
2.0
3.3
—
—
V
V
VLL3 voltage
• HREFSEL = 0
• HREFSEL = 1
3.0 − 5%
5 − 5%
3.0
5
—
—
V
V
1. The actual value used could vary with tolerance.
2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter
within the device's reference manual.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
66
Freescale Semiconductor, Inc.
Dimensions
3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
4. 2000 pF load LCD, 32 Hz frame frequency
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
144-pin LQFP
Then use this document number
98ASS23177W
98ASA00222D
144-pin MAPBGA
8 Pinout
8.1 K40 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQF MAP
P
—
—
1
BGA
L5
RESERVED RESERVED RESERVED
M5
D3
NC
NC
NC
PTE0
ADC1_SE4
a
ADC1_SE4
a
PTE0
SPI1_PCS1 UART1_TX
SDHC0_D1 FB_AD27
I2C1_SDA
I2C1_SCL
2
3
4
D2
D1
E4
PTE1
PTE2
PTE3
ADC1_SE5
a
ADC1_SE5
a
PTE1
PTE2
PTE3
SPI1_SOUT UART1_RX SDHC0_D0 FB_AD26
ADC1_SE6
a
ADC1_SE6
a
SPI1_SCK
SPI1_SIN
UART1_CT
S_b
SDHC0_DC FB_AD25
LK
ADC1_SE7
a
ADC1_SE7
a
UART1_RT
S_b
SDHC0_CM FB_AD24
D
5
6
7
E5
F6
E3
VDD
VSS
VDD
VDD
VSS
VSS
PTE4
DISABLED
PTE4
SPI1_PCS0 UART3_TX
SDHC0_D3 FB_CS3_b/
FB_BE7_0_
FB_TA_b
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
67
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQF MAP
P
BGA
BLS31_24_
b
8
E2
PTE5
PTE6
DISABLED
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2 FB_TBST_b
/FB_CS2_b/
FB_BE15_8
_BLS23_16
_b
9
E1
PTE6
SPI1_PCS3 UART3_CT
S_b
I2S0_MCLK FB_ALE/
FB_CS1_b/
I2S0_CLKIN
FB_TS_b
10
11
12
13
14
15
F4
F3
F2
F1
G4
G3
PTE7
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTE7
UART3_RT
S_b
I2S0_RXD
FB_CS0_b
FB_AD4
PTE8
PTE8
UART5_TX
I2S0_RX_F
S
PTE9
PTE9
UART5_RX I2S0_RX_B FB_AD3
CLK
PTE10
PTE11
PTE12
PTE10
PTE11
PTE12
UART5_CT
S_b
I2S0_TXD
FB_AD2
FB_AD1
FB_AD0
UART5_RT
S_b
I2S0_TX_F
S
I2S0_TX_B
CLK
16
17
18
19
20
21
22
23
24
25
26
27
E6
F7
H3
H1
H2
G1
G2
J1
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
J2
ADC0_DM1 ADC0_DM1 ADC0_DM1
ADC1_DP1 ADC1_DP1 ADC1_DP1
ADC1_DM1 ADC1_DM1 ADC1_DM1
PGA0_DP/ PGA0_DP/ PGA0_DP/
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
K1
K2
L1
ADC1_DP3
ADC1_DP3
ADC1_DP3
28
29
30
L2
M1
M2
PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
PGA0_DM/
PGA0_DM/
PGA1_DP/
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3
PGA1_DM/
PGA1_DP/
PGA1_DP/
ADC0_DP3
PGA1_DM/
ADC0_DP3
PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
31
32
H5
G5
VDDA
VDDA
VDDA
VREFH
VREFH
VREFH
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
68
Freescale Semiconductor, Inc.
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQF MAP
P
BGA
G6
33
34
35
VREFL
VSSA
VREFL
VREFL
H6
VSSA
VSSA
K3
ADC1_SE1
6/
ADC1_SE1
6/
ADC1_SE1
6/
CMP2_IN2/
ADC0_SE2
2
CMP2_IN2/
ADC0_SE2
2
CMP2_IN2/
ADC0_SE2
2
36
37
J3
ADC0_SE1
6/
CMP1_IN2/
ADC0_SE2
1
ADC0_SE1
6/
CMP1_IN2/
ADC0_SE2
1
ADC0_SE1
6/
CMP1_IN2/
ADC0_SE2
1
M3
VREF_OUT/ VREF_OUT/ VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
38
39
L3
L4
DAC0_OUT/ DAC0_OUT/ DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
CMP1_IN3/
ADC0_SE2
3
CMP1_IN3/
ADC0_SE2
3
DAC1_OUT/ DAC1_OUT/ DAC1_OUT/
CMP2_IN3/
ADC1_SE2
3
CMP2_IN3/
ADC1_SE2
3
CMP2_IN3/
ADC1_SE2
3
40
41
42
43
44
45
M7
M6
L6
—
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
VDD
VDD
VDD
—
VSS
VSS
VSS
M4
PTE24
ADC0_SE1
7
ADC0_SE1
7
PTE24
CAN1_TX
CAN1_RX
UART4_TX
UART4_RX
EWM_OUT
_b
46
47
48
K5
K4
J4
PTE25
PTE26
PTE27
ADC0_SE1
8
ADC0_SE1
8
PTE25
PTE26
PTE27
FB_AD23
FB_AD22
FB_AD21
FB_AD20
EWM_IN
DISABLED
DISABLED
DISABLED
UART4_CT
S_b
RTC_CLKO USB_CLKIN
UT
UART4_RT
S_b
49
50
H4
J5
PTE28
PTA0
PTE28
PTA0
JTAG_TCL
K/
SWD_CLK/
EZP_CLK
TSI0_CH1
TSI0_CH2
UART0_CT
S_b
FTM0_CH5
JTAG_TCL
K/
SWD_CLK
EZP_CLK
51
52
J6
PTA1
PTA2
JTAG_TDI/
EZP_DI
PTA1
PTA2
UART0_RX FTM0_CH6
JTAG_TDI
EZP_DI
K6
JTAG_TDO/ TSI0_CH3
TRACE_SW
O/EZP_DO
UART0_TX
FTM0_CH7
JTAG_TDO/ EZP_DO
TRACE_SW
O
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
69
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQF MAP
P
BGA
53
K7
PTA3
PTA4
PTA5
JTAG_TMS/ TSI0_CH4
SWD_DIO
PTA3
UART0_RT
S_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
JTAG_TMS/
SWD_DIO
54
55
L7
NMI_b/
TSI0_CH5
PTA4
PTA5
NMI_b
EZP_CS_b
EZP_CS_b
M8
DISABLED
CMP2_OUT I2S0_RX_B JTAG_TRS
CLK
T
56
57
58
E7
G7
J7
VDD
VSS
VDD
VDD
VSS
VSS
PTA6
DISABLED
PTA6
PTA7
PTA8
PTA9
PTA10
PTA11
PTA12
FTM0_CH3
FTM0_CH4
FTM1_CH0
FTM1_CH1
FTM2_CH0
FTM2_CH1
FTM1_CH0
FB_CLKOU
T
TRACE_CL
KOUT
59
60
61
62
63
64
J8
K8
L8
M9
L9
K9
PTA7
ADC0_SE1
0
ADC0_SE1
0
FB_AD18
FB_AD17
FB_AD16
FB_AD15
FB_OE_b
TRACE_D3
PTA8
ADC0_SE1
1
ADC0_SE1
1
FTM1_QD_ TRACE_D2
PHA
PTA9
DISABLED
DISABLED
DISABLED
CMP2_IN0
FTM1_QD_ TRACE_D1
PHB
PTA10
PTA11
PTA12
FTM2_QD_ TRACE_D0
PHA
FTM2_QD_
PHB
CMP2_IN0
CMP2_IN1
CAN0_TX
CAN0_RX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_1
6_BLS15_8
_b
I2S0_TXD
FTM1_QD_
PHA
65
J9
PTA13
CMP2_IN1
PTA13
FTM1_CH1
FB_CS4_b/
FB_TSIZ0/
FB_BE31_2
4_BLS7_0_
b
I2S0_TX_F
S
FTM1_QD_
PHB
66
L10 PTA14
DISABLED
PTA14
SPI0_PCS0 UART0_TX
FB_AD31
I2S0_TX_B
CLK
67
68
L11 PTA15
K10 PTA16
DISABLED
DISABLED
PTA15
PTA16
SPI0_SCK
UART0_RX
FB_AD30
FB_AD29
I2S0_RXD
SPI0_SOUT UART0_CT
S_b
I2S0_RX_F
S
69
K11 PTA17
ADC1_SE1
7
ADC1_SE1
7
PTA17
SPI0_SIN
UART0_RT
S_b
FB_AD28
I2S0_MCLK I2S0_CLKIN
70
71
72
E8
G8
VDD
VSS
VDD
VDD
VSS
VSS
M12 PTA18
EXTAL
EXTAL
PTA18
PTA19
FTM0_FLT2 FTM_CLKIN
0
73
M11 PTA19
XTAL
XTAL
FTM1_FLT0 FTM_CLKIN
1
LPT0_ALT1
74
75
76
77
L12 RESET_b
K12 PTA24
J12 PTA25
J11 PTA26
RESET_b
DISABLED
DISABLED
DISABLED
RESET_b
PTA24
PTA25
PTA26
FB_AD14
FB_AD13
FB_AD12
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
70
Freescale Semiconductor, Inc.
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQF MAP
P
BGA
78
79
80
81
J10 PTA27
H12 PTA28
H11 PTA29
H10 PTB0
DISABLED
DISABLED
DISABLED
LCD_P0/
ADC0_SE8/ ADC0_SE8/
ADC1_SE8/ ADC1_SE8/
TSI0_CH0
PTA27
FB_AD11
FB_AD10
FB_AD19
PTA28
PTA29
PTB0
LCD_P0/
I2C0_SCL
I2C0_SDA
FTM1_CH0
FTM1_CH1
FTM1_QD_ LCD_P0
PHA
TSI0_CH0
82
H9
PTB1
LCD_P1/
ADC0_SE9/ ADC0_SE9/
ADC1_SE9/ ADC1_SE9/
LCD_P1/
PTB1
FTM1_QD_ LCD_P1
PHB
TSI0_CH6
TSI0_CH6
83
84
85
86
87
88
G12 PTB2
G11 PTB3
G10 PTB4
LCD_P2/
ADC0_SE1
2/TSI0_CH7 2/TSI0_CH7
LCD_P2/
ADC0_SE1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
I2C0_SCL
I2C0_SDA
UART0_RT
S_b
FTM0_FLT3 LCD_P2
FTM0_FLT0 LCD_P3
FTM1_FLT0 LCD_P4
FTM2_FLT0 LCD_P5
LCD_P6
LCD_P3/
ADC0_SE1
3/TSI0_CH8 3/TSI0_CH8
LCD_P3/
ADC0_SE1
UART0_CT
S_b
LCD_P4/
ADC1_SE1
0
LCD_P4/
ADC1_SE1
0
G9
PTB5
LCD_P5/
ADC1_SE1
1
LCD_P5/
ADC1_SE1
1
F12 PTB6
F11 PTB7
F10 PTB8
LCD_P6/
ADC1_SE1
2
LCD_P6/
ADC1_SE1
2
LCD_P7/
ADC1_SE1
3
LCD_P7/
ADC1_SE1
3
LCD_P7
89
90
91
LCD_P8
LCD_P8
PTB8
PTB9
PTB10
UART3_RT
S_b
LCD_P8
LCD_P9
F9
PTB9
LCD_P9
LCD_P9
SPI1_PCS1 UART3_CT
S_b
E12 PTB10
E11 PTB11
LCD_P10/
ADC1_SE1
4
LCD_P10/
ADC1_SE1
4
SPI1_PCS0 UART3_RX
FTM0_FLT1 LCD_P10
92
LCD_P11/
ADC1_SE1
5
LCD_P11/
ADC1_SE1
5
PTB11
SPI1_SCK
UART3_TX
FTM0_FLT2 LCD_P11
93
94
95
H7
F5
VSS
VDD
VSS
VDD
VSS
VDD
E10 PTB16
LCD_P12/
TSI0_CH9
LCD_P12/
TSI0_CH9
PTB16
PTB17
PTB18
SPI1_SOUT UART0_RX
EWM_IN
LCD_P12
LCD_P13
96
97
E9
PTB17
LCD_P13/
LCD_P13/
SPI1_SIN
CAN0_TX
UART0_TX
FTM2_CH0
EWM_OUT
_b
TSI0_CH10 TSI0_CH10
LCD_P14/ LCD_P14/
TSI0_CH11 TSI0_CH11
D12 PTB18
I2S0_TX_B
CLK
FTM2_QD_ LCD_P14
PHA
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
71
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQF MAP
P
BGA
98
D11 PTB19
LCD_P15/
TSI0_CH12 TSI0_CH12
LCD_P15/
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_F
S
FTM2_QD_ LCD_P15
PHB
99
D10 PTB20
LCD_P16
LCD_P17
LCD_P18
LCD_P19
LCD_P16
LCD_P17
LCD_P18
LCD_P19
PTB20
PTB21
PTB22
PTB23
PTC0
SPI2_PCS0
SPI2_SCK
SPI2_SOUT
SPI2_SIN
CMP0_OUT LCD_P16
CMP1_OUT LCD_P17
CMP2_OUT LCD_P18
LCD_P19
100
101
102
103
D9
PTB21
C12 PTB22
C11 PTB23
B12 PTC0
SPI0_PCS5
LCD_P20/
ADC0_SE1
4/
LCD_P20/
ADC0_SE1
4/
SPI0_PCS4 PDB0_EXT
RG
I2S0_TXD
FTM0_CH0
FTM0_CH1
LCD_P20
TSI0_CH13 TSI0_CH13
104
105
B11 PTC1
A12 PTC2
LCD_P21/
ADC0_SE1
5/
LCD_P21/
ADC0_SE1
5/
PTC1
PTC2
SPI0_PCS3 UART1_RT
S_b
LCD_P21
LCD_P22
TSI0_CH14 TSI0_CH14
LCD_P22/
ADC0_SE4
b/
LCD_P22/
ADC0_SE4
b/
SPI0_PCS2 UART1_CT
S_b
CMP1_IN0/
CMP1_IN0/
TSI0_CH15 TSI0_CH15
106
A11 PTC3
LCD_P23/
CMP1_IN1
LCD_P23/
CMP1_IN1
PTC3
SPI0_PCS1 UART1_RX FTM0_CH2
LCD_P23
107
108
109
110
111
112
113
114
115
H8
VSS
VSS
VSS
C10 VLL3
VLL3
VLL3
C9
B9
VLL2
VLL1
VLL2
VLL2
VLL1
VLL1
B10 VCAP2
A10 VCAP1
VCAP2
VCAP1
LCD_P24
LCD_P25
VCAP2
VCAP1
LCD_P24
LCD_P25
A9
D8
C8
PTC4
PTC5
PTC6
PTC4
PTC5
PTC6
SPI0_PCS0 UART1_TX
SPI0_SCK
FTM0_CH3
LPT0_ALT2
CMP1_OUT LCD_P24
CMP0_OUT LCD_P25
LCD_P26
LCD_P26/
CMP0_IN0
LCD_P26/
CMP0_IN0
SPI0_SOUT PDB0_EXT
RG
116
117
B8
A8
PTC7
PTC8
LCD_P27/
CMP0_IN1
LCD_P27/
CMP0_IN1
PTC7
PTC8
SPI0_SIN
LCD_P27
LCD_P28
LCD_P28/
ADC1_SE4
b/
LCD_P28/
ADC1_SE4
b/
I2S0_MCLK I2S0_CLKIN
CMP0_IN2
CMP0_IN2
118
119
120
D7
C7
B7
PTC9
LCD_P29/
ADC1_SE5
b/
LCD_P29/
ADC1_SE5
b/
PTC9
I2S0_RX_B
CLK
FTM2_FLT0 LCD_P29
LCD_P30
CMP0_IN3
CMP0_IN3
PTC10
PTC11
LCD_P30/
ADC1_SE6
b/
LCD_P30/
ADC1_SE6
b/
PTC10
PTC11
I2C1_SCL
I2C1_SDA
I2S0_RX_F
S
CMP0_IN4
CMP0_IN4
LCD_P31/
ADC1_SE7
b
LCD_P31/
ADC1_SE7
b
I2S0_RXD
LCD_P31
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
72
Freescale Semiconductor, Inc.
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQF MAP
P
BGA
121
A7
PTC12
PTC13
LCD_P32
LCD_P33
LCD_P32
LCD_P33
PTC12
UART4_RT
S_b
LCD_P32
LCD_P33
122
D6
PTC13
UART4_CT
S_b
123
124
125
126
127
C6
B6
A6
D5
C5
PTC14
PTC15
PTC16
PTC17
PTC18
LCD_P34
LCD_P35
LCD_P36
LCD_P37
LCD_P38
LCD_P34
LCD_P35
LCD_P36
LCD_P37
LCD_P38
PTC14
PTC15
PTC16
PTC17
PTC18
UART4_RX
UART4_TX
UART3_RX
UART3_TX
LCD_P34
LCD_P35
LCD_P36
LCD_P37
LCD_P38
CAN1_RX
CAN1_TX
UART3_RT
S_b
128
129
130
B5
A5
D4
PTC19
PTD0
PTD1
LCD_P39
LCD_P40
LCD_P39
LCD_P40
PTC19
PTD0
PTD1
UART3_CT
S_b
LCD_P39
LCD_P40
LCD_P41
SPI0_PCS0 UART2_RT
S_b
LCD_P41/
ADC0_SE5
b
LCD_P41/
ADC0_SE5
b
SPI0_SCK
UART2_CT
S_b
131
132
133
C4
B4
A4
PTD2
PTD3
PTD4
LCD_P42
LCD_P43
LCD_P44
LCD_P42
LCD_P43
LCD_P44
PTD2
PTD3
PTD4
SPI0_SOUT UART2_RX
SPI0_SIN UART2_TX
LCD_P42
LCD_P43
LCD_P44
SPI0_PCS1 UART0_RT
S_b
FTM0_CH4
FTM0_CH5
EWM_IN
134
135
A3
A2
PTD5
PTD6
LCD_P45/
ADC0_SE6
b
LCD_P45/
ADC0_SE6
b
PTD5
PTD6
SPI0_PCS2 UART0_CT
S_b
EWM_OUT
_b
LCD_P45
LCD_P46/
ADC0_SE7
b
LCD_P46/
ADC0_SE7
b
SPI0_PCS3 UART0_RX FTM0_CH6
FTM0_FLT0 LCD_P46
FTM0_FLT1 LCD_P47
136
137
138
139
M10 VSS
VSS
VSS
F8
A1
B3
VDD
VDD
VDD
PTD7
PTD10
LCD_P47
DISABLED
LCD_P47
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
PTD10
UART5_RT
S_b
FB_AD9
140
B2
PTD11
DISABLED
PTD11
SPI2_PCS0 UART5_CT
S_b
SDHC0_CL FB_AD8
KIN
141
142
143
144
B1
C3
C2
C1
PTD12
PTD13
PTD14
PTD15
DISABLED
DISABLED
DISABLED
DISABLED
PTD12
PTD13
PTD14
PTD15
SPI2_SCK
SPI2_SOUT
SPI2_SIN
SDHC0_D4 FB_AD7
SDHC0_D5 FB_AD6
SDHC0_D6 FB_AD5
SDHC0_D7 FB_RW_b
SPI2_PCS1
8.2 K40 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
73
Pinout
PTE0
PTE1
1
108
107
106
105
104
103
102
101
100
99
VLL3
2
VSS
PTE2
3
PTC3
PTC2
PTC1
PTC0
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
PTE3
4
VDD
5
VSS
6
PTE4
7
PTE5
8
PTE6
9
PTE7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PTE8
98
PTE9
97
PTE10
PTE11
PTE12
VDD
96
95
94
VSS
93
VSS
PTB11
PTB10
PTB9
92
VSS
91
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
90
PTB8
89
PTB7
88
PTB6
87
PTB5
86
PTB4
85
PTB3
84
PTB2
83
PGA0_DP/ADC0_DP0/ADC1_DP3
PGA0_DM/ADC0_DM0/ADC1_DM3
PGA1_DP/ADC1_DP0/ADC0_DP3
PGA1_DM/ADC1_DM0/ADC0_DM3
VDDA
PTB1
82
PTB0
81
PTA29
PTA28
PTA27
PTA26
PTA25
PTA24
RESET_b
PTA19
80
79
78
VREFH
77
VREFL
76
VSSA
75
ADC1_SE16/CMP2_IN2/ADC0_SE22
ADC0_SE16/CMP1_IN2/ADC0_SE21
74
73
Figure 27. K40 144 LQFP Pinout Diagram
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
74
Freescale Semiconductor, Inc.
Revision History
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
PTC8
PTC4
VCAP1
PTC3
PTC2
PTC0
A
B
C
D
E
F
PTD7
PTD6
PTD5
PTD4
PTD0
PTC16
PTC12
PTD12
PTD15
PTD11
PTD14
PTD10
PTD13
PTE0
PTE4
PTE8
PTE12
VSS
PTD3
PTD2
PTD1
PTE3
PTC19
PTC18
PTC17
VDD
PTC15
PTC14
PTC13
VDD
PTC11
PTC10
PTC9
VDD
PTC7
PTC6
PTC5
VDD
VLL1
VLL2
VCAP2
VLL3
PTC1
PTB23
PTB19
PTB11
PTB7
PTB22
PTB18
PTB10
PTB6
PTE2
PTE1
PTB21
PTB17
PTB9
PTB20
PTB16
PTB8
PTE6
PTE5
PTE10
PTE9
PTE7
VDD
VSS
VSS
VDD
G
H
J
G
H
J
VOUT33
USB0_DP
ADC0_DP1
VREGIN
USB0_DM
ADC0_DM1
ADC1_DM1
PTE11
PTE28
PTE27
PTE26
VREFH
VDDA
VREFL
VSSA
PTA1
PTA2
VBAT
VSS
VSS
PTB5
PTB4
PTB3
PTB2
VSS
VSS
PTB1
PTB0
PTA29
PTA26
PTA17
PTA15
PTA28
PTA25
PTA24
RESET_b
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
PTA0
PTA6
PTA3
PTA4
PTA7
PTA8
PTA9
PTA13
PTA12
PTA11
PTA27
PTA16
PTA14
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
K
L
K
L
ADC1_DP1
PGA0_DP/
PTE25
RESERVED
PGA0_DM/ DAC0_OUT/ DAC1_OUT/
CMP2_IN3/
ADC0_DP0/ ADC0_DM0/ CMP1_IN3/
ADC1_DP3
ADC1_DM3 ADC0_SE23 ADC1_SE23
VREF_OUT/
PGA1_DM/
PGA1_DP/
CMP1_IN5/
M
M
ADC1_DP0/ ADC1_DM0/
PTE24
NC
EXTAL32
XTAL32
PTA5
PTA10
VSS
PTA19
PTA18
CMP0_IN5/
ADC1_SE18
ADC0_DP3
ADC0_DM3
1
2
3
4
5
6
7
8
9
10
11
12
Figure 28. K40 144 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Table 49. Revision History
Rev. No.
Date
Substantial Changes
1
11/2010
Initial public revision
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
75
Revision History
Table 49. Revision History (continued)
Rev. No.
Date
3/2011
3/2011
3/2011
Substantial Changes
2
3
4
Many updates throughout
Added sections that were inadvertently removed in previous revision
Reworded IIC footnote in "Voltage and Current Operating Requirements" table.
Added paragraph to "Peripheral operating requirements and behaviors" section.
Added "JTAG full voltage range electricals" table to the "JTAG electricals" section.
5
6/2011
• Changed supported part numbers per new part number scheme
• Changed DC injection current specs in "Voltage and current operating requirements"
table
• Changed Input leakage current and internal pullup/pulldown resistor specs in "Voltage
and current operating behaviors" table
• Split Low power stop mode current specs by temperature range in "Power
consumption operating behaviors" table
• Changed typical IDD_VBAT spec in "Power consumption operating behaviors" table
• Added LPTMR clock specs to "Device clock specifications" table
• Changed Minimum external reset pulse width in "General switching specifications"
table
• Changed PLL operating current in "MCG specifications" table
• Added footnote to PLL period jitter in "MCG specifications" table
• Changed Supply current in "Oscillator DC electrical specifications" table
• Changed Crystal startup time in "Oscillator frequency specifications" table
• Changed Operating voltage in "EzPort switching specifications" table
• Changed title of "FlexBus switching specifications" table and added Output valid and
hold specs
• Added "FlexBus full range switching specifications" table
• Changed ADC asynchronous clock source specs in "16-bit ADC characteristics" table
• Changed Gain spec in "16-bit ADC with PGA characteristics" table
• Added typical Input DC current to "16-bit ADC with PGA characteristics" table
• Changed Input offset voltage and ENOB notes field in "16-bit ADC with PGA
characteristics" table
• Changed Analog comparator initialization delay in "Comparator and 6-bit DAC
electrical specifications"
• Changed Code-to-code settling time, DAC output voltage range low, and Temperature
coefficient offset voltage in "12-bit DAC operating behaviors" table
• Changed Temperature drift and Load regulation in "VREF full-range operating
behaviors" table
• Changed Regulator output voltage in "USB VREG electrical specifications" table
• Changed ILIM description and specs in "USB VREG electrical specifications" table
• Changed DSPI_SCK cycle time specs in "DSPI timing" tables
• Changed DSPI_SS specs in "Slave mode DSPI timing (low-speed mode)" table
• Changed DSPI_SCK to DSPI_SOUT valid spec in "Slave mode DSPI timing (high-
speed mode)" table
• Changed Reference oscillator current source base current spec and added Low-
power current adder footer in "TSI electrical specifications" table
• Added LCD glass capacitance footnote
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
76
Freescale Semiconductor, Inc.
Revision History
Table 49. Revision History (continued)
Rev. No.
Date
Substantial Changes
6
9/2011
• Added AC electrical specifications.
• Replaced TBDs with silicon data throughout.
• In "Power mode transition operating behaviors" table, removed entry times.
• Updated "EMC radiated emissions operating behaviors" to remove SAE level and also
added data for 144LQFP.
• Clarified "EP7" in "EzPort switching specifications" table and "EzPort Timing Diagram".
• Added "ENOB vs. ADC_CLK for 16-bit differential and 16-bit single-ended modes"
figures.
• Updated IDD_RUN numbers in 'Power consumption operating behaviors' section.
• Clarified 'Diagram: Typical IDD_RUN operating behavior' section and updated 'Run
mode supply current vs. core frequency — all peripheral clocks disabled' figure.
• In 'Voltage reference electrical specifications' section, updated CL, Vtdrift, and Vvdrift
values.
• In 'USB electrical specifications' section, updated VDP_SRC, IDDstby, and 'VReg33out
values.
• In 'LCD electrical characteristics' section, updated VIREG and ΔRTRIM values.
K40 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
77
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Document Number: K40P144M100SF2
Rev. 6, 9/2011
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