MKL15Z128VLK4 [FREESCALE]
KL15 Sub-Family Data Sheet; KL15子系列数据手册
| 型号： | MKL15Z128VLK4 |
| 厂家： | 
Freescale |
| 描述： | KL15 Sub-Family Data Sheet |
| 文件： | 总52页 (文件大小：1773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: KL15P80M48SF0
Rev. 3, 9/19/2012
Freescale Semiconductor
Data Sheet: Technical Data
KL15P80M48SF0
KL15 Sub-Family Data Sheet
Supports the following:
MKL15Z32VFM4, MKL15Z64VFM4,
MKL15Z128VFM4, MKL15Z32VFT4,
MKL15Z64VFT4, MKL15Z128VFT4,
MKL15Z32VLH4, MKL15Z64VLH4,
MKL15Z128VLH4, MKL15Z32VLK4,
MKL15Z64VLK4 and MKL15Z128VLK4
Features
Security and integrity modules
– 80-bit unique identification (ID) number per chip
•
•
Operating Characteristics
– Voltage range: 1.71 to 3.6 V
•
Human-machine interface
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
Performance
– Up to 48 MHz ARM® Cortex-M0+ core
•
•
Analog modules
– 16-bit SAR ADC
– 12-bit DAC
– Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
•
•
Memories and memory interfaces
– Up to 128 KB program flash memory
– Up to 16 KB RAM
Clocks
Timers
•
•
– 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal
oscillator
– Multi-purpose clock source
– Six channel Timer/PWM (TPM)
– Two 2-channel Timer/PWM (TPM)
– Periodic interrupt timers
– 16-bit low-power timer (LPTMR)
– Real-time clock
System peripherals
– Nine low-power modes to provide power
optimization based on application requirements
– 4-channel DMA controller, supporting up to 63
request sources
Communication interfaces
– Two 8-bit SPI modules
– Two I2C modules
•
– COP Software watchdog
– Low-leakage wakeup unit
– One low power UART module
– Two UART modules
– SWD interface and Micro Trace buffer
– Bit Manipulation Engine (BME)
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................3
5.3 Switching specifications.....................................................21
5.3.1 Device clock specifications...................................21
5.3.2 General Switching Specifications..........................22
5.4 Thermal specifications.......................................................22
5.4.1 Thermal operating requirements...........................22
5.4.2 Thermal attributes.................................................22
6 Peripheral operating requirements and behaviors....................23
6.1 Core modules....................................................................23
6.1.1 SWD Electricals ...................................................23
6.2 System modules................................................................25
6.3 Clock modules...................................................................25
6.3.1 MCG specifications...............................................25
6.3.2 Oscillator electrical specifications.........................27
6.4 Memories and memory interfaces.....................................29
6.4.1 Flash electrical specifications................................29
6.5 Security and integrity modules..........................................30
6.6 Analog...............................................................................31
6.6.1 ADC electrical specifications.................................31
6.6.2 CMP and 6-bit DAC electrical specifications.........35
6.6.3 12-bit DAC electrical characteristics.....................36
6.7 Timers................................................................................39
6.8 Communication interfaces.................................................39
6.8.1 SPI switching specifications..................................39
6.8.2 I2C.........................................................................43
6.8.3 UART....................................................................43
6.9 Human-machine interfaces (HMI)......................................44
6.9.1 TSI electrical specifications...................................44
7 Dimensions...............................................................................44
7.1 Obtaining package dimensions.........................................44
8 Pinout........................................................................................44
8.1 KL15 Signal Multiplexing and Pin Assignments................44
8.2 KL15 Pinouts.....................................................................47
9 Revision History........................................................................51
1.1 Determining valid orderable parts......................................3
2 Part identification......................................................................3
2.1 Description.........................................................................3
2.2 Format...............................................................................3
2.3 Fields.................................................................................3
2.4 Example............................................................................4
3 Terminology and guidelines......................................................4
3.1 Definition: Operating requirement......................................4
3.2 Definition: Operating behavior...........................................4
3.3 Definition: Attribute............................................................5
3.4 Definition: Rating...............................................................5
3.5 Result of exceeding a rating..............................................6
3.6 Relationship between ratings and operating
requirements......................................................................6
3.7 Guidelines for ratings and operating requirements............7
3.8 Definition: Typical value.....................................................7
3.9 Typical Value Conditions...................................................8
4 Ratings......................................................................................8
4.1 Thermal handling ratings...................................................8
4.2 Moisture handling ratings..................................................9
4.3 ESD handling ratings.........................................................9
4.4 Voltage and current operating ratings...............................9
5 General.....................................................................................9
5.1 AC electrical characteristics..............................................9
5.2 Nonswitching electrical specifications...............................10
5.2.1 Voltage and current operating requirements.........10
5.2.2 LVD and POR operating requirements.................11
5.2.3 Voltage and current operating behaviors..............12
5.2.4 Power mode transition operating behaviors..........13
5.2.5 Power consumption operating behaviors..............13
5.2.6 EMC radiated emissions operating behaviors.......20
5.2.7 Designing with radiated emissions in mind...........21
5.2.8 Capacitance attributes..........................................21
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
2
Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.freescale.com and perform a part number search for
the following device numbers: PKL15 and MKL15
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KL##
A
Kinetis family
Key attribute
• KL15
• Z = Cortex-M0+
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
3
Terminology and guidelines
Field
Description
Values
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• LK = 80 LQFP (12 mm x 12 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 4 = 48 MHz
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MKL15Z32VFT4
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
4
Freescale Semiconductor, Inc.
Terminology and guidelines
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
5
Terminology and guidelines
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
6
Freescale Semiconductor, Inc.
Terminology and guidelines
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
7
Ratings
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
4 Ratings
4.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
8
Freescale Semiconductor, Inc.
General
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
1
2
V
-100
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
120
mA
V
VDIO
VAIO
ID
Digital pin input voltage (except RESET)
Analog pins1and RESET pin input voltage
–0.3
–0.3
–25
3.6
VDD + 0.3
25
V
Instantaneous maximum current single pin limit (applies to all
port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
9
General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assumes:
1. output pins
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
Input hysteresis
0.06 × VDD
—
V
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
10
Freescale Semiconductor, Inc.
General
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IICDIO
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
-5
—
mA
IICAIO
Analog2 pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
3
mA
-5
—
—
+5
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
V
• Negative current injection
• Positive current injection
+25
VRAM
VDD voltage required to retain RAM
1.2
—
1. All digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If
VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor
is calculated as R=(VDIO_MIN-VIN)/|IIC|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN
(=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is
calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
60
—
mV
V
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
11
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
40
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
5.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -1.5 mA
1
VDD – 0.5
VDD – 0.5
—
—
V
V
VOH
Output high voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -6 mA
1
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
100
mA
1
1
—
—
0.5
0.5
V
V
VOL
Output low voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
—
—
100
1
mA
μA
Input leakage current (per pin) for full temperature
range
2
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
65
μA
μA
2
2
Input leakage current (total all pins) for full temperature
range
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
12
Freescale Semiconductor, Inc.
General
Table 3. Voltage and current operating behaviors (continued)
Symbol
RPU
Description
Min.
20
Max.
50
Unit
kΩ
Notes
Internal pullup resistors
Internal pulldown resistors
3
4
RPD
20
50
kΩ
1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
Table 4. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR After a POR event, amount of time from the point
—
—
300
μs
VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• LLS → RUN
—
—
—
—
—
—
95
93
42
4
115
115
53
μs
μs
μs
μs
μs
μs
4.6
4.4
4.4
• VLPS → RUN
• STOP → RUN
4
4
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
13
General
5.2.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUNCO_ Run mode current in compute operation - 48
MHz core / 24 MHz flash/ bus disabled, LPTMR
CM
running using 4MHz internal reference clock,
CoreMark® benchmark code executing from
flash
—
6.4
—
mA
• at 3.0 V
IDD_RUNCO Run mode current in compute operation - 48
MHz core / 24 MHz flash / bus clock disabled,
code of while(1) loop executing from flash
3
3
—
—
4.1
5.1
5.2
6.3
mA
mA
• at 3.0 V
IDD_RUN Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks disabled, code of
while(1) loop executing from flash
• at 3.0 V
IDD_RUN Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks enabled, code of
while(1) loop executing from flash
3, 4,
• at 3.0 V
• at 25 °C
• at 125 °C
—
—
6.4
6.8
7.8
8.3
mA
mA
IDD_WAIT Wait mode current - core disabled / 48 MHz
system / 24 MHz bus / flash disabled (flash doze
enabled), all peripheral clocks disabled
• at 3.0 V
3
3
3
5
—
—
—
—
3.7
2.9
2.5
188
5.0
4.2
3.7
570
mA
mA
mA
μA
IDD_WAIT Wait mode current - core disabled / 24 MHz
system / 24 MHz bus / flash disabled (flash doze
enabled), all peripheral clocks disabled
• at 3.0 V
IDD_PSTOP2 Stop mode current with partial stop 2 clocking
option - core and system disabled / 10.5 MHz
bus
• at 3.0 V
IDD_VLPRCO Very low power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus
clock disabled, code of while(1) loop executing
from flash
• at 3.0 V
IDD_VLPR Very low power run mode current - 4 MHz core /
5
—
224
613
μA
0.8 MHz bus and flash, all peripheral clocks
disabled, code of while(1) loop executing from
flash
• at 3.0 V
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
14
Freescale Semiconductor, Inc.
General
Table 5. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPR Very low power run mode current - 4 MHz core /
5, 4
—
300
745
μA
0.8 MHz bus and flash, all peripheral clocks
enabled, code of while(1) loop executing from
flash
• at 3.0 V
IDD_VLPW Very low power wait mode current - core
disabled / 4 MHz system / 0.8 MHz bus / flash
disabled (flash doze enabled), all peripheral
clocks disabled
—
135
496
μA
5
• at 3.0 V
IDD_STOP Stop mode current at 3.0 V
at 25 °C
—
—
—
—
—
345
357
392
438
551
490
827
at 50 °C
μA
at 70 °C
869
at 85 °C
927
at 105 °C
1065
IDD_VLPS Very-low-power stop mode current at 3.0 V
at 25 °C
—
—
—
—
—
4.4
10
20
37
81
16
35
at 50 °C
μA
μA
at 70 °C
50
at 85 °C
112
201
at 105 °C
IDD_LLS Low leakage stop mode current at 3.0 V
at 25 °C
—
—
—
—
—
1.9
3.6
6.5
13
3.7
39
43
49
69
at 50 °C
at 70 °C
at 85 °C
at 105 °C
30
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
μA
at 25 °C
—
—
—
—
—
1.4
2.5
5.1
9.2
21
3.2
19
21
26
38
at 50 °C
at 70 °C
at 85 °C
at 105 °C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0V
at 25°C
at 50°C
at 70°C
at 85°C
at 105°C
—
—
—
—
—
0.7
1.3
2.3
5.1
13
1.4
13
14
17
25
μA
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
15
General
Table 5. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLLS0 Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
nA
—
—
—
—
—
381
956
943
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
11760
13260
15700
23480
2370
4800
12410
IDD_VLLS0 Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0 V
6
—
—
—
—
—
176
760
860
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
3577
nA
2120
4500
12130
11660
18450
22441
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG configured for PEE mode. CoreMark benchmark compiled using Keil 4.54 with optimization level 3, optimized for
time.
3. MCG configured for FEI mode.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode.
6. No brownout
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
uA
IEREFSTEN4MHz
External 4MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
16
Freescale Semiconductor, Inc.
General
Unit
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
-40
25
50
70
85
105
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
440
440
490
510
510
490
490
490
560
560
540
540
540
560
560
560
560
560
560
560
570
570
570
610
610
580
580
680
680
680
VLLS1
VLLS3
LLS
nA
VLPS
STOP
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
22
22
22
22
22
22
µA
nA
Includes 6-bit DAC power consumption.
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432
357
388
475
532
810
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
66
66
66
66
66
66
µA
MCGIRCLK (4MHz internal reference
clock)
214
237
246
254
260
268
OSCERCLK (4MHz external crystal)
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100Hz clock signal. No load
is placed on the I/O generating the clock
signal. Includes selected clock source
and I/O switching currents.
µA
µA
MCGIRCLK (4MHz internal reference
clock)
86
86
86
86
86
86
OSCERCLK (4MHz external crystal)
235
45
256
45
265
45
274
45
280
45
287
45
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
17
General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
366
366
366
366
366
366
µA
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode, and BLPE for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
18
Freescale Semiconductor, Inc.
General
Run Mode Current Vs Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
All Peripheral CLK Gates
All On
CLK Ratio
Flash-Core
Core Freq (MHz)
Figure 2. Run mode supply current vs. core frequency
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
19
General
All Off
All On
CLK Ratio
Flash-Core
Core Freq (MHz)
Figure 3. VLPR mode current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 64-pin LQFP
package
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
13
15
12
7
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
M
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
20
Freescale Semiconductor, Inc.
General
2. VDD = 3.3 V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 48 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
48
24
24
24
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
VLPR mode1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
4
1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fFLASH
fLPTMR
fERCLK
Flash clock
1
LPTMR clock
24
16
24
16
External reference clock
fLPTMR_pin LPTMR clock
fLPTMR_ERCL LPTMR external reference clock
K
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
21
General
Symbol
Description
Min.
Max.
Unit
Notes
fosc_hi_2
Oscillator crystal or resonator frequency — high
—
16
MHz
frequency mode (high range) (MCG_C2[RANGE]=1x)
fTPM
TPM asynchronous clock
—
—
8
8
MHz
MHz
fUART0
UART0 asynchronous clock
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General Switching Specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and I2C signals.
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
16
—
—
ns
2
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise and fall time
ns
3
—
36
ns
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 9. Thermal operating requirements
Symbol
TJ
Description
Min.
Max.
125
Unit
°C
Die junction temperature
Ambient temperature
–40
–40
TA
105
°C
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
5.4.2 Thermal attributes
Table 10. Thermal attributes
Board type
Symbol
Description
80
64
48 QFN 32 QFN
Unit
Notes
LQFP
LQFP
Single-layer (1S)
RθJA
Thermal resistance, junction
to ambient (natural
convection)
70
53
—
—
71
52
59
46
84
28
69
22
92
33
75
27
°C/W
1
Four-layer (2s2p)
Single-layer (1S)
Four-layer (2s2p)
RθJA
Thermal resistance, junction
to ambient (natural
convection)
°C/W
°C/W
°C/W
RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance, junction
to board
34
15
34
20
5
10
2.0
5.0
12
1.8
8
°C/W
°C/W
°C/W
2
3
4
Thermal resistance, junction
to case
Thermal characterization
parameter, junction to
package top outside center
(natural convection)
0.6
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD Electricals
Table 11. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
Table 11. SWD full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 4. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 5. Serial wire data timing
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 12. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/-0.7
0.4
3
%fdco
%fdco
1, 2
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0 - 70 °C
1.5
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
—
4
—
3
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage ---
factory trimmed at nominal VDD and 25 °C
+1/-2
%fintf_ft
2
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
—
—
5
MHz
kHz
kHz
floc_low
floc_high
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS = 00)
640 × ffll_ref
20.97
MHz
3, 4
frequency range
Mid range (DRS = 01)
1280 × ffll_ref
40
41.94
48
MHz
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
Table 12. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fdco_t_DMX32 DCO output
frequency
Low range (DRS = 00)
732 × ffll_ref
—
23.99
—
MHz
5, 6
Mid range (DRS = 01)
1464 × ffll_ref
—
—
—
47.97
180
—
—
—
1
MHz
ps
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
7
8
tfll_acquire FLL target frequency acquisition time
ms
PLL
fvco
Ipll
VCO operating frequency
PLL operating current
48.0
—
—
100
—
MHz
µA
9
9
1060
• PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2
MHz, VDIV multiplier = 48)
Ipll
PLL operating current
—
600
—
—
µA
• PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2
MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 48 MHz
2.0
4.0
MHz
Jcyc_pll
10
10
—
—
120
50
—
—
ps
ps
• fvco = 100 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
—
—
1350
600
—
—
ps
ps
• fvco = 100 MHz
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
150 × 10-6
+ 1075(1/
%
%
s
tpll_lock
11
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft
.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 13. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
10
—
1
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 13. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
RS Series resistor — low-frequency, low-power
—
—
—
kΩ
mode (HGO=0)
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
—
200
—
—
—
kΩ
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all
other cases external capacitors must be used..
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 14. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high
frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
—
48
60
MHz
%
1, 2
40
50
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. Oscillator frequency specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tcst Crystal startup time — 32 kHz low-frequency,
—
750
—
ms
3, 4
low-power mode (HGO=0)
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 15. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
thversscr Sector Erase high-voltage time
—
113
452
ms
ms
1
1
thversall
Erase All high-voltage time
—
52
1. Maximum time based on expectations at cycling end-of-life.
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
6.4.1.2 Flash timing specifications — commands
Table 16. Flash command timing specifications
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec1k Read 1s Section execution time (flash sector)
1
1
1
tpgmchk
trdrsrc
tpgm4
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
45
μs
—
30
μs
65
14
—
145
114
1.8
25
μs
tersscr
trd1all
ms
ms
μs
2
1
trdonce
—
tpgmonce Program Once execution time
65
62
—
—
μs
tersall
Erase All Blocks execution time
500
30
ms
μs
2
1
tvfykey
Verify Backdoor Access Key execution time
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3 Flash high voltage current behaviors
Table 17. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
6.4.1.4 Reliability specifications
Table 18. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 19 and Table 20 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 19. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Ground voltage
Absolute
—
Delta to VDD (VDD-VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
3
Delta to VSS (VSS - VSSA
)
0
ADC reference
voltage high
VDDA
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
3
VADIN
CADIN
Input voltage
VREFL
—
—
8
VREFH
10
V
Input capacitance
• 16-bit mode
pF
• 8-/10-/12-bit modes
—
4
5
RADIN
RAS
Input resistance
—
2
5
kΩ
kΩ
Analog source
resistance
13-/12-bit modes
fADCK < 4 MHz
4
—
—
5
fADCK
fADCK
Crate
ADC conversion ≤ 1312-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
5
5
6
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 1312 bit modes
rate
No ADC hardware averaging
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 19. 16-bit ADC operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Crate
ADC conversion 16-bit mode
rate
6
No ADC hardware averaging
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA
.
4. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best
results. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1ns.
5. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 6. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
IDDA_ADC Supply current
0.215
—
1.7
mA
3
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
1.2
2.4
3.0
4.4
Typ.2
Max.
3.9
Unit
Notes
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
4.0
6.1
clock source
fADACK
5.2
7.3
6.2
9.5
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
—
0.7
-1.1 to +1.9
-0.3 to 0.5
• <12-bit modes
• 12-bit modes
—
—
0.2
1.0
INL
EFS
Integral non-
linearity
-2.7 to +1.9
-0.7 to +0.5
LSB4
5
• <12-bit modes
• 12-bit modes
• <12-bit modes
—
—
—
0.5
-4
Full-scale error
-5.4
-1.8
LSB4
LSB4
VADIN =
VDDA
-1.4
5
EQ
Quantization
error
• 16-bit modes
—
—
-1 to 0
—
—
• ≤1312-bit modes
0.5
ENOB
Effective number 16-bit differential mode
6
of bits
• Avg = 32
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg = 4
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
—
—
–94
-85
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
16-bit differential mode
• Avg = 32
82
78
95
90
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
33
Peripheral operating requirements and behaviors
Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
IIn
leakage
current
EIL
Input leakage
error
IIn × RAS
mV
=
(refer to
the MCU's
voltage
and current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
—
—
1.715
719
—
—
mV/°C
mV
VTEMP25 Temp sensor
voltage
25 °C
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
Figure 7. Typical ENOB vs. ADC_CLK for 16-bit differential mode
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 8. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.2 CMP and 6-bit DAC electrical specifications
Table 21. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
Supply current, high-speed mode (EN = 1, PMODE =
1)
—
200
μA
IDDLS
VAIN
VAIO
VH
Supply current, low-speed mode (EN = 1, PMODE = 0)
Analog input voltage
—
VSS
—
—
—
—
20
VDD
20
μA
V
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
mV
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
• CR0[HYSTCTR] = 01
10
20
30
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN = 1, PMODE
= 1)
20
ns
tDLS
Propagation delay, low-speed mode (EN = 1, PMODE
= 0)
80
250
600
ns
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
Table 21. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
—
Typ.
—
Max.
40
Unit
μs
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
IDAC6b
INL
—
7
—
μA
LSB3
–0.5
–0.3
—
0.5
0.3
DNL
—
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
HYSTCTR
Setting
Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
HYSTCTR
Setting
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.6.3 12-bit DAC electrical characteristics
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.3.1 12-bit DAC operating requirements
Table 22. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
TA
Desciption
Min.
1.71
1.13
Max.
3.6
3.6
Unit
V
Notes
Supply voltage
Reference voltage
Temperature
V
1
Operating temperature
range of the device
°C
CL
IL
Output load capacitance
Output load current
—
—
100
1
pF
2
mA
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
6.6.3.2 12-bit DAC operating behaviors
Table 23. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
250
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
—
100
15
0.7
—
900
200
30
μA
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
μs
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
1
μs
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
100
VDACR
8
mV
mV
LSB
LSB
LSB
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
—
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
—
2
3
4
Differential non-linearity error — VDACR > 2
V
—
1
Differential non-linearity error — VDACR
VREF_OUT
=
—
1
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance load = 3 kΩ
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
Table 23. 12-bit DAC operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
SR
Slew rate -80h→ F7Fh→ 80h
V/μs
• High power (SPHP
)
1.2
1.7
—
—
• Low power (SPLP
3dB bandwidth
)
0.05
0.12
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
Figure 11. Typical INL error vs. digital code
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 12. Offset at half scale vs. temperature
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
6.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's Reference Manual for information about the modified transfer formats used for
communicating with slower peripheral devices.
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as
well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 24. SPI master mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
16
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
10
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 25. SPI master mode timing on slew rate enabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
96
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
52
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
5
=
(CPOL 0)
(OUTPUT)
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
LSB OUT
MSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI master mode timing (CPHA = 0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL 0)
=
(OUTPUT)
5
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
MSB IN
BIT 6 . . . 1
LSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
MASTER MSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA = 1)
Table 26. SPI slave mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
1
2
3
4
5
fop
tSPSCK
tLead
tLag
Frequency of operation
0
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
1
1
—
tperiph
tperiph
ns
—
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
Table continues on the next page...
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
Table 26. SPI slave mode timing on slew rate disabled pads (continued)
Num.
6
Symbol Description
Min.
2
Max.
—
Unit
ns
Note
—
—
3
tSU
tHI
ta
Data setup time (inputs)
7
Data hold time (inputs)
Slave access time
7
—
ns
8
—
—
—
0
tperiph
tperiph
22
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
Table 27. SPI slave mode timing on slew rate enabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2
7
—
ns
7
—
ns
8
—
—
—
0
tperiph
tperiph
122
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL 0)
=
(INPUT)
5
5
3
SPSCK
=
(CPOL 1)
(INPUT)
9
8
10
11
11
MISO
(OUTPUT)
see
SEE
BIT 6 . . . 1
SLAVE LSB OUT
SLAVE MSB
7
note
NOTE
6
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined!
Figure 15. SPI slave mode timing (CPHA = 0)
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
=
(CPOL 0)
(INPUT)
5
5
SPSCK
=
(CPOL 1)
(INPUT)
11
9
10
SLAVE MSB OUT
MISO
(OUTPUT)
see
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
note
8
6
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE: Not defined!
Figure 16. SPI slave mode timing (CPHA = 1)
6.8.2 I2C
See General switching specifications.
6.8.3 UART
See General switching specifications.
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
43
Dimensions
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 28. TSI electrical specifications
Symbol
TSI_RUNF
TSI_RUNV
Description
Min.
—
Type
100
—
Max
—
Unit
µA
Fixed power consumption in run mode
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
128
µA
TSI_EN
TSI_DIS
Power consumption in enable mode
Power consumption in disable mode
TSI analog enable time
—
—
100
1.2
66
—
—
µA
µA
µs
pF
V
TSI_TEN
—
—
TSI_CREF
TSI_DVOLT
TSI reference capacitor
—
1.0
—
—
Voltage variation of VP & VM around nominal
values
0.19
1.03
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.freescale.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
32-pin QFN
Then use this document number
98ASA00473D
48-pin QFN
64-pin LQFP
80-pin LQFP
98ASA00466D
98ASS23234W
98ASS23174W
8 Pinout
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
44
Freescale Semiconductor, Inc.
Pinout
8.1 KL15 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
80
64
48
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP
QFN
QFN
1
2
3
4
5
6
7
8
9
1
2
—
—
—
—
—
—
1
1
PTE0
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
VDD
PTE0
UART1_TX
UART1_RX
RTC_CLKOUT CMP0_OUT
SPI1_MISO
I2C1_SDA
I2C1_SCL
2
PTE1
PTE2
PTE3
PTE4
PTE5
VDD
PTE1
PTE2
PTE3
PTE4
PTE5
SPI1_MOSI
SPI1_SCK
SPI1_MISO
SPI1_PCS0
—
—
—
—
3
—
—
—
—
—
—
3
SPI1_MOSI
VDD
VSS
4
2
VSS
VSS
5
3
PTE16
ADC0_DP1/
ADC0_SE1
ADC0_DP1/
ADC0_SE1
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
SPI0_PCS0
SPI0_SCK
SPI0_MOSI
SPI0_MISO
UART2_TX
UART2_RX
TPM_CLKIN0
TPM_CLKIN1
10
11
12
13
14
15
16
6
7
4
5
4
5
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
ADC0_DM1/
ADC0_SE5a
ADC0_DM1/
ADC0_SE5a
LPTMR0_
ALT3
ADC0_DP2/
ADC0_SE2
ADC0_DP2/
ADC0_SE2
I2C0_SDA
I2C0_SCL
UART0_TX
UART0_RX
UART2_TX
UART2_RX
SPI0_MISO
SPI0_MOSI
8
6
6
ADC0_DM2/
ADC0_SE6a
ADC0_DM2/
ADC0_SE6a
9
7
—
—
—
—
ADC0_DP0/
ADC0_SE0
ADC0_DP0/
ADC0_SE0
TPM1_CH0
TPM1_CH1
TPM2_CH0
TPM2_CH1
10
11
12
8
ADC0_DM0/
ADC0_SE4a
ADC0_DM0/
ADC0_SE4a
—
—
ADC0_DP3/
ADC0_SE3
ADC0_DP3/
ADC0_SE3
ADC0_DM3/
ADC0_SE7a
ADC0_DM3/
ADC0_SE7a
17
18
19
20
21
13
14
15
16
17
9
7
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
10
11
12
13
—
—
8
—
PTE29
CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29
PTE30
TPM0_CH2
TPM0_CH3
TPM_CLKIN0
TPM_CLKIN1
22
18
14
9
PTE30
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
23
24
25
26
27
28
19
20
21
22
23
24
—
15
16
17
18
19
—
—
—
10
11
12
PTE31
PTE24
PTE25
PTA0
DISABLED
DISABLED
DISABLED
SWD_CLK
DISABLED
DISABLED
PTE31
PTE24
PTE25
PTA0
TPM0_CH4
TPM0_CH0
TPM0_CH1
TPM0_CH5
TPM2_CH0
TPM2_CH1
I2C0_SCL
I2C0_SDA
TSI0_CH1
TSI0_CH2
TSI0_CH3
SWD_CLK
PTA1
PTA1
UART0_RX
UART0_TX
PTA2
PTA2
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
45
Pinout
80
64
48
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP
QFN
QFN
29
30
31
32
33
34
35
36
37
38
39
40
41
25
26
27
28
29
—
—
—
—
30
31
32
33
20
21
—
—
—
—
—
—
—
22
23
24
25
13
14
—
—
—
—
—
—
—
15
16
17
18
PTA3
SWD_DIO
NMI_b
TSI0_CH4
TSI0_CH5
PTA3
I2C1_SCL
I2C1_SDA
TPM0_CH0
TPM0_CH1
TPM0_CH2
TPM1_CH0
TPM1_CH1
UART0_TX
UART0_RX
SWD_DIO
NMI_b
PTA4
PTA4
PTA5
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
VDD
PTA5
PTA12
PTA13
PTA14
PTA15
PTA16
PTA17
VDD
PTA12
PTA13
PTA14
PTA15
PTA16
PTA17
SPI0_PCS0
SPI0_SCK
SPI0_MOSI
SPI0_MISO
SPI0_MISO
SPI0_MOSI
VDD
VSS
VSS
VSS
PTA18
PTA19
EXTAL0
XTAL0
EXTAL0
XTAL0
PTA18
PTA19
UART1_RX
UART1_TX
TPM_CLKIN0
TPM_CLKIN1
LPTMR0_
ALT1
42
43
34
35
26
27
19
20
RESET_b
RESET_b
PTA20
PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
TPM1_CH0
TPM1_CH1
TPM2_CH0
TPM2_CH1
EXTRG_IN
44
45
46
36
37
38
28
29
30
21
—
—
PTB1
PTB2
PTB3
ADC0_SE9/
TSI0_CH6
ADC0_SE9/
TSI0_CH6
PTB1
PTB2
PTB3
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
47
48
49
50
51
52
53
54
55
—
—
—
—
39
40
41
42
43
—
—
—
—
31
32
—
—
33
—
—
—
—
—
—
—
—
—
PTB8
DISABLED
DISABLED
DISABLED
DISABLED
TSI0_CH9
TSI0_CH10
TSI0_CH11
TSI0_CH12
PTB8
PTB9
PTB9
PTB10
PTB11
PTB16
PTB17
PTB18
PTB19
PTC0
PTB10
PTB11
PTB16
PTB17
PTB18
PTB19
PTC0
SPI1_PCS0
SPI1_SCK
SPI1_MOSI
SPI1_MISO
TSI0_CH9
TSI0_CH10
TSI0_CH11
TSI0_CH12
UART0_RX
UART0_TX
TPM2_CH0
TPM2_CH1
EXTRG_IN
TPM_CLKIN0
TPM_CLKIN1
SPI1_MISO
SPI1_MOSI
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
CMP0_OUT
56
44
34
22
PTC1/
LLWU_P6/
RTC_CLKIN
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL
I2C1_SDA
TPM0_CH0
57
58
45
46
35
36
23
24
PTC2
ADC0_SE11/
TSI0_CH15
ADC0_SE11/
TSI0_CH15
PTC2
TPM0_CH1
TPM0_CH2
PTC3/
LLWU_P7
DISABLED
PTC3/
LLWU_P7
UART1_RX
UART1_TX
CLKOUT
59
60
61
47
48
49
—
—
37
—
—
25
VSS
VDD
VSS
VSS
VDD
VDD
PTC4/
DISABLED
PTC4/
SPI0_PCS0
TPM0_CH3
LLWU_P8
LLWU_P8
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
46
Freescale Semiconductor, Inc.
Pinout
80
64
48
QFN
32
QFN
Pin Name
Default
DISABLED
CMP0_IN0
ALT0
ALT1
ALT2
SPI0_SCK
SPI0_MOSI
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP
62
63
50
51
38
39
26
27
PTC5/
LLWU_P9
PTC5/
LLWU_P9
LPTMR0_
ALT2
CMP0_OUT
PTC6/
LLWU_P10
CMP0_IN0
PTC6/
LLWU_P10
EXTRG_IN
SPI0_MISO
SPI0_MOSI
64
65
66
67
68
69
70
71
72
73
74
75
76
77
52
53
54
55
56
—
—
—
—
57
58
59
60
61
40
—
—
—
—
—
—
—
—
41
42
43
44
45
28
—
—
—
—
—
—
—
—
—
—
—
—
29
PTC7
CMP0_IN1
CMP0_IN2
CMP0_IN3
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
ADC0_SE5b
DISABLED
DISABLED
DISABLED
CMP0_IN1
CMP0_IN2
CMP0_IN3
PTC7
SPI0_MISO
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
PTC8
PTC8
TPM0_CH4
TPM0_CH5
PTC9
PTC9
PTC10
PTC11
PTC12
PTC13
PTC16
PTC17
PTD0
PTC10
PTC11
PTC12
PTC13
PTC16
PTC17
PTD0
TPM_CLKIN0
TPM_CLKIN1
SPI0_PCS0
SPI0_SCK
SPI0_MOSI
SPI0_MISO
SPI1_PCS0
TPM0_CH0
TPM0_CH1
TPM0_CH2
TPM0_CH3
TPM0_CH4
PTD1
ADC0_SE5b
PTD1
PTD2
PTD2
UART2_RX
UART2_TX
UART2_RX
SPI0_MISO
SPI0_MOSI
PTD3
PTD3
PTD4/
PTD4/
LLWU_P14
LLWU_P14
78
79
62
63
46
47
30
31
PTD5
ADC0_SE6b
ADC0_SE7b
ADC0_SE6b
ADC0_SE7b
PTD5
SPI1_SCK
UART2_TX
UART0_RX
TPM0_CH5
PTD6/
LLWU_P15
PTD6/
LLWU_P15
SPI1_MOSI
SPI1_MISO
SPI1_MOSI
80
64
48
32
PTD7
DISABLED
PTD7
SPI1_MISO
UART0_TX
8.2 KL15 Pinouts
The below figures show the pinout diagrams for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
47
Pinout
1
PTE0
PTE1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDD
2
VSS
3
PTE2
PTC3/LLWU_P7
PTC2
4
PTE3
5
PTE4
PTC1/LLWU_P6/RTC_CL
PTC0
6
PTE5
7
VDD
PTB19
8
VSS
PTB18
9
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
VDDA
VREFH
VREFL
VSSA
PTB17
10
11
12
13
14
15
16
17
18
19
20
PTB16
PTB11
PTB10
PTB9
PTB8
PTB3
PTB2
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
Figure 17. KL15 80-pin LQFP pinout diagram
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
48
Freescale Semiconductor, Inc.
Pinout
PTE0
PTE1
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
VSS
VDD
3
PTC3/LLWU_P7
PTC2
VSS
4
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
VDDA
VREFH
VREFL
VSSA
5
PTC1/LLWU_P6/RTC_CLKIN
6
PTC0
7
PTB19
8
PTB18
9
PTB17
10
11
12
13
14
15
16
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
Figure 18. KL15 64-pin LQFP pinout diagram
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
49
Pinout
PTC3/LLWU_P7
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
1
2
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
VDDA
VREFH
VREFL
VSSA
3
PTC0
4
PTB17
5
PTB16
6
PTB3
7
PTB2
8
PTB1
9
PTB0/LLWU_P5
RESET_b
PTA19
10
11
12
Figure 19. KL15 48-pin QFN pinout diagram
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
50
Freescale Semiconductor, Inc.
Revision History
PTC3/LLWU_P7
PTC2
PTE0
PTE1
24
23
22
21
20
19
1
2
3
4
5
6
7
8
PTC1/LLWU_P6/RTC_CLKIN
PTE16
PTE17
PTE18
PTE19
VDDA
VSSA
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
18
17
PTA18
Figure 20. KL15 32-pin QFN pinout diagram
9 Revision History
The following table provides a revision history for this document.
Table 29. Revision History
Rev. No.
Date
7/2012
9/2012
9/2012
Substantial Changes
1
2
3
Initial NDA release.
Completed all the TBDs, initial public release.
Updated Signal Multiplexing and Pin Assignments table to add UART2
signals.
KL15 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
51
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sales representative.
Japan:
For information on Freescale's Environmental Products program, go to
http://www.freescale.com/epp.
Freescale Semiconductor Japan Ltd.
Headquarters
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
© 2012 Freescale Semiconductor, Inc.
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
support.asia@freescale.com
Document Number: KL15P80M48SF0
Rev. 3, 9/19/2012
相关型号：
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