MPC5533 [FREESCALE]
Microcontroller Data Sheet; 单片机的数据手册型号: | MPC5533 |
厂家: | Freescale |
描述: | Microcontroller Data Sheet |
文件: | 总50页 (文件大小:1079K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: MPC5533
Rev. 0.0, 10 Oct 2008
Freescale Semiconductor
Data Sheet: Technical Data
MPC5533
Microcontroller Data Sheet
by: Microcontroller Division
Contents
This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5533
microcontroller device. For functional characteristics,
refer to the MPC5534 Microcontroller Reference
Manual.
1
2
3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . 5
3.3 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 EMI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 ESD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 VRC and POR Electrical Specifications . . . . . . . . . 9
3.7 Power-Up/Down Sequencing. . . . . . . . . . . . . . . . . 10
3.8 DC Electrical Specifications . . . . . . . . . . . . . . . . . 13
3.9 Oscillator and FMPLL Electrical Characteristics . . 20
3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22
3.11 H7Fb Flash Memory Electrical Characteristics . . . 23
3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1
Overview
The MPC5533 microcontroller (MCU) is a member of
the MPC5500 family of microcontrollers built on the
Power Architecture™ embedded technology. This
family of parts has many new features coupled with high
performance CMOS technology to provide substantial
reduction of cost per feature and significant performance
improvement over the MPC500 family.
4
5
Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1 MPC5533 208 MAP BGA Pinout. . . . . . . . . . . . . . 43
4.2 MPC5533 324 PBGA Pinout . . . . . . . . . . . . . . . . . 44
4.3 MPC5533 208-Pin Package Dimensions. . . . . . . . 45
4.4 MPC5533 324-Pin Package Dimensions. . . . . . . . 47
The host processor core of this device complies with the
Power Architecture embedded category that is 100%
user-mode compatible (including floating point library)
with the original Power PC™ user instruction set
architecture (UISA). The embedded architecture
enhancements improve the performance in embedded
applications. The core also has additional instructions,
including digital signal processing (DSP) instructions,
beyond the original Power PC instruction set.
Revision History for the MPC5533 Data Sheet . . . . . . . 49
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Overview
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565.
The host processor core of the MPC5533 also includes an instruction set enhancement allowing variable
length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this
enhancement, it is possible to significantly reduce the code size footprint.
The MPC5533 has a single-level memory hierarchy consisting of 48-kilobytes (KB) on-chip SRAM and
768 KB of internal flash memory. Both the SRAM and the flash memory can hold instructions and data.
The complex input/output timer functions of the MPC5533 are performed by an enhanced time processor
unit (eTPU) engine. The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over
the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per
channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is
programmed using a high-level programming language.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and an enhanced serial
communications interface (eSCI).
The MCU has an on-chip enhanced queued analog-to-digital converter (eQADC) with a 5 V conversion
range. The 324 package has 40-channels; the 208 package has 34 channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. Interrupts and reset control are
also determined by the SIU. The internal multiplexer sub-block (IMUX) provides multiplexing of eQADC
trigger sources and external interrupt signal multiplexing.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
2
Freescale Semiconductor
Ordering Information
2
Ordering Information
5533
R
VF
80
M PC
M
Qualification status
Core code
Device number
Temperature range
Package identifier
Operating frequency (MHz)
Tape and reel status
Tape and Reel Status
R = Tape and reel
(blank) = Trays
Operating Frequency
40 = 40 MHz
66 = 66 MHz
Package Identifier
Temperature Range
M = –40° C to 125° C
VF = 208MAPBGA SnPb
VM = 208MAPBGA Pb-free
ZQ = 324PBGA SnPb
VZ = 324PBGA Pb-free
80 = 80 MHz
Qualification Status
P = Pre qualification
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Note: Not all options are available on all devices. Refer to Table 1.
Figure 1. MPC5500 Family Part Number Example
Unless noted in this data sheet, all specifications apply from T to T .
L
H
Table 1. Orderable Part Numbers
Operating Temperature 1
Speed (MHz)
Freescale Part Number
Package Description
Nominal
Max. 2 (fMAX
)
Min. (TL)
Max. (TH)
MPC5533MVM80
MPC5533MVM66
MPC5533MVM40
MPC5533MVF80
MPC5533MVF66
MPC5533MVF40
MPC5533MVZ80
MPC5533MVZ66
MPC5533MVZ40
MPC5533MZQ80
MPC5533MZQ66
MPC5533MZQ40
80
66
40
80
66
40
80
66
40
80
66
40
82
68
42
82
68
42
82
68
42
82
68
42
MPC5533 208 package
Lead-free (PbFree)
–40° C
125° C
MPC5533 208 package
Leaded (SnPb)
–40° C
–40° C
–40° C
125° C
125° C
125° C
MPC5533 324 package
Lead-free (PbFree)
MPC5533 324 package
Leaded (SnPb)
1
The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH.
2
Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).
42 MHz parts allow for 40 MHz system clock + 2% FM; 68 MHz parts allow for 66 MHz system clock + 2% FM, and
82 MHz parts allow for 80 MHz system clock + 2% FM.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
3
Freescale Semiconductor
Electrical Characteristics
3
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MCU.
3.1
Maximum Rating
1
Table 2. Absolute Maximum Ratings
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
2
4
5
6
7
8
9
1.5 V core supply voltage 2
Flash program/erase voltage
Flash read voltage
VDD
VPP
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
1.7
6.5
4.6
1.7
4.6
4.6
4.6
5.5
4.6
6.5
V
V
V
V
V
V
V
V
V
V
VFLASH
VSTBY
VDDSYN
VDD33
VRC33
VDDA
SRAM standby voltage
Clock synthesizer voltage
3.3 V I/O buffer voltage
Voltage regulator control input voltage
Analog supply voltage (reference to VSSA
)
10 I/O supply voltage (fast I/O pads) 3
11 I/O supply voltage (slow and medium I/O pads) 3
12 DC input voltage 4
VDDEH powered I/O pads
VDDE powered I/O pads
VDDE
VDDEH
VIN
–1.0 5
–1.0 5
6.5 6
4.6 7
V
13 Analog reference high voltage (reference to VRL
)
VRH
–0.3
–0.1
5.5
0.1
V
V
V
V
V
V
V
V
14
15
V
SS to VSSA differential voltage
DD to VDDA differential voltage
VSS – VSSA
VDD – VDDA
VRH – VRL
V
–VDDA
–0.3
VDD
5.5
16 VREF differential voltage
17
18
V
RH to VDDA differential voltage
RL to VSSA differential voltage
VRH – VDDA
VRL – VSSA
VDDEH – VDDA
VDDF – VDD
–5.5
5.5
V
–0.3
0.3
19 VDDEH to VDDA differential voltage
–VDDA
–0.3
VDDEH
0.3
20
21
VDDF to VDD differential voltage
VRC33 to VDDSYN differential voltage spec has been moved to Table 9 DC Electrical Specifications, Spec 43a.
22 VSSSYN to VSS differential voltage
23 RCVSS to VSS differential voltage
24 Maximum DC digital input current 8
VSSSYN – VSS
VRCVSS – VSS
IMAXD
–0.1
–0.1
–2
0.1
0.1
2
V
V
V
mA
4
(per pin, applies to all digital pins)
25 Maximum DC analog input current 9
(per pin, applies to all analog pins)
26 Maximum operating temperature range 10
Die junction temperature
IMAXA
TJ
–3
TL
3
mA
oC
oC
150.0
150.0
27 Storage temperature range
TSTG
–55.0
MPC5533 Microcontroller Data Sheet, Rev. 0.0
4
Freescale Semiconductor
Electrical Characteristics
1
Table 2. Absolute Maximum Ratings (continued)
Spec
Characteristic
Symbol
Min.
Max.
Unit
28 Maximum solder temperature 11
Lead free (Pb-free)
Leaded (SnPb)
29 Moisture sensitivity level 12
TSDR
MSL
—
—
260.0
245.0
oC
—
3
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond any of the listed maxima can affect device reliability
or cause permanent damage to the device.
2
3
4
1.5 V 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 oC.
All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH
.
AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of
60 hours over the complete lifetime of the device (injection current not limited for this duration).
5
6
7
Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met. Keep the negative DC
voltage greater than –0.6 V on SINB during the internal power-on reset (POR) state.
Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDEH supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications.
Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the maximum
injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications.
Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
Total injection current for all analog input pins must not exceed 15 mA.
8
9
10 Lifetime operation at these specification limits is not guaranteed.
11 Moisture sensitivity profile per IPC/JEDEC J-STD-020D.
12 Moisture sensitivity per JEDEC test method A112.
3.2
Thermal Characteristics
The shaded rows in the following table indicate information specific to a four-layer board.
Table 3. MPC5533 Thermal Characteristic
Package
Spec
MPC5533 Thermal Characteristic
Symbol
Unit
208
324
MAPBGA
PBGA
1
2
3
4
5
6
7
Junction to ambient 1, 2, natural convection (one-layer board)
Junction to ambient 1, 3, natural convection (four-layer board 2s2p)
Junction to ambient (@200 ft./min., one-layer board)
Junction to ambient (@200 ft./min., four-layer board 2s2p)
Junction to board 4 (four-layer board 2s2p)
RθJA
RθJA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
42
26
34
22
15
8
34
23
28
20
15
10
2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction to case 5
Junction to package top 6, natural convection
2
1
Junction temperature is a function of: on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other board components, and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board in a horizontal position.
Per JEDEC JESD51-6 with the board in a horizontal position.
2
3
4
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
5
Freescale Semiconductor
Electrical Characteristics
5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
6
The thermal characterization parameter indicates the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2.
3.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimation of the device junction temperature, T , can be obtained from the equation:
J
T = T + (R
× P )
D
J
A
θJA
where:
o
T = ambient temperature for the package ( C)
A
o
R
= junction to ambient thermal resistance ( C/W)
θJA
P = power dissipation in the package (W)
D
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide
consistent values for estimations and comparisons. The difference between the values determined for the
single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground
plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance
depends on the:
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to
connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal
performance. When the clearance between the vias leave the planes virtually disconnected, the thermal
performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly
packed printed circuit board. The value obtained on a board with the internal planes is usually within the
normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components are well separated
2
Overall power dissipation on the board is less than 0.02 W/cm
The thermal performance of any component depends on the power dissipation of the surrounding
components. In addition, the ambient temperature varies widely within the application. For many natural
convection and especially closed box applications, the board temperature at the perimeter (edge) of the
package is approximately the same as the local air temperature near the device. Specifying the local
ambient conditions explicitly as the board temperature provides a more precise description of the local
ambient conditions that determine the temperature of the device.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
6
Freescale Semiconductor
Electrical Characteristics
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R
× P )
D
J
B
θJB
where:
o
T = junction temperature ( C)
J
o
T = board temperature at the package perimeter ( C/W)
B
o
R
= junction-to-board thermal resistance ( C/W) per JESD51-8
θJB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value
for the junction temperature is predictable. Ensure the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a
case-to-ambient thermal resistance:
R
= R
+ R
θJA
θJC θCA
where:
o
R
R
R
= junction-to-ambient thermal resistance ( C/W)
θJA
θJC
θCA
o
= junction-to-case thermal resistance ( C/W)
o
= case-to-ambient thermal resistance ( C/W)
R
is device related and is not affected by other factors. The thermal environment can be controlled to
θJC
change the case-to-ambient thermal resistance, R
. For example, change the air flow around the device,
θCA
add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device. This description is most useful for
packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient.
For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal
resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes
when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The
junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. This model can be used to generate simple estimations and for
computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the
thermal characterization parameter (Ψ ) to determine the junction temperature by measuring the
JT
temperature at the top center of the package case using the following equation:
T = T + (Ψ × P )
J
T
JT
D
where:
o
T = thermocouple temperature on top of the package ( C)
T
o
Ψ
= thermal characterization parameter ( C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using
a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple
MPC5533 Microcontroller Data Sheet, Rev. 0.0
7
Freescale Semiconductor
Electrical Characteristics
so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple
junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat
against the package case to avoid measurement errors caused by the cooling effects of the thermocouple
wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Rd.
San Jose, CA., 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the web at http://www.jedec.org.
•
•
•
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled
Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance
and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999,
pp. 212–220.
3.3
Package
The MPC5533 is available in packaged form. Read the package options in Section 2, “Ordering
Information.” Refer to Section 4, “Mechanicals,” for pinouts and package drawings.
3.4
EMI (Electromagnetic Interference) Characteristics
1
Table 4. EMI Testing Specifications
Spec
Characteristic
Minimum
Typical
Maximum
Unit
1
2
3
4
5
6
Scan range
0.15
—
—
—
1000
fMAX
—
MHz
MHz
V
Operating frequency
VDD operating voltages
—
1.5
3.3
5.0
—
VDDSYN, VRC33, VDD33, VFLASH, VDDE operating voltages
VPP, VDDEH, VDDA operating voltages
Maximum amplitude
—
—
V
—
—
14 2
32 3
V
—
dBuV
7
Operating temperature
—
—
25
oC
1
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554
and applied to the MPC5500 family as generic EMI performance data.
2
3
Measured with the single-chip EMI program.
Measured with the expanded EMI program.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
8
Freescale Semiconductor
Electrical Characteristics
3.5
ESD (Electromagnetic Static Discharge) Characteristics
1, 2
Table 5. ESD Ratings
Characteristic
Symbol
Value
Unit
ESD for human body model (HBM)
HBM circuit description
2000
1500
V
Ω
R1
C
100
pF
500 (all pins)
750 (corner pins)
ESD for field induced charge model (FDCM)
V
Number of pulses per pin:
Positive pulses (HBM)
Negative pulses (HBM)
—
—
1
1
—
—
Interval of pulses
—
1
second
1
All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2
Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification requirements,
which includes the complete DC parametric and functional testing at room temperature and hot temperature.
3.6
Voltage Regulator Controller (V ) and Power-On Reset (POR)
Electrical Specifications
RC
The following table lists the V and POR electrical specifications:
RC
Table 6. VRC/POR Electrical Specifications
Spec
Characteristic
Negated (ramp up)
Symbol
Min.
Max. Units
1.1
1.1
1.35
V
1
1.5 V (VDD) POR 1
VPOR15
Asserted (ramp down)
1.35
Asserted (ramp up)
Negated (ramp up)
Asserted (ramp down)
Negated (ramp down)
0.0
2.0
2.0
0.0
0.30
2.85
2.85
0.30
2
3.3 V (VDDSYN) POR 1
VPOR33
V
Negated (ramp up)
2.0
2.0
2.85
2.85
RESET pin supply
(VDDEH6) POR 1, 2
3
4
5
VPOR5
V
Asserted (ramp down)
Before VRC allows the pass
transistor to start turning on
VTRANS_START
VTRANS_ON
1.0
2.0
2.0
V
V
When VRC allows the pass transistor
to completely turn on 3, 4
2.85
V
RC33 voltage
When the voltage is greater than the
voltage at which the VRC keeps the
1.5 V supply in regulation 5, 6
– 40o C
25o C
6
7
8
VVRC33REG
3.0
—
V
Current can be sourced
by VRCCTL at Tj:
11.0
9.0
—
—
—
mA
mA
mA
7
IVRCCTL
150o C
7.5
Voltage differential during power up such that:
VDD33 can lag VDDSYN or VDDEH6, before VDDSYN and VDDEH6 reach the
VPOR33 and VPOR5 minimums respectively.
VDD33_LAG
—
1.0
V
MPC5533 Microcontroller Data Sheet, Rev. 0.0
9
Freescale Semiconductor
Electrical Characteristics
Spec
Table 6. VRC/POR Electrical Specifications (continued)
Characteristic
Symbol
Min.
Max. Units
9
Absolute value of slew rate on power supply pins
—
—
35
40
50
50
—
V/ms
—
Required gain at Tj:
IDD ÷ IVRCCTL (@ fsys = fMAX
– 40o C
25o C
)
BETA10
—
—
10
150o C
500
—
6, 7, 8, 9
1
On power up, assert RESET before VPOR15, VPOR33, and VPOR5 negate (internal POR). RESET must remain asserted until
the power supplies are within the operating conditions as specified in Table 9 DC Electrical Specifications. On power down,
assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts.
2
3
4
5
6
VIL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to VPOR5
.
Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
At peak current for device.
Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass
transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance
(less than 1 Ω). VRCCTL must have a nominal 1 μF phase compensation capacitor to ground. VDD must have a 20 μF (nominal)
bulk capacitor (greater than 4 μF over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01 μF, two 0.1 μF, and one 1 μF capacitors around the package on the VDD supply signals.
7
8
9
IVRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V.
Refer to Table 1 for the maximum operating frequency.
Values are based on IDD from high-use applications as explained in the IDD Electrical Specification.
10 BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (IDD ÷ IVRCCTL).
3.7
Power-Up/Down Sequencing
Power sequencing between the 1.5 V power supply and V
or the RESET power supplies is required
DDSYN
if using an external 1.5 V power supply with V
tied to ground (GND). To avoid power-sequencing,
RC33
V
must be powered up within the specified operating range, even if the on-chip voltage regulator
RC33
controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”
Power sequencing requires that V
must reach a certain voltage where the values are read as ones
DD33
before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on
VDD33.”
Although power sequencing is not required between V
and V
during power up, V
must
RC33
RC33
DDSYN
not lead V
by more than 600 mV or lag by more than 100 mV for the V stage turn-on to operate
DDSYN
RC
within specification. Higher spikes in the emitter current of the pass transistor occur if V
leads or lags
RC33
V
by more than these amounts. The value of that higher spike in current depends on the board power
DDSYN
supply circuitry and the amount of board level capacitance.
Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase
of the current consumed by V . If V lags V by more than 100 mV, the increase in current
RC33
RC33
DDSYN
consumed can drop V low enough to assert the 1.5 V POR again. Oscillations are possible when the
DD
1.5 V POR asserts and stops the system clock, causing the voltage on V to rise until the 1.5 V POR
DD
negates again. All oscillations stop when V
is powered sufficiently.
RC33
MPC5533 Microcontroller Data Sheet, Rev. 0.0
10
Freescale Semiconductor
Electrical Characteristics
When powering down, V
and V
have no delta requirement to each other, because the bypass
RC33
DDSYN
capacitors internal and external to the device are already charged. When not powering up or down, no delta
between V and V is required for the V to operate within specification.
RC33
DDSYN
RC
There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending
on which supplies are powered.
Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).
Table 7. Pin Status for Fast Pads During the Power Sequence
Pin Status for Fast Pad Output Driver
VDDE
VDD33
VDD
POR
pad_fc (fast)
Low
—
—
Asserted
Asserted
Asserted
Asserted
Asserted
Negated
Low
VDDE
VDDE
VDDE
VDDE
VDDE
Low
Low
VDD
Low
VDD
VDD
High
High
Low
VDD33
VDD33
VDD33
High impedance (Hi-Z)
Hi-Z
Functional
Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and
pad_sh (slow type).
Table 8. Pin Status for Medium and Slow Pads During the Power Sequence
Pin Status for Medium and Slow Pad Output Driver
VDDEH
VDD
POR
pad_mh (medium) pad_sh (slow)
Low
—
Asserted
Asserted
Asserted
Negated
Low
High impedance (Hi-Z)
Hi-Z
VDDEH
VDDEH
VDDEH
Low
VDD
VDD
Functional
The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins
during power up.
Before exiting the internal POR state, the pins go to a high-impedance state until POR negates. When the
internal POR negates, the functional state of the signal during reset applies and the weak-pull devices (up
or down) are enabled as defined in the device reference manual. If V is too low to correctly propagate
DD
the logic signals, the weak-pull devices can pull the signals to V
and V
.
DDE
DDEH
To avoid this condition, minimize the ramp time of the V supply to a time period less than the time
DD
required to enable the external circuitry connected to the device outputs.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
11
Freescale Semiconductor
Electrical Characteristics
3.7.1
Input Value of Pins During POR Dependent on VDD33
When powering up the device, V
must not lag the latest V
or RESET power pin (V
) by
DD33
DDSYN
DDEH6
more than the V
lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
DD33
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. V can lag V or the RESET power
DD33
DDSYN
pin (V
), but cannot lag both by more than the V
lag specification. This V
lag specification
DDEH6
DD33
DD33
applies during power up only. V
has no lead or lag requirements when powering down.
DD33
3.7.2
Power-Up Sequence (VRC33 Grounded)
The 1.5 V V power supply must rise to 1.35 V before the 3.3 V V
power supply and the RESET
DDSYN
DD
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, V must be within specification before the 3.3 V POR and the RESET
DD
POR negate.
VDDSYN and RESET Power
VDD
2.0 V
1.35 V
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
Figure 2. Power-Up Sequence (V
Grounded)
RC33
3.7.3
Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence with V
grounded is if V decreases to less than
DD
RC33
its operating range, V
or the RESET power must decrease to less than 2.0 V before the V power
DDSYN
DD
increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed
POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
12
Freescale Semiconductor
Electrical Characteristics
3.8
DC Electrical Specifications
Table 9. DC Electrical Specifications (T = T – T )
A
L
H
Spec
Characteristic
Symbol
Min
Max.
Unit
1
2
3
4
5
6
8
9
Core supply voltage (average DC RMS voltage)
Input/output supply voltage (fast input/output) 1
Input/output supply voltage (slow and medium input/output)
3.3 V input/output buffer voltage
VDD
VDDE
1.35
1.62
3.0
3.0
3.0
4.5
4.5
3.0
0.8
3.0
1.65
3.6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDDEH
VDD33
VRC33
VDDA
5.25
3.6
Voltage regulator control input voltage
Analog supply voltage 2
3.6
5.25
Flash programming voltage 3
VPP
5.25
Flash read voltage
VFLASH
VSTBY
VDDSYN
VIH_F
3.6
10 SRAM standby voltage 4
1.2
11 Clock synthesizer operating voltage
12 Fast I/O input high voltage
3.6
0.65 × VDDE
VSS – 0.3
VDDE + 0.3
0.35 × VDDE
VDDEH + 0.3
0.35 × VDDEH
13 Fast I/O input low voltage
VIL_F
14 Medium and slow I/O input high voltage
15 Medium and slow I/O input low voltage
16 Fast input hysteresis
VIH_S
VIL_S
0.65 × VDDEH
VSS – 0.3
VHYS_F
VHYS_S
VINDC
VOH_F
0.1 × VDDE
0.1 × VDDEH
17 Medium and slow I/O input hysteresis
18 Analog input voltage
VSSA – 0.3
VDDA + 0.3
—
19 Fast output high voltage ( IOH_F = –2.0 mA )
0.8 × VDDE
20 Slow and medium output high voltage
IOH_S = –2.0 mA
VOH_S
VOL_F
VOL_S
0.80 × VDDEH
0.85 × VDDEH
—
V
IOH_S = –1.0 mA
21 Fast output low voltage ( IOL_F = 2.0 mA )
—
—
0.2 × VDDE
V
V
22 Slow and medium output low voltage
IOL_S = 2.0 mA
0.20 × VDDEH
0.15 × VDDEH
IOL_S = 1.0 mA
23 Load capacitance (fast I/O) 5
DSC (SIU_PCR[8:9] ) = 0b00
—
—
—
—
10
20
30
50
pF
pF
pF
pF
= 0b01
= 0b10
= 0b11
CL
24 Input capacitance (digital pins)
25 Input capacitance (analog pins)
CIN
—
—
7
pF
pF
CIN_A
10
26 Input capacitance:
(Shared digital and analog pins AN[12]_MA[0]_SDS,
AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK)
CIN_M
—
12
pF
MPC5533 Microcontroller Data Sheet, Rev. 0.0
13
Freescale Semiconductor
Electrical Characteristics
Table 9. DC Electrical Specifications (T = T – T ) (continued)
A
L
H
Spec
Characteristic
Symbol
Min
Max.
Unit
27a Operating current 1.5 V supplies @ 82 MHz: 6, 7
VDD (including VDDF max current) @1.65 V high use 8, 9, 10, 11, 12
VDD (including VDDF max current) @1.35 V high use 8, 9, 10, 11, 12
IDD
IDD
—
—
250
180
mA
mA
27b Operating current 1.5 V supplies @ 68 MHz: 13, 14
VDD (including VDDF max current) @1.65 V high use15, 16, 17
VDD (including VDDF max current) @1.35 V high use 15, 16, 17
IDD
IDD
—
—
210
160
mA
mA
27c Operating current 1.5 V supplies @ 42 MHz: 13, 14
VDD (including VDDF max current) @1.65 V high use 15, 16, 17
VDD (including VDDF max current) @1.35 V high use 15, 16, 17
IDD
IDD
—
—
130
110
mA
mA
27d Refer to Figure 3 for an interpolation of this data.18
IDD_STBY @ 25o C
V
STBY @ 0.8 V
IDD_STBY
IDD_STBY
IDD_STBY
—
—
—
20
30
50
μA
μA
μA
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDD_STBY @ 60o C
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDD_STBY
IDD_STBY
IDD_STBY
—
—
—
70
100
200
μA
μA
μA
IDD_STBY @ 150o C (Tj)
VSTBY @ 0.8 V
IDD_STBY
IDD_STBY
IDD_STBY
—
—
—
1200
1500
2000
μA
μA
μA
VSTBY @ 1.0 V
VSTBY @ 1.2 V
28 Operating current 3.3 V supplies @ fMAX MHz
19
VDD33
IDD_33
—
2 + (values
derived from
procedure of
mA
footnote 19
)
VFLASH
IVFLASH
IDDSYN
—
—
10
15
mA
mA
VDDSYN
29 Operating current 5.0 V supplies (12 MHz ADCLK):
VDDA (VDDA0 + VDDA1
Analog reference supply current (VRH, VRL
VPP
)
IDD_A
IREF
IPP
—
—
—
20.0
1.0
25.0
mA
mA
mA
)
30 Operating current VDDE supplies: 20
VDDEH1
VDDE2
VDDE3
VDDEH4
VDDE5
VDDEH6
VDDE7
VDDEH8
VDDEH9
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
—
—
—
—
—
—
—
—
—
Refer to
mA
mA
mA
mA
mA
mA
mA
mA
mA
Footnote 20
MPC5533 Microcontroller Data Sheet, Rev. 0.0
14
Freescale Semiconductor
Electrical Characteristics
Table 9. DC Electrical Specifications (T = T – T ) (continued)
A
L
H
Spec
Characteristic
Symbol
Min
Max.
Unit
31 Fast I/O weak pullup current 21
1.62–1.98 V
2.25–2.75 V
3.00–3.60 V
10
20
20
110
130
170
μA
μA
μA
IACT_F
Fast I/O weak pulldown current 21
1.62–1.98 V
10
20
20
100
130
170
μA
μA
μA
2.25–2.75 V
3.00–3.60 V
32 Slow and medium I/O weak pullup/down current 21
3.0–3.6 V
4.5–5.5 V
IACT_S
10
20
150
170
μA
μA
33 I/O input leakage current 22
34 DC injection current (per pin)
35 Analog input current, channel off 23
IINACT_D
IIC
–2.5
–2.0
–150
2.5
2.0
μA
mA
nA
IINACT_A
150
35a Analog input current, shared analog / digital pins
(AN[12], AN[13], AN[14], AN[15])
IINACT_AD
–2.5
2.5
μA
36
V
SS to VSSA differential voltage 24
VSS – VSSA
VRL
VRL – VSSA
VRH
–100
VSSA – 0.1
–100
VDDA – 0.1
4.5
100
VSSA + 0.1
100
mV
V
37 Analog reference low voltage
38 VRL differential voltage
mV
V
39 Analog reference high voltage
VDDA + 0.1
5.25
40 VREF differential voltage
VRH – VRL
V
41 VSSSYN to VSS differential voltage
42 VRCVSS to VSS differential voltage
43 VDDF to VDD differential voltage
VSSSYN – VSS
VRCVSS – VSS
VDDF – VDD
VRC33 – VDDSYN
VIDIFF
–50
50
mV
mV
mV
V
–50
50
–100
–0.1
100
43a VRC33 to VDDSYN differential voltage
44 Analog input differential signal range (with common mode 2.5 V)
45 Operating temperature range, ambient (packaged)
46 Slew rate on power-supply pins
0.1 25
2.5
–2.5
V
TA = (TL to TH)
—
TL
TH
οC
V/ms
—
50
1
2
3
4
5
6
7
8
9
VDDE2 and VDDE3 are limited to 2.25–3.6 V only if EBTS = 0; VDDE2 and VDDE3 have a range of 1.6–3.6 V if EBTS = 1.
| VDDA0 – VDDA1 | must be < 0.1 V.
VPP can drop to 3.0 V during read operations.
If standby operation is not required, connect VSTBY to ground.
Applies to CLKOUT, external bus pins, and Nexus pins.
Maximum average RMS DC current.
Figure 3 shows an illustration of the IDD_STBY values interpolated for these temperature values.
Average current measured on Automotive benchmark.
Peak currents can be higher on specialized code.
10 High use current measured while running optimized SPE assembly code with all channels of the eTPU running autonomously, plus
the eDMA transferring data continuously from SRAM to SRAM.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
15
Freescale Semiconductor
Electrical Characteristics
11 Power requirements for the VDD33 supply depend on the frequency of operation, load of all I/O pins, and the voltages on the I/O
segments. Refer to Table 11 for values to calculate power dissipation for specific operation.
12 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The
total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.
13 Maximum average RMS DC current.
14 Figure 3 shows an illustration of the IDD_STBY values interpolated for these temperature values.
15 Average current measured on automotive benchmark.
16 Peak currents can be higher on specialized code.
17 High use current measured while running optimized SPE assembly code with all channels of the eTPU running autonomously, plus
the eDMA transferring data continuously from SRAM to SRAM.
18 Figure 3 shows an illustration of the IDD_STBY values interpolated for these temperature values.
19 Power requirements for the VDD33 supply depend on the frequency of operation, load of all I/O pins, and the voltages on the I/O
segments. Refer to Table 11 for values to calculate the power dissipation for a specific operation.
20 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The
total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.
21 Absolute value of current, measured at VIL and VIH.
22 Weak pullup/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh.
23 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 oC
to 12 oC, in the ambient temperature range of 50 oC to 125 oC. Applies to pad types: pad_a and pad_ae.
24
V
refers to both VSSA0 and VSSA1. | VSSA0 – VSSA1 | must be < 0.1 V.
SSA
25 Up to 0.6 V during power up and power down.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
16
Freescale Semiconductor
Electrical Characteristics
Figure 3 shows an approximate interpolation of the I
worst-case specification to estimate values at
STBY
different voltages and temperatures. The vertical lines shown at 25 οC, 60 οC, and 150 οC in Figure 3 are
the I
specifications (27d) listed in Table 9.
DD_STBY
Istby vs. Junction Temp
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
0.8V
1.0V
1.2V
800
700
600
500
400
300
200
100
0
0
10
20
30
40
50
60
70
80
90
100 110 120 130 140 150
Temp (C)
Figure 3. I
Worst-case Specifications
STBY
MPC5533 Microcontroller Data Sheet, Rev. 0.0
17
Freescale Semiconductor
Electrical Characteristics
3.8.1
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The
power consumption is the sum of all output pin currents for a segment. The output pin current can be
calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to
calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table 10.
1
Table 10. I/O Pad Average DC Current (T = T – T )
A
L
H
Drive Select /
Slew Rate
Control Setting
Frequency
(MHz)
Spec
Pad Type
Symbol
Load2 (pF)
Voltage (V)
Current (mA)
1
25
10
2
50
50
50
200
50
50
50
200
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
5.25
5.25
5.25
5.25
5.25
5.25
5.25
5.25
3.6
11
01
00
00
11
01
00
00
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
8.0
3.2
0.7
2.4
17.3
6.5
1.1
3.9
2.8
5.2
8.5
11.0
1.6
2.9
4.2
6.7
2.4
4.4
7.2
9.3
1.3
2.5
3.5
5.7
1.7
3.1
5.1
6.6
1.0
1.8
2.5
4.0
2
Slow
IDRV_SH
3
4
2
5
50
20
3.33
3.33
66
66
66
66
66
66
66
66
56
56
56
56
56
56
56
56
40
40
40
40
40
40
40
40
6
Medium
IDRV_MH
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3.6
3.6
3.6
1.98
1.98
1.98
1.98
3.6
3.6
3.6
3.6
Fast
IDRV_FC
1.98
1.98
1.98
1.98
3.6
3.6
3.6
3.6
1.98
1.98
1.98
1.98
1
2
These values are estimates from simulation and are not tested. Currents apply to output pins only.
All loads are lumped.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
18
Freescale Semiconductor
Electrical Characteristics
3.8.2
I/O Pad VDD33 Current Specifications
The power consumption of the V
supply dependents on the usage of the pins on all I/O segments. The
DD33
power consumption is the sum of all input and output pin V
currents for all I/O segments. The output
DD33
pin V
current can be calculated from Table 11 based on the voltage, frequency, and load on all fast
DD33
(pad_fc) pins. The input pin V
current can be calculated from Table 11 based on the voltage,
DD33
frequency, and load on all pad_sh and pad_mh pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table 11.
1
Table 11. V
Pad Average DC Current (T = T – T )
DD33
A
L
H
Frequency
(MHz)
Load 2
(pF)
VDD33
(V)
VDDE
(V)
Drive
Select
Current
(mA)
Spec
Pad Type
Symbol
Inputs
1
2
Slow
I33_SH
I33_MH
66
66
0.5
0.5
3.6
3.6
5.5
5.5
NA
NA
0.003
0.003
Medium
Outputs
3
66
66
66
66
66
66
66
66
56
56
56
56
56
56
56
56
40
40
40
40
40
40
40
40
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0.35
0.53
0.62
0.79
0.35
0.44
0.53
0.70
0.30
0.45
0.52
0.67
0.30
0.37
0.45
0.60
0.21
0.31
0.37
0.48
0.21
0.27
0.32
0.42
4
5
3.6
6
3.6
7
1.98
1.98
1.98
1.98
3.6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
3.6
3.6
3.6
Fast
I33_FC
1.98
1.98
1.98
1.98
3.6
3.6
3.6
3.6
1.98
1.98
1.98
1.98
1
2
These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input
pins for the slow and medium pads only.
All loads are lumped.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
19
Freescale Semiconductor
Electrical Characteristics
3.9
Oscillator and FMPLL Electrical Characteristics
Table 12. FMPLL Electrical Specifications
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
PLL reference frequency range: 1
Crystal reference
fref_crystal
fref_ext
8
8
20
20
1
MHz
External reference
Dual controller (1:1 mode)
fref_1:1
24
fsys ÷ 2
3
2
3
4
5
System frequency 2
fsys
tCYC
f
ICO(MIN) ÷ 2RFD
fMAX
MHz
ns
System clock period
—
100
7.4
1 ÷ fsys
1000
17.5
—
Loss of reference frequency 4
Self-clocked mode (SCM) frequency 5
EXTAL input high voltage crystal mode 6
fLOR
kHz
MHz
V
fSCM
VIHEXT
VXTAL + 0.4 V
6
7
All other modes
[dual controller (1:1), bypass, external reference]
VIHEXT
VILEXT
(VDDE5 ÷ 2) + 0.4 V
—
V
V
EXTAL input low voltage crystal mode 7
—
V
XTAL – 0.4 V
All other modes
[dual controller (1:1), bypass, external reference]
VILEXT
IXTAL
—
0.8
—
(VDDE5 ÷ 2) – 0.4 V
V
8
9
XTAL current 8
3
mA
pF
pF
pF
Total on-chip stray capacitance on XTAL
Total on-chip stray capacitance on EXTAL
CS_XTAL
CS_EXTAL
CL
1.5
1.5
10
—
Crystal manufacturer’s recommended capacitive
load
Refer to crystal
specification
Refer to crystal
specification
11
12
Discrete load capacitance to connect to EXTAL
Discrete load capacitance to connect to XTAL
PLL lock time 10
CL_EXTAL
(2 × CL)– CS_EXTAL
– CPCB_EXTAL
pF
pF
—
—
9
CL_XTAL
(2 × CL) – CS_XTAL
13
14
15
9
– CPCB_XTAL
tlpll
—
750
2
μs
Dual controller (1:1) clock skew
tskew
–2
ns
(between CLKOUT and EXTAL) 11, 12
16
17
18
Duty cycle of reference
Frequency unLOCK range
Frequency LOCK range
tDC
fUL
40
60
4.0
2.0
%
–4.0
–2.0
% fSYS
% fSYS
fLCK
MPC5533 Microcontroller Data Sheet, Rev. 0.0
20
Freescale Semiconductor
Electrical Characteristics
Table 12. FMPLL Electrical Specifications (continued)
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec
Characteristic
Symbol
Minimum
Maximum
Unit
CLKOUT period jitter, measured at fSYS max: 13, 14
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over a 2 ms interval)
CJITTER
%
fCLKOUT
19
—
—
5.0
0.01
Frequency modulation range limit 15
(do not exceed fsys maximum)
%fSYS
20
CMOD
0.8
2.4
ICO frequency
21
22
fico = [ fref_crystal × (MFD + 4) ] ÷ (PREDIV + 1) 16
fico = [ fref_ext × (MFD + 4) ] ÷ (PREDIV + 1)
fico
48
4
8017
MHz
MHz
Predivider output frequency (to PLL)
fPREDIV
20 18
1
Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency
remains within 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.
2
3
4
All internal registers retain data at 0 Hz.
Up to the maximum frequency rating of the device (refer to Table 1).
Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
5
The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below fLOR. SCM frequency is
measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.
NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.
6
7
Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vextal – Vxtal) must be ≥ 400 mV for the oscillator’s comparator to produce the output clock.
Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vxtal – Vextal) must be ≥ 400 mV for the oscillator’s comparator to produce the output clock.
Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
8
9
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
10 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal
startup time.
11 PLL is operating in 1:1 PLL mode.
12
V
= 3.0–3.6 V.
DDE
13 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider is set to divide-by-two.
14 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).
15 Modulation depth selected must not result in fsys value greater than the fsys maximum specified value.
16 f = f ÷ (2RFD
)
sys
ico
17 The ICO frequency can be higher than the maximum allowable system frequency. For this case, set the FMPLL synthesizer
control register reduced frequency divider (FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001). Therefore, for a 40 MHz
maximum device (system frequency), program the FMPLL to generate 80 MHz at the ICO output and then divide-by-two the
RFD to provide the 40 MHz clock.
18 Maximum value for dual controller (1:1) mode is (fMAX ÷ 2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).
MPC5533 Microcontroller Data Sheet, Rev. 0.0
21
Freescale Semiconductor
Electrical Characteristics
3.10 eQADC Electrical Characteristics
Table 13. eQADC Conversion Specifications (TA = TL to TH)
Spec
Characteristic
ADC clock (ADCLK) frequency 1
Symbol
Minimum
Maximum
Unit
1
FADCLK
CC
1
12
MHz
Conversion cycles
Differential
ADCLK
cycles
2
13 + 2 (15)
14 + 2 (16)
13 + 128 (141)
14 + 128 (142)
Single ended
3
4
5
6
7
8
9
Stop mode recovery time 2
Resolution 3
TSR
—
10
1.25
–4
—
—
4
μs
mV
INL: 6 MHz ADC clock
INL: 12 MHz ADC clock
DNL: 6 MHz ADC clock
DNL: 12 MHz ADC clock
Offset error with calibration
INL6
Counts 3
Counts
Counts
Counts
Counts
Counts
mA
INL12
DNL6
DNL12
OFFWC
GAINWC
IINJ
–8
8
–3 4
–6 4
–4 5
–8 6
–1
3 4
6 4
4 5
8 6
1
10 Full-scale gain error with calibration
11 Disruptive input injection current 7, 8, 9, 10
Incremental error due to injection current. All channels are
10 kΩ < Rs <100 kΩ
12
EINJ
–4
4
Counts
Channel under test has Rs = 10 kΩ,
IINJ = IINJMAX, IINJMIN
Total unadjusted error (TUE) for single ended conversions
13
TUE
–4
4
Counts
with calibration 11, 12, 13, 14, 15
1
2
Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The
maximum value is based on 800 KS/s and the minimum value is based on 20 MHz oscillator clock frequency divided by a
maximum 16 factor.
Stop mode recovery time begins when the ADC control register enable bits are set until the ADC is ready to perform
conversions.
3
4
5
6
7
At VRH – VRL = 5.12 V, one least significant bit (LSB) = 1.25, mV = one count.
Guaranteed 10-bit mono tonicity.
The absolute value of the offset error without calibration ≤ 100 counts.
The absolute value of the full scale gain error without calibration ≤ 120 counts.
Below disruptive current conditions, the channel being stressed has conversion values of: 0x3FF for analog inputs greater than
VRH, and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
8
9
Exceeding the limit can cause a conversion error on both stressed and unstressed channels. Transitions within the limit do not
affect device reliability or cause permanent damage.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.
10 This condition applies to two adjacent pads on the internal pad.
11 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
12 TUE does not apply to differential conversions.
13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.
14 TUE includes all internal device errors such as internal reference variation (75% Ref, 25% Ref).
15 Depending on the input impedance, the analog input leakage current (Table 9. DC Electrical Specifications, spec 35a) can
affect the actual TUE measured on analog channels AN[12], AN[13], AN[14], AN[15].
MPC5533 Microcontroller Data Sheet, Rev. 0.0
22
Freescale Semiconductor
Electrical Characteristics
3.11 H7Fb Flash Memory Electrical Characteristics
Spec
Table 14. Flash Program and Erase Specifications (T = T to T )
A
L
H
Initial
Spec
Flash Program Characteristic
Symbol
Min.
Typical 1
Max. 3 Unit
Max. 2
3
4
Doubleword (64 bits) program time 4
Page program time 4
Tdwprogram
Tpprogram
—
—
—
—
—
—
10
—
500
500
μs
μs
22
44 5
525
525
675
1800
7
16 KB block pre-program and erase time
48 KB block pre-program and erase time
64 KB block pre-program and erase time
128 KB block pre-program and erase time
T16kpperase
T48kpperase
T64kpperase
T128kpperase
325
435
525
675
5000
5000
5000
7500
ms
ms
ms
ms
9
10
8
Minimum operating frequency for program and erase
operations 6
11
—
25
—
—
—
MHz
Typical program and erase times are calculated at 25 oC operating temperature using nominal supply values.
Initial factory condition: ≤ 100 program/erase cycles, 25 oC, using a typical supply voltage measured at a minimum system
1
2
frequency of 80 MHz.
3
The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized
but not guaranteed.
4
5
6
Actual hardware programming times. This does not include software overhead.
Page size is 128 bits (4 words).
The read frequency of the flash can range up to the maximum operating frequency. There is no minimum read frequency
condition.
Table 15. Flash EEPROM Module Life (T = T to T )
A
L
H
Spec
Characteristic
Symbol
Min.
Typical 1 Unit
cycles
100,000 cycles
Number of program/erase cycles per block for 16 KB, 48 KB, and
64 KB blocks over the operating temperature range (TJ)
1a
P/E
100,000
—
Number of program/erase cycles per block for 128 KB blocks over the
operating temperature range (TJ)
1b
2
P/E
1000
Data retention
Retention
Blocks with 0–1,000 P/E cycles
Blocks with 1,001–100,000 P/E cycles
20
5
—
—
years
1
Typical endurance is evaluated at 25o C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for
Nonvolatile Memory.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
23
Freescale Semiconductor
Electrical Characteristics
Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference
manual for definitions of these bit fields.
1
Table 16. FLASH_BIU Settings vs. Frequency of Operation
DPFEN 2
Target Maximum Frequency (MHz)
APC
RWSC
WWSC
IPFEN 2
PFLIM 3
BFEN 2
Up to and including 27 MHz 4, 5
0b000
0b000
0b01
0b0
0b1
0b0
0b1
0b000
to
0b0
0b1
0b010
Up to and including 52 MHz 6
Up to and including 77 MHz 7
Up to and including 82 MHz 8
Reset values:
0b001
0b010
0b011
0b111
0b001
0b010
0b011
0b111
0b01
0b01
0b01
0b11
0b0
0b1
0b0
0b1
0b000
to
0b010
0b0
0b1
0b0
0b1
0b0
0b1
0b000
to
0b010
0b0
0b1
0b0
0b1
0b0
0b1
0b000
to
0b010
0b0
0b1
0b0
0b0
0b000
0b0
1
Illegal combinations exist. Use entries from the same row in this table.
For maximum flash performance, set to 0b1.
2
3
4
5
6
7
8
For maximum flash performance, set to 0b010.
27 MHz parts allow for 25 MHz system clock + 2% frequency modulation (FM).
The APC, RWSC, and WWSC combination requires setting the PRD bit to 1 in the flash MCR register.
52 MHz parts allow for 50 MHz system clock + 2% FM.
77 MHz parts allow for 75 MHz system clock + 2% FM.
82 MHz parts allow for 80 MHz system clock + 2% FM.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
24
Freescale Semiconductor
Electrical Characteristics
3.12 AC Specifications
3.12.1 Pad AC Specifications
1
Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)
2, 3, 4
SRC / DSC
(binary)
Out Delay
(ns)
Rise / Fall 4, 5
(ns)
Load Drive
(pF)
Spec
Pad
26
82
15
60
50
200
50
11
01
00
11
01
00
75
40
1
Slow high voltage (SH)
137
377
476
16
80
200
50
200
260
8
200
50
43
30
200
50
34
15
2
3
Medium high voltage (MH)
61
35
200
50
192
239
100
125
2.7
2.5
2.4
2.3
7500
9000
200
10
00
01
10
11
—
—
20
Fast
3.1
30
50
4
5
Pullup/down (3.6 V max)
Pullup/down (5.5 V max)
—
—
50
50
1
These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at:
VDD = 1.35–1.65 V; VDDE = 1.62–1.98 V; VDDEH = 4.5–5.25 V; VDD33 and VDDSYN = 3.0–3.6 V; and TA = TL to TH.
2
3
This parameter is supplied for reference and is guaranteed by design (not tested).
The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock,
add a maximum of one system clock to the output delay.
4
5
The output delay and rise and fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization rather than 100% tested.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
25
Freescale Semiconductor
Electrical Characteristics
Table 18. Derated Pad AC Specifications (VDDEH = 3.3 V, VDDE = 3.3 V)
1
2, 3, 4
SRC/DSC
(binary)
Out Delay
(ns)
Rise / Fall 3, 5
(ns)
Load Drive
(pF)
Spec
Pad
39
120
101
188
507
597
23
23
87
50
200
50
11
01
00
11
01
00
52
1
Slow high voltage (SH)
111
248
312
12
200
50
200
50
64
44
200
50
50
22
2
3
Medium high voltage (MH)
90
50
200
50
261
305
123
156
2.4
2.2
2.1
2.1
7500
9500
200
10
00
01
10
11
—
—
20
Fast
3.2
30
50
4
5
Pullup/down (3.6 V max)
Pullup/down (5.5 V max)
—
—
50
50
1
These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at:
VDD = 1.35–1.65 V; VDDE = 3.0–3.6 V; VDDEH = 3.0–3.6 V; VDD33 and VDDSYN = 3.0–3.6 V; and TA = TL to TH.
2
3
4
This parameter is supplied for reference and guaranteed by design (not tested).
The output delay, and the rise and fall, are calculated to 20% or 80% of the respective signal.
The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock, add a maximum of one
system clock to the output delay.
5
This parameter is guaranteed by characterization rather than 100% tested.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
26
Freescale Semiconductor
Electrical Characteristics
VDD ÷ 2
Pad
internal data
input signal
Rising-edge
out
Falling-edge
out
delay
delay
VOH
Pad
output
VOL
Figure 4. Pad Output Delay
3.13 AC Timing
3.13.1 Reset and Configuration Pin Timing
1
Table 19. Reset and Configuration Pin Timing
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
2
3
4
RESET pulse width
tRPW
tGPW
tRCSU
tRCH
10
2
—
—
—
—
tCYC
tCYC
tCYC
tCYC
RESET glitch detect pulse width
PLLCFG, BOOTCFG, WKPCFG, RSTCFG setup time to RSTOUT valid
PLLCFG, BOOTCFG, WKPCFG, RSTCFG hold time from RSTOUT valid
10
0
1
Reset timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
27
Freescale Semiconductor
Electrical Characteristics
2
RESET
1
RSTOUT
3
PLLCFG
BOOTCFG
RSTCFG
WKPCFG
4
Figure 5. Reset and Configuration Pin Timing
3.13.2 IEEE 1149.1 Interface Timing
1
Table 20. JTAG Pin AC Electrical Characteristics
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
2
3
4
5
6
7
8
9
TCK cycle time
tJCYC
tJDC
100
40
—
5
—
60
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock pulse width (measured at VDDE ÷ 2)
TCK rise and fall times (40% to 70%)
TMS, TDI data setup time
tTCKRISE
tTMSS, TDIS
tTMSH, TDIH
tTDOV
tTDOI
t
—
—
20
—
20
—
—
50
50
50
—
—
TMS, TDI data hold time
t
25
—
0
TCK low to TDO data valid
TCK low to TDO data invalid
TCK low to TDO high impedance
JCOMP assertion time
tTDOHZ
tJCMPPW
tJCMPS
tBSDV
—
100
40
—
—
—
50
50
10 JCOMP setup time to TCK low
11 TCK falling-edge to output valid
12 TCK falling-edge to output valid out of high impedance
13 TCK falling-edge to output high impedance (Hi-Z)
14 Boundary scan input valid to TCK rising-edge
15 TCK rising-edge to boundary scan input invalid
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
1
These specifications apply to JTAG boundary scan only. JTAG timing specified at: VDDE = 3.0–3.6 V and TA = TL to TH.
Refer to Table 21 for Nexus specifications.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
28
Freescale Semiconductor
Electrical Characteristics
TCK
2
3
3
2
1
Figure 6. JTAG Test Clock Input Timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 7. JTAG Test Access Port Timing
MPC5533 Microcontroller Data Sheet, Rev. 0.0
29
Freescale Semiconductor
Electrical Characteristics
TCK
10
JCOMP
9
Figure 8. JTAG JCOMP Timing
MPC5533 Microcontroller Data Sheet, Rev. 0.0
30
Freescale Semiconductor
Electrical Characteristics
TCK
11
13
Output
signals
12
Output
signals
14
15
Input
signals
Figure 9. JTAG Boundary Scan Timing
MPC5533 Microcontroller Data Sheet, Rev. 0.0
31
Freescale Semiconductor
Electrical Characteristics
3.13.3 Nexus Timing
1
Table 21. Nexus Debug Port Timing
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
2
3
4
5
6
7
8
9
MCKO cycle time
tMCYC
tMDC
1 2
40
8
tCYC
%
MCKO duty cycle
60
3.0
3.0
3.0
—
MCKO low to MDO data valid 3
MCKO low to MSEO data valid 3
MCKO low to EVTO data valid 3
EVTI pulse width
tMDOV
–1.5
–1.5
–1.5
4.0
1
ns
tMSEOV
tEVTOV
ns
ns
tEVTIPW
tEVTOPW
tTCYC
tTCYC
tMCYC
tCYC
%
EVTO pulse width
—
TCK cycle time
4 4
—
TCK duty cycle
tTDC
40
60
—
10 TDI, TMS data setup time
11 TDI, TMS data hold time
TCK low to TDO data valid
t
NTDIS, tNTMSS
8
ns
t
NTDIH, tNTMSH
tJOV
5
—
ns
12
VDDE = 2.25–3.0 V
DDE = 3.0–3.6 V
13 RDY valid to MCKO 5
0
0
12
10
—
ns
ns
—
V
—
—
1
JTAG specifications apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of
MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.35–1.65 V, VDDE = 2.25–3.6 V,
VDD33 and VDDSYN = 3.0–3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10.
2
3
4
The Nexus AUX port runs up to 82 MHz.
MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs.
Limit the maximum frequency to approximately 16 MHz (VDDE = 2.25–3.0 V) or 20 MHz (VDDE = 3.0–3.6 V) to meet the timing
specification for tJOV of [0.2 x tJCYC] as outlined in the IEEE-ISTO 5001-2003 specification.
5
The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly.
1
2
MCKO
4
5
3
MDO
MSEO
EVTO
Output Data Valid
Figure 10. Nexus Output Timing
MPC5533 Microcontroller Data Sheet, Rev. 0.0
32
Freescale Semiconductor
Electrical Characteristics
TCK
10
11
TMS, TDI
12
TDO
Figure 11. Nexus TDI, TMS, TDO Timing
MPC5533 Microcontroller Data Sheet, Rev. 0.0
33
Freescale Semiconductor
Electrical Characteristics
3.13.4 External Bus Interface (EBI) Timing
Table 22 lists the timing information for the external bus interface (EBI).
1, 2
Table 22. External Bus Operation Timing
External Bus Frequency 3
Characteristic
and
Spec
Symbol
Unit
Notes
20 MHz
33 MHz
40 MHz
Description
Min.
Max
—
Min.
Max
Min.
Max
—
Signalsaremeasured at
1
CLKOUT period
TC
24.4
17.5
—
14.9
ns
50% VDDE
.
2
3
4
CLKOUT duty cycle
CLKOUT rise time
CLKOUT fall time
tCDC
tCRT
tCFT
tCOH
45%
—
55%
45%
—
55%
—
45%
—
55%
TC
ns
ns
4
4
—
—
4
4
4
—
1.06
—
—
1.06
—
—
1.06
—
CLKOUT positive edge to
output signal invalid or
Hi-Z (hold time)
EBTS = 0
EBTS = 1
—
—
—
ns
1.5
1.5
1.5
External bus interface
CS[0:3]
Hold time selectable via
SIU_ECCR
ADDR[8:31]
DATA[0:15]
RD_WR
BDIP
[EBTS] bit.
5 5
WE/BE[0:1]
OE
TS
TA
CLKOUT positive edge to
output signal valid
(output delay)
tCOV
10.06
11.0
10.06
11.0
10.06
11.0
EBTS = 0
EBTS = 1
—
—
—
ns
External bus interface
CS[0:3]
ADDR[8:31]
DATA[0:15]
RD_WR
BDIP
Output valid time
selectable via
SIU_ECCR
6 5
[EBTS] bit.
WE/BE[0:1]
OE
TS
TA
MPC5533 Microcontroller Data Sheet, Rev. 0.0
34
Freescale Semiconductor
Electrical Characteristics
1, 2
Table 22. External Bus Operation Timing
External Bus Frequency 3
20 MHz 33 MHz
(continued)
Max
Characteristic
and
Spec
Symbol
Unit
Notes
40 MHz
Description
Min.
Max
Min.
Max
Min.
Input signal valid to
CLKOUT positive edge
(setup time)
External bus interface
7 5
tCIS
10.0
—
10.0
—
10.0
—
ns
ADDR[8:31]
DATA[0:15]
RD_WR
TS
TA
CLKOUT positive edge to
input signal invalid (hold
time)
External bus interface
8 5
tCIH
1.0
—
1.0
—
1.0
—
ns
ADDR[8:31]
DATA[0:15]
RD_WR
TS
TA
1
2
3
EBI timing specified at VDDE = 1.6–3.6 V (unless stated otherwise), TA = TL to TH, and CL = 30 pF with DSC = 0b10.
The external bus is limited to half the speed of the internal bus.
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
42 MHz parts allow for 40 MHz system clock + 2% FM; 68 MHz parts allow for a 66 MHz system clock + 2% FM, and
82 MHz parts allow for 80 MHz system clock + 2% FM.
4
5
6
Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V).
Available on the 324 package only; not available on the 208 package.
EBTS = 0 timings are tested and valid at VDDE = 2.25–3.6 V only; EBTS = 1 timings are tested and valid at VDDE = 1.6–3.6 V.
3.13.5 External Interrupt Timing (IRQ Signals)
1
Table 23. External Interrupt Timing
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
2
3
IRQ pulse-width low
IRQ pulse-width high
IRQ edge-to-edge time 2
tIPWL
TIPWH
tICYC
3
3
6
—
—
—
tCYC
tCYC
tCYC
1
2
IRQ timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH.
Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
35
Freescale Semiconductor
Electrical Characteristics
IRQ
2
1
3
Figure 12. External Interrupt Timing
3.13.6 eTPU Timing
1
Table 24. eTPU Timing
Spec
Characteristic
eTPU input channel pulse width
eTPU output channel pulse width
Symbol
Min.
Max
Unit
1
2
tICPW
4
2 2
—
—
tCYC
tCYC
tOCPW
1
2
eTPU timing specified at: VDDEH = 3.0–5.25 V and TA = TL to TH.
This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
2
eTPU
output
eTPU input
and TCRCLK
1
Figure 13. eTPU Timing
MPC5533 Microcontroller Data Sheet, Rev. 0.0
36
Freescale Semiconductor
Electrical Characteristics
3.13.7 DSPI Timing
1, 2
Table 25. DSPI Timing
40 MHz
66 MHz
Min.
80 MHz
Unit
Spec
Characteristic
SCK cycle time 3, 4
PCS to SCK delay5
After SCK delay6
SCK duty cycle
Symbol
Min.
Max
Max
Min.
Max
1
2
3
tSCK
tCSC
tASC
48.8 ns
46
5.8 ms
—
28.4 ns
26
3.5 ms
—
24.4 ns
22
2.9 ms
—
—
ns
ns
45
—
25
—
21
—
(tSCK ÷ 2) (tSCK ÷ 2)
(tSCK ÷ 2)
– 2 ns
(tSCK ÷ 2) (tSCK ÷ 2) (tSCK ÷ 2)
4
5
tSDC
tA
ns
ns
– 2 ns
+ 2 ns
+ 2 ns
– 2 ns
+ 2 ns
Slave access time
(SS active to SOUT driven)
—
25
—
—
25
—
25
Slave SOUT disable time
(SS inactive to SOUT Hi-Z, or
invalid)
6
tDIS
—
25
25
—
25
ns
7
8
PCSx to PCSS time
PCSS to PCSx time
tPCSC
tPASC
tSUI
4
5
—
—
4
5
—
—
4
5
—
—
ns
ns
Data setup time for inputs
Master (MTFE = 0)
20
2
–4
20
—
—
—
—
20
2
6
—
—
—
—
20
2
8
—
—
—
—
ns
ns
ns
ns
9
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
20
20
Data hold time for inputs
Master (MTFE = 0)
tHI
tSUO
tHO
–4
7
45
–4
—
—
—
—
–4
7
25
–4
—
—
—
—
–4
7
21
–4
—
—
—
—
ns
ns
ns
ns
10
11
12
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
Data valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
—
—
—
—
5
25
45
5
—
—
—
—
5
25
25
5
—
—
—
—
5
25
21
5
ns
ns
ns
ns
Data hold time for outputs
Master (MTFE = 0)
–5
5.5
8
—
—
—
—
–5
5.5
4
—
—
—
—
–5
5.5
3
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–5
–5
–5
1
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of
S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25 V, TA = TL to TH, and
CL = 50 pF with SRC = 0b11.
2
3
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
42 MHz parts allow for 40 MHz system clock + 2% FM; 68 MHz parts allow for a 66 MHz system clock + 2% FM, and
82 MHz parts allow for 80 MHz system clock + 2% FM.
The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.
These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.
4
5
6
7
The actual minimum SCK cycle time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.
MPC5533 Microcontroller Data Sheet, Rev. 0.0
37
Freescale Semiconductor
Electrical Characteristics
2
3
PCSx
1
4
SCK output
(CPOL=0)
4
SCK output
(CPOL=1)
10
9
Last data
SIN
First data
Data
Data
12
11
First data
Last data
SOUT
Figure 14. DSPI Classic SPI Timing—Master, CPHA = 0
PCSx
SCK output
(CPOL=0)
10
SCK output
(CPOL=1)
9
Data
Data
First data
Last data
SIN
12
11
SOUT
Last data
First data
Figure 15. DSPI Classic SPI Timing—Master, CPHA = 1
MPC5533 Microcontroller Data Sheet, Rev. 0.0
38
Freescale Semiconductor
Electrical Characteristics
3
2
SS
1
4
SCK input
(CPOL=0)
4
SCK input
(CPOL=1)
5
11
12
Data
6
First data
Last data
SOUT
9
10
First data
Data
Last data
SIN
Figure 16. DSPI Classic SPI Timing—Slave, CPHA = 0
SS
SCK input
(CPOL=0)
SCK input
(CPOL=1)
11
5
6
12
Last data
Data
Data
SOUT
SIN
First data
10
9
Last data
First data
Figure 17. DSPI Classic SPI Timing—Slave, CPHA = 1
MPC5533 Microcontroller Data Sheet, Rev. 0.0
39
Freescale Semiconductor
Electrical Characteristics
3
PCSx
4
1
2
SCK output
(CPOL=0)
4
SCK output
(CPOL=1)
9
10
SIN
First data
Last data
Last data
Data
12
11
SOUT
First data
Data
Figure 18. DSPI Modified Transfer Format Timing—Master, CPHA = 0
PCSx
SCK output
(CPOL=0)
SCK output
(CPOL=1)
10
9
SIN
Last data
First data
Data
12
Data
11
First data
Last data
SOUT
Figure 19. DSPI Modified Transfer Format Timing—Master, CPHA = 1
MPC5533 Microcontroller Data Sheet, Rev. 0.0
40
Freescale Semiconductor
Electrical Characteristics
3
2
SS
1
SCK input
(CPOL=0)
4
4
SCK input
(CPOL=1)
12
11
6
5
First data
9
Data
Data
Last data
10
SOUT
Last data
First data
SIN
Figure 20. DSPI Modified Transfer Format Timing—Slave, CPHA = 0
SS
SCK input
(CPOL=0)
SCK input
(CPOL=1)
11
5
6
12
Last data
First data
10
Data
Data
SOUT
SIN
9
First data
Last data
Figure 21. DSPI Modified Transfer Format Timing—Slave, CPHA = 1
8
7
PCSS
PCSx
Figure 22. DSPI PCS Strobe (PCSS) Timing
MPC5533 Microcontroller Data Sheet, Rev. 0.0
41
Freescale Semiconductor
Electrical Characteristics
3.13.8 eQADC SSI Timing
Table 26. EQADC SSI Timing Characteristics
Spec
Rating
Symbol
Minimum
Typical
Maximum
Unit
1, 2
2
3
4
5
6
7
8
FCK period (tFCK = 1 ÷ fFCK
Clock (FCK) high time
Clock (FCK) low time
SDS lead / lag time
)
tFCK
2
—
—
—
—
—
—
—
17
tSYS_CLK
ns
tFCKHT
tFCKLT
tSDS_LL
tSDO_LL
tEQ_SU
tEQ_HO
tSYS_CLK − 6.5
9 × (tSYS_CLK + 6.5)
tSYS_CLK − 6.5
8 × (tSYS_CLK + 6.5)
ns
–7.5
–7.5
22
+7.5
+7.5
—
ns
SDO lead / lag time
ns
EQADC data setup time (inputs)
EQADC data hold time (inputs)
ns
1
—
ns
1
2
SS timing specified at VDDEH = 3.0–5.25 V, TA = TL to TH, and CL = 25 pF with SRC = 0b11. Maximum operating frequency
varies depending on track delays, master pad delays, and slave pad delays.
FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number.
2
3
4
FCK
SDS
5
6
4
5
25th
1st (MSB)
2nd
26th
SDO
External device data sample at
FCK falling-edge
8
7
1st (MSB) 2nd
25th
26th
SDI
EQADC data sample at
FCK rising-edge
Figure 23. EQADC SSI Timing
MPC5533 Microcontroller Data Sheet, Rev. 0.0
42
Freescale Semiconductor
Mechanicals
4
Mechanicals
4.1
MPC5533 208 MAP BGA Pinout
Figure 24 is a pinout for the MPC5533 208 MAP BGA package.
NOTES
V
and V
are connected internally on the 208-ball package and
DDEH10
DDEH6
are listed as V
.
DDEH6
The MPC5500 devices are pin compatible for software portability and use
the primary function names to label the pins in the BGA diagram. Although
some devices do not support all the primary functions shown in the BGA
diagram, the muxed and GPIO signals on those pins remain available. See
the signals chapter in the device reference manual for the signal muxing.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSSA1 AN1
AN5
VRH
VRL
AN27 VSSA0 AN12 MDO2 MDO0 VDD33 VSS
VSS VDD
VSS MSEO0 TCK
A
B
C
D
E
F
VSS
AN9
AN11 VDDA1
AN38 AN21
A
B
C
D
E
F
REF
BYPC
AN22 AN25 AN28 VDDA0 AN13 MDO3 MDO1
VDD
VSS
AN0
AN4
AN3
AN6
AN7
AN23 AN32 AN33 AN14 AN15
VDDEH
VSTBY VDD
VSS
VDD
AN37
AN17 AN34 AN16
AN24 AN30 AN31 AN35
VSS
TMS
TDI
EVTO TEST
EVTI MSEO1
VDD33 AN39
ETPUA ETPUA
VSS
VDD
AN36
AN18
AN2
9
VDDE7
30
31
ETPUA ETPUA ETPUA
28 29 26
VDDEH
6
TDO MCKO JCOMP
ETPUA ETPUA ETPUA ETPUA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SOUTB PCSB3 SINB PCSB0
PCSA3 PCSB4 PCSB2 PCSB1
PCSB5 TXDA PCSA2 SCKB
G
H
J
G
H
J
24
27
25
21
ETPUA ETPUA ETPUA ETPUA
23 22 17 18
ETPUA ETPUA ETPUA ETPUA
20 19 14 13
ETPUA ETPUA ETPUA VDDEH
CNTXC RXDA RSTOUT VPP
WKP
K
L
K
L
16
15
7
1
ETPUA ETPUA ETPUA TCRCLK
TXDB CNRXC
RESET
12 11
6
A
CFG
ETPUA ETPUA ETPUA ETPUA
PLL
BOOT
VSS
SYN
RXDB
M
N
P
R
T
M
N
P
R
T
10
9
1
5
CFG0 CFG1
ETPUA ETPUA ETPUA
EMIOS EMIOS VDDEH EMIOS EMIOS
VRC
CTL
PLL
CFG1
VDD33
VDDE2
VDD33 VSS
CNTXA VDD
EXTAL
VSS
VDD
8
4
0
2
10
4
12
21
ETPUA ETPUA
GPIO
207
EMIOS EMIOS EMIOS EMIOS EMIOS
VSS VRC33 XTAL
VSS
VDD
3
2
6
8
16 17 22
GPIO EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
206
VDD
CNRXA CNRXB VDD
VSS
CS0
VSS
VDD
4
3
9
11
14
19
23
SYN
VSS
16
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
0
4
ENG
CNTXB VDDE5
CLK
VDD
15
VSS
1
VDD
2
OE
3
1
5
5
6
7
7
13
8
15
9
18
10
20
11
12
13
14
Figure 24. MPC5533 208 Package
MPC5533 Microcontroller Data Sheet, Rev. 0.0
43
Freescale Semiconductor
Mechanicals
4.2
MPC5533 324 PBGA Pinout
Figure 25 is a pinout for the MPC5533 324 PBGA package.
NOTE
The MPC5500 devices are pin compatible for software portability and use
the primary function names to label the pins in the BGA diagram. Although
some devices do not support all the primary functions shown in the BGA
diagram, the muxed and GPIO signals on those pins remain available. See
the signals chapter in the device reference manual for the signal muxing.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AN35 VSSA0 AN12 MDO11 MDO10 MDO8
AN32 VSSA0 AN13 MDO9 MDO7 MDO4 MDO0
15
16
17
18
19
20
21
22
VSSA1 AN1
AN5
VRH
VRL
AN27 AN28
AN26 AN31
VDD VDD33 VSS
A
B
VSS
VDD VSTBY AN37
AN11 VDDA1
A
REF
BYPC
AN16
AN20
AN9
AN0
AN4
AN3
AN23
AN22
AN6
VSS VDDE7
VDD33 VSS
VDD
VSS
AN36
VDD
VSS
AN39
AN8
AN19
AN17
AN38
B
ETPUA ETPUA
30
AN21
AN7
AN2
AN25 AN30 AN33 VDDA0 AN14 MDO5 MDO2 MDO1
VDDEH
VSS VDDE7 VDD
C
D
E
C
D
E
31
ETPUA ETPUA ETPUA
28 29 26
AN10 AN18
AN24 AN29
AN34
AN15 MDO6 MDO3
VSS VDDE7 TCK
VDDE7 TMS TDO
VDDE7 JCOMP EVTI
TDI
VDD
9
ETPUA ETPUA ETPUA ETPUA
24 27 25 21
TEST
EVTO
ETPUA ETPUA ETPUA ETPUA
23
F
F
22
17
18
ETPUA ETPUA ETPUA ETPUA
RDY MCKO MSEO0 MSEO1
G
H
J
G
H
J
20
19
14
13
ETPUA ETPUA ETPUA VDDEH
VDDEH GPIO GPIO
SINB
16 15 10
1
10
203
204
ETPUA ETPUA ETPUA ETPUA
12 11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDE7
SOUTB PCSB3 PCSB0 PCSB1
PCSA3 PCSB4 SCKB PCSB2
PCSB5 SOUTA SINA SCKA
PCSA1 PCSA0 PCSA2 VPP
PCSA4 TXDA PCSA5 VFLASH
6
9
ETPUA ETPUA ETPUA ETPUA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
K
8
7
2
5
ETPUA ETPUA ETPUA ETPUA
L
L
4
3
0
1
TCRCLK
A
VDDE2 VDDE2 VSS
M
N
P
BDIP
CS1
CS0
M
N
P
VSS
VSS
VSS VDDE2 VSS
VSS VDDE2 VSS
CS3
CS2
WE1
WE0
ADDR ADDR
RST
CNTXC RXDA RSTOUT
CFG
RD_WR
VDDE2
VDD33
TA
16
17
ADDR ADDR
WKP
CNRXC TXDB RESET
CFG
R
T
R
T
18
19
ADDR ADDR ADDR
20 21 12
BOOT
CFG1
VSS
SYN
VRC
VSS
RXDB
TS
NC
Note:
No connect. Reserved (W18 & Y19 are shorted to each other)
ADDR ADDR ADDR ADDR
VDDEH PLL
BOOT
EXTAL
XTAL
U
V
U
V
22
23
13
14
6
CFG1 CFG0
ADDR ADDR ADDR ADDR
VRC
CTL
PLL
CFG0
VDD
24
25
15
31
ADDR
26
ADDR
30
DATA DATA DATA EMIOS EMIOS VDDEH EMIOS EMIOS
VDD
SYN
VDDE2 VDD33 VDDE2
VDDE5
NC
VSS
NC
VDD VRC33
VSS
W
Y
VDDE2
VSS
VDD
W
Y
11
12
14
2
8
4
12
21
ADDR ADDR
28
DATA DATA DATA GPIO DATA DATA EMIOS EMIOS EMIOS EMIOS EMIOS
VDDE2
CNTXA VDDE5
VDD VDD33
VSS
VDD
VDD
27
8
9
10
207
13
15
6
10
15
13
17
16
22
ADDR
29
DATA
1
GPIO DATA DATA
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
VDDE2
VDDE2
VDDE2
CNRXA VDDE5 CLKOUT VSS
VDD
AA
VSS
AA
AB
206
5
7
OE
9
3
5
9
19
23
DATA DATA DATA DATA DATA
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
ENG
CNTXB CNRXB VDDE5
CLK
VSS
22
AB VSS
1
VDD VDDE2
0
2
3
4
6
0
1
4
7
11
14
18
20
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
Figure 25. MPC5533 324 Package
MPC5533 Microcontroller Data Sheet, Rev. 0.0
44
Freescale Semiconductor
Mechanicals
4.3
MPC5533 208-Pin Package Dimensions
The package drawings of the MPC5533 208-pin MAP BGA are shown in Figure 26.
Figure 26. MPC5533 208-Pin Package
MPC5533 Microcontroller Data Sheet, Rev. 0.0
45
Freescale Semiconductor
Mechanicals
Figure 26. MPC5533 208 MAP BGA Package (continued)
MPC5533 Microcontroller Data Sheet, Rev. 0.0
46
Freescale Semiconductor
Mechanicals
4.4
MPC5533 324-Pin Package Dimensions
The package drawings of the MPC5533 324-pin TEPBGA package are shown in Figure 27.
Figure 27. MPC5533 324 TEPBGA Package
MPC5533 Microcontroller Data Sheet, Rev. 0.0
47
Freescale Semiconductor
Mechanicals
Figure 27. MPC5533 324 TEPBGA Package (continued)
MPC5533 Microcontroller Data Sheet, Rev. 0.0
48
Freescale Semiconductor
Revision History for the MPC5533 Data Sheet
5
Revision History for the MPC5533 Data Sheet
Table 27 provides a revision history of the MPC5533 Data Sheet.
Table 27. Revision History for the MPC5533 Data Sheet
Substantive Change(s)
Version
Initial version for MPC5533.
Rev. 0.0
MPC5533 Microcontroller Data Sheet, Rev. 0.0
49
Freescale Semiconductor
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Document Number: MPC5533
Rev. 0.0
10 Oct 2008
相关型号:
MPC5533MVF66
FLASH, 66MHz, MICROCONTROLLER, PBGA208, 17 X 17 MM, 1 MM PITCH, MO-151AAF-1, PLASTIC, MAPBGA-208
NXP
MPC5533MVM40
FLASH, 40MHz, MICROCONTROLLER, PBGA208, 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-151AAF-1, PLASTIC, MAPBGA-208
NXP
MPC5533MVM66
FLASH, 66MHz, MICROCONTROLLER, PBGA208, 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-151AAF-1, PLASTIC, MAPBGA-208
NXP
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