MPC5553AZQ80R2 [FREESCALE]
Microcontroller; 微控制器
| 型号： | MPC5553AZQ80R2 |
| 厂家： | 
Freescale |
| 描述： | Microcontroller |
| 文件： | 总60页 (文件大小：1585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC5553
Rev. 0, 06/2006
Freescale Semiconductor
Data Sheet: Product Preview
MPC5553 Microcontroller
Data Sheet
by: Microcontroller Division
Contents
This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5553
microcontroller device. For functional characteristics,
refer to the MPC5553/MPC5554 Microcontroller
Reference Manual.
1
2
3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5
3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 EMI (Electromagnetic Interference) Characteristics 9
3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 VRC/POR Electrical Specifications . . . . . . . . . . . . 10
3.7 Power Up/Down Sequencing. . . . . . . . . . . . . . . . . 11
3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 13
3.9 Oscillator & FMPLL Electrical Characteristics . . . . 19
3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 20
3.11 H7Fa Flash Memory Electrical Characteristics . . . 21
3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14 Fast Ethernet AC Timing Specifications . . . . . . . . 45
1
Overview
The MPC5553 microcontroller (MCU) is a member of
the MPC5500 family of microcontrollers based on the
PowerPC™ Book E architecture. This family of parts
contains many new features coupled with high
performance CMOS technology to provide substantial
reduction of cost per feature and significant performance
improvement over the MPC500 family.
4
5
Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.1 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . 55
The host processor core of this device is compatible with
the PowerPC Book E architecture. It is 100% user mode
compatible (with floating point library) with the classic
PowerPC instruction set. The Book E architecture has
enhancements that improve the PowerPC architecture’s
fit in embedded applications. This core also has
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
additional instructions, including digital signal
processing (DSP) instructions, beyond the classic
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
• Preliminary—Subject to Change Without Notice
Overview
PowerPC instruction set. This family of parts contains many new features coupled with high performance
CMOS technology to provide significant performance improvement over the MPC565.
The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the
8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM
and 1.5 Mbyte internal Flash memory. Both the internal SRAM and the Flash memory can hold
instructions and data. The external bus interface has been designed to support most of the standard
memories used with the MPC5xx family.
The complex I/O timer functions of the MPC5500 family are performed by an enhanced time processor
unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over
the TPU by providing 24-bit timers, double action hardware channels, variable number of parameters per
channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be
programmed using a high-level programming language.
The less complex timer functions of the MPC5500 family are performed by the enhanced modular
input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single action, double
action, pulse width modulation (PWM), and modulus counter operation. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIO) signals.
The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter
(eQADC).
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also found in the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing
of eQADC trigger sources, daisy chaining the DSPIs and external interrupt signal multiplexing.
MPC5553 Microcontroller Data Sheet, Rev. 0
2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Ordering Information
2
Ordering Information
5553
M PC
M
80 R2
ZP
Qualification Status
Core Code
Device Number
Temperature Range
Package Identifier
Operating Frequency (MHz)
Tape and Reel Status
Temperature Range
M = -40° C to 125° C
A = -55° C to 125° C
Package Identifier
Operating Frequency
80 = 80MHz
112 = 112MHz
132 = 132MHz
Tape and Reel Status
R2 = Tape and Reel
(blank) = Trays
ZP = 416PBGA SnPb
VR = 416PBGA Pb-free
VF = 208MAPBGA SnPb
VM = 208MAPBGA Pb-free
ZQ = 324PBGA SnPb
VZ = 324PBGA Pb-free
Qualification Status
P = Pre Qualification
M = Full Spec Qualified
Note: Not all options are available on all devices. Refer to Table 1.
Figure 1. MPC5500 Family Part Number Example
Table 1. Orderable Part Numbers
Speed
Freescale Part
Number
Max Speed1
(MHz) (fMAX)
Description
Temperature
(MHz)
MPC5553MVR132
MPC5553MZP132
MPC5553MVZ132
MPC5553MZQ132
MPC5553MVF132
MPC5553MVM132
MPC5553MVR112
MPC5553MZP112
MPC5553MVZ112
MPC5553MZQ112
MPC5553MVF112
MPC5553MVM112
MPC5553MVR80
MPC5553MZP80
MPC5553MVZ80
MPC5553MZQ80
MPC5553 Lead free 416 package
MPC5553 Lead 416 package
MPC5553 Lead free 324 package
MPC5553 Lead 324 package
MPC5553 Lead 208 package
MPC5553 Lead free 208 package
MPC5553 Lead free 416 package
MPC5553 Lead 416 package
MPC5553 Lead free 324 package
MPC5553 Lead 324 package
MPC5553 Lead 208 package
MPC5553 Lead free 208 package
MPC5553 Lead free 416 package
MPC5553 Lead 416 package
MPC5553 Lead free 324 package
MPC5553 Lead 324 package
132
132
132
132
132
132
112
112
112
112
112
112
80
132
132
132
132
132
132
114
114
114
114
114
114
82
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
-40° C to 125° C
80
82
80
82
80
82
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
3
Electrical Characteristics
Table 1. Orderable Part Numbers (continued)
MPC5553MVF80
MPC5553 Lead 208 package
80
80
82
82
-40° C to 125° C
-40° C to 125° C
MPC5553MVM80
MPC5553 Lead free 208 package
1
Speed is the nominal maximum frequency. Max Speed is the maximum speed allowed including any frequency
modulation. 80-MHz parts allow for 80 MHz + 2% modulation. However, 132-MHz allows only 128 MHz + 2% FM.
3
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MCU.
3.1
Maximum Ratings
1
Table 2. Absolute Maximum Ratings
Num
Characteristic
1.5V Core Supply Voltage 3
Symbol
Min
Max2
Unit
1
2
3
4
5
6
7
8
9
VDD
VPP
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
–0.3
1.7
6.5
1.7
4.6
1.7
4.6
4.6
4.6
5.5
4.6
6.5
V
V
V
V
V
V
V
V
V
V
V
Flash Program/Erase Voltage
Flash Core Voltage
VDDF
Flash Read Voltage
VFLASH
VSTBY
VDDSYN
VDD33
VRC33
VDDA
SRAM Standby Voltage
Clock Synthesizer Voltage
3.3V I/O Buffer Voltage
Voltage Regulator Control Input Voltage
Analog Supply Voltage (reference to VSSA
–0.3
)
– 0.3
– 0.3
– 0.3
10 I/O Supply Voltage (Fast I/O Pads) 4
11 I/O Supply Voltage (Slow/Medium I/O Pads) 4
12 DC Input Voltage5
VDDE
VDDEH
VIN
VDDEH powered I/O Pads, except eTPUB15 and
SINB (DSPI_B_SIN)
VDDEH powered I/O Pads (eTPUB15 and SINB)
VDDE powered I/O Pads
–1.06
6.58
V
–0.37
–1.06
6.58
4.69
13 Analog Reference High Voltage (reference to VRL)
14 VSS Differential Voltage
VRH
– 0.3
– 0.1
5.5
0.1
V
V
V
V
V
V
V
V
VSS – VSSA
DD – VDDA
15 VDD Differential Voltage
V
– VDDA
– 0.3
VDD
5.5
16
VREF Differential Voltage
VRH – VRL
VRH – VDDA
VRL – VSSA
VDDEH – VDDA
VDDF – VDD
17 VRH to VDDA Differential Voltage
– 5.5
5.5
18
19
V
RL to VSSA Differential Voltage
DDEH to VDDA Differential Voltage
– 0.3
0.3
V
–VDDA
–0.3
VDDEH
0.3
20 VDDF to VDD Differential Voltage
21 This spec has been moved to Table 9, spec 43a.
22 VSSSYN to VSS Differential Voltage
V
SSSYN – VSS
–0.1
0.1
V
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
4
Freescale Semiconductor
Electrical Characteristics
1
Table 2. Absolute Maximum Ratings (continued)
Num
Characteristic
Symbol
Min
Max2
Unit
23 VRCVSS to VSS Differential Voltage
24 Maximum DC Digital Input Current 10 (per pin, applies to all
digital pins)5
VRCVSS – VSS
IMAXD
–0.1
–2
0.1
2
V
mA
25 Maximum DC Analog Input Current 11 (per pin, applies to all
analog pins)
26 Maximum Operating Temperature Range 12 — Die Junction
Temperature
IMAXA
TJ
–3
3
mA
oC
– 40.0
150.0
27 Storage Temperature Range
28 Maximum Solder Temperature 13
29 Moisture Sensitivity Level 14
TSTG
TSDR
MSL
– 55.0
—
150.0
260.0
3
oC
oC
—
1
2
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or
cause permanent damage to the device.
Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have
not yet been determined.
3
4
5
1.5V +/– 10% for proper operation. This parameter is specified at a maximum junction temperature of 150C.
All functional non-supply I/O pins are clamped to VSS and VDDE or VDDEH.
AC signal over and undershoot of the input voltages of up to +/– 2.0 volts is permitted for a cumulative duration of 60 hours
over the complete lifetime of the device (injection current does not need to be limited for this duration).
6
7
Internal structures will hold the voltage above –1.0 volt if the injection current limit of 1 mA is met.
Internal structures will not clamp to a safe voltage. External protection must be used to ensure that voltage on the pin stays
above –0.3 volts.
8
9
Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDEH supplies, if the maximum
injection current specification is met (1 mA for all pins) and VDDEH is within Operating Voltage specifications.
Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the maximum
injection current specification is met (1 mA for all pins) and VDDE is within Operating Voltage specifications.
10 Total injection current for all pins (including both digital and analog) must not exceed 25mA.
11 Total injection current for all analog input pins must not exceed 15mA.
12 Lifetime operation at these specification limits is not guaranteed.
13 Solder profile per CDF-AEC-Q100.
14 Moisture sensitivity per JEDEC test method A112.
3.2
Thermal Characteristics
Table 3. Thermal Characteristics
Value
Num
Characteristic
Junction to Ambient 1, 2
Natural Convection
(Single layer board)
Junction to Ambient 1, 3
Natural Convection
Symbol
Unit
208 MAPBGA 324 PBGA 416 PBGA
1
RθJA
°C/W
41
30
21
29
2
RθJA
°C/W
25
21
(Four layer board 2s2p)
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
5
Electrical Characteristics
Table 3. Thermal Characteristics (continued)
Value
Num
Characteristic
Symbol
Unit
208 MAPBGA 324 PBGA 416 PBGA
3
4
5
Junction to Ambient 1, 3
(@200 ft./min.,
Single layer board)
Junction to Ambient 1, 3
(@200 ft./min.,
Four layer board 2s2p)
Junction to Board 4
RθJMA
°C/W
33
22
15
24
17
12
23
18
13
RθJMA
°C/W
°C/W
RθJB
(Four layer board 2s2p)
6
7
Junction to Case 5
Junction to Package Top 6
Natural Convection
RθJC
°C/W
°C/W
7
2
8
2
9
2
ΨJT
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
3
4
Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5
6
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
3.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
× P )
D
J
A
θJA
where:
o
T = ambient temperature for the package ( C)
A
o
R
= junction to ambient thermal resistance ( C/W)
θJA
P = power dissipation in the package (W)
D
The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide
consistent values for estimations and comparisons. The difference between the values determined on the
single-layer (1s) board and on the four-layer board with two signal layers and a power and a ground plane
(2s2p) clearly demonstrate that the effective thermal resistance of the component is not a constant. It
depends on the construction of the application board (number of planes), the effective size of the board
which cools the component, how well the component is thermally and electrically connected to the planes,
and the power being dissipated by adjacent components.
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to
connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal
MPC5553 Microcontroller Data Sheet, Rev. 0
6
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
performance. When the clearance between through vias leave the planes virtually disconnected, the
thermal performance is also greatly reduced.
As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed
circuit board. The value obtained on the board with the internal planes is usually appropriate if the
application board has one oz (35 micron nominal thickness) internal planes, the components are well
2
separated, and the overall power dissipation on the board is less than 0.02 W/cm .
The thermal performance of any component depends strongly on the power dissipation of surrounding
components. In addition, the ambient temperature varies widely within the application. For many natural
convection and especially closed box applications, the board temperature at the perimeter (edge) of the
package is approximately the same as the local air temperature near the device. Specifying the local
ambient conditions explicitly as the board temperature provides a more precise description of the local
ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R
× P )
D
J
B
θJB
where:
o
T = junction temperature ( C)
J
o
T = board temperature at the package perimeter ( C/W)
B
o
R
= junction to board thermal resistance ( C/W) per JESD51-8
θJB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition, with the
component soldered to a board with internal planes.
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal
resistance and a case to ambient thermal resistance:
R
= R
+ R
θJA
θJC θCA
where:
o
R
R
R
= junction to ambient thermal resistance ( C/W)
θJA
θJC
θCA
o
= junction to case thermal resistance ( C/W)
o
= case to ambient thermal resistance ( C/W)
R
is device related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case to ambient thermal resistance, R
. For instance, the user can change the air flow around
θCA
the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the
thermal dissipation on the printed circuit board surrounding the device. This description is most useful for
packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient.
For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction to board thermal
resistance and the junction to case thermal resistance. The junction to case covers the situation where a
heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The
junction to board thermal resistance describes the thermal performance when most of the heat is conducted
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
7
Preliminary—Subject to Change Without Notice
Electrical Characteristics
to the printed circuit board. This model can be used for either hand estimations or for a computational fluid
dynamics (CFD) thermal model.
To determine the junction temperature of the device in the application after prototypes are available, the
Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T + (Ψ × P )
J
T
JT
D
where:
o
T = thermocouple temperature on top of the package ( C)
T
o
Ψ
= thermal characterization parameter ( C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
References:
Semiconductor Equipment and Materials International
805 East Middlefield Rd
Mountain View, CA 94043
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
•
•
•
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled
Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego,
1999, pp. 212–220.
3.3
Package
The MPC5553 is available in packaged form. Package options are listed in Section 2, “Ordering
Information.”
Refer to Section 4, “Mechanicals,” for pinouts and package drawings.
MPC5553 Microcontroller Data Sheet, Rev. 0
8
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
3.4
EMI (Electromagnetic Interference) Characteristics
1
Table 4. EMI Testing Specifications
Num
Characteristic
Min. Value
Typ. Value
Max. Value
Unit
1
2
3
4
5
6
Scan Range
0.15
—
—
—
1000
132
—
MHz
MHz
V
Operating Frequency
VDD Operating Voltages
—
1.5
3.3
5.0
—
VDDSYN, VRC33, VDD33, VFLASH, VDDE Operating Voltages
VPP, VDDEH, VDDA Operating Voltages
Maximum Amplitude
—
—
V
—
—
142
323
V
—
dBuV
7
Operating Temperature
—
—
25
oC
1
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing is performed on the MPC5554 and
applied to MPC5500 family as generic EMI performance data.
2
3
As measured with “single-chip” EMI program.
As measured with “expanded” EMI program.
3.5
ESD Characteristics
1, 2
Table 5. ESD Ratings
Characteristic
Symbol
Value
Unit
ESD for Human Body Model (HBM)
HBM Circuit Description
2000
1500
V
R1
C
Ohm
pF
100
ESD for Field Induced Charge Model (FDCM)
500 (all pins)
750 (corner pins)
V
Number of Pulses per pin:
Positive Pulses (HBM)
Negative Pulses (HBM)
—
—
1
1
—
—
Interval of Pulses
—
1
second
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room
temperature followed by hot temperature, unless specified otherwise in the device specification
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
9
Preliminary—Subject to Change Without Notice
Electrical Characteristics
3.6
VRC/POR Electrical Specifications
Table 6. VRC/POR Electrical Specifications
Num
Characteristic
Symbol
Min
Max
Units
1
2
3
4
5
6
7
1.5V (VDD) POR Negated (Ramp Up)
1.5V (VDD) POR Asserted (Ramp Down)
V_POR15
V_POR33
V_POR5
1.1
1.1
1.35
1.35
V
3.3V (VDDSYN) POR Negated (Ramp Up)
3.3V (VDDSYN) POR Asserted (Ramp Down)
2.0
2.0
2.85
2.85
V
V
V
V
V
RESET Pin Supply (VDDEH6) POR Negated (Ramp Up)
RESET Pin Supply (VDDEH6) POR Asserted (Ramp Down)
2.0
2.0
2.85
2.85
VRC33 voltage before regulator controller allows the pass transistor
to start turning on
V_TRANS_
START
1.0
2.0
3.0
2.0
2.85
—
VRC33 voltage when regulator controller allows the pass transistor
to completely turn on1, 2
V_TRANS_ON
V_VRC33REG
I_VRCCTL5
VRC33 voltage above which the regulator controller will keep the
1.5V supply in regulation3, 4
Current which can be sourced by VRCCTL
mA
mA
mA
mA
V
– 40C
25C
11.0
9.0
7.5
—
—
—
150C (Tj)
—
8
Voltage differential during power up that VDD33 can lag VDDSYN or
VDDEH6 before VDDSYN and VDDEH6 reach V_POR33 and
V_POR5 minimums respectively
VDD33_LAG
BETA7
1.0
9
Absolute value of Slew Rate on power supply pins
—
50
V/ms
10
Required Gain:
Idd / I_VRCCTL (@vdd = 1.35v, fsys = 132MHz)4, 6
– 40C
25C
55.08
58.08
70.08
—
—
—
—
—
150C (Tj)
500
1
2
3
4
User must be able to supply full operating current for the 1.5V supply when the 3.3V supply reaches this range.
Current limit may be reached during ramp up and should not be treated as short circuit current.
At peak current for device.
Assumes that the Freescale recommended board requirements and transistor recommendations are met. Board signal
traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass
transistor to the VDD package signals should have a maximum of 100 nH inductance and minimal resistance (<1 ohm).
VRCCTL should have a nominal 1µF phase compensation capacitor to ground. VDD should have a 20 µF (nominal) bulk
capacitor (> 4 µF over all conditions, including lifetime). High frequency bypass capacitors consisting of eight 0.01 µF, two 0.1
µF, and one 1 µF capacitors should be place around the package on the VDD supply signals.
5
6
7
I_VRCCTL measured at the following conditions: VDD=1.35V, VRC33=3.1V, V_VRCCTL=2.2V.
Values are based on IDD from high use applications as explained in the IDD Electrical Specification.
BETA is measured on a per part basis and is calculated as IDD / I_VRCCTL and represents the worst case external transistor
BETA.
8
Preliminary value. Final specification pending characterization.
MPC5553 Microcontroller Data Sheet, Rev. 0
10
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
3.7
Power Up/Down Sequencing
Power sequencing between the 1.5-V power supply and VDDSYN or the RESET power supplies is
required if the user provides an external 1.5-V power supply and ties VRC33 to ground. To avoid this
power sequencing requirement, power up VRC33 within the specified operating range, even if not using
the on-chip voltage regulator controller. Refer to Section 3.7.1, “Power Up Sequence (If VRC33
Grounded)” and Section 3.7.2, “Power Down Sequence (If VRC33 Grounded).”
Another power sequencing requirement is that VDD33 must be of sufficient voltage before POR negates,
so that the values on certain pins are treated as 1s when POR does negate. Refer to Section 3.7.3, “Input
Value of Pins During POR Dependent on VDD33.”
Although there is no power sequencing required between VRC33 and VDDSYN during power up, for the
VRC stage turn-on to operate within specification, VRC33 must not lead VDDSYN by more than 600 mV
or lag by more than 100 mV. Higher spikes in the emitter current of the pass transistor will occur if VRC33
leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on
the board power supply circuitry and the amount of board level capacitance.
Furthermore, when all of the PORs negate, the system clock will start to toggle, adding another large
increase of the current consumption from VRC33. If VRC33 lags VDDSYN by more than 100 mV, this
increased current consumption can drop VDD low enough to assert the 1.5-V POR again. Oscillations are
even possible because when the 1.5-V POR asserts, the system clock stops, causing the voltage on VDD
to rise until the 1.5-V POR negates again. Any oscillations stop when VRC33 is powered sufficiently.
When powering down, VRC33 and VDDSYN do not have a delta requirement to each other, because the
bypass capacitors internal and external to the device are already charged.
When not powering up or down, VRC33 and VDDSYN do not have a delta requirement to each other for
the VRC to operate within specification.
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive
current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Table 7
gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type), and Table 8 for all
pins with pad type pad_mh (medium type) and pad_sh (slow type).
Table 7. Power Sequence Pin States (Fast Pads)
pad_fc (Fast)
VDDE
VDD33
VDD
Output Driver
State
Comment
LOW
VDDE
VDDE
VDDE
X
X
Low
High
Functional I/O pins are clamped to VSS and VDDE
LOW
X
VDD33
VDD33
LOW
VDD
High Impedance
Functional
POR asserted.
No POR asserted
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
11
Electrical Characteristics
Table 8. Power Sequence Pin States (Medium and Slow Pads)
pad_mh/pad_sh
VDDEH
VDD
(Medium and Slow)
Output Driver
Comment
LOW
X
Low
Functional I/O pins are clamped to VSS and VDDEH
POR asserted
VDDEH
VDDEH
LOW
VDD
High Impedance
Functional
No POR asserted
3.7.1
Power Up Sequence (If VRC33 Grounded)
In this case, the 1.5-V VDD supply must rise to 1.35-V before the 3.3-V VDDSYN and the RESET power
supplies rises above 2.0 V. This ensures that digital logic in the PLL on the 1.5-V supply will not begin to
operate below the specified operation range lower limit of 1.35 V. Since the internal 1.5-V POR is disabled,
the internal 3.3-V POR or the RESET power POR must be depended on to hold the device in reset. Since
they may negate as low as 2.0 V, it is necessary for VDD to be within spec before the 3.3-V POR and the
RESET POR negate.
VDDSYN and RESET Power
VDD
2.0V
1.35V
VDD must reach 1.35V before VDDSYN and the RESET power reach 2.0V
Figure 2. Power Up Sequence if VRC33 Grounded
3.7.2
Power Down Sequence (If VRC33 Grounded)
In this case, the only requirement is that if VDD falls below its operating range, VDDSYN or the RESET
power must fall below 2.0 V before VDD is allowed to rise back into its operating range. This ensures that
digital 1.5-V logic that is only reset by ORed_POR, which may have been affected by the 1.5V supply
falling below spec, is reset properly.
3.7.3
Input Value of Pins During POR Dependent on VDD33
In order to avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not
treated as 1s when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6)
when powering the device by more than the VDD33 lag specification in Table 6. VDD33 individually can
lag either VDDSYN or the RESET pin power (VDDEH6) by more than the VDD33 lag specification.
VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33
lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag
requirements when powering down.
MPC5553 Microcontroller Data Sheet, Rev. 0
12
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
3.8
DC Electrical Specifications
Table 9. DC Electrical Specifications
Num
Characteristic
Symbol
Min
Max
Unit
1
2
3
4
5
6
8
9
Core Supply Voltage (average DC RMS voltage)
I/O Supply Voltage (Fast I/O)
I/O Supply Voltage (Slow/Medium I/O)
3.3V I/O Buffer Voltage
VDD
VDDE
1.35
1.62
3.0
3.0
3.0
4.5
4.5
3.0
0.8
3.0
1.65
3.6
V
V
V
V
V
V
V
V
V
V
V
VDDEH
VDD33
VRC33
VDDA
5.25
3.6
Voltage Regulator Control Input Voltage
Analog Supply Voltage1
3.6
5.25
5.25
3.6
Flash Programming Voltage2
Flash Read Voltage
VPP
VFLASH
VSTBY
VDDSYN
VIH_F
10 SRAM Standby Voltage3
1.2
11 Clock Synthesizer Operating Voltage
12 Fast I/O Input High Voltage
3.6
0.65 *
VDDE
VDDE + 0.3
13 Fast I/O Input Low Voltage
VIL_F
VIH_S
VIL_S
VSS – 0.3
0.35 *
VDDE
V
V
V
14 Medium/Slow I/O Input High Voltage
15 Medium/Slow I/O Input Low Voltage
0.65 *
VDDEH
VDDEH
0.3
+
VSS – 0.3
0.35 *
VDDEH
0.1 * VDDE
0.1 * VDDEH
16 Fast I/O Input Hysteresis
17 Medium/Slow I/O Input Hysteresis
18 Analog Input Voltage
VHYS_F
VHYS_S
VINDC
V
V
V
VSSA –
VDDA +
0.3
0.3
19 Fast I/O Output High Voltage (IOH_F = –2.0mA)
VOH_F
VOH_S
0.8 * VDDE
—
—
V
V
20 Slow/Medium I/O Output High Voltage (IOH_S = –2.0mA)
0.8 *
VDDEH
21 Fast I/O Output Low Voltage (IOL_F = 2.0mA)
VOL_F
VOL_S
—
—
0.2 * VDDE
V
V
22 Slow/Medium I/O Output Low Voltage (IOL_S = 2.0mA)
0.2 *
VDDEH
23 Load Capacitance (Fast I/O)4
DSC(SIU_PCR[8:9]) = 0b00
DSC(SIU_PCR[8:9]) = 0b01
DSC(SIU_PCR[8:9]) = 0b10
DSC(SIU_PCR[8:9]) = 0b11
CL
—
—
—
10
20
30
50
pF
pF
pF
pF
24 Input Capacitance (Digital Pins)
25 Input Capacitance (Analog Pins)
CIN
—
—
7
pF
pF
CIN_A
10
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
13
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Num
Table 9. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
26 Input Capacitance (Shared digital and analog pins AN12_MA0_SDS,
AN12_MA1_SDO, AN14_MA2_SDI, and AN15_FCK)
CIN_M
—
12
pF
27a Operating Current5 1.5V Supplies @ 132MHz:
VDD (including VDDF max current)6, 7 @1.65V Typical Use
VDD (including VDDF max current)6, 7 @1.35V Typical Use
VDD (including VDDF max current) 7, 8 @1.65V High Use
VDD (including VDDF max current)7, 8@1.35V High Use
IDD
IDD
IDD
IDD
—
—
—
—
5509
4509
6009
4909
mA
mA
mA
mA
27b Operating Current 51.5V Supplies @ 114MHz:
VDD (including VDDF max current)6, 7@1.65V Typical Use
VDD (including VDDF max current)6, 7@1.35V Typical Use
VDD (including VDDF max current)7, 8 @1.65V High Use
VDD (including VDDF max current)7, 8 @1.35V High Use
IDD
IDD
IDD
IDD
—
—
—
—
4609
3809
5209
4209
mA
mA
mA
mA
27c Operating Current5 1.5V Supplies @ 82MHz:
VDD (including VDDF max current)6, 7 @1.65V Typical Use
VDD (including VDDF max current)6, 7 @1.35V Typical Use
VDD (including VDDF max current)7, 8 @1.65V High Use
VDD (including VDDF max current)7, 8 @1.35V High Use
IDD
IDD
IDD
IDD
—
—
—
—
3509
2909
4009
3309
mA
mA
mA
mA
27d
IDDSTBY @ 25C
VSTBY @ 0.8V
VSTBY @ 1.0V
VSTBY @ 1.2V
IDDSTBY
IDDSTBY
IDDSTBY
—
—
—
20
30
50
µA
µA
µA
IDDSTBY @ 60C
VSTBY @ 0.8V
VSTBY @ 1.0V
VSTBY @ 1.2V
IDDSTBY
IDDSTBY
IDDSTBY
—
—
—
70
100
200
µA
µA
µA
IDDSTBY @ 150C (Tj)
VSTBY @ 0.8V
VSTBY @ 1.0V
VSTBY @ 1.2V
IDDSTBY
IDDSTBY
IDDSTBY
—
—
—
1200
1500
2000
µA
µA
µA
28 Operating Current 3.3V Supplies @ 132MHz:
VDD3310
IDD33
—
2 + values mA
derived
from
procedure
ofFootnote
10
VFLASH
VDDSYN
IVFLASH
IDDSYN
—
—
10
15
mA
mA
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
14
Freescale Semiconductor
Electrical Characteristics
Table 9. DC Electrical Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
29 Operating Current 5.0V Supplies @ 132MHz (12MHz ADCLK):
—
—
—
—
VDDA (VDDA0 + VDDA1)
Analog Reference Supply Current (VRH, VRL)
VPP
IDDA
IREF
IPP
20.0
1.0
25
mA
mA
mA
30 Operating Current VDDE11 Supplies:
VDDEH1
VDDE2
VDDE3
VDDEH4
VDDE5
VDDEH6
VDDE7
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
—
—
—
—
—
—
—
—
—
See
mA
mA
mA
mA
mA
mA
mA
mA
mA
Footnote
11
VDDEH8
VDDEH9
31 Fast I/O Weak Pull Up Current12
1.62V – 1.98V
IACT_F
10
20
20
110
130
170
µA
µA
µA
2.25V – 2.75V
3.0V – 3.6V
Fast I/O Weak Pull Down Current12
1.62V – 1.98V
10
20
20
100
130
170
µA
µA
µA
2.25V – 2.75V
3.0V – 3.6V
32 Slow/Medium I/O Weak Pull Up/Down Current13
IACT_S
3.0V – 3.6V
4.5V – 5.5V
10
20
150
170
µA
µA
33 I/O Input Leakage Current14
34 DC Injection Current (per pin)
35 Analog Input Current, Channel Off15
IINACT_D
IIC
IINACT_A
IINACT_AD
– 2.5
– 2.0
–150
– 2.5
2.5
2.0
150
2.5
µA
mA
nA
µA
35a Analog Input Current, Shared Analog/Digital pins
(AN12, AN13, AN14, AN15)
36 VSS Differential Voltage16
VSS – VSSA
VRL
– 100
100
mV
V
37 Analog Reference Low Voltage
VSSA –
0.1
VSSA +
0.1
38 VRL Differential Voltage
VRL – VSSA
VRH
–100
100
mV
V
39 Analog Reference High Voltage
VDDA –
0.1
VDDA +
0.1
40 VREF Differential Voltage
VRH – VRL
VSSSYN – VSS
VRCVSS – VSS
VDDF – VDD
4.5
–50
5.25
50
V
41 VSSSYN to VSS Differential Voltage
42 VRCVSS to VSS Differential Voltage
43 VDDF to VDD Differential Voltage2
mV
mV
mV
–50
50
–100
100
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
15
Electrical Characteristics
Num
Table 9. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
43a VRC33 to VDDSYN Differential Voltage
VRC33 – VDDSYN
VIDIFF
–0.1
– 2.5
0.117
2.5
V
V
44 Analog Input Differential Signal Range (with common mode 2.5V)
45 Operating Temperature Range — Ambient (Packaged)
TA
– 40.0
125.0
οC
(TL to TH)
46 Slew rate on power supply pins
—
—
50
V/ms
1
2
3
4
5
6
7
8
| VDDA0–VDDA1 | must be < 0.1V
VPP can drop to 3.0 volts during read operations.
During standby operation. If standby operation is not required, VSTBY can be connected to ground.
Applies to CLKOUT, external bus pins, and Nexus pins.
Maximum average RMS DC current.
Average current measured on Automotive benchmark.
Peak currents may be higher on specialized code.
High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache (0%
miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from
SRAM to SRAM. Higher currents could be seen if an “idle” loop that crosses cache lines is run from cache. Code should be
written to avoid this condition.
9
Preliminary. Final specification pending characterization.
10 Power requirements for the VDD33 supply are dependent on the frequency of operation and load of all I/O pins, and the
voltages on the I/O segments. See Table 11 for values to calculate power dissipation for specific operation.
11 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular
I/O segment, and the voltage of the I/O segment. See Table 10 for values to calculate power dissipation for specific operation.
The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.
12 Absolute value of current, measured at VIL and VIH.
13 Absolute value of current, measured at VIL and VIH.
14 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and
pad_mh.
15 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each
8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
16 VSSA refers to both VSSA0 and VSSA1. | VSSA0–VSSA1 | must be < 0.1V
17 Up to 0.6 volts during power up and power down.
3.8.1
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The
power consumption is the sum of all output pin currents for a particular segment. The output pin current
can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to
calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table 10.
MPC5553 Microcontroller Data Sheet, Rev. 0
16
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
1
Table 10. I/O Pad Average DC Current
Drive Select /
Slew Rate
Control
Frequency
(MHz)
Load2
(pF)
Num
Pad Type
Symbol
Voltage (V)
Current (mA)
1
Slow
IDRV_SH
25
10
2
50
50
50
200
50
50
50
200
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
5.25
5.25
5.25
5.25
5.25
5.25
5.25
5.25
3.6
11
01
00
00
11
01
00
00
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
8.0
3.2
0.7
2.4
17.3
6.5
1.1
3.9
2.8
5.2
8.5
11.0
1.6
2.9
4.2
6.7
2.4
4.4
7.2
9.3
1.3
2.5
3.5
5.7
1.7
3.1
5.1
6.6
1.0
1.8
2.5
4.0
2
3
4
2
5
Medium
Fast
IDRV_MH
50
20
3.33
3.33
66
66
66
66
66
66
66
66
56
56
56
56
56
56
56
56
40
40
40
40
40
40
40
40
6
7
8
9
IDRV_FC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3.6
3.6
3.6
1.98
1.98
1.98
1.98
3.6
3.6
3.6
3.6
1.98
1.98
1.98
1.98
3.6
3.6
3.6
3.6
1.98
1.98
1.98
1.98
1
2
These values are estimated from simulation and are not tested. Currents apply to output pins only.
All loads are lumped.
3.8.2
I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments.
The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The
output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on
all fast (pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage,
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
17
Preliminary—Subject to Change Without Notice
Electrical Characteristics
frequency, and load on all pad_sh and pad_sh pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table 11.
1
Table 11. VDD33 Pad Average DC Current
Frequency
(MHz)
Load2
(pF)
Drive
Select
Num
Pad Type
Symbol
VDD33 (V)
VDDE (V)
Current (mA)
Inputs
1
2
Slow
I33_SH
I33_MH
66
66
0.5
0.5
3.6
3.6
5.5
5.5
NA
NA
0.003
0.003
Medium
Outputs
3
Fast
I33_FC
66
66
66
66
66
66
66
66
56
56
56
56
56
56
56
56
40
40
40
40
40
40
40
40
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
10
20
30
50
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0.35
0.53
0.62
0.79
0.35
0.44
0.53
0.7
4
5
3.6
6
3.6
7
1.98
1.98
1.98
1.98
3.6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0.30
0.45
0.52
0.67
0.30
0.37
0.45
0.60
0.21
0.31
0.37
0.48
0.21
0.27
0.32
0.42
3.6
3.6
3.6
1.98
1.98
1.98
1.98
3.6
3.6
3.6
3.6
1.98
1.98
1.98
1.98
1
2
These values are estimated from simulation and not tested. Currents apply to output pins only for the fast pads and to input
pins only for the slow and medium pads.
All loads are lumped.
MPC5553 Microcontroller Data Sheet, Rev. 0
18
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
3.9
Oscillator & FMPLL Electrical Characteristics
Table 12. HiP7 FMPLL Electrical Specifications
(VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)
Min.
Value
Max.
Unit
Num
Characteristic
Symbol
Value
1
PLL Reference Frequency Range:
Crystal reference
MHz
fref_crystal
fref_ext
8
8
20
20
External reference
Dual Controller (1:1 mode)
fref_1:1
24
fsys/2
2
2
3
4
5
6
System Frequency 1
fsys
tCYC
fLOR
fSCM
fico(min) ÷ 2RFD
fMAX
MHz
ns
System Clock Period
—
100
7.4
1 / fsys
1000
17.5
Loss of Reference Frequency 3
Self Clocked Mode (SCM) Frequency 4
kHz
MHz
EXTAL Input High Voltage
Crystal Mode 5
VIHEXT
VIHEXT
Vxtal + 0.4v
—
—
V
V
All other modes (Dual Controller (1:1),
Bypass, External Reference)
((VDDE5/2) + 0.4v)
7
EXTAL Input Low Voltage
Crystal Mode 6
VILEXT
VILEXT
—
—
Vxtal – 0.4v
V
V
All other modes (Dual Controller (1:1),
Bypass, External Reference)
((VDDE5/2) – 0.4v)
8
9
XTAL Current 7
IXTAL
CS_XTAL
CS_EXTAL
CL
0.8
—
3
mA
pF
pF
pF
Total On-chip stray capacitance on XTAL
Total On-chip stray capacitance on EXTAL
1.5
1.5
10
11
—
Crystal manufacturer’s recommended
capacitive load
See crystal
specification
See crystal
specification
12
13
Discrete load capacitance to be connected
to EXTAL
CL_EXTAL
CL_XTAL
—
2*CL – CS_EXTAL
–
pF
pF
8
CPCB_EXTAL
Discrete load capacitance to be connected
to XTAL
—
2*CL – CS_XTAL
–
8
CPCB_XTAL
14
15
PLL Lock Time9
tlpll
—
750
2
µs
Dual Controller (1:1) Clock Skew (between
CLKOUT and EXTAL) 10, 11
tskew
–2
ns
16
17
18
19
Duty Cycle of reference
Frequency un-LOCK Range
Frequency LOCK Range
CLKOUT Period Jitter,12, 13
Measured at fSYS Max
Peak-to-peak Jitter
tdc
fUL
fLCK
Cjitter
40
60
4.0
2.0
%
– 4.0
– 2.0
% fsys
% fsys
% fclkout
—
—
5.0
.01
(Clock edge to clock edge)
Long Term Jitter
(Averaged over 2 ms interval)
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
19
Electrical Characteristics
Table 12. HiP7 FMPLL Electrical Specifications (continued)
(VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)
Min.
Max.
Value
Num
Characteristic
Symbol
Value
Unit
20
Frequency Modulation Range Limit 14
(fsysMax must not be exceeded)
Cmod
0.8
48
4
2.4
%fsys
21
ICO Frequency.
fico
fsys
MHz
f
ico=[fref*(MFD+4)]/(PREDIV+1)15
22
Predivider Output Frequency (to PLL)
fPREDIV
fMAX
MHz
1
2
3
4
All internal registers retain data at 0 Hz.
Up to the maximum frequency rating of the device (see Table 1).
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
Self clocked mode (SCM) frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR
This frequency is measured on the CLKOUT pin with the divider set to divide-by-2 of the system clock. NOTE: In SCM, the
MFD and PREDIV have no effect and the RFD is bypassed.
.
5
6
This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
Vextal – Vxtal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock.
This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
Vxtal – Vextal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock.
7
8
9
Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time will also include the crystal
startup time.
10 PLL is operating in 1:1 PLL mode.
11 VDDE = 3.0 to 3.6V
12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider set to divide-by-2.
.
13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of jitter + Cmod.
14 Modulation depth selected must not result in fsys value greater than the fsys maximum specified value.
15
f
= fico / (2RFD
)
sys
3.10 eQADC Electrical Characteristics
Table 13. eQADC Conversion Specifications (Operating)
Num
Characteristic
ADC Clock (ADCLK) Frequency1
Symbol
Min
Max
Unit
1
2
FADCLK
CC
1
12
MHz
Conversion Cycles
Differential
ADCLK
cycles
13+2 (or 15) 13+128 (or 141)
14+2 (or 16) 14+128 (or 142)
Single Ended
3
4
5
6
Stop Mode Recovery Time2
Resolution3
TSR
—
10
1.25
–4
—
—
4
µs
mV
Counts3
INL: 6 MHz ADC Clock
INL: 12 MHz ADC Clock
INL6
INL12
–8
8
Counts
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
20
Freescale Semiconductor
Electrical Characteristics
Table 13. eQADC Conversion Specifications (Operating) (continued)
Num
Characteristic
DNL: 6 MHz ADC Clock
Symbol
Min
Max
Unit
7
8
9
DNL6
DNL12
OFFWC
GAINWC
IINJ
–3 4
–6 4
–4 5
–8 6
–1
3 4
64
4 5
8 6
1
Counts
Counts
Counts
Counts
mA
DNL: 12 MHz ADC Clock
Offset Error with Calibration
10 Full Scale Gain Error with Calibration
11 Disruptive Input Injection Current 7, 8, 9, 10
12 Incremental Error due to injection current. All channels have
same 10kΩ < Rs <100kΩ
EINJ
–4
4
Counts
Channel under test has Rs=10kΩ,
IINJ=IINJMAX INJMIN
,I
13 Total Unadjusted Error for single ended conversions with
calibration11, 12, 13, 14, 15
TUE
–4
4
Counts
1
2
Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The
maximum value is based on 800KS/s and the minimum value is based on 20MHz oscillator clock frequency divided by a
maximum 16 factor.
Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that
the ADC is ready to perform conversions.
3
4
5
6
7
At VRH – VRL = 5.12 V, one lsb = 1.25 mV = one count
Guaranteed 10-bit monotonicity
The absolute value of the offset error without calibration ≤ 100 counts.
The absolute value of the full scale gain error without calibration ≤ 120 counts.
Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than
VRH and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
8
9
Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do
not affect device reliability or cause permanent damage.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP = VDDA + 0.5V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.
10 Condition applies to two adjacent pads on the internal pad.
11 The TUE specification will always be better than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
12 TUE does not apply to differential conversions.
13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.
14 TUE includes all internal device error such as internal reference variation (75% Ref, 25% Ref)
15 Depending on the customer input impedance, the Analog Input Leakage current (DC Electrical specification 35a) may affect
the actual TUE measured on analog channels AN12, AN13, AN14, AN15.
3.11 H7Fa Flash Memory Electrical Characteristics
1
Table 14. Flash Program and Erase Specifications
Initial
Num
Characteristic
Symbol
Min
Typ
Max3 Unit
Max2
3
4
7
9
Double Word (64 bits) Program Time4
Page Program Time4
Tdwprogram
Tpprogram
T16kpperase
T48kpperase
—
—
—
—
10
22
—
500
500
µs
µs
445
400
400
16 Kbyte Block Pre-program and Erase Time
48 Kbyte Block Pre-program and Erase Time
265
340
5000
5000
ms
ms
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
21
Electrical Characteristics
Num
1
Table 14. Flash Program and Erase Specifications (continued)
Initial
Max2
Characteristic
Symbol
Min
Typ
Max3 Unit
10
8
64 Kbyte Block Pre-program and Erase Time
128 Kbyte Block Pre-program and Erase Time
T64kpperase
T128kpperase
—
—
—
25
400
500
—
500
1250
—
5000
15,000 ms
MHz
ms
11
Minimum operating frequency for program and erase
operations6
—
1
2
3
Typical program and erase times assume nominal supply values and operation at 25 oC.
Initial factory condition: ≤ 100 program/erase cycles, 25 oC, typical supply voltage, 80MHz minimum system frequency.
The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized
but not guaranteed.
4
5
6
Actual hardware programming times. This does not include software overhead.
Page size is 256 bits (8 words).
Read frequency of the flash can be up to the maximum operating frequency of the device. There is no minimum read frequency
condition.
Table 15. Flash EEPROM Module Life (Full Temperature Range)
Num
Characteristic
Symbol
Min
Typical1 Unit
cycles
1a
Number of Program/Erase cycles per block for 16 Kbyte, 48 Kbyte, and 64
Kbyte blocks over the operating temperature range (TJ)
P/E
100,000
—
1b
2
Number of Program/Erase cycles per block for 128 Kbyte blocks over the
operating temperature range (TJ)
P/E
10,000 100,000 cycles
Data retention
Retention
—
years
Blocks with 0 – 1,000 P/E cycles
Blocks with 1,001 – 100,000 P/E cycles
20
5
1
Typical endurance is evaluated at 25C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619 “Typical Endurance
for Nonvolatile Memory.”
Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device Reference
Manual for definitions of these bit-fields.
Table 16. FLASH_BIU Settings vs. Frequency of Operation
Maximum Frequency (MHz)
APC
RWSC
WWSC
DPFEN
IPFEN
PFLIM
BFEN
up to and including 82 MHz1
0b001
0b001
0b01
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b000- 0b0, 0b14
0b1103
up to and including 102 MHz5
up to and including132 MHz6
Default Setting after Reset
0b001
0b010
0b111
0b010
0b011
0b111
0b01
0b01
0b11
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b000- 0b0, 0b14
0b1103
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b000- 0b0, 0b14
0b1103
0b00
0b00
0b000
0b0
1
This setting allows for 80 MHz system clock with 2% frequency modulation.
MPC5553 Microcontroller Data Sheet, Rev. 0
22
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
2
3
4
5
6
For maximum flash performance, this should be set to 0b11.
For maximum flash performance, this should be set to 0b110.
For maximum flash performance, this should be set to 0b1.
This setting allows for 100 MHz system clock with 2% frequency modulation.
This setting allows for 128 MHz system clock with 2% frequency modulation.
3.12 AC Specifications
3.12.1 Pad AC Specifications
1
Table 17. Pad AC Specifications (VDDEH = 5.0V, VDDE = 1.8V)
Out Delay2, 3, 4
(ns)
Rise/Fall4, 5
(ns)
Load Drive
(pF)
Num
Pad
SRC/DSC
1
Slow High Voltage (SH)
11
26
82
15
60
50
200
50
01
00
11
01
00
75
40
137
377
476
16
80
200
50
200
260
8
200
50
2
Medium High Voltage (MH)
43
30
200
50
34
15
61
35
200
50
192
239
3.1
100
125
2.7
2.5
2.4
2.3
7500
9000
200
10
3
Fast
00
01
10
11
—
—
20
30
50
4
5
Pull Up/Down (3.6V max)
Pull Up/Down (5.5V max)
—
—
50
50
1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDE = 1.62V to 1.98V, VDDEH = 4.5V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH.
2
3
4
5
This parameter is supplied for reference and is not guaranteed by design and not tested.
Out delay is shown in Figure 3. Add a maximum of one system clock to the output delay for delay with respect to system clock.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
23
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Table 18. De-rated Pad AC Specifications (VDDEH = 3.3V, VDDE = 3.3V)
1
Out Delay2, 3, 4
(ns)
Rise/Fall3, 5
(ns)
Load Drive
(pF)
Num
Pad
SRC/DSC
1
2
3
Slow High Voltage (SH)
Medium High Voltage (MH)
Fast
11
39
120
101
188
507
597
23
23
87
50
200
50
01
00
11
01
00
52
111
248
312
12
200
50
200
50
64
44
200
50
50
22
90
50
200
50
261
305
3.2
123
156
2.4
2.2
2.1
2.1
7500
9500
200
10
00
01
10
11
—
—
20
30
50
4
5
Pull Up/Down (3.6V max)
Pull Up/Down (5.5V max)
—
—
50
50
1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDE = 3.0V to 3.6V, VDDEH = 3.0V to 3.6V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH.
2
3
4
5
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
Out delay is shown in Figure 3. Add a maximum of one system clock to the output delay for delay with respect to system clock.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
MPC5553 Microcontroller Data Sheet, Rev. 0
24
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
VDD/2
Pad
Internal Data Input Signal
Rising
Edge
Out
Falling
Edge
Out
Delay
Delay
VOH
Pad
Output
VOL
Figure 3. Pad Output Delay
3.13 AC Timing
3.13.1 Reset and Configuration Pin Timing
1
Table 19. Reset and Configuration Pin Timing
Num
Characteristic
Symbol
Min
Max
Unit
1
2
3
4
RESET Pulse Width
tRPW
tGPW
tRCSU
tRCH
10
2
—
—
—
—
tCYC
tCYC
tCYC
tCYC
RESET Glitch Detect Pulse Width
PLLCFG, BOOTCFG, WKPCFG, RSTCFG Setup Time to RSTOUT Valid
PLLCFG, BOOTCFG, WKPCFG, RSTCFG Hold Time from RSTOUT Valid
10
0
1
Reset timing specified at FSYS = 132MHz, VDDEH = 3.0V to 5.25V, VDD = 1.35V to 1.65V, TA = TL to TH.
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
25
Preliminary—Subject to Change Without Notice
Electrical Characteristics
2
RESET
1
RSTOUT
3
PLLCFG
BOOTCFG
RSTCFG
WKPCFG
4
Figure 4. Reset and Configuration Pin Timing
3.13.2 IEEE 1149.1 Interface Timing
1
Table 20. JTAG Pin AC Electrical Characteristics
Num
Characteristic
Symbol
Min
Max
Unit
1
2
3
4
5
6
7
8
9
TCK Cycle Time
tJCYC
tJDC
tTCKRISE
TMSS, tTDIS
tTMSH, TDIH
tTDOV
tTDOI
100
40
—
5
—
60
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK Clock Pulse Width (Measured at VDDE/2)
TCK Rise and Fall Times (40% – 70%)
TMS, TDI Data Setup Time
t
—
—
20
—
20
—
—
50
50
50
—
—
TMS, TDI Data Hold Time
t
25
—
0
TCK Low to TDO Data Valid
TCK Low to TDO Data Invalid
TCK Low to TDO High Impedance
JCOMP Assertion Time
tTDOHZ
tJCMPPW
tJCMPS
tBSDV
—
100
40
—
—
—
50
50
10 JCOMP Setup Time to TCK Low
11 TCK Falling Edge to Output Valid
12 TCK Falling Edge to Output Valid out of High Impedance
13 TCK Falling Edge to Output High Impedance
14 Boundary Scan Input Valid to TCK Rising Edge
15 TCK Rising Edge to Boundary Scan Input Invalid
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
1
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 1.35V to 1.65V, VDDE = 3.0V to 3.6V,
VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10, SRC = 0b11. See Table 21 for functional
specifications.
MPC5553 Microcontroller Data Sheet, Rev. 0
26
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
TCK
2
3
3
2
1
Figure 5. JTAG Test Clock Input Timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 6. JTAG Test Access Port Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
27
Electrical Characteristics
TCK
10
JCOMP
9
Figure 7. JTAG JCOMP Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
28
Freescale Semiconductor
Electrical Characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 8. JTAG Boundary Scan Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
29
Electrical Characteristics
3.13.3 Nexus Timing
1
Table 21. Nexus Debug Port Timing
Num
Characteristic
Symbol
Min
Max
Unit
1
2
3
4
5
6
7
8
9
MCKO Cycle Time
tMCYC
tMDC
12
40
8
tCYC
%
MCKO Duty Cycle
60
3.0
3.0
3.0
—
MCKO Low to MDO Data Valid3
MCKO Low to MSEO Data Valid3
MCKO Low to EVTO Data Valid3
EVTI Pulse Width
tMDOV
–1.5
–1.5
–1.5
4.0
1
ns
tMSEOV
tEVTOV
ns
ns
tEVTIPW
tEVTOPW
tTCYC
tTCYC
tMCYC
tCYC
%
EVTO Pulse Width
TCK Cycle Time
44
—
60
—
—
TCK Duty Cycle
tTDC
40
10 TDI, TMS Data Setup Time
11 TDI, TMS Data Hold Time
12 TCK Low to TDO Data Valid
VDDE = 2.25 to 3.0 volts
t
NTDIS, tNTMSS
8
ns
t
NTDIH, tNTMSH
5
ns
tJOV
0
0
12
9
ns
ns
—
VDDE = 3.0 to 3.6 volts
13 RDY Valid to MCKO5
—
—
—
1
2
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from
50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.35V to 1.65V, VDDE = 2.25V to 3.6V,
VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10.
The Nexus AUX port can only run up to 82MHz. The NPC_PCR[MCKO_DIV] must be set to divide by 2 if the system frequency
is above 82MHz
3
4
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
The maximum frequency must be limited to approximately 16 MHz (VDDE= 2.25 to 3.0 volts) or 22 MHz (VDDE= 3.0 to 3.6
volts) to meet the timing specification for tJOV of 0.2 x tJCYC as outlined in the IEEE-ISTO 5001-2003 specification.
5
The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.
1
2
MCKO
4
5
3
MDO
MSEO
EVTO
Output Data Valid
Figure 9. Nexus Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
30
Freescale Semiconductor
Electrical Characteristics
TCK
10
11
TMS, TDI
12
TDO
Figure 10. Nexus TDI, TMS, TDO Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
31
Electrical Characteristics
3.13.4 External Bus Interface (EBI) Timing
1
Table 22. Bus Operation Timing
40 MHz
56 MHz
66 MHz
(ext. bus)2
(ext. bus)2
(ext. bus)2
#
Characteristic/Description Symbol
Unit
Notes
Min
Max
Min
Max
Min
Max
1
CLKOUT Period
TC
25.0
—
17.9
—
15.2
—
ns Signals are
measured at 50%
VDDE.
2
3
4
5
CLKOUT duty cycle
CLKOUT rise time
CLKOUT fall time
tCDC
tCRT
tCFT
tCOH
45%
—
55%
45%
—
55%
45%
—
55%
TC
ns
ns
3
3
3
—
—
—
3
3
3
—
1.06/
1.5
—
—
1.06/
1.5
—
—
1.06/
1.5
—
CLKOUT Positive Edge to
Output Signal Invalid or High
Z (Hold Time)
—
—
—
ns Hold time
selectable via
SIU_ECCR[EBTS]
bit:
ADDR[8:31]
BDIP
EBTS=0/EBTS=1
BG4
BR5
CS[0:3]
DATA[0:31]
OE
RD_WR
TA
TEA
TS
TSIZ[0:1]
WE[0:3]/BE[0:3]
6
CLKOUT Posedge to Output
Signal Valid (Output Delay)
tCOV
—
10.06/
11.0
—
7.56/
8.5
—
6.06/
7.0
ns Output valid time
selectable via
SIU_ECCR[EBTS]
bit:
ADDR[8:31]
BDIP
EBTS=0/EBTS=1
BG4
BR5
CS[0:3]
DATA[0:31]
OE
RD_WR
TA
TEA
TS
TSIZ[0:1]
WE[0:3]/BE[0:3]
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
32
Freescale Semiconductor
Electrical Characteristics
1
Table 22. Bus Operation Timing (continued)
40 MHz
56 MHz
66 MHz
(ext. bus)2
(ext. bus)2
(ext. bus)2
#
Characteristic/Description Symbol
Unit
Notes
Min
Max
Min
Max
Min
Max
7
Input Signal Valid to CLKOUT
Posedge (Setup Time)
tCIS
10.0
—
7.0
—
5.0
—
ns
ADDR[8:31]
BB
BG5
BR5
DATA[0:31]
RD_WR
TA
TEA
TS
TSIZ[0:1]
8
CLKOUT Posedge to Input
Signal Invalid
tCIH
1.0
—
1.0
—
1.0
—
ns
(Hold Time)
ADDR[8:31]
BB
BG5
BR5
DATA[0:31]
RD_WR
TA
TEA
TS
TSIZ[0:1]
1
EBI timing specified at VDD = 1.35V to 1.65V, VDDE = 1.6V to 3.6V (unless stated otherwise), VDD33 and VDDSYN = 3.0V
to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10.
2
3
4
5
6
The external bus is limited to half the speed of the internal bus.
Refer to Fast Pad timing in Table 17 and Table 18 (different values for 1.8V vs 3.3V).
Internal Arbitration
External Arbitration
The EBTS=0 timings are only valid/ tested at VDDE=2.25-3.6V, whereas EBTS=1 timings are valid/tested at 1.6–3.6V.
Voh_f
VDDE/2
Vol_f
CLKOUT
2
3
2
4
1
Figure 11. CLKOUT Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
33
Preliminary—Subject to Change Without Notice
Electrical Characteristics
VDDE/2
CLKOUT
6
5
VDDE/2
5
OUTPUT
BUS
VDDE/2
6
5
5
OUTPUT
SIGNAL
VDDE/2
6
OUTPUT
SIGNAL
VDDE/2
Figure 12. Synchronous Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
34
Freescale Semiconductor
Electrical Characteristics
CLKOUT
VDDE/2
7
8
INPUT
BUS
VDDE/2
7
8
INPUT
SIGNAL
VDDE/2
Figure 13. Synchronous Input Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
35
Electrical Characteristics
3.13.5 External Interrupt Timing (IRQ Pin)
1
Table 23. External Interrupt Timing
Num
Characteristic
Symbol
Min
Max
Unit
1
2
3
IRQ Pulse Width Low
IRQ Pulse Width High
IRQ Edge to Edge Time2
tIPWL
TIPWH
tICYC
3
3
6
—
—
—
tCYC
tCYC
tCYC
1
2
IRQ timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH, and CL = 200pF with SRC = 0b11.
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
IRQ
2
1
3
Figure 14. External Interrupt Timing
CLKOUT
4
IRQ
Figure 15. External Interrupt Setup Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
36
Freescale Semiconductor
Electrical Characteristics
3.13.6 eTPU Timing
1
Table 24. eTPU Timing
Characteristic
eTPU Input Channel Pulse Width
eTPU Output Channel Pulse Width
Num
Symbol
Min
Max
Unit
1
2
tICPW
4
2
—
—
tCYC
tCYC
tOCPW
1
eTPU timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH, and CL = 200pF with SRC = 0b11.
2
eTPU
OUTPUT
eTPU INPUT
AND TCRCLK
1
Figure 16. eTPU Timing
CLKOUT
4
eTPU
OUTPUT
3
eTPU INPUT
AND TCRCLK
Figure 17. eTPU Input/Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
37
Preliminary—Subject to Change Without Notice
Electrical Characteristics
3.13.7 eMIOS (MTS) Timing
1
Table 25. MTS Timing
Num
Characteristic
Symbol
Min
Max
Unit
1
2
eMIOS (MTS) Input Pulse Width
eMIOS (MTS) Output Pulse Width
tMIPW
4
1
—
—
tCYC
tCYC
tMOPW
1
MTS timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH, and CL = 50pF with SRC = 0b11.
3.13.8 DSPI Timing
1
Table 26. DSPI Timing
80 MHz
Symbol
112 MHz
132 MHz
Num
Characteristic
SCK Cycle TIme2,3
PCS to SCK Delay4
After SCK Delay5
SCK Duty Cycle
Unit
Min
Max
Min
Max
Min
Max
1
2
3
4
tSCK
tCSC
tASC
tSDC
25ns
23
2.9ms 17.9ns 2.0ms
15.2ns
13
1.7ms
—
—
ns
ns
ns
—
—
15
14
—
—
—
—
22
12
—
tSCK/2
–2ns
tSCK/2
+ 2ns
—
—
5
6
Slave Access Time
(SS active to SOUT driven)
tA
—
25
—
—
25
25
—
—
25
25
ns
ns
Slave SOUT Disable Time
(SS inactive to SOUT High-Z or
invalid)
tDIS
—
25
7
8
9
PCSx to PCSS time
PCSS to PCSx time
tPCSC
tPASC
tSUI
4
5
—
—
4
5
—
—
4
5
—
—
ns
ns
Data Setup Time for Inputs
Master (MTFE = 0)
20
2
–4
20
—
—
—
—
20
2
3
—
—
—
—
20
2
6
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
20
20
10
Data Hold Time for Inputs
Master (MTFE = 0)
tHI
–4
7
21
–4
—
—
—
—
–4
7
14
–4
—
—
—
—
–4
7
12
–4
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
38
Freescale Semiconductor
Electrical Characteristics
1
Table 26. DSPI Timing (continued)
80 MHz
112 MHz
132 MHz
Unit
Num
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
11
Data Valid (after SCK edge)
Master (MTFE = 0)
tSUO
—
—
—
—
5
25
18
5
—
—
—
—
5
25
14
5
—
—
—
—
5
25
13
5
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
12
Data Hold Time for Outputs
Master (MTFE = 0)
tHO
–5
5.5
8
—
—
—
—
–5
5.5
4
—
—
—
—
–5
5.5
3
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–5
–5
–5
1
2
DSPI timing specified at VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH,
and CL = 50pF with SRC = 0b11.
The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two MPC55xx devices communicating over a DSPI link.
3
4
5
6
The actual minimum SCK Cycle Time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
39
Electrical Characteristics
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Figure 19. DSPI Classic SPI Timing — Master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
9
10
Data
Last Data
First Data
SIN
Figure 20. DSPI Classic SPI Timing — Slave, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
40
Freescale Semiconductor
Electrical Characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Figure 21. DSPI Classic SPI Timing — Slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
Last Data
Last Data
Data
12
11
SOUT
First Data
Data
Figure 22. DSPI Modified Transfer Format Timing — Master, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
41
Electrical Characteristics
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Figure 23. DSPI Modified Transfer Format Timing — Master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Figure 24. DSPI Modified Transfer Format Timing — Slave, CPHA =0
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
42
Freescale Semiconductor
Electrical Characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Figure 25. DSPI Modified Transfer Format Timing — Slave, CPHA =1
8
7
PCSS
PCSx
Figure 26. DSPI PCS Strobe (PCSS) Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
43
Electrical Characteristics
3.13.9 eQADC SSI Timing
1
Table 27. EQADC SSI Timing Characteristics (pads at 3.3V or at 5.0V)
CLOAD = 25pF on all outputs. Pad drive strength set to maximum.
Num
Rating
FCK Frequency 2, 3
Symbol
Min
Typ
Max
Unit
1
2
3
4
5
6
7
8
fFCK
tFCK
1/17
—
—
—
—
—
—
—
—
1/2
fSYS_CLK
tSYS_CLK
ns
FCK Period (tFCK = 1/ fFCK
Clock (FCK) High Time
Clock (FCK) Low Time
SDS Lead/Lag Time
)
2
17
tFCKHT
tFCKLT
tSDS_LL
tSDO_LL
tSYS_CLK − 6.5
9* tSYS_CLK + 6.5
tSYS_CLK − 6.5
8* tSYS_CLK + 6.5
ns
–7.5
–7.5
22
+7.5
+7.5
—
ns
SDO Lead/Lag Time
ns
EQADC Data Setup Time (Inputs)
EQADC Data Hold Time (Inputs)
tEQ SU
ns
_
tEQ_HO
1
—
ns
1
SS timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH, and CL = 50pF with SRC = 0b11.
2
3
Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.
FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
2
3
4
FCK
SDS
5
6
4
5
25th
1st (MSB)
2nd
26th
SDO
External Device Data Sample at
FCK Falling Edge
8
7
1st (MSB) 2nd
25th
26th
SDI
EQADC Data Sample at
FCK Rising Edge
Figure 27. EQADC SSI Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
44
Freescale Semiconductor
Electrical Characteristics
3.14 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at 3.3 V. Note that the timing
specifications for the MII signals are independent of system clock frequency (part speed designation).
3.14.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed 4× the RX_CLK
frequency.
Table 28 lists MII receive channel timings.
Table 28. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
1
2
3
4
RXD[3:0], RX_DV, RX_ER to RX_CLK setup
RX_CLK to RXD[3:0], RX_DV, RX_ER hold
RX_CLK pulse width high
5
—
—
ns
5
ns
35%
35%
65%
65%
RX_CLK period
RX_CLK period
RX_CLK pulse width low
Figure 28 shows MII receive signal timings listed in Table 28.
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
M2
Figure 28. MII Receive Signal Timing Diagram
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
45
Electrical Characteristics
3.14.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising
or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of
non-compliant MII PHYs.
Refer to the ethernet chapter of the device Reference Manual for details of this option and how to enable it.
Table 29 lists MII transmit channel timings.
Table 29. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
5
6
7
8
TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
TX_CLK to TXD[3:0], TX_EN, TX_ER valid
TX_CLK pulse width high
5
—
ns
—
25
ns
35%
35%
65%
65%
TX_CLK period
TX_CLK period
TX_CLK pulse width low
Figure 29 shows MII transmit signal timings listed in Table 29.
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
Figure 29. MII Transmit Signal Timing Diagram
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
46
Freescale Semiconductor
Electrical Characteristics
3.14.3 MII Async Inputs Signal Timing (CRS and COL)
Table 30 lists MII asynchronous inputs signal timing.
Table 30. MII Async Inputs Signal Timing
Num
Characteristic
CRS, COL minimum pulse width
Min
Max
Unit
9
1.5
—
TX_CLK period
Figure 30 shows MII asynchronous input timings listed in Table 30.
CRS, COL
M9
Figure 30. MII Async Inputs Timing Diagram
3.14.4 MII Serial Management Channel Timing (MDIO and MDC)
Table 31 lists MII serial management channel timings. The FEC functions correctly with a maximum
MDC frequency of 2.5 MHz.
Table 31. MII Serial Management Channel Timing
Num
Characteristic
Min Max
Unit
10
11
12
13
14
15
MDC falling edge to MDIO output invalid (minimum propagation delay)
MDC falling edge to MDIO output valid (max prop delay)
MDIO (input) to MDC rising edge setup
MDIO (input) to MDC rising edge hold
MDC pulse width high
0
—
10
0
—
25
—
—
ns
ns
ns
ns
40% 60% MDC period
40% 60% MDC period
MDC pulse width low
Figure 31 shows MII serial management channel timings listed in Table 31.
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
47
Preliminary—Subject to Change Without Notice
Electrical Characteristics
M14
M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
Figure 31. MII Serial Management Channel Timing Diagram
M13
CLKOUT
RESET
5
5
6
6
RSTOUT
Figure 32. Reset and Configuration Pin Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
48
Freescale Semiconductor
Mechanicals
4
Mechanicals
Pinouts
4.1
4.1.1
MPC5553 416 PBGA Pinout
Figure 33, Figure 34, and Figure 35 show the pinout for the MPC5553 416 PBGA package. While the
MPC5553 and the MPC5554/MPC5565/MPC5566 are pin-compatible, the MPC5553 ball map is shown
here to highlight the balls that are not connected to any signal on the MCP5553 (the eTPUB[0:31] and
TSIZ[0:1]). The alternate Ethernet signals that are multiplexed with the data bus are not shown for the
MPC5553.
NOTE
Some pins have names that include functions that are not available on all
family members. For example, ball R25 of the 416 BGA package is named
‘SINA,’ but the MPC5553 does not have a DSPI_A module. In this case, the
SINA pin can only be used for its alternate functions of GPIO94 or PCSC2.
See the specific device reference manual for functions available on each
device in the family.
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
49
Preliminary—Subject to Change Without Notice
Mechanicals
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ETRIG
1
GPIO
205
AN1
AN5
VRH
AN23 AN27 AN28 AN35 VSSA0 AN15
AN22 AN26 AN31 AN32 VSSA0 AN14
NC_1 NC_2 NC_3 NC_4
MDO11 MDO8 VDD VDD33 VSS
A
B
VSS VSTBY AN37 AN11 VDDA1 AN16
VDD VSS AN36 AN39 AN19 AN20
A
REF
BYPC
ETRIG
0
AN0
AN4
AN3
NC_5 NC_6 NC_7 NC_8 MDO10 MDO7 MDO4 MDO0 VSS VDDE7
B
AN21
AN7
AN2
VRL
AN6
AN25 AN30 AN33 VDDA0 AN13 NC_9 NC_10 NC_11 NC_12 MDO9 MDO6 MDO3 MDO1 VSS VDDE7 VDD
C
D
E
VDD33 VDD
ETPUA ETPUA
VSS
VDD
AN8
VSS
VDD
AN17 VSSA1
AN38 AN9
C
VDDEH
9
VDDEH
8
AN10 AN18
AN24 AN29 AN34
AN12 NC_13 NC_14 NC_15 NC_16 MDO5 MDO2
VSS VDDE7 TCK
VDDE7 TMS TDO
TDI
D
30
31
ETPUA ETPUA VDDEH
28 29
TEST
E
1
ETPUA ETPUA ETPUA VDDEH
MSEO0 JCOMP EVTI EVTO
GPIO
F
F
24
27
26
1
ETPUA ETPUA ETPUA ETPUA
MSEO1 MCKO
NC_17
G
H
J
G
H
23
22
25
21
204
ETPUA ETPUA ETPUA ETPUA
20 19 18 17
GPIO
RDY
Version 2.1 – 13 July 2004
NC_18 NC_19
203
ETPUA ETPUA ETPUA ETPUA
16 15 14 13
VDDEH
6
NC_20 NC_21 NC_22
J
ETPUA ETPUA ETPUA ETPUA
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDE7 VDDE7 VDDE7 VDDE7
NC_23 NC_24 NC_25 NC_26
NC_27 NC_28 NC_29 NC_30
NC_31 NC_32 NC_33 SINB
SOUTB PCSB3 PCSB0 PCSB1
PCSA3 PCSB4 SCKB PCSB2
PCSB5 SOUTA SINA SCKA
PCSA1 PCSA0 PCSA2 VPP
PCSA4 TXDA PCSA5 VFLASH
K
K
12
11
10
9
ETPUA ETPUA ETPUA ETPUA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDE7
VSS VDDE7
VSS VDDE7
L
L
8
7
6
5
ETPUA ETPUA ETPUA ETPUA
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
M
N
P
M
N
4
3
2
1
ETPUA TCRCLK
BDIP
TEA
0
A
VSS
VSS
VSS
VSS
VSS
VSS
CS3
CS2
CS1
CS0
P
R
T
WE3
WE2
WE1
WE0
R
VDDE2 VSS VDDE2 VDDE2 VDDE2 VDDE2 VSS
VSS VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS
VDDE2 NC_34 RD_WR VDDE2
ADDR
T
U
V
NC_35
TA
VDD33
U
16
ADDR ADDR
18 17
ADDR
8
RST
CNTXC RXDA RSTOUT
CFG
TS
V
ADDR ADDR ADDR ADDR
RXDB CNRXC TXDB RESET
W
Y
W
Y
20
19
9
10
NC_X
Note:
No connects (x = 1 to 38)
ADDR ADDR ADDR
WKP BOOT VRC
VSS
SYN
VDDE2
22
21
11
CFG
CFG1
VSS
NC_36 NC_37
No connect. AC22 & AD23 reserved
ADDR ADDR ADDR ADDR
VDDEH PLL
BOOT
EXTAL
XTAL
AA
AA
AB
AC
AD
AE
AF
24
23
13
12
6
CFG1 CFG0
ADDR ADDR ADDR
VRC
CTL
PLL
CFG0
VDD
AB VDDE2
25
15
14
ADDR ADDR ADDR
DATA DATA
26 28
DATA DATA DATA DATA
DATA DATA EMIOS EMIOS EMIOS EMIOS VDDEH
VDDE2
VDD
SYN
VDDE2
VDDE5 NC_36 VSS
VDD VRC33
AC
AD
AE
VSS
VDD
26
27
31
30
31
8
10
12
14
2
8
12
21
4
ADDR ADDR
DATA DATA DATA DATA
24 25 27 29
GPIO DATA DATA DATA DATA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
VDD33
CNTXA VDDE5 NC_37 VSS
VDD VDD33
VSS
VDD
28
30
207
9
11
13
15
3
6
10
15
17
22
ADDR
29
DATA DATA DATA DATA DATA DATA DATA DATA
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
CNRXA VDDE5 CLKOUT VSS
OE
BR
BG
VDD
VSS
VDD
17
19
VDDE2
5
21
23
0
2
4
6
VDDE2
11
1
5
9
13
16
19
23
DATA DATA
DATA DATA GPIO DATA DATA
DATA DATA
5
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
ENG
CLK
NC_38
14
CNTXB CNRXB VDDE5
22 23 24
VSS
26
AF VSS
1
VDD
2
16
18
20
22
206
1
3
7
0
4
7
11
14
18
20
3
4
6
7
8
9
10
12
13
15
16
17
18
19
20
21
25
Figure 33. MPC5553 416 Package
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
50
Freescale Semiconductor
Mechanicals
1
2
3
4
5
6
7
8
9
10
11
12
13
AN1
AN5
VRH
AN23 AN27 AN28
AN35
A
B
VSS VSTBY AN37 AN11 VDDA1 AN16
VDD VSS AN36 AN39 AN19 AN20
REF
BYPC
AN0
AN4
AN3
AN22 AN26 AN31 AN32
AN21
AN7
AN2
VRL
AN6
AN25 AN30 AN33
AN24 AN29 AN34
C
D
E
VDD33 VDD
ETPUA ETPUA
VSS
VDD
AN8
VSS
VDD
AN17 VSSA1
AN38 AN9
AN10 AN18
30
31
ETPUA ETPUA VDDEH
28 29
1
ETPUA ETPUA ETPUA VDDEH
F
24
27
26
1
ETPUA ETPUA ETPUA ETPUA
G
H
J
23
22
25
21
Version 2.1 – 13 July 2004
ETPUA ETPUA ETPUA ETPUA
20 19 18 17
ETPUA ETPUA ETPUA ETPUA
16 15 14 13
ETPUA ETPUA ETPUA ETPUA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
12
11
10
9
ETPUA ETPUA ETPUA ETPUA
L
8
7
6
5
ETPUA ETPUA ETPUA ETPUA
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
M
N
P
4
3
2
1
ETPUA TCRCLK
BDIP
TEA
0
A
CS3
CS2
CS1
CS0
R
T
WE3
WE2
WE1
WE0
VDDE2 VSS VDDE2 VDDE2
VSS VDDE2 VDDE2 VDDE2
VDDE2 NC_34 RD_WR VDDE2
ADDR
U
V
NC_35
TA
VDD33
16
ADDR ADDR
18 17
ADDR
8
TS
ADDR ADDR ADDR ADDR
NC_X
W
Y
Note:
No connects (x = 1 to 38)
20
19
9
10
ADDR ADDR ADDR
VDDE2
NC_36 NC_37
No connect. AC22 & AD23 reserved
22
21
11
ADDR ADDR ADDR ADDR
AA
24
23
13
12
ADDR ADDR ADDR
AB VDDE2
25
15
14
ADDR ADDR ADDR
DATA DATA
26 28
DATA DATA DATA DATA
VDDE2
VDDE2
AC
AD
VSS
VDD
26
27
31
30
31
8
10
ADDR ADDR
DATA DATA DATA DATA
24 25 27 29
GPIO DATA DATA DATA
VDD33
VSS
VDD
28
30
207
9
11
13
ADDR
29
DATA DATA DATA DATA DATA DATA DATA DATA
OE
BR
AE
VSS
VDD
17
19
VDDE2
5
21
23
0
2
4
6
VDDE2
11
DATA DATA
DATA DATA
GPIO DATA DATA
DATA DATA
5
AF VSS
1
VDD
2
16
18
20
6
22
7
206
1
3
7
3
4
8
9
10
12
13
Figure 34. MPC5553 416 Package, Left Side
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
51
Mechanicals
14
15
16
17
18
19
20
21
22
23
24
25
26
ETRIG
1
GPIO
205
VSSA0 AN15
VSSA0 AN14
NC_1 NC_2 NC_3 NC_4
MDO11 MDO8 VDD VDD33 VSS
A
ETRIG
0
NC_5 NC_6 NC_7 NC_8 MDO10 MDO7 MDO4 MDO0
VSS VDDE7
B
VDDA0 AN13 NC_9 NC_10 NC_11 NC_12 MDO9 MDO6 MDO3 MDO1
VSS VDDE7 VDD
C
VDDEH
9
VDDEH
8
AN12 NC_13 NC_14 NC_15 NC_16 MDO5 MDO2
VSS VDDE7 TCK
VDDE7 TMS TDO
TDI
D
TEST
EVTO
NC_17
E
MSEO0 JCOMP EVTI
F
GPIO
MSEO1 MCKO
204
G
H
GPIO
203
RDY
NC_18 NC_19
VDDEH
6
NC_20 NC_21 NC_22
J
VDDE7 VDDE7 VDDE7 VDDE7
NC_23 NC_24 NC_25 NC_26
NC_27 NC_28 NC_29 NC_30
NC_31 NC_32 NC_33 SINB
SOUTB PCSB3 PCSB0 PCSB1
PCSA3 PCSB4 SCKB PCSB2
PCSB5 SOUTA SINA SCKA
PCSA1 PCSA0 PCSA2 VPP
PCSA4 TXDA PCSA5 VFLASH
K
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDE7
VSS VDDE7
VSS VDDE7
L
M
N
VSS
VSS
VSS
VSS
VSS
VSS
P
R
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
T
U
RST
CNTXC RXDA RSTOUT
CFG
V
RXDB CNRXC TXDB RESET
W
Y
WKP BOOT
CFG CFG1
VRC
VSS
VSS
SYN
VDDEH PLL
BOOT
EXTAL
XTAL
AA
AB
AC
AD
AE
AF
6
CFG1 CFG0
VRC
CTL
PLL
CFG0
VDD
DATA DATA EMIOS EMIOS EMIOS EMIOS VDDEH
VDD
SYN
VDDE5 NC_36 VSS
VDD VRC33
12
14
2
8
12
21
4
DATA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
CNTXA VDDE5 NC_37 VSS
VDD VDD33
15
3
6
10
15
17
22
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
BG
CNRXA VDDE5 CLKOUT VSS
VDD
1
5
9
13
16
19
23
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
ENG
CLK
NC_38
14
CNTXB CNRXB VDDE5
22 23 24
VSS
26
0
4
7
11
14
18
20
15
16
17
18
19
20
21
25
Figure 35. MPC5553 416 Package, Right Side
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
52
Freescale Semiconductor
Mechanicals
4.1.2
MPC5553 324 PBGA Pinout
Figure 36 is a pinout for the MPC5553 324 PBGA package.
1
2
3
4
5
6
7
8
9
10
11
12
13
AN28 AN35 VSSA0 AN12 MDO11 MDO10 MDO8 VDD VDD33 VSS
AN31 AN32 VSSA0 AN13 MDO9 MDO7 MDO4 MDO0 VSS VDDE7
14
15
16
17
18
19
20
21
22
VSSA1 AN1
AN5
VRH
VRL
AN27
A
B
VSS
VDD VSTBY AN37 AN11 VDDA1
A
REF
BYPC
AN16
AN20 AN21
AN9
AN0
AN4
AN3
AN23 AN26
AN22 AN25
VDD33 VSS
VDD
VSS
AN36
VDD
VSS
AN39
AN8
AN19
AN17
AN38
B
ETPUA ETPUA
30
AN7
AN2
AN30 AN33 VDDA0 AN14 MDO5 MDO2 MDO1
VDDEH
VSS VDDE7 VDD
C
D
E
C
D
E
31
ETPUA ETPUA ETPUA
28 29 26
AN10 AN18
AN6
AN24
AN29
AN34
AN15 MDO6 MDO3
VSS VDDE7 TCK
VDDE7 TMS TDO
VDDE7 JCOMP EVTI
TDI
VDD
9
ETPUA ETPUA ETPUA ETPUA
24 27 25 21
TEST
EVTO
ETPUA ETPUA ETPUA ETPUA
23
F
F
22
17
18
ETPUA ETPUA ETPUA ETPUA
RDY MCKO MSEO0 MSEO1
G
H
J
G
H
J
20
19
14
13
Version 2.2p – 13 July 2004
ETPUA ETPUA ETPUA VDDEH
VDDEH GPIO GPIO
SINB
16 15 10
1
10
203
204
ETPUA ETPUA ETPUA ETPUA
12 11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VDDE7
SOUTB PCSB3 PCSB0 PCSB1
PCSA3 PCSB4 SCKB PCSB2
PCSB5 SOUTA SINA SCKA
PCSA1 PCSA0 PCSA2 VPP
PCSA4 TXDA PCSA5 VFLASH
6
9
ETPUA ETPUA ETPUA ETPUA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
K
8
7
2
5
ETPUA ETPUA ETPUA ETPUA
L
L
4
3
0
1
TCRCLK
A
VDDE2 VDDE2 VSS
M
N
P
BDIP
CS1
CS0
M
N
P
VSS
VSS
VSS VDDE2 VSS
VSS VDDE2 VSS
CS3
CS2
WE1
WE0
ADDR ADDR
RST
CNTXC RXDA RSTOUT
CFG
RD_WR
VDDE2
VDD33
TA
16
17
ADDR ADDR
WKP
CNRXC TXDB RESET
CFG
R
T
R
T
18
19
ADDR ADDR ADDR
20 21 12
BOOT
CFG1
VRC
VSS
VSS
SYN
RXDB
TS
NC
Note:
No connect. Reserved (W18 & Y19 are shorted to each other)
ADDR ADDR ADDR ADDR
VDDEH PLL
BOOT
EXTAL
XTAL
U
V
U
V
22
23
13
14
6
CFG1 CFG0
ADDR ADDR ADDR ADDR
VRC
CTL
PLL
CFG0
VDD
24
25
15
31
ADDR
26
ADDR
30
DATA DATA DATA EMIOS EMIOS VDDEH EMIOS EMIOS
VDD
SYN
VDDE2 VDD33 VDDE2
DATA DATA DATA
VDDE5
NC
VSS
NC
VDD VRC33
VSS
W
Y
VDDE2
VSS
VDD
W
Y
11
12
14
2
8
4
12
21
ADDR ADDR
28
GPIO DATA DATA EMIOS EMIOS EMIOS EMIOS EMIOS
VDDE2
CNTXA VDDE5
VDD VDD33
VSS
VDD
VDD
27
8
9
10
207
13
15
6
10
15
13
17
22
ADDR
29
DATA
1
GPIO DATA DATA
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
3
VDDE2
VDDE2
VDDE2
CNRXA VDDE5 CLKOUT VSS
VDD
AA
VSS
AA
AB
206
5
7
OE
9
5
9
16
19
23
DATA DATA DATA DATA DATA
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
0
ENG
CNTXB CNRXB VDDE5
CLK
VSS
22
AB VSS
1
VDD VDDE2
0
2
3
4
6
1
4
7
11
14
18
20
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
Figure 36. MPC5553 324 Package
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
53
Preliminary—Subject to Change Without Notice
Mechanicals
4.1.3
MPC5553 208 MAP BGA Pinout
Figure 37 is a pinout for the MPC5553 208 MAP BGA package.
NOTE
VDDEH10 and VDDEH6 are connected internally on the 208-ball package
and are listed as VDDEH6.
1
2
3
4
5
6
7
8
9
10
AN27 VSSA0 AN12 MDO2 MDO0 VDD33 VSS
VSS VDD
VSS MSEO0 TCK
11
12
13
14
15
16
VSSA1 AN1
AN5
VRH
VRL
A
B
C
D
E
F
VSS
AN9
AN11 VDDA1
AN38 AN21
A
B
C
D
E
F
REF
BYPC
AN22 AN25 AN28 VDDA0 AN13 MDO3 MDO1
VDD
VSS
AN0
AN4
AN3
AN6
AN7
AN23 AN32 AN33 AN14 AN15
VDDEH
VSTBY VDD
VSS
VDD
AN37
AN17 AN34 AN16
AN24 AN30 AN31 AN35
VSS
TMS
TDI
EVTO TEST
EVTI MSEO1
VDD33 AN39
ETPUA ETPUA
VSS
VDD
AN36
AN18
AN2
9
VDDE7
30
31
ETPUA ETPUA ETPUA
28 29 26
VDDEH
6
TDO MCKO JCOMP
8 June 2005p
ETPUA ETPUA ETPUA ETPUA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SOUTB PCSB3 SINB PCSB0
PCSA3 PCSB4 PCSB2 PCSB1
PCSB5 TXDA PCSA2 SCKB
G
H
J
G
H
J
24
27
25
21
ETPUA ETPUA ETPUA ETPUA
23 22 17 18
ETPUA ETPUA ETPUA ETPUA
20 19 14 13
ETPUA ETPUA ETPUA VDDEH
CNTXC RXDA RSTOUT VPP
WKP
K
L
K
L
16
15
7
1
ETPUA ETPUA ETPUA TCRCLK
TXDB CNRXC
RESET
12 11
6
A
CFG
CS0
Note:
No connect. R1 reserved for CS0
ETPUA ETPUA ETPUA ETPUA
PLL
BOOT
VSS
SYN
RXDB
M
N
P
R
T
M
N
P
R
T
10
9
1
5
CFG0 CFG1
ETPUA ETPUA ETPUA
EMIOS EMIOS VDDEH EMIOS EMIOS
2
VRC
CTL
PLL
VDD33
VDDE2
VDD33 VSS
CNTXA VDD
EXTAL
VSS
VDD
8
4
0
10
4
12
21
CFG1
ETPUA ETPUA
GPIO
207
EMIOS EMIOS EMIOS EMIOS EMIOS
6
VSS VRC33 XTAL
VSS
VDD
3
2
8
16 17 22
GPIO EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
206
VDD
CNRXA CNRXB VDD
VSS
CS0
VSS
VDD
4
3
9
11
14
19
23
SYN
VSS
16
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS
0
4
ENG
CNTXB VDDE5
CLK
VDD
15
VSS
1
VDD
2
OE
3
1
5
5
6
7
7
13
8
15
9
18
10
20
11
12
13
14
Figure 37. MPC5553 208 Package
MPC5553 Microcontroller Data Sheet, Rev. 0
54
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Mechanicals
4.2
Package Dimensions
4.2.1
MPC5553 416-Pin Package
Figure 38 is a package drawing of the MPC5553 416 pin TEPBGA package.
Figure 38. MPC5553 416 TEPBGA Package
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
55
Preliminary—Subject to Change Without Notice
Mechanicals
4.2.2
MPC5553 324-Pin Package
Figure 39 is a package drawing of the MPC5553 324-pin TEPBGA package.
Figure 39. MPC5553 324 TEPBGA Package
MPC5553 Microcontroller Data Sheet, Rev. 0
56
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Mechanicals
4.2.3
MPC5553 208-Pin Package
Figure 40 is a package drawing of the MPC5553 208-pin MAP BGA package.
Figure 40. MPC5553 208 MAP BGA Package
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
57
Preliminary—Subject to Change Without Notice
Revision History
5 Revision History
Table 32 provides a revision history of this document.
Table 32. Revision History
Substantive Change(s)
This is the first released version of this document.
Revision
Location(s)
Rev. 0
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
58
Freescale Semiconductor
THIS PAGE IS INTENTIONALLY BLANK
MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
59
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Document Number: MPC5553
Rev. 0
06/2006
Preliminary—Subject to Change Without Notice
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