MPC8245ARZU400D [FREESCALE]
Part Number Specification for the MPC8245ARZUnnnX Series; 为MPC8245ARZUnnnX系列型号规格
| 型号： | MPC8245ARZU400D |
| 厂家： | 
Freescale |
| 描述： | Part Number Specification for the MPC8245ARZUnnnX Series |
| 文件： | 总20页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC8245ARZUPNS
Rev. 2, 07/2004
Freescale Semiconductor
Advance Information
MPC8245
Part Number Specification for the
MPC8245ARZUnnnX Series
This document describes part-number-specific changes to
recommended operating conditions and revised electrical
specifications, as applicable, from those described in the general
MPC8245 Integrated Processor Hardware Specifications
(Order No. MPC8245EC). The MPC8245 combines a
PowerPC™ MPC603e core with a PCI bridge.
Freescale Part Numbers Affected:
MPC8245RZU400D
MPC8245ARZU400D
MPC8245ARZU466D
Specifications provided in this document supersede those in the
MPC8245 Integrated Processor Hardware Specifications, Rev. 3
or later, for the part numbers listed in Table A only.
Specifications not addressed in this document are unchanged.
Because this document is frequently updated, refer to
http://www.freescale.com or to your Freescale sales office for the
latest version.
Note that headings and table numbers in this document are not
consecutively numbered. They are intended to correspond to the
heading or table affected in the general hardware specification.
Part numbers addressed in this document are listed in Table A. For
more detailed ordering information, see Section 9, “Ordering
Information.”
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Features
Table A. Part Numbers Addressed in this Data Sheet
Operating Conditions
Processor
Version
Register
Value
Freescale
Part No.
Significant Differences from
Hardware Specification
CPU
Frequency
(MHz)
T
J
V
DD
(°C)
MPC8245RZU400D
MPC8245ARZU400D
MPC8245ARZU466D
400
400
466
2.1 ± 100 mV
0 to 85 Modified voltage and temperature
specifications to achieve 400 MHz
0x80811014
0 to 85 Modified voltage and temperature
specifications to achieve 400 MHz
0 to 85 Modified voltage and temperature
specifications to achieve 466 MHz
Note: The X prefix in a Freescale part number designates a ‘pilot production prototype’ as defined by Freescale SOP
3-13. These are from a limited production volume of prototypes that are manufactured, tested, and inspected for quality
on a qualified technology to simulate normal production. These parts have only preliminary reliability and
characterization data. Before pilot production prototypes can be shipped, written authorization from the customer must
be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still
occur while shipping pilot production prototypes.
The ‘A’ in the part number represents parts that are manufactured under a 29-angstrom process instead of the original
35-angstrom process.
2 Features
This section summarizes changes to the power management feature of the MPC8245 described in the MPC8245
Integrated Processor Hardware Specifications.
3 General Parameters
This section summarizes changes to the general parameters of the MPC8245 core power supply described in the
MPC8245 Integrated Processor Hardware Specifications.
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
2
Freescale Semiconductor
General Parameters
4.1.1 Absolute Maximum Ratings
The tables in this section describe the MPC8245 DC electrical characteristics. Table 1 provides the absolute
maximum ratings.
Table 1. Absolute Maximum Ratings
1
Characteristic
Symbol
Range
Unit
Supply voltage—CPU core and peripheral logic
Supply voltage—memory bus drivers
Supply voltage—PCI and standard I/O buffers
Supply voltage—PLLs
V
–0.3 to 2.2
–0.3 to 3.6
–0.3 to 3.6
–0.3 to 2.2
–0.3 to 5.4
–0.3 to 3.6
0 to 85
V
V
DD
GV
OV
DD
DD
V
AV /AV
2
DD
V
DD
Supply voltage—PCI reference
LV
V
V
DD
in
2
Input voltage
V
Operational die-junction temperature range
Storage temperature range
Notes:
T
°C
°C
j
T
–55 to 150
stg
1. Table 2 shows functional and tested operating conditions. Absolute maximum ratings are stress ratings only, and functional
operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
2. PCI inputs with LV = 5 V ± 5% V DC may undergo corresponding stress at voltages exceeding LV + 0.5 V DC.
DD
DD
4.1.2 Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8245 part numbers described herein.
(1)
Table 2. Recommended Operating Conditions
Recommended
Characteristic
Symbol
Value for
Unit
400 MHz CPU
Supply voltage
V
2.1 V ± 100 mV
2.1 V ± 100 mV
2.1 V ± 100 mV
0 to 85
V
V
DD
CPU PLL supply voltage
AV
DD
PLL supply voltage—peripheral logic
AV
2
V
DD
(2)
Die-junction temperature
T
°C
j
Notes:
1. Freescale tested these operating conditions and recommends them. Proper device operation outside of these conditions is
not guaranteed.
2. For information about the thermal characteristics of this part, refer to the MPC8245 Integrated Processor Hardware
Specifications. Note that the lower die-junction temperature creates a greater need to use a heat sink with this part.
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
3
General Parameters
4.1.5 Power Characteristics
The AC electrical characteristics and AC timing for the parts described in this document are unaffected, and comply
with the MPC8245 Integrated Processor Hardware Specifications. Table 5 provides the power consumption for the
MPC8245 part numbers described herein.
Table 5. Power Consumption
PCI Bus Clock/Memory Bus Clock
CPU Clock Frequency (MHz)
Mode
Unit
Notes
66/133/399
66/133/466
Typical
Max—CFP
Max—INT
Doze
2.8
3.3
2.8
1.9
0.7
3.2
3.6
3.1
2.1
0.8
0.4
W
W
W
W
W
W
1, 5
1, 2
1, 3
1, 4, 6
1, 4, 6
1, 4, 6
Nap
Sleep
0.4
10
I/O Power Supplies
Mode
Range
Range
Unit
Notes
Typ—OV
Typ—GV
Notes:
140–360
140–360
mW
7, 8
DD
DD
340–920
340–930
mW
7, 9
1. The values include V , AV , and AV 2, but do not include I/O supply power.
DD
DD
DD
2. Maximum—FP power is measured at V = 2.1 V with dynamic power management enabled while running an entirely
DD
cache-resident, looping, floating point multiplication instruction.
3. Maximum—INT power is measured at V = 2.1 V with dynamic power management enabled while running entirely
DD
cache-resident, looping, integer instructions.
4. Power saving mode maximums are measured at V = 2.1 V while the device is in doze, nap, or sleep mode.
DD
5. Typical power is measured at V = AV = 2.1 V, OV = 3.3 V where a nominal FP value, a nominal INT value, and a
DD
DD
DD
value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory
are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. The typical minimum I/O power values was the result of the MPC8245 performing cache resident integer operations at the
slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz.
8. The typical maximum OV value resulted from the MPC8245 operating at the fastest frequency combination of
DD
66:133:399 (PCI:Mem:CPU) MHz for the 400-MHz part, 66:133:466 (PCI:Mem:CPU) MHz for the 466-MHz part, and
performing continuous flushes of cache lines with alternating ones and zeros to PCI memory.
9. The typical maximum GV value resulted from the MPC8245 operating at the fastest frequency combination of
DD
66:133:399 (PCI:Mem:CPU) MHz for the 400-MHz part, 66:133:466 (PCI:Mem:CPU) MHz for the 466-MHz part, and
performing continuous flushes of cache lines with alternating ones and zeros on 64-bit boundaries to local memory.
10. Power consumption of PLL supply pins (AV and AV 2) < 15 mW that the design guarantees but were not tested.
DD
DD
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
4
General Parameters
4.3.1 Clock AC Specifications
Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation for 29 angstrom parts
(400 and 466 MHz). These graphs define the areas of DLL locking for various modes. The gray areas show where
the DLL will lock.
Register settings that define each DLL mode are shown in Table 9.
Table 9. DLL Mode Definition
Value of Bit 2 of Config
Register at 0x76
Value of Bit 7 of Config
Register at 0x72
DLL Mode
Normal tap delay,
No DLL extend
0
0
1
1
0
1
0
1
Normal tap delay,
DLL extend
Max tap delay,
No DLL extend
Max tap delay,
DLL extend
The DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished by
increasing the time between each of the 128 tap points in the delay line. Although this increased time makes it easier
to guarantee that the reference clock will be within the DLL lock range, it also means there may be slightly more
jitter in the output clock of the DLL, should the phase comparator shift the clock between adjacent tap points. Refer
to Freescale application note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for details on
memory design.
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
5
General Parameters
30
25
20
15
10
N = 1
N = 2
7.5
0
1
2
3
4
5
T
Propagation Delay Time (ns)
loop
Figure 7. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 0
and Normal Tap Delay
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
6
Freescale Semiconductor
General Parameters
30
25
20
15
N = 1
10
N = 2
7.5
0
1
2
3
4
5
T
Propagation Delay Time (ns)
loop
Figure 8. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1
and Normal Tap Delay
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
7
General Parameters
30
25
20
15
10
N = 1
N = 2
7.5
0
1
2
3
4
5
T
Propagation Delay Time (ns)
loop
Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 0
and Max Tap Delay
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
8
Freescale Semiconductor
General Parameters
30
25
20
15
N = 1
N = 2
10
7.5
0
1
2
3
4
5
T
Propagation Delay Time (ns)
loop
Figure 10. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1
and Max Tap Delay
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
9
General Parameters
4.3.3 Output AC Timing Specification
Table 11 provides the processor bus AC timing specification for output hold time for debug signals in the 466-MHz
CPU of the MPC8245 at recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V. All output
DD
timings assume a purely resistive 50-Ω load (see Figure 14 in the MPC8245 Integrated Processor Hardware
Specifications). Output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias,
and connectors in the system. These specifications are for the default driver strengths listed in the MPC8245
Integrated Processor Hardware Specifications.
Table 11. Output AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
13b
Output hold (debug signals)
0.0
—
ns
1
Note:
1. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of the
memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in question. SDRAM_SYNC_IN is
the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising
edges occur on every rising and falling edge of PCI_SYNC_IN).
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
10
Freescale Semiconductor
PLL Configuration
6 PLL Configuration
The MPC8245 internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN (PCI bus)
frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency of
operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO) frequency of operation
for memory-to-CPU frequency multiplying. The PLL configurations for the 400- and 466-MHz parts are shown in
Table 18 and Table 19, respectively.
Table 18. PLL Configurations for the 400-MHz Part Offering
9
400-MHz Part
Multipliers
Periph
Logic/Mem CPU Clock
Bus Clock
Range
(MHz)
PLL_CFG
[0:4]
PCI Clock Input
Ref
11,14,15
(PCI_SYNC_IN)
PCI-to-Mem Mem-to-CPU
Range
(MHz)
1
Range
(Mem VCO)
(CPU VCO)
(MHz)
2
0
00000
00001
25–44
75–132
75–132
50–66
188–330
225–396
225–297
100–133
100–184
3 (2)
3 (2)
2.5 (2)
3 (2)
5
1
25–44
13
9
1
1
2
00010
50 –66
1 (4)
4.5 (2)
2 (4)
16
8
3
00011
50 –66
50–66
1 (Bypass)
2 (4)
4
4
00100
25–46
50–92
2 (4)
17
6
00110
Bypass
60–66
Bypass
1 (Bypass)
4 (2)
Bypass
3 (2)
6
1
7 (Rev. B)
00111
60 –66
180–198
350–392
180–198
180–264
225–396
204–297
180–230
238–347
180–276
263–399
180–264
250–330
180–198
300–396
182–329
272–400
200–368
200–264
13
5
7 (Rev. D)
00111
25–28
100–112
60–66
3.5 (2)
3 (2)
6
1
1
8
9
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
60 –66
1 (4)
6
45 –66
90–132
50–88
2 (2)
2 (2)
5
A
25–44
2 (4)
4.5 (2)
3 (2)
3
1
4
1
4
B
45 –66
68–99
1.5 (2)
2 (4)
6
C
36 –46
72–92
2.5 (2)
3.5 (2)
3 (2)
3
D
45 –66
68–99
1.5 (2)
2 (4)
6
E
30 –46
60–92
5
F
25–38
30–44
75–114
60–132
100–132
90–99
3 (2)
3.5 (2)
2 (2)
2
10
11
12
13
14
15
16
17
3 (2)
2
25–33
4 (2)
2.5 (2)
2 (2)
6
1
60 –66
1.5 (2)
4 (2)
5
25–33
100–132
52–94
3 (2)
6
4
5
26 –47
2 (4)
3.5 (2)
4 (2)
3
27 –40
68–100
50–92
2.5 (2)
2 (4)
4
25–46
25–33
4 (2)
2
100–132
4 (2)
2 (2)
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
11
PLL Configuration
Table 18. PLL Configurations for the 400-MHz Part Offering (continued)
9
400-MHz Part
Multipliers
Periph
Logic/Mem CPU Clock
Bus Clock
Range
(MHz)
PLL_CFG
[0:4]
PCI Clock Input
Ref
11,14,15
(PCI_SYNC_IN)
PCI-to-Mem Mem-to-CPU
Range
(MHz)
1
Range
(Mem VCO)
(CPU VCO)
(MHz)
3
5
1
1
1
1
1
18
11000
11001
11010
27 –53
68–132
72–132
204–396
180–330
200–264
204–396
198–297
180–248
2.5 (2)
2 (2)
1 (4)
2 (2)
1.5 (2)
1.5 (2)
Off
3 (2)
2.5 (2)
4 (2)
3 (2)
3 (2)
2.5 (2)
Off
6
19
1A
36 –66
9
50 –66
50–66
13
3
1B
11011
34 –66
68–132
6
1C
11100
11101
44 –66
66–99
6
1D
48 –66
72–99
10
1E (Rev. B)
1E (Rev. D)
1F
11110
Not usable
66–114
3
5
11110
33 –57
231–399
2 (2)
Off
3.5 (2)
Off
10
11111
Not usable
Notes:
1. Limited by maximum PCI input frequency (66 MHz).
2. Limited by maximum system memory interface operating frequency (133 MHz).
3. Limited by minimum memory VCO frequency (132 MHz).
4. Limited due to maximum memory VCO frequency (372 MHz).
5. Limited by maximum CPU operating frequency (400 MHz).
6. Limited by minimum CPU VCO frequency (360 MHz).
7. Limited by maximum CPU VCO frequency (800 MHz).
8. Limited by minimum CPU operating frequency (100 MHz).
9. Limited by minimum memory bus frequency (50 MHz).
10. In clock off mode, no clocking occurs inside the MPC8245, regardless of the PCI_SYNC_IN input.
11. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for
clarity.
12. PLL_CFG[0:4] settings that are not listed are reserved.
13. Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not
backwards-compatible.
14. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully
backwards-compatible.
15. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
16. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for
hardware modeling support. The AC timing specifications given in this document do not apply in the PLL
bypass mode.
17. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the
peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In
this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode
operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be
externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications
given in this document do not apply in the dual PLL bypass mode.
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
12
Freescale Semiconductor
PLL Configuration
Table 19. PLL Configurations for the 466-MHz Part Offering
9
466-MHz Part
Multipliers
Periph
Logic/Mem CPU Clock
Bus Clock
Range
(MHz)
PLL_CFG
[0:4]
PCI Clock Input
Ref
11,14,15
(PCI_SYNC_IN)
PCI-to-Mem Mem-to-CPU
Range
(MHz)
1
Range
(Mem VCO)
(CPU VCO)
(MHz)
2
0
1
00000
00001
25–44
75–132
75–132
50–66
188–330
225–396
225–297
100–133
100–184
3 (2)
3 (2)
2.5 (2)
3 (2)
2
25–44
13
9
1
1
2
00010
50 –66
1 (4)
4.5 (2)
2 (4)
16
8
3
00011
50 –66
50–66
1 (Bypass)
2 (4)
4
4
00100
25–46
25–33
50–92
2 (4)
17
6
00110
Bypass
100–133
60–66
Bypass
4 (2)
Bypass
3.5 (2)
3 (2)
2
7
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
350–466
180–198
180–264
225–432
204–297
180–230
238–347
180–276
263–462
180–264
250–330
180–198
300–396
182–329
272–460
200–368
200–264
204–396
180–330
200–264
204–396
198–297
180–248
6
1
1
8
60 –66
1 (4)
6
9
45 –66
90–132
50–96
2 (2)
2 (2)
4
A
25–46
2 (4)
4.5 (2)
3 (2)
3
1
4
1
4
B
45 –66
68–99
1.5 (2)
2 (4)
6
C
36 –46
72–92
2.5 (2)
3.5 (2)
3 (2)
3
D
45 –66
68–99
1.5 (2)
2 (4)
6
E
30 –46
60–92
2
F
25–44
75–132
60–132
100–132
90–99
3 (2)
3.5 (2)
2 (2)
6
2
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
30 –44
3 (2)
2
25–33
4 (2)
2.5 (2)
2 (2)
6
1
60 –66
1.5 (2)
4 (2)
2
25–33
100–132
52–94
3 (2)
6
4
5
26 –47
2 (4)
3.5 (2)
4 (2)
3
27 –46
68–115
50–92
2.5 (2)
2 (4)
4
25–46
25–33
4 (2)
2
100–132
68–132
72–132
50–66
4 (2)
2 (2)
3
2
1
1
1
1
1
27 –53
2.5 (2)
2 (2)
3 (2)
6
36 –66
2.5 (2)
4 (2)
9
50 –66
1 (4)
13
3
11011
34 –66
68–132
66–99
2 (2)
3 (2)
6
11100
11101
44 –66
1.5 (2)
1.5 (2)
3 (2)
6
48 –66
72–99
2.5 (2)
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
13
PLL Configuration
Table 19. PLL Configurations for the 466-MHz Part Offering (continued)
9
466-MHz Part
Multipliers
Periph
Logic/Mem CPU Clock
Bus Clock
Range
(MHz)
PLL_CFG
[0:4]
PCI Clock Input
Ref
11,14,15
(PCI_SYNC_IN)
PCI-to-Mem Mem-to-CPU
Range
(MHz)
1
Range
(Mem VCO)
(CPU VCO)
(MHz)
3
1,2
1E
1F
11110
33 –66
66–132
231–462
2 (2)
Off
3.5 (2)
Off
10
11111
Not usable
Notes:
1. Limited by maximum PCI input frequency (66 MHz).
2. Limited by maximum memory interface operating frequency (133 MHz).
3. Limited by minimum memory VCO frequency (132 MHz).
4. Limited due to maximum memory VCO frequency (372 MHz).
5. Limited by maximum CPU operating frequency (466 MHz).
6. Limited by minimum CPU VCO frequency (360 MHz).
7. Limited by maximum CPU VCO frequency (932 MHz).
8. Limited by minimum CPU operating frequency (100 MHz).
9. Limited by minimum memory bus frequency (50 MHz).
10. In clock off mode, no clocking occurs inside the MPC8245 regardless of the PCI_SYNC_IN input.
11. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for
clarity.
12. PLL_CFG[0:4] settings not listed are reserved.
13. Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not
backwards-compatible.
14. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully
backwards-compatible.
15. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
16. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for
hardware modeling support. The AC timing specifications given in this document do not apply in the PLL
bypass mode.
17. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the
peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In
this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode
operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be
externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications
given in this document do not apply in the dual PLL bypass mode.
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
14
Freescale Semiconductor
Ordering Information
9 Ordering Information
Ordering information for the parts covered in this document is provided in Section 9.1, “Part Numbers Fully
Addressed by This Document.” Section 9.2, “Part Marking,” addresses the marking specifications.
9.1
Part Numbers Fully Addressed by This Document
Table 21 provides the ordering information for the MPC8245 parts described herein. Note that the individual part
numbers correspond to a maximum processor core frequency.
Table 21. Part Numbering Nomenclature
MPC nnnn
X(1)
xx
nnn
X
R
Processor
Frequency
(MHz)
Product
Code
Part
Identifier
Process
Descriptor
Part
Specification
Package
Revision Level
MPC
8245
—
R = Partial Spec.
ZU = TBGA
400
Contact local Freescale
sales office
2.1 V ± 100 mV
0° to 85°C
A =
29 Angstrom
R = Partial Spec.
ZU = TBGA
400, 466
Contact local Freescale
sales office
2.1 V ± 100 mV
0° to 85°C
Notes:
1. Note that on the standard ‘L’ specification, the process descriptor is not added because it is the standard size for
the part (35 angstrom). The 400- and 466-MHz parts marked with ‘A’ follow a different process description
(29 angstrom), which is different from the 35-angstrom process on the 350-MHz and lower frequency parts.
9.2 Part Marking
Parts are marked as in the example shown in Figure 33.
MPC8245AR
ZUnnnx
MMMMMM
ATWLYYWWA
8245
TBGA
Notes:
MMMMMM is the 6-digit mask number.
ATWLYYWWA is the traceability code.
Figure 33. Freescale Part Marking for TBGA Device
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
15
Document Revision History
Document Revision History
Table B provides a revision history for this part number specification.
Table B Document Revision History
Rev. No.
Date
Substantive Change(s)
0
Original release.
0.1
1.0
Minor edit to part number.
• Added to list of parts covered by this document, including the non-A process identifier parts. Updated
Table A and Table 20.
• Nontechnical reformatting.
2
07/12/04 • Updated to Freescale template.
• Updated section numbers to accurately reflect hardware specifications sections.
• Changed junction temperature range in Table 1 to reflect range depicted in Table A (0° to 85°C).
• Added Section 4.3.1 to illustrate DLL locking graphs for 29 angstrom parts (400- and 466-MHz parts).
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
16
Freescale Semiconductor
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
17
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
18
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
Freescale Semiconductor
19
Information in this document is provided solely to enable system and software implementers to use
Freescale Semiconductor products. There are no express or implied copyright licenses granted
hereunder to design or fabricate any integrated circuits or integrated circuits based on the information
in this document.
How to Reach Us:
USA/Europe/Locations Not Listed:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405,
Freescale Semiconductor reserves the right to make changes without further notice to any products
herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters
which may be provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts.
Freescale Semiconductor does not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized for use as components
in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer purchase or use
Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was
negligent regarding the design or manufacture of the part.
Denver, Colorado 80217
1-480-768-2130
(800) 521-6274
Japan:
Freescale Semiconductor Japan Ltd.
Technical Information Center
3-20-1, Minami-Azabu, Minato-ku
Tokyo 106-8573, Japan
81-3-3440-3569
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T. Hong Kong
852-26668334
Home Page:
www.freescale.com
Learn More: For more information about Freescale Semiconductor products, please visit
www.freescale.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described
product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and
used under license. All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2004.
MPC8245ARZUPNS
Rev. 2
07/2004
相关型号：
MPC8245LVV333D
32-BIT, 333MHz, RISC PROCESSOR, PBGA352, 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-352
NXP
MPC8245LZU300B
32-BIT, 300MHz, RISC PROCESSOR, PBGA352, 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
MOTOROLA
©2020 ICPDF网 联系我们和版权申明