MPC8275ZQE_技术文档

MPC8280EC

Rev. 1.7, 12/2006

Freescale Semiconductor

Technical Data

MPC8280

PowerQUICC II™ Family

Hardware Specifications

Contents

This document contains detailed information about power

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7

3. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 8

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 11

5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6. AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 14

7. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 24

8. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 73

10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 76

11. Document Revision History . . . . . . . . . . . . . . . . . . . 76

considerations, DC/AC electrical characteristics, and AC timing

specifications for .13µm (HiP7) members of the

PowerQUICC II™ family of integrated communications

processors—the MPC8280, the MPC8275, and the MPC8270

(collectively called 'the MPC8280' throughout this document).

Overview

1 Overview

Table 1 shows the functionality supported by each device in the MPC8280 family.

Table 1. MPC8280 PowerQUICC II Family Functionality

Devices

Functionality

MPC8270

MPC8275

516 PBGA

MPC8280

480 TBGA

Package ¹

480 TBGA 516 PBGA

Serial communications controllers (SCCs)

QUICC multi-channel controller (QMC)

Fast communication controllers (FCCs)

I-Cache (Kbyte)

4

—

3

4

—

3

4

—

3

4

—

3

16

3

16

3

16

3

16

3

D-Cache (Kbyte)

Ethernet (10/100)

UTOPIA II Ports

0

2

Multi-channel controllers (MCCs)

PCI bridge

1

2

Yes

—

1

Yes

—

1

Yes

—

1

Yes

1

Transmission convergence (TC) layer

Inverse multiplexing for ATM (IMA)

Universal serial bus (USB) 2.0 full/low rate

Security engine (SEC)

—

1

Refer to Table 2.

Devices in the MPC8280 family are available in three packages—the standard ZU package and the alternate VR or

ZQ packages—as shown in Table 2. Note that throughout this document references to the MPC8280 and the

MPC8270 are inclusive of VR and ZQ package devices unless otherwise specified. For more information on VR and

ZQ packages, contact your Freescale sales office. For package ordering information, refer to Section 10, “Ordering

Information.”

Table 2. HiP7 PowerQUICC II Device Packages

Code

ZU

VR

ZQ

(Package)

(480 TBGA—Leaded)

(516 PBGA—Lead free)

(516 PBGA—Lead spheres)

MPC8280

MPC8270

MPC8275VR

MPC8270VR

MPC8275ZQ

MPC8270ZQ

Device

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

2

Freescale Semiconductor

Overview

Figure 1 shows the block diagram. Shaded portions are device-specific; refer to the notes below.

16 Kbytes

I-Cache

I-MMU

System Interface Unit

60x Bus

(SIU)

G2_LE Core

16 Kbytes

D-Cache

Bus Interface Unit

PCI Bus

32 bits, up to 66 MHz

60x-to-PCI

Bridge

D-MMU

or

60x-to-Local

Bridge

Local Bus

32 bits, up to 100 MHz

Communication Processor Module (CPM)

Memory Controller

Clock Counter

32 KB

Instruction

RAM

32 KB

Data

RAM

Timers

Interrupt

Controller

Serial

DMAs

Parallel I/O

32-bit RISC Microcontroller

and Program ROM

4 Virtual

IDMAs

System Functions

Baud Rate

Generators

IMA

1

Microcode

I²C

MCC1

MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4/ SMC1 SMC2

SPI

1

USB

TC Layer Hardware1

Time Slot Assigner

Serial Interface2

Non-Multiplexed

I/O

3 MII or RMII

Ports

2 UTOPIA

Ports3

8 TDM Ports2

Notes:

¹MPC8280 only (not on MPC8270, the VR package, nor the ZQ package)

²MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have

only 1 SI block and 4 TDM ports (TDM2[A–D]).

³MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC8270VR, nor MPC8270ZQ)

Figure 1. MPC8280 Block Diagram

1.1 Features

The major features of the MPC8280 are as follows:

•

Dual-issue integer (G2_LE) core

— A core version of the EC603e microprocessor

— System core microprocessor supporting frequencies of 166–450 MHz

— Separate 16-Kbyte data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— Architecture-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

3

Overview

— High-performance (SPEC95 benchmark at 450 MHz; 855 Dhrystones MIPS at 450 MHz)

— Supports bus snooping for data cache coherency

— Floating-point unit (FPU)

•

Separate power supply for internal logic and for I/O

Separate PLLs for G2_LE core and for the CPM

— G2_LE core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1 ratios

— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios

64-bit data and 32-bit address 60x bus

•

— Bus supports multiple master designs

— Supports single- and four-beat burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

— Supports data parity or ECC and address parity

32-bit data and 18-bit address local bus

•

— Single-master bus, supports external slaves

— Eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

60x-to-PCI bridge

— Programmable host bridge and agent

— 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

— PCI-to-60x address remapping

•

PCI bridge

— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz

— On-chip arbitration

— Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming

— PCI host bridge or peripheral capabilities

— Includes 4 DMA channels for the following transfers:

– PCI-to-60x to 60x-to-PCI

– 60x-to-PCI to PCI-to-60x

– PCI-to-60x to PCI-to-60x

– 60x-to-PCI to 60x-to-PCI

— Includes all of the configuration registers (which are automatically loaded from the EPROM and used

to configure the MPC8280) required by the PCI standard as well as message and doorbell registers

— Supports the I O standard

2

— Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August 3, 1998)

— Support for 66.67/83.33/100 MHz, 3.3 V specification

— 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

4

Freescale Semiconductor

Overview

— Uses the local bus signals, removing need for additional pins

System interface unit (SIU)

•

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

12-bank memory controller

•

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user- definable

peripherals

— Byte write enables and selectable parity generation

— 32-bit address decodes with programmable bank size

— Three user-programmable machines, general-purpose chip-select machine, and page-mode pipeline

SDRAM machine

— Byte selects for 64-bus width (60x) and byte selects for 32-bus width (local)

— Dedicated interface logic for SDRAM

•

CPU core can be disabled and the device can be used in slave mode to an external core

Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for

communications protocols

— Interfaces to G2_LE core through an on-chip 32-Kbyte dual-port data RAM, an on-chip 32-Kbyte

dual-port instruction RAM and DMA controller

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Three fast communications controllers supporting the following protocols:

– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII)

or reduced media independent interface (RMII)

– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0

protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external connections (no ATM

support for the MPC8270)

– Transparent

– HDLC—Up to T3 rates (clear channel)

– FCC2 can also be connected to the TC layer (MPC8280 only)

— Two multichannel controllers (MCCs) (one MCC on the MPC8270)

– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four

subgroups of 32 channels each.

– Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up

to four TDM interfaces per MCC

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

5

Overview

— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital

portions of the following protocols:

– Ethernet/IEEE 802.3 CDMA/CS

– HDLC/SDLC and HDLC bus

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART

– Binary synchronous (BISYNC) communications

– Transparent

— Universal serial bus (USB) controller

– Supports USB 2.0 full/low rate compatible

– USB host mode

– Supports control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– NRZI encoding/decoding with bit stuffing

– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate

configuration). Note that low-speed operation requires an external hub.

– Flexible data buffers with multiple buffers per frame

– Supports local loopback mode for diagnostics (12 Mbps only)

– Supports USB slave mode

– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– CRC5 checking

– NRZI encoding/decoding with bit stuffing

– 12- or 1.5-Mbps data rate

– Flexible data buffers with multiple buffers per frame

– Automatic retransmission upon transmit error

— Two serial management controllers (SMCs), identical to those of the MPC860

– Provide management for BRI devices as general circuit interface (GCI) controllers in time-

division-multiplexed (TDM) channels

– Transparent

– UART (low-speed operation)

— One serial peripheral interface identical to the MPC860 SPI

2

— One inter-integrated circuit (I C) controller (identical to the MPC860 I C controller)

– Microwire compatible

– Multiple-master, single-master, and slave modes

— Up to eight TDM interfaces (four on the MPC8270)

– Supports two groups of four TDM channels for a total of eight TDMs (one group of four on the

MPC8270 and the MPC8275)

– 2,048 bytes of SI RAM

– Bit or byte resolution

– Independent transmit and receive routing, frame synchronization

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

6

Freescale Semiconductor

Operating Conditions

– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary

rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM

serial interfaces

— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs,

SMCs, and serial channels

— Four independent 16-bit timers that can be interconnected as two 32-bit timers

•

Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only).Supported by eight transfer transmission

convergence (TC) layers between the TDMs and FCC2.

Transmission convergence (TC) layer (MPC8280 only)

2 Operating Conditions

Table 3 shows the maximum electrical ratings.

Table 3. Absolute Maximum Ratings ¹

Rating

Symbol

Value

Unit

Core supply voltage ²

PLL supply voltage²

I/O supply voltage ³

Input voltage ⁴

VDD

VCCSYN

VDDH

VIN

-0.3 – 2.25

-0.3 – 4.0

V

GND(-0.3) – 3.6

120

V

Junction temperature

Storage temperature range

T_j

°C

T_STG

(-55) – (+150)

1

Absolute maximum ratings are stress ratings only; functional operation (see Table 4) at the maximums is not

guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.

2

Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V during normal operation. It is recommended

that VDD/VCCSYN should be raised before or simultaneous with VDDH during power-on reset. VDD/VCCSYN may

exceed VDDH by more than 0.4 V during power-on reset for no more than 100 ms.

3

4

Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH

should not exceed VDD/VCCSYN by more than 2.5 V during normal operation.

Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.

Table 4 lists recommended operational voltage conditions.

Table 4. Recommended Operating Conditions ¹

Rating

Symbol

Value

Unit

Core supply voltage

PLL supply voltage

I/O supply voltage

VDD

VCCSYN

VDDH

VIN

1.45 – 1.60

3.135 – 3.465

GND (-0.3) – 3.465

105 ²

V

Input voltage

V

Junction temperature (maximum)

Ambient temperature

T_j

°C

T_A

0–70²

1

Caution: These are the recommended and tested operating conditions. Proper operation outside of these conditions

is not guaranteed.

2

Note that for extended temperature parts the range is (-40)_T– 105_T.

j

A

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

7

DC Electrical Characteristics

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is

advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages

to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic

voltage level (either GND or V ).

CC

Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the MPC8280.

Note that in PCI mode the I/O interface is different.

4 V

GV_DD+ 5%

V_IH

GV_DD

GND

GND – 0.3 V

V_IL

GND – 1.0 V

Not to exceed 10%

of t_{SDRAM_CLK}

Figure 2. Overshoot/Undershoot Voltage

3 DC Electrical Characteristics

Table 5 shows DC electrical characteristics.

Table 5. DC Electrical Characteristics ¹

Characteristic

Symbol

Min

Max

Unit

Input high voltage—

V_IH

2.0

3.465

V

all inputs except TCK, TRST and PORESET ²

Input low voltage

V_IL

V_IHC

V_ILC

I_IN

GND

2.4

GND

—

0.8

3.465

0.4

10

V

CLKIN input high voltage

CLKIN input low voltage

V

Input leakage current, V_IN= VDDH ³

Hi-Z (off state) leakage current, V_IN= VDDH³

Signal low input current, V_IL= 0.8 V ⁴

Signal high input current, V_IH= 2.0 V

µA

V

I_OZ

I_L

—

10

—

1

I_H

—

1

Output high voltage, I_OH= –2 mA

V_OH

2.4

—

except UTOPIA mode, and open drain pins

In UTOPIA mode ⁵(UTOPIA pins only): I_OH= -8.0mA

PA[0-31]

PB[4-31]

PC[0-31]

PD[4-31]

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

8

Freescale Semiconductor

DC Electrical Characteristics

Table 5. DC Electrical Characteristics ¹(continued)

Characteristic

Symbol

Min

Max

Unit

In UTOPIA mode⁵(UTOPIA pins only): I_OL= 8.0mA

V_OL

—

0.5

V

PA[0-31]

PB[4-31]

PC[0-31]

PD[4-31]

I_OL= 6.0mA

V

—

0.4

V

OL

BR

BG

ABB/IRQ2

TS

A[0-31]

TT[0-4]

TBST

TSIZE[0–3]

AACK

ARTRY

DBG

DBB/IRQ3

D[0-63]

DP(0)/RSRV/EXT_BR2

DP(1)/IRQ1/EXT_BG2

DP(2)/TLBISYNC/IRQ2/EXT_DBG2

DP(3)/IRQ3/EXT_BR3/CKSTP_OUT

DP(4)/IRQ4/EXT_BG3/CORE_SREST

DP(5)/TBEN/EXT_DBG3/IRQ5/CINT

DP(6)/CSE(0)/IRQ6

DP(7)/CSE(1)/IRQ7

PSDVAL

TA

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

L2_HIT/IRQ4

CPU_BG/BADDR31/IRQ5/CINT

CPU_DBG

CPU_BR

IRQ0/NMI_OUT

IRQ7/INT_OUT/APE

PORESET

HRESET

SRESET

RSTCONF

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

9

DC Electrical Characteristics

Table 5. DC Electrical Characteristics ¹(continued)

Characteristic

Symbol

Min

Max

Unit

I

= 5.3mA

CS[0-9]

V

—

0.4

V

OL

CS(10)/BCTL1

CS(11)/AP(0)

BADDR[27–28]

ALE

BCTL0

PWE[0–7]/PSDDQM[0–7]/PBS[0–7]

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

PSDAMUX/PGPL5

LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3]

LSDA10/LGPL0/PCI_MODCKH0

LSDWE/LGPL1/PCI_MODCKH1

LOE/LSDRAS/LGPL2/PCI_MODCKH2

LSDCAS/LGPL3/PCI_MODCKH3

LGTA/LUPMWAIT/LGPL4/LPBS

LSDAMUX/LGPL5/PCI_MODCK

LWR

MODCK[1–3]/AP[1–3]/TC[0–2]/BNKSEL[0–2]

I

= 3.2mA

OL

L_A14/PAR

L_A15/FRAME/SMI

L_A16/TRDY

L_A17/IRDY/CKSTP_OUT

L_A18/STOP

L_A19/DEVSEL

L_A20/IDSEL

L_A21/PERR

L_A22/SERR

L_A23/REQ0

L_A24/REQ1/HSEJSW

L_A25/GNT0

L_A26/GNT1/HSLED

L_A27/GNT2/HSENUM

L_A28/RST/CORE_SRESET

L_A29/INTA

L_A30/REQ2

L_A31

LCL_D[0-31]/AD[0-31]

LCL_DP[0-3]/C/BE[0-3]

PA[0–31]

PB[4–31]

PC[0–31]

PD[4–31]

TDO

QREQ

1

2

The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive

DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.

TCK, TRST and PORESET have min VIH = 2.5V.

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

10

Freescale Semiconductor

Thermal Characteristics

3

4

The leakage current is measured for nominal VDDH,VCCSYN, and VDD.

V_ILfor IIC interface does not match IIC standard, but does meet IIC standard for V_OLand should not cause any

compatibility issue.

5

MPC8280, MPC8275VR, MPC8275ZQ only.

4 Thermal Characteristics

Table 6 describes thermal characteristics for both the packages. See Table 2 for information about a given device’s

package. For the discussions sections 4.1 and 4.5, P = (V × I ) + PI/O, where PI/O is the power dissipation of

D

DD

the I/O drivers.

Table 6. Thermal Characteristics

Value

Characteristic

Symbol

Unit

Air Flow

480 TBGA

516 PBGA

Junction to ambient—

single-layer board ¹

16

11

12

9

27

21

19

16

11

8

Natural convection

R_θJA

°C/W

1 m/s

Junction to ambient—

four-layer board

Natural convection

R_θJA

1 m/s

—

Junction to board ²

R_θJB

R_θJC

Ψ_JT

6

°C/W

Junction to case ³

2

—

Junction-to-package top ⁴

2

—

1

2

Assumes no thermal vias.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

3

4

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is

written as Psi-JT.

4.1 Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, T_J, in C can be obtained from the following equation:

T = T + (R

× P )

D

J

A

θJA

where:

T = ambient temperature (ºC)

A

R

= package junction-to-ambient thermal resistance (ºC/W)

θJA

P = power dissipation in package

D

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation

of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor

of two (in the quantity T – T ) are possible.

J

A

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

11

Thermal Characteristics

4.2 Estimation with Junction-to-Case Thermal Resistance

Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance

and a case-to-ambient thermal resistance:

R

= R

+ R

θJC θCA

θJA

where:

R

= junction-to-ambient thermal resistance (ºC/W)

= junction-to-case thermal resistance (ºC/W)

= case-to-ambient thermal resistance (ºC/W)

θJA

θJC

θCA

R

is device related and cannot be influenced by the user. The user adjusts the thermal environment to affect the

θJC

case-to-ambient thermal resistance, R

. For instance, the user can change the air flow around the device, add a

θCA

heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the

printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks

where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most

packages, a better model is required.

4.3 Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two-resistor model

consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case thermal resistance

covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the

package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is

conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages,

especially PBGA packages, is strongly dependent on the board temperature.

If the board temperature is known, an estimate of the junction temperature in the environment can be made using

the following equation:

T = T + (R

× P )

D

J

B

θJB

where:

R

= junction-to-board thermal resistance (ºC/W)

θJB

T = board temperature (ºC)

B

P = power dissipation in package

D

If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable

predictions of junction temperature can be made. For this method to work, the board and board mounting must be

similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a

power and a ground plane) and by attaching the thermal balls to the ground plane.

4.4 Estimation Using Simulation

When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor

model can be used with the thermal simulation of the application, or a more accurate and complex model of the

package can be used in the thermal simulation.

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

12

Freescale Semiconductor

Power Dissipation

4.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal

characterization parameter (Ψ ) can be used to determine the junction temperature with a measurement of the

JT

temperature at the top center of the package case using the following equation:

T = T + (Ψ × P )

J

T

JT

D

where:

Ψ

= thermal characterization parameter

JT

T = thermocouple temperature on top of package

T

P = power dissipation in package

D

The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the

thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and

over 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the case to avoid

measurement errors caused by cooling effects of the thermocouple wire.

4.6 Layout Practices

Each VDD and VDDH pin should be provided with a low-impedance path to the board’s power supplies. Each

ground pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct

groups of logic on chip. The VDD and VDDH power supplies should be bypassed to ground using by-pass

capacitors located as close as possible to the four sides of the package. For filtering high frequency noise, a capacitor

of 0.1uF on each VDD and VDDH pin is recommended. Further, for medium frequency noise, a total of 2 capacitors

of 47uF for VDD and 2 capacitors of 47uF for VDDH are also recommnded. The capacitor leads and associated

printed circuit traces connecting to chip VDD, VDDH and ground should be kept to less than half an inch per

capacitor lead. Boards should employ separate inner layers for power and GND planes.

All output pins on the MPC8280 have fast rise and fall times. Printed circuit (PC) trace interconnection length should

be minimized to minimize overdamped conditions and reflections caused by these fast output switching times. This

recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are

recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the

PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher

capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all

unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels

on the PLL supply pins.

5 Power Dissipation

Table 7 provides preliminary, estimated power dissipation for various configurations. Note that suitable thermal

management is required to ensure the junction temperature does not exceed the maximum specified value. Also note

that the I/O power should be included when determining whether to use a heat sink. For a complete list of possible

clock configurations, refer to Section 7, “Clock Configuration Modes.”

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

13

AC Electrical Characteristics

Table 7. Estimated Power Dissipation for Various Configurations ¹

P_INT(W)

Vddl 1.5 Volts

2, 3

CPM

Multiplication

Factor

CPU

Multiplication

Factor

Bus

(MHz)

CPM

(MHz)

CPU

(MHz)

Nominal

Maximum

66.67

83.33

100

2.5

3

166

200

233

250

292

300

3.5

4

233

266

300

333

375

417

400

450

0.95

1.0

1.05

1.1

4

1.05

1.25

1.3

3.5

3

4.5

4

1.15

1.35

1.4

3

4.5

5

3.5

3

1.45

1.5

1.55

1.6

4

100

3

4.5

1.55

1.65

1

2

3

Test temperature = 105° C

P_INT= I_DDx V_DDWatts

Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:

66.7 MHz = 0.45 W (nominal), 0.5 W (maximum)

83.3 MHz = 0.5W (nominal), 0.6 W (maximum)

100 MHz = 0.6 W (nominal), 0.7 W (maximum)

6 AC Electrical Characteristics

The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for

66.67/83.33/100 MHz devices. Note that AC timings are based on a 50-pf load for MAX Delay and 10-pf load for

MIN delay. Typical output buffer impedances are shown in Table 8.

Table 8. Output Buffer Impedances ¹

Output Buffers

Typical Impedance (Ω)

60x bus

45 or 27 ²

Local bus

Memory controller

Parallel I/O

PCI

45

45 or 27²

45

27

1

2

These are typical values at 65° C. Impedance may vary by 25% with process and temperature.

On silicon revision 0.0 (mask #: 0K49M), selectable impedance is not available. Impedance is set at 45 Ω.

On all other revisions, impedance value is selected through the SIUMCR[20,21]. Refer to the MPC8280

PowerQUICC II Family Reference Manual.

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

14

Freescale Semiconductor

AC Electrical Characteristics

6.1 CPM AC Characteristics

Table 9 lists CPM output characteristics.

Table 9. AC Characteristics for CPM Outputs ¹

Spec Number

Max Min

Characteristic Value (ns)

Maximum Delay

Minimum Delay

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp36a sp37a FCC outputs—internal clock (NMSI)

sp36b sp37b FCC outputs—external clock (NMSI)

6

8

5.5

8

5.5

8

0.5

2

0.5

2

0.5

2

sp38a sp39a SCC/SMC/SPI/I2C outputs—internal

clock (NMSI)

10

0

sp38b sp39b SCC/SMC/SPI/I2C outputs—external

clock (NMSI)

8

2

sp40 sp41 TDM outputs/SI

sp42 sp43 TIMER/IDMA outputs

sp42a sp43a PIO outputs

11

2.5

0.5

2.5

0.5

2.5

0.5

1

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

Table 10 lists CPM input characteristics.

NOTE: Rise/Fall Time on CPM Input Pins

It is recommended that the rise/fall time on CPM input pins should not exceed 5 ns.

This should be enforced especially on clock signals. Rise time refers to signal

transitions from 10% to 90% of VCC; fall time refers to transitions from 90% to

10% of VCC.

Table 10. AC Characteristics for CPM Inputs ¹

Spec Number

Setup Hold

Value (ns)

Characteristic

Setup

Hold

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp16a sp17a FCC inputs—internal clock (NMSI)

sp16b sp17b FCC inputs—external clock (NMSI)

6

2.5

6

2.5

6

2.5

6

0

2

0

2

0

2

0

sp18a sp19a SCC/SMC/SPI/I2C inputs—internal

clock (NMSI)

sp18b sp19b SCC/SMC/SPI/I2C inputs—external

clock (NMSI)

4

2

sp20 sp21 TDM inputs/SI

5

8

5

8

5

8

2.5

0.5

2.5

0.5

2.5

0.5

sp22 sp23 PIO/TIMER/IDMA inputs

1

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.

Timings are measured at the pin.

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

15

AC Electrical Characteristics

NOTE

Although the specifications generally reference the rising edge of the clock, the

following AC timing diagrams also apply when the falling edge is the active edge.

Figure 3 shows the FCC internal clock.

BRG_OUT

sp17a

sp16a

FCC input signals

FCC output signals

sp36a/sp37a

Note: When GFMR[TCI] = 0

sp36a/sp37a

FCC output signals

Note: When GFMR.[TCI] = 1

Figure 3. FCC Internal Clock Diagram

Figure 4 shows the FCC external clock.

Serial ClKin

sp17b

sp16b

FCC input signals

sp36b/sp37b

FCC output signals

Note: When GFMR[TCI] = 0

sp36b/sp37b

FCC output signals

Note: When GFMR[TCI] = 1

Figure 4. FCC External Clock Diagram

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

16

Freescale Semiconductor

AC Electrical Characteristics

2

Figure 5 shows the SCC/SMC/SPI/I C external clock.

Serial CLKin

sp19b

sp18b

SCC/SMC/SPI/I2C input signals

(See note)

sp38b/sp39b

SCC/SMC/SPI/I2C output signals

(See note)

Note: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

Figure 5. SCC/SMC/SPI/I²C External Clock Diagram

2

Figure 6 shows the SCC/SMC/SPI/I C internal clock.

BRG_OUT

sp19a

sp18a

SCC/SMC/SPI/I2C input signals

(See note)

sp38a/sp39a

SCC/SMC/SPI/I2C output signals

(See note)

Note: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

Figure 6. SCC/SMC/SPI/I²C Internal Clock Diagram

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

17

AC Electrical Characteristics

Figure 7 shows TDM input and output signals.

Serial CLKin

sp20

sp21

TDM input signals

sp40/sp41

TDM output signals

Note: There are four possible TDM timing conditions:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

Figure 7. TDM Signal Diagram

Figure 8 shows PIO and timer signals.

Sys clk

sp23

sp22

PIO/IDMA/TIMER[TGATE assertion] input signals

(See note)

sp23

sp22

TIMER input signal [TGATE deassertion]

(See note)

sp42/sp43

IDMA output signals

sp42/sp43

sp42a/sp43a

TIMER(sp42/43)/ PIO(sp42a/sp43a)

output signals

Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.

Figure 8. PIO and Timer Signal Diagram

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

18

Freescale Semiconductor

AC Electrical Characteristics

6.2 SIU AC Characteristics

NOTE: CLKIN Jitter and Duty Cycle

The CLKIN input to the MPC8280 should not exceed +/– 150 psec of jitter

(peak-to-peak). This represents total input jitter—the combination of short term

(cycle-to-cycle) and long term (cumulative). The duty cycle of CLKIN should not

exceed the ratio of 40:60. The rise/file time of CLKIN should adhere to the typical

SDRAM device AC clock requirement of 1 V/ns to meet SDRAM AC specs.

NOTE: Spread Spectrum Clocking

Spread spectrum clocking is allowed with 1% input frequency down-spread at

maximum 60 KHz modulation rate regardless of input frequency.

NOTE: PCI AC Timing

The MPC8280 meets the timing requirements of PCI Specification Revision 2.2.

Refer to Sections 7.2 and 7.3 and “Note: Tval (Output Hold)” to determine if a

specific clock configuration is compliant.

Table 11 lists SIU input characteristics.

Table 11. AC Characteristics for SIU Inputs ¹

Spec Number

Setup Hold

Value (ns)

Characteristic

Setup

Hold

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp11 sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/

TEA

6

5

3.5

0.5

sp12 sp10 Data bus in normal mode

5

7

4

5

3.5

0.5

sp13 sp10 Data bus in ECC and PARITY modes

sp13a sp10 Pipeline mode—Data bus (with or

without ECC/PARITY)

5

7

4

5

4

2.5

3.5

2.5

3.5

0.5

—

0.5

sp14 sp10 DP pins

sp14a sp10 Pipeline mode—DP pins

sp15 sp10 All other pins

—

5

0.5

1

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.

Timings are measured at the pin.

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

19

AC Electrical Characteristics

Table 12 lists SIU output characteristics.

Table 12. AC Characteristics for SIU Outputs ¹

Spec Number

Max Min

Value (ns)

Characteristic

Maximum Delay

Minimum Delay

66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz

sp31 sp30 PSDVAL/TEA/TA

sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT

sp33a sp30 Data bus ²

7

8

6

5.5

7

1

6.5

5.5

7

6.5

6

0.7

1

0.7

1

0.7

1

sp33b sp30 DP

sp34 sp30 Memory controller signals/ALE

sp35 sp30 All other signals

sp35a sp30 AP

6

1

6

1

7

1

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2

To achieve 1 ns of hold time at 66, 83, or 100 MHz, a minimum loading of 20 pF is required.

NOTE

Activating data pipelining (setting BRx[DR] in the memory controller) improves

the AC timing.

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

20

Freescale Semiconductor

AC Electrical Characteristics

Figure 9 shows the interaction of several bus signals.

CLKin

sp10

sp11

AACK/TA/TS/

DBG/BG/BR input signals

sp10

sp11a

ARTRY/TEA input signals

sp12

DATA bus normal mode

input signal

sp10

sp15

All other input signals

sp30

sp31

PSDVAL/TEA/TA output signals

sp32

sp30

ADD/ADD_atr/BADDR/CI/

GBL/WT output signals

sp33a

DATA bus output signals

sp35

All other output signals

sp35a

(except AP)

sp30

AP signals

Figure 9. Bus Signals

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

21

AC Electrical Characteristics

Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).

CLKin

sp10

sp13

DATA bus, ECC, and PARITY mode

input signals

sp10

sp13a

Pipeline mode—

DATA bus, ECC, and PARITY mode

input signals

sp10

sp14

DP mode input signal

sp14a

Pipeline mode—

DP mode input signal

sp33b

sp30

DP mode output signal

Figure 10. Parity Mode Diagram

Figure 11 shows signal behavior in MEMC mode.

CLKin

V_CLK

sp34/sp30

Memory controller signals

Figure 11. MEMC Mode Diagram

NOTE

Generally, all MPC8280 bus and system output signals are driven from the rising

edge of the input clock (CLKin). Memory controller signals, however, trigger on

four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1,

T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of

CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio

selected, as shown in Table 13.

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

22

Freescale Semiconductor

AC Electrical Characteristics

Table 13. Tick Spacing for Memory Controller Signals

Tick Spacing (T1 Occurs at the Rising Edge of CLKin)

T2 T3 T4

1/4 CLKin 1/2 CLKin 3/4 CLKin

PLL Clock Ratio

1:2, 1:3, 1:4, 1:5, 1:6

1:2.5

1:3.5

3/10 CLKin

4/14 CLKin

1/2 CLKin

8/10 CLKin

11/14 CLKin

Figure 12 is a representation of the information in Table 13.

CLKin

for 1:2, 1:3, 1:4, 1:5, 1:6

T1

T2

T3

T4

CLKin

for 1:2.5

T2

T4

for 1:3.5

T2

T4

Figure 12. Internal Tick Spacing for Memory Controller Signals

NOTE

The UPM machine outputs change on the internal tick determined by the memory

controller programming; the AC specifications are relative to the internal tick. Note

that SDRAM and GPCM machine outputs change on CLKin’s rising edge.

6.3 JTAG Timings

Table 14 lists the JTAG timings.

Table 14. JTAG Timings¹

Symbol²

Parameter

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

f_JTG

t_JTG

0

30

15

0

33.3

—

MHz

ns

JTAG external clock pulse width measured at 1.4V

JTAG external clock rise and fall times

t_JTKHKL

—

ns

6

t_JTGRand

t_JTGF

5

ns

3

6

TRST assert time

Input setup times

t_TRST

25

—

ns

,

4

7

t_JTDVKH

t_JTIVKH

4

—

ns

,

Boundary-scan data

TMS, TDI

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

23

Clock Configuration Modes

Table 14. JTAG Timings¹(continued)

Parameter

Symbol²

Min

Max

Unit

Notes

Input hold times

Output valid times

Output hold times

4

7

t_JTDXKH

t_JTIXKH

10

—

ns

,

Boundary-scan data

TMS, TDI

5

7

t_JTKLDV

t_JTKLOV

—

10

ns

,

.

Boundary-scan data

TDO

5

7

t_JTKLDX

t_JTKLOX

1

—

ns

,

Boundary-scan data

TDO

JTAG external clock to output high impedance

Boundary-scan data

TDO

5

6

t_JTKLDZ

t_JTKLOZ

1

10

ns

,

1

All outputs are measured from the midpoint voltage of the falling/rising edge of t_TCLKto the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load.

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2

The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t(_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example,

t

_JTDVKHsymbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state

(V) relative to the t_JTGclock reference (K) going to the high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG

timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t_JTGclock reference (K)

going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters

representing the clock of a particular functional. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall).

3

4

5

6

7

TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

Non-JTAG signal input timing with respect to t_TCLK

.

Non-JTAG signal output timing with respect to t_TCLK

Guaranteed by design.

.

Guaranteed by design and device characterization.

7 Clock Configuration Modes

The MPC8280 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set according to three

input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 15.

Table 15. MPC8280 Clocking Modes

Pins

PCI Clock

Frequency Range

(MHZ)

Clocking Mode

Reference

PCI_MODE PCI_CFG[0] PCI_MODCK¹

1

0

—

0

—

0

Local bus

PCI host

—

Table 16

Table 17

Table 18

Table 19

Table 20

50–66

25–50

50–66

25–50

0

1

0

PCI agent

1

Determines PCI clock frequency range. Refer to Sections 7.2 and 7.3.

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

24

Freescale Semiconductor

Clock Configuration Modes

In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits during

the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from hardware configuration

word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selected MPC8280 clock

operation mode as described in the following sections.

7.1 Local Bus Mode

Table 16 lists clock configurations for the MPC8280 in local bus mode. The frequencies listed are for the purpose

of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not

exceed the frequency rating of the user’s device.

NOTE

Clock configurations change only after PORESET is asserted.

Table 16. Clock Configurations for Local Bus Mode ¹

Bus Clock ³

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Mode ²

CPM

CPU

Multiplication

Factor ⁴

Factor ⁵

MODCK_H-MODCK[1-3] Low

High

Low

High

Low

High

Default Modes (MODCK_H= 0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

37.5

33.3

37.5

30.0

60.0

50.0

60.0

50.0

133.3

100.0

167.0

160.0

3

112.5

100.0

150.0

120.0

100.0

150.0

125.0

400.0

334.0

400.0

4

5

150.0

166.7

150.0

533.3

666.7

400.0

500.0

417.5

501.0

400.0

480.0

4

5

2

2.5

3

2

2.5

3

Full Configuration Modes

0001_000

0001_001

0001_010

0001_011

0001_100

50.0

167.0

145.8

2

100.0

334.0

291.7

4

5

6

200.0

250.0

300.0

668.0

835.0

875.0

Reserved

0001_101

0001_110

1000_111

0001_111

0010_000

0010_001

37.5

33.3

133.3

3

112.5

400.0

4

5

150.0

166.7

183.3

200.0

533.3

666.7

733.3

800.0

100.0

5.5

6

Reserved

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

25

Clock Configuration Modes

Mode ²

Table 16. Clock Configurations for Local Bus Mode ¹(continued)

Bus Clock ³

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

CPM

CPU

Multiplication

Factor ⁴

Factor ⁵

MODCK_H-MODCK[1-3] Low

High

Low

High

Low

High

0010_010

0010_011

0010_100

0010_101

0010_110

37.5

30.0

25.0

100.0

4

150.0

120.0

100.0

400.0

4

5

6

7

8

150.0

175.0

200.0

400.0

500.0

600.0

700.0

800.0

0010_111

0011_000

0011_001

0011_010

0011_011

Reserved

30.0

25.0

80.0

5

150.0

125.0

400.0

5

6

7

8

150.0

175.0

200.0

400.0

480.0

560.0

640.0

0011_100

0011_101

0011_110

0011_111

0100_000

Reserved

25.0

66.7

6

150.0

400.0

6

7

8

150.0

175.0

200.0

400.0

466.7

533.3

150.0

0101_101

0101_110

0101_111

0110_000

0110_001

0110_010

75.0

60.0

50.0

167.0

2

150.0

120.0

100.0

334.0

2

2.5

3

166.7

200.0

250.0

334.0

417.5

501.0

584.5

668.0

751.5

3.5

4

4.5

0110_011

0110_100

0110_101

0110_110

0110_111

0111_000

Reserved

60.0

50.0

42.9

40.0

160.0

2.5

150.0

125.0

107.1

100.0

400.0

2.5

3

150.0

160.0

180.0

400.0

480.0

560.0

640.0

720.0

3.5

4

4.5

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

26

Freescale Semiconductor

Clock Configuration Modes

Table 16. Clock Configurations for Local Bus Mode ¹(continued)

Bus Clock ³

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Mode ²

CPM

CPU

Multiplication

Factor ⁴

Factor ⁵

MODCK_H-MODCK[1-3] Low

High

Low

High

Low

High

0111_001

0111_010

Reserved

0111_011

0111_100

0111_101

0111_110

0111_111

50.0

42.9

37.5

33.3

133.3

3

150.0

400.0

3

150.0

400.0

466.7

533.3

600.0

128.6

112.5

100.0

3.5

4

4.5

Reserved

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

1000_110

Reserved

42.9

37.5

33.3

30.0

28.6

114.3

3.5

150.0

400.0

3.5

4

150.0

400.0

457.1

514.3

571.4

628.6

131.3

116.7

105.0

100.0

4.5

5

5.5

1100_000

1100_001

1100_010

Reserved

1101_000

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a

table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose

of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not

violate the frequency rating of the user’s device. The minimum CPM frequency is 120 MHz. Minimum CPU frequency

is determined by the clock mode. For modes with a CPU multiplication factor <= 3, the minimum CPU frequency is

150 MHz for commercial temperature devices and 175 MHz for extended temperature devices. For modes with a CPU

multiplication factor >= 3.5: for Rev0.1 the minimum CPU frequency is 250 MHz; for RevA or later the minimum CPU

frequency is 150 MHz for commercial temperature devices and 175 MHz for extended temperature devices.

2

3

4

5

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

60x and local bus frequency. Identical to CLKIN.

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

27

Clock Configuration Modes

7.2 PCI Host Mode

Table 17 and Table 18 show clock configurations for PCI host mode. The frequencies listed are for the purpose of

illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not

exceed the frequency rating of the user’s device. In addition, note the following:

NOTE: PCI_MODCK

In PCI mode only, PCI_MODCK comes from the LGPL5 pin and

MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.

NOTE: Tval (Output Hold)

The minimum Tval = 2 ns when PCI_MODCK = 1, and the minimum Tval = 1 ns

when PCI_MODCK = 0. Therefore, designers should use clock configurations that

fit this condition to achieve PCI-compliant AC timing.

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0) ^{1, 2}

Bus Clock ⁴

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

Mode ³

CPM

CPU

PCI

Division

Factor

Multiplication

Factor ⁵

Factor ⁶

MODCK_H-

MODCK[1-3]

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

60.0 66.7

50.0 66.7

60.0 80.0

50.0 66.7

2

120.0 133.3

100.0 133.3

150.0 200.0

2.5

3

150.0 166.7

150.0 200.0

180.0 240.0

210.0 280.0

240.0 320.0

150.0 200.0

175.0 233.3

200.0 266.6

2

3

60.0 66.7

50.0 66.7

2.5

3

3.5

4

3

3.5

3

3.5

4

Full Configuration Modes

0001_000

0001_001

0001_010

0001_011

50.0 66.7

3

150.0 200.0

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

3

50.0 66.7

0010_000

0010_001

0010_010

0010_011

50.0 66.7

4

200.0 266.6

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

4

50.0 66.7

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

28

Freescale Semiconductor

Clock Configuration Modes

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0) ^{1, 2}(continued)

Bus Clock ⁴

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

Mode ³

CPM

CPU

PCI

Division

Factor

Multiplication

Factor ⁵

Factor ⁶

MODCK_H-

MODCK[1-3]

Low High

0010_100

0010_101

0010_110

75.0 100.0

4

300.0 400.0

5

5.5

6

375.0 500.0

412.5 549.9

450.0 599.9

6

50.0 66.7

0011_000

0011_001

0011_010

0011_011

50.0 66.7

5

250.0 333.3

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

5

50.0 66.7

0100_000

0100_001

0100_010

0100_011

Reserved

50.0 66.7

6

300.0 400.0

6

7

8

300.0 400.0

350.0 466.6

400.0 533.3

6

50.0 66.7

0101_000

0101_001

0101_010

0101_011

0101_100

60.0 66.7

50.0 66.7

2

120.0 133.3

100.0 133.3

2.5

3

150.0 166.7

150.0 200.0

175.0 233.3

200.0 266.6

225.0 300.0

2

60.0 66.7

50.0 66.7

3.5

4

4.5

0110_000

0110_001

0110_010

0110_011

0110_100

0110_101

0110_110

60.0 80.0

2.5

150.0 200.0

2.5

3

150.0 200.0

180.0 240.0

210.0 280.0

240.0 320.0

270.0 360.0

300.0 400.0

360.0 480.0

3

50.0 66.7

3.5

4

4.5

5

6

0111_000

0111_001

0111_010

0111_011

Reserved

50.0 66.7

3

150.0 200.0

3

3.5

4

150.0 200.0

175.0 233.3

200.0 266.6

3

50.0 66.7

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

29

Clock Configuration Modes

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0) ^{1, 2}(continued)

Bus Clock ⁴

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

Mode ³

CPM

CPU

PCI

(MHz)

Multiplication

Division

Factor

Factor ⁵

Factor ⁶

MODCK_H-

MODCK[1-3]

Low High

0111_100

50.0 66.7

3

150.0 200.0

4.5

225.0 300.0

3

50.0 66.7

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

1000_110

Reserved

66.7 88.9

3

200.0 266.6

3

3.5

4

200.0 266.6

233.3 311.1

266.7 355.5

300.0 400.0

400.0 533.3

433.3 577.7

4

50.0 66.7

4.5

6

6.5

1001_000

1001_001

1001_010

1001_011

1001_100

Reserved

57.1 76.2

3.5

200.0 266.6

3.5

4

200.0 266.6

228.6 304.7

257.1 342.8

4

50.0 66.7

4.5

1001_101

1001_110

1001_111

85.7 114.3

3.5

300.0 400.0

5

5.5

6

428.6 571.4

471.4 628.5

514.3 685.6

6

50.0 66.7

1010_000

1010_001

1010_010

1010_011

1010_100

75.0 100.0

2

150.0 200.0

2

2.5

3

150.0 200.0

187.5 250.0

225.0 300.0

262.5 350.0

300.0 400.0

3

50.0 66.7

3.5

4

1011_000

1011_001

1011_010

1011_011

1011_100

1011_101

Reserved

80.0 106.7

2.5

200.0 266.6

2.5

3

200.0 266.6

240.0 320.0

280.0 373.3

320.0 426.6

360.0 480.0

4

50.0 66.7

3.5

4

4.5

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

30

Freescale Semiconductor

Clock Configuration Modes

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0) ^{1, 2}(continued)

Bus Clock ⁴

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

Mode ³

CPM

CPU

PCI

Division

Factor

Multiplication

Factor ⁵

Factor ⁶

MODCK_H-

MODCK[1-3]

Low High

1101_000

1101_001

1101_010

1101_011

1101_100

100.0 133.3

2.5

250.0 333.3

3

3.5

4

300.0 400.0

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

5

50.0 66.7

4.5

5

1101_101

1101_110

125.0 166.7

2

250.0 333.3

3

4

375.0 500.0

500.0 666.6

5

50.0 66.7

1110_000

1110_001

1110_010

1110_011

1110_100

100.0 133.3

3

300.0 400.0

3.5

4

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

6

50.0 66.7

4.5

5

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table

entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of

illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not violate

the frequency rating of the user’s device. The minimum CPM frequency is 120 MHz. Minimum CPU frequency is

determined by the clock mode. For modes with a CPU multiplication factor <= 3, the minimum CPU frequency is 150

MHz for commercial temperature devices and 175 MHz for extended temperature devices. For modes with a CPU

multiplication factor >= 3.5: for Rev0.1 the minimum CPU frequency is 250 MHz; for RevA or later the minimum CPU

frequency is 150 MHz for commercial temperature devices and 175 MHz for extended temperature devices.

2

3

4

5

6

As Table 15 shows, PCI_MODCK determines the PCI clock frequency range. Refer to Table 18 for lower configurations.

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

60x and local bus frequency. Identical to CLKIN.

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

31

Clock Configuration Modes

Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1) ^{1, 2}

Bus Clock ⁴

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

Mode ³

CPM

CPU

PCI

Division

Factor

Multiplication

Factor ⁵

Factor ⁶

MODCK_H-

MODCK[1-3]

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

60.0 100.0

50.0 100.0

60.0 120.0

50.0 100.0

2

120.0 200.0

100.0 200.0

150.0 300.0

2.5

3

150.0 250.0

150.0 300.0

180.0 360.0

210.0 420.0

240.0 480.0

150.0 300.0

175.0 350.0

200.0 400.0

4

6

30.0 50.0

25.0 50.0

2.5

3

3.5

4

3

3.5

4

3

Full Configuration Modes

0001_000

0001_001

0001_010

0001_011

50.0 100.0

3

150.0 300.0

5

6

7

8

250.0 500.0

300.0 600.0

350.0 700.0

400.0 800.0

6

25.0 50.0

0010_000

0010_001

0010_010

0010_011

50.0 100.0

4

200.0 400.0

5

6

7

8

250.0 500.0

300.0 600.0

350.0 700.0

400.0 800.0

8

25.0 50.0

0010_100

0010_101

0010_110

37.5 75.0

4

150.0 300.0

5

5.5

6

187.5 375.0

206.3 412.5

225.0 450.0

6

25.0 50.0

0011_000

0011_001

0011_010

0011_011

30.0 50.0

25.0 50.0

5

150.0 250.0

125.0 250.0

5

6

7

8

150.0 250.0

150.0 300.0

175.0 350.0

200.0 400.0

5

30.0 50.0

25.0 50.0

0100_000

0100_001

0100_010

Reserved

25.0 50.0

6

150.0 300.0

6

7

150.0 300.0

175.0 350.0

6

25.0 50.0

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

32

Freescale Semiconductor

Clock Configuration Modes

Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1) ^{1, 2}(continued)

Bus Clock ⁴

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

Mode ³

CPM

CPU

PCI

Division

Factor

Multiplication

Factor ⁵

Factor ⁶

MODCK_H-

MODCK[1-3]

Low High

0100_011

25.0 50.0

6

150.0 300.0

8

200.0 400.0

6

25.0 50.0

0101_000

0101_001

0101_010

0101_011

0101_100

60.0 100.0

50.0 100.0

2

120.0 200.0

100.0 200.0

2.5

3

150.0 250.0

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

4

30.0 50.0

25.0 50.0

3.5

4

4.5

0110_000

0110_001

0110_010

0110_011

0110_100

0110_101

0110_110

60.0 120.0

2.5

150.0 300.0

2.5

3

150.0 300.0

180.0 360.0

210.0 420.0

240.0 480.0

270.0 540.0

300.0 600.0

360.0 720.0

6

25.0 50.0

3.5

4

4.5

5

6

0111_000

0111_001

0111_010

0111_011

0111_100

Reserved

50.0 100.0

3

150.0 300.0

3

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

6

25.0 50.0

3.5

4

4.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

1000_110

Reserved

66.7 133.3

3

200.0 400.0

3

3.5

4

200.0 400.0

233.3 466.7

266.7 533.3

300.0 600.0

400.0 800.0

433.3 866.7

8

25.0 50.0

4.5

6

6.5

1001_000

1001_001

Reserved

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

33

Clock Configuration Modes

Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1) ^{1, 2}(continued)

Bus Clock ⁴

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

Mode ³

CPM

CPU

PCI

Division

Factor

Multiplication

Factor ⁵

Factor ⁶

MODCK_H-

MODCK[1-3]

Low High

1001_010

1001_011

1001_100

57.1 114.3

3.5

200.0 400.0

3.5

4

200.0 400.0

228.6 457.1

257.1 514.3

8

25.0 50.0

4.5

1001_101

1001_110

1001_111

42.9 85.7

3.5

150.0 300.0

5

5.5

6

214.3 428.6

235.7 471.4

257.1 514.3

6

25.0 50.0

1010_000

1010_001

1010_010

1010_011

1010_100

75.0 150.0

2

150.0 300.0

2

2.5

3

150.0 300.0

187.5 375.0

225.0 450.0

262.5 525.0

300.0 600.0

6

25.0 50.0

3.5

4

1011_000

1011_001

1011_010

1011_011

1011_100

1011_101

Reserved

80.0 160.0

2.5

200.0 400.0

2.5

3

200.0 400.0

240.0 480.0

280.0 560.0

320.0 640.0

360.0 720.0

8

25.0 50.0

3.5

4

4.5

1101_000

1101_001

1101_010

1101_011

1101_100

50.0 100.0

2.5

125.0 250.0

3

3.5

4

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

250.0 500.0

5

25.0 50.0

4.5

5

1101_101

1101_110

62.5 125.0

2

125.0 250.0

3

4

187.5 375.0

250.0 500.0

5

25.0 50.0

1110_000

1110_001

50.0 100.0

3

150.0 300.0

3.5

4

175.0 350.0

200.0 400.0

6

25.0 50.0

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

34

Freescale Semiconductor

Clock Configuration Modes

Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1) ^{1, 2}(continued)

Bus Clock ⁴

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

Mode ³

CPM

CPU

PCI

Division

Factor

Multiplication

Factor ⁵

Factor ⁶

MODCK_H-

MODCK[1-3]

Low High

1110_010

1110_011

1110_100

50.0 100.0

3

150.0 300.0

4.5

5

225.0 450.0

250.0 500.0

275.0 550.0

6

25.0 50.0

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table

entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration

only. Users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency

rating of the user’s device. The minimum CPM frequency is 120 MHz. Minimum CPU frequency is determined by the clock

mode. For modes with a CPU multiplication factor <= 3, the minimum CPU frequency is 150 MHz for commercial

temperature devices and 175 MHz for extended temperature devices. For modes with a CPU multiplication factor >= 3.5:

for Rev0.1 the minimum CPU frequency is 250 MHz; for RevA or later the minimum CPU frequency is 150 MHz for

commercial temperature devices and 175 MHz for extended temperature devices.

2

3

4

5

6

As Table 15 shows, PCI_MODCK determines the PCI clock frequency range. Refer to Table 17 for higher configurations.

MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.

60x and local bus frequency. Identical to CLKIN.

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

7.3 PCI Agent Mode

Table 19 and Table 20 show configurations for PCI agent mode. The frequencies listed are for the purpose of

illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not

exceed the frequency rating of the user’s device. In addition, note the following:

NOTE: PCI_MODCK

In PCI mode only, PCI_MODCK comes from the LGPL5 pin and

MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.

NOTE: Tval (Output Hold)

The minimum Tval = 2 ns when PCI_MODCK = 1, and the minimum Tval = 1 ns

when PCI_MODCK = 0. Therefore, designers should use clock configurations that

fit this condition to achieve PCI-compliant AC timing.

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

35

Clock Configuration Modes

Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) ^{1, 2}

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

Mode ³

CPM

CPU

Bus

Division

Factor

Multiplication

Factor ⁴

Factor ⁵

MODCK_H-

MODCK[1-3]

Low High

Default Modes (MODCK_H=0000

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

60.0 66.7

50.0 66.7

2

3

4

120.0 133.3

100.0 133.3

150.0 200.0

200.0 266.6

2.5

3

150.0 166.7

150.0 200.0

200.0 266.6

180.0 240.0

210.0 280.0

233.3 311.1

240.0 320.0

2

60.0 66.7

50.0 66.7

60.0 80.0

66.7 88.9

80.0 106.7

3

4

3

2.5

3

3.5

3

2.5

Full Configuration Modes

0001_001

0001_010

0001_011

0001_100

60.0 66.7

50.0 66.7

2

120.0 133.3

100.0 133.3

5

6

7

8

150.0 166.7

150.0 200.0

175.0 233.3

200.0 266.6

4

30.0 33.3

25.0 33.3

0010_001

0010_010

0010_011

0010_100

50.0 66.7

3

150.0 200.0

3

180.0 240.0

210.0 280.0

240.0 320.0

270.0 360.0

2.5

60.0 80.0

3.5

4

4.5

0011_000

0011_001

0011_010

0011_011

0011_100

Reserved

0100_000

0100_001

0100_010

0100_011

0100_100

Reserved

50.0 66.7

3

150.0 200.0

3

150.0 200.0

175.0 200.0

200.0 266.6

225.0 300.0

3

50.0 66.7

3.5

4

4.5

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

36

Freescale Semiconductor

Clock Configuration Modes

Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) ^{1, 2}(continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

Mode ³

CPM

CPU

Bus

Division

Factor

Multiplication

Factor ⁴

Factor ⁵

MODCK_H-

MODCK[1-3]

Low High

0101_000

0101_001

0101_010

0101_011

0101_100

0101_101

0101_110

50.0 66.7

5

250.0 333.3

2.5

3

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

2.5

100.0 133.3

3.5

4

4.5

5

5.5

0110_000

0110_001

0110_010

0110_011

0110_100

Reserved

50.0 66.7

4

200.0 266.6

3

200.0 266.6

233.3 311.1

266.7 355.5

300.0 400.0

3

66.7 88.9

3.5

4

4.5

0111_000

0111_001

0111_010

0111_011

50.0 66.7

3

150.0 200.0

2

150.0 200.0

187.5 250.0

225.0 300.0

262.5 350.0

2

75.0 100.0

2.5

3

3.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

Reserved

50.0 66.7

3

150.0 200.0

2.5

3

150.0 166.7

180.0 240.0

210.0 280.0

240.0 320.0

270.0 360.0

2.5

60.0 80.0

3.5

4

4.5

1001_000

1001_001

1001_010

1001_011

1001_100

Reserved

4

50.0 66.7

4

200.0 266.6

225.0 300.0

4

50.0 66.7

4.5

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

37

Clock Configuration Modes

Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) ^{1, 2}(continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

Mode ³

CPM

CPU

Bus

Division

Factor

Multiplication

Factor ⁴

Factor ⁵

MODCK_H-

MODCK[1-3]

Low High

1010_000

1010_001

1010_010

1010_011

1010_100

Reserved

50.0 66.7

4

200.0 266.6

3

200.0 266.6

233.3 311.1

266.7 355.5

300.0 400.0

3

66.7 88.9

3.5

4

4.5

1011_000

1011_001

1011_010

1011_011

1011_100

Reserved

50.0 66.7

4

200.0 266.6

2.5

3

200.0 266.6

240.0 320.0

280.0 373.3

320.0 426.6

2.5

80.0 106.7

3.5

4

1100_101

1100_110

1100_111

1101_000

50.0 66.7

6

300.0 400.0

4

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

3

100.0 133.3

4.5

5

5.5

1101_001

1101_010

1101_011

1101_100

50.0 66.7

6

300.0 400.0

3.5

4

420.0 559.9

480.0 639.9

540.0 719.9

600.0 799.9

2.5

120.0 160.0

4.5

5

1110_000

1110_001

1110_010

1110_011

50.0 66.7

5

250.0 333.3

2.5

3

312.5 416.6

375.0 500.0

437.5 583.3

500.0 666.6

2

125.0 166.7

3.5

4

1110_100

1110_101

1110_110

1110_111

50.0 66.7

5

250.0 333.3

4

333.3 444.4

375.0 500.0

416.7 555.5

458.3 611.1

3

83.3 111.1

4.5

5

5.5

MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

38