MPC8313CZQGDFA [FREESCALE]
PowerQUICC™ II Pro Processor Hardware Specifications; 的PowerQUICC ™II Pro处理器硬件规格
| 型号： | MPC8313CZQGDFA |
| 厂家： | 
Freescale |
| 描述： | PowerQUICC™ II Pro Processor Hardware Specifications |
| 文件： | 总100页 (文件大小：1203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC8313EEC
Rev. 2.1, 12/2008
Freescale Semiconductor
Technical Data
MPC8313E
PowerQUICC II Pro Processor
Hardware Specifications
™
Contents
This document provides an overview of the MPC8313E
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
PowerQUICC™ II Pro processor features, including a block
diagram showing the major functional components. The
MPC8313E is a cost-effective, low-power, highly integrated
host processor that addresses the requirements of several
printing and imaging, consumer, and industrial applications,
including main CPUs and I/O processors in printing systems,
networking switches and line cards, wireless LANs
(WLANs), network access servers (NAS), VPN routers,
intelligent NIC, and industrial controllers. The MPC8313E
extends the PowerQUICC™ family, adding higher CPU
performance, additional functionality, and faster interfaces
while addressing the requirements related to time-to-market,
price, power consumption, and package size.
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 14
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8. Ethernet: Three-Speed Ethernet, MII Management . 21
9. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 36
10. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11. Enhanced Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . 47
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
15. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
16. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
17. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
18. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
19. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 63
20. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
21. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
22. System Design Information . . . . . . . . . . . . . . . . . . . 88
23. Document Revision History . . . . . . . . . . . . . . . . . . . 94
24. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 97
NOTE
The information in this document is accurate for
revisions 1.0, 2.x, and later. See Section 24.1, “Part
Numbers Fully Addressed by this Document.”
© Freescale Semiconductor, Inc., 2007, 2008. All rights reserved.
Overview
1 Overview
The MPC8313E incorporates the e300c3 core, which includes 16 Kbytes of L1 instruction and data caches
and on-chip memory management units (MMUs). The MPC8313E has interfaces to dual enhanced
three-speed 10/100/1000 Mbps Ethernet controllers, a DDR1/DDR2 SDRAM memory controller, an
enhanced local bus controller, a 32-bit PCI controller, a dedicated security engine, a USB 2.0 dual-role
2
controller and an on-chip full-speed PHY, a programmable interrupt controller, dual I C controllers, a
4-channel DMA controller, and a general-purpose I/O port. A block diagram of the MPC8313E is shown
in Figure 1.
DUART
Dual I C
e300c3 Core w/FPU and
Power Management
2
Timers
GPIO
Interrupt
16-KB
I-Cache
16-KB
D-Cache
Local Bus,
SPI
DDR1/DDR2
Controller
Controller
USB 2.0
Host/Device/OTG
Gb Ethernet
MAC
Gb Ethernet
MAC
Security Engine 2.2
I/O Sequencer
(IOS)
On-Chip
ULPI
FS PHY
PCI
DMA
Note: The MPC8313 does not include a security engine.
Figure 1. MPC8313E Block Diagram
The MPC8313E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded
from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES,
3DES, AES, SHA-1, and MD-5 algorithms.
1.1
MPC8313E Features
The following features are supported in the MPC8313E:
•
Embedded PowerPC™ e300 processor core built on Power Architecture™ technology; operates at
up to 333 MHz.
•
•
High-performance, low-power, and cost-effective host processor
DDR1/DDR2 memory controller—one 16-/32-bit interface at up to 333 MHz supporting both
DDR1 and DDR2
•
•
16-Kbyte instruction cache and 16-Kbyte data cache, a floating point unit, and two integer units
Peripheral interfaces such as 32-bit PCI interface with up to 66-MHz operation, 16-bit enhanced
local bus interface with up to 66-MHz operation, and USB 2.0 (full speed) with an on-chip PHY.
•
•
•
Security engine provides acceleration for control and data plane security protocols
Power management controller for low-power consumption
High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
2
Freescale Semiconductor
Overview
1.2
Serial Interfaces
2
The following interfaces are supported in the MPC8313E: dual UART, dual I C, and an SPI interface
1.3
Security Engine
The security engine is optimized to handle all the algorithms associated with IPSec, IEEE Std 802.11i®,
and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution
units (EUs). The execution units are as follows:
•
•
•
Data encryption standard execution unit (DEU), supporting DES and 3DES
Advanced encryption standard unit (AESU), supporting AES
Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-224, SHA-256, and
HMAC with any algorithm
•
One crypto-channel supporting multi-command descriptor chains
1.4
DDR Memory Controller
The MPC8313E DDR1/DDR2 memory controller includes the following features:
•
•
•
•
•
Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM
Support for up to 333 MHz
Support for two physical banks (chip selects), each bank independently addressable
64-Mbit to 1-Gbit devices with x8/x16/x32 data ports (no direct x4 support)
Support for one 16-bit device or two 8-bit devices on a 16-bit bus, or one 32-bit device or two
16-bit devices on a 32-bit bus
•
•
•
•
Support for up to 16 simultaneous open pages
Supports auto refresh
On-the-fly power management using CKE
1.8-/2.5-V SSTL2 compatible I/O
1.5
PCI Controller
The MPC8313E PCI controller includes the following features:
•
•
•
•
•
•
PCI specification revision 2.3 compatible
Single 32-bit data PCI interface operates at up to 66 MHz
PCI 3.3-V compatible (not 5-V compatible)
Support for host and agent modes
On-chip arbitration, supporting three external masters on PCI
Selectable hardware-enforced coherency
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
3
Overview
1.6
USB Dual-Role Controller
The MPC8313E USB controller includes the following features:
•
Supports USB on-the-go mode, which includes both device and host functionality, when using an
external ULPI (UTMI + low-pin interface) PHY
•
•
Compatible with Universal Serial Bus Specification, Rev. 2.0
Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
•
•
•
Supports full-speed (12 Mbps), and low-speed (1.5 Mbps) operation. Low-speed operation is
supported only in host mode.
Supports UTMI + low pin interface (ULPI) or on-chip USB 2.0 full-speed PHY
1.7
Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
The MPC8313E eTSECs include the following features:
•
•
Two RGMII/SGMII/MII/RMII/RTBI interfaces
Two controllers designed to comply with IEEE Std 802.3®, 802.3u®, 802.3x®, 802.3z®,
802.3au®, and 802.3ab®
•
Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating
mode
•
•
•
•
•
•
•
•
•
•
•
•
MII management interface for external PHY control and status
Three-speed support (10/100/1000 Mbps)
On-chip high-speed serial interface to external SGMII PHY interface
Support for IEEE Std 1588™
Support for two full-duplex FIFO interface modes
Multiple PHY interface configuration
TCP/IP acceleration and QoS features available
IP v4 and IP v6 header recognition on receive
IP v4 header checksum verification and generation
TCP and UDP checksum verification and generation
Per-packet configurable acceleration
Recognition of VLAN, stacked (queue in queue) VLAN, IEEE Std 802.2®, PPPoE session, MPLS
stacks, and ESP/AH IP-security headers
•
•
Transmission from up to eight physical queues.
Reception to up to eight physical queues
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
4
Freescale Semiconductor
Overview
•
Full- and half-duplex Ethernet support (1000 Mbps supports only full-duplex):
— IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
software-programmed PAUSE frame generation and recognition)
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and
IEEE 802.1 virtual local area network (VLAN) tags and priority
— VLAN insertion and deletion
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
— Retransmission following a collision
— CRC generation and verification of inbound/outbound packets
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
MAC address recognition:
•
•
— Exact match on primary and virtual 48-bit unicast addresses
– VRRP and HSRP support for seamless router fail-over
— Up to 16 exact-match MAC addresses supported
— Broadcast address (accept/reject)
— Hash table match on up to 512 multicast addresses
— Promiscuous mode
Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet
programming models
•
•
•
RMON statistics support
10-Kbyte internal transmit and 2-Kbyte receive FIFOs
MII management interface for control and status
1.8
Programmable Interrupt Controller (PIC)
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible
solution for general-purpose interrupt control. The PIC programming model supports 5 external and 34
internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller.
1.9
Power Management Controller (PMC)
The MPC8313E power management controller includes the following features:
•
•
•
•
•
Provides power management when the device is used in both host and agent modes
Supports PCI power management 1.2 D0, D1, D2, D3hot, and D3cold states
On-chip split power supply controlled through external power switch for minimum standby power
Support for PME generation in PCI agent mode, PME detection in PCI host mode
Supports wake-up from Ethernet (Magic Packet), USB, GPIO, and PCI (PME input as host)
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
5
Electrical Characteristics
1.10 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the MPC8313E to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit.
2
1.11 DMA Controller, Dual I C, DUART, Local Bus Controller, and
Timers
The MPC8313E provides an integrated four-channel DMA controller with the following features:
•
Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(accessible by local masters)
•
Supports misaligned transfers
2
There are two I C controllers. These synchronous, multi-master buses can be connected to additional
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. The 16-byte FIFOs are supported for both the transmitter and the receiver.
The MPC8313E local bus controller (LBC) port allows connections with a wide variety of external DSPs
and ASICs. Three separate state machines share the same external pins and can be programmed separately
to access different types of devices. The general-purpose chip select machine (GPCM) controls accesses
to asynchronous devices using a simple handshake protocol. The three user programmable machines
(UPMs) can be programmed to interface to synchronous devices or custom ASIC interfaces. Each chip
select can be configured so that the associated chip interface can be controlled by the GPCM or UPM
controller. The FCM provides a glueless interface to parallel-bus NAND Flash E2PROM devices. The
FCM contains three basic configuration register groups—BRn, ORn, and FMR. Both may exist in the
same system. The local bus can operate at up to 66 MHz.
The MPC8313E system timers include the following features: periodic interrupt timer, real time clock,
software watchdog timer, and two general-purpose timer blocks.
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8313E. The MPC8313E is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
6
Freescale Semiconductor
Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
1
Table 1. Absolute Maximum Ratings
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
PLL supply voltage
V
–0.3 to 1.26
–0.3 to 1.26
–0.3 to 1.26
–0.3 to 1.26
V
V
V
V
V
—
—
—
—
—
DD
AV
DD
Core power supply for SerDes transceivers
Pad power supply for SerDes transceivers
DDR and DDR2 DRAM I/O voltage
XCOREV
DD
XPADV
DD
GV
–0.3 to 2.75
–0.3 to 1.98
DD
PCI, local bus, DUART, system control and power
management, I C, and JTAG I/O voltage
NV /LV
–0.3 to 3.6
V
—
DD
DD
2
eTSEC, USB
LV
/LV
–0.3 to 3.6
V
V
V
V
—
DDA
DDB
Input voltage
DDR DRAM signals
MV
–0.3 to (GV + 0.3)
2, 5
2, 5
4, 5
IN
DD
DDR DRAM reference
MV
–0.3 to (GV + 0.3)
DD
REF
Enhanced three-speed Ethernet signals
LV
–0.3 to (LV
+ 0.3)
+ 0.3)
IN
DDA
or
–0.3 to (LV
DDB
Local bus, DUART, SYS_CLK_IN, system
control, and power management, I C, and
JTAG signals
OV
–0.3 to (NV + 0.3)
V
3, 5
IN
IN
DD
2
PCI
OV
T
–0.3 to (NV + 0.3)
V
6
DD
Storage temperature range
–55 to 150
°C
—
STG
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MV must not exceed GV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
3. Caution: OV must not exceed NV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
4. Caution: LV must not exceed LV /LV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
DDB
IN
DDA
power-on reset and power-down sequences.
2.1.2
Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the MPC8313E. Note that the values in
Table 2 are the recommended and tested operating conditions. If a particular block is given a voltage
falling within the range in the Recommended Value column, the MPC8313E is capable of delivering the
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
7
Electrical Characteristics
amount of current listed in the Current Requirement column; this is the maximum current possible. Proper
device operation outside of these conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Recommended
Current
Requirement
Characteristic
Core supply voltage
Symbol
Unit
1
Value
V
1.0 V ± 50 mV
1.0 V ± 50 mV
1.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
469 mA
377 mA
170 mA
—
DD
Internal core logic constant power
SerDes internal digital power
V
DDC
XCOREV
XCOREV
DD
SerDes internal digital ground
0.0
SS
SerDes I/O digital power
XPADV
XPADV
1.0
10 mA
—
DD
SerDes I/O digital ground
0.0
SS
DD
SS
SerDes analog power for PLL
SDAV
SDAV
1.0 V ± 50 mV
0.0
10 mA
—
SerDes analog ground for PLL
Dedicated 3.3 V analog power for USB PLL
Dedicated 1.0 V analog power for USB PLL
Dedicated analog ground for USB PLL
Dedicated USB power for USB bias circuit
Dedicated USB ground for USB bias circuit
Dedicated power for USB transceiver
Dedicated ground for USB transceiver
Analog power for e300 core APLL
Analog power for system APLL
USB_PLL_PWR3
USB_PLL_PWR1
USB_PLL_GND
USB_VDDA_BIAS
USB_VSSA_BIAS
USB_VDDA
3.3 V ± 300 mV
1.0 V ± 50 mV
0.0
2–3 mA
2–3 mA
—
3.3 V ± 300 mV
0.0
4–5 mA
—
3.3 V ± 300 mV
0.0
75 mA
—
USB_VSSA
AV
AV
1.0 V ± 50 mV
1.0 V ± 50 mV
2.5 V ± 125 mV
1.8 V ± 80 mV
1/2 DDR supply
2–3 mA
2–3 mA
131 mA
140 mA
—
DD1
DD2
DDR1 DRAM I/O voltage (333 MHz, 32-bit operation)
DDR2 DRAM I/O voltage (333 MHz, 32-bit operation)
Differential reference voltage for DDR controller
GV
GV
DD
DD
MV
REF
(0.49 × GV to
DD
0.51 × GV
)
DD
2
Standard I/O voltage
eTSEC2 IO supply
NV
3.3 V ± 300 mV
V
V
74 mA
22 mA
DD
LV
2.5 V ± 125 mV/
3.3 V ± 300 mV
DDA
eTSEC1/USB DR IO supply
LV
2.5 V ± 125 mV/
3.3 V ± 300 mV
V
44 mA
DDB
Supply for eLBC IOs
Analog and digital ground
Junction temperature
LV
3.3 V ± 300 mV
0.0
V
V
16 mA
—
DD
V
SS
T
0 to 105
°C
—
J
1
GV , NV , AV , and V must track each other and must vary in the same direction—either in the positive or negative
DD
DD
DD
DD
direction.
2
Some GPIO pins may operate from a 2.5-V supply when configured for other functions.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
8
Freescale Semiconductor
Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8313E.
G/L/NV + 20%
DD
G/L/NV + 5%
DD
G/L/NV
V
DD
IH
V
SS
V
V
– 0.3 V
SS
SS
V
IL
– 0.7 V
Not to Exceed 10%
1
of t
interface
Note:
1. Note that t
refers to the clock period associated with the bus clock
interface
interface.
Figure 2. Overshoot/Undershoot Voltage for GV /NV /LV
DD
DD
DD
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths.
Table 3. Output Drive Capability
Driver Type
Output Impedance (Ω)
Supply Voltage
NV = 3.3 V
Local bus interface utilities signals
PCI signals
42
25
18
18
42
42
42
42
DD
DDR signal
GV = 2.5 V
DD
DDR2 signal
GV = 1.8 V
DD
2
DUART, system control, I C, JTAG, SPI
NV = 3.3 V
DD
GPIO signals
eTSEC signals
USB signals
NV = 3.3 V
DD
LV
, LV
= 2.5/3.3 V
DDB
DDA
LV
= 2.5/3.3 V
DDB
2.2
Power Sequencing
The MPC8313E does not require the core supply voltage (V and V
) and IO supply voltages (GV
,
DD
DDC
DD
LV , and OV ) to be applied in any particular order. Note that during power ramp-up, before the power
DD
DD
supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a period of
time that all input and output pins are actively driven and cause contention and excessive current. In order
to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (V
DD
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
9
Power Characteristics
and V
) before the I/O voltage (GV , LV , and OV ) and assert PORESET before the power
DD DD DD
DDC
supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise
to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies
(I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating
PORESET.
Note that there is no specific power down sequence requirement for the MPC8313E. I/O voltage supplies
(GV , LV , and OV ) do not have any ordering requirements with respect to one another.
DD
DD
DD
I/O Voltage (GV , GV , and OV )
DD
DD
DD
V
Core Voltage (V , V
)
DD DDC
0.7 V
90%
t
0
PORESET
t
/t
>= 32 clocks
SYS_CLK_IN PCI_SYNC_IN
Figure 3. Power-Up Sequencing Example
3 Power Characteristics
The estimated typical power dissipation, not including I/O supply power, for this family of MPC8313E
devices is shown in Table 4. Table 5 shows the estimated typical I/O power dissipation.
1
Table 4. MPC8313E Power Dissipation
Maximum for
Rev. 1.0
Maximum for
Core Frequency
(MHz)
CSB Frequency
(MHz)
2
Typical
Rev. 2.x or Later
Unit
3
3
Silicon
Silicon
333
400
167
133
820
820
1020
1020
1200
1200
mW
mW
1
The values do not include I/O supply power or AV , but do include core, USB PLL, and a portion of SerDes
DD
digital power (not including XCOREV , XPADV , or SDAV , which all have dedicated power supplies for
DD
DD
DD
the SerDes PHY).
2
3
Typical power is based on a voltage of V = 1.05 V and an artificial smoker test running at room
temperature.
Maximum power is based on a voltage of V = 1.05 V, a junction temperature of T = 105°C, and an artificial
smoker test.
DD
DD
J
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
10
Power Characteristics
Table 5 describes a typical scenario where blocks with the stated percentage of utilization and impedances
consume the amount of power described.
1
Table 5. MPC8313E Typical I/O Power Dissipation
LV
LV
(3.3 V)
/
LV
LV
(2.5 V)
/
DDA
DDA
GV
GV
NV
LV
DD
(3.3 V)
DD
DD
DD
Interface
Parameter
Unit Comments
DDB
DDB
(1.8 V) (2.5 V) (3.3 V)
DDR 1, 60% utilization,
50% read/write
333 MHz,
32 bits
—
—
0.355
0.323
—
—
—
—
—
W
W
—
—
R = 22 Ω
s
266 MHz,
32 bits
—
—
—
R = 50 Ω
t
single pair of clock
capacitive load: data = 8 pF,
control address = 8 pF,
clock = 8 pF
DDR 2, 60% utilization,
50% read/write
333 MHz,
32 bits
0.266
0.246
—
—
—
—
—
—
—
—
—
—
W
W
—
—
R = 22 Ω
s
266 MHz,
32 bits
R = 75 Ω
t
single pair of clock
capacitive load: data = 8 pF,
control address = 8 pF,
clock = 8 pF
PCI I/O load = 50 pF
33 MHz
66 MHz
66 MHz
50 MHz
—
—
—
—
—
—
—
—
—
—
0.120
0.249
—
—
—
—
—
—
—
—
—
—
W
W
W
W
W
—
—
—
—
Local bus I/O load = 20 pF
TSEC I/O load = 20 pF
—
0.056
0.040
—
—
—
MII,
25 MHz
—
0.008
Multiple by
number of
interface
used
RGMII,
125 MHz
—
—
—
0.078
0.044
—
W
USBDR controller load = 20 pF
Other I/O
60 MHz
—
—
—
—
—
—
0.078
—
—
—
—
—
W
W
—
—
0.015
Table 6 shows the estimated core power dissipation of the MPC8313E while transitioning into the
D3 warm low-power state.
1
Table 6. MPC8313E Low-Power Modes Power Dissipation
Rev. 2.x or
Later
2
3
333-MHz Core, 167-MHz CSB
Rev. 1.0
Unit
3
D3 warm
400
425
mW
1
2
All interfaces are enabled. For further power savings, disable the clocks to unused
blocks.
The interfaces are run at the following frequencies: DDR: 333 MHz, eLBC 83 MHz,
PCI 33 MHz, eTSEC1 and TSEC2: 167 MHz, SEC: 167 MHz, USB: 167 MHz. See
the SCCR register for more information.
This is maximum power in D3 Warm based on a voltage of 1.05 V and a junction
temperature of 105°C.
3
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
11
Clock Input Timing
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8313E.
4.1
DC Electrical Characteristics
Table 7 provides the system clock input (SYS_CLK_IN/PCI_SYNC_IN) DC timing specifications for the
MPC8313E.
Table 7. SYS_CLK_IN DC Electrical Characteristics
Parameter
Input high voltage
Condition
Symbol
Min
Max
Unit
—
—
V
2.4
–0.3
—
NV + 0.3
V
V
IH
DD
Input low voltage
V
I
0.4
±10
±10
IL
SYS_CLK_IN input current
PCI_SYNC_IN input current
0 V ≤ V ≤ NV
μA
μA
IN
DD
IN
IN
0 V ≤ V ≤ 0.5 V
I
—
IN
or
NV – 0.5 V ≤ V ≤ NV
DD
IN
DD
PCI_SYNC_IN input current
0.5 V ≤ V ≤ NV – 0.5 V
I
—
±50
μA
IN
DD
IN
4.2
AC Electrical Characteristics
The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK,
depending on whether the device is configured in PCI host or PCI agent mode. Table 8 provides the system
clock input (SYS_CLK_IN/PCI_CLK) AC timing specifications for the MPC8313E.
Table 8. SYS_CLK_IN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
SYS_CLK_IN/PCI_CLK frequency
SYS_CLK_IN/PCI_CLK cycle time
SYS_CLK_IN/PCI_CLK rise and fall time
SYS_CLK_IN/PCI_CLK duty cycle
SYS_CLK_IN/PCI_CLK jitter
Notes:
f
t
24
15
0.6
40
—
—
—
66.67
—
MHz
ns
1
—
2
SYS_CLK_IN
SYS_CLK_IN
t
, t
0.8
—
1.2
ns
KH KL
t
/t
60
%
3
KHK SYS_CLK_IN
—
—
±150
ps
4, 5
1. Caution: The system, core, security block must not exceed their respective maximum or minimum operating frequencies.
2. Rise and fall times for SYS_CLK_IN/PCI_CLK are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set
low to allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
12
Freescale Semiconductor
RESET Initialization
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8313E.
5.1
RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins.
Table 9. RESET Pins DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
V
—
—
2.1
–0.3
—
NV + 0.3
V
V
IH
DD
Input low voltage
Input current
V
I
0.8
±5
IL
0 V ≤ V ≤ NV
μA
V
IN
IN
DD
Output high voltage
Output low voltage
Output low voltage
V
I
= –8.0 mA
OH
2.4
—
—
OH
V
I
= 8.0 mA
= 3.2 mA
OL
0.5
0.4
V
OL
OL
V
I
—
V
OL
5.2
RESET AC Electrical Characteristics
Table 10 provides the reset initialization AC timing specifications.
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET (input) to activate reset flow
32
32
—
—
t
1
2
PCI_SYNC_IN
Required assertion time of PORESET with stable clock and power applied to
SYS_CLK_IN when the device is in PCI host mode
t
SYS_CLK_IN
PCI_SYNC_IN
PCI_SYNC_IN
Required assertion time of PORESET with stable clock and power applied to
PCI_SYNC_IN when the device is in PCI agent mode
32
—
t
t
1
HRESET assertion (output)
512
4
—
—
1
2
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]
and CFG_SYS_CLK_IN_DIV) with respect to negation of PORESET when
the device is in PCI host mode
t
SYS_CLK_IN
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2]
and CFG_CLKIN_DIV) with respect to negation of PORESET when the
device is in PCI agent mode
4
—
t
1
PCI_SYNC_IN
Input hold time for POR configuration signals with respect to negation of
HRESET
0
—
4
ns
ns
—
3
Time for the device to turn off POR configuration signal drivers with respect
to the assertion of HRESET
—
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
13
DDR and DDR2 SDRAM
Table 10. RESET Initialization Timing Specifications (continued)
Parameter/Condition
Min
Max
Unit
Notes
Time for the device to turn on POR configuration signal drivers with respect to
the negation of HRESET
1
—
t
1, 3
PCI_SYNC_IN
Notes:
1. t
is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
PCI_SYNC_IN
clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV.
2. t is the clock period of the input clock applied to SYS_CLK_IN. It is only valid when the device is in PCI host mode.
SYS_CLK_IN
3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 11 provides the PLL lock times.
Table 11. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs
—
6 DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface. Note that
DDR SDRAM is GV (typ) = 2.5 V and DDR2 SDRAM is GV (typ) = 1.8 V.
DD
DD
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) when
GV (typ) = 1.8 V.
DD
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V
DD
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GV
MV
1.7
1.9
V
V
1
2
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
– 0.04
MV
+ 0.04
REF
V
3
REF
V
MV
+ 0.125
GV + 0.3
V
—
—
4
IH
REF
DD
Input low voltage
V
I
–0.3
MV
– 0.125
REF
V
IL
Output leakage current
–9.9
–13.4
13.4
9.9
μA
mA
mA
OZ
OH
Output high current (V
= 1.420 V)
I
—
—
—
—
OUT
Output low current (V
= 0.280 V)
I
OL
OUT
Notes:
1. GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2. MV
is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver. Peak-to-peak
REF
DD DD
may not exceed ±2% of the DC value.
noise on MV
REF
3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
TT
equal to MV
. This rail should track variations in the DC level of MV
.
REF
REF
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
.
DD
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
14
Freescale Semiconductor
DDR and DDR2 SDRAM
Table 13 provides the DDR2 capacitance when GV (typ) = 1.8 V.
DD
Table 13. DDR2 SDRAM Capacitance for GV (typ) = 1.8 V
DD
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
Delta input/output capacitance: DQ, DQS, DQS
Note:
C
6
8
pF
pF
1
1
IO
C
—
0.5
DIO
1. This parameter is sampled. GV = 1.8 V ± 0.090 V, f = 1 MHz, T = 25°C, V
= GV /2, V
(peak-to-peak) = 0.2 V.
DD
A
OUT
DD
OUT
Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when
GV (typ) = 2.5 V.
DD
Table 14. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V
DD
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GV
MV
2.3
2.7
V
V
1
2
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
– 0.04
+ 0.15
MV
+ 0.04
REF
V
3
REF
REF
V
MV
GV + 0.3
V
—
—
4
IH
DD
Input low voltage
V
I
–0.3
MV
– 0.15
REF
V
IL
Output leakage current
–9.9
–16.2
16.2
–9.9
μA
mA
mA
OZ
OH
Output high current (V
= 1.95 V)
I
—
—
—
—
OUT
Output low current (V
= 0.35 V)
I
OL
OUT
Notes:
1. GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2. MV
is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver. Peak-to-peak
REF
DD DD
may not exceed ±2% of the DC value.
noise on MV
REF
3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
TT
equal to MV
. This rail should track variations in the DC level of MV
.
REF
REF
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
.
DD
Table 15 provides the DDR capacitance when GV (typ) = 2.5 V.
DD
Table 15. DDR SDRAM Capacitance for GV (typ) = 2.5 V
DD
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
Delta input/output capacitance: DQ, DQS
Note:
C
6
8
pF
pF
1
1
IO
C
—
0.5
DIO
1. This parameter is sampled. GV = 2.5 V ± 0.125 V, f = 1 MHz, T = 25°C, V
= GV /2, V
(peak-to-peak) = 0.2 V.
DD
A
OUT
DD
OUT
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
15
DDR and DDR2 SDRAM
Table 16 provides the current draw characteristics for MV
.
REF
Table 16. Current Draw Characteristics for MV
REF
Parameter/Condition
Current draw for MV
Symbol
Min
Max
Unit
Note
I
—
500
μA
1
REF
MVREF
Note:
1. The voltage regulator for MV
must be able to supply up to 500 μA current.
REF
6.2
DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR and DDR2 SDRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GV (typ) = 1.8 V.
DD
Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 ± 5%.
Parameter
Symbol
Min
Max
– 0.25
REF
Unit
Notes
AC input low voltage
AC input high voltage
V
—
MV
V
V
—
—
IL
V
MV
+ 0.25
REF
—
IH
Table 18 provides the input AC timing specifications for the DDR SDRAM when GV (typ) = 2.5 V.
DD
Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions with GVDD of 2.5 ± 5%.
Parameter
Symbol
Min
Max
– 0.31
REF
Unit
Notes
AC input low voltage
AC input high voltage
V
—
MV
V
V
—
—
IL
V
MV
+ 0.31
REF
—
IH
Table 19 provides the input AC timing specifications for the DDR2 SDRAM interface.
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions. with GVDD of 2.5 ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Controller skew for MDQS—MDQ
t
—
—
ps
1, 2
CISKEW
333 MHz
266 MHz
Notes:
—
–750
–750
750
750
—
—
—
—
—
1. t
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
CISKEW
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
. This can be
DISKEW
determined by the following equation: t
= ± (T/4 – abs(t
)) where T is the clock period and abs(t
) is the
DISKEW
CISKEW
CISKEW
absolute value of t
.
CISKEW
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
16
DDR and DDR2 SDRAM
Figure 4 illustrates the DDR input timing diagram showing the t
timing parameter.
DISKEW
MCK[n]
MCK[n]
t
MCK
MDQS[n]
MDQ[x]
D0
D1
t
DISKEW
t
DISKEW
Figure 4. DDR Input Timing Diagram
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Rev. 1.0 Silicon
1
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n] cycle time, MCK[n]/MCK[n] crossing
t
6
10
ns
ns
2
3
MCK
ADDR/CMD output setup with respect to MCK
t
t
t
t
DDKHAS
DDKHAX
DDKHCS
DDKHCX
333 MHz
266 MHz
2.1
2.5
—
—
ADDR/CMD output hold with respect to MCK
ns
ns
ns
3
3
3
333 MHz
266 MHz
2.4
3.15
—
—
MCS[n] output setup with respect to MCK
333 MHz
266 MHz
2.4
3.15
—
—
MCS[n] output hold with respect to MCK
333 MHz
266 MHz
2.4
3.15
—
—
MCK to MDQS Skew
t
–0.6
0.6
ns
ps
4
5
DDKHMH
MDQ//MDM output setup with respect to
MDQS
t
t
t
DDKHDS,
t
DDKLDS
333 MHz
266 MHz
800
900
—
—
MDQ//MDM output hold with respect to MDQS
ps
ns
5
6
DDKHDX,
t
DDKLDX
333 MHz
266 MHz
900
1100
—
—
MDQS preamble start
–0.5 × t
– 0.6
–0.5 × t
+ 0.6
MCK
DDKHMP
MCK
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
17
DDR and DDR2 SDRAM
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Rev. 1.0 Silicon (continued)
1
Parameter
Symbol
Min
Max
Unit
Notes
MDQS epilogue end
Notes:
t
–0.6
0.6
ns
6
DDKHME
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. Output hold time can be read as DDR timing
(first two letters of functional block)(reference)(state)(signal)(state)
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H) state until
t
DDKHAS
MCK
outputs (A) are setup (S) or output valid time. Also, t
symbolizes DDR timing (DD) for the time t
memory clock
DDKLDX
MCK
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
4. Note that t follows the symbol conventions described in note 1. For example, t describes the DDR timing (DD)
DDKHMH
DDKHMH
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
can be modified through control
DDKHMH
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, for a
description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
symbol conventions described in note 1.
follows the
DDKHMP
Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Silicon Rev 2.x or Later
1
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n] cycle time, MCK[n]/MCK[n] crossing
t
6
10
ns
ns
2
3
MCK
ADDR/CMD output setup with respect to MCK
t
t
t
t
DDKHAS
DDKHAX
DDKHCS
DDKHCX
333 MHz
266 MHz
2.1
2.5
—
—
ADDR/CMD output hold with respect to MCK
ns
ns
ns
3
3
3
333 MHz
266 MHz
2.0
2.7
—
—
MCS[n] output setup with respect to MCK
333 MHz
266 MHz
2.1
3.15
—
—
MCS[n] output hold with respect to MCK
333 MHz
266 MHz
2.0
2.7
—
—
MCK to MDQS Skew
t
–0.6
0.6
ns
ps
4
5
DDKHMH
MDQ//MDM output setup with respect to
t
DDKHDS,
MDQS
t
DDKLDS
333 MHz
266 MHz
800
900
—
—
MDQ//MDM output hold with respect to MDQS
t
ps
5
DDKHDX,
t
DDKLDX
333 MHz
266 MHz
750
1000
—
—
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
18
DDR and DDR2 SDRAM
Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Silicon Rev 2.x or Later (continued)
1
Parameter
MDQS preamble start
Symbol
Min
Max
Unit
Notes
t
–0.5 × t
– 0.6
–0.5 × t
+ 0.6
ns
ns
6
6
DDKHMP
MCK
MCK
MDQS epilogue end
t
–0.6
0.6
DDKHME
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. Output hold time can be read as DDR timing
(first two letters of functional block)(reference)(state)(signal)(state)
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H) state until
t
DDKHAS
MCK
outputs (A) are setup (S) or output valid time. Also, t
symbolizes DDR timing (DD) for the time t
memory clock
DDKLDX
MCK
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
4. Note that t follows the symbol conventions described in note 1. For example, t describes the DDR timing (DD)
DDKHMH
DDKHMH
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
can be modified through control
DDKHMH
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, for a
description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
symbol conventions described in note 1.
follows the
DDKHMP
NOTE
For the ADDR/CMD setup and hold specifications in Table 21, it is
assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t
).
DDKHMH
MCK[n]
MCK[n]
t
MCK
t
(max) = 0.6 ns
DDKHMH
MDQS
MDQS
t
(min) = –0.6 ns
DDKHMH
Figure 5. Timing Diagram for t
DDKHMH
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
19
DUART
Figure 6 shows the DDR and DDR2 SDRAM output timing diagram.
MCK[n]
MCK[n]
t
MCK
t
,t
DDKHAS DDKHCS
t
, t
DDKHAX DDKHCX
ADDR/CMD
Write A0
NOOP
t
DDKHMP
t
DDKHMH
MDQS[n]
MDQ[x]
t
DDKHME
t
DDKHDS
t
DDKLDS
D0
D1
t
DDKLDX
t
DDKHDX
Figure 6. DDR and DDR2 SDRAM Output Timing Diagram
Figure 7 provides the AC test load for the DDR bus.
Output
Z = 50 Ω
0
GV /2
DD
R = 50 Ω
L
Figure 7. DDR AC Test Load
7 DUART
This section describes the DC and AC electrical specifications for the DUART interface.
7.1
DUART DC Electrical Characteristics
Table 22 provides the DC electrical characteristics for the DUART interface.
Table 22. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
V
2.0
NV + 0.3
V
V
IH
DD
Low-level input voltage NV
V
–0.3
0.8
—
DD
IL
High-level output voltage, I = –100 μA
V
NV – 0.2
V
OH
OH
DD
Low-level output voltage, I = 100 μA
V
—
—
0.2
±5
V
OL
OL
IN
Input current (0 V ≤V ≤ NV
)
DD
I
μA
IN
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
20
Ethernet: Three-Speed Ethernet, MII Management
7.2
DUART AC Electrical Specifications
Table 23 provides the AC timing parameters for the DUART interface.
Table 23. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
Maximum baud rate
Oversample rate
Notes:
256
> 1,000,000
16
baud
baud
—
—
1
2
1. Actual attainable baud rate is limited by the latency of interrupt processing.
th
2. The middle of a start bit is detected as the 8 sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
th
sampled each 16 sample.
8 Ethernet: Three-Speed Ethernet, MII Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII
management.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI Electrical
Characteristics
The electrical characteristics specified here apply to all the media independent interface (MII), reduced
gigabit media independent interface (RGMII), serial gigabit media independent interface (SGMII), and
reduced ten-bit interface (RTBI) signals except management data input/output (MDIO) and management
data clock (MDC). The RGMII and RTBI interfaces are defined for 2.5 V, while the MII interface can be
operated at 3.3 V. The RMII and SGMII interfaces can be operated at either 3.3 or 2.5 V. The RGMII and
RTBI interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical
Layer Device Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC
are specified in Section 8.5, “Ethernet Management Interface Electrical Characteristics.”
8.1.1
TSEC DC Electrical Characteristics
All RGMII, RMII, and RTBI drivers and receivers comply with the DC parametric attributes specified in
Table 24 and Table 25. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as
defined by JEDEC EIA/JESD8-5.
Table 24. MII DC Electrical Characteristics
Parameter
Symbol
/LV
Conditions
Min
Max
Unit
Supply voltage 3.3 V
Output high voltage
LV
—
2.97
2.40
3.63
V
V
DDA
DDB
V
I
= –4.0 mA
LV
or LV
= Min
LV
LV
+ 0.3
DDA
OH
OH
DDA
DDB
or
+ 0.3
DDB
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
21
Ethernet: Three-Speed Ethernet, MII Management
Table 24. MII DC Electrical Characteristics (continued)
Symbol Conditions Min
Parameter
Max
Unit
Output low voltage
Input high voltage
V
I
= 4.0 mA
—
LV
or LV
—
= Min
V
SS
0.50
V
V
OL
OL
DDA
DDB
V
2.0
LV
LV
+ 0.3
DDA
IH
or
+ 0.3
DDB
Input low voltage
Input high current
Input low current
Note:
V
I
—
—
–0.3
—
0.90
40
V
IL
1
V
= LV
or LV
DDB
μA
μA
IH
IN
DDA
1
I
V
= VSS
IN
–600
—
IL
1. The symbol V , in this case, represents the LV symbol referenced in Table 1 and Table 2.
IN
IN
Table 25. RGMII/RTBI DC Electrical Characteristics
Parameters
Symbol
/LV
Conditions
Min
Max
Unit
Supply voltage 2.5 V
Output high voltage
LV
—
2.37
2.00
2.63
V
V
DDA
DDB
V
I
= –1.0 mA
LV
or LV
= Min
LV
LV
+ 0.3
DDA
OH
OH
DDA
DDB
or
+ 0.3
DDB
Output low voltage
Input high voltage
V
I
= 1.0 mA
—
LV
LV
or LV
or LV
= Min
= Min
V – 0.3
SS
0.40
+ 0.3
DDA
V
V
OL
OL
DDA
DDA
DDB
DDB
V
1.7
LV
LV
IH
or
+ 0.3
DDB
Input low voltage
Input high current
Input low current
Note:
V
—
LV
or LV
= Min
–0.3
—
0.70
10
V
IL
DDA
DDB
1
V
I
= LV
or LV
DDB
μA
μA
IH
IN
DDA
1
I
V
= V
–15
—
IL
IN
SS
1. Note that the symbol V , in this case, represents the LV symbol referenced in Table 1 and Table 2.
IN
IN
8.2
MII, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for MII, RMII, RGMII, and RTBI are presented in this section.
8.2.1
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
22
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
8.2.1.1
MII Transmit AC Timing Specifications
Table 26 provides the MII transmit AC timing specifications.
Table 26. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB/NVDD of 3.3 V ± 0.3 V.
Parameter/Condition Symbol
TX_CLK clock period 10 Mbps
1
Min
Typ
Max
Unit
t
t
—
—
400
40
—
5
—
—
ns
ns
%
MTX
MTX
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
t
t
35
1
65
15
4.0
4.0
MTXH/ MTX
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
t
ns
ns
ns
MTKHDX
TX_CLK data clock rise V (min) to V (max)
t
MTXR
1.0
1.0
—
—
IL
IH
TX_CLK data clock fall V (max) to V (min)
t
MTXF
IH
IL
Note:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes MII transmit
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
MTX
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
MTX
used with the appropriate letter: R (rise) or F (fall).
Figure 8 shows the MII transmit AC timing diagram.
t
t
MTXR
MTX
TX_CLK
t
t
MTXH
MTXF
TXD[3:0]
TX_EN
TX_ER
t
MTKHDX
Figure 8. MII Transmit AC Timing Diagram
8.2.1.2
MII Receive AC Timing Specifications
Table 27 provides the MII receive AC timing specifications.
Table 27. MII Receive AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB/NVDD of 3.3 V ± 0.3 V.
Parameter/Condition Symbol
RX_CLK clock period 10 Mbps
1
Min
Typ
Max
Unit
t
—
—
400
40
—
—
—
65
—
ns
ns
%
MRX
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
t
MRX
t
/t
35
MRXH MRX
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
t
10.0
—
ns
MRDVKH
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
23
Ethernet: Three-Speed Ethernet, MII Management
Table 27. MII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDDA/LVDDB/NVDD of 3.3 V ± 0.3 V.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
t
10.0
1.0
—
—
—
—
ns
ns
ns
MRDXKH
RX_CLK clock rise V (min) to V (max)
t
MRXR
4.0
4.0
IL
IH
RX_CLK clock fall time V (max) to V (min)
t
MRXF
1.0
IH
IL
Note:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes MII receive
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K)
MRX
going to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data input
MRDXKL
signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in general,
MRX
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
MRX
with the appropriate letter: R (rise) or F (fall).
Figure 9 provides the AC test load for TSEC.
Output
Z = 50 Ω
0
LV
/2 or LV
/2
DDB
DDA
R = 50 Ω
L
Figure 9. TSEC AC Test Load
Figure 10 shows the MII receive AC timing diagram.
t
t
MRXR
MRX
RX_CLK
t
t
MRXF
MRXH
RXD[3:0]
RX_DV
RX_ER
Valid Data
t
MRDVKH
t
MRDXKH
Figure 10. MII Receive AC Timing Diagram RMII AC Timing Specifications
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
24
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
8.2.1.3
RMII Transmit AC Timing Specifications
Table 28 provides the RMII transmit AC timing specifications.
Table 28. RMII Transmit AC Timing Specifications
At recommended operating conditions with NVDD of 3.3 V ± 0.3 V.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
REF_CLK clock
t
—
35
2
20
—
—
—
—
—
65
ns
%
RMX
REF_CLK duty cycle
t
t
RMXH/ RMX
REF_CLK to RMII data TXD[1:0], TX_EN delay
t
10
ns
ns
ns
RMTKHDX
REF_CLK data clock rise V (min) to V (max)
t
RMXR
1.0
1.0
4.0
4.0
IL
IH
REF_CLK data clock fall V (max) to V (min)
t
RMXF
IH
IL
Note:
1. The symbols used for timing specifications follow the pattern of t
for
(first three letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes RMII
(first two letters of functional block)(reference)(state)(signal)(state)
RMTKHDX
transmit timing (RMT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
RMX
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of t represents the RMII(RM) reference (X) clock. For rise and fall times, the latter
RMX
convention is used with the appropriate letter: R (rise) or F (fall).
Figure 11 shows the RMII transmit AC timing diagram.
t
t
RMX
RMXR
REF_CLK
t
t
RMXF
RMXH
TXD[1:0]
TX_EN
t
RMTKHDX
Figure 11. RMII Transmit AC Timing Diagram
8.2.1.4
RMII Receive AC Timing Specifications
Table 29 provides the RMII receive AC timing specifications.
Table 29. RMII Receive AC Timing Specifications
At recommended operating conditions with NVDD of 3.3 V ± 0.3 V.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
REF_CLK clock period
t
—
35
20
—
—
—
—
—
65
—
ns
%
RMX
REF_CLK duty cycle
t
/t
RMXH RMX
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
t
t
4.0
2.0
1.0
ns
ns
ns
RMRDVKH
RMRDXKH
—
REF_CLK clock rise V (min) to V (max)
t
RMXR
4.0
IL
IH
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
25
Ethernet: Three-Speed Ethernet, MII Management
Table 29. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with NVDD of 3.3 V ± 0.3 V.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
REF_CLK clock fall time V (max) to V (min)
t
RMXF
1.0
—
4.0
ns
IH
IL
Note:
1. The symbols used for timing specifications follow the pattern of t
for
(first three letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes RMII
(first two letters of functional block)(reference)(state)(signal)(state)
RMRDVKH
receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock
RMX
reference (K) going to the high (H) state or setup time. Also, t
the time data input signals (D) went invalid (X) relative to the t
symbolizes RMII receive timing (RMR) with respect to
clock reference (K) going to the low (L) state or hold time.
RMRDXKL
RMX
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of t represents the RMII (RM) reference (X) clock. For rise and fall times, the latter
RMX
convention is used with the appropriate letter: R (rise) or F (fall).
Figure 12 provides the AC test load.
Output
Z = 50 Ω
0
NV /2
DD
R = 50 Ω
L
Figure 12. AC Test Load
Figure 13 shows the RMII receive AC timing diagram.
t
t
RMXR
RMX
REF_CLK
t
t
RMXF
RMXH
RXD[1:0]
CRS_DV
RX_ER
Valid Data
t
RMRDVKH
t
RMRDXKH
Figure 13. RMII Receive AC Timing Diagram
8.2.2
RGMII and RTBI AC Timing Specifications
Table 30 presents the RGMII and RTBI AC timing specifications.
Table 30. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB of 2.5 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
t
t
–0.5
1.0
7.2
45
—
—
0.5
2.8
8.8
55
ns
ns
ns
%
SKRGT
SKRGT
2
Data to clock input skew (at receiver)
3
Clock cycle duration
t
8.0
50
RGT
4, 5
Duty cycle for 1000Base-T
t
/t
RGTH RGT
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
26
Ethernet: Three-Speed Ethernet, MII Management
Table 30. RGMII and RTBI AC Timing Specifications (continued)
At recommended operating conditions with LVDDA/LVDDB of 2.5 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
3, 5
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
t
/t
40
—
—
—
47
50
—
60
0.75
0.75
—
%
ns
ns
ns
%
RGTH RGT
t
RGTR
Fall time (20%–80%)
t
—
RGTF
6
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes:
t
8.0
—
G12
t
/t
53
G125H G125
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of t represents the RTBI (T) receive (RX) clock. Note also that the
RGT
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is
added to the associated clock signal.
3. For 10 and 100 Mbps, t
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
RGT
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t
between.
of the lowest speed transitioned
RGT
5. Duty cycle reference is LV
/2 or LV
/2.
DDA
DDB
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
Figure 14 shows the RGMII and RTBI AC timing and multiplexing diagrams.
t
RGT
t
RGTH
GTX_CLK
(At Transmitter)
t
SKRGT
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
t
SKRGT
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
t
SKRGT
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
t
SKRGT
RX_CLK
(At PHY)
Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
27
Ethernet: Three-Speed Ethernet, MII Management
8.3
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-coupled serial link from the dedicated SerDes interface of
MPC8313E as shown in Figure 15, where C is the external (on board) AC-coupled capacitor. Each
TX
output pin of the SerDes transmitter differential pair features a 50-Ω output impedance. Each input of the
SerDes receiver differential pair features 50-Ω on-die termination to XCOREVSS. The reference circuit
of the SerDes transmitter and receiver is shown in Figure 33.
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of
this eTSEC port can be left floating. The input signals should be terminated based on the guidelines
described in Section 22.5, “Connection Recommendations,” as long as such termination does not violate
the desired POR configuration requirement on these pins, if applicable.
When operating in SGMII mode, the TSEC_GTX_CLK125 clock is not required for this port. Instead, the
SerDes reference clock is required on SD_REF_CLK and SD_REF_CLK pins.
8.3.1
DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in Section 9,
“High-Speed Serial Interfaces (HSSI).”
8.3.2
AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK
Table 31 lists the SGMII SerDes reference clock AC requirements. Note that SD_REF_CLK and
SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
Table 31. SD_REF_CLK and SD_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typ
Max
Unit
t
REFCLK cycle time
—
—
8
—
ns
ps
REF
t
t
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles
—
100
REFCJ
Phase jitter. Deviation in edge location with respect to mean
edge location
–50
—
50
ps
REFPJ
8.3.3
SGMII Transmitter and Receiver DC Electrical Characteristics
Table 32 and Table 33 describe the SGMII SerDes transmitter and receiver AC-coupled DC electrical
characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SD_TX[n] and
SD_TX[n]) as depicted in Figure 16.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
28
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Table 32. SGMII DC Transmitter Electrical Characteristics
Parameter
Supply voltage
Symbol
XCOREV
Min
Typ
Max
Unit
Notes
0.95
—
1.0
—
1.05
V
DD
Output high voltage
V
XCOREV
/2 mV
1
1
OH
DD-Typ
+ |V
|
/2
OD -max
Output low voltage
V
XCOREV
/2
—
—
mV
OL
DD-Typ
– |V
|
/2
OD -max
Output ringing
V
—
—
10
%
RING
2, 3
Output differential voltage
|V
|
323
500
725
mV
Equalization
setting: 1.0x
OD
Output offset voltage
V
425
40
500
—
575
60
mV
1, 4
OS
Output impedance
(single-ended)
R
Ω
O
Mismatch in a pair
ΔR
—
—
—
—
—
—
—
—
10
25
25
40
%
O
Change in V between 0 and 1
Δ|V
|
mV
mV
mA
OD
OD
OS
Change in V between 0 and 1
ΔV
OS
Output current on short to GND
I
, I
SA SB
Notes:
1. This will not align to DC-coupled SGMII. XCOREV
= 1.0 V.
DD-Typ
2. |V | = |V
– V
|. |V | is also referred as output differential peak voltage. V
= 2*|V |.
OD
TXn
TXn
OD
TX-DIFFp-p OD
3. The |V | value shown in the Typ column is based on the condition of XCOREV
= 1.0 V, no common mode offset
OD
DD-Typ
variation (V
= 500 mV), SerDes transmitter is terminated with 100-Ω differential load between TX[n] and TX[n].
OS
4. V is also referred to as output common mode voltage.
OS
TXn
RXm
50 Ω
C
C
TX
50 Ω
Receiver
Transmitter
50 Ω
TX
TXn
RXm
50 Ω
50 Ω
MPC8313E SGMII
SerDes Interface
C
RXn
TXm
TX
TX
50 Ω
Receiver
Transmitter
50 Ω
C
RXn
TXm
50 Ω
Figure 15. 4-Wire AC-Coupled SGMII Serial Link Connection Example
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
29
Ethernet: Three-Speed Ethernet, MII Management
MPC8313E SGMII
SerDes Interface
TXn
TXn
50 Ω
50
50
Ω
Transmitter
V
V
os
OD
50 Ω
Ω
Figure 16. SGMII Transmitter DC Measurement Circuit
Table 33. SGMII DC Receiver Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Supply voltage
XCOREV
0.95
1.0
N/A
—
1.05
V
DD
DC Input voltage range
1
2
Input differential voltage
V
100
30
—
1200
100
100
120
35
mV
mV
mV
Ω
RX_DIFFp-p
Loss of signal threshold
VL
—
OS
Input AC common mode voltage
Receiver differential input impedance
Receiver common mode input impedance
Common mode input voltage
V
—
3
4
CM_ACp-p
Z
80
20
—
100
—
RX_DIFF
Z
Ω
RX_CM
V
V
—
V
CM
xcorevss
Notes:
1. Input must be externally AC-coupled.
2. V
3. V
is also referred to as peak to peak input differential voltage
is also referred to as peak to peak AC common mode voltage.
RX_DIFFp-p
CM_ACp-p
4. On-chip termination to XCOREV
.
SS
8.3.4
SGMII AC Timing Specifications
This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver
characteristics are measured at the transmitter outputs (TX[n] and TX[n]) or at the receiver inputs (RX[n]
and RX[n]) as depicted in Figure 18, respectively.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
30
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
8.3.4.1
SGMII Transmit AC Timing Specifications
Table 34 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.
Table 34. SGMII Transmit AC Timing Specifications
At recommended operating conditions with XCOREVDD = 1.0 V ± 5%.
Parameter
Deterministic jitter
Symbol
Min
Typ
Max
Unit
Notes
JD
JT
—
—
—
—
0.17
0.35
UI p-p
UI p-p
ps
Total jitter
Unit interval
UI
799.92
50
800
—
800.08
120
1
V
V
fall time (80%–20%)
rise time (20%–80%)
tfall
ps
OD
OD
t
50
—
120
ps
rise
Note:
1. Each UI is 800 ps ± 100 ppm.
8.3.4.2
SGMII Receive AC Timing Specifications
Table 35 provides the SGMII receive AC timing specifications. Source synchronous clocking is not
supported. Clock is recovered from the data. Figure 17 shows the SGMII receiver input compliance mask
eye diagram.
Table 35. SGMII Receive AC Timing Specifications
At recommended operating conditions with XCOREVDD = 1.0 V ± 5%.
Parameter
Deterministic jitter tolerance
Symbol
Min
Typ
Max
Unit
Notes
JD
JDR
JSIN
JT
0.37
0.55
0.1
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
1
1
1
1
Combined deterministic and random jitter tolerance
Sinusoidal jitter tolerance
Total jitter tolerance
—
0.65
—
—
–12
Bit error ratio
BER
UI
—
10
Unit interval
799.92
5
800
—
800.08
200
ps
2
3
AC coupling capacitor
C
nF
TX
Notes:
1. Measured at receiver.
2. Each UI is 800 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It is recommended to be placed near the device transmitter outputs.
4. Refer to the RapidIO™ 1x/4x LP Serial Physical Layer Specification, for interpretation of jitter specifications.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
31
Ethernet: Three-Speed Ethernet, MII Management
V
/2
/2
RX_DIFFp-p-max
V
RX_DIFFp-p-min
RX_DIFFp-p-min
0
–V
–V
/2
/2
RX_DIFFp-p-max
1
0
0.275
0.4
0.6
0.725
Time (UI)
Figure 17. SGMII Receiver Input Compliance Mask
D+ Package
Pin
C = TX
TX
Silicon
+ Package
C = TX
D– Package
R = 50 Ω
R = 50 Ω
Pin
Figure 18. SGMII AC Test/Measurement Load
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
32
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
8.4
eTSEC IEEE 1588 AC Specifications
Figure 19 provides the data and command output timing diagram.
t
T1588CLKOUT
t
T1588CLKOUTH
TSEC_1588_CLK_OUT
t
T1588OV
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
The output delay is count starting rising edge if t
count starting falling edge.
is non-inverting. Otherwise, it is
Note:
T1588CLKOUT
Figure 19. eTSEC IEEE 1588 Output AC Timing
Figure 20 provides the data and command input timing diagram.
t
T1588CLK
t
T1588CLKH
TSEC_1588_CLK
TSEC_1588_TRIG_IN
t
T1588TRIGH
Figure 20. eTSEC IEEE 1588 Input AC Timing
The IEEE 1588 AC timing specifications are in Table 36.
Table 36. eTSEC IEEE 1588 AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
TSEC_1588_CLK clock period
TSEC_1588_CLK duty cycle
t
3.8
40
—
—
50
—
T
× 9
ns
%
1, 3
T1588CLK
RX_CLK
t
/t
60
T1588CLKH T1588CLK
TSEC_1588_CLK peak-to-peak
jitter
t
250
2.0
2.0
—
ps
T1588CLKINJ
Rise time eTSEC_1588_CLK
(20%–80%)
t
1.0
1.0
—
—
—
50
—
ns
ns
ns
%
T1588CLKINR
Fall time eTSEC_1588_CLK
(80%–20%)
t
T1588CLKINF
TSEC_1588_CLK_OUT clock
period
t
t
2 × t
T1588CLK
T1588CLKOUT
TSEC_1588_CLK_OUT duty cycle
30
70
T1588CLKOTH
/t
T1588CLKOUT
TSEC_1588_PULSE_OUT
t
0.5
3.0
ns
T1588OV
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
33
Ethernet: Three-Speed Ethernet, MII Management
Table 36. eTSEC IEEE 1588 AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
TSEC_1588_TRIG_IN pulse width
t
2 × t
—
—
ns
2
T1588TRIGH
T1588CLK_MAX
Notes:
1.T
is the max clock period of eTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the MPC8313E
RX_CLK
PowerQUICC™ II Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers.
2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8313E PowerQUICC™
II Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers.
3. The maximum value of t
is not only defined by the value of T
, but also defined by the recovered clock. For
T1588CLK
RX_CLK
example, for 10/100/1000 Mbps modes, the maximum value of t
is 3600, 280, and 56 ns, respectively.
T1588CLK
8.5
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
MII, RMII, RGMII, SGMII, and RTBI are specified in Section 8.1, “Enhanced Three-Speed Ethernet
Controller (eTSEC) (10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI Electrical Characteristics.”
8.5.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 2.5 V or 3.3 V. Table 37 and Table 38
provide the DC electrical characteristics for MDIO and MDC.
Table 37. MII Management DC Electrical Characteristics When Powered at 2.5 V
Parameter
Symbol
/NV
Conditions
Min
Max
Unit
Supply voltage (2.5 V)
Output high voltage
NV
—
2.37
2.00
2.63
V
V
DDA
DDB
V
I
= –1.0 mA
NV
or NV
= Min
NV
NV
+ 0.3
DDA
or
OH
OH
DDA
DDB
+ 0.3
DDB
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Note:
V
I
= 1.0 mA
—
NV
NV
NV
or NV
or NV
or NV
= Min
= Min
= Min
V – 0.3
SS
0.40
—
V
V
OL
OL
DDA
DDA
DDA
DDB
DDB
DDB
V
1.7
–0.3
—
IH
V
—
0.70
10
V
IL
1
I
V
= NV
or NV
DDB
μA
μA
IH
IN
DDA
DDA
I
V
= NV
or NV
DDB
–15
—
IL
IN
1. Note that the symbol V , in this case, represents the LV symbol referenced in Table 1 and Table 2.
IN
IN
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
34
Ethernet: Three-Speed Ethernet, MII Management
Table 38. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Symbol
/NV
Conditions
Min
Max
Unit
Supply voltage (3.3 V) NV
Output high voltage
—
2.97
2.10
3.63
V
V
DDA
DDB
V
I
= –1.0 mA
= 1.0 mA
NV
LV
or NV
= Min
= Min
NV
NV
+ 0.3
DDA
or
OH
OH
DDA
DDA
DDB
+ 0.3
DDB
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Note:
V
I
or LV
V
SS
0.50
—
V
V
OL
OL
DDB
V
—
—
2.0
—
IH
V
0.80
40
V
IL
1
I
NV
NV
or NV
or NV
= Max
V
= 2.1 V
= 0.5 V
—
μA
μA
IH
DDA
DDA
DDB
DDB
IN
I
= Max
V
–600
—
IL
IN
1. Note that the symbol V , in this case, represents the LV symbol referenced in Table 1 and Table 2.
IN
IN
8.5.2
MII Management AC Electrical Specifications
Table 39 provides the MII management AC timing specifications.
Table 39. MII Management AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB is 3.3 V ± 0.3V or 2.5 V ± 5%
1
Parameter/Condition
MDC frequency
Symbol
Min
Typ
Max
Unit
Notes
f
t
—
—
32
10
5
2.5
400
—
—
—
MHz
ns
2
MDC
MDC
MDC period
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
t
—
ns
MDCH
t
—
170
—
ns
MDKHDX
t
—
ns
MDDVKH
MDDXKH
t
0
—
—
ns
t
—
—
—
10
10
ns
MDCR
MDC fall time
t
—
ns
MDHF
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes management
(first two letters of functional block)(reference)(state)(signal)(state)
MDKHDX
data timing (MD) for the time t
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
MDC
Also, t
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
MDDVKH
(V) relative to the t
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
MDC
convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt Clock Select] field determines the clock frequency
of the Mgmt Clock EC_MDC.)
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
35
High-Speed Serial Interfaces (HSSI)
Figure 21 shows the MII management AC timing diagram.
t
t
MDCR
MDC
MDC
t
t
MDCF
MDCH
MDIO
(Input)
t
MDDVKH
t
MDDXKH
MDIO
(Output)
t
MDKHDX
Figure 21. MII Management Interface Timing Diagram
9 High-Speed Serial Interfaces (HSSI)
This section describes the common portion of SerDes DC electrical specifications, which is the DC
requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits
are also shown.
9.1
Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 22 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for
description. The figure shows waveform for either a transmitter output (TXn and TXn) or a receiver input
(RXn and RXn). Each signal swings between A volts and B volts where A > B.
Using this waveform, the definitions are as follows. To simplify illustration, the following definitions
assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling
environment.
1. Single-ended swing
The transmitter output signals and the receiver input signals TXn, TXn, RXn, and RXn each have
a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s single-ended swing.
2. Differential output voltage, V (or differential output swing):
OD
The differential output voltage (or swing) of the transmitter, V , is defined as the difference of
OD
the two complimentary output voltages: V
negative.
– V
The V value can be either positive or
TXn
TXn. OD
3. Differential input voltage, V (or differential input swing):
ID
The differential input voltage (or swing) of the receiver, V , is defined as the difference of the two
ID
complimentary input voltages: V
– V
. The V value can be either positive or negative.
RXn
RXn ID
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
36
High-Speed Serial Interfaces (HSSI)
4. Differential peak voltage, V
DIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal
is defined as differential peak voltage, V = |A – B| volts.
DIFFp
5. Differential peak-to-peak, V
DIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter
output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,
V
= 2 × V
= 2 × |(A – B)| volts, which is twice of differential swing in amplitude, or
DIFFp-p
DIFFp
twice of the differential peak. For example, the output differential peak-peak voltage can also be
calculated as V = 2 × |V |.
TX-DIFFp-p
OD
6. Differential waveform
The differential waveform is constructed by subtracting the inverting signal (TXn, for example)
from the non-inverting signal (TXn, for example) within a differential pair. There is only one signal
trace curve in a differential waveform. The voltage represented in the differential waveform is not
referenced to ground. Refer to Figure 31 as an example for differential waveform.
7. Common mode voltage, V
cm
The common mode voltage is equal to one half of the sum of the voltages between each conductor
of a balanced interchange circuit and ground. In this example, for SerDes output, V
=
cm_out
(V
+ V )/2 = (A + B)/2, which is the arithmetic mean of the two complimentary output
TXn
TXn
voltages within a differential pair. In a system, the common mode voltage may often differ from
one component’s output to the other’s input. Sometimes, it may be even different between the
receiver input and driver output circuits within the same component. It’s also referred as the DC
offset in some occasion.
TXn or RXn
A Volts
V
= (A + B)/2
cm
TXn or RXn
B Volts
Differential Swing, V or V = A – B
ID
OD
Differential Peak Voltage, V
= |A – B|
DIFFp
Differential Peak-Peak Voltage, V
= 2*V
(not shown)
DIFFpp
DIFFp
Figure 22. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (current mode logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or
TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the
differential signaling environment is fully symmetrical, the transmitter output’s differential swing (V
)
OD
has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between
500 and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other phase. The peak
OD
differential voltage (V
) is 500 mV. The peak-to-peak differential voltage (V
) is 1000 mV p-p.
DIFFp
DIFFp-p
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
37
High-Speed Serial Interfaces (HSSI)
9.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks input is SD_REF_CLK and SD_REF_CLK
for SGMII interface.
The following sections describe the SerDes reference clock requirements and some application
information.
9.2.1
SerDes Reference Clock Receiver Characteristics
Figure 23 shows a receiver reference diagram of the SerDes reference clocks.
•
•
The supply voltage requirements for XCOREV are specified in Table 1 and Table 2.
DD
SerDes reference clock receiver reference circuit structure:
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown
in Figure 23. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-Ω
termination to XCOREV followed by on-chip AC coupling.
SS
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
differential mode and single-ended mode description below for further detailed requirements.
•
The maximum average current requirement that also determines the common mode voltage range:
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above XCOREV .
SS
For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output
driven by its current source from 0 to 16 mA (0–0.8 V), such that each phase of the differential
input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.
— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 Ω to
XCOREV DC, or it exceeds the maximum input current limitations, then it must be
SS
AC-coupled off-chip.
•
The input amplitude requirement. This requirement is described in detail in the following sections.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
38
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
50 Ω
SDn_REF_CLK
SDn_REF_CLK
Input
Amp
50 Ω
Figure 23. Receiver of SerDes Reference Clocks
9.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8313E SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
•
Differential mode
— The input amplitude of the differential clock must be between 400 and 1600 mV differential
peak-to-peak (or between 200 and 800 mV differential peak). In other words, each signal wire
of the differential pair must have a single-ended swing less than 800 mV and greater than
200 mV. This requirement is the same for both external DC-coupled or AC-coupled
connection.
— For external DC-coupled connection, as described in Section 9.2.1, “SerDes Reference Clock
Receiver Characteristics,” the maximum average current requirements sets the requirement for
average voltage (common mode voltage) to be between 100 and 400 mV. Figure 24 shows the
SerDes reference clock input requirement for the DC-coupled connection scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
XCOREV . Each signal wire of the differential inputs is allowed to swing below and above
SS
the command mode voltage (XCOREV ). Figure 25 shows the SerDes reference clock input
SS
requirement for AC-coupled connection scheme.
•
Single-ended mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude
(single-ended swing) must be between 400 and 800 mV peak-to-peak (from V to V ) with
min
max
SD_REF_CLK either left unconnected or tied to ground.
— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 26 shows
the SerDes reference clock input requirement for the single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
AC coupled externally. For the best noise performance, the reference of the clock could be DC
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
39
High-Speed Serial Interfaces (HSSI)
or AC coupled into the unused phase (SD_REF_CLK) through the same source impedance as
the clock input (SD_REF_CLK) in use.
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK
V
< 800 mV
max
100 mV < V < 400 mV
cm
V
> 0 V
min
SD_REF_CLK
Figure 24. Differential Reference Clock Input DC Requirements (External DC-Coupled)
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK
V
< V + 400 mV
max cm
V
cm
SD_REF_CLK
V
> V – 400 mV
min cm
Figure 25. Differential Reference Clock Input DC Requirements (External AC-Coupled)
400 mV < SD_REF_CLK Input Amplitude < 800 mV
SD_REF_CLK
0 V
SD_REF_CLK
Figure 26. Single-Ended Reference Clock Input DC Requirements
9.2.3
Interfacing With Other Differential Signaling Levels
•
With on-chip termination to XCOREV , the differential reference clocks inputs are HCSL
SS
(high-speed current steering logic) compatible DC coupled.
•
•
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC coupled due to the limited common mode input range allowed (100
to 400 mV) for DC-coupled connection.
LVPECL outputs can produce a signal with too large of an amplitude and may need to be
DC-biased at the clock driver output first, then followed with series attenuation resistor to reduce
the amplitude, in addition to AC coupling.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
40
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
NOTE
Figure 27 to Figure 30 are for conceptual reference only. Due to the fact that
the clock driver chip's internal structure, output impedance, and termination
requirements are different between various clock driver chip manufacturers,
it is possible that the clock circuit reference designs provided by clock
driver chip vendors are different from what is shown in the figures. They
might also vary from one vendor to the other. Therefore, Freescale can
neither provide the optimal clock driver reference circuits, nor guarantee the
correctness of the following clock driver connection reference circuits. It is
recommended that the system designer contact the selected clock driver
chip vendor for the optimal reference circuits for the MPC8313E SerDes
reference clock receiver requirement provided in this document.
Figure 27 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with MPC8313E SerDes reference clock
input’s DC requirement.
HCSL CLK Driver Chip
MPC8313E
50 Ω
CLK_Out
SDn_REF_CLK
33 Ω
33 Ω
SerDes Refer.
CLK Receiver
100 Ω Differential PWB Trace
Clock Driver
CLK_Out
SDnn_REF_CLK
50 Ω
Clock driver vendor dependent
source termination resistor
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
Figure 27. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 28 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common mode voltage is higher than the MPC8313E SerDes reference clock
input’s allowed range (100 to 400 mV), the AC-coupled connection scheme must be used. It assumes the
LVDS output driver features a 50-Ω termination resistor. It also assumes that the LVDS transmitter
establishes its own common mode level without relying on the receiver or other external component.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
41
High-Speed Serial Interfaces (HSSI)
LVDS CLK Driver Chip
MPC8313E
50 Ω
CLK_Out
SDn_REF_CLK
SDn_REF_CLK
10 nF
SerDes Refer.
CLK Receiver
100 Ω Differential PWB Trace
Clock Driver
10 nF
CLK_Out
50 Ω
Figure 28. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
Figure 29 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with
the MPC8313E SerDes reference clock input’s DC requirement, AC coupling has to be used. Figure 29
assumes that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL
outputs prior to AC coupling. Its value could be ranged from 140 to 240 Ω depending on the clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8313E
SerDes3 reference clock’s differential input amplitude requirement (between 200 and 800 mV differential
peak). For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference
clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω.
Consult with the clock driver chip manufacturer to verify whether this connection scheme is compatible
with a particular clock driver chip.
LVPECL CLK Driver Chip
MPC8313E
50 Ω
SDn_REF_CLK
10 nF
CLK_Out
R2
SerDes Refer.
CLK Receiver
R1
R1
100 Ω Differential PWB Trace
10 nF
Clock Driver
CLK_Out
R2
SDn_REF_CLK
50 Ω
Figure 29. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
42
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 30 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with the MPC8313E SerDes reference clock
input’s DC requirement.
Single-Ended CLK
Driver Chip
MPC8313E
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
SDn_REF_CLK
33 Ω
Clock Driver
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω Differential PWB Trace
SDn_REF_CLK
50 Ω
50 Ω
Figure 30. Single-Ended Connection (Reference Only)
9.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low-phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 40 describes some AC parameters for SGMII protocol.
Table 40. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.0 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising edge rate
Falling edge rate
Rise edge rate
Fall edge rate
1.0
1.0
4.0
4.0
V/ns
V/ns
mV
2, 3
2, 3
2
Differential input high voltage
Differential input low voltage
V
+200
—
—
IH
V
–200
mV
2
IL
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
43
High-Speed Serial Interfaces (HSSI)
Table 40. SerDes Reference Clock Common AC Parameters (continued)
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.0 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Rise-fall
matching
—
20
%
1, 4
Notes:
1. Measurement taken from single-ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 31.
4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
200 mV window centered on the median cross point, where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge
rate of SDn_REF_CLK should be compared to the fall edge rate of SDn_REF_CLK, the maximum allowed difference should
not exceed 20% of the slowest edge rate. See Figure 32.
Rise Edge Rage
Fall Edge Rate
V
= +200 mV
0.0 V
IH
V
= –200 mV
IL
SDn_REF_CLK
Minus
SDn_REF_CLK
Figure 31. Differential Measurement Points for Rise and Fall Time
T
T
RISE
FALL
SDn_REF_CLK
SDn_REF_CLK
V
V
+ 100 mV
CROSS MEDIAN
V
V
CROSS MEDIAN
CROSS MEDIAN
– 100 mV
CROSS MEDIAN
SDn_REF_CLK
SDn_REF_CLK
Figure 32. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol
based on application usage. Refer to the following section for detailed information:
•
Section 8.3.2, “AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK
9.2.4.1 Spread Spectrum Clock
SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread
spectrum clock source.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
44
Freescale Semiconductor
USB
9.3
SerDes Transmitter and Receiver Reference Circuits
Figure 33 shows the reference circuits for the SerDes data lane’s transmitter and receiver.
RXn
TXn
50 Ω
50 Ω
50 Ω
Receiver
Transmitter
50 Ω
TXn
RXn
Figure 33. SerDes Transmitter and Receiver Reference Circuits
The SerDes data lane’s DC and AC specifications are defined in the interface protocol section listed below
(SGMII) based on the application usage:
•
Section 8.3, “SGMII Interface Electrical Characteristics
Please note that a external AC-coupling capacitor is required for the above serial transmission protocol
with the capacitor value defined in the specifications of the protocol section.
10 USB
10.1 USB Dual-Role Controllers
This section provides the AC and DC electrical specifications for the USB interface.
10.1.1 USB DC Electrical Characteristics
Table 41 provides the DC electrical characteristics for the USB interface.
Table 41. USB DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
+ 0.3
DDB
Unit
V
2.0
–0.3
—
LV
V
V
IH
Low-level input voltage
Input current
V
I
0.8
±5
—
IL
μA
V
IN
High-level output voltage, I = –100 μA
V
LV
– 0.2
DDB
OH
OH
Low-level output voltage, I = 100 μA
V
—
0.2
V
OL
OL
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
45
USB
10.1.2 USB AC Electrical Specifications
Table 42 describes the general timing parameters of the USB interface.
Table 42. USB General Timing Parameters (ULPI Mode Only)
1
Parameter
Symbol
Min
Max
Unit
Notes
USB clock cycle time
t
15
4
—
—
—
7
ns
ns
ns
ns
ns
USCK
Input setup to USB clock—all inputs
input hold to USB clock—all inputs
USB clock to output valid—all outputs
Output hold from USB clock—all outputs
Note:
t
USIVKH
USIXKH
t
1
t
t
—
2
USKHOV
USKHOX
—
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes USB timing
(first two letters of functional block)(reference)(state)(signal)(state)
USIXKH
(USB) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, t
USKHOX
symbolizes us timing (USB) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or
output hold time.
Figure 34 and Figure 35 provide the AC test load and signals for the USB, respectively.
Output
NV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 34. USB AC Test Load
USBDR_CLK
t
USIXKH
t
USIVKH
Input Signals
t
t
USKHOV
USKHOX
Output Signals
Figure 35. USB Signals
10.2 On-Chip USB PHY
This section describes the DC and AC electrical specifications for the on-chip USB PHY of the
MPC8313E. See Chapter 7 in the USB Specifications Rev. 2, for more information.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
46
Freescale Semiconductor
Enhanced Local Bus
Table 43 provides the USB clock input (USB_CLK_IN) DC timing specifications.
Table 43. USB_CLK_IN DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Input high voltage
Input low voltage
V
2.7
NV + 0.3
V
V
IH
DD
V
–0.3
0.4
IL
Table 44 provides the USB clock input (USB_CLK_IN) AC timing specifications.
Table 44. USB_CLK_IN AC Timing Specifications
Parameter/Condition
Frequency range
Conditions
Symbol
Min
Typ
Max
Unit
—
—
f
—
–0.05
40
24
0
48
0.05
60
MHz
%
USB_CLK_IN
Clock frequency tolerance
Reference clock duty cycle
t
CLK_TOL
Measured at 1.6 V
t
50
—
%
CLK_DUTY
Total input jitter/time interval
error
Peak-to-peak value measured with a
second order high-pass filter of 500 kHz
bandwidth
t
—
200
ps
CLK_PJ
11 Enhanced Local Bus
This section describes the DC and AC electrical specifications for the local bus interface.
11.1 Local Bus DC Electrical Characteristics
Table 45 provides the DC electrical characteristics for the local bus interface.
Table 45. Local Bus DC Electrical Characteristics at 3.3 V
Parameter
High-level input voltage for Rev 1.0
Symbol
Min
Max
LV + 0.3
Unit
V
V
2.0
2.1
–0.3
—
V
V
IH
IH
DD
High-level input voltage for Rev 2.x or later
LV + 0.3
DD
Low-level input voltage
V
I
0.8
±5
—
V
IL
1
Input current, (V
= 0 V or V = LV
)
μA
V
IN
IN
DD
IN
High-level output voltage, (LV = min, I
= –2 mA)
= 2 mA)
V
LV – 0.2
DD
OH
OH
OH
DD
Low-level output voltage, (LV = min, I
V
—
0.2
V
DD
OL
Note: The parameters stated in above table are valid for all revisions unless explicitly mentioned.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
47
Enhanced Local Bus
11.2 Local Bus AC Electrical Specifications
Table 46 describes the general timing parameters of the local bus interface.
Table 46. Local Bus General Timing Parameters
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus cycle time
t
15
7
—
—
—
—
—
—
3.0
—
—
—
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
3, 4
3, 4
5
LBK
Input setup to local bus clock
t
t
LBIVKH
LBIXKH
Input hold from local bus clock
1.0
1.5
3
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
LALE output rise to LCLK negative edge
LALE output fall to LCLK negative edge
LALE output fall to LCLK negative edge
LALE output fall to LCLK negative edge
Local bus clock to output valid
t
t
t
LBOTOT1
LBOTOT2
LBOTOT3
LALEHOV
6
2.5
—
7
t
t
t
t
–1.5
–5.0
–4.5
—
5
6
7
3
8
LALETOT1
LALETOT2
LALETOT3
t
t
LBKHOV
Local bus clock to output high impedance for LAD
Notes:
—
4
LBKHOZ
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes local bus
(first two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one (1).
clock reference (K) goes high (H), in this case for
LBK
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from NV /2 of the rising/falling edge of LCLK0 to 0.4 × NV of the signal in question for 3.3-V
DD
DD
signaling levels.
4. Input timings are measured at the pin.
5.t
6.t
7.t
and t
should be used when RCWH[LALE] is not set and the load on LALE output pin is at least 10 pF less
LBOTOT1
LALETOT1
than the load on LAD output pins.
and t should be used when RCWH[LALE] is set and the load on LALE output pin is at least 10 pF less than
LBOTOT2
LALETOT2
the load on LAD output pins.
and t should be used when RCWH[LALE] is set and the load on LALE output pin equals to the load on LAD
LBOTOT3
LALETOT3
output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Figure 36 provides the AC test load for the local bus.
Output
NV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 36. Local Bus AC Test Load
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
48
Freescale Semiconductor
Enhanced Local Bus
Figure 37 through Figure 40 show the local bus signals.
LCLK[n]
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:15]
t
LBIXKH
t
LBIVKH
Input Signal:
LGTA
t
LBIXKH
t
LBKHOV
Output Signals:
LBCTL/LBCKE/LOE
t
LBKHOZ
t
LBKHOV
Output Signals:
LAD[0:15]
t
LBOTOT
LALE
Figure 37. Local Bus Signals, Non-Special Signals Only
LCLK
T1
T3
t
LBKHOZ
t
LBKHOV
GPCM Mode Output Signals:
LCS[0:3]/LWE
t
LBIXKH
t
LBIVKH
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:15]
t
LBKHOZ
t
LBKHOV
UPM Mode Output Signals:
LCS[0:3]/LBS[0:1]/LGPL[0:5]
Figure 38. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
49
Enhanced Local Bus
LCLK
T1
T2
T3
T4
t
LBKHOZ
t
LBKHOV
GPCM Mode Output Signals:
LCS[0:3]/LWE
t
LBIXKH
t
LBIVKH
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:15]
t
LBKHOZ
t
LBKHOV
UPM Mode Output Signals:
LCS[0:3]/LBS[0:1]/LGPL[0:5]
Figure 39. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4
LCLK[n]
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:15]
t
t
LBIXKH
LBIXKH
t
LBIVKH
Input Signal:
LGTA
t
LBKHOV
Output Signals:
LBCTL/LBCKE/LOE
t
LBKHOZ
t
LBKHOV
Output Signals:
LAD[0:15]
t
LBOTOT
t
t
LALEHOV
LALETOT
LALE
Figure 40. Local Bus Signals, LALE with Respect to LCLK
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
50
Freescale Semiconductor
JTAG
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std 1149.1™ (JTAG)
interface.
12.1 JTAG DC Electrical Characteristics
Table 47 provides the DC electrical characteristics for the IEEE Std 1149.1 (JTAG) interface.
Table 47. JTAG Interface DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
V
—
—
—
2.1
–0.3
—
NV + 0.3
V
V
IH
DD
Input low voltage
Input current
V
I
0.8
±5
IL
μA
V
IN
Output high voltage
Output low voltage
Output low voltage
V
I
= –8.0 mA
OH
2.4
—
—
OH
V
I
= 8.0 mA
= 3.2 mA
OL
0.5
0.4
V
OL
OL
V
I
—
V
OL
12.2 JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE Std 1149.1 (JTAG) interface.
Table 48 provides the JTAG AC timing specifications as defined in Figure 42 through Figure 45.
1
Table 48. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)
At recommended operating conditions (see Table 2).
2
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
f
0
33.3
—
MHz
ns
JTG
t
30
15
0
JTG
t
—
ns
JTKHKL
t
& t
2
ns
JTGR
JTGF
t
25
—
ns
3
4
TRST
Input setup times:
ns
Boundary-scan data
t
t
4
4
—
—
JTDVKH
TMS, TDI
JTIVKH
Input hold times:
Valid times:
ns
ns
Boundary-scan data
TMS, TDI
t
t
10
10
—
—
4
5
JTDXKH
JTIXKH
Boundary-scan data
TDO
t
t
2
2
11
11
JTKLDV
JTKLOV
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
51
JTAG
1
Table 48. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) (continued)
At recommended operating conditions (see Table 2).
2
Parameter
Symbol
Min
Max
Unit
Notes
Output hold times:
Boundary-scan data
TDO
t
t
2
2
—
—
ns
5
JTKLDX
JTKLOX
JTAG external clock to output high impedance:
Boundary-scan data
TDO
t
t
2
2
19
9
ns
5, 6
JTKLDZ
JTKLOZ
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
to the midpoint of the signal in question.
TCLK
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 34).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes JTAG device
(first two letters of functional block)(reference)(state)(signal)(state)
JTDVKH
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
clock reference (K)
JTG
going to the high (H) state or setup time. Also, t
symbolizes JTAG timing (JT) with respect to the time data input signals
JTDXKH
(D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
JTG
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
.
TCLK
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
.
TCLK
Figure 41 provides the AC test load for TDO and the boundary-scan outputs.
Output
NV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 41. AC Test Load for the JTAG Interface
Figure 42 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
t
VM
VM
t
JTGR
JTKHKL
t
t
JTGF
JTG
VM = Midpoint Voltage (NV /2)
DD
Figure 42. JTAG Clock Input Timing Diagram
Figure 43 provides the TRST timing diagram.
TRST
VM
VM
t
TRST
VM = Midpoint Voltage (NV /2)
DD
Figure 43. TRST Timing Diagram
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
52
Freescale Semiconductor
JTAG
Figure 44 provides the boundary-scan timing diagram.
JTAG
External Clock
VM
VM
t
JTDVKH
t
JTDXKH
Boundary
Data Inputs
Input
Data Valid
t
JTKLDV
t
JTKLDX
Boundary
Data Outputs
Output Data Valid
t
JTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (NV /2)
DD
Figure 44. Boundary-Scan Timing Diagram
Figure 45 provides the test access port timing diagram.
JTAG
VM
VM
External Clock
t
JTIVKH
t
JTIXKH
Input
TDI, TMS
TDO
Data Valid
t
JTKLOV
t
JTKLOX
Output Data Valid
t
JTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (NV /2)
DD
Figure 45. Test Access Port Timing Diagram
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
53
I2C
13 I2C
2
This section describes the DC and AC electrical characteristics for the I C interface.
2
13.1 I C DC Electrical Characteristics
2
Table 49 provides the DC electrical characteristics for the I C interface.
2
Table 49. I C DC Electrical Characteristics
At recommended operating conditions with NVDD of 3.3 V ± 0.3 V.
Parameter
Input high voltage level
Symbol
Min
Max
Unit
Notes
V
0.7 × NV
–0.3
0
NV + 0.3
V
V
IH
DD
DD
Input low voltage level
V
0.3 × NV
IL
DD
Low level output voltage
V
0.2 × NV
V
1
2
OL
DD
Output fall time from V (min) to V (max) with a bus
t
20 + 0.1 × C
B
250
ns
IH
IL
I2KLKV
capacitance from 10 to 400 pF
Pulse width of spikes which must be suppressed by
the input filter
t
0
50
ns
3
4
I2KHKL
Capacitance for each I/O pin
C
I
—
—
10
pF
I
Input current, (0 V ≤ V ≤ NV
)
± 5
μA
IN
DD
IN
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. C = capacitance of one bus line in pF.
B
3. Refer to the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, for information on the digital
filter used.
4. I/O pins obstruct the SDA and SCL lines if NV is switched off.
DD
2
13.2 I C AC Electrical Specifications
2
Table 50 provides the AC timing parameters for the I C interface.
2
Table 50. I C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 49).
1
Parameter
Symbol
Min
Max
Unit
SCL clock frequency
f
0
400
—
kHz
μs
I2C
Low period of the SCL clock
High period of the SCL clock
t
1.3
0.6
0.6
0.6
I2CL
I2CH
t
—
μs
Setup time for a repeated START condition
t
—
μs
I2SVKH
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
t
—
μs
I2SXKL
Data setup time
t
100
—
ns
I2DVKH
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
54
Freescale Semiconductor
I2C
2
Table 50. I C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 49).
1
Parameter
Symbol
Min
Max
Unit
Data hold time:
t
μs
I2DXKL
CBUS compatible masters
—
0
—
0.9
2
2
3
I C bus devices
5
Fall time of both SDA and SCL signals
Setup time for STOP condition
t
—
0.6
300
—
ns
μs
μs
V
I2CF
t
I2PVKH
Bus free time between a STOP and START condition
t
1.3
—
I2KHDX
Noise margin at the LOW level for each connected device (including
hysteresis)
V
0.1 × NV
—
NL
DD
DD
Noise margin at the HIGH level for each connected device (including
hysteresis)
V
0.2 × NV
—
V
NH
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
2
inputs and t
for outputs. For example, t
symbolizes I C timing (I2)
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
with respect to the time data input signals (D) reach the valid state (V) relative to the t clock reference (K) going to the high
I2C
2
(H) state or setup time. Also, t
symbolizes I C timing (I2) for the time that the data with respect to the start condition
clock reference (K) going to the low (L) state or hold time. Also, t
I2SXKL
2
(S) went invalid (X) relative to the t
symbolizes I C
I2C
I2PVKH
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t clock
I2C
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. The MPC8313E provides a hold time of at least 300 ns for the SDA signal (referred to the V
the undefined region of the falling edge of SCL.
of the SCL signal) to bridge
IHmin
3. The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
I2DVKH
I2CL
4. C = capacitance of one bus line in pF.
B
2
5. The MPC8313E does not follow the I C-BUS Specifications, Version 2.1, regarding the t
AC parameter.
I2CF
2
Figure 46 provides the AC test load for the I C.
Output
NV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
2
Figure 46. I C AC Test Load
2
Figure 47 shows the AC timing diagram for the I C bus.
SDA
t
t
t
t
I2CF
I2CF
I2DVKH
I2KHKL
t
t
t
I2CR
I2CL
I2SXKL
SCL
t
t
t
t
I2PVKH
I2SXKL
I2CH
I2SVKH
t
S
Sr
P
I2DXKL
S
2
Figure 47. I C Bus AC Timing Diagram
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
55
PCI
14 PCI
This section describes the DC and AC electrical specifications for the PCI bus.
14.1 PCI DC Electrical Characteristics
Table 51 provides the DC electrical characteristics for the PCI interface.
1
Table 51. PCI DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
V
V
≥ V (min) or
0.5 × NV
–0.5
NV + 0.3
V
V
IH
OUT
OH
DD
DD
V
V
≤ V (max)
0.3 × NV
IL
OUT
OL
DD
V
NV = min, I = –100 μA
0.9 × NV
—
—
V
OH
DD
OH
DD
V
NV = min, I = 100 μA
0.1 × NV
V
OL
DD
OL
DD
I
0 V ≤ V ≤ NV
DD
—
±5
μA
IN
IN
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
14.2 PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus. Note that the PCI_CLK or
PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8313E is configured
as a host or agent device.
Table 52 shows the PCI AC timing specifications at 66 MHz.
.
Table 52. PCI AC Timing Specifications at 66 MHz
1
Parameter
Symbol
Min
Max
Unit
Notes
Clock to output valid
t
—
1
6.0
—
ns
ns
ns
ns
ns
2
PCKHOV
Output hold from clock
Clock to output high impedance
Input setup to clock
Input hold from clock
Notes:
2
t
PCKHOX
t
—
3.0
0
14
—
2, 3
2, 4
2, 4
PCKHOZ
t
PCIVKH
t
—
PCIXKH
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes PCI timing
(first two letters of functional block)(reference)(state)(signal)(state)
PCIVKH
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t
, reference
SYS
(K) going to the high (H) state or setup time. Also, t
symbolizes PCI timing (PC) with respect to the time hard reset
PCRHFV
(R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
56
Freescale Semiconductor
PCI
Table 53 shows the PCI AC timing specifications at 33 MHz.
Table 53. PCI AC Timing Specifications at 33 MHz
1
Parameter
Symbol
Min
Max
Unit
Notes
Clock to output valid
t
—
2
11
—
14
—
—
ns
ns
ns
ns
ns
2
PCKHOV
PCKHOX
Output hold from clock
Clock to output high impedance
Input setup to clock
Input hold from clock
Notes:
2
t
t
—
3.0
0
2, 3
2, 4
2, 4
PCKHOZ
t
PCIVKH
PCIXKH
t
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes PCI timing
(first two letters of functional block)(reference)(state)(signal)(state)
PCIVKH
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t
, reference
SYS
(K) going to the high (H) state or setup time. Also, t
symbolizes PCI timing (PC) with respect to the time hard reset
PCRHFV
(R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
Figure 48 provides the AC test load for PCI.
Output
NV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 48. PCI AC Test Load
Figure 49 shows the PCI input AC timing conditions.
CLK
t
PCIVKH
t
PCIXKH
Input
Figure 49. PCI Input AC Timing Measurement Conditions
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
57
Timers
Figure 50 shows the PCI output AC timing conditions.
CLK
t
PCKHOV
t
PCKHOX
Output Delay
t
PCKHOZ
High-Impedance
Output
Figure 50. PCI Output AC Timing Measurement Condition
15 Timers
This section describes the DC and AC electrical specifications for the timers.
15.1 Timers DC Electrical Characteristics
Table 54 provides the DC electrical characteristics for the MPC8313E timers pins, including TIN, TOUT,
TGATE, and RTC_CLK.
Table 54. Timers DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
= –8.0 mA
OH
Min
Max
Unit
V
I
2.4
—
—
V
V
OH
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 8.0 mA
= 3.2 mA
—
0.5
0.4
OL
OL
V
I
—
V
OL
OL
V
2.1
–0.3
—
NV + 0.3
V
IH
DD
V
—
0.8
±5
V
IL
I
0 V ≤ V ≤ NV
DD
μA
IN
IN
15.2 Timers AC Timing Specifications
Table 55 provides the Timers input and output AC timing specifications.
1
Table 55. Timers Input AC Timing Specifications
2
Characteristic
Symbol
Min
Unit
Timers inputs—minimum pulse width
Notes:
t
20
ns
TIWID
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any
external synchronous logic. Timers inputs are required to be valid for at least t
ns to ensure proper operation
TIWID
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
58
Freescale Semiconductor
GPIO
Figure 51 provides the AC test load for the Timers.
Output
Z = 50 Ω
0
NV /2
DD
R = 50 Ω
L
Figure 51. Timers AC Test Load
16 GPIO
This section describes the DC and AC electrical specifications for the GPIO.
16.1 GPIO DC Electrical Characteristics
Table 56 provides the DC electrical characteristics for the GPIO when the GPIO pins are operating from
a 3.3-V supply.
1
Table 56. GPIO (When Operating at 3.3 V) DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
= –8.0 mA
OH
Min
Max
Unit
V
I
2.4
—
—
V
V
OH
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
I
= 8.0 mA
= 3.2 mA
—
0.5
0.4
OL
OL
V
I
—
V
OL
OL
V
2.0
–0.3
—
NV + 0.3
V
IH
DD
V
—
0.8
±5
V
IL
I
0 V ≤ V ≤ NV
DD
μA
IN
IN
1
This specification only applies to GPIO pins that are operating from a 3.3-V supply. See Table 63 for the power supply listed
for the individual GPIO signal.
Table 57 provides the DC electrical characteristics for the GPIO when the GPIO pins are operating from
a 2.5-V supply.
1
Table 57. GPIO (When Operating at 2.5 V) DC Electrical Characteristics
Parameters
Symbol
NV
Conditions
Min
Max
Unit
Supply voltage 2.5 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
—
2.37
2.00
2.63
V
V
DD
V
I
= –1.0 mA
= 1.0 mA
—
NV = min
NV + 0.3
OH
OH
DD
DD
V
I
NV = min
V – 0.3
SS
0.40
V
OL
OL
DD
V
NV = min
1.7
–0.3
—
NV + 0.3
V
IH
DD
DD
V
I
—
NV = min
0.70
10
V
IL
DD
DD
V
= NV
μA
IH
IN
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
59
IPIC
1
Table 57. GPIO (When Operating at 2.5 V) DC Electrical Characteristics (continued)
Parameters
Input low current
Symbol
Conditions
= V
Min
Max
Unit
I
V
–15
—
μA
IL
IN
SS
1
This specification only applies to GPIO pins that are operating from a 2.5-V supply. See Table 63 for the power supply listed
for the individual GPIO signal.
16.2 GPIO AC Timing Specifications
Table 58 provides the GPIO input and output AC timing specifications.
1
Table 58. GPIO Input AC Timing Specifications
2
Characteristic
Symbol
Min
Unit
GPIO inputs—minimum pulse width
Notes:
t
20
ns
PIWID
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLKIN. Timings
are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least t
ns to ensure proper operation.
PIWID
Figure 52 provides the AC test load for the GPIO.
Output
NV /2
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 52. GPIO AC Test Load
17 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins.
17.1 IPIC DC Electrical Characteristics
Table 59 provides the DC electrical characteristics for the external interrupt pins.
Table 59. IPIC DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
V
—
—
—
2.1
–0.3
—
NV + 0.3
V
V
IH
DD
Input low voltage
Input current
V
I
0.8
±5
IL
μA
V
IN
Output low voltage
Output low voltage
V
I
= 8.0 mA
= 3.2 mA
OL
—
0.5
0.4
OL
OL
V
I
—
V
OL
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
60
SPI
17.2 IPIC AC Timing Specifications
Table 60 provides the IPIC input and output AC timing specifications.
1
Table 60. IPIC Input AC Timing Specifications
2
Characteristic
Symbol
Min
Unit
IPIC inputs—minimum pulse width
t
20
ns
PIWID
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
external synchronous logic. IPIC inputs are required to be valid for at least t
in edge triggered mode.
ns to ensure proper operation when working
PIWID
18 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8313E.
18.1 SPI DC Electrical Characteristics
Table 61 provides the DC electrical characteristics for the MPC8313E SPI.
Table 61. SPI DC Electrical Characteristics
Characteristic
Output high voltage
Symbol
Condition
= –6.0 mA
OH
Min
Max
Unit
V
I
2.4
—
—
V
V
OH
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
V
V
I
= 6.0 mA
= 3.2 mA
—
0.5
0.4
OL
OL
I
—
V
OL
OL
V
2.1
–0.3
—
NV + 0.3
V
IH
DD
V
—
0.8
±5
V
IL
I
0 V ≤ V ≤ NV
DD
μA
IN
IN
18.2 SPI AC Timing Specifications
Table 62 and provide the SPI input and output AC timing specifications.
1
Table 62. SPI AC Timing Specifications
2
Characteristic
Symbol
Min
Max
Unit
SPI outputs—master mode (internal clock) delay
SPI outputs—slave mode (external clock) delay
t
0.5
2
6
8
ns
ns
ns
ns
ns
NIKHOV
t
NEKHOV
SPI inputs—master mode (internal clock) input setup time
SPI inputs—master mode (internal clock) input hold time
SPI inputs—slave mode (external clock) input setup time
t
t
6
—
—
—
NIIVKH
0
NIIXKH
t
4
NEIVKH
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
61
SPI
1
Table 62. SPI AC Timing Specifications
2
Characteristic
Symbol
Min
Max
Unit
SPI inputs—slave mode (external clock) input hold time
t
2
—
ns
NEIXKH
Notes:
1. Output specifications are measured from the 50% level of the rising edge of SYS_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes the NMSI
(first two letters of functional block)(reference)(state)(signal)(state)
NIKHOV
outputs internal timing (NI) for the time t
valid (V).
memory clock reference (K) goes from the high state (H) until outputs (O) are
SPI
Figure 53 provides the AC test load for the SPI.
Output
NV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 53. SPI AC Test Load
Figure 54 through Figure 55 represent the AC timing from Table 62. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 54 shows the SPI timing in slave mode (external clock).
SPICLK (Input)
t
NEIXKH
t
NEIVKH
Input Signals:
SPIMOSI
(See Note)
t
NEKHOV
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 54. SPI AC Timing in Slave Mode (External Clock) Diagram
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
62
Freescale Semiconductor
Package and Pin Listings
Figure 55 shows the SPI timing in master mode (internal clock).
SPICLK (Output)
t
NIIXKH
t
NIIVKH
Input Signals:
SPIMISO
(See Note)
t
NIKHOV
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
Figure 55. SPI AC Timing in Master Mode (Internal Clock) Diagram
19 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8313E is available in
a thermally enhanced plastic ball grid array (TEPBGAII), see Section 19.1, “Package Parameters for the
MPC8313E TEPBGAII,” and Section 19.2, “Mechanical Dimensions of the MPC8313E TEPBGAII,” for
information on the TEPBGAII.
19.1 Package Parameters for the MPC8313E TEPBGAII
The package parameters are as provided in the following list. The package type is 27 mm × 27 mm,
516 TEPBGAII.
Package outline
Interconnects
Pitch
27 mm × 27 mm
516
1.00 mm
2.25 mm
Module height (typical)
Solder Balls
95.5 Sn/0.5 Cu/4 Ag (VR package),
62 Sn/36 Pb/2 Ag (ZQ package)
Ball diameter (typical)
0.6 mm
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
63
Package and Pin Listings
19.2 Mechanical Dimensions of the MPC8313E TEPBGAII
Figure 56 shows the mechanical dimensions and bottom surface nomenclature of the 516-TEPBGAII
package.
Notes:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Package code 5368 is to account for PGE and the built-in heat spreader.
Figure 56. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8313E TEPBGAII
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
64
Freescale Semiconductor
Package and Pin Listings
19.3 Pinout Listings
Table 63 provides the pin-out listing for the MPC8313E, TEPBGAII package.
Table 63. MPC8313E TEPBGAII Pinout Listing
Power
Supply
Signal
Package Pin Number
DDR Memory Controller Interface
Pin Type
Notes
MEMC_MDQ0
MEMC_MDQ1
MEMC_MDQ2
MEMC_MDQ3
MEMC_MDQ4
MEMC_MDQ5
MEMC_MDQ6
MEMC_MDQ7
MEMC_MDQ8
MEMC_MDQ9
MEMC_MDQ10
MEMC_MDQ11
MEMC_MDQ12
MEMC_MDQ13
MEMC_MDQ14
MEMC_MDQ15
MEMC_MDQ16
MEMC_MDQ17
MEMC_MDQ18
MEMC_MDQ19
MEMC_MDQ20
MEMC_MDQ21
MEMC_MDQ22
MEMC_MDQ23
MEMC_MDQ24
MEMC_MDQ25
MEMC_MDQ26
MEMC_MDQ27
MEMC_MDQ28
A8
A9
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
C10
C9
E9
E11
E10
C8
E8
A6
B6
C6
C7
D7
D6
A5
A19
D18
A17
E17
E16
C18
D19
C19
E19
A22
C21
C20
A21
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
65
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
MEMC_MDQ29
MEMC_MDQ30
MEMC_MDQ31
MEMC_MDM0
MEMC_MDM1
MEMC_MDM2
MEMC_MDM3
MEMC_MDQS0
MEMC_MDQS1
MEMC_MDQS2
MEMC_MDQS3
MEMC_MBA0
MEMC_MBA1
MEMC_MBA2
MEMC_MA0
A20
C22
B22
B7
IO
IO
IO
O
O
O
O
IO
IO
IO
IO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
E6
E18
E20
A7
E7
B19
A23
D15
A18
A15
E12
D11
B11
A11
A12
E13
C12
E14
B15
C17
C13
A16
C15
C16
E15
B18
C11
B10
MEMC_MA1
MEMC_MA2
MEMC_MA3
MEMC_MA4
MEMC_MA5
MEMC_MA6
MEMC_MA7
MEMC_MA8
MEMC_MA9
MEMC_MA10
MEMC_MA11
MEMC_MA12
MEMC_MA13
MEMC_MA14
MEMC_MWE
MEMC_MRAS
MEMC_MCAS
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
66
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
MEMC_MCS0
MEMC_MCS1
MEMC_MCKE
MEMC_MCK
D10
A10
B14
A13
A14
B23
C23
O
O
O
O
O
O
O
GV
GV
GV
GV
GV
GV
GV
DD
DD
DD
DD
DD
DD
DD
3
MEMC_MCK
MEMC_MODT0
MEMC_MODT1
Local Bus Controller Interface
LAD0
LAD1
LAD2
LAD3
LAD4
LAD5
LAD6
LAD7
LAD8
LAD9
LAD10
LAD11
LAD12
LAD13
LAD14
LAD15
LA16
K25
K24
K23
K22
J25
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
J24
J23
J22
H24
F26
G24
F25
E25
F24
G22
F23
AC25
AC26
AB22
AB23
AB24
AB25
AB26
E22
LA17
O
LA18
O
LA19
O
LA20
O
LA21
O
LA22
O
LA23
O
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
67
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
LA24
E23
D22
D23
J26
O
O
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
LA25
LCS0
O
LCS1
O
LCS2
F22
O
LCS3
D26
E24
H26
L22
O
LWE0/LFWE
O
LWE1
O
LBCTL
O
LALE/M1LALE/M2LALE
LGPL0/LFCLE
E26
AA23
AA24
AA25
AA26
Y22
E21
H22
G26
AC24
Y24
Y26
W22
W24
W26
V22
V23
V24
V25
V26
U22
AD24
L25
O
O
LGPL1/LFALE
O
LGPL2/LOE/LFRE
LGPL3/LFWP
O
O
LGPL4/LGTA/LUPWAIT/LFRB
LGPL5
IO
O
LCLK0
O
LCLK1
O
LA0/GPIO0/MSRCID0
LA1/GPIO1//MSRCID1
LA2/GPIO2//MSRCID2
LA3/GPIO3//MSRCID3
LA4/GPIO4//MSRCID4
LA5/GPIO5/MDVAL
LA6/GPIO6
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
LA7/GPIO7/TSEC_1588_TRIG2
LA8/GPIO13/TSEC_1588_ALARM1
LA9/GPIO14/TSEC_1588_PP3
LA10/TSEC_1588_CLK
LA11/TSEC_1588_GCLK
LA12/TSEC_1588_PP1
LA13/TSEC_1588_PP2
8
8
8
8
8
8
8
O
O
O
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
68
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
LA14/TSEC_1588_TRIG1
LA15/TSEC_1588_ALARM2
L24
K26
O
O
LV
LV
8
8
DD
DD
DUART
UART_SOUT1/MSRCID0
N2
M5
M1
K1
M3
L1
O
IO
IO
IO
O
NV
NV
NV
NV
NV
NV
NV
NV
DD
DD
DD
DD
DD
DD
DD
DD
UART_SIN1/MSRCID1
UART_CTS1/GPIO8/MSRCID2
UART_RTS1/GPIO9/MSRCID3
UART_SOUT2/MSRCID4/TSEC_1588_CLK
UART_SIN2/MDVAL/TSEC_1588_GCLK
UART_CTS2/TSEC_1588_PP1
UART_RTS2/TSEC_1588_PP2
8
8
8
8
IO
IO
IO
L5
L3
2
I C interface
IIC1_SDA/CKSTOP_OUT/TSEC_1588_TRIG1
IIC1_SCL/CKSTOP_IN/TSEC_1588_ALARM2
IIC2_SDA/PMC_PWR_OK/GPIO10
IIC2_SCL/GPIO11
J4
J2
J3
H5
IO
IO
IO
IO
NV
NV
NV
NV
2, 8
2, 8
2
DD
DD
DD
DD
2
Interrupts
MCP_OUT
G5
K5
K4
K2
K3
J1
O
I
NV
NV
NV
NV
NV
NV
2
DD
DD
DD
DD
DD
DD
IRQ0/MCP_IN
IRQ1
I
IRQ2
I
IRQ3/CKSTOP_OUT
IRQ4/CKSTOP_IN/GPIO12
IO
IO
Configuration
CFG_CLKIN_DIV
EXT_PWR_CTRL
CFG_LBIU_MUX_EN
D5
J5
I
O
I
NV
NV
NV
DD
DD
DD
R24
JTAG
TCK
TDI
E1
E2
E3
I
I
NV
NV
NV
DD
DD
DD
4
3
TDO
O
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
69
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
TMS
E4
E5
I
I
NV
NV
4
4
DD
DD
TRST
TEST
TEST_MODE
QUIESCE
F4
F5
I
NV
NV
6
DD
DD
DEBUG
O
System Control
HRESET
PORESET
SRESET
F2
F3
F1
IO
NV
NV
NV
1
DD
DD
DD
I
I
Clocks
SYS_CR_CLK_IN
SYS_CR_CLK_OUT
SYS_CLK_IN
U26
U25
U23
T26
R26
T22
U24
R22
T24
I
O
I
NV
NV
NV
NV
NV
NV
NV
NV
NV
DD
DD
DD
DD
DD
DD
DD
DD
DD
USB_CR_CLK_IN
USB_CR_CLK_OUT
USB_CLK_IN
I
O
I
PCI_SYNC_OUT
RTC_PIT_CLOCK
PCI_SYNC_IN
O
I
3
I
MISC
PCI
THERM0
THERM1
N1
N3
I
I
NV
NV
7
7
DD
DD
PCI_INTA
PCI_RESET_OUT
PCI_AD0
AF7
O
O
NV
NV
NV
NV
NV
NV
NV
NV
DD
DD
DD
DD
DD
DD
DD
DD
AB11
AB20
AF23
AF22
AB19
AE22
AF21
IO
IO
IO
IO
IO
IO
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
70
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
PCI_AD6
AD19
AD20
AC18
AD18
AB18
AE19
AB17
AE18
AD17
AF19
AB14
AF15
AD14
AE14
AF12
AE11
AD12
AB13
AF9
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3
PCI_PAR
AD11
AE10
AB12
AD10
AC10
AF10
AF8
AC19
AB15
AF14
AF11
AD16
AF16
PCI_FRAME
5
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
71
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
PCI_TRDY
AD13
AC15
AF13
AC14
AF20
AE15
AD15
AB10
AD9
IO
IO
IO
IO
I
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
5
5
5
5
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
PCI_IRDY
PCI_STOP
PCI_DEVSEL
PCI_IDSEL
PCI_SERR
IO
IO
IO
I
5
5
PCI_PERR
PCI_REQ0
PCI_REQ1/CPCI_HS_ES
PCI_REQ2
AD8
I
PCI_GNT0
AC11
AE7
IO
O
O
I
PCI_GNT1/CPCI_HS_LED
PCI_GNT2/CPCI_HS_ENUM
M66EN
AD7
AD21
AF17
AB16
AF18
AD22
PCI_CLK0
O
O
O
IO
PCI_CLK1
PCI_CLK2
PCI_PME
ETSEC1/_USBULPI
TSEC1_COL/USBDR_TXDRXD0
AD2
AC3
AF3
AE3
AD3
AC6
AF4
AB6
AB5
AD4
AF5
AE6
AC7
IO
IO
IO
IO
IO
IO
IO
IO
I
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
DDB
DDB
DDB
DDB
DDB
DDB
DDB
DDB
DDB
DDB
DDB
DDB
DDB
TSEC1_CRS/USBDR_TXDRXD1
TSEC1_GTX_CLK/USBDR_TXDRXD2
TSEC1_RX_CLK/USBDR_TXDRXD3
TSEC1_RX_DV/USBDR_TXDRXD4
TSEC1_RXD3/USBDR_TXDRXD5
3
TSEC1_RXD2/USBDR_TXDRXD6
TSEC1_RXD1/USBDR_TXDRXD7
TSEC1_RXD0/USBDR_NXT/TSEC_1588_TRIG1
TSEC1_RX_ER/USBDR_DIR/TSEC_1588_TRIG2
TSEC1_TX_CLK/USBDR_CLK/TSEC_1588_CLK
TSEC1_TXD3/TSEC_1588_GCLK
I
I
O
O
TSEC1_TXD2/TSEC_1588_PP1
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
72
Freescale Semiconductor
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
TSEC1_TXD1/TSEC_1588_PP2
TSEC1_TXD0/USBDR_STP/TSEC_1588_PP3
TSEC1_TX_EN/TSEC_1588_ALARM1
TSEC1_TX_ER/TSEC_1588_ALARM2
TSEC1_GTX_CLK125
AD6
AD5
AB7
AB8
AE1
AF6
AB9
O
O
O
O
I
LV
LV
LV
LV
LV
DDB
DDB
DDB
DDB
DDB
TSEC1_MDC/LB_POR_CFG_BOOT_ECC_DIS
TSEC1_MDIO
O
IO
NV
NV
9
2
DD
DD
ETSEC2
TSEC2_COL/GTM1_TIN4/GTM2_TIN3/GPIO15
TSEC2_CRS/GTM1_TGATE4/GTM2_TGATE3/GPIO16
TSEC2_GTX_CLK/GTM1_TOUT4/GTM2_TOUT3/GPIO17
TSEC2_RX_CLK/GTM1_TIN2/GTM2_TIN1/GPIO18
TSCE2_RX_DV/GTM1_TGATE2/GTM2_TGATE1/GPIO19
TSEC2_RXD3/GPIO20
AB4
AB3
AC1
AC2
AA3
Y5
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
TSEC2_RXD2/GPIO21
AA4
AB2
AA5
AA2
AB1
W3
TSEC2_RXD1/GPIO22
TSEC2_RXD0/GPIO23
TSEC2_RX_ER/GTM1_TOUT2/GTM2_TOUT1/GPIO24
TSEC2_TX_CLK/GPIO25
TSEC2_TXD3/CFG_RESET_SOURCE0
TSEC2_TXD2/CFG_RESET_SOURCE1
TSEC2_TXD1/CFG_RESET_SOURCE2
TSEC2_TXD0/CFG_RESET_SOURCE3
TSEC2_TX_EN/GPIO26
Y1
W5
Y3
AA1
W1
TSEC2_TX_ER/GPIO27
SGMII PHY
TXA
TXA
RXA
RXA
TXB
TXB
U3
V3
U1
V1
P4
N4
O
O
I
I
O
O
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
73
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
RXB
R1
P1
V5
I
I
I
RXB
SD_IMP_CAL_RX
200 Ω to
GND
SD_REF_CLK
SD_REF_CLK
SD_PLL_TPD
SD_IMP_CAL_TX
T5
T4
T2
N5
I
I
O
I
100 Ω to
GND
SDAVDD
R5
R4
R3
IO
O
SD_PLL_TPA_ANA
SDAVSS
IO
USB PHY
USB_DP
P26
N26
P24
L26
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
USB_DM
USB_VBUS
USB_TPA
USB_RBIAS
USB_PLL_PWR3
USB_PLL_GND
USB_PLL_PWR1
USB_VSSA_BIAS
USB_VDDA_BIAS
USB_VSSA
M24
M26
N24
N25
M25
M22
N22
P22
USB_VDDA
GTM/USB
USBDR_DRIVE_VBUS/GTM1_TIN1/GTM2_TIN2/LSRCID0
AD23
AE23
IO
IO
NV
NV
DD
DD
USBDR_PWRFAULT/GTM1_TGATE1/GTM2_TGATE2/
LSRCID1
USBDR_PCTL0/GTM1_TOUT1/LSRCID2
USBDR_PCTL1/LBC_PM_REF_10/LSRCID3
AC22
AB21
O
O
NV
NV
DD
DD
SPI
SPIMOSI/GTM1_TIN3/GTM2_TIN4/GPIO28/LSRCID4
H1
IO
NV
DD
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
74
Freescale Semiconductor
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
SPIMISO/GTM1_TGATE3/GTM2_TGATE4/GPIO29/
LDVAL
H3
IO
NV
DD
SPICLK/GTM1_TOUT3/GPIO30
SPISEL/GPIO31
G1
G3
IO
IO
NV
NV
DD
DD
Power and Ground Supplies
AV
AV
F14
P21
Powerfore300
core APLL
(1.0 V)
—
DD1
DD2
Power for
system APLL
(1.0 V)
—
—
GV
A2,A3,A4,A24,A25,B3,
B4,B5,B12,B13,B20,B21,
B24,B25,B26,D1,D2,D8,
D9,D16,D17
Power for
DDR1 and
DDR2 DRAM
I/O voltage
(1.8/2.5 V)
DD
LV
LV
D24,D25,G23,H23,R23, Power for local
—
—
DD
T23,W25,Y25,AA22,AC23
bus (3.3 V)
W2,Y2
Power for
eTSEC2
DDA
DDB
(2.5 V, 3.3 V)
LV
AC8,AC9,AE4,AE5
C14,D14
Power for
eTSEC1/
USB DR
—
(2.5 V, 3.3 V)
MV
Reference
voltage signal
for DDR
—
—
REF
NV
G4,H4,L2,M2,AC16,AC17, Standard I/O
AD25,AD26,AE12,AE13, voltage (3.3 V)
AE20,AE21,AE24,AE25,
DD
AE26,AF24,AF25
V
V
K11,K12,K13,K14,K15,
K16,L10,L17,M10,M17,
N10,N17,U12,U13,
Power for core
(1.0 V)
—
—
DD
F6,F10,F19,K6,K10,K17,
Internal core
DDC
K21,P6,P10,P17,R10,R17, logic constant
T10,T17,U10,U11,U14,
U15,U16,U17,W6,W21,
AA6,AA10,AA14,AA19
power (1.0 V)
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
75
Package and Pin Listings
Table 63. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
V
B1,B2,B8,B9,B16,B17,C1,
C2,C3,C4,C5,C24,C25,
C26,D3,D4,D12,D13,D20,
D21,F8,F11,F13,F16,F17,
F21,G2,G25,H2,H6,H21,
H25,L4,L6,L11,L12,L13,
L14,L15,L16,L21,L23,M4,
M11,M12,M13,M14,M15,
M16,M23,N6,N11,N12,
N13,N14,N15,N16,
—
—
SS
N21,N23,P11,P12,P13,
P14,P15,P16,P23,P25,
R11,R12,R13,R14,R15,
R16,R25,T6,T11,T12,T13,
T14,T15,T16,T21,T25,U5,
U6,U21,W4,W23,Y4,Y23,
AA8,AA11,AA13,AA16,
AA17,AA21,AC4,AC5,
AC12,AC13,AC20,AC21,
AD1,AE2,AE8,AE9,AE16,
AE17,AF2
XCOREV
XCOREV
T1,U2,V2
Core power for
SerDes
transceivers
(1.0 V)
—
DD
SS
P2,R2,T3
P5,U4
—
—
—
XPADV
Pad power for
SerDes
DD
transceivers
(1.0 V)
XPADV
P3,V4
—
—
SS
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to NV
.
DD
2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to NV
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
.
DD
5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. This pin must always be tied to V
.
SS
7. Internal thermally sensitive resistor, resistor value varies linearly with temperature. Useful for determining the junction
temperature.
8. 1588 signals are available on these pins only in MPC8313 Rev 2.x or later.
9. LB_POR_CFG_BOOT_ECC_DIS is available only in MPC8313 Rev 2.x or later.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
76
Freescale Semiconductor
Clocking
20 Clocking
Figure 57 shows the internal distribution of clocks within the MPC8313E.
MPC8313E
e300c3 Core
core_clk
Core PLL
USB Mac
1
x M
USB PHY
PLL
To DDR
Memory
Controller
mux
csb_clk
DDR
DDR
Memory
Device
MEMC_MCK
MEMC_MCK
Clock
USB_CLK_IN
Divider
/2
USB_CR_CLK_IN
ddr_clk
2
x L
Crystal
Clock
Unit
System
PLL
lbc_clk
/1,/2
USB_CR_CLK_OUT
/n
Local Bus
Memory
Device
To Local Bus
LCLK[0:1]
LBC
Clock
Divider
csb_clk to Rest
of the Device
CFG_CLKIN_DIV
PCI_CLK/
PCI_SYNC_IN
SYS_CLK_IN
SYS_CR_CLK_IN
1
0
PCI_SYNC_OUT
Crystal
PCI Clock
Divider (÷2)
SYS_CR_CLK_OUT
3
PCI_CLK_OUT[0:2]
RTC_CLK (32 kHz)
GTX_CLK125
125-MHz Source
eTSEC
Protocol
RTC
Converter
Sys Ref
1
2
Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL].
Multiplication factor L = 2, 3, 4, 5, and 6. Value is decided by RCWLR[SPMF].
Figure 57. MPC8313E Clock Subsystem
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
77
Clocking
The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK,
depending on whether the device is configured in PCI host or PCI agent mode. When the device is
configured as a PCI host device, SYS_CLK_IN is its primary input clock. SYS_CLK_IN feeds the PCI
clock divider (÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The
CFG_CLKIN_DIV configuration input selects whether SYS_CLK_IN or SYS_CLK_IN/2 is driven out
on the PCI_SYNC_OUT signal. The OCCR[PCICOEn] parameters select whether the PCI_SYNC_OUT
is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PCI agent device the SYS_CLK_IN signal should be tied to VSS.
As shown in Figure 57, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbc_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV) is the SYS_CLK_IN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)
which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,
Clocking, and Initialization,” in the MPC8313E PowerQUICC II Pro Integrated Processor Family
Reference Manual, for more information on the clock subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWL[DDRCM])
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The internal lbc_clk frequency is determined by the following equation:
lbc_clk = csb_clk × (1 + RCWL[LBCM])
Note that lbc_clk is not the external local bus frequency; lbc_clk passes through the a LBC clock divider
to create the external local bus clock outputs (LCLK[0:1]). The LBC clock divider ratio is controlled by
LCCR[CLKDIV].
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset. Table 64 specifies which units have a configurable clock
frequency.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
78
Freescale Semiconductor
Clocking
Table 64. Configurable Clock Units
Default
Frequency
Unit
Options
TSEC1
TSEC2
csb_clk
csb_clk
csb_clk
csb_clk
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
2
Security Core, I C, SAP, TPR
USB DR
PCI and DMA complex
Table 65 provides the operating frequencies for the MPC8313E TEPBGAII under recommended operating
conditions (see Table 2).
Table 65. Operating Frequencies for TEPBGAII
Maximum
Operating Frequency
1
Characteristic
Unit
e300 core frequency (core_clk)
333
167
167
66
MHz
MHz
MHz
MHz
MHz
Coherent system bus frequency (csb_clk)
2
DDR1/2 memory bus frequency (MCK)
3
Local bus frequency (LCLKn)
PCI input frequency (SYS_CLK_IN or PCI_CLK)
66
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be
chosen such that the resulting csb_clk, MCK, LCLK[0:1], and core_clk frequencies do not
exceed their respective maximum or minimum operating frequencies. The value of
SCCR[ENCCM] and SCCR[USBDRCM] must be programmed such that the maximum
internal operating frequency of the security core and USB modules do not exceed their
respective value listed in this table.
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on
LCCR[CLKDIV]), which is in turn, 1x or 2x the csb_clk frequency (depending on
RCWL[LBCM]).
20.1 System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 66 shows the multiplication factor
encodings for the system PLL.
Table 66. System PLL Multiplication Factors
System PLL
RCWL[SPMF]
Multiplication Factor
0000
0001
0010
Reserved
Reserved
× 2
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
79
Clocking
Table 66. System PLL Multiplication Factors (continued)
System PLL
RCWL[SPMF]
Multiplication Factor
0011
0100
× 3
× 4
0101
× 5
0110
× 6
0111–1111
Reserved
As described in Section 20, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (SYS_CLK_IN or PCI_SYNC_IN) and the internal coherent system bus clock
(csb_clk). Table 67 shows the expected frequency values for the CSB frequency for select csb_clk to
SYS_CLK_IN/PCI_SYNC_IN ratios.
Table 67. CSB Frequency Options
2
Input Clock Frequency (MHz)
CFG_CLKIN_DIV
csb_clk :Input
Clock Ratio
SPMF
24
25
33.33
66.67
1
2
at Reset
csb_clk Frequency (MHz)
High
High
High
High
High
Low
Low
Low
Low
Low
0010
0011
0100
0101
0110
0010
0011
0100
0101
0110
2:1
3:1
4:1
5:1
6:1
2:1
3:1
4:11
5:1
6:1
133
100
100
125
150
133
167
120
144
133
100
133
167
100
125
150
120
144
1
2
CFG_CLKIN_DIV select the ratio between SYS_CLK_IN and PCI_SYNC_OUT.
SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
80
Freescale Semiconductor
Clocking
20.2 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 68 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 68 should be considered as reserved.
NOTE
Core VCO frequency = core frequency × VCO divider. The VCO divider,
which is determined by RCWLR[COREPLL], must be set properly so that
the core VCO frequency is in the range of 400–800 MHz.
Table 68. e300 Core PLL Configuration
RCWL[COREPLL]
1
2
core_clk : csb_clk Ratio
VCO Divider (VCOD)
0–1
nn
2–5
6
0000
0
PLL bypassed
PLL bypassed
(PLL off, csb_clk clocks core directly)
(PLL off, csb_clk clocks core directly)
11
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
nnnn
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0011
0011
0011
n
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
n/a
1:1
n/a
2
4
8
2
4
8
2
4
8
2
4
8
2
4
8
1:1
1:1
1.5:1
1.5:1
1.5:1
2:1
2:1
2:1
2.5:1
2.5:1
2.5:1
3:1
3:1
3:1
1
2
For core_clk:csb_clk ratios of 2.5:1 and 3:1, the core_clk must not exceed its maximum operating frequency of
333 MHz.
Core VCO frequency = core frequency × VCO divider. Note that VCO divider has to be set properly so that the core
VCO frequency is in the range of 400–800 MHz.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
81
Thermal
20.3 Example Clock Frequency Combinations
Table 69 shows several possible frequency combinations that can be selected based on the indicated input
reference frequencies, with RCWLR[LBCM] = 0 and RCWLR[DDRCM] =1, such that the LBC operates
with a frequency equal to the frequency of csb_clk and the DDR controller operates at twice the frequency
of csb_clk.
Table 69. System Clock Frequencies
LBC(lbc_clk)
e300 Core(core_clk)
SYS_
CSB
DDR
USB
ref
1
2
3
CLK_IN/ SPMF VCOD VCO
PCI_CLK
/2
/4
/8
× 1 × 1.5 × 2 × 2.5 × 3
4
5
(csb_clk) (ddr_clk)
6
25.0
25.0
33.3
33.3
48.0
66.7
6
5
5
4
3
2
2
2
2
2
2
2
600.0
500.0
666.0
532.8
576.0
533.4
150.0
125.0
166.5
133.2
144.0
133.3
300.0
250.0
333.0
266.4
288.0
266.7
—
37.5 18.8 Note
150.0 225 300 375
—
62.5 31.25 15.6 Note 6 125.0 188 250 313 375
41.63 20.8 Note 6 166.5 250 333
66.6 33.3 16.7 Note 6 133.2 200 266 333 400
36 18.0 48.0 144.0 216 288 360
66.7 33.34 16.7 Note 6 133.3 200 267 333 400
—
—
—
—
—
1
2
3
4
System PLL multiplication factor.
System PLL VCO divider.
When considering operating frequencies, the valid core VCO operating range of 400–800 MHz must not be violated.
Due to erratum eTSEC40, csb_clk frequencies of less than 133 MHz do not support gigabit Ethernet data rates. The core
frequency must be 333 MHz for gigabit Ethernet operation. This erratum will be fixed in revision 2 silicon.
Frequency of USB PLL input reference.
5
6
USB reference clock must be supplied from a separate source as it must be 24 or 48 MHz, the USB reference must be
supplied from a separate external source using USB_CLK_IN.
21 Thermal
This section describes the thermal specifications of the MPC8313E.
21.1 Thermal Characteristics
Table 70 provides the package thermal characteristics for the 516, 27 × 27 mm TEPBGAII.
Table 70. Package Thermal Characteristics for TEPBGAII
Characteristic
Board Type
Symbol
TEPBGA II
Unit
Notes
Junction-to-ambient natural convection
Junction-to-ambient natural convection
Junction-to-ambient (@200 ft/min)
Junction-to-ambient (@200 ft/min)
Junction-to-board
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
—
RθJA
RθJA
25
18
20
15
10
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 2, 3
1, 3
1, 3
4
RθJMA
RθJMA
RθJB
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
82
Thermal
Notes
Table 70. Package Thermal Characteristics for TEPBGAII (continued)
Characteristic
Junction-to-case
Board Type
Symbol
TEPBGA II
Unit
—
RθJC
8
7
°C/W
°C/W
5
6
Junction-to-package top
Natural convection
ΨJT
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
21.2 Thermal Management Information
For the following sections, P = (V × I ) + P , where P is the power dissipation of the I/O drivers.
D
DD
DD
I/O
I/O
21.2.1 Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
× P )
D
J
A
θJA
where:
T = junction temperature (°C)
J
T = ambient temperature for the package (°C)
A
R
= junction-to-ambient thermal resistance (°C/W)
θJA
P = power dissipation in the package (W)
D
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. As a general statement, the value obtained on a single layer board is
appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
Test cases have demonstrated that errors of a factor of two (in the quantity T – T ) are possible.
J
A
21.2.2 Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
83
Thermal
(edge) of the package is approximately the same as the local air temperature near the device. Specifying
the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R
× P )
D
J
B
θJB
where:
T = junction temperature (°C)
J
T = board temperature at the package perimeter (°C)
B
R
= junction-to-board thermal resistance (°C/W) per JESD51–8
θJB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.
21.2.3 Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (Ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T + (Ψ × P )
J
T
JT
D
where:
T = junction temperature (°C)
J
T = thermocouple temperature on top of package (°C)
T
Ψ
= thermal characterization parameter (°C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
21.2.4 Heat Sinks and Junction-to-Case Thermal Resistance
In some application environments, a heat sink is required to provide the necessary thermal management of
the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case
thermal resistance and a case to ambient thermal resistance:
R
= R
+ R
θJA
θJC θCA
where:
R
R
R
= junction-to-ambient thermal resistance (°C/W)
= junction-to-case thermal resistance (°C/W)
= case-to- ambient thermal resistance (°C/W)
θJA
θJC
θCA
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
84
Freescale Semiconductor
Thermal
R
θJC is device related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For instance, the user can change the size of the heat
sink, the airflow around the device, the interface material, the mounting arrangement on the printed-circuit
board, or change the thermal dissipation on the printed-circuit board surrounding the device.
To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been
simulated with a few commercially available heat sinks. The heat sink choice is determined by the
application environment (temperature, airflow, adjacent component power dissipation) and the physical
space available. Because there is not a standard application environment, a standard heat sink is not
required.
Table 71. Thermal Resistance for TEPBGAII with Heat Sink in Open Flow
Thermal Resistance
Heat Sink Assuming Thermal Grease
Airflow
(°C/W)
Wakefield 53 × 53 × 2.5 mm pin fin
Natural convection
0.5 m/s
13.0
10.6
9.7
1 m/s
2 m/s
9.2
4 m/s
8.9
Aavid 35 × 31 × 23 mm pin fin
Aavid 30 × 30 × 9.4 mm pin fin
Aavid 43 × 41 × 16.5 mm pin fin
Natural convection
0.5 m/s
14.4
11.3
10.5
9.9
1 m/s
2 m/s
4 m/s
9.4
Natural convection
0.5 m/s
16.5
13.5
12.1
10.9
10.0
14.5
11.7
10.5
9.7
1 m/s
2 m/s
4 m/s
Natural convection
0.5 m/s
1 m/s
2 m/s
4 m/s
9.2
Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling and the convection cooling of the
air moving through the application. Simplified thermal models of the packages can be assembled using the
junction-to-case and junction-to-board thermal resistances listed in Table 71. More detailed thermal
models can be made available on request.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
85
Thermal
Heat sink Vendors include the following list:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
603-224-9988
408-749-7601
818-842-7277
408-436-8770
Alpha Novatech
473 Sapena Ct. #12
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC)
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
Internet: www.mei-thermal.com
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105
Internet: www.chipcoolers.com
800-522-6752
603-635-2800
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
Interface material vendors include the following:
Chomerics, Inc.
77 Dragon Ct.
Woburn, MA 01801
Internet: www.chomerics.com
781-935-4850
800-248-2481
Dow-Corning Corporation
Corporate Center
PO BOX 994
Midland, MI 48686-0994
Internet: www.dowcorning.com
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
888-642-7674
Phoenix, AZ 85044
Internet: www.microsi.com
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
86
Freescale Semiconductor
Thermal
The Bergquist Company
18930 West 78th St.
800-347-4572
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
21.3 Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use
thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the
board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would
lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint
lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force.
If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic
surfaces and its performance verified under the application requirements.
21.3.1 Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction to case
thermal resistance.
T = T + (Rθ x P )
J
C
JC
D
where:
T = junction temperature (°C)
J
T = case temperature of the package
C
Rθ = junction-to-case thermal resistance
JC
P = power dissipation
D
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
87
System Design Information
22 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8313E SYS_CLK_IN
22.1 System Clocking
The MPC8313E includes three PLLs.
1. The platform PLL (AV
) generates the platform clock from the externally supplied
DD2
SYS_CLK_IN input in PCI host mode or SYS_CLK_IN/PCI_SYNC_IN in PCI agent mode. The
frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL ratio
configuration bits as described in Section 20.1, “System PLL Configuration.”
2. The e300 core PLL (AV
) generates the core clock as a slave to the platform clock. The
DD1
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in Section 20.2, “Core PLL Configuration.”
3. There is a PLL for the SerDes block.
22.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AV
,
DD1
AV
, and SDAV , respectively). The AV level should always be equivalent to V , and preferably
DD2
DD DD DD
these voltages are derived directly from V through a low frequency filter scheme such as the following.
DD
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 58, one to each of the five AV pins. By
DD
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize
DD
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
DD
Figure 58 shows the PLL power supply filter circuits.
1.0 Ω
V
AV
and AV
DD1 DD2
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
Figure 58. PLL Power Supply Filter Circuit
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
88
Freescale Semiconductor
System Design Information
The SDAV signal provides power for the analog portions of the SerDes PLL. To ensure stability of the
DD
internal clock, the power supplied to the PLL is filtered using a circuit like the one shown in Figure 59.
For maximum effectiveness, the filter circuit should be placed as closely as possible to the SDAV ball
DD
to ensure it filters out as much noise as possible. The ground connection should be near the SDAV ball.
DD
The 0.003-µF capacitor is closest to the ball, followed by the two 2.2-µF capacitors, and finally the 1-Ω
resistor to the board supply plane. The capacitors are connected from traces from SDAV to the ground
DD
plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be
kept short, wide, and direct.
1.0 Ω
SDAV
SDAV
XCOREV
DD
SS
DD
1
1
2.2 µF
2.2 µF
0.003 µF
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
Figure 59. SerDes PLL Power Supply Filter Circuit
Note the following:
•
•
SDAV should be a filtered version of XCOREV
.
DD
DD
Output signals on the SerDes interface are fed from the XPADV power plane. Input signals and
DD
sensitive transceiver analog circuits are on the XCOREV supply.
DD
•
Power: XPADV consumes less than 300 mW; XCOREV + SDAV consumes less than
DD DD DD
750 mW.
22.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8313E system, and the
MPC8313E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each V , NV , GV , LV , LV ,
DD
DD
DD
DD
DDA
and LV
pin of the device. These decoupling capacitors should receive their power from separate V
,
DD
DDB
NV , GV , LV , LV
, LV
, and VSS power planes in the PCB, utilizing short traces to
DD
DD
DD
DDA
DDB
minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern.
Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V , NV , GV , LV , LV
, and LV
planes, to enable quick recharging of the
DD
DD
DD
DD
DDA
DDB
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100 to 330 µF (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor
for best values and types of bulk capacitors.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
89
System Design Information
22.4 SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (XCOREV and XPADV ) to
DD
DD
ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling
scheme is outlined below.
Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power
and ground should be done with multiple vias to further reduce inductance.
•
First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
•
•
Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (XCOREV and
DD
XPADV ) to the board ground plane on each side of the device. This should be done for all
DD
SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
22.5 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to NV , GV , LV , LV
, or LV
as required.
DD
DD
DD
DDA
DDB
Unused active high inputs should be connected to V . All NC (no-connect) signals must remain
SS
unconnected.
Power and ground connections must be made to all external V , NV , GV , LV , LV
, LV
,
DD
DD
DD
DD
DDA
DDB
and V pins of the device.
SS
22.6 Output Buffer DC Impedance
The MPC8313E drivers are characterized over process, voltage, and temperature. For all buses, the driver
2
is a push-pull single-ended driver type (open drain for I C).
To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to NV
0
DD
or V . Then, the value of each resistor is varied until the pad voltage is NV /2 (see Figure 60). The
SS
DD
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open), and R is trimmed until the voltage at the pad equals
P
NV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each
DD
P
P
N
other in value. Then, Z = (R + R )/2.
0
P
N
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
90
System Design Information
NV
DD
R
N
SW2
SW1
Pad
Data
R
P
V
SS
Figure 60. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V = R
while driving logic 1 with an external precision differential termination resistor of value R . The
× I
. Second, the output voltage is measured
1
source
source
term
measured voltage is V = (1/(1/R + 1/R )) × I
. Solving for the output impedance gives R
=
2
1
2
source
source
R
× (V /V – 1). The drive current is then I
= V /R
.
term
1
2
source
1
source
Table 72 summarizes the signal impedance targets. The driver impedance are targeted at minimum V
,
DD
nominal NV , 105°C.
DD
Table 72. Impedance Characteristics
Local Bus, Ethernet,
PCI Signals
(Not Including PCI
Output Clocks)
PCI Output Clocks
(Including
PCI_SYNC_OUT)
DUART, Control,
Configuration, Power
Management
Impedance
DDR DRAM Symbol
Unit
R
N
42 Target
42 Target
NA
25 Target
25 Target
NA
42 Target
42 Target
NA
20 Target
20 Target
NA
Z
Z
Ω
Ω
Ω
0
0
R
P
Differential
Z
DIFF
Note: Nominal supply voltages. See Table 1, T = 105°C.
J
22.7 Configuration Pin Muxing
The MPC8313E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is
disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections
to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should
minimize the disruption of signal quality or speed for output pins thus configured.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
91
System Design Information
22.8 Pull-Up Resistor Requirements
The MPC8313E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
2
including I C, Ethernet management MDIO, and IPIC (integrated programmable interrupt controller).
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 61. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions because most have asynchronous behavior and spurious assertion,
which give unpredictable results.
Refer to the PCI 2.2 Specification, for all pull-ups required for PCI.
22.9 JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in
IEEE 1149.1, but is provided on any Freescale devices that are built on Power Architecture technology.
The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does
not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state
using only the TCK and TMS signals, systems generally assert TRST during power-on reset. Because the
JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying
TRST to PORESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert TRST without causing
PORESET. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these
signals with logic.
The arrangement shown in Figure 61 allows the COP to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header are not used,
TRST should be tied to PORESET so that it is asserted when the system reset signal (PORESET) is
asserted.
The COP header shown in Figure 61 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header).
There is no standardized way to number the COP header shown in Figure 61; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 61 is common to all known emulators.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
92
Freescale Semiconductor
System Design Information
PORESET
PORESET
From Target
Board Sources
(if any)
SRESET
HRESET
SRESET
HRESET
10 kΩ
HRESET
NV
NV
DD
DD
13
11
SRESET
10 kΩ
10 kΩ
10 kΩ
NV
NV
DD
DD
TRST
TRST
4
1
3
2
4
2 kΩ
VDD_SENSE
1
6
NV
DD
5
6
NC
5
7
8
CHKSTP_OUT
CHKSTP_OUT
15
10 kΩ
9
10
12
NV
NV
DD
DD
11
10 kΩ
2
14
KEY
No pin
13
15
CHKSTP_IN
TMS
CHKSTP_IN
TMS
8
9
1
3
16
TDO
TDI
COP Connector
Physical Pin Out
TDO
TDI
TCK
7
2
TCK
NC
NC
NC
10
12
16
Notes:
1. Some systems require power to be fed from the application board into the debugger repeater card
via the COP header. In this case the resistor value for VDD_SENSE should be around 20 Ω.
2. Key location; pin 14 is not physically present on the COP header.
Figure 61. JTAG Interface Connection
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
93
Document Revision History
23 Document Revision History
Table 73 provides a revision history for this hardware specification.
Table 73. Document Revision History
Rev.
Number
Date
Substantive Change(s)
2.1
2
12/2008
10/2008
• Added Figure 2, after Table 2 and renumbered the following figures.
• Added Note “The information in this document is accurate for revision 1.0, and 2.x and later. See
Section 24.1, “Part Numbers Fully Addressed by this Document,” before Section 1, “Overview.”
• Added part numbering details for all the silicon revisions in Table 74.
• Changed V from 2.7 V to 2.4 V in Table 7.
IH
• Added a row for V level for Rev 2.x or later in Table 45.
IH
• Added a column for maximum power dissipation in low power mode for Rev 2.x or later silicon in
Table 6.
• Added a column for Power Nos for Rev 2.x or later silicon and added a row for 400 MHz in Table 4.
• Removed footnote, “These are preliminary estimates.” from Table 4.
• Added Table 21 for DDR AC Specs on Rev 2.x or later silicon.
• Added Section 9, “High-Speed Serial Interfaces (HSSI).”
• Added LFWE, LFCLE, LFALE, LOE, LFRE, LFWP, LGTA, LUPWAIT, and LFRB in Table 63.
• In Table 39, added note 2: “This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt
Clock Select] field determines the clock frequency of the Mgmt Clock EC_MDC.)”
• Removed mentions of SGMII (SGMII has separate specs) from Section 8.1, “Enhanced
Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI
Electrical Characteristics.”
• Corrected Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI Electrical Characteristics,” to state that
RGMII/RTBI interfaces only operate at 2.5 V, not 3.3 V.
• Added ZQ package to ordering information In Table 74 and Section 19.1, “Package Parameters for
the MPC8313E TEPBGAII” (applicable to both silicon rev. 1.0 and 2.1)
• Removed footnotes 5 and 6 from Table 1 (left over when the PCI undershoot/overshoot voltages and
maximum AC waveforms were removed from Section 2.1.2, “Power Supply Voltage Specification”).
• Removed SD_PLL_TPD (T2) and SD_PLL_TPA_ANA (R4) from Table 63.
•
Added Section 8.3, “SGMII Interface Electrical Characteristics.” Removed Section 8.5.3 SGMII DC
Electrical Characteristics.
• Removed “HRESET negation to SRESET negation (output)” spec and changed “HRESET/SRESET
assertion (output)” spec to “HRESET assertion (output)” in Table 10.
• Clarified POR configuration signal specs to “Time for the device to turn off POR configuration signal
drivers with respect to the assertion of HRESET” and “Time for the device to turn on POR
configuration signal drivers with respect to the negation of HRESET” in Table 10.
• Added Section 24.2, “Part Marking,” and Figure 62.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
94
Freescale Semiconductor
Document Revision History
Table 73. Document Revision History (continued)
Substantive Change(s)
Rev.
Number
Date
1
3/2008
• Replaced OVDD with NV everywhere
DD
• Added XCOREVDD and XPADVDD to Table 1
• Moved VDD and VDDC to the top of the table before SerDes supplies in Table 2
• In Table 2 split DDR row into two from total current requirement of 425 mA. One for DDR1 (131 mA)
and other for DDR2 (140 mA).
• In Table 2 corrected current requirement numbers for NV from 27 mA to 74 mA, LV from 60 mA
DD
DD
to 16 mA, LV
from 85 mA to 22 mA and LV
from 85 mA to 44 mA.
DDA
DDB
• In Table 2 corrected Vdd and Vddc current requirements from 560 mA and 454 mA to 469 and
377 mA, respectively. Corrected Avdd1 and Avdd2 current requirements from 10 mA to 2–3 mA, and
XCOREVDD from 100 mA to 170 mA.
• In Table 2, added row stating junction temperature range of 0 to 105•C. Added footnote 2 stating
GPIO pins may operate from 2.5-V supply as well when configured for different functionality.
• In Section 2.1.2, “Power Supply Voltage Specification,” added a note describing the purpose of
Table 2.
• In Section 3, “Power Characteristics,” added a note describing the purpose of Table 5.
• Rewrote Section 2.2, “Power Sequencing,” and added Figure 3.
• In Table 4, added “but do include core, USB PLL, and a portion of SerDes digital power...” to Note 1.
• In Table 4 corrected “Typical power” to “Maximum power” in note 2 and added a note for Typical
Power.
• In Table 4 removed 266-MHz row as 266-MHz core parts are not offered.
• In Table 5, moved Local bus typical power dissipation under LVdd.
• Added Table 6 to show the low power mode power dissipation for D3warm mode.
• In Table 8 corrected SYS_CLK_IN frequency range from 25–66 MHz to 24–66.67 MHz.
• Added Section 8.4, “eTSEC IEEE 1588 AC Specifications”
• In Table 42 changed minimum value of USB input hold t
from 0 to 1ns
USIXKH
• Added Table 43 and Table 44 showing USB clock in specifications
• In Table 46, added rows for t
Figure 40.
, t
t
and t
parameters. Added
LALEHOV LALETOT1, LALETOT2,
LALETOT3
• In Table 50, removed row for rise time (t
). Removed minimum value of t
. Added note 5 stating
I2CR
I2CF
that the device does not follow the I2C-BUS Specifications version 2.1 regarding the t
parameter.
AC
I2CF
• In Table 56, added a note stating: “This specification only applies to GPIO pins that are operating
from a 3.3-V supply. See Table 63 for the power supply listed for the individual GPIO signal.” [
• Added Table 57 to show DC characteristics for GPIO pins supplied by a 2.5-V supply. Same as
eTSEC DC characteristics when operating at 2.5 V.
• In Section 20, “Clocking,” corrected the sentence “When the device is configured as a PCI agent
device, PCI_SYNC_IN is the primary input clock.” to state “When the device is configured as a PCI
agent device, PCI_CLK is the primary input clock.”
• Added “Value is decided by RCWLR[COREPLL]” to note 1 of Figure 57
• Added paragraph and Figure 59 to Section 22.2, “PLL Power Supply Filtering.”
• Added Section 22.4, “SerDes Block Power Supply Decoupling Recommendations
• Removed the two figures on PCI undershoot/overshoot voltages and maximum AC waveforms from
Section 2.1.2, “Power Supply Voltage Specification,”
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
95
Document Revision History
Table 73. Document Revision History (continued)
Substantive Change(s)
Rev.
Date
Number
1
3/2008
• In Table 63, added LBC_PM_REF_10 & LSRCID3 as muxed with USBDR_PCTL1
• In Table 63, added LSRCID2 as muxed with USBDR_PCTL0
• In Table 63, added LSRCID1 as muxed with USBDR_PWRFAULT
• In Table 63, added LSRCID0 as muxed with USBDR_DRIVE_VBUS
• In Table 63, moved T1, U2,& V2 from V to XCOREVDD.
DD
• In Table 63, moved P2, R2, & T3 from V to XCOREVSS.
SS
• In Table 63, moved P5, & U4 from V to XPADVDD.
DD
• In Table 63, moved P3, & V4 from V to XPADVSS.
SS
• In Table 63, removed “Double with pad” for AV
and Ground Supplies section
and AV
and moved AV
and AV
to Power
DD2
DD1
DD2
DD1
• In Table 63, added impedance control requirements for SD_IMP_CAL_TX (100 ohms to GND) and
SD_IMP_CAL_RX (200 ohms to GND).
• In Table 63, updated muxing in pinout to show new options for selecting IEEE 1588 functionality.
Added footnote 8
• In Table 63, updated muxing in pinout to show new LBC ECC boot enable control muxed with
eTSEC1_MDC
• Added pin type information for power supplies.
• Removed N1 and N3 from Vss section of Table 63. Added Therm0 and Therm1 (N1 and N3,
respectively). Added note 7 to state: “Internal thermally sensitive resistor, resistor value varies
linearly with temperature. Useful for determining the junction temperature.”
• In Table 65 corrected maximum frequency of Local Bus Frequency from “33–66” to 66 MHz
• In Table 65 corrected maximum frequency of PCI from “24–66” to 66 MHz
• Added “which is determined by RCWLR[COREPLL],” to the note in Section 20.2, “Core PLL
Configuration” about the VCO divider.
• Added “(VCOD)” next to VCO divider column in Table 68. Added footnote stating that core_clk
frequency must not exceed its maximum, so 2.5:1 and 3:1 core_clk:csb_clk ratios are invalid for
certain csb_clk values.
• In Table 69, notes were confusing. Added note 3 for VCO column, note 4 for CSB (csb_clk) column,
note 5 for USB ref column, and note 6 to replace “Note 1”. Clarified note 4 to explain erratum
eTSEC40.
• In Table 69, updated note 6 to specify USB reference clock frequencies limited to 24 and 48 for rev.
2 silicon.
• Replaced Table 71 “Thermal Resistance for TEPBGAII with Heat Sink in Open Flow”.
• Removed last row of Table 19.
• Removed 200 MHz rows from Table 21 and Table 5.
• Changed VIH minimum spec from 2.0 to 2.1 for clock, PIC, JTAG, SPI, and reset pins in Table 9,
Table 47, Table 54, Table 59, and Table 61.
• Added Figure 4 showing the DDR input timing diagram.
• In Table 19, removed “MDM” from the “MDQS-MDQ/MECC/MDM” text under the Parameter
column for the tCISKEW parameter. MDM is an output signal and should be removed from
the input AC timing spec table (tCISKEW).
• Added “and power” to rows 2 and 3 in Table 10
• Added the sentence “Once both the power supplies...” and PORESET to Section 2.2, “Power
Sequencing,” and Figure 3.
• In Figure 35, corrected “USB0_CLK/USB1_CLK/DR_CLK” with “USBDR_CLK”
• In Table 42, clarified that AC specs are for ULPI only.
0
6/2007
Initial release.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
96
Freescale Semiconductor
Ordering Information
24 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
Section 24.1, “Part Numbers Fully Addressed by this Document.”
24.1 Part Numbers Fully Addressed by this Document
Table 74 provides the Freescale part numbering nomenclature for the MPC8313E. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Freescale sales office. In addition to the processor frequency, the part numbering scheme also
includes an application modifier which may specify special application conditions. Each part number also
contains a revision code which refers to the die mask revision number.
Table 74. Part Numbering Nomenclature
MPC nnnn
pp
aa
a
x
e
t
Product
Code
Part
Identifier
Encryption
Acceleration
Temperature
Range
e300 core
Frequency
DDR
Frequency
Revision
Level
1
Package
3
2
MPC
8313
Blank = Not
included
E = included
Blank = 0° to 105°C ZQ = PB
C= –40° to 105°C TEPBGAII
AF = 333 MHz F = 333 MHz Blank = 1.0
GD = 400 MHz D = 266 MHz A = 2.0
B = 2.1
VR = PB free
TEPBGAII
Notes:
1. See Section 19, “Package and Pin Listings,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
3. Contact local Freescale office on availability of parts with °C temperature range.
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
97
Ordering Information
24.2 Part Marking
Parts are marked as shown in Figure 62.
MPCnnnnetppaaar
core/ddr MHz
ATWLYYWW
CCCCC
MMMMM YWWLAZ
TePBGA
Notes:
MPCnnnnetppaar is the orderable part number.
ATWLYYWW is the standard assembly, test, year, and work week codes.
CCCCC is the country code.
MMMMM is the mask number.
Figure 62. Part Marking for TEPBGAII Device
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
98
Freescale Semiconductor
Ordering Information
THIS PAGE INTENTIONALLY LEFT BLANK
™
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
99
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or
+1-480-768-2130
www.freescale.com/support
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064
Japan
0120 191014 or
+81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
support.asia@freescale.com
Semiconductor was negligent regarding the design or manufacture of the part.
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800 441-2447 or
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
The Power Architecture and Power.org word marks and the Power and Power.org logos
and related marks are trademarks and service marks licensed by Power.org. The
PowerPC name is a trademark of IBM Corp. and is used under license. RapidIO is a
registered trademark of the RapidIO Trade Association. IEEE Std 802.1, 802.2, 802.3,
802.3u, 802.3x, 802.3z, 802.3ab, 802.3au, 802.11i, 1149.1, and 1588 are registered
trademarks or trademarks of the Institute of Electrical and Electronics Engineers, Inc.,
(IEEE). This product is not endosed or approved by the IEEE. All other product or
service names are the property of their respective owners.
+1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
© Freescale Semiconductor, Inc., 2007, 2008. All rights reserved.
Document Number: MPC8313EEC
Rev. 2.1
12/2008
相关型号：
MPC8313ECVRAFF
32-BIT, 333MHz, MICROPROCESSOR, PBGA516, 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-516
NXP
©2020 ICPDF网 联系我们和版权申明