MPC8377CVRALFA [FREESCALE]
PowerQUICC™ II Pro Processor Hardware Specifications; 的PowerQUICC ™II Pro处理器硬件规格
| 型号： | MPC8377CVRALFA |
| 厂家： | 
Freescale |
| 描述： | PowerQUICC™ II Pro Processor Hardware Specifications |
| 文件： | 总124页 (文件大小：1457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC8377EEC
Rev. 2, 10/2009
Freescale Semiconductor
Technical Data
MPC8377E
PowerQUICC II Pro Processor
Hardware Specifications
™
Contents
This document provides an overview of the MPC8377E
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PowerQUICC™ II Pro processor features, including a block
diagram showing the major functional components. The
device is a cost-effective, low-power, highly integrated host
processor that addresses the requirements of several printing
and imaging, consumer, and industrial applications,
including main CPUs and I/O processors in printing systems,
networking switches and line cards, wireless LANs
(WLANs), network access servers (NAS), VPN routers,
intelligent NIC, and industrial controllers. The MPC8377E
extends the PowerQUICC™ family, adding higher CPU
performance, additional functionality, and faster interfaces
while addressing the requirements related to time-to-market,
price, power consumption, and package size.
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 16
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 22
9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11. Enhanced Secure Digital Host Controller (eSDHC) . 42
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
15. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
16. Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 67
17. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
18. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
19. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
20. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
21. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 76
22. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 86
23. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
24. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
25. System Design Information . . . . . . . . . . . . . . . . . . 117
26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 119
27. Document Revision History . . . . . . . . . . . . . . . . . . 122
1 Overview
The MPC8377E incorporates the e300c4s core, which
includes 32 Kbytes of L1 instruction and data caches and
on-chip memory management units (MMUs). The device
offers two enhanced three-speed 10, 100, 1000 Mbps
Ethernet interfaces, a DDR1/DDR2 SDRAM memory
controller, a flexible, a 32-bit local bus controller, a 32-bit
PCI controller, an optional dedicated security engine, a USB
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Overview
2
2.0 dual-role controller, a programmable interrupt controller, dual I C controllers, a 4-channel DMA
controller, an enhanced secured digital host controller, and a general-purpose I/O port. The block diagram
of the MPC8377E is shown in Figure 1.
MPC8377E
DUART
Dual I2C
e300 Core
Timers
GPIO
32-Kbyte
D-Cache
32-Kbyte
I-Cache
DDR1/DDR2
SDRAM
Controller
SPI
Enhanced
Local Bus
Interrupt
Controller
Security
USB 2.0
PCI
PCI
SATA
PHY PHY
eTSEC
eTSEC
Hi-Speed
Express
Express
RGMII, RMII, RGMII, RMII,
RTBI, MII RTBI, MII
DMA
PCI
Host Device
x1
x1
Figure 1. MPC8377E Block Diagram and Features
The following features are supported in the MPC8377E:
•
e300c4s core built on Power Architecture™ technology with 32-Kbyte instruction cache and
32-Kbyte data cache, a floating point unit, and two integer units
•
•
•
•
•
•
DDR1/DDR2 memory controller supporting a 32/64-bit interface
Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation
32-bit local bus interface running up to 133-MHz
USB 2.0 (full/high speed) support
Power management controller for low-power consumption
High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration
•
Optional security engine provides acceleration for control and data plane security protocols
The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive
cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator
provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
2
Freescale Semiconductor
Overview
In addition to the security engine, new high-speed interfaces such as PCI Express and SATA are included.
Table 1 compares the differences between MPC837xE derivatives and provides the number of ports
available for each interface.
Table 1. High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E
Descriptions
MPC8377E
MPC8378E
MPC8379E
SGMII
PCI Express®
SATA
0
2
2
2
2
0
0
0
4
1.1
DDR Memory Controller
The DDR1/DDR2 memory controller includes the following features:
•
•
•
•
Single 32- or 64-bit interface supporting both DDR1 and DDR2 SDRAM
Support for up to 400-MHz data rate
Support up to 4 chip selects
64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with ×8/×16/×32 data ports (no
direct ×4 support)
•
•
•
•
Support for up to 32 simultaneous open pages
Supports auto refresh
On-the-fly power management using CKE
1.8-/2.5-V SSTL2 compatible I/O
1.2
USB Dual-Role Controller
The USB controller includes the following features:
•
Supports USB on-the-go mode, including both device and host functionality, when using an
external ULPI (UTMI + low-pin interface) PHY
•
•
Complies with USB Specification, Rev. 2.0
Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
•
•
•
Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation;
low-speed operation is supported only in host mode
Supports UTMI + low pin interface (ULPI)
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
3
Overview
1.3
Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
The eTSECs include the following features:
•
•
Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI
Two controllers conform to IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z,
IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588™ standards
•
•
Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating
mode
MII management interface for external PHY control and status
1.4
Integrated Programmable Interrupt Controller (IPIC)
The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a
flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with
the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources.
Interrupts can also be redirected to an external interrupt controller.
1.5
Power Management Controller (PMC)
The power management controller includes the following features:
•
•
•
•
•
Provides power management when the device is used in both host and agent modes
Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states
Support for PME generation in PCI agent mode, PME detection in PCI host mode
Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)
Supports MPC8349E backward-compatibility mode
1.6
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit.
2
1.7
DMA Controller, Dual I C, DUART, Enhanced Local Bus Controller
(eLBC), and Timers
The device provides an integrated four-channel DMA controller with the following features:
•
Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(accessible by local masters)
•
Supports misaligned transfers
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
4
Freescale Semiconductor
Overview
2
There are two I C controllers. These synchronous, multi-master buses can be connected to additional
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.
The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides
a seamless interface to many types of memory devices and peripherals. The memory controller is
responsible for controlling eight memory banks shared by a NAND Flash control machine (FCM), a
general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As
such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash,
EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other
peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with
data signals to reduce the device pin count.
The enhanced local bus controller also includes a number of data checking and protection features, such
as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle
is terminated within a user-specified period. The local bus can operate at up to 133 MHz.
The system timers include the following features: periodic interrupt timer, real time clock, software
watchdog timer, and two general-purpose timer blocks.
1.8
Security Engine
The optional security engine is optimized to handle all the algorithms associated with IPSec,
IEEE 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto
execution units (EUs). The execution units are:
•
•
•
Data encryption standard execution unit (DEU), supporting DES and 3DES
Advanced encryption standard unit (AESU), supporting AES
Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any
algorithm
•
One crypto-channel supporting multi-command descriptor chains
1.9
PCI Controller
The PCI controller includes the following features:
•
•
•
•
•
•
PCI Specification Revision 2.3 compatible
Single 32-bit data PCI interface operates at up to 66 MHz
PCI 3.3-V compatible (not 5-V compatible)
Support for host and agent modes
On-chip arbitration, supporting 5 external masters on PCI
Selectable hardware-enforced coherency
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
5
Overview
1.10 PCI Express® Controller
The PCI Express® controller includes the following features:
•
•
•
•
•
•
•
•
•
•
•
PCI Express 1.0a compatible
Two ×1 links or one ×2 link width
Auto-detection of number of connected lanes
Selectable operation as root complex or endpoint
Both 32- and 64-bit addressing
128-byte maximum payload size
Support for MSI and INTx interrupt messages
Virtual channel 0 only
Selectable Traffic Class
Full 64-bit decode with 32-bit wide windows
Dedicated four channel descriptor-based DMA engine per interface
1.11 Serial ATA (SATA) Controllers
The serial ATA (SATA) controllers have the following features:
•
•
•
•
•
•
•
•
•
•
•
•
Supports Serial ATA Rev 2.5 Specification
Spread spectrum clocking on receive
Asynchronous notification
Hot Plug including asynchronous signal recovery
Link power management
Native command queuing
Staggered spin-up and port multiplier support
Port multiplier support
SATA 1.5 and 3.0 Gb/s operation
Interrupt driven
Power management support
Error handling and diagnostic features
— Far end/near end loopback
— Failed CRC error reporting
— Increased ALIGN insertion rates
Scrambling and CONT override
•
1.12 Enhanced Secured Digital Host Controller (eSDHC)
The enhanced SD Host Controller (eSDHC) has the following features:
•
•
Conforms to SD Host Controller Standard Specification, Rev 2.0 with Test Event register support.
Compatible with the MMC System Specification, Rev 4.0
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
6
Freescale Semiconductor
Electrical Characteristics
•
Compatible with the SD Memory Card Specification, Rev 2.0, and supports High Capacity SD
memory cards
•
•
Compatible with the SDIO Card Specification Rev, 1.2
Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,
MMCplus, MMC 4x, and RS-MMC cards
•
•
•
SD bus clock frequency up to 50 MHz
Supports 1-/4-bit SD and SDIO modes, 1-/4-bit MMC modes
Supports internal DMA capabilities
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8377E. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 2 provides the absolute maximum ratings.
1
Table 2. Absolute Maximum Ratings
Characteristic Symbol
Max Value
Unit
Notes
Core supply voltage
V
–0.3 to 1.1
–0.3 to 1.1
V
V
V
—
—
—
DD
PLL supply voltage (e300 core, system and eLBC)
DDR1 and DDR2 DRAM I/O voltage
AV
DD
GV
–0.3 to 2.75
–0.3 to 1.98
DD
Three-speed Ethernet I/O, MII management voltage
LV [1,2]
–0.3 to 3.63
–0.3 to 3.63
V
V
—
—
DD
2
PCI, DUART, system control and power management, I C, and
JTAG I/O voltage
OV
DD
Local bus
SerDes
LBV
–0.3 to 3.63
–0.3 to 1.1
V
V
V
V
V
V
—
6
DD
L[1,2]_nV
DD
Input voltage
DDR DRAM signals
MV
–0.3 to (GV + 0.3)
2, 4
2, 4
—
IN
DD
DDR DRAM reference
MV
–0.3 to (GV + 0.3)
DD
REF
Three-speed Ethernet signals
LV
–0.3 to (LV + 0.3)
DD
IN
PCI, DUART, CLKIN, system control and power
OV
–0.3 to (OV + 0.3)
3, 4
IN
DD
2
management, I C, and JTAG signals
Local Bus
LB
–0.3 to (LBV + 0.3)
V
5
IN
DD
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
7
Electrical Characteristics
1
Table 2. Absolute Maximum Ratings (continued)
Characteristic
Symbol
Max Value
–55 to 150
Unit
Notes
Storage temperature range
T
°C
—
STG
Notes:
1
Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2
3
Caution: MV must not exceed GV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
IN
DD
Caution: OV must not exceed OV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
4
5
(M,O)V and MV
may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
REF
IN
OV on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
IN
shown in Figure 2.
6
L[1,2]_nV includes SDAV _0, XCOREV , and XPADV power inputs.
DD
DD
DD
DD
2.1.2
Power Supply Voltage Specification
Table 3 provides the recommended operating conditions for the device. Note that the values in Table 3 are
the recommended and tested operating conditions. Proper device operation outside of these conditions is
not guaranteed.
Table 3. Recommended Operating Conditions
Recommended
Characteristic
Symbol
Unit Notes
Value
Core supply voltage
up to 667 MHz
800 MHz
V
1.0 50 mV
1.05 50 mV
1.0 50 mV
1.05 50 mV
V
V
V
V
V
1
1
1
1
1
DD
PLL supply voltage (e300 core, system, and
eLBC)
up to 667 MHz
800 MHz
AV
DD
DDR1 and DDR2 DRAM I/O voltage
GV
2.5 V 125 mV
1.8 V 90 mV
DD
Three-speed Ethernet I/O, MII management voltage
LV [1,2]
3.3 V 165 mV
2.5 V 125 mV
V
V
V
—
1
DD
2
PCI, local bus, DUART, system control and power management, I C, and
JTAG I/O voltage
OV
3.3 V 165 mV
DD
Local Bus
LBV
1.8 V 90 mV
2.5 V 125 mV
3.3 V 165 mV
—
DD
SerDes
up to 667 MHz
800 MHz
L[1,2]_nV
1.0 50 mV
V
V
1, 2
1, 2
DD
1.05 V 50 mV
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
8
Electrical Characteristics
Table 3. Recommended Operating Conditions (continued)
Recommended
Characteristic
Symbol
Unit Notes
Value
Operating temperature range
commerical
T
T
T =0 (min)—
°C
°C
—
—
a
a
T =125 (max)
j
j
extended temperature
T
T =–40 (min)—
a
a
T
T =125 (max)
j
j
Notes:
1
GV , OV , AV , and V must track each other and must vary in the same direction—either in the positive or negative
DD
DD
DD
DD
direction.
2
L[1,2]_nV , SDAV _0, XCOREV , and XPADV power inputs.
DD
DD
DD
DD
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the device.
G/L/O
+ 20%
VDD
G/L/O
+ 5%
VDD
G/L/O
V
VDD
IH
GND
GND – 0.3 V
V
IL
GND – 0.7 V
Not to Exceed 10%
of tinterface1
Note:
1. Note that t
refers to the clock period associated with the bus clock interface.
interface
2. Please note that with the PCI overshoot allowed (as specified above), the device does
not fully comply with the maximum AC ratings and device protection guideline outlined in
the PCI Rev. 2.3 Specification (Section 4.2.2.3).
Figure 2. Overshoot/Undershoot Voltage for GV /OV /LV
DD
DD
DD
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
9
Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 4 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 4. Output Drive Capability
1
Driver Type
Local bus interface utilities signals
Output Impedance (Ω)
Supply Voltage
LBV = 2.5 V, 3.3 V
45
40
25
18
18
45
45
45
DD
LBV = 1.8 V
DD
PCI signals
OV = 3.3 V
DD
DDR1 signal
GV = 2.5 V
DD
DDR2 signal
GV = 1.8 V
DD
eTSEC 10/100/1000 signals
LV = 2.5 V, 3.3 V
DD
2
DUART, system control, I C, JTAG, SPI, and USB
OV = 3.3 V
DD
GPIO signals
OV = 3.3 V
DD
1
Specialized SerDes output capabilities are described in the relevant sections of these specifications (such as PCI Express and
SATA)
2.2
Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device
operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are
supplied before the core voltage, there may be a period of time that all input and output pins will actively
be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to
eliminate excessive current draw, apply the core voltages (V and AV ) before the I/O voltages and
DD
DD
assert PORESET before the power supplies fully ramp up. V and AV must reach 90% of their
DD
DD
nominal value before GV , LV , and OV reach 10% of their value, see Figure 3. I/O voltage
DD
DD
DD
supplies, GV , LV , and OV do not have any ordering requirements with respect to one another.
DD
DD
DD
I/O Voltage (GVDD, LVDD, and OVDD)
V
Core Voltage (VDD AVDD)
,
0.7 V
90%
t
0
Figure 3. Power-Up Sequencing Example
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
10
Freescale Semiconductor
Power Characteristics
Please note that the SerDes power supply (L[1,2]_nV ) should follow the same timing as the core supply
DD
(V ).
DD
The opposite sequence applies to the power down requirements. The I/O supplies must go down first and
immediately followed by the core and PLL supplies.
3 Power Characteristics
The estimated typical power dissipation for the MPC8377E device is shown in Table 5.
1
Table 5. MPC8377E Power Dissipation
Core Frequency CSB/DDR Frequency
Sleep Power
Typical Application Typical Application Max Application
2
2
3
4
(MHz)
(MHz)
at T = 65°C (W)
at T = 65°C (W)
at T = 125°C (W)
at T = 125°C (W)
j
j
j
j
333
167
400
266
300
225
333
250
355
266
400
300
333
266
400
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.9
1.8
2.0
1.9
2.0
1.9
2.0
1.9
2.0
2.0
2.1
2.0
2.1
2.0
2.5
3.2
3.0
3.3
3.1
3.2
3.1
3.3
3.2
3.3
3.2
3.4
3.3
3.3
3.3
3.8
3.8
3.6
4.0
3.8
3.8
3.7
3.9
3.8
4.0
3.9
4.1
4.0
4.1
3.9
4.3
333
400
450
500
533
600
667
800
Note:
1
The values do not include I/O supply power (OV , LV , GV ) or AV . For I/O power values, see Table 6.
DD
DD
DD
DD
2
3
4
Typical power is based on a voltage of V = 1.0 V for core frequences ≤ 667 MHz or V = 1.05 V for core frequences of
DD
DD
800 MHz, and running a Dhrystone benchmark application.
Typical power is based on a voltage of V = 1.0 V for core frequences ≤ 667 MHz or V = 1.05 V for core frequences of
DD
DD
800 MHz, and running a Dhrystone benchmark application.
Maximum power is based on a voltage of V = 1.0 V for core frequences ≤ 667 MHz or V = 1.05 V for core frequences of
DD
DD
800 MHz, worst case process, and running an artificial smoke test.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
11
Power Characteristics
Table 6 shows the estimated typical I/O power dissipation for the device.
Table 6. MPC8377E Typical I/O Power Dissipation
GV
(1.8 V)
GV /LBV
OV
LV
LV
L[1,2]_nV
DD
DD
DD
DD
DD
DD
DD
Interface
Parameter
Unit
Comments
(2.5 V)
(3.3 V) (3.3 V) (2.5 V) (1.0 V)
200MHzdata
rate, 32-bit
0.28
0.35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
—
200MHzdata
rate, 64-bit
0.41
0.31
0.46
0.33
0.48
0.35
0.51
0.38
0.49
0.4
W
W
W
W
W
W
W
W
266MHzdata
rate, 32-bit
266MHzdata
rate, 64-bit
0.56
0.43
0.6
300MHzdata
rate, 32-bit
DDR I/O
65%
utilization
2 pair of
clocks
300MHzdata
rate, 64-bit
333MHzdata
rate, 32-bit
0.45
0.64
—
333MHzdata
rate, 64-bit
400 MHz
data rate,
32-bit
400 MHz
data rate,
64-bit
0.56
—
—
—
—
—
W
33 MHz,
32-bit
—
—
0.04
0.07
0.29
0.24
0.15
0.13
0.1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
W
W
W
W
W
—
—
PCI I/O
Load =
30 pf
66 MHz,
32-bit
—
—
167 MHz,
32-bit
0.09
0.07
0.05
0.04
0.03
0.17
0.14
0.09
0.07
0.06
133 MHz,
32-bit
Local Bus
I/O
Load =
25 pf
83 MHz,
32-bit
66 MHz,
32-bit
50 MHz,
32-bit
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
12
Freescale Semiconductor
Clock Input Timing
Comments
Table 6. MPC8377E Typical I/O Power Dissipation (continued)
GV
GV /LBV
OV
LV
LV
L[1,2]_nV
DD
DD
DD
DD
DD
DD
DD
Interface
Parameter
Unit
(1.8 V)
(2.5 V)
(3.3 V) (3.3 V) (2.5 V) (1.0 V)
MII or RMII
—
—
—
—
0.02
—
—
—
—
W
Multiply by
number of
interfaces used.
eTSEC I/O
Load =
25 pf
RGMII or
RTBI
—
—
0.05
W
—
—
USB
(60MHz
Clock)
12 Mbps
—
—
—
—
0.01
0.2
—
—
—
—
—
—
W
W
480 Mbps
SerDes
per lane
—
—
—
—
—
—
—
—
—
0.029
—
W
W
—
—
Other I/O
0.01
Note: The values given are for typical, and not worst case, switching.
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8377E. Note that
the PCI_CLK/PCI_SYNC_IN signal or CLKIN signal is used as the PCI input clock depending on
whether the device is configured as a host or agent device. CLKIN is used when the device is in host mode.
4.1
DC Electrical Characteristics
Table 7 provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device.
Table 7. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
—
—
V
2.7
–0.3
—
OV + 0.3
V
V
1
1
IH
DD
V
I
0.4
10
30
IL
CLKIN Input current
PCI_CLK Input current
0 V ≤V ≤ OV
μA
μA
—
—
IN
DD
IN
IN
0 V ≤V ≤ 0.5 V or
I
—
IN
OV – 0.5 V ≤V ≤ OV
DD
IN
DD
Note:
1
In PCI agent mode, this specification does not comply with PCI 2.3 Specification.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
13
RESET Initialization
4.2
AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.
Table 8. CLKIN AC Timing Specifications
Parameter
Symbol
Min
Typical
Max
Unit
Notes
CLKIN/PCI_CLK frequency
CLKIN/PCI_CLK cycle time
CLKIN/PCI_CLK rise and fall time
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
f
t
25
15
0.6
40
—
—
—
66.666
40
MHz
ns
1, 6
—
2
CLKIN
CLKIN
t
, t
1.0
—
2.3
ns
KH KL
t
/t
60
%
3
KHK CLKIN
—
—
150
ps
4, 5
Notes:
1
Caution: The system, core and security block must not exceed their respective maximum or minimum operating frequencies.
Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
2
3
4
5
Timing is guaranteed by design and characterization.
This represents the total input jitter-short term and long term-and is guaranteed by design.
The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
6
Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8377E.
5.1
RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins of the device.
Table 9. RESET Pins DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
V
—
—
—
2.0
–0.3
—
OV + 0.3
V
V
IH
DD
Input low voltage
Input current
V
I
0.8
30
IL
μA
V
IN
Output high voltage
Output low voltage
Output low voltage
Note:
V
I
= –8.0 mA
OH
2.4
—
—
OH
V
I
= 8.0 mA
= 3.2 mA
0.5
0.4
V
OL
OL
OL
V
I
—
V
OL
• This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant.
• HRESET and SRESET are open drain pin, thus V is not relevant for these pins.
OH
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
14
Freescale Semiconductor
RESET Initialization
5.2
RESET AC Electrical Characteristics
Table 10 provides the reset initialization AC timing specifications of the device.
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET to activate reset flow
32
32
—
—
t
t
1
2
PCI_SYNC_IN
Required assertion time of PORESET with stable clock applied to CLKIN when
the device is in PCI host mode
t
CLKIN
Required assertion time of PORESET with stable clock applied to PCI_CLK when
the device is in PCI agent mode
32
—
1
PCI_SYNC_IN
HRESET assertion (output)
512
16
4
—
—
—
t
t
1
1
2
PCI_SYNC_IN
PCI_SYNC_IN
HRESET negation to negation (output)
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI host mode
t
CLKIN
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI agent mode
4
—
t
t
1
PCI_SYNC_IN
Input hold time for POR config signals with respect to negation of HRESET
0
—
4
ns
ns
—
3
Time for the device to turn off POR config signals with respect to the assertion of
HRESET
—
Time for the device to start driving functional output signals multiplexed with the
POR configuration signals with respect to the negation of HRESET
1
—
1, 3
PCI_SYNC_IN
Note:
1
t
is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
PCI_SYNC_IN
clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8379E
Integrated Host Processor Reference Manual for more details.
2
3
t
is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the
CLKIN
MPC8379E Integrated Host Processor Reference Manual for more details.
POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV.
Table 11 provides the PLL lock times.
Table 11. PLL Lock Times
Parameter
Min
Max
100
Unit
Notes
PLL lock times
—
μs
—
Note:
• The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL
ratio. See Section 23, “Clocking,” for more information.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
15
DDR1 and DDR2 SDRAM
6 DDR1 and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8377E. Note that DDR1 SDRAM is GV (typ) = 2.5 V and DDR2 SDRAM is GV (typ) = 1.8 V.
DD
DD
6.1
DDR1 and DDR2 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GV (typ) = 1.8 V.
DD
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V
DD
Parameter
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GV
MV
1.71
1.89
V
V
1
2, 5
3
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
– 0.04
MV
+ 0.04
REF
V
REF
V
MV
+ 0.140
GV + 0.3
V
—
—
4
IH
REF
DD
Input low voltage
V
I
–0.3
MV
– 0.140
V
IL
REF
Output leakage current
–40
–13.4
13.4
40
μA
mA
mA
OZ
OH
Output high current (V
= 1.40 V)
I
—
—
—
—
OUT
Output low current (V
= 0.3 V)
I
OL
OUT
Note:
1
GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2
MV
noise on MV
is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver. Peak-to-peak
DD DD
REF
may not exceed 2% of the DC value.
REF
3
V
is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
TT
equal to MV . This rail should track variations in the DC level of MV
.
REF
REF
4
5
Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
See AN3665, MPC837xE Design Checklist, for proper DDR termination.
.
DD
Table 13 provides the DDR2 capacitance when GV (typ) = 1.8 V.
DD
Table 13. DDR2 SDRAM Capacitance for GV (typ) = 1.8 V
DD
Parameter
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
C
6
8
pF
pF
1
1
IO
Delta input/output capacitance: DQ, DQS, DQS
C
—
0.5
DIO
Note:
1
This parameter is sampled. GV = 1.8 V 0.090 V, f = 1 MHz, T = 25°C, V
= GV /2, V
(peak-to-peak) = 0.2 V.
DD
A
OUT
DD
OUT
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
16
DDR1 and DDR2 SDRAM
Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when
GV (typ) = 2.5 V.
DD
Table 14. DDR SDRAM DC Electrical Characteristics for GV
(typ) = 2.5 V
DD
Parameter
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GV
MV
2.375
2.625
V
V
1
2, 5
3
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
– 0.04
+ 0.18
MV
+ 0.04
REF
V
REF
REF
V
MV
GV + 0.3
V
—
—
4
IH
DD
Input low voltage
V
I
–0.3
MV
– 0.18
REF
V
IL
Output leakage current
–40
–15.2
15.2
40
μA
mA
mA
OZ
OH
Output high current (V
= 1.9 V)
I
—
—
—
—
OUT
Output low current (V
= 0.38 V)
I
OL
OUT
Note:
1
GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2
MV
noise on MV
is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver. Peak-to-peak
DD DD
REF
may not exceed 2% of the DC value.
REF
3
V
is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
TT
equal to MV . This rail should track variations in the DC level of MV
.
REF
REF
4
5
Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
See AN3665, MPC837xE Design Checklist, for proper DDR termination.
.
DD
Table 15 provides the DDR capacitance when GV (typ) = 2.5 V.
DD
Table 15. DDR SDRAM Capacitance for GV (typ) = 2.5 V
DD
Parameter
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
C
6
8
pF
pF
1
1
IO
Delta input/output capacitance: DQ, DQS
C
—
0.5
DIO
Note:
1
This parameter is sampled. GV = 2.5 V 0.125 V, f = 1 MHz, T = 25°C, V
= GV /2, V
(peak-to-peak) = 0.2 V.
DD
A
OUT
DD
OUT
Table 16 provides the current draw characteristics for MV
.
REF
Table 16. Current Draw Characteristics for MV
REF
Max
Parameter
Current draw for MV
Symbol
Min
Typ
Unit
Note
I
μA
1, 2
REF
MVREF
DDR1
DDR2
—
—
250
150
600
400
Note:
1
The voltage regulator for MV
must be able to supply up to the stated maximum current.
REF
2
This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
17
DDR1 and DDR2 SDRAM
6.2
DDR1 and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR1 and DDR2 SDRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.
Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter
Symbol
Min
Max
– 0.25
REF
Unit
AC input low voltage
AC input high voltage
V
—
MV
V
V
IL
V
MV
+ 0.25
REF
—
IH
Table 18 provides the input AC timing specifications for the DDR1 SDRAM when GV (typ) = 2.5 V.
DD
Table 18. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter
Symbol
Min
Max
– 0.31
REF
Unit
AC input low voltage
AC input high voltage
V
—
MV
V
V
IL
V
MV
+ 0.31
REF
—
IH
Table 19 provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.
Table 19. DDR1 and DDR2 SDRAM Input AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
Notes
Controller skew for MDQS-MDQ/MECC/MDM
400 MHz data rate
t
ps
1, 2
3
—
—
CISKEW
–500
–750
–750
500
750
750
333 MHz data rate
266 MHz data rate
Note:
1
t
represents the total amount of skew consumed by the controller between MDQSn and any corresponding bit that will
CISKEW
be captured with MDQSn. This should be subtracted from the total timing budget.
2
3
The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
. This can be
DISKEW
determined by the following equation: t
=
[T/4 – |t
|] where T is the MCK clock period and |t
| is the
DISKEW
CISKEW
CISKEW
absolute value of t
.
CISKEW
This specification applies only to DDR2 interface.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
18
Freescale Semiconductor
DDR1 and DDR2 SDRAM
6.2.2
DDR1 and DDR2 SDRAM Output AC Timing Specifications
Table 20 shows the DDR1 and DDR2 SDRAM output AC timing specifications.
Table 20. DDR1 and DDR2 SDRAM Output AC Timing Specifications
1
Parameter
Symbol
Min
Max
Unit
Notes
MCKn cycle time, MCKn/MCKn crossing
t
5
10
ns
ns
2
MCK
ADDR/CMD output setup with respect to MCK
400 MHz data rate
t
3, 7
DDKHAS
DDKHAX
DDKHCS
DDKHCX
1.95
2.40
3.15
4.20
—
—
—
—
333 MHz data rate
266 MHz data rate
200 MHz data rate
ADDR/CMD output hold with respect to MCK
400 MHz data rate
t
ns
ns
ns
3, 7
1.95
2.40
3.15
4.20
—
—
—
—
333 MHz data rate
266 MHz data rate
200 MHz data rate
MCSn output setup with respect to MCK
400 MHz data rate
t
t
3
1.95
2.40
3.15
4.20
—
—
—
—
333 MHz data rate
266 MHz data rate
200 MHz data rate
MCSn output hold with respect to MCK
400 MHz data rate
3
1.95
2.40
3.15
4.20
—
—
—
—
333 MHz data rate
266 MHz data rate
200 MHz data rate
MCK to MDQS skew
t
–0.6
0.6
ns
ps
4, 8
5, 8
DDKHMH
MDQ//MDM output setup with respect to MDQS
400 MHz data rate
t
t
t
DDKHDS,
t
550
800
1100
1200
—
—
—
—
DDKLDS
333 MHz data rate
266 MHz data rate
200 MHz data rate
MDQ//MDM output hold with respect to MDQS
400 MHz data rate
ps
ns
5, 8
6, 8
DDKHDX,
t
700
800
1100
1200
—
—
—
—
DDKLDX
333 MHz data rate
266 MHz data rate
200 MHz data rate
MDQS preamble start
–0.5 × t
–0.6
–0.5 × t
+ 0.6
MCK
DDKHMP
MCK
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
19
DDR1 and DDR2 SDRAM
Table 20. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)
1
Parameter
MDQS epilogue end
Symbol
Min
Max
Unit
Notes
t
–0.6
0.6
ns
6, 8
DDKHME
Note:
1
The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state) (reference)(state)
inputs and t
for outputs. Output hold time can be read as DDR timing
(first two letters of functional block)(reference)(state)(signal)(state)
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H) state until outputs
t
DDKHAS
MCK
(A) are setup (S) or output valid time. Also, t
symbolizes DDR timing (DD) for the time t
memory clock reference
DDKLDX
MCK
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2
3
4
All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.
ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
Note that t follows the symbol conventions described in Note 1. For example, t describes the DDR timing (DD)
DDKHMH
DDKHMH
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
can be modified through control
DDKHMH
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in
the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8379E PowerQUICC II Pro Host Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
5
6
Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or
data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
All outputs are referenced to the rising edge of MCKn at the pins of the microprocessor. Note that t
conventions described in Note 1.
follows the symbol
DDKHMP
7
8
Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle.
See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
The minimum frequency for DDR2 is 250 MHz data rate (125 MHz clock), 167 MHz data rate (83 MHz
clock) for DDR1.
Figure 4 shows the DDR1 and DDR2 SDRAM output timing for the MCK to MDQS skew measurement
(t
).
DDKHMH
MCK[n]
MCK[n]
t
MCK
t
DDKHMHmax) = 0.6 ns
MDQS
MDQS
t
DDKHMH(min) = –0.6 ns
Figure 4. DDR Timing Diagram for t
DDKHMH
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
20
Freescale Semiconductor
DUART
Figure 5 shows the DDR1 and DDR2 SDRAM output timing diagram.
MCK[n]
MCK[n]
t
MCK
t
,t
DDKHAS DDKHCS
t
,t
DDKHAX DDKHCX
ADDR/CMD
Write A0
NOOP
t
DDKHMP
t
DDKHMH
MDQS[n]
MDQ[x]
t
DDKHDS
t
DDKHME
t
DDKLDS
D0
D1
t
DDKLDX
t
DDKHDX
Figure 5. DDR1 and DDR2 SDRAM Output Timing Diagram
Figure 6 provides the AC test load for the DDR bus.
GVDD/2
Output
Z = 50 Ω
0
R = 50 Ω
L
Figure 6. DDR AC Test Load
7 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8377E.
7.1
DUART DC Electrical Characteristics
Table 21 provides the DC electrical characteristics for the DUART interface of the device.
Table 21. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage OV
V
2
OV + 0.3
V
V
IH
DD
V
–0.3
0.8
DD
IL
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
21
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Table 21. DUART DC Electrical Characteristics (continued)
High-level output voltage,
= –100 μA
V
OV – 0.2
—
0.2
30
V
V
OH
DD
I
OH
Low-level output voltage,
= 100 μA
V
I
—
—
OL
I
OL
Input current,
μA
IN
(0 V ≤V ≤ OV
)
IN
DD
Note:
• The symbol V , in this case, represents the OV symbol referenced in Table 2.
IN
IN
7.2
DUART AC Electrical Specifications
Table 22 provides the AC timing parameters for the DUART interface of the device.
Table 22. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
Maximum baud rate
Oversample rate
256
> 1,000,000
16
baud
baud
—
—
1
2
Notes:
1
Actual attainable baud rate will be limited by the latency of interrupt processing.
2
th
The middle of a start bit is detected as the 8 sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
th
sampled each 16 sample.
8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet
controller.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—MII/RGMII/RTBI/RMII DC Electrical
Characteristics
The electrical characteristics specified here apply to media independent interface (MII), reduced gigabit
media independent interface (RGMII), reduced ten-bit interface (RTBI), reduced media independent
interface (RMII) signals, management data input/output (MDIO) and management data clock (MDC).
The MII and RMII interfaces are defined for 3.3 V, while the RGMII and RTBI interfaces can be operated
at 2.5 V. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface
(RGMII) Specification Version 1.3. The RMII interface follows the RMII Consortium RMII Specification
Version 1.2.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
22
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.1.1
MII, RMII, RGMII, and RTBI DC Electrical Characteristics
MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 23 and
Table 24. The RGMII and RTBI signals in Table 24 are based on a 2.5 V CMOS interface voltage as
defined by JEDEC EIA/JESD8-5.
Table 23. MII and RMII DC Electrical Characteristics
Parameter
Supply voltage 3.3 V
Symbol
Min
Max
Unit
Notes
LV
LV
3.13
3.47
V
DD1
DD2
Output high voltage
(LV /LV = Min, I = –4.0 mA)
OH
V
2.40
LV
LV
/LV
DD2
+ 0.3
+ 0.3
V
V
—
—
OH
DD1
DD1
DD1
DD2
Output low voltage
(LV /LV = Min, I = 4.0 mA)
V
GND
0.50
OL
DD1
DD2
OL
Input high voltage
Input low voltage
Input high current
V
2.0
–0.3
—
/LV
V
V
—
—
IH
DD2
V
I
0.90
30
IL
μA
IH
(V = LV
, V = LV
)
DD2
IN
DD1
IN
Input low current
I
–600
—
μA
—
IL
(V = GND)
IN
Note:
1. LV
LV
supports eTSEC 1.
supports eTSEC 2.
DD1
DD2
Table 24. RGMII and RTBI DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage 2.5 V
LV
LV
2.37
2.63
V
1, 2
DD1
DD2
Output high voltage
V
2.00
LV
LV
/LV
DD2
+ 0.3
+ 0.3
V
V
—
—
OH
DD1
DD1
(LV
/LV
= Min, IOH = –1.0 mA)
DD2
DD1
Output low voltage
(LV /LV = Min, I = 1.0 mA)
V
GND – 0.3
0.40
OL
DD1
DD2
OL
Input high voltage
Input low voltage
Input high current
V
2.0
–0.3
—
/LV
V
V
—
—
IH
DD2
V
I
0.70
–20
IL
μA
1, 2
IH
(V = LV
, V = LV
)
DD2
IN
DD1 IN
Input low current
I
–20
—
μA
—
IL
(V = GND)
IN
Note:
1
LV
supports eTSEC 1.
supports eTSEC 2.
DD1
DD2
2
LV
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
23
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.2
MII, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for MII, RGMII, RMII and RTBI are presented in this section.
8.2.1
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.1.1
MII Transmit AC Timing Specifications
Table 25 provides the MII transmit AC timing specifications.
Table 25. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
1
Parameter
Symbol
Min
Typical
Max
Unit
TX_CLK clock period 10 Mbps
t
—
—
400
40
—
5
—
—
ns
ns
%
MTX
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
t
MTX
t
t
35
1
65
15
4.0
4.0
MTXH/ MTX
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
TX_CLK data clock rise (20%-80%)
TX_CLK data clock fall (80%-20%)
t
ns
ns
ns
MTKHDX
t
1.0
1.0
—
—
MTXR
t
MTXF
Note:
1
The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
transmit timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
MTX
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
MTX
convention is used with the appropriate letter: R (rise) or F (fall).
Figure 7 shows the MII transmit AC timing diagram.
t
t
MTXR
MTX
TX_CLK
t
t
MTXF
MTXH
TXD[3:0]
TX_EN
TX_ER
t
MTKHDX
Figure 7. MII Transmit AC Timing Diagram
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
24
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.2.1.2
MII Receive AC Timing Specifications
Table 26 provides the MII receive AC timing specifications.
Table 26. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
1
Parameter
Symbol
Min
Typical
Max
Unit
Input low voltage
V
—
1.9
—
—
—
0.7
—
V
IL
Input high voltage
V
V
IH
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
t
t
400
40
—
—
ns
ns
%
MRX
MRX
—
—
t
/t
35
65
—
MRXH MRX
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%-80%)
RX_CLK clock fall time (80%-20%)
t
10.0
10.0
1.0
1.0
—
ns
ns
ns
ns
MRDVKH
MRDXKH
t
—
—
t
—
4.0
4.0
MRXR
t
—
MRXF
Note:
1
The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII receive
clock reference (K) going
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
MRX
to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data input signals
MRDXKL
(D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in general, the
MRX
clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,
the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
MRX
appropriate letter: R (rise) or F (fall).
Figure 8 provides the AC test load for eTSEC.
Output
LVDD/2
Z = 50 Ω
0
R = 50 Ω
L
Figure 8. eTSEC AC Test Load
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
25
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 9 shows the MII receive AC timing diagram.
t
t
MRXR
MRX
RX_CLK
t
t
MRXH
MRXF
RXD[3:0]
RX_DV
RX_ER
Valid Data
t
MRDVKH
t
MRDXKL
Figure 9. MII Receive AC Timing Diagram
8.2.2
RGMII and RTBI AC Timing Specifications
Table 27 presents the RGMII and RTBI AC timing specifications.
Table 27. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V 5%.
1
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock period
t
–600
1.0
7.2
45
0
600
2.8
8.8
55
ps
ns
ns
%
—
2
SKRGT
t
—
SKRGT
t
8.0
50
50
—
3
RGT
Duty cycle for 1000Base-T
t
t
/t
4
RGTH RGT
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
/t
40
60
%
3, 4
—
—
5
RGTH RGT
t
—
0.75
0.75
—
ns
ns
ns
%
RGTR
Fall time (20%–80%)
t
—
—
RGTF
EC_GTX_CLK125 reference clock period
EC_GTX_CLK125 reference clock duty cycle
t
—
8.0
—
G12
t
/t
47
53
—
G125H G125
measured at 0.5 × LV
DD1
Note:
1
Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being
represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2
This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal.
3
4
For 10 and 100 Mbps, t
scales to 400 ns 40 ns and 40 ns 4 ns, respectively.
RGT
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t
between
of the lowest speed transitioned
RGT
5
This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
26
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 10 provides the AC test load for eTSEC.
Output
LVDD/2
Z = 50 Ω
0
R = 50 Ω
L
Figure 10. eTSEC AC Test Load
Figure 11 shows the RGMII and RTBI AC timing and multiplexing diagrams.
t
RGT
t
RGTH
GTX_CLK
(At Transmitter)
t
SKRGT
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
t
SKRGT
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
t
SKRGT
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
t
SKRGT
RX_CLK
(At PHY)
Figure 11. RGMII and RTBI AC Timing and Multiplexing Diagrams
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
27
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.2.3
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.3.1
RMII Transmit AC Timing Specifications
The RMII transmit AC timing specifications are in Table 28.
Table 28. RMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
1
Parameter
Symbol
Min
Typical
Max
Unit
REF_CLK clock period
t
15.0
35
20.0
50
—
25.0
65
ns
%
RMT
REF_CLK duty cycle
t
RMTH
REF_CLK peak-to-peak jitter
Rise time REF_CLK (20%–80%)
Fall time REF_CLK (80%–20%)
REF_CLK to RMII data TXD[1:0], TX_EN delay
t
—
250
2.0
ps
ns
ns
ns
RMTJ
t
1.0
1.0
2.0
—
RMTR
t
—
2.0
RMTF
t
—
10.0
RMTDX
Note:
1
The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
transmit timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
MTX
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
MTX
convention is used with the appropriate letter: R (rise) or F (fall).
Figure 12 shows the RMII transmit AC timing diagram.
t
t
RMTR
RMT
REF_CLK
t
t
RMTH
RMTF
TXD[1:0]
TX_EN
TX_ER
t
RMTDX
Figure 12. RMII Transmit AC Timing Diagram
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
28
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.2.3.2
RMII Receive AC Timing Specifications
Table 29 shows the RMII receive AC timing specifications.
Table 29. RMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Input low voltage at 3.3 LV
V
—
2.0
15.0
35
—
—
0.8
—
V
DD
IL
Input high voltage at 3.3 LV
REF_CLK clock period
REF_CLK duty cycle
V
V
DD
IH
t
20.0
50
—
25.0
65
ns
%
RMR
t
t
RMRH
REF_CLK peak-to-peak jitter
t
—
250
2.0
2.0
—
ps
ns
ns
ns
ns
RMRJ
RMRR
Rise time REF_CLK (20%–80%)
1.0
1.0
4.0
2.0
—
Fall time REF_CLK (80%–20%)
t
—
RMRF
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge
t
—
RMRDV
t
—
—
RMRDX
Note:
1
The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference
MRX
(K) going to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data
MRDXKL
input signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in
MRX
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
MRX
used with the appropriate letter: R (rise) or F (fall).
Figure 13 provides the AC test load for eTSEC.
LVDD/2
Output
Z = 50 Ω
0
R = 50 Ω
L
Figure 13. eTSEC AC Test Load
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
29
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 14 shows the RMII receive AC timing diagram.
t
t
RMRR
RMR
REF_CLK
t
t
RMRH
RMRF
RXD[1:0]
CRS_DV
RX_ER
Valid Data
t
RMRDV
t
RMRDX
Figure 14. RMII Receive AC Timing Diagram
8.3
Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock).
Figure 15 provides the AC test load for eTSEC.
LVDD/2
Output
Z = 50 Ω
0
R = 50 Ω
L
Figure 15. eTSEC AC Test Load
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 2.5 V or 3.3 V. The DC electrical
characteristics for MDIO and MDC are provided in Table 30 and Table 31.
Table 30. MII Management DC Electrical Characteristics When Powered at 2.5 V
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage (2.5 V)
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
—
LV
V
2.37
2.00
2.63
V
V
DD1
I
= –1.0 mA
= 1.0 mA
—
LV
LV
LV
LV
= Min
= Min
= Min
= Min
LV
+ 0.3
OH
DD1
DD1
DD1
DD1
OH
DD1
I
V
GND – 0.3
1.7
0.40
—
V
OL
OL
V
V
IH
—
V
I
–0.3
0.70
20
V
IL
V
= LV
= LV
—
μA
μA
IN
IN
DD1
DD1
IH
V
I
–15
—
IL
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
30
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Table 31. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage (3.3 V)
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
—
LV
V
3.135
2.10
GND
2.00
—
3.465
V
V
DD1
I
= –1.0 mA
LV
LV
= Min
= Min
LV
+ 0.3
DD1
OH
DD1
DD1
OH
I
= 1.0 mA
V
0.50
V
OL
OL
—
—
V
—
0.80
30
V
IH
V
I
V
IL
1
LV
LV
= Max
V
= 2.1 V
= 0.5 V
—
μA
μA
DD1
IN
IH
= Max
V
I
IL
–600
—
DD1
IN
8.3.2
MII Management AC Electrical Specifications
Table 32 provides the MII management AC timing specifications.
Table 32. MII Management AC Timing Specifications
1
Parameter
MDC frequency
Symbol
Min
Typical
Max
Unit
Notes
f
t
2.5
80
32
—
—
—
8.3
400
—
MHz
ns
2, 3
—
—
5
MDC
MDC
MDC period
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
t
ns
MDCH
t
t
t
t
2 × (t
× 8)
—
ns
MDKHDV
MDKHDX
MDDVKH
MDDXKH
plb_clk
10
—
—
—
—
—
2 × (t
× 8)
ns
3, 5
—
—
4
plb_clk
5
0
—
ns
—
10
10
ns
t
—
—
ns
MDCR
MDC fall time
t
ns
4
MDCF
Note:
1
The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes
(first two letters of functional block)(reference)(state)(signal)(state)
MDKHDX
management data timing (MD) for the time t
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
MDC
hold time. Also, t
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
MDDVKH
valid state (V) relative to the t
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the
MDC
latter convention is used with the appropriate letter: R (rise) or F (fall).
2
3
This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency
divided by 64.)
This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency
is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and
the minimum frequency is 1.7 MHz.)
4
5
Guaranteed by design.
t
is the platform (CSB) clock divided according to the SCCR[TSEC1CM].
plb_clk
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
31
USB
Figure 16 shows the MII management AC timing diagram.
t
t
MDCR
MDC
MDC
t
t
MDCF
MDCH
MDIO
(Input)
MDDVKH
t
t
MDDXKH
MDIO
(Output)
t
MDKHDX
Figure 16. MII Management Interface Timing Diagram
9 USB
This section provides the AC and DC electrical characteristics for the USB dual-role controllers.
9.1
USB DC Electrical Characteristics
Table 33 provides the DC electrical characteristics for the USB interface at recommended
OV = 3.3 V ± 165 mV.
DD
Table 33. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
Input current
V
2
OV + 0.3
V
V
IH
DD
V
I
–0.3
—
0.8
30
—
IL
μA
V
IN
High-level output voltage,
V
OV – 0.2
OH
DD
I
= –100 μA
OH
Low-level output voltage,
= 100 μA
V
—
0.2
V
OL
I
OL
Note:
The symbol V , in this case, represents the OV symbol referenced in Table 2.
IN
IN
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
32
Local Bus
9.2
USB AC Electrical Specifications
Table 34 describes the general timing parameters of the USB interface of the device.
Table 34. USB General Timing Parameters (ULPI Mode Only)
1
Parameter
Symbol
Min
Max
Unit
USB clock cycle time
t
15
4
—
—
—
7
ns
ns
ns
ns
ns
USCK
Input setup to USB clock—all inputs
input hold to USB clock—all inputs
USB clock to output valid—all outputs
Output hold from USB clock—all outputs
t
t
USIVKH
USIXKH
1
t
t
—
2
USKHOV
USKHOX
—
Figure 17 and Figure 18 provide the AC test load and signals for the USB, respectively.
OVDD/2
Output
Z = 50 Ω
0
R = 50 Ω
L
Figure 17. USB AC Test Load
USBDR_CLK
t
USIXKH
t
USIVKH
Input Signals
t
t
USKHOX
USKHOV
Output Signals
Figure 18. USB Interface Timing Diagram
10 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8377E.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
33
Local Bus
10.1 Local Bus DC Electrical Characteristics
Table 35 and Table 36 provides the DC electrical characteristics for the local bus interface.
Table 35. Local Bus DC Electrical Characteristics (LBV = 3.3 V)
DD
At recommended operating conditions with LBVDD = 3.3 V.
Parameter
Conditions
Symbol
LBV
Min
Max
Unit
Supply voltage 3.3 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
—
3.135
2.40
—
3.465
—
V
V
DD
I
= –4.0 mA
= 4.0 mA
—
LBV = Min
V
OH
OH
DD
I
LBV = Min
V
OL
0.50
V
OL
DD
—
—
V
2.0
LBV + 0.3
V
IH
DD
—
V
I
–0.3
—
0.90
30
V
IL
1
V
= LBV
μA
μA
IN
DD
IH
1
V
= GND
I
–30
—
IN
IL
Table 36. Local Bus DC Electrical Characteristics (LBV = 2.5 V)
DD
At recommended operating conditions with LBVDD = 2.5 V.
Parameter
Conditions
Symbol
LBV
Min
Max
Unit
Supply voltage 2.5 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
—
2.37
2.00
—
2.73
—
V
V
DD
I
= –1.0 mA
= 1.0 mA
—
LBV = Min
V
OH
OH
DD
I
LBV = Min
V
OL
0.40
V
OL
DD
LBV = Min
V
1.7
LBV + 0.3
V
DD
IH
DD
—
LBV = Min
V
I
–0.3
—
0.70
20
V
DD
IL
1
V
= LBV
μA
μA
IN
DD
IH
1
V
= GND
I
–20
—
IN
IL
Table 37. Local Bus DC Electrical Characteristics (LBV = 1.8 V)
DD
At recommended operating conditions with LBVDD = 1.8 V.
Parameter
Conditions
Symbol
LBV
Min
Max
Unit
Supply voltage 1.8 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
—
1.71
1.89
—
V
V
DD
I
= –1.0 mA
= 1.0 mA
—
LBV = Min
V
LBV – 0.45
OH
DD
OH
DD
I
LBV = Min
V
OL
—
0.45
V
OL
DD
LBV = Min
V
0.65 × LBV
LBV + 0.3
V
DD
IH
DD
DD
—
LBV = Min
V
I
–0.3
—
0.35 × LBV
DD
V
DD
IL
1
V
= LBV
10
—
μA
μA
IN
DD
IH
1
V
= GND
I
–10
IN
IL
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
34
Local Bus
10.2 Local Bus AC Electrical Specifications
Table 38 describes the general timing parameters of the local bus interface of the device.
Table 38. Local Bus General Timing Parameters—PLL Enable Mode
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus cycle time
t
7.5
1.5
1.0
1.5
1.5
3
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
3, 4
3, 4
3, 4
5
LBK
Input setup to local bus clock (except LUPWAIT/LGTA)
Input hold from local bus clock
t
t
LBIVKH
LBIXKH
—
LUPWAIT/LGTA input setup to local bus clock
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
Local bus clock to LALE rise
t
—
LBIVKH1
LBOTOT1
LBOTOT2
LBOTOT3
t
t
t
—
—
6
2.5
—
—
7
t
4.5
4.5
3.8
—
—
3
LBKHLR
LBKHOV
LBKHOZ
LBKHOX
Local bus clock to output valid (except LALE)
Local bus clock to output high impedance for LAD/LDP
Output hold from local bus clock for LAD/LDP
t
t
t
—
—
3, 8
3
1
Note:
1
The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes local bus
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one(1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to
LBKHOX
LBK
the output (O) going invalid (X) or output hold time.
2
3
4
5
All timings are in reference to rising edge of LSYNC_IN at LBV /2 and the 0.4 LBV of the signal in question.
×
DD
DD
All signals are measured from LBV /2 of the rising/falling edge of LSYNC_IN to 0.5 × LBV of the signal in question.
DD
DD
Input timings are measured at the pin.
t
should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load on
LBOTOT1
LAD output pins.
6
t
should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on LAD
LBOTOT2
output pins.
7
8
t
should be used when LBCR[AHD] is set and the load on LALE output pin equals to the load on LAD output pins.
LBOTOT3
For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
35
Local Bus
Table 38 describes the general timing parameters of the local bus interface of the device.
Table 39. Local Bus General Timing Parameters—PLL Bypass Mode
1
Parameter
Local bus cycle time
Symbol
Min
Max
Unit
Notes
t
15
7.0
1.0
1.5
—
—
—
—
ns
ns
ns
ns
2
LBK
Input setup to local bus clock
Input hold from local bus clock
t
3, 4
3, 4
5
LBIVKH
t
LBIXKH
LALE output fall to LAD output transition (LATCH
hold time)
t
t
t
LBOTOT1
LALE output fall to LAD output transition (LATCH
hold time)
3.0
2.5
—
—
ns
ns
6
7
LBOTOT2
LBOTOT3
LALE output fall to LAD output transition (LATCH
hold time)
Local bus clock to output valid
t
—
—
3.0
4.0
ns
ns
3
LBKHOV
Local bus clock to output high impedance for
LAD/LDP
t
3, 8
LBKHOZ
Note:
1
The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes local bus
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case
clock reference (K) to go high (H), with respect
LBK
LBK
for clock one(1). Also, t
symbolizes local bus timing (LB) for the t
LBKHOX
to the output (O) going invalid (X) or output hold time.
2
3
All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
All signals are measured from LBV /2 of the rising/falling edge of LCLK0 to 0.4 × LBV of the signal in question for 3.3-V
DD
DD
signaling levels.
4
5
Input timings are measured at the pin.
should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load on
t
LBOTOT1
LAD output pins.
6
t
should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on LAD
LBOTOT2
output pins.
7
8
t
should be used when LBCR[AHD] is set and the load on LALE output pin equals to the load on LAD output pins.
LBOTOT3
For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Figure 19 provides the AC test load for the local bus.
OVDD/2
Output
Z = 50 Ω
0
R = 50 Ω
L
Figure 19. Local Bus AC Test Load
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
36
Freescale Semiconductor
Local Bus
Figure 20 through Figure 25 show the local bus signals.
LSYNC_IN
t
t
LBIXKH
t
LBIVKH
LBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
LBIXKH
t
Input Signal:
LGTA
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
t
LBKHOX
t
LBKHOV
LA[27:31]/LBCTL/LBCKE/LOE
t
LBKHOZ
LBKHOX
t
t
LBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ
LBKHOX
t
t
LBKHOV
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
t
LBKHLR
LALE
Figure 20. Local Bus Signals, Non-special Signals Only (PLL Enable Mode)
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
37
Local Bus
LCLK[n]
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:15]
t
LBIXKH
t
LBIVKH
Input Signal:
LGTA
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE
t
t
LBKHOV
t
t
LBKHOZ
LBKHOZ
LBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOV
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
t
LBKHLR
LALE
Figure 21. Local Bus Signals, Non-special Signals Only (PLL Bypass Mode)
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
38
Freescale Semiconductor
Local Bus
LSYNC_IN
T1
T3
t
t
LBKHOV
LBKHOX
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
t
LBIXKH
t
LBIVKH
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOX
t
LBKHOV
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
t
LBKHOZ
LBKHOX
t
t
t
LBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ
LBKHOX
t
LBKHOV
Output (Address) Signal:
LAD[0:31]
Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (PLL Enable Mode)
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
39
Local Bus
LCLK
T1
T3
t
LBKHOZ
t
LBKHOV
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
t
LBIXKH
t
LBIVKH
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOV
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
t
LBKHOZ
t
LBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ
t
LBKHOV
Output (Address) Signal:
LAD[0:31]
Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (PLL Bypass Mode)
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
40
Freescale Semiconductor
Local Bus
LSYNC_IN
T1
T2
T3
T4
t
LBKHOZ
t
LBKHOV
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
t
LBIXKH
t
LBIVKH
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:31]
t
LBKHOX
t
LBKHOV
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
t
LBKHOZ
LBKHOX
t
t
LBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ
LBKHOX
t
t
LBKHOV
Output (Address) Signal:
LAD[0:31]
Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Enable Mode)
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
41
Enhanced Secure Digital Host Controller (eSDHC)
LCLK
T1
T2
T3
T4
t
LBKHOZ
t
LBKHOV
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
t
LBIXKH
t
LBIVKH
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH
t
LBIVKH
Input Signals:
LAD[0:31]
t
LBKHOV
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
t
t
LBKHOZ
LBKHOZ
t
LBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOV
Output (Address) Signal:
LAD[0:31]
Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode)
11 Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC) interface of the
MPC8377E.
The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the
SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both full-
and high-speed modes.
Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed
mode, that data will be driven at the rising edge of the clock.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
42
Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
Due to the special implementation of the eSDHC, there are constraints regarding the clock and data signals
propagation delay on the user board. The constraints are for minimum and maximum delays, as well as
skew between the CLK and DAT/CMD signals.
In full speed mode, there is no need to add special delay on the data or clock signals. The user should make
sure to meet the timing requirements as described further within this document.
If the system is designed to support both high-speed and full-speed cards, the high-speed constraints
should be fulfilled. If the systems is designed to operate up to 25 MHz only, full-speed mode is
recommended.
11.1 eSDHC DC Electrical Characteristics
Table 40 provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device.
Table 40. eSDHC interface DC Electrical Characteristics
Parameter
Input high voltage
Symbol
Condition
Min
Max
Unit
V
—
0.625 × OV
–0.3
OV + 0.3
V
V
IH
DD
DD
Input low voltage
Input current
V
—
0.25 × OV
IL
DD
I
—
—
30
—
μA
V
IN
Output high voltage
V
I
= –100 uA,
0.75 × OV
DD
OH
OH
at OV (min)
DD
Output low voltage
V
I
= +100 uA,
—
0.125 × OV
V
OL
OL
DD
at OV (min)
DD
11.2 eSDHC AC Timing Specifications (Full-Speed Mode)
This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device.
Table 41 provides the eSDHC AC timing specifications for full-speed mode as defined in Figure 27 and
Figure 28.
Table 41. eSDHC AC Timing Specifications for Full-Speed Mode
At recommended operating conditions OVDD = 3.3 V 165 mV.
1
Parameter
Symbol
Min
Max
Unit
Notes
SD_CLK clock frequency—full speed mode
SD_CLK clock cycle
f
t
0
25
—
MHz
ns
—
—
—
2
SFSCK
SFSCK
40
0
SD_CLK clock frequency—identification mode
SD_CLK clock low time
f
400
—
KHz
ns
SIDCK
t
15
15
—
SFSCKL
SD_CLK clock high time
t
—
ns
2
SFSCKH
SD_CLK clock rise and fall times
t
/
5
ns
2
SFSCKR
t
SFSCKF
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
t
5
—
ns
2
SFSIVKH
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
43
Enhanced Secure Digital Host Controller (eSDHC)
Table 41. eSDHC AC Timing Specifications for Full-Speed Mode (continued)
At recommended operating conditions OVDD = 3.3 V 165 mV.
1
Parameter
Symbol
Min
Max
Unit
Notes
Input hold times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
t
0
—
ns
2
SFSIXKH
SD_CLK delay within device
Output valid: SD_CLK to SD_CMD, SD_DATx valid
Output hold: SD_CLK to SD_CMD, SD_DATx valid
SD card input setup
t
1.5
—
0
—
4
ns
ns
—
ns
ns
ns
ns
4
2
INT_CLK_DLY
t
t
SFSKHOV
—
—
—
14
—
—
3
SFSKHOX
t
5
ISU
SD card input hold
t
5
3
IH
SD card output valid
t
—
0
3
ODLY
SD card output hold
t
3
OH
Notes:
1
The symbols used for timing specifications herein follow the pattern of t
(first three letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first three letters of functional block)(reference)(state)(signal)(state)
SFSIXKH
symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going
to high (H). Also t symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect
SFSKHOV
to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is
based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
2
3
4
Measured at capacitive load of 40 pF.
For reference only, according to the SD card specifications.
Average, for reference only.
Figure 26 provides the eSDHC clock input timing diagram.
eSDHC
External Clock
VM
VM
VM
operational mode
t
t
SFSCKH
SFSCKL
t
SFSCK
t
SFSCKF
t
SFSCKR
VM = Midpoint Voltage (OV /2)
DD
Figure 26. eSDHC Clock Input Timing Diagram
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
44
Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
11.2.1 Full-Speed Output Path (Write)
Figure 27 provides the data and command output timing diagram.
t
(Clock Cycle)
SFSCK
SD CLK at the
MPC8377E Pin
Driving
Edge
t
CLK_DELAY
SD CLK at
the Card Pin
Sampling
Edge
Output Valid Time: t
Output Hold Time: t
SFSKHOV
SFSKHOX
t
SFSCKL
Output from the
MPC8377E Pins
Input at the
MPC8377E Pins
t
t
(5 ns)
DATA_DELAY
IH
t
(5 ns)
ISU
Figure 27. Full Speed Output Path
11.2.1.1 Full-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
No clock delay:
t
+ t
+ t
+ t
+ t
< t
< t
SFSKHOV
DATA_DELAY
ISU
SFSCKL
With clock delay:
t
t
+ t
SFSKHOV
DATA_DELAY
ISU
SFSCKL
CLK_DELAY
– t – t
+ t
< t
+ t
SFSCK CLK_DELAY ISU SFSKHOV
DATA_DELAY
SFSCKL
This means that data can be delayed versus clock up to 11 ns in ideal case of t
= 20 ns:
SFSCKL
t
t
+ 20 < 40 + t
– 5 – 4
DATA_DELAY
DATA_DELAY
CLK_DELAY
< 11 + t
CLK_DELAY
11.2.1.2 Full-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
t
t
< t
+ t + t
– t
DATA_DELAY IH
CLK_DELAY
CLK_DELAY
SFSCKL
SFSKHOX
+ t – t
< t
+ t
IH SFSKHOX
SFSCKL DATA_DELAY
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
45
Enhanced Secure Digital Host Controller (eSDHC)
This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of
t
= 20 ns:
SFSCLKL
t
t
+ 5 – 0 < 20 + t
CLK_DELAY
CLK_DELAY
DATA_DELAY
< 15 + t
DATA_DELAY
11.2.1.3 Full-Speed Write Combined Formula
The following equation is the combined formula to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
t
+ t – t
< t
+ t < t
DATA_DELAY
+ t
– t
– t
CLK_DELAY
IH SFSKHOX
SFSCKL
SFSCK CLK_DELAY ISU SFSKHOV
11.2.2 Full-Speed Input Path (Read)
Figure 28 provides the data and command input timing diagram.
t
(Clock Cycle)
SFSCK
SD CLK at the
MPC8377E Pin
Sampling
Edge
t
CLK_DELAY
SD CLK at
the Card Pin
Driving
Edge
t
t
DATA_DELAY
ODLY
t
OH
Output from the
SD Card Pins
Input at the
MPC8377E Pins
(MPC8377E Input Hold)
t
SFSIXKH
t
SFSIVKH
Figure 28. Full Speed Input Path
11.2.2.1 Full-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
t
t
+ t
+ t
+ t
< t
+ t
< t
CLK_DELAY
CLK_DELAY
DATA_DELAY
ODLY
SFSIVKH
– t – t
SFSCK
– t
DATA_DELAY
SFSCK ODLY SFSIVKH INT_CLK_DLY
11.2.2.2 Full-Speed Read Meeting Hold (Minimum Delay)
There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.
t
+ t + t
> t
DATA_DELAY SFSIXKH
CLK_DELAY
OH
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
46
Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled.
11.3 eSDHC AC Timing Specifications (High-Speed Mode)
Table 42 provides the eSDHC AC timing specifications for high-speed mode as defined in Figure 30 and
Figure 31.
Table 42. eSDHC AC Timing Specifications for High-Speed Mode
At recommended operating conditions OVDD = 3.3 V 165 mV.
1
Parameter
Symbol
Min
Max
Unit
Notes
SD_CLK clock frequency—high speed mode
SD_CLK clock cycle
f
0
20
0
50
—
MHz
ns
—
—
—
2
SHSCK
t
SFSCK
SD_CLK clock frequency—identification mode
SD_CLK clock low time
f
400
—
KHz
ns
SIDCK
t
7
SHSCKL
SD_CLK clock high time
t
7
—
ns
2
SHSCKH
SD_CLK clock rise and fall times
t
—
3
ns
2
SHSCKR/
t
SHSCKF
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
t
5
—
ns
2
SHSIVKH
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid
SD_CLK delay within device
t
0
—
0
—
4
ns
ns
ns
ns
ns
ns
ns
ns
2
2
2
4
3
3
3
3
SHSIXKH
t
SHSKHOV
SHSKHOX
t
—
—
—
—
14
—
t
1.5
6
INT_CLK_DLY
SD Card Input Setup
t
ISU
SD Card Input Hold
t
2
IH
SD Card Output Valid
t
—
2.5
ODLY
SD Card Output Hold
t
OH
Note:
1
The symbols used for timing specifications herein follow the pattern of t
(first three letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first three letters of functional block)(reference)(state)(signal)(state)
SFSIXKH
symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going
to high (H). Also t symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect
SFSKHOV
to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is
based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
2
3
4
Measured at capacitive load of 40 pF.
For reference only, according to the SD card specifications.
Average, for reference only.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
47
Enhanced Secure Digital Host Controller (eSDHC)
Figure 29 provides the eSDHC clock input timing diagram.
eSDHC
External Clock
VM
VM
VM
operational mode
t
L
t
SHSCK
SHSCKH
t
SHSCK
t
SHSCKF
t
SHSCKR
VM = Midpoint Voltage (OVDD/2)
Figure 29. eSDHC Clock Input Timing Diagram
11.3.1 High-Speed Output Path (Write)
Figure 30 provides the data and command output timing diagram.
t
(Clock Cycle)
SHSCK
SD CLK at the
MPC8377E Pin
Driving
Edge
t
CLK_DELAY
SD CLK at
the Card Pin
Sampling
Edge
Output Valid Time: t
Output Hold Time: t
SHSKHOV
t
SHSCKL
SHSKHOX
Output from the
MPC8377E Pins
Input at the
SD Card Pins
t
t
(2 ns)
DATA_DELAY
IH
t
(6 ns)
ISU
Figure 30. High Speed Output Path
11.3.1.1 High-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
Zero clock delay:
t
+ t
+ t
< t
SHSKHOV
DATA_DELAY
ISU
SHSCKL
With clock delay:
t
t
+ t
+ t
< t
+ t
CLK_DELAY
SHSKHOV
DATA_DELAY
ISU
SHSCKL
– t
DATA_DELAY CLK_DELAY
< t
– t
– t
SHSCKL ISU SHSKHOV
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
48
Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
This means that data delay should be equal or less than the clock delay in the ideal case where
= 10 ns:
t
SHSCLKL
t
t
– t
DATA_DELAY CLK_DELAY
< 10 – 6 – 4
– t
DATA_DELAY CLK_DELAY
< 0
11.3.1.2 High-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
t
t
< t
+ t + t
SHSKHOX
– t
DATA_DELAY IH
CLK_DELAY
SHSCKL
– t
CLK_DELAY DATA_DELAY
< t
+ t
– t
SHSKHOX IH
SHSCKL
This means that clock can be delayed versus data up to 8 ns (external delay line) in ideal case of
= 10 ns:
t
SHSCLKL
t
t
– t
CLK_DELAY DATA_DELAY
< 10 + 0 – 2
– t
CLK_DELAY DATA_DELAY
< 8
11.3.2 High-Speed Input Path (Read)
Figure 31 provides the data and command input timing diagram.
t
(Clock Cycle)
SHSCK
1/2 Cycle
Wrong Edge
Right Edge
SD CLK at the
MPC8377E Pin
Sampling
Edge
t
CLK_DELAY
Driving
Edge
SD CLK at
the Card Pin
t
ODLY
t
t
DATA_DELAY
OH
Output from the
SD Card Pins
Input at the
MPC8377E Pins
t
(MPC8377E Input Hold)
SHSIVKH
(MPC8377E Input Setup)
t
SHSIXKH
Figure 31. High Speed Input Path
For the input path, the device eSDHC expects to sample the data 1.5 internal clock cycles after it was
driven by the SD card. Since in this mode the SD card drives the data at the rising edge of the clock, a
sufficient delay to the clock and the data must exist to ensure it will not be sampled at the wrong internal
clock falling edge. Note that the internal clock which is guaranteed to be 50% duty cycle is used to sample
the data, and therefore used in the equations.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
49
JTAG
11.3.2.1 High-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
t
t
+ t
+ t
+ t
+ t
< 1.5 × t
SHSCK
CLK_DELAY
CLK_DELAY
DATA_DELAY
ODLY
SHSIVKH
< 1.5 × t
– t
– t
DATA_DELAY
SHSCK ODLY SHSIVKH
This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cycle:
t
t
+ t
+ t
< 30 – 14 – 5
CLK_DELAY
CLK_DELAY
DATA_DELAY
< 11
DATA_DELAY
11.3.2.2 High-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
0.5 × t
0.5 × t
< t
+ t
+ t – t
+ t
+ t
SHSCK
CLK_DELAY
DATA_DELAY
– t
OH SHSIXKH
INT_CLK_DLY
– t + t
< t
CLK_DELAY
SHSCK OH
SHSIXKH INT_CLK_DLY
DATA_DELAY
This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle:
10 – 2.5 + (-1.5) < t + t
CLK_DELAY
DATA_DELAY
6 < t
+ t
DATA_DELAY
CLK_DELAY
11.3.2.3 High-Speed Read Combined Formula
The following equation is the combined formula to calculate the propagation delay range of the SD_CLK
and SD_DAT/CMD signals on the PCB.
0.5 × t
– t + t
< t
+ t < 1.5 × t
DATA_DELAY
– t
– t
SHSCK OH
SHSIXKH
CLK_DELAY
SHSCK ODLY SHSIVKH
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of
the MPC8377E.
12.1 JTAG DC Electrical Characteristics
Table 43 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the
MPC8377E.
Table 43. JTAG interface DC Electrical Characteristics
Parameter
Input high voltage
Symbol
Condition
Min
Max
Unit
V
—
—
—
2.5
–0.3
—
OV + 0.3
V
V
IH
DD
Input low voltage
Input current
V
I
0.8
30
IL
μA
IN
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
50
JTAG
Table 43. JTAG interface DC Electrical Characteristics (continued)
Parameter
Output high voltage
Symbol
Condition
= –8.0 mA
OH
Min
Max
Unit
V
I
2.4
—
—
0.5
0.4
V
V
V
OH
Output low voltage
Output low voltage
V
I
= 8.0 mA
= 3.2 mA
OL
OL
OL
V
I
—
OL
12.2 JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.
Table 44 provides the JTAG AC timing specifications as defined in Figure 33 through Figure 36.
1
Table 44. JTAG AC Timing Specifications (Independent of CLKIN)
2
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
f
0
33.3
—
MHz
ns
—
—
—
—
3
JTG
JTG
t
30
15
0
t
—
ns
JTKHKL
t
& t
2
ns
JTGR
JTGF
t
25
—
ns
TRST
Input setup times:
ns
Boundary-scan data
t
t
4
4
—
—
4
4
JTDVKH
TMS, TDI
t
JTIVKH
Input hold times:
Valid times:
ns
ns
ns
Boundary-scan data
TMS, TDI
10
10
—
—
JTDXKH
t
JTIXKH
Boundary-scan data
TDO
t
t
2
2
11
11
—
—
JTKLDV
JTKLOV
Output hold times:
Boundary-scan data
TDO
t
t
2
2
—
—
JTKLDX
JTKLOX
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
51
JTAG
1
Table 44. JTAG AC Timing Specifications (Independent of CLKIN) (continued)
2
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock to output high impedance:
Boundary-scan data
TDO
ns
t
t
2
2
19
9
5
JTKLDZ
JTKLOZ
Notes:
1
All outputs are measured from the midpoint voltage of the falling/rising edge of t
to the midpoint of the signal in question.
TCLK
The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see Figure 17).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2
The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes JTAG
(first two letters of functional block)(reference)(state)(signal)(state)
JTDVKH
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
clock
JTG
reference (K) going to the high (H) state or setup time. Also, t
symbolizes JTAG timing (JT) with respect to the time
JTDXKH
data input signals (D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state. Note that, in general,
JTG
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3
4
5
TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
Non-JTAG signal input timing with respect to t
.
TCLK
Non-JTAG signal output timing with respect to t
.
TCLK
Figure 32 provides the AC test load for TDO and the boundary-scan outputs of the device.
Z = 50 Ω
OVDD/2
Output
0
R = 50 Ω
L
Figure 32. AC Test Load for the JTAG Interface
Figure 33 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
t
t
JTKHKL
JTGR
t
t
JTGF
JTG
VM = Midpoint Voltage (OVDD/2)
Figure 33. JTAG Clock Input Timing Diagram
Figure 34 provides the TRST timing diagram.
TRST
VM
VM
t
TRST
VM = Midpoint Voltage (OVDD/2)
Figure 34. TRST Timing Diagram
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Freescale Semiconductor
JTAG
Figure 35 provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
t
JTDVKH
t
JTDXKH
Boundary
Data Inputs
Input
Data Valid
t
JTKLDV
t
JTKLDX
Boundary
Data Outputs
Output Data Valid
t
JTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 35. Boundary-Scan Timing Diagram
Figure 36 provides the test access port timing diagram.
JTAG
VM
VM
External Clock
t
JTIVKH
t
JTIXKH
Input
TDI, TMS
TDO
Data Valid
t
JTKLOV
t
JTKLOX
Output Data Valid
t
JTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 36. Test Access Port Timing Diagram
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
53
I2C
13 I2C
2
This section describes the DC and AC electrical characteristics for the I C interface of the MPC8377E.
2
13.1 I C DC Electrical Characteristics
2
Table 45 provides the DC electrical characteristics for the I C interface of the MPC8377E.
2
Table 45. I C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V 165 mV.
Parameter
Symbol
Min
Max
Unit Notes
Input high voltage level
Input low voltage level
Low level output voltage
V
0.7 × OV
–0.3
OV + 0.3
V
V
—
—
1
IH
DD
DD
V
0.3 × OV
IL
DD
V
0
0.2 × OV
V
OL
DD
Output fall time from V (min) to V (max) with a bus capacitance
from 10 to 400 pF
t
20 + 0.1 × C
B
250
ns
2
IH
IL
I2KLKV
Pulse width of spikes which must be suppressed by the input filter
Capacitance for each I/O pin
t
0
50
10
30
ns
pF
μA
3
—
4
I2KHKL
C
—
—
I
Input current
I
IN
(0 V ≤ V ≤ OV
)
DD
IN
Note:
1
Output voltage (open drain or open collector) condition = 3 mA sink current.
2
3
C = capacitance of one bus line in pF.
B
Refer to the MPC8379E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter
used.
4
I/O pins will obstruct the SDA and SCL lines if OV is switched off.
DD
2
13.2 I C AC Electrical Specifications
2
Table 46 provides the AC timing parameters for the I C interface of the device.
2
Table 46. I C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 45).
1
Parameter
Symbol
Min
Max
Unit Notes
SCL clock frequency
f
0
400
—
kHz
μs
—
—
—
—
—
I2C
Low period of the SCL clock
High period of the SCL clock
t
1.3
0.6
0.6
0.6
I2CL
I2CH
t
—
μs
Setup time for a repeated START condition
t
—
μs
I2SVKH
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
t
—
μs
I2SXKL
Data setup time
t
100
—
ns
—
I2DVKH
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
54
Freescale Semiconductor
I2C
2
Table 46. I C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 45).
1
Parameter
Symbol
Min
Max
Unit Notes
Data hold time
t
μs
2, 3
I2DXKL
CBUS compatible masters
—
0
—
0.9
2
I C bus devices
Setup time for STOP condition
t
0.6
1.3
—
—
—
μs
μs
V
—
—
—
I2PVKH
Bus free time between a STOP and START condition
t
I2KHDX
Noise margin at the LOW level for each connected device (including
hysteresis)
V
0.1 × OV
NL
DD
DD
Noise margin at the HIGH level for each connected device (including
hysteresis)
V
0.2 × OV
—
V
—
NH
Note:
1
The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
2
for inputs and t
for outputs. For example, t
symbolizes I C timing
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K) going to the
I2C
2
high (H) state or setup time. Also, t
(S) went invalid (X) relative to the t
symbolizes I C timing (I2) for the time that the data with respect to the start condition
clock reference (K) going to the low (L) state or hold time. Also, t
I2SXKL
2
symbolizes I C
I2C
I2PVKH
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
clock
I2C
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2
3
MPC8377E provides a hold time of at least 300 ns for the SDA signal (referred to the V
undefined region of the falling edge of SCL.
of the SCL signal) to bridge the
IHmin
The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
I2CL
I2DVKH
2
Figure 37 provides the AC test load for the I C.
OVDD/2
Output
Z = 50 Ω
0
R = 50 Ω
L
2
Figure 37. I C AC Test Load
2
Figure 38 shows the AC timing diagram for the I C bus.
SDA
t
t
t
t
I2CF
I2CF
I2DVKH
I2KHKL
t
t
t
I2CR
I2CL
I2SXKL
SCL
t
t
t
t
I2PVKH
I2SXKL
I2CH
I2SVKH
t
I2DXKL
S
Sr
P
S
2
Figure 38. I C Bus AC Timing Diagram
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
55
PCI
14 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8377E.
14.1 PCI DC Electrical Characteristics
Table 47 provides the DC electrical characteristics for the PCI interface of the device. The DC
characteristics of the PORESET signal, which can be used as PCI RST in applications where the device is
a PCI agent, deviates from the standard PCI levels.
Table 47. PCI DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
V
≥ V (min) or
V
0.5 × OV
–0.5
OV + 0.5
V
V
OUT
OH
IH
DD
DD
DD
V
≤ V (max)
V
0.3 × OV
OUT
OL
IL
DD
I
= –500 μA
= 1500 μA
V
0.9 × OV
—
—
V
OH
OH
I
V
0.1 × OV
V
OL
OL
DD
0 V ≤ V ≤ OV
I
—
30
μA
IN
DD
IN
Note:
• The symbol V , in this case, represents the OV symbol referenced in Table 2.
IN
IN
14.2 PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the device. Note that the
PCI_CLK/PCI_SYNC_IN or CLKIN signal is used as the PCI input clock depending on whether the
MPC8377E is configured as a host or agent device. CLKIN is used when the device is in host mode.
Table 48 shows the PCI AC timing specifications at 66 MHz.
.
Table 48. PCI AC Timing Specifications at 66 MHz
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1×OVDD, VIH = 0.7×OVDD
.
1
Parameter
Clock to output valid
Symbol
Min
Max
Unit
Notes
t
t
t
—
1
6.0
—
ns
ns
ns
ns
2
PCKHOV
Output hold from Clock
Clock to output high impedance
Input setup to Clock
2
PCKHOX
PCKHOZ
—
3.0
14
—
2, 3
2, 4
t
PCIVKH
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Freescale Semiconductor
56
PCI
Table 48. PCI AC Timing Specifications at 66 MHz (continued)
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1×OVDD, VIH = 0.7×OVDD
.
1
Parameter
Input hold from Clock
Symbol
Min
Max
Unit
Notes
t
0.25
—
—
ns
ns
2, 4, 6
5
PCIXKH
Output Clock Skew
t
0.5
PCKOSK
Notes:
1
Note that the symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
PCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN
clock, t , reference (K) going to the high (H) state or setup time. Also, t symbolizes PCI timing (PC) with respect to
SYS
PCRHFV
the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2
3
See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4
5
6
Input timings are measured at the pin.
PCI specifications allows 1 ns skew for 66 MHz but includes the total allowed skew, board, connectors, etc.
Value does not comply with the PCI 2.3 Local Bus Specifications.
Table 49 shows the PCI AC timing specifications at 33 MHz.
Table 49. PCI AC Timing Specifications at 33 MHz
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 × OVDD, VIH = 0.7×OVDD
.
1
Parameter
Clock to output valid
Symbol
Min
Max
Unit
Notes
t
—
2
11
—
ns
ns
ns
ns
ns
ns
2
2
PCKHOV
Output hold from Clock
Clock to output high impedance
Input setup to Clock
t
PCKHOX
t
—
14
—
2, 3
2, 4
2, 4, 6
5
PCKHOZ
t
3.0
0.25
—
PCIVKH
Input hold from Clock
Output Clock skew
t
—
PCIXKH
t
0.5
PCKOSK
Note:
1
Note that the symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
PCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN
clock, t , reference (K) going to the high (H) state or setup time. Also, t symbolizes PCI timing (PC) with respect to
SYS
PCRHFV
the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2
3
See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4
5
6
Input timings are measured at the pin.
PCI specifications allows 2 ns skew for 33 MHz but includes the total allowed skew, board, connectors, etc.
Value does not comply with the PCI 2.3 Local Bus Specifications.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
57
PCI Express
Figure 39 provides the AC test load for PCI.
Output
OVDD/2
Z = 50 Ω
0
R = 50 Ω
L
Figure 39. PCI AC Test Load
Figure 40 shows the PCI input AC timing conditions.
CLK
t
PCIVKH
t
PCIXKH
Input
Figure 40. PCI Input AC Timing Measurement Conditions
Figure 41 shows the PCI output AC timing conditions.
CLK
t
PCKHOV
t
PCKHOX
Output Delay
t
PCKHOZ
High-Impedance
Output
Figure 41. PCI Output AC Timing Measurement Condition
15 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus.
15.1 DC Requirements for PCI Express SD_REF_CLK and
SD_REF_CLK
For more information see Section 21, “High-Speed Serial Interfaces (HSSI).”
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15.2 AC Requirements for PCI Express SerDes Clocks
Table 50 lists the PCI Express SerDes clock AC requirements.
Table 50. SD_REF_CLK and SD_REF_CLK AC Requirements
Parameter
Symbol
Min
Typical
Max
Unit
Notes
REFCLK cycle time
t
—
—
10
—
—
ns
ps
—
—
REF
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles.
t
t
100
REFCJ
REFCLK phase jitter peak-to-peak. Deviation in edge
location with respect to mean edge location.
–50
—
+50
ps
—
REFPJ
SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)
t
—
—
—
100
+50
ps
ps
—
CKCJ
SD_REF_CLK/_B phase jitter peak-to-peak. Deviation in
edge location with respect to mean edge location.
t
–50
2, 3
CKPJ
Note:
1
All options provide serial interface bit rate of 1.5 and 3.0 Gbps.
2
3
-12
In a frequency band from 150 kHz to 15 MHz, at BER of 10
.
Total peak-to-peak Deterministic Jitter “J ” should be less than or equal to 50 ps.
D
15.3 Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
15.4 Physical Layer Specifications
Following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer please use the PCI Express
Base Specification, Rev. 1.0a.
NOTE
The voltage levels of the transmitter and the receiver depend on the SerDes
control registers which should be programmed at the recommended values
for PCI Express protocol (that is, L1_nV = 1.0 V).
DD
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PCI Express
15.4.1 Differential Transmitter (Tx) Output
Table 51 defines the specifications for the differential output at all transmitters. The parameters are
specified at the component pins.
Table 51. Differential Transmitter (Tx) Output Specifications
Parameter
Unit interval
Conditions
Symbol
Min
Typical
Max
Units Notes
Each U
ppm. U
is 400 ps 300
UI
399.88
400
400.12
ps
1
PETX
does not account
PETX
for Spread Spectrum Clock
dictated variations.
Differential
peak-to-peak output
voltage
V
V
= 2 × |V
–
V
0.8
—
1.2
V
2
2
PEDPPTX
TX-D+
TX-DIFFp-p
|
TX-D-
De-emphasized
differential output
voltage (ratio)
Ratio of the V
second and following bits after
a transition divided by the
of the
V
–3.0
–3.5
–4.0
dB
PEDPPTX
TX-DE-RATIO
V
of the first bit after a
PEDPPTX
transition.
Minimum Tx eye width The maximum Transmitter
jitter can be derived as
T
0.70
—
—
—
—
UI
UI
2, 3
2, 3
TX-EYE
T
= 1 –
TX-MAX-JITTER
U
= 0.3 UI.
PEEWTX
Maximum time between Jitter is defined as the
T
0.15
TX-EYE-MEDIAN-to-
MAX-JITTER
the jitter median and
maximum deviation
from the median
measurement variation of the
crossing points (V = 0
V) in relation to a recovered
TX UI. A recovered TX UI is
calculated over 3500
PEDPPTX
consecutive unit intervals of
sample data. Jitter is
measured using all edges of
the 250 consecutive UI in the
center of the 3500 UI used for
calculating the TX UI.
D+/D– Tx output
rise/fall time
—
T
V
, T
0.125
—
—
—
—
UI
2, 5
2
TX-RISE TX-FALL
RMS AC peak common V
mode output voltage
= RMS(|V
–
V
TX-CM-ACp
20
mV
PEACPCMTX
TXD+
V
V
|/2 – V
)
TXD-
TX-CM-DC
= DC
of
TX-CM-DC
(avg)
|V
– V
|/2
TX-D+
TX-D-
Absolute delta of DC
common mode voltage V
|V
–
0
—
100
mV
2
TX-CM-DC (during LO)
TX-CM-DC- ACTIVE-
IDLE-DELTA
TX-CM-Idle-DC (During Electrical
during LO and electrical
idle
|<=100 mV
Idle)
V
= DC
of
(avg)
TX-CM-DC
|V
– V
|/2 [LO]
TX-D+
TX-D-
V
= DC
of
(avg)
TX-CM-Idle-DC
|V
– V
|/2 [Electrical
TX-D+
TX-D-
Idle]
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PCI Express
Table 51. Differential Transmitter (Tx) Output Specifications (continued)
Parameter
Conditions
– V
Symbol
Min
Typical
Max
Units Notes
Absolute delta of DC
common mode
between D+ and D–
|V
≤ 25 mV
V
|V
V
|
V
0
—
25
mV
2
TX-CM-DC-D+
TX-CM-DC-D-
TX-CM-DC-LINE-
DELTA
= DC
of
TX-CM-DC-D+
(avg)
(avg)
|
TX-D+
= DC
of
TX-CM-DC-D-
|V
|
TX-D-
Electrical idle
differential peak output -V
voltage
V
= |V
V
0
—
20
mV
mV
2
6
PEEIDPTX
TX-IDLE-D+
TX-IDLE-DIFFp
| ≤ 20 mV
TX-IDLE-D-
Amount of voltage
The total amount of voltage
V
—
XPADV /2
600
TX-RCV-DETECT
DD
change allowed during change that a transmitter can
receiver detection
apply to sense whether a low
impedance receiver is
present.
Tx DC common mode The allowed DC common
V
0
XPADV /2
—
90
—
V
mA
UI
6
TX-DC-CM
DD
voltage
mode voltage under any
conditions.
Tx short circuit current The total current the
limit transmitter can provide when
shorted to its ground
I
—
50
—
—
—
—
TX-SHORT
Minimum time spent in Minimum time a transmitter
T
TX-IDLE-MIN
electrical idle
must be in electrical idle.
Utilized by the receiver to start
looking for an electrical idle
exit after successfully
receiving an electrical idle
ordered set.
Maximum time to
transition to a valid
electrical idle after
sending an electrical
idle ordered set
After sending an electrical idle
ordered set, the transmitter
must meet all electrical idle
specifications within this time.
This is considered a
T
—
—
20
UI
—
TX-IDLE-SET-TO-IDLE
debounce time for the
transmitter to meet electrical
idle after transitioning from
LO.
Maximum time to
transition to valid Tx
specifications after
Maximum time to meet all Tx
specifications when
transitioning from electrical
T
—
—
20
UI
—
TX-IDLE-TO-DIFF-DATA
leaving an electrical idle idle to sending differential
condition
data. This is considered a
debounce time for the Tx to
meet all Tx specifications after
leaving electrical idle
Differential return loss Measured over 50 MHz to
1.25 GHz.
RL
12
—
—
dB
4
TX-DIFF
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PCI Express
Table 51. Differential Transmitter (Tx) Output Specifications (continued)
Parameter
Conditions
Symbol
RL
Min
Typical
Max
Units Notes
Common mode return Measured over 50 MHz to
6
—
—
dB
Ω
4
TX-CM
loss
1.25 GHz.
DC differential Tx
impedance
Tx DC differential mode low
impedance
Z
80
40
100
—
120
—
—
—
TX-DIFF-DC
Transmitter DC
impedance
Required Tx D+ as well as D–
DC impedance during all
states
Z
Ω
TX-DC
Lane-to-Lane output
skew
Static skew between any two
transmitter lanes within a
single link
L
—
—
—
500 +
2 UI
ps
—
—
TX-SKEW
AC coupling capacitor All transmitters should be AC
coupled. The AC coupling is
C
75
200
nF
TX
required either within the
media or within the
transmitting component itself.
Crosslink random
timeout
This random timeout helps
resolve conflicts in crosslink
configuration by eventually
resulting in only one
T
0
—
1
ms
7
crosslink
downstream and one
upstream port.
Note:
1
No test load is necessarily associated with this value.
2
Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 44 and measured over
any 250 consecutive Tx UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 42.)
3
A T
= 0.70 UI provides for a total sum of deterministic and random jitter budget of T
= 0.30 UI for the
TX-JITTER-MAX
TX-EYE
transmitter collected over any 250 consecutive Tx UIs. The T
median is less than half of the total
TX-EYE-MEDIAN-to-MAX-JITTER
Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed
to the averaged time value.
4
The transmitter input impedance will result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and
D– line (that is, as measured by a vector network analyzer with 50-Ω probes, see Figure 44). Note that the series capacitors,
C
, is optional for the return loss measurement.
TX
5
6
7
Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 44 for both V
See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.
and V
.
TX-D+
TX-D-
See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
15.4.2 Transmitter Compliance Eye Diagrams
The Tx eye diagram in Figure 42 is specified using the passive compliance/test measurement load (see
Figure 44) in place of any real PCI Express interconnect + Rx component. There are two eye diagrams that
must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate the
center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a
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PCI Express
transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always
relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx
UI.
NOTE
It is recommended that the recovered Tx UI be calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
VTX-DIFF = 0 mV
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
(D+ D– Crossing Point)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
[De-emphasized Bit]
566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)
0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX
)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
Figure 42. Minimum Transmitter Timing and Voltage Output Compliance Specifications
15.4.3 Differential Receiver (Rx) Input Specifications
Table 52 defines the specifications for the differential input at all receivers. The parameters are specified
at the component pins.
Table 52. Differential Receiver (Rx) Input Specifications
Parameter
Unit interval
Comments
Symbol
Min
Typical
Max
Units
Notes
Each U
ppm. U
is 400 ps 300
UI
399.88
400
400.12
ps
1
PERX
does not account
PERX
for Spread Spectrum Clock
dictated variations.
Differential peak-to-peak
output voltage
V
V
= 2 × |V
–
V
0.175
—
1.200
V
2
PEDPPRX
RX-D+
RX-DIFFp-p
|
RX-D-
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PCI Express
Table 52. Differential Receiver (Rx) Input Specifications (continued)
Parameter
Comments
Symbol
Min
Typical
Max
Units
Notes
Minimum receiver eye
width
The maximum interconnect
media and transmitter jitter that
can be tolerated by the receiver
can be derived as
T
0.4
—
—
UI
2, 3
RX-EYE
T
= 1 –
RX-MAX-JITTER
U
= 0.6 UI.
PEEWRX
Maximum time between
the jitter median and
Jitter is defined as the
measurement variation of the
T
—
—
0.3
UI
2, 3, 7
RX-EYE-MEDIAN-to
-MAX-JITTER
maximum deviation from crossing points (V
= 0
PEDPPRX
the median.
V) in relation to a recovered Tx
UI. A recovered Tx UI is
calculated over 3500
consecutive unit intervals of
sample data. Jitter is measured
using all edges of the 250
consecutive UI in the center of
the 3500 UI used for calculating
the Tx UI.
AC peak common mode
input voltage
V
V
V
= |V
–
V
RX-CM-ACp
—
10
6
—
—
—
150
—
mV
dB
dB
2
4
4
PEACPCMRX
RXD+
|/2 – V
RXD-
RX-CM-DC
= DC
of |V
RX-D+
RX-CM-DC
(avg)
– V
|/2
RX-D-
Differential return loss
Measured over 50 MHz to 1.25
GHz with the D+ and D– lines
biased at +300 mV and –300
mV, respectively.
RL
RX-DIFF
Common mode return
loss
Measured over 50 MHz to 1.25
GHz with the D+ and D– lines
biased at 0 V.
RL
—
RX-CM
DC differential input
impedance
RX DC differential mode
impedance.
Z
80
40
100
50
120
60
Ω
Ω
5
RX-DIFF-DC
DC Input Impedance
Required RX D+ as well as D-
DC impedance (50 20%
tolerance).
Z
2, 5
RX-DC
Powered down DC input Required RX D+ as well as D–
Z
200 k
65
—
—
—
Ω
6
RX-HIGH-IMP-DC
impedance
DC impedance when the
receiver terminations do not
have power.
Electrical idle detect
threshold
V
= 2 × |V
-V
|
V
175
mV
—
PEEIDT
RX-D+ RX-D-
RX-IDLE-DET-DIFF
p-p
Measured at the package pins
of the receiver
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PCI Express
Table 52. Differential Receiver (Rx) Input Specifications (continued)
Parameter
Comments
Symbol
Min
Typical
Max
Units
ms
Notes
Unexpected Electrical Idle An unexpected electrical idle
Enter Detect Threshold
Integration Time
T
—
—
10
—
RX-IDLE-DET-DIFF-
ENTERTIME
(Vrx-diffp-p <
Vrx-idle-det-diffp-p) must be
recognized no longer than
Trx-idle-det-diff-entertime to
signal an unexpected idle
condition.
Total Skew
Skew across all lanes on a link.
This includes variation in the
length of SKP ordered set (e.g.
COM and one to five SKP
L
—
—
20
ns
—
RX-SKEW
Symbols) at the Rx as well as
any delay differences arising
from the interconnect itself.
Note:
1
No test load is necessarily associated with this value.
2
Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 44 should be used
as the Rx device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 43). If the
clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must be
used as a reference for the eye diagram.
3
A T
= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
Rx-EYE
interconnect collected any 250 consecutive UIs. The TRx-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
4
The receiver input impedance will result in a differential return loss greater than or equal to 10 dB with the D+ line biased to
300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference
impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured by a vector
network analyzer with 50-Ω probes, see Figure 44). Note that the series capacitors, C , is optional for the return loss
Tx
measurement.
5
6
Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there
is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure
that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured
at 300 mV above the Rx ground.
7
It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated
data.
15.5 Receiver Compliance Eye Diagrams
The Rx eye diagram in Figure 43 is specified using the passive compliance/test measurement load (see
Figure 44) in place of any real PCI Express Rx component. In general, the minimum receiver eye diagram
measured with the compliance/test measurement load (see Figure 44) is larger than the minimum receiver
eye diagram measured over a range of systems at the input receiver of any real PCI Express component.
The degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon
™
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65
PCI Express
parasitic characteristics that cause the real PCI Express component to vary in impedance from the
compliance/test measurement load. The input receiver eye diagram is implementation specific and is not
specified. Rx component designer should provide additional margin to adequately compensate for the
degraded minimum receiver eye diagram (shown in Figure 43) expected at the input receiver based on an
adequate combination of system simulations and the return loss measured looking into the Rx package and
silicon. The Rx eye diagram must be aligned in time using the jitter median to locate the center of the eye
diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx
UI.
NOTE
The reference impedance for return loss measurements is 50. to ground for
both the D+ and D– line (that is, as measured by a Vector Network Analyzer
with 50. probes—see Figure 44). Note that the series capacitors, C
are optional for the return loss measurement.
,
PEACCTX
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
Figure 43. Minimum Receiver Eye Timing and Voltage Compliance Specification
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Freescale Semiconductor
Serial ATA (SATA)
15.5.1 Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test/measurement load shown in Figure 44.
NOTE
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary. If the vendor does not explicitly state where the measurement
point is located, the measurement point is assumed to be the D+ and D–
package pins.
D+ Package Pin
C = C
C = C
TX
TX
TX Silicon +
Package
R = 50 Ω
R = 50 Ω
D– Package Pin
Figure 44. Compliance Test/Measurement Load
16 Serial ATA (SATA)
This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the
MPC8377E. Note that the external cabled applications or long backplane applications (Gen1x and Gen2x)
are not supported.
16.1 Requirements for SATA REF_CLK
The reference clock is a single ended input clock required for the SATA interface operation. The AC
requirements for the SATA reference clock are listed in the Table 53.
Table 53. SATA Reference Clock Input Requirements
Parameter
Condition
Symbol
Min
Typical
Max
Unit
Notes
SD_REF_CLK/ SD_REF_CLK
frequency range
—
t
—
100/125/150
—
MHz
1
CLK_REF
SD_REF_CLK/ SD_REF_CLK
clock frequency tolerance
—
t
–350
40
0
+350
60
ppm
%
—
—
CLK_TOL
SD_REF_CLK/ SD_REF_CLK
reference clock duty cycle
Measured at 1.6V
t
50
CLK_DUTY
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67
Serial ATA (SATA)
Table 53. SATA Reference Clock Input Requirements (continued)
Parameter
Condition
Symbol
Min
Typical
Max
Unit
Notes
SD_REF_CLK/ SD_REF_CLK
cycle to cycle Clock jitter (period
jitter)
Cycle-to-cycle at
ref clock input
t
—
—
100
ps
—
CLK_CJ
CLK_PJ
SD_REF_CLK/ SD_REF_CLK total Peak-to-peak jitter
t
–50
—
+50
ps
2, 3
reference clock jitter, phase jitter
(peak-peak)
at ref clock input
Note:
1
Only 100/125/150 MHz have been tested, othe in between values will not work correctly with the rest of the system.
2
3
-12
In a frequency band from 150 kHz to 15 MHz at BER of 10
.
Total peak to peak Deterministic Jitter "D " should be less than or equal to 50 ps.
J
Figure 45 shows the SATA reference clock timing waveform.
T
H
Ref_CLK
T
L
Figure 45. SATA Reference Clock Timing Waveform
16.2 Transmitter (Tx) Output Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA
interface.
16.2.1 Gen1i/1.5G Transmitter Specifications
Table 54 provides the DC differential transmitter output DC characteristics for the SATA interface at
Gen1i or 1.5 Gbits/s transmission.
Table 54. Gen1i/1.5G Transmitter (Tx) DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
mV
Notes
Tx differential output voltage
Tx differential pair impedance
Note:
V
400
85
500
100
600
115
1
SATA_TXDIFF
p-p
Z
Ω
—
SATA_TXDIFFIM
1
Terminated by 50 Ω load.
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Serial ATA (SATA)
Table 55 provides the differential transmitter output AC characteristics for the SATA interface at Gen1i or
1.5 Gbits/s transmission.
Table 55. Gen1i/1.5G Transmitter AC Specifications
Parameter
Channel speed
Symbol
Min
Typical
Max
Units
Notes
t
—
666.4333
—
1.5
666.667
—
—
Gbps
ps
—
—
1
CH_SPEED
Unit interval
T
670.2333
0.355
UI
SATA_TXTJ5UI
Total jitter, data-data
5 UI
U
UI
UI
UI
UI
p-p
p-p
p-p
p-p
Total jitter, data-data
250 UI
U
—
—
—
—
—
—
0.47
0.175
0.22
1
1
1
SATA_TXTJ250UI
Deterministic jitter, data-data
5 UI
U
SATA_TXDJ5UI
Deterministic jitter, data-data
250 UI
U
SATA_TXDJ250UI
Note:
1
Measured at Tx output pins peak to peak phase variation, random data pattern.
16.2.2 Gen2i/3G Transmitter Specifications
Table 56 provides the differential transmitter output DC characteristics for the SATA interface at Gen2i or
3.0 Gbits/s transmission.
Table 56. Gen 2i/3G Transmitter DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
mV
Notes
Tx differential output voltage
Tx differential pair impedance
Note:
V
400
85
550
100
700
115
1
SATA_TXDIFF
p-p
Z
Ω
—
SATA_TXDIFFIM
1
Terminated by 50 Ω load.
Table 57 provides the differential transmitter output AC characteristics for the SATA interface at Gen2i or
3.0 Gbits/s transmission.
Table 57. Gen 2i/3G Transmitter AC Specifications
Parameter
Channel speed
Symbol
Min
Typical
Max
Units
Notes
t
—
333.2
—
3.0
333.33
—
—
335.11
0.3
Gbps
ps
—
—
1
CH_SPEED
Unit interval
Total jitter
T
UI
SATA_TXTJfB/10
U
UI
p-p
f
=f
/10
C3dB BAUD
Total jitter
= f
U
—
—
0.37
UI
1
SATA_TXTJfB/500
p-p
f
/500
BAUD
C3dB
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Serial ATA (SATA)
Table 57. Gen 2i/3G Transmitter AC Specifications (continued)
Parameter
Symbol
Min
Typical
Max
Units
Notes
Total jitter
= f
U
—
—
0.55
UI
UI
UI
UI
1
SATA_TXTJfB/1667
p-p
p-p
p-p
p-p
f
/1667
BAUD
C3dB
Deterministic jitter
= f /10
U
—
—
—
—
—
—
0.17
0.19
0.35
1
1
1
SATA_TXDJfB/10
SATA_TXDJfB/500
U
SATA_TXDJfB/1667
f
C3dB
BAUD
Deterministic jitter
= f /500
U
f
C3dB
BAUD
Deterministic jitter
= f /1667
f
C3dB
BAUD
Note:
1
Measured at Tx output pins peak to peak phase variation, random data pattern.
16.3 Differential Receiver (Rx) Input Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G differential receiver input AC characteristics.
16.3.1 Gen1i/1.5G Receiver Specifications
Table 58 provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA
interface.
Table 58. Gen1i/1.5G Receiver Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
mV
Notes
Differential input voltage
V
Z
240
85
500
100
600
115
1
SATA_RXDIFF
p-p
Differential Rx input impedance
Ω
—
SATA_RXSEIM
Note:
1
Voltage relative to common of either signal comprising a differential pair.
Table 59 provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA
interface.
Table 59. Gen 1i/1.5G Receiver AC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Unit interval
T
666.4333
—
666.667
—
670.2333
0.43
ps
—
1
UI
Total jitter, data-data
5 UI
U
UI
UI
UI
SATA_TXTJ5UI
p-p
p-p
p-p
Total jitter, data-data
250 UI
U
—
—
—
—
0.60
0.25
1
1
SATA_TXTJ250UI
Deterministic jitter, data-data
5 UI
U
SATA_TXDJ5UI
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Serial ATA (SATA)
Table 59. Gen 1i/1.5G Receiver AC Specifications (continued)
Parameter
Symbol
Min
Typical
Max
Units
UI
Notes
Deterministic jitter, data-data
250 UI
U
—
—
0.35
1
SATA_TXDJ250UI
p-p
Note:
1
Measured at Tx output pins peak to peak phase variation, random data pattern.
16.3.2 Gen2i/3G Receiver (Rx) Specifications
Table 60 provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA
interface.
Table 60. Gen2i/3G Receiver Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input voltage
V
Z
275
85
500
100
750
115
mVp-p
1
SATA_RXDIFF
Differential RX input impedance
Ω
—
SATA_RXSEIM
Note:
1
Voltage relative to common of either signal comprising a differential pair.
Table 61 provides the differential receiver output AC characteristics for the SATA interface at Gen2i or
3.0 Gbits/s transmission.
Table 61. Gen 2i/3G Receiver AC Specifications
Parameter
Channel Speed
Symbol
Min
Typical
Max
Units
Notes
t
—
333.2
—
3.0
333.33
—
—
Gbps
ps
—
—
1
CH_SPEED
Unit Interval
Total jitter
T
335.11
0.46
UI
SATA_TXTJfB/10
U
UI
UI
UI
UI
UI
UI
p-p
p-p
p-p
p-p
p-p
p-p
f
= f
/10
C3dB
BAUD
Total jitter
= f
U
—
—
—
—
—
—
—
—
—
—
0.60
0.65
0.35
0.42
0.35
1
1
1
1
1
SATA_TXTJfB/500
f
/500
/1667
C3dB
BAUD
Total jitter
= f
U
SATA_TXTJfB/1667
f
C3dB
BAUD
Deterministic jitter
= f /10
U
SATA_TXDJfB/10
SATA_TXDJfB/500
U
SATA_TXDJfB/1667
f
C3dB
BAUD
Deterministic jitter
= f /500
U
f
C3dB
BAUD
Deterministic jitter
= f /1667
f
C3dB
BAUD
Note:
1
Measured at Tx output pins peak to peak phase variation, random data pattern.
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Timers
17 Timers
This section describes the DC and AC electrical specifications for the timers of the MPC8377E.
17.1 Timers DC Electrical Characteristics
Table 62 provides the DC electrical characteristics for the device timers pins, including TIN, TOUT,
TGATE, and RTC_CLK.
Table 62. Timers DC Electrical Characteristics
Parameter
Output high voltage
Condition
= –6.0 mA
Symbol
Min
Max
Unit
I
V
2.4
—
—
0.5
0.4
V
V
OH
OH
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
I
= 6.0 mA
= 3.2 mA
—
V
OL
OL
OL
I
V
—
V
OL
V
2.0
–0.3
—
OV + 0.3
V
IH
DD
—
V
0.8
30
V
IL
0 V ≤ V ≤ OV
I
μA
IN
DD
IN
17.2 Timers AC Timing Specifications
Table 63 provides the timers input and output AC timing specifications.
Table 63. Timers Input AC Timing Specifications 1
Parameter Symbol
Timers inputs—minimum pulse width
2
Min
Unit
t
20
ns
TIWID
Note:
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2
Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any
external synchronous logic. Timers inputs are required to be valid for at least t
ns to ensure proper operation
TIWID
Figure 46 provides the AC test load for the timers.
Output
OVDD/2
Z = 50 Ω
0
R = 50 Ω
L
Figure 46. Timers AC Test Load
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GPIO
18 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the MPC8377E.
18.1 GPIO DC Electrical Characteristics
Table 64 provides the DC electrical characteristics for the device GPIO.
Table 64. GPIO DC Electrical Characteristics
This specification applies when operating at 3.3 V 165 mV supply.
Parameter
Output high voltage
Condition
= –6.0 mA
Symbol
Min
Max
Unit
I
V
2.4
—
—
0.5
0.4
V
V
OH
OH
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
I
= 6.0 mA
= 3.2 mA
—
V
OL
OL
I
V
—
V
OL
OL
V
2.0
–0.3
—
OV + 0.3
V
IH
DD
—
V
I
0.8
30
V
IL
0 V ≤ V ≤ OV
μA
IN
DD
IN
18.2 GPIO AC Timing Specifications
Table 65 provides the GPIO input and output AC timing specifications.
Table 65. GPIO Input AC Timing Specifications
Parameter Symbol
Min
20
Unit
ns
GPIO inputs—minimum pulse width
Note:
t
PIWID
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLKIN. Timings
are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least t
ns to ensure proper operation.
PIWID
Figure 47 provides the AC test load for the GPIO.
OVDD/2
Output
Z = 50 Ω
0
R = 50 Ω
L
Figure 47. GPIO AC Test Load
19 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins of the
MPC8377E.
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SPI
19.1 IPIC DC Electrical Characteristics
Table 66 provides the DC electrical characteristics for the external interrupt pins of the MPC8377E.
Table 66. IPIC DC Electrical Characteristics
Parameter
Input high voltage
Condition
Symbol
Min
Max
Unit
—
—
—
V
2.0
–0.3
—
OV + 0.3
V
V
IH
DD
Input low voltage
Input current
V
I
0.8
30
IL
μA
V
IN
Output low voltage
Output low voltage
Note:
I
= 6.0 mA
= 3.2 mA
V
—
0.5
0.4
OL
OL
I
V
—
V
OL
OL
1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT.
2. IRQ_OUT and MCP_OUT are open drain pins, thus V is not relevant for those pins.
OH
19.2 IPIC AC Timing Specifications
Table 67 provides the IPIC input and output AC timing specifications.
Table 67. IPIC Input AC Timing Specifications
Parameter
Symbol
Min
Unit
IPIC inputs—minimum pulse width
t
20
ns
PIWID
Note:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
external synchronous logic. IPIC inputs are required to be valid for at least t
in edge triggered mode.
ns to ensure proper operation when working
PIWID
20 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8377E.
20.1 SPI DC Electrical Characteristics
Table 68 provides the DC electrical characteristics for the device SPI.
Table 68. SPI DC Electrical Characteristics
Parameter
Input high voltage
Condition
Symbol
Min
Max
Unit
—
—
—
V
2.0
–0.3
—
OV + 0.3
V
V
IH
DD
Input low voltage
Input current
V
I
0.8
30
—
IL
μA
V
IN
Output high voltage
I
= –8.0 mA
V
2.4
OH
OH
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SPI
Table 68. SPI DC Electrical Characteristics (continued)
Parameter
Condition
Symbol
Min
Max
Unit
Output low voltage
Output low voltage
I
= 8.0 mA
= 3.2 mA
V
—
—
0.5
0.4
V
V
OL
OL
I
V
OL
OL
20.2 SPI AC Timing Specifications
Table 69 provides the SPI input and output AC timing specifications.
Table 69. SPI AC Timing Specifications
1
Parameter
Symbol
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
SPI outputs—Slave mode (external clock) delay
SPI inputs—Master mode (internal clock) input setup time
SPI inputs—Master mode (internal clock)input hold time
SPI inputs—Slave mode (external clock) input setup time
SPI inputs—Slave mode (external clock) input hold time
Note:
t
0.5
2
6
ns
ns
ns
ns
ns
ns
NIKHOV
t
8
NEKHOV
t
4
—
—
—
—
NIIVKH
t
0
NIIXKH
t
4
NEIVKH
NEIXKH
t
2
1
The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state) (reference)(state)
inputs and t
for outputs. For example, t
symbolizes the internal
(first two letters of functional block)(reference)(state)(signal)(state)
NIKHOV
timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin. The maximum SPICLK input frequency is 66.666 MHz.
Figure 48 provides the AC test load for the SPI.
Output
OVDD/2
Z = 50 Ω
0
R = 50 Ω
L
Figure 48. SPI AC Test Load
Figure 49 through Figure 50 represent the AC timing from Table 69. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
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High-Speed Serial Interfaces (HSSI)
Figure 49 shows the SPI timing in slave mode (external clock).
SPICLK (input)
tN
EIXKH
t
NEIVKH
Input Signals:
SPIMOSI
(See Note)
t
NEKHOV
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 49. SPI AC Timing in Slave Mode (External Clock) Diagram
Figure 50 shows the SPI timing in master mode (internal clock).
SPICLK (output)
t
NIIXKH
t
NIIVKH
Input Signals:
SPIMISO
(See Note)
t
NIKHOV
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
Figure 50. SPI AC Timing in Master Mode (Internal Clock) Diagram
21 High-Speed Serial Interfaces (HSSI)
The MPC8377E features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial
interconnect applications. See Table 1 for the interfaces supported.
This section describes the common portion of SerDes DC electrical specifications, which is the DC
requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits
are also shown.
21.1 Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 51 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for
description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a
receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B.
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High-Speed Serial Interfaces (HSSI)
Using this waveform, the definitions are as follows. To simplify illustration, the following definitions
assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling
environment.
•
•
•
Single-Ended Swing
The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and
SDn_RX each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s
single-ended swing.
Differential Output Voltage, V (or Differential Output Swing):
OD
The differential output voltage (or swing) of the transmitter, V , is defined as the difference of
the two complimentary output voltages: V
or negative.
OD
– V . The V value can be either positive
SDn_TX
SDn_TX OD
Differential Input Voltage, V (or Differential Input Swing):
ID
The differential input voltage (or swing) of the receiver, V , is defined as the difference of the two
ID
complimentary input voltages: V
negative.
– V The V value can be either positive or
SDn_RX
SDn_RX. ID
•
•
Differential Peak Voltage, V
DIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal
is defined as differential peak voltage, V = |A – B| volts.
DIFFp
Differential Peak-to-Peak, V
DIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter
output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,
V
= 2 × V
= 2 × |(A – B)| volts, which is twice of differential swing in amplitude, or
DIFFp-p
DIFFp
twice of the differential peak. For example, the output differential peak-peak voltage can also be
calculated as V = 2 × |V |.
TX-DIFFp-p
OD
•
•
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for
example) from the non-inverting signal (SDn_TX, for example) within a differential pair. There is
only one signal trace curve in a differential waveform. The voltage represented in the differential
waveform is not referenced to ground. Refer to Figure 60 as an example for differential waveform.
Common Mode Voltage, V
cm
The common mode voltage is equal to one half of the sum of the voltages between each conductor
of a balanced interchange circuit and ground. In this example, for SerDes output,
V
= (V
+ V
) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two
cm_out
SDn_TX
SDn_TX
complimentary output voltages within a differential pair. In a system, the common mode voltage
may often differ from one component’s output to the other’s input. Sometimes it may be even
different between the receiver input and driver output circuits within the same component. It is also
referred as the DC offset in some occasion.
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High-Speed Serial Interfaces (HSSI)
SDn_TX or
SDn_RX
A Volts
B Volts
V
= (A + B)/2
cm
SDn_TXor
SDn_RX
Differential Swing, VID or VOD = A – B
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown)
Figure 51. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV , which is referred as the single-ended swing for each signal. In this example, since
p-p
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
OD
between 500 mV and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other
OD
phase. The peak differential voltage (V
) is 500 mV. The peak-to-peak differential voltage (V
)
DIFFp
DIFFp-p
is 1000 mV
.
p-p
21.2 SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for both lanes of SerDes1, and SD2_REF_CLK and SD2_REF_CLK for both lanes of
SerDes2.
The following sections describe the SerDes reference clock requirements and some application
information.
21.2.1 SerDes Reference Clock Receiver Characteristics
Figure 52 shows a receiver reference diagram of the SerDes reference clocks.
•
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
shown in Figure 52. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
50 Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
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High-Speed Serial Interfaces (HSSI)
— The SerDes reference clock input can be either differential or single-ended. Refer to the
Differential Mode and Single-ended Mode description below for further detailed requirements.
•
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
(0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above
SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such
that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to
SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it
must be AC-coupled off-chip.
•
The input amplitude requirement
— This requirement is described in detail in the following sections.
50 Ω
SDn_REF_CLK
Input
Amp
SDn_REF_CLK
50 Ω
Figure 52. Receiver of SerDes Reference Clocks
21.2.2 DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the device SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
•
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV
differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,
each signal wire of the differential pair must have a single-ended swing less than 800 mV and
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High-Speed Serial Interfaces (HSSI)
greater than 200 mV. This requirement is the same for both external DC-coupled or
AC-coupled connection.
— For external DC-coupled connection, as described in Section 21.2.1, “SerDes Reference
Clock Receiver Characteristics,” the maximum average current requirements sets the
requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV.
Figure 53 shows the SerDes reference clock input requirement for DC-coupled connection
scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn). Figure 54 shows the SerDes reference clock
input requirement for AC-coupled connection scheme.
•
Single-ended Mode
— The reference clock can also be single-ended. The SD _REF_CLK input amplitude
(single-ended swing) must be between 400 mV and 800 mV (from V to V ) with
p-p
min
max
SDn_REF_CLK either left unconnected or tied to ground.
— The SDn_REF_CLK input average voltage must be between 200 mV and 400 mV. Figure 55
shows the SerDes reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
AC-coupled externally. For the best noise performance, the reference of the clock could be DC
or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as
the clock input (SDn_REF_CLK) in use.
200 mV < Input Amplitude or Differential Peak < 800 mV
SDn_REF_CLK
V
< 800 mV
max
100 mV < V < 400 mV
cm
V
> 0 V
SDn_REF_CLK
min
Figure 53. Differential Reference Clock Input DC Requirements (External DC-Coupled)
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High-Speed Serial Interfaces (HSSI)
200 mV < Input Amplitude or Differential Peak < 800 mV
SDn_REF_CLK
SDn_REF_CLK
150
fdafdV
< V + 400 mV
cm
max
V
< V + 400 mV
max
cm
Vcm
V
> V – 400m V
min
cm
Figure 54. Differential Reference Clock Input DC Requirements (External AC-Coupled)
400 mV < SDn_REF_CLK Input Amplitude < 800 mV
SDn_REF_CLK
0 V
SDn_REF_CLK
Figure 55. Single-Ended Reference Clock Input DC Requirements
21.2.3 Interfacing With Other Differential Signaling Levels
The following list provides information about interfacing with other differential signaling levels.
•
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are
HCSL (high-speed current steering logic) compatible DC-coupled.
•
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC-coupled due to the limited common mode input range allowed
(100 mV to 400 mV) for DC-coupled connection.
•
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in
addition to AC-coupling.
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
81
High-Speed Serial Interfaces (HSSI)
NOTE
Figure 56 to Figure 59 below are for conceptual reference only. Due to the
fact that clock driver chip's internal structure, output impedance, and
termination requirements are different between various clock driver chip
manufacturers, it is very possible that the clock circuit reference designs
provided by the clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the device SerDes reference clock receiver requirement
provided in this document.
Figure 56 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with device SerDes reference clock
input’s DC requirement.
MPC8377E
HCSL CLK Driver Chip
50 Ω
SDn_REF_CLK
CLK_Out
33 Ω
33 Ω
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
CLK_Out
SDn_REF_CLK
50 Ω
Clock driver vendor dependent
source termination resistor
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
Figure 56. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 57 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common mode voltage is higher than the device SerDes reference clock input’s
allowed range (100 to 400 mV), AC-coupled connection scheme must be used. It assumes the LVDS
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
82
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
output driver features a 50-Ω termination resistor. It also assumes that the LVDS transmitter establishes its
own common mode level without relying on the receiver or other external component.
MPC8377E
LVDS CLK Driver Chip
50
Ω
SDn_REF_CLK
SDn_REF_CLK
10 nF
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
CLK_Out
10 nF
50 Ω
Figure 57. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
Figure 58 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with
device SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 58 assumes
that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL outputs
prior to AC-coupling. Its value could be ranged from 140 Ω to 240 Ω depending on clock driver vendor’s
requirement. R2 is used together with the SerDes reference clock receiver’s 50 Ω termination resistor to
attenuate the LVPECL output’s differential peak level such that it meets the device SerDes reference
clock’s differential input amplitude requirement (between 200 mV and 800 mV differential peak). For
example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input
amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. Please consult
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
83
High-Speed Serial Interfaces (HSSI)
clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular
clock driver chip.
MPC8377E
LVPECL CLK Driver Chip
50 Ω
SDn_REF_CLK
CLK_Out
10 nF
R2
SerDes Refer.
CLK Receiver
R1
R1
100 Ω differential PWB trace
10 nF
Clock Driver
R2
SDn_REF_CLK
CLK_Out
50 Ω
Figure 58. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Figure 59 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’s DC
requirement.
Single-Ended CLK
Driver Chip
MPC8377E
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
SDn_REF_CLK
33 Ω
Clock Driver
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
SDn_REF_CLK
50
Ω
50 Ω
Figure 59. Single-Ended Connection (Reference Only)
21.2.4 AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
84
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 70 describes some AC parameters common to PCI Express and SATA protocols.
Table 70. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS or XVDD_SRDS = 1.0 V 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising Edge Rate
Falling Edge Rate
Rise Edge Rate
Fall Edge Rate
1.0
1.0
200
—
4.0
4.0
—
V/ns
V/ns
mV
mV
%
2, 3
2, 3
2
Differential Input High Voltage
Differential Input Low Voltage
V
IH
V
–200
20
2
IL
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Rise-Fall Matching
—
1, 4
Note:
1
Measurement taken from single ended waveform.
2
Measurement taken from differential waveform.
3
Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 60.
4
Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge
Rate of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference
should not exceed 20% of the slowest edge rate. See Figure 61.
Rise Edge Rate
Fall Edge Rate
VIH = +200 mV
0.0 V
VIL = –200 mV
SDn_REF_CLK
Minus
SDn_REF_CLK
Figure 60. Differential Measurement Points for Rise and Fall Time
T
T
RISE
FALL
SDn_REF_CLK
SDn_REF_CLK
V
V
+100 mV
CROSS MEDIAN
V
V
CROSS MEDIAN
CROSS MEDIAN
–100 mV
CROSS MEDIAN
SDn_REF_CLK
SDn_REF_CLK
Figure 61. Single-Ended Measurement Points for Rise and Fall Time Matching
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
85
Package and Pin Listings
21.3 SerDes Transmitter and Receiver Reference Circuits
Figure 62 shows the reference circuits for SerDes data lane’s transmitter and receiver.
SD1_RXn or
SD2_RXn
SD1_TXn or
SD2_TXn
50
50
Ω
Ω
50 Ω
50 Ω
Receiver
Transmitter
SD1_TXn or
SD2_TXn
SD1_RXn or
SD2_RXn
Figure 62. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below in
this document based on the application usage:
•
•
•
Section 8, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC)”
Section 15, “PCI Express”
Section 16, “Serial ATA (SATA)”
Note that an external AC coupling capacitor is required for the above three serial transmission protocols
with the capacitor value defined in specification of each protocol section.
22 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions.
22.1 Package Parameters for the MPC8377E TePBGA II
The package parameters are provided in the following list. The package type is 31 mm 31 mm,
×
689 plastic ball grid array (TePBGA II).
Package outline
Interconnects
31 mm × 31 mm
689
Pitch
1.00 mm
Module height (typical)
Solder Balls
2.0 mm to 2.46 mm (maximum)
3.5% Ag, 96.5% Sn
0.60 mm
Ball diameter (typical)
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
86
Package and Pin Listings
Figure 63 shows the mechanical dimensions and bottom surface nomenclature of the TEPBGA II package.
Figure 63. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II
Note:
1
All dimensions are in millimeters.
2
Dimensioning and tolerancing per ASME Y14. 5M-1994.
3
Maximum solder ball diameter measured parallel to Datum A.
4
Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5
Parallelism measurement should exclude any effect of mark on top surface of package.
22.2 Pinout Listings
Table 71 provides the pin-out listing for the TePBGA II package.
Table 71. TePBGA II Pinout Listing
Signal
Package Pin Number
Pin Type
Power Supply
Notes
Clock Signals
CLKIN
K24
I
OVDD
—
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
87
Package and Pin Listings
Signal
Table 71. TePBGA II Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
PCI_CLK/PCI_SYNC_IN
C10
N24
L24
I
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
3
PCI_SYNC_OUT
PCI_CLK0
O
O
O
O
O
O
I
—
—
—
—
—
—
PCI_CLK1
M24
M25
M26
L26
PCI_CLK2
PCI_CLK3
PCI_CLK4
RTC/PIT_CLOCK
AF11
DDR SDRAM Memory Interface
MA0
MA1
U3
U1
T5
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MA2
MA3
T3
MA4
T2
MA5
T1
MA6
R1
P2
P1
N4
V3
M5
N1
M2
M1
U5
U4
M3
W5
H1
K1
V1
W2
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MBA0
MBA1
MBA2
MCAS_B
MCK_B0
MCK_B1
MCK_B2
MCK_B3
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Freescale Semiconductor
Package and Pin Listings
Table 71. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
MCK_B4
MCK_B5
MCK0
AA1
AB2
J1
O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
3
O
MCK1
L1
O
MCK2
V2
O
MCK3
W1
Y1
O
MCK4
O
MCK5
AB1
M4
R5
W3
P3
O
MCKE0
MCKE1
MCS_B0
MCS_B1
MCS_B2
MCS_B3
MDIC0
MDIC1
MDM0
MDM1
MDM2
MDM3
MDM4
MDM5
MDM6
MDM7
MDM8
MDQ0
MDQ1
MDQ2
MDQ3
MDQ4
MDQ5
MDQ6
MDQ7
O
O
3
O
—
—
—
—
9
O
T4
O
R4
AH8
AJ8
B6
O
I/O
I/O
O
9
—
—
—
—
—
—
—
—
—
11
11
11
11
11
11
11
11
B2
O
E2
O
E1
O
Y6
O
AC6
AE6
AJ4
L6
O
O
O
O
A8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A6
C7
D8
A7
A5
A3
C6
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Freescale Semiconductor
89
Package and Pin Listings
Signal
Table 71. TePBGA II Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
MDQ8
MDQ9
D7
E8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
MDQ10
MDQ11
MDQ12
MDQ13
MDQ14
MDQ15
MDQ16
MDQ17
MDQ18
MDQ19
MDQ20
MDQ21
MDQ22
MDQ23
MDQ24
MDQ25
MDQ26
MDQ27
MDQ28
MDQ29
MDQ30
MDQ31
MDQ32
MDQ33
MDQ34
MDQ35
MDQ36
MDQ37
MDQ38
MDQ39
MDQ40
B1
D5
B3
D6
C3
C2
D4
E6
F6
G4
F8
E4
C1
G6
F2
G5
H6
H4
D1
G3
H5
F1
W6
AC1
AC3
AE1
V6
Y5
AA4
AB6
AD3
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Freescale Semiconductor
90
Package and Pin Listings
Table 71. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
MDQ41
MDQ42
MDQ43
MDQ44
MDQ45
MDQ46
MDQ47
MDQ48
MDQ49
MDQ50
MDQ51
MDQ52
MDQ53
MDQ54
MDQ55
MDQ56
MDQ57
MDQ58
MDQ59
MDQ60
MDQ61
MDQ62
MDQ63
MDQS0
MDQS1
MDQS2
MDQS3
MDQS4
MDQS5
MDQS6
MDQS7
MDQS8
MECC0/MSRCID0
AC4
AD4
AF1
AE4
AC5
AE2
AE3
AG1
AG2
AG3
AF5
AE5
AD7
AH2
AG4
AH3
AG5
AF8
AJ5
AF6
AF7
AH6
AH7
C8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
—
C4
E3
G2
AB5
AD1
AH1
AJ3
G1
J6
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
91
Package and Pin Listings
Signal
Table 71. TePBGA II Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
MECC1/MSRCID1
J3
K2
K3
J5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
6
MECC2/MSRCID2
MECC3/MSRCID3
MECC4/MSRCID4
MECC5/MDVAL
MECC6
J2
L5
MECC7
L2
MODT0
N5
U6
M6
P6
AA3
K4
W4
Y2
MODT1
O
6
MODT2
O
6
MODT3
O
6
MRAS_B
O
—
11
11
—
MVREF1
I
MVREF2
I
MWE_B
O
DUART Interface
UART_SIN1/MSRCID2/LSRCID2
UART_SOUT1/MSRCID0/LSRCID0
UART_CTS_B[1]/MSRCID4/LSRCID4
UART_RTS_B1
L28
L27
K26
N27
K27
I/O
O
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
I/O
O
UART_SIN2/MSRCID3/
LSRCID3
I/O
UART_SOUT2/MSRCID1/LSRCID1
UART_CTS_B[2]/MDVAL/LDVAL
UART_RTS_B[2]
K28
K29
L29
O
I/O
O
OVDD
OVDD
OVDD
—
—
—
Enhanced Local Bus Controller (eLBC) Interface
LAD0
LAD1
LAD2
LAD3
LAD4
LAD5
LAD6
E24
G28
H25
F26
C26
J28
I/O
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
—
—
—
—
—
—
—
I/O
I/O
I/O
I/O
I/O
I/O
F21
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Freescale Semiconductor
92
Package and Pin Listings
Table 71. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
LAD7
LAD8
F23
E25
E26
A23
F24
G24
F25
H28
G25
F27
B21
A25
C28
H24
E23
B28
D28
A27
C25
B27
H27
E21
F20
D29
E20
H26
C29
E28
B26
J25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LAD9
LAD10
LAD11
LAD12
LAD13
LAD14
LAD15
LA11/LAD16
LA12/LAD17
LA13/LAD18
LA14/LAD19
LA15/LAD20
LA16/LAD21
LA17/LAD22
LA18/LAD23
LA19/LAD24
LA20/LAD25
LA21/LAD26
LA22/LAD27
LA23/LAD28
LA24/LAD29
LA25/LAD30
LA26/LAD31
LA27
LA28
O
LA29
O
LA30
O
LA31
O
LA10/LALE
LBCTL
H29
A22
B22
O
O
LCLK0
O
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
93
Package and Pin Listings
Signal
Table 71. TePBGA II Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
LCLK1
LCLK2
C23
B23
D25
F19
C27
D24
C24
B29
E29
F29
D21
A26
F22
C21
J29
O
O
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LCS_B0
O
LCS_B1
O
LCS_B2
O
LCS_B3
O
LCS_B4/LDP0
LCS_B5/LDP1
LA7/LCS_B6/LDP2
LA8/LCS_B7/LDP3
LFCLE/LGPL0
LFALE/LGPL1
LFRE_B/LGPL2/LOE_B
LFWP_B/LGPL3
I/O
I/O
I/O
I/O
O
O
O
O
LGPL4/LFRB_B/LGTA_B/
LUPWAIT/LPBSE
I/O
LA9/LGPL5
G29
A21
D23
E22
B25
E27
F28
O
I
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
—
—
—
—
—
—
—
LSYNC_IN
LSYNC_OUT
O
O
O
O
O
LWE_B0/LFWE0/LBS_B0
LWE_B1/LFWE1/LBS_B1
LWE_B2/LFWE2/LBS_B2
LWE_B3/LFWE3/LBS_B3
eTSEC1/GPIO1/GPIO2/CFG_RESET Interface
TSEC1_COL/GPIO2[20]
TSEC1_CRS/GPIO2[21]
TSEC1_GTX_CLK
TSEC1_RX_CLK
AF22
AE20
AJ25
AG22
AD19
AD20
AD22
AE21
AE22
I/O
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
—
—
—
—
—
—
—
—
—
I/O
O
I
TSEC1_RX_DV
I
TSEC1_RX_ER/GPIO2[25]
TSEC1_RXD0
I/O
I
I
I
TSEC1_RXD1
TSEC1_RXD2
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
94
Freescale Semiconductor
Package and Pin Listings
Table 71. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
TSEC1_RXD3
TSEC1_TX_CLK
AD21
AJ22
AG23
AH22
AD23
I
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
—
—
—
—
—
I
TSEC1_TX_EN
O
TSEC1_TX_ER/CFG_LBMUX
I/O
I/O
TSEC1_TXD0/
CFG_RESET_SOURCE[0]
TSEC1_TXD1/
CFG_RESET_SOURCE[1]
AE23
AF23
AJ24
I/O
I/O
I/O
LVDD1
LVDD1
LVDD1
—
—
—
TSEC1_TXD2/
CFG_RESET_SOURCE[2]
TSEC1_TXD3/
CFG_RESET_SOURCE[3]
EC_GTX_CLK125
EC_MDC/CFG_CLKIN_DIV
EC_MDIO
AH24
AJ21
AH21
I
LVDD1
LVDD1
LVDD1
—
—
—
I/O
I/O
eTSEC2/GPIO1 Interface
TSEC2_COL/GPIO1[21]/
TSEC1_TMR_TRIG1
AJ27
I/O
I/O
LVDD2
LVDD2
—
—
TSEC2_CRS/GPIO1[22]/
TSEC1_TMR_TRIG2
AG29
TSEC2_GTX_CLK
AF28
AF25
O
I
LVDD2
LVDD2
—
—
TSEC2_RX_CLK/
TSEC1_TMR_CLK
TSEC2_RX_DV/GPIO1[23]
TSEC2_RX_ER/GPIO1[25]
TSEC2_RXD0/GPIO1[16]
TSEC2_RXD1/GPIO1[15]
TSEC2_RXD2/GPIO1[14]
TSEC2_RXD3/GPIO1[13]
AF26
AG25
AE28
AE29
AH26
AH25
AG28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LVDD2
LVDD2
LVDD2
LVDD2
LVDD2
LVDD2
LVDD2
—
—
—
—
—
—
—
TSEC2_TX_CLK/GPIO2[24]/
TSEC1_TMR_GCLK
TSEC2_TX_EN/GPIO1[12]/
TSEC1_TMR_ALARM2
AJ26
AG26
AH28
I/O
I/O
I/O
LVDD2
LVDD2
LVDD2
—
—
—
TSEC2_TX_ER/GPIO1[24]/
TSEC1_TMR_ALARM1
TSEC2_TXD0/GPIO1[20]
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
95
Package and Pin Listings
Signal
Table 71. TePBGA II Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
TSEC2_TXD1/GPIO1[19]/
AF27
I/O
I/O
I/O
LVDD2
—
TSEC1_TMR_PP1
TSEC2_TXD2/GPIO1[18]/
TSEC1_TMR_PP2
AJ28
AF29
LVDD2
LVDD2
—
—
TSEC2_TXD3/GPIO1[17]/
TSEC1_TMR_PP3
GPIO1 Interface
GPIO1[0]/GTM1_TIN1/
GTM2_TIN2/DREQ0_B
P25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
—
—
—
GPIO1[1]/GTM1_TGATE1_B/
GTM2_TGATE2_B/DACK0_B
N25
N26
B9
GPIO1[2]/GTM1_TOUT1_B/
DDONE0_B
GPIO1[3]/GTM1_TIN2/
GTM2_TIN1/DREQ1_B
GPIO1[4]/GTM1_TGATE2_B/
GTM2_TGATE1_B/DACK1_B
N29
M29
A9
GPIO1[5]/GTM1_TOUT2_B/
GTM2_TOUT1_B/DDONE1_B
GPIO1[6]/GTM1_TIN3/
GTM2_TIN4/DREQ2_B
GPIO1[7]/GTM1_TGATE3_B/
GTM2_TGATE4_B/DACK2_B
B10
J26
J24
J27
P24
GPIO1[8]/GTM1_TOUT3_B/
DDONE2_B
GPIO1[9]/GTM1_TIN4/
GTM2_TIN3/DREQ3_B
GPIO1[10]/GTM1_TGATE4_B/GTM2_T
GATE3_B/DACK3_B
GPIO1[11]/GTM1_TOUT4_B/
GTM2_TOUT3_B/DDONE3_B
USB/GPIO2 Interface
USBDR_CLK/GPIO2[23]
USBDR_DIR_DPPULLUP/GPIO2[9]
USBDR_NXT/GPIO2[8]
AJ11
AG12
AJ10
AF10
AE9
I/O
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
USBDR_PCTL0/GPIO2[11]/SD_DAT2
USBDR_PCTL1/GPIO2[22]/SD_DAT3
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
96
Package and Pin Listings
Table 71. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
USBDR_PWRFAULT/
GPIO2[10]/SD_DAT1
AG13
I/O
OVDD
—
USBDR_STP_SUSPEND
USBDR_D0_ENABLEN/GPIO2[0]
USBDR_D1_SER_TXD/GPIO2[1]
USBDR_D2_VMO_SE0/GPIO2[2]
USBDR_D3_SPEED/GPIO2[3]
USBDR_D4_DP/GPIO2[4]
AH12
AG10
AF13
AG11
AH11
AG9
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
12
—
—
—
—
—
—
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
USBDR_D5_DM/GPIO2[5]
AF9
USBDR_D6_SER_RCV/GPIO2[6]
USBDR_D7_DRVVBUS/GPIO2[7]
AH13
AH10
2
I C Interface
IIC1_SCL
IIC1_SDA
IIC2_SCL
IIC2_SDA
C12
B12
A10
A12
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
2
2
2
2
JTAG Interface
TCK
TDI
B13
E14
C13
A13
E11
I
I
OVDD
OVDD
OVDD
OVDD
OVDD
—
4
TDO
O
I
3
TMS
4
TRST_B
I
4
PCI Signals
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
P26
N28
P29
P27
R26
R29
T24
T25
R27
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
97
Package and Pin Listings
Signal
Table 71. TePBGA II Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
PCI_AD9
PCI_AD10
P28
U25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
PCI_AD11
R28
PCI_AD12
U26
PCI_AD13
U24
PCI_AD14
T29
PCI_AD15
V24
PCI_AD16
Y26
PCI_AD17
V28
PCI_AD18
AA25
AA26
W29
AA24
AA27
AC26
AB25
AB24
AA28
AA29
AC24
AC25
AB28
AE24
T26
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C_BE_B0
PCI_C_BE_B1
PCI_C_BE_B2
PCI_C_BE_B3
PCI_DEVSEL_B
PCI_FRAME_B
PCI_GNT_B0
PCI_GNT_B[1]/CPCI_HS_LED
PCI_GNT_B[2]/CPCI_HS_ENUM
PCI_GNT_B[3]/PCI_PME
T28
V29
Y29
U28
V27
—
—
—
—
—
AE27
AC28
AD27
AC27
O
O
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
98
Package and Pin Listings
Table 71. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
PCI_GNT_B[4]
PCI_IDSEL
AE25
W28
AD29
U29
O
I
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
5
PCI_INTA_B/IRQ_OUT_B
PCI_IRDY_B
O
2
I/O
I/O
I/O
I/O
I
5
PCI_PAR
V25
—
5
PCI_PERR_B
Y25
PCI_REQ_B0
AE26
AC29
AB29
AD26
W27
AD28
V26
—
—
—
—
—
—
5
PCI_REQ_B[1]/CPCI_HS_ES
PCI_REQ_B2
I
PCI_REQ_B3
I
PCI_REQ_B4
I
PCI_RESET_OUT_B
PCI_SERR_B
O
I/O
I/O
I/O
I
PCI_STOP_B
W26
Y24
5
PCI_TRDY_B
5
M66EN
AD15
—
Programmable Interrupt Controller (PIC) Interface
MCP_OUT_B
IRQ_B0/MCP_IN_B/GPIO2[12]
IRQ_B1/GPIO2[13]
AD14
F9
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
2
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
E9
IRQ_B2/GPIO2[14]
F10
D9
IRQ_B3/GPIO2[15]
IRQ_B4/GPIO2[16]
C9
IRQ_B5/GPIO2[17]/
USBDR_PWRFAULT
AE10
IRQ_B6/GPIO2[18]
IRQ_B7/GPIO2[19]
AD10
AD9
I/O
I/O
OVDD
OVDD
—
—
PMC Interface
D13
QUIESCE_B
O
OVDD
—
SerDes1 Interface
L1_SD_IMP_CAL_RX
L1_SD_IMP_CAL_TX
AJ14
I
I
L1_XPADVDD
L1_XPADVDD
—
—
AG19
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
99
Package and Pin Listings
Signal
Table 71. TePBGA II Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
L1_SD_REF_CLK
AJ17
AH17
AJ15
AH15
AJ19
AH19
AF15
AE15
AF18
AE18
AJ18
I
I
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
—
—
—
—
—
—
—
—
—
—
—
—
L1_SD_REF_CLK_B
L1_SD_RXA_N
L1_SD_RXA_P
L1_SD_RXE_N
L1_SD_RXE_P
L1_SD_TXA_N
L1_SD_TXA_P
L1_SD_TXE_N
L1_SD_TXE_P
L1_SDAVDD_0
I
I
I
I
O
O
O
O
SerDes
PLL Power
(1.0 or
1.05 V)
L1_SDAVSS_0
L1_XCOREVDD
AG17
SerDes
PLL GND
—
—
—
—
AH14, AJ16, AF17, AH20, AJ20
SerDes
Core Power
(1.0 or
1.05 V)
L1_XCOREVSS
L1_XPADVDD
AG14, AG15, AG16, AH16, AG18, AG20
SerDes
Core GND
—
—
—
—
AE16, AF16, AD18, AE19, AF19
SerDes I/O
Power (1.0
or 1.05 V)
L1_XPADVSS
AF14, AE17, AF20
SerDes I/O
GND
—
—
SerDes2 Interface
L2_SD_IMP_CAL_RX
L2_SD_IMP_CAL_TX
L2_SD_REF_CLK
L2_SD_REF_CLK_B
L2_SD_RXA_N
C19
C15
B17
A17
A19
B19
A15
B15
D18
I
I
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
—
—
—
—
—
—
—
—
—
I
I
I
L2_SD_RXA_P
I
L2_SD_RXE_N
I
L2_SD_RXE_P
I
L2_SD_TXA_N
O
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
100
Freescale Semiconductor
Package and Pin Listings
Table 71. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
L2_SD_TXA_P
L2_SD_TXE_N
L2_SD_TXE_P
L2_SDAVDD_0
E18
D15
E15
A16
O
O
O
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
—
—
—
—
—
SerDes
PLL Power
(1.0 or
1.05 V)
L2_SDAVSS_0
L2_XCOREVDD
C17
SerDes
PLL GND
—
—
—
—
A14, B14, D17, B18, B20
SerDes
Core Power
(1.0 or
1.05 V)
L2_XCOREVSS
L2_XPADVDD
C14, C16, A18, C18, A20, C20
D14, E16, F18, D19, E19
SerDes
Core GND
—
—
—
—
SerDes I/O
Power (1.0
or 1.05 V)
L2_XPADVSS
D16, E17, D20
SerDes I/O
GND
—
—
SPI Interface
SPICLK/SD_CLK
SPIMISO/SD_DAT0
SPIMOSI/SD_CMD
SPISEL_B/SD_CD
AH9
AD11
AJ9
I/O
I/O
I/O
I
OVDD
OVDD
OVDD
OVDD
—
—
—
—
AE11
System Control Interface
SRESET_B
HRESET_B
PORESET_B
AD12
AE12
AE14
I/O
I/O
I
OVDD
OVDD
OVDD
2
1
—
Test Interface
E10
TEST
I
I
OVDD
—
10
13
Thermal Management
F15
Reserved
Power Supply Signals
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
101
Package and Pin Listings
Table 71. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
LVDD1
AC21, AG21, AH23
Power for
eTSEC 1
I/O (2.5 V,
3.3 V)
LVDD1
—
LVDD2
LBVDD
VDD
AG24, AH27, AH29
Power for
eTSEC 2
I/O (2.5 V,
3.3 V)
LVDD2
LBVDD
VDD
—
—
—
G20, D22, A24, G26, D27, A28
Power for
eLBC
(3.3, 2.5, or
1.8 V)
K10, L10, M10, N10, P10, R10, T10, U10, Power for
V10, W10, Y10, K11, R11, Y11, K12, Y12,
K13, Y13, K14, Y14, K15, L15, W15, Y15,
K16, Y16, K17, Y17, K18, Y18, K19, R19,
Y19, K20, L20, M20, N20, P20, R20, T20,
U20, V20, W20, Y20
Core
(1.0 V or
1.5 V)
GND
(VSS)
A1, AJ1, H2, N2, AA2, AD2, D3, R3, AF3,
A4, F4, J4, L4, V4, Y4, AB4, B5, E5, P5,
AH5, K6, T6, AA6, AD6, AG6, F7, J7, Y7,
AJ7, B8, AE8, AG8, G9, AC9, B11, D11,
F11, L11, M11, N11, P11, T11, U11, V11,
W11, L12, M12, N12, P12, R12, T12,
U12, V12, W12, E12, E13, L13, M13, N13,
P13, R13, T13, U13, V13, W13, AE13,
AJ13, F14, L14, M14, N14, P14, R14,
T14, U14, V14, W14, M15, N15, P15,
R15, T15, U15, V15, L16, M16, N16, P16,
R16, T16, U16, V16, W16, L17, M17,
N17, P17, R17, T17, U17, V17, W17, L18,
M18, N18, P18, R18, T18, U18, V18,
W18, L19, M19, N19, P19, T19, U19, V19,
W19, AC20, G21, AF21, C22, J23, AA23,
AJ23, B24, W24, AF24, K25, R25, AD25,
D26, G27, M27, T27, Y27, AB27, AG27,
A29, AJ29
—
—
—
AVDD_C
AVDD_L
AVDD_P
AD13
Power for
e300 PLL
(1.0 or
—
—
—
—
—
—
1.05 V)
F13
Power for
eLBC PLL
(1.0 or
1.05 V)
F12
Power for
system PLL
(1.0 V)
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
102
Freescale Semiconductor
Package and Pin Listings
Table 71. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Notes
GVDD
A2, D2, R2, U2, AC2, AF2, AJ2, F3, H3,
L3, N3, Y3, AB3, B4, P4, AF4, AH4, C5,
Power for
DDR
GVDD
—
F5, K5, V5, AA5, AD5, N6, R6, AJ6, B7, SDRAMI/O
E7, K7, AA7, AE7, AG7, AD8
Voltage(2.5
or 1.8 V)
OVDD
AC10, D10, D12, AF12, AJ12, K23, Y23, PCI, USB,
R24, AD24, L25, W25, AB26, U27, M28, and other
OVDD
—
Y28, G10, A11, C11
Standard
(3.3 V)
No Connect
NC
F16, F17, AD16, AD17
Pull Down
—
—
—
—
8
7
Pull Down
B16, AH18
Note:
1
This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD.
This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD.
This output is actively driven during reset rather than being released to high impedance during reset.
These JTAG pins have weak internal pull-up P-FETs that are always enabled.
2
3
4
5
This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI Specification recommendation and see
AN3665, MPC837xE Design Checklist, for more details.
6
7
8
9
These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
This pin must always be tied to GND using a 0 Ω resistor.
This pin must always be left not connected.
For DDR2 operation, it is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR
power using an 18.2 Ω resistor.
10
11
12
13
This pin must always be tied low. If it is left floating it may cause the device to malfunction.
See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
This pin must not be pulled down during PORESET.
Open or tie to GND.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
103
Clocking
23 Clocking
Figure 64 shows the internal distribution of clocks within the MPC8377E.
e300 core
core_clk
Core PLL
csb_clk
to DDR
memory
controller
6
6
DDR
DDR
Memory
Device
MCK[0:5]
MCK[0:5]
Clock
Div
ddr_clk
lbiu_clk
/2
Clock
Unit
System PLL
/n
LCLK[0:2]
to local bus
memory
Local Bus
Memory
Device
LBIU
DLL
LSYNC_OUT
LSYNC_IN
controller
csb_clk to rest
of the device
PCI_CLK/
PCI_SYNC_IN
CFG_CLKIN_DIV
CLKIN
PCI_SYNC_OUT
PCI_CLK[0:4]
PCI Clock
Divider
5
Figure 64. MPC8377E Clock Subsystem
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI
host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the
multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICOEn]
parameters select whether CFG_CLKIN_DIV is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PCI agent device the CLKIN signal should be tied to GND.
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Freescale Semiconductor
Clocking
As shown in Figure 64, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)
which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,
Clocking, and Initialization,” in the MPC8379E Reference Manual for more information on the clock
subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWL[DDRCM])
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The internal lbiu_clk frequency is determined by the following equation:
lbiu_clk = csb_clk × (1 + RCWL[LBCM])
Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider
to create the external local bus clock outputs (LCLK[0:2]). The eLBC clock divider ratio is controlled by
LCCR[CLKDIV].
Some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk
frequency. Those units have a default clock ratio that can be configured by a memory mapped register after
the device comes out of reset. Table 72 specifies which units have a configurable clock frequency.
Table 72. Configurable Clock Units
Default
Frequency
Unit
Options
eTSEC1, eTSEC2
csb_clk/3
csb_clk/3
csb_clk/3
csb_clk/3
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
2
1
eSDHC and I C1
Security block
USB DR
PCI and DMA complex
PCI Express1, 2
SATA1, 2
csb_clk/3
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
1
2
2
This only applies to I C1 (I C2 clock is not configurable).
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105
Clocking
Table 73 provides the operating frequencies for the TePBGA II package under recommended operating
conditions (see Table 3).
Table 73. Operating Frequencies for TePBGA II
Minimum Operating
Frequency (MHz)
Maximum Operating
Frequency (MHz)
1
Parameter
e300 core frequency (core_clk)
333
133
125
167
—
800
400
200
333
133
400
66
Coherent system bus frequency (csb_clk)
2
DDR2 memory bus frequency (MCK)
2
DDR1 memory bus frequency (MCK)
3
Local bus frequency (LCLKn)
Local bus controller frequency (lbc_clk)
PCI input frequency (CLKIN or PCI_CLK)
eTSEC frequency
—
25
—
400
200
200
200
400
200
Security encryption controller frequency
USB controller frequency
—
—
eSDHC controller frequency
PCI Express controller frequency
SATA controller frequency
—
—
—
Note:
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk, MCK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core, USB modules,
SATA, and eSDHC will not exceed their respective value listed in this table.
The DDR data rate is 2× the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the csb_clk frequency (depending on RCWL[LBIUCM]).
2
3
23.1 System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. The system PLL VCO frequency depends
on RCWL[DDRCM] and RCWL[LBCM]. Table 74 shows the multiplication factor encodings for the
system PLL.
NOTE
If RCWL[DDRCM] and RCWL[LBCM] are both cleared, the system PLL
VCO frequency = (CSB frequency) × (System PLL VCO Divider).
If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL VCO
frequency = 2 × (CSB frequency) × (System PLL VCO Divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 400–800 MHz.
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Freescale Semiconductor
Clocking
Table 74. System PLL Multiplication Factors
RCWL[SPMF] System PLL Multiplication Factor
0000
0001
Reserved
Reserved
× 2
0010
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111–1111
× 7 to × 15
As described in Section 23, “Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 76
and Table 77 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 75.
Table 75. System PLL VCO Divider
RCWL[SVCOD]
VCO Division Factor
00
01
10
11
4
8
2
1
Table 76. CSB Frequency Options for Host Mode
Input Clock Frequency (MHz)
2
csb_clk :
CFG_CLKIN_DIV
SPMF
Input Clock
25
33.33
66.67
—
1
at Reset
2
Ratio
csb_clk Frequency (MHz)
High
High
High
High
0010
0011
0100
0101
2 : 1
3 : 1
4 : 1
5 : 1
133
—
100
100
125
133
167
—
—
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107
Clocking
Table 76. CSB Frequency Options for Host Mode (continued)
2
Input Clock Frequency (MHz)
csb_clk :
CFG_CLKIN_DIV
SPMF
Input Clock
Ratio
25
33.33
66.67
1
at Reset
2
csb_clk Frequency (MHz)
—
High
High
High
High
High
High
High
High
High
High
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6 : 1
7 : 1
—
8 : 1
9 : 1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
1
2
CFG_CLKIN_DIV select the ratio between CLKIN and PCI_SYNC_OUT.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
Table 77. CSB Frequency Options for Agent Mode
Input Clock
2
Frequency (MHz)
csb_clk :
CFG_CLKIN_DIV
SPMF
Input Clock
Ratio
1
at reset
25
33.33
66.67
2
csb_clk Frequency (MHz)
—
Low
Low
Low
Low
0010
0011
0100
0101
2 : 1
3 : 1
4 : 1
5 : 1
133
—
100
—
133
—
—
125
—
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108
Clocking
Table 77. CSB Frequency Options for Agent Mode (continued)
Input Clock
2
Frequency (MHz)
csb_clk :
CFG_CLKIN_DIV
SPMF
Input Clock
1
at reset
25
33.33
66.67
—
2
Ratio
csb_clk Frequency (MHz)
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6 : 1
7 : 1
150
175
200
225
250
275
300
325
200
233
266
300
333
8 : 1
9 : 1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
1
2
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
23.2 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 78 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 78 should be considered as reserved.
NOTE
Core VCO frequency = core frequency × VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 800–1600 MHz.
Table 78. e300 Core PLL Configuration
RCWL[COREPLL]
1
core_clk : csb_clk Ratio
VCO Divider
0–1
nn
2–5
6
0000
0
PLL bypassed
(PLL off, csb_clk clocks
core directly)
PLL bypassed
(PLL off, csb_clk clocks
core directly)
11
00
01
10
nnnn
0001
0001
0001
n
0
0
0
n/a
1:1
1:1
1:1
n/a
2
4
8
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Freescale Semiconductor
109
Clocking
Table 78. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
1
core_clk : csb_clk Ratio
VCO Divider
0–1
2–5
6
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
0001
0001
0001
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0011
0011
0100
0100
0100
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1.5:1
1.5:1
1.5:1
2:1
2
4
8
2
4
8
2
4
8
2
4
8
2
4
8
2
4
8
2:1
2:1
2.5:1
2.5:1
2.5:1
3:1
3:1
3:1
3.5:1
3.5:1
3.5:1
4:1
4:1
4:1
Note:
1
Core VCO frequency = Core frequency × VCO divider. Note that VCO divider has to be
set properly so that the core VCO frequency is in the range of 800–1600 MHz.
23.3 Suggested PLL Configurations
Table 79 shows suggested PLL configurations for different input clocks (LBCM = 0).
Table 79. Example Clock Frequency Combinations
1
1
eLBC
e300 Core
Sys
VCO
DDRdata
rate
1
1
,3
Ref
LBCM DDRCM SVCOD SPMF
CSB
/2
/4
/8
× 1 × 1.5 × 2 × 2.5 × 3
1,
1,
4
2
25.0
25.0
33.3
33.3
0
0
0
0
1
1
1
1
2
2
2
2
5
6
5
4
500
600
667
533
125
150
167
133
250
62.5 31.3 15.6
—
—
—
—
—
—
—
—
—
—
—
375
6
300
333
267
75
37.5 18.8
41.6 20.8
375 450
6
83.3
333 416 500
333 400
66.7 33.3 16.7
—
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Freescale Semiconductor
110
Thermal
Table 79. Example Clock Frequency Combinations (continued)
1
1
eLBC
e300 Core
Sys
VCO
DDRdata
rate
1
1
,3
Ref
LBCM DDRCM SVCOD SPMF
CSB
/2
/4
/8
× 1 × 1.5 × 2 × 2.5 × 3
1,
1,
4
2
6
48.0
66.7
25.0
33.3
50.0
50.0
66.7
66.7
66.7
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
2
2
4
2
4
2
2
2
2
3
2
8
8
4
8
4
5
6
576
533
800
533
800
800
533
667
800
144
133
200
288
72
36
18
—
—
—
—
—
—
—
—
—
—
—
—
360 432
333 400
266
200
267
200
66.7 33.3 16.7
6
100
133
100
—
50
25
400 500 600
6
6
266.7
200
66.7 33.3
400 533 667 800
400 500 600
600 800
400 533 667 800
50
25
50
—
5
6
400
400
267
333
100
—
—
6
266.7
333
133
—
66.7 33.3
6
83.3
100
41.6 333 500 667
50 400 600 800
—
—
—
—
5
6
400
400
—
Note:
1
Values in MHz.
2
3
4
5
6
System PLL VCO range: 400–800 MHz.
CSB frequencies less than 133 MHz will not support Gigabit Ethernet rates.
Minimum data rate for DDR2 is 250 MHz and for DDR1 is 167 MHz.
Applies to DDR2 only.
Applies to eLBC PLL-enabled mode only.
24 Thermal
This section describes the thermal specifications of the MPC8377E.
24.1 Thermal Characteristics
Table 80 provides the package thermal characteristics for the 689 31 × 31mm TePBGA II package.
Table 80. Package Thermal Characteristics for TePBGA II
Parameter
Symbol
Value
Unit
Notes
Junction-to-ambient natural convection on single layer board (1s)
Junction-to-ambient natural convection on four layer board (2s2p)
Junction-to-ambient (at 200 ft/min) on single layer board (1s)
Junction-to-ambient (at 200 ft/min) on four layer board (2s2p)
Junction-to-board thermal
R
R
21
15
16
12
8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 2, 3
1, 3
1, 3
4
θJA
θJA
R
R
θJMA
θJMA
R
θJB
θJC
Junction-to-case thermal
R
6
5
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Freescale Semiconductor
111
Thermal
Table 80. Package Thermal Characteristics for TePBGA II (continued)
Parameter
Symbol
Value
Unit
Notes
Junction-to-package natural convection on top
ψ
6
°C/W
6
JT
Note:
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
3
4
Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5
6
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
24.2 Thermal Management Information
For the following sections, P = (V
× I ) + P where P is the power dissipation of the I/O drivers.
DD I/O I/O
D
DD
24.2.1 Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
× P )
D
J
A
θJA
where:
T = junction temperature (°C)
J
T = ambient temperature for the package (°C)
A
R
= junction to ambient thermal resistance (°C/W)
θJA
P = power dissipation in the package (W)
D
The junction to ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Generally, the value obtained on a single layer board is appropriate for
a tightly packed printed circuit board. The value obtained on the board with the internal planes is usually
appropriate if the board has low power dissipation and the components are well separated. Test cases have
demonstrated that errors of a factor of two (in the quantity T – T ) are possible.
J
A
24.2.2 Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
NOTE
The heat sink cannot be mounted on the package.
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112
Freescale Semiconductor
Thermal
The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter
(edge) of the package is approximately the same as the local air temperature near the device. Specifying
the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R
× P )
D
J
A
θJB
where:
T = ambient temperature for the package (°C)
A
R
= junction to board thermal resistance (°C/W) per JESD51-8
θJB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.
24.2.3 Experimental Determination of Junction Temperature
NOTE
The heat sink cannot be mounted on the package.
To determine the junction temperature of the device in the application after prototypes are available, use
the thermal characterization parameter (Ψ ) to determine the junction temperature and a measure of the
JT
temperature at the top center of the package case using the following equation:
T = T + (Ψ × P )
J
T
JT
D
where:
T = junction temperature (°C)
J
T = thermocouple temperature on top of package (°C)
T
Ψ
= junction to ambient thermal resistance (°C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type
T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
24.2.4 Heat Sinks and Junction-to-Case Thermal Resistance
For the power values the device is expected to operate at, it is anticipated that a heat sink will be required.
A preliminary estimate of heat sink performance can be obtained from the following first first-cut
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
113
Thermal
approach. The thermal resistance is expressed as the sum of a junction to case thermal resistance and a
case-to-ambient thermal resistance:
R
= R
+ R
θJC θCA
θJA
where:
R
= junction to ambient thermal resistance (°C/W)
= junction to case thermal resistance (°C/W)
= case to ambient thermal resistance (°C/W)
θJA
θJC
θCA
R
R
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
This first-cut approach overestimates the heat sink size required, since heat flow through the board is not
accounted for, which can be as much as one-third to one-half of the power generated in the package.
Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling through the package and board and
the convection cooling due to the air moving through the application. Simplified thermal models of the
packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in
the thermal resistance table. More detailed thermal models can be made available on request.
The thermal performance of devices with heat sinks has been simulated with a few commercially available
heat sinks. The heat sink choice is determined by the application environment (temperature, air flow,
adjacent component power dissipation) and the physical space available. Because of the wide variety of
application environments, a single standard heat sink applicable to all cannot be specified.
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114
Freescale Semiconductor
Thermal
Table 81 shows the heat sink thermal resistance for TePBGA II package with heat sinks, simulated in a
standard JEDEC environment, per JESD 51-6.
Table 81. Thermal Resistance with Heat Sink in Open Flow (TePBGA II)
Thermal Resistance
Heat Sink Assuming Thermal Grease
Air Flow
(°/W)
AAVID 30 × 30 × 9.4 mm Pin Fin
Natural Convection
0.5 m/s
13.1
10.6
9.3
8.2
7.5
11.1
8.5
7.7
7.2
6.8
11.3
9.0
7.8
7.0
6.5
9.7
7.7
6.8
6.4
6.1
1 m/s
2 m/s
4 m/s
AAVID 31 × 35 × 23 mm Pin Fin
AAVID 43× 41× 16.5mm Pin Fin
Wakefield, 53 × 53 × 25 mm Pin Fin
Natural Convection
0.5 m/s
1 m/s
2 m/s
4 m/s
Natural Convection
0.5 m/s
1 m/s
2 m/s
4 m/s
Natural Convection
0.5 m/s
1 m/s
2 m/s
4 m/s
Heat sink vendors include the following:
Aavid Thermalloy
www.aavidthermalloy.com
Alpha Novatech
www.alphanovatech.com
International Electronic Research Corporation (IERC)
www.ctscorp.com
Millennium Electronics (MEI)
www.mei-thermal.com
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Freescale Semiconductor
115
Thermal
Tyco Electronics
Chip Coolers™
www.chipcoolers.com
Wakefield Engineering
www.wakefield.com
Interface material vendors include the following:
Chomerics, Inc.
www.chomerics.com
Dow-Corning Corporation
Dow-Corning Electronic Materials
www.dowcorning.com
Shin-Etsu MicroSi, Inc.
www.microsi.com
The Bergquist Company
www.bergquistcompany.com
24.3 Heat Sink Attachment
The device requires the use of heat sinks. When heat sinks are attached, an interface material is required,
preferably thermal grease and a spring clip. The spring clip should connect to the printed circuit board,
either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces
that can lift the edge of the package or peel the package from the board. Such peeling forces reduce the
solder joint lifetime of the package. The recommended maximum compressive force on the top of the
package is 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces,
and its performance should be verified under the application requirements.
24.3.1 Experimental Determination of the Junction Temperature with a
Heat Sink
When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimize the size of the clearance to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
difficulties with this technique, many engineers measure the heat sink temperature and then back calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this
case temperature, the junction temperature is determined from the junction to case thermal resistance.
T = T + (R
× P )
D
J
C
θJC
where:
T = junction temperature (°C)
J
T = case temperature of the package (°C)
C
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System Design Information
R
= junction to case thermal resistance (°C/W)
θJC
P = power dissipation (W)
D
25 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8377E.
25.1 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The AV
DD
DD
level should always be equivalent to V , and preferably these voltages will be derived directly from V
DD
through a low frequency filter scheme.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 65, one to each of the five AV pins. By
DD
providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize
DD
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
DD
Figure 65 shows the PLL power supply filter circuit.
10 Ω
VDD
AVDD (or L2AVDD)
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 65. PLL Power Supply Filter Circuit
25.2 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the device system, and the device itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the device. These
decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
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117
System Design Information
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
25.3 Connection Recommendations
To ensure reliable operation, it is highly recommended that unused inputs be connected to an appropriate
signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused
active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins
of the device.
25.4 Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
2
push-pull single-ended driver type (open drain for I C).
To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
0
or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 66). The
DD
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals
P
OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each
DD
P
P
N
other in value. Then, Z = (R + R )/2.
0
P
N
OVDD
R
N
SW2
SW1
Pad
Data
R
P
OGND
Figure 66. Driver Impedance Measurement
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Ordering Information
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V = R
while driving logic 1 with an external precision differential termination resistor of value R . The
× I
. Second, the output voltage is measured
1
source
source
term
measured voltage is V = (1/(1/R + 1/R )) × I
. Solving for the output impedance gives R
=
2
1
2
source
source
R
× (V /V – 1). The drive current is then I
= V /R
.
term
1
2
source
1
source
Table 82 summarizes the signal impedance targets. The driver impedance are targeted at minimum V
,
DD
nominal OV , 105°C.
DD
Table 82. Impedance Characteristics
Local Bus, Ethernet,
PCI Signals
(not including PCI
output clocks)
PCI Output Clocks
(including
PCI_SYNC_OUT)
DUART, Control,
Configuration, Power
Management
Impedance
DDR DRAM Symbol
Unit
R
N
42 Target
42 Target
NA
25 Target
25 Target
NA
42 Target
42 Target
NA
20 Target
20 Target
NA
Z
Z
W
W
W
0
0
R
P
Differential
Z
DIFF
Note: Nominal supply voltages. See Table 2, T = 105°C.
j
25.5 Configuration Pin Muxing
The device provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration
pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is
disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections
to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should
minimize the disruption of signal quality or speed for output pins thus configured.
25.6 Pull-Up Resistor Requirements
The device requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
2
including I C pins, Ethernet Management MDIO pin and IPIC interrupt pins.
For more information on required pull-up resistors and the connections required for the JTAG interface,
see AN3665, “MPC837xE Design Checklist.”
26 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
Section 26.1, “Part Numbers Fully Addressed by This Document.”
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Ordering Information
26.1 Part Numbers Fully Addressed by This Document
Table 83 provides the Freescale part numbering nomenclature for the MPC8377E. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Freescale sales office. In addition to the processor frequency, the part numbering scheme also
includes an application modifier which may specify special application conditions. Each part number also
contains a revision code which refers to the die mask revision number.
Table 83. Part Numbering Nomenclature
MPC 8377
ZQ
AF
D
A
E
C
Product
Code Identifier
Part
Encryption
Acceleration
Temperature
Range
e300 core
Frequency
DDR
Data Rate
Revision
Level
2
Package
1
3, 4
MPC
8377
Blank = Not included Blank = 0°C (T ) to VR = Pb-free
AL = 667 MHz G = 400 MHz Contact local
a
E = included
125°C (T )
689 TePBGA II AJ = 533 MHz F = 333 MHz
Freescale
AG = 400 MHz D = 266 MHz sales office
AN = 800 MHz
j
C = –40°C (T ) to
a
125°C (T )
j
Note:
1
Contact local Freescale office on availability of parts with an extended temperature range.
See Section 22, “Package and Pin Listings,” for more information on the available package type.
2
3
Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
4
An 800 MHz device is not supported in extended temperature (–40 °C to 125 °C).
Table 84 lists the available core and DDR data rate frequency combinations.
Table 84. Available Parts (Core/DDR Data Rate)
MPC8377E
MPC8378E
MPC8379E
800 MHz/400 MHz
667 MHz/400 MHz
533 MHz/333 MHz
400 MHz/266 MHz
800 MHz/400 MHz
667 MHz/400 MHz
533 MHz/333 MHz
400 MHz/266 MHz
800 MHz/400 MHz
667 MHz/400 MHz
533 MHz/333 MHz
400 MHz/266 MHz
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Ordering Information
Table 85 shows the SVR and PVR settings by device.
Table 85. SVR and PVR Settings by Product Revision
SVR
PVR
Device
Package
Rev 1.0
Rev. 2.1
Rev. 1.0
Rev. 2.1
MPC8377
MPC8377E
MPC8378
MPC8378E
MPC8379
MPC8379E
0x80C7_0010
0x80C6_0010
0x80C5_0010
0x80C4_0010
0x80C3_0010
0x80C2_0010
0x80C7_0021
0x80C6_0021
0x80C5_0021
0x80C4_0021
0x80C3_0021
0x80C2_0021
TePBGA II
0x8086_1010
0x8086_1011
26.2 Part Marking
Parts are marked as in the example shown in Figure 67.
MPCnnnnetppaaar
core/platform MHZ
ATWLYYWW
CCCCC
*MMMMM
YWWLAZ
TePBGA II
Notes:
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
Figure 67. Freescale Part Marking for TePBGA II Devices
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121
Document Revision History
27 Document Revision History
Table 86 provides a revision history for this hardware specification.
Table 86. Document Revision History
Revision Date
Substantive Change(s)
2
10/2009 • In Table 3, “Recommended Operating Conditions,” added “Operating temperature range” values.
1
• In Table 5, “MPC8377E Power Dissipation ,” corrected maximal application for 800/400 MHz to 4.3 W.
1
• In Table 5, “MPC8377E Power Dissipation ,” added a column for “Typical Application at T = 65°C (W)”.
j
1
• In Table 5, “MPC8377E Power Dissipation ,” added a column for “Sleep Power at T = 65°C (W)”.
j
• In Table 10, removed overbar from CFG_CLKIN_DIV.
• In Table 16, “Current Draw Characteristics for MV
,” updated I
maximum value for both DDR1
MVREF
REF
and DDR2 to 600 and 400 μA, respectively. Also, updated Note 1 and added Note 2.
• In Table 19, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” column headings renamed to
“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.
• In Table 19, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” and Table 20, “DDR1 and
DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.
• In Table 28, “RMII Transmit AC Timing Specifications,” updated t
I to 2.0 ns.
RMTDX
• In Table 59, Gen 1i/1.5G Receiver AC Specifications,” and Table 61, Gen 2i/3G Receiver AC
Specifications,” corrected titles from “Transmitter” to “Receiver”.
• In Table 71, “TePBGA II Pinout Listing,” removed pin THERM0; it is now Reserved. Also added 1.05 V
to VDD pin.
• In Table 73, “Operating Frequencies for TePBGA II,” corrected “DDR2 memory bus frequency (MCK)”
range to 125–200.
• In Table 78, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.
• In Table 79, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .
• In Section 20.2, “SPI AC Timing Specifications,” corrected t
respectively.
and t
to t
and t
,
NIKHOX
NEKHOX
NIKHOV
NEKHOV
1
02/2009 • In Table 3, “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two
rows for SerDes. In addition, changed 666 to 667 MHz.
1
• In Table 5, “MPC8377E Power Dissipation ,” added Notes 4 and 5. In addition, changed 666 to 667
MHz.
• In Table 12, “DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V,” Table 20, “DDR1 and
DD
DDR2 SDRAM Output AC Timing Specifications,” and Table 71, “TePBGA II Pinout Listing,” added
footnote to references to MVREF, MDQ, and MDQS, referencing AN3665, MPC837xE Design Checklist.
• In Table 20, updated t
minimum value for 333 MHz to 2.40.
DDKHCX
• In Table 71, “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified
footnote 10 and added footnote 13.
• In Table 73, “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for core_clk.
• In Table 79, “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.
• Updated part numbering information in AF column in Table 83, “Part Numbering Nomenclature.” In
addition, modified extended temperature information in notes 1 and 4.
• In Table 84, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.
0
12/2008 Initial public release.
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Document Revision History
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Document Number: MPC8377EEC
Rev. 2
10/2009
相关型号：
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800MHz, MICROPROCESSOR, PBGA689, 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, TEBGAII-689
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