MPC8533CVTALGB [FREESCALE]
PowerQUICC™ III Integrated Processor Hardware Specifications; 的PowerQUICC ™III集成处理器硬件规格
| 型号： | MPC8533CVTALGB |
| 厂家： | 
Freescale |
| 描述： | PowerQUICC™ III Integrated Processor Hardware Specifications |
| 文件： | 总116页 (文件大小：1273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC8533EEC
Rev. 3, 11/2009
Freescale Semiconductor
Technical Data
MPC8533E PowerQUICC™ III
Integrated Processor
Hardware Specifications
Contents
1 MPC8533E Overview
This section provides a high-level overview of MPC8533E
features. Figure 1 shows the major functional units within
the device.
1. MPC8533E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 17
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8. Enhanced Three-Speed Ethernet (eTSEC),
1.1
Key Features
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9. Ethernet Management Interface Electrical
The following list provides an overview of the device feature
set:
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11. Programmable Interrupt Controller . . . . . . . . . . . . . 51
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
16. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 60
17. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 78
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
21. System Design Information . . . . . . . . . . . . . . . . . . 102
22. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 111
23. Document Revision History . . . . . . . . . . . . . . . . . . 114
•
High-performance 32-bit Book E–enhanced core
built on Power Architecture™ technology:
— 32-Kbyte L1 instruction cache and 32-Kbyte L1
data cache with parity protection. Caches can be
locked entirely or on a per-line basis, with
separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary
processing unit). Provides an extensive
instruction set for vector (64-bit) integer and
fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as
they are defined by the SPE APU.
© Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.
MPC8533E Overview
— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit GPRs.
— 36-bit real addressing
— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
for single-precision (32-bit) floating-point instructions.
— Memory management unit (MMU). Especially designed for embedded applications. Supports
4-Kbyte–4-Gbyte page sizes.
— Enhanced hardware and software debug support
— Performance monitor facility that is similar to, but separate from, the device performance
monitor
The e500 defines features that are not implemented on this device. It also generally defines some features
that this device implements more specifically. An understanding of these differences can be critical to
ensure proper operations.
•
256-Kbyte L2 cache/SRAM
— Flexible configuration
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
– 1, 2, or 4 ways can be configured for stashing only.
— Eight-way set-associative cache organization (32-byte cache lines)
— Supports locking entire cache or selected lines. Individual line locks are set and cleared through
Book E instructions or by externally mastered transactions.
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately.
— SRAM features include the following:
– I/O devices access SRAM regions by marking transactions as snoopable (global).
– Regions can reside at any aligned location in the memory map.
– Byte-accessible ECC is protected using read-modify-write transaction accesses for
smaller-than-cache-line accesses.
•
•
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 36-bit address space.
— Inbound and outbound ATMUs map to larger external address spaces.
– Three inbound windows plus a configuration window on PCI and PCI Express
– Four outbound windows plus default translation for PCI and PCI Express
DDR/DDR2 memory controller
— Programmable timing supporting DDR and DDR2 SDRAM
— 64-bit data interface
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
2
Freescale Semiconductor
MPC8533E Overview
— Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes
— DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports
— Full ECC support
— Page mode support
– Up to 16 simultaneous open pages for DDR
– Up to 32 simultaneous open pages for DDR2
— Contiguous or discontiguous memory mapping
— Sleep mode support for self-refresh SDRAM
— On-die termination support when using DDR2
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2)
Programmable interrupt controller (PIC)
•
— Programming model is compliant with the OpenPIC architecture.
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
— Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
— Four global high resolution timers/counters that can generate interrupts
— Supports a variety of other internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing.
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.
— Interrupt summary registers allow fast identification of interrupt source.
•
Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,
IKE, WTLS/WAP, SSL/TLS, and 3GPP
— Four crypto-channels, each supporting multi-command descriptor chains
– Dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— PKEU—public key execution unit
– RSA and Diffie-Hellman; programmable field size up to 2048 bits
– Elliptic curve cryptography with F m and F(p) modes and programmable field size up to
2
511 bits
— DEU—Data Encryption Standard execution unit
– DES, 3DES
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
3
MPC8533E Overview
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— AESU—Advanced Encryption Standard unit
– Implements the Rijndael symmetric key cipher
– ECB, CBC, CTR, and CCM modes
– 128-, 192-, and 256-bit key lengths
— AFEU—ARC four execution unit
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— MDEU—message digest execution unit
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— KEU—Kasumi execution unit
– Implements F8 algorithm for encryption and F9 algorithm for integrity checking
– Also supports A5/3 and GEA-3 algorithms
— RNG—random number generator
— XOR engine for parity checking in RAID storage applications
2
•
•
Dual I C controllers
— Two-wire interface
— Multiple master support
2
— Master or slave I C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
2
— Optionally loads configuration data from serial ROM at reset via the I C interface
— Can be used to initialize configuration registers and/or memory
2
— Supports extended I C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
•
•
— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
— Multiplexed 32-bit address and data bus operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.
— Two protocol engines available on a per chip select basis:
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
4
Freescale Semiconductor
MPC8533E Overview
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
— Parity support
— Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
Two enhanced three-speed Ethernet controllers (eTSECs)
— Three-speed support (10/100/1000 Mbps)
•
— Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, and
IEEE 802.3ab-compliant controllers
— Support for various Ethernet physical interfaces:
– 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, and RGMII.
– 10/100 Mbps full- and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII.
— Flexible configuration for multiple PHY interface configurations.
— TCP/IP acceleration and QoS features available
– IP v4 and IP v6 header recognition on receive
– IP v4 header checksum verification and generation
– TCP and UDP checksum verification and generation
– Per-packet configurable acceleration
– Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS
stacks, and ESP/AH IP-security headers
– Supported in all FIFO modes
— Quality of service support:
– Transmission from up to eight physical queues
– Reception to up to eight physical queues
— Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):
– IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
software-programmed PAUSE frame generation and recognition)
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and
IEEE Std 802.1™ virtual local area network (VLAN) tags and priority
— VLAN insertion and deletion
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
— Retransmission following a collision
— CRC generation and verification of inbound/outbound frames
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
— MAC address recognition:
– Exact match on primary and virtual 48-bit unicast addresses
– VRRP and HSRP support for seamless router fail-over
– Up to 16 exact-match MAC addresses supported
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
5
MPC8533E Overview
– Broadcast address (accept/reject)
– Hash table match on up to 512 multicast addresses
– Promiscuous mode
— Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet
programming models
— RMON statistics support
— 10-Kbyte internal transmit and 2-Kbyte receive FIFOs
— MII management interface for control and status
— Ability to force allocation of header information and buffer descriptors into L2 cache
OCeaN switch fabric
•
•
— Full crossbar packet switch
— Reorders packets from a source based on priorities
— Reorders packets to bypass blocked packets
— Implements starvation avoidance algorithms
— Supports packets with payloads of up to 256 bytes
Integrated DMA controller
— Four-channel controller
— All channels accessible by both the local and remote masters
— Extended DMA functions (advanced chaining and striding capability)
— Support for scatter and gather transfers
— Misaligned transfer capability
— Interrupt on completed segment, link, list, and error
— Supports transfers to or from any local memory or I/O port
— Selectable hardware-enforced coherency (snoop/no snoop)
— Ability to start and flow control each DMA channel from external 3-pin interface
— Ability to launch DMA from single write transaction
PCI controller
•
— PCI 2.2 compatible
— One 32-bit PCI port with support for speeds from 16 to 66 MHz
— Host and agent mode support
— 64-bit dual address cycle (DAC) support
— Supports PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses
— Supports posting of processor-to-PCI and PCI-to-memory writes
— PCI 3.3-V compatible
— Selectable hardware-enforced coherency
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
6
Freescale Semiconductor
MPC8533E Overview
•
Three PCI Express interfaces
— Two ×4 link width interfaces and one ×1 link width interface
— PCI Express 1.0a compatible
— Auto-detection of number of connected lanes
— Selectable operation as root complex or endpoint
— Both 32- and 64-bit addressing
— 256-byte maximum payload size
— Virtual channel 0 only
— Traffic class 0 only
— Full 64-bit decode with 32-bit wide windows
Power management
•
•
— Supports power saving modes: doze, nap, and sleep
— Employs dynamic power management, which automatically minimizes power consumption of
blocks when they are idle
System performance monitor
— Supports eight 32-bit counters that count the occurrence of selected events
— Ability to count up to 512 counter-specific events
— Supports 64 reference events that can be counted on any of the 8 counters
— Supports duration and quantity threshold counting
— Burstiness feature that permits counting of burst events with a programmable time between
bursts
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
System access port
•
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE Std 1149.1™-compliant, JTAG boundary scan
783 FC-PBGA package
•
•
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
7
Electrical Characteristics
MPC8533E
e500 Core
256-Kbyte
L2
Cache
32-Kbyte
32-Kbyte
D-Cache
XOR
Acceleration
I-Cache
64-Bit
e500
Coherency
Module
Local
Bus
Security
Acceleration
DDR/DDR2
SDRAM
OpenPIC
Controller
PCI
Express
x4/x2/x1
32-Bit
PCI
Performance
Monitor
Gigabit
Ethernet
DUART
2x I2C
PCI
Express
x1
PCI
Express
x4/x2/x1
DMA
Figure 1. MPC8533E Block Diagram
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8533E. This device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
1
Table 1. Absolute Maximum Ratings
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
PLL supply voltage
V
–0.3 to 1.1
–0.3 to 1.1
–0.3 to 1.1
–0.3 to 1.1
V
V
V
V
—
—
—
—
DD
AV
SV
XV
DD
DD
DD
Core power supply for SerDes transceivers
Pad power supply for SerDes transceivers
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
8
Electrical Characteristics
1
Table 1. Absolute Maximum Ratings (continued)
Characteristic Symbol Max Value
GV
Unit
Notes
DDR and DDR2 DRAM I/O voltage
–0.3 to 2.75
–0.3 to 1.98
V
—
DD
Three-speed Ethernet I/O, MII management voltage
LV (eTSEC1)
–0.3 to 3.63
–0.3 to 2.75
V
V
V
V
—
—
—
—
DD
TV (eTSEC3)
–0.3 to 3.63
–0.3 to 2.75
DD
2
PCI, DUART, system control and power management, I C, and
JTAG I/O voltage
OV
BV
–0.3 to 3.63
DD
DD
Local bus I/O voltage
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
Input voltage
DDR/DDR2 DRAM signals
DDR/DDR2 DRAM reference
Three-speed Ethernet signals
MV
–0.3 to (GV + 0.3)
V
V
V
2
2
2
IN
DD
MV
–0.3 to (GV + 0.3)
DD
REF
LV
–0.3 to (LV + 0.3)
DD
IN
TV
–0.3 to (TV + 0.3)
IN
DD
Local bus signals
BV
–0.3 to (BV + 0.3)
V
V
—
2
IN
DD
DUART, SYSCLK, system control and power
OV
–0.3 to (OV + 0.3)
DD
IN
IN
2
management, I C, and JTAG signals
PCI
OV
T
–0.3 to (OV + 0.3)
V
2
DD
Storage temperature range
–55 to 150
°C
—
STG
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause.
2. (M,L,O)V , and MV
may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
REF
IN
2.1.2
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for this device. Note that the values in Table 2 are
the recommended and tested operating conditions. Proper device operation outside these conditions is not
guaranteed.
Table 2. Recommended Operating Conditions
Recommended
Characteristic
Symbol
Unit
Notes
Value
Core supply voltage
PLL supply voltage
V
1.0 ± 50 mV
1.0 ± 50 mV
1.0 ± 50 mV
1.0 ± 50 mV
V
V
V
V
V
—
1
DD
AV
SV
XV
DD
DD
DD
Core power supply for SerDes transceivers
Pad power supply for SerDes transceivers
DDR and DDR2 DRAM I/O voltage
—
—
2
GV
2.5 V ± 125 mV
1.8 V ± 90 mV
DD
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
9
Electrical Characteristics
Table 2. Recommended Operating Conditions (continued)
Recommended
Value
Characteristic
Three-speed Ethernet I/O voltage
Symbol
LV
Unit
Notes
3.3 V ± 165 mV
2.5 V ± 125 mV
V
4
DD
(eTSEC1)
TV
(eTSEC3)
3.3 V ± 165 mV
2.5 V ± 125 mV
DD
2
PCI, DUART, PCI Express, system control and power management, I C,
and JTAG I/O voltage
OV
3.3 V ± 165 mV
V
V
3
5
DD
DD
Local bus I/O voltage
BV
3.3 V ± 165 mV
2.5 V ± 125 mV
1.8 V ± 90 mV
Input voltage
DDR and DDR2 DRAM signals
DDR and DDR2 DRAM reference
Three-speed Ethernet signals
MV
GND to GV
V
V
V
2
2
4
IN
DD
MV
GND to GV /2
DD
REF
LV
GND to LV
DD
IN
TV
GND to TV
IN
DD
Local bus signals
BV
GND to BV
V
V
5
3
IN
DD
PCI, Local bus, DUART, SYSCLK, system control
and power management, I C, and JTAG signals
OV
T
GND to OV
0 to 90
IN
DD
2
Junction temperature range
°C
—
j
Notes:
1. This voltage is the input to the filter discussed in Section 21.2, “PLL Power Supply Filtering,” and not necessarily the voltage
at the AV pin, which may be reduced from V by the filter.
DD
DD
2. Caution: MV must not exceed GV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
3. Caution: OV must not exceed OV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
4. Caution: T/LV must not exceed T/ LV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
5. Caution: BV must not exceed BV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
10
Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8533E.
B/G/L/OV + 20%
DD
B/G/L/OV + 5%
DD
B/G/L/OV
V
DD
IH
GND
GND – 0.3 V
V
IL
GND – 0.7 V
Not to Exceed 10%
1
of t
CLOCK
Notes:
1. t
refers to the clock period associated with the respective interface:
CLOCK
2
For I C and JTAG, t
For DDR, t
For eTSEC, t
For LBIU, t
references SYSCLK.
CLOCK
references MCLK.
CLOCK
CLOCK
references EC_GTX_CLK125.
references LCLK.
CLOCK
CLOCK
For PCI, t
references PCI_CLK or SYSCLK.
2. Please note that with the PCI overshoot allowed (as specified above), the device
does not fully comply with the maximum AC ratings and device protection
guideline outlined in Section 4.2.2.3 of the PCI 2.2 Local Bus Specifications.
Figure 2. Overshoot/Undershoot Voltage for GV /OV /LV /BV /TV
DD
DD
DD
DD
DD
The core voltage must always be provided at nominal 1.0 V (see Table 2 for actual recommended core
voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must
be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the
associated I/O supply voltage. OV and LV based receivers are simple CMOS I/O circuits and satisfy
DD
DD
appropriate LVCMOS type specifications. The DDR2 SDRAM interface uses a single-ended differential
receiver referenced the externally supplied MV
the SSTL2 electrical signaling standard.
signal (nominally set to GV /2) as is appropriate for
REF
DD
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
11
Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths.
Table 3. Output Drive Capability
Programmable
Output Impedance
Supply
Voltage
Driver Type
Notes
(Ω)
Local bus interface utilities signals
25
35
BV = 3.3 V
1
DD
BV = 2.5 V
DD
45 (default)
45 (default)
125
BV = 3.3 V
DD
BV = 2.5 V
DD
BV = 1.8 V
DD
PCI signals
25
42 (default)
20
OV = 3.3 V
2
DD
DDR signal
GV = 2.5 V
—
—
DD
DDR2 signal
16
GV = 1.8 V
DD
32 (half strength mode)
TSEC signals
42
42
LV = 2.5/3.3 V
—
—
—
DD
DUART, system control, JTAG
OV = 3.3 V
DD
2
I C
150
OV = 3.3 V
DD
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
2.2
Power Sequencing
The device requires its power rails to be applied in specific sequence in order to ensure proper device
operation. These requirements are as follows for power up:
1. V , AV _n, BV , LV , SV , OV , TV , XV
DD
DD
DD
DD
DD
DD
DD
DD
2. GV
DD
Note that all supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines
must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before
the voltage rails on the current step reach 10% of theirs.
In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is
no concern about any of the DDR signals being in an indeterminate state during power up, then the
sequencing for GV is not required.
DD
From a system standpoint, if any of the I/O power supplies ramp prior to the V core supply, the I/Os
DD
associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be
drawn by the device.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
12
Freescale Semiconductor
Power Characteristics
3 Power Characteristics
The estimated typical core power dissipation for the core complex bus (CCB) versus the core frequency
for this family of PowerQUICC III devices is shown in Table 4.
Table 4. MPC8533E Core Power Dissipation
Core Frequency
(MHz)
Platform
Frequency (MHz)
V
(V)
Junction
Temperature (°C)
Power
(W)
DD
Power Mode
Typical
Notes
667
333
400
400
533
1.0
65
90
2.6
3.75
5.85
2.9
4.0
6.0
3.6
4.4
6.2
3.9
5.0
6.5
1, 2
1, 3
1, 4
1, 2
1, 3
1, 4
1, 2
1, 3
1, 4
1, 2
1, 3
1, 4
Thermal
Maximum
Typical
800
1.0
1.0
1.0
65
90
Thermal
Maximum
Typical
1000
1067
65
90
Thermal
Maximum
Typical
65
90
Thermal
Maximum
Notes:
1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and
configurations. The values do not include power dissipation for I/O supplies.
2. Typical power is an average value measured at the nominal recommended core voltage (V ) and 65°C junction temperature
DD
(see Table 2) while running the Dhrystone 2.1 benchmark.
3. Thermal power is the average power measured at nominal core voltage (V ) and maximum operating junction temperature
DD
(see Table 2) while running the Dhrystone 2.1 benchmark.
4. Maximum power is the maximum power measured at nominal core voltage (V ) and maximum operating junction
DD
temperature (see Table 2) while running a smoke test which includes an entirely L1-cache-resident, contrived sequence of
instructions which keep the execution unit maximally busy.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
13
Input Clocks
4 Input Clocks
4.1
System Clock Timing
Table 5 provides the system clock (SYSCLK) AC timing specifications for the MPC8533E.
Table 5. SYSCLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.
Parameter/Condition
SYSCLK frequency
Symbol
Min
Typical
Max
Unit
Notes
f
t
33
7.5
0.6
40
—
—
133
30.3
2.1
MHz
ns
1
—
2
SYSCLK
SYSCLK
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
t
, t
1.0
—
ns
KH KL
t
/t
60
%
—
3, 4
KHK SYSCLK
—
—
—
±150
ps
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio
settings.
2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
3. This represents the total input jitter—short- and long-term.
4. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
4.1.1
SYSCLK and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference
emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise
magnitude in order to meet industry and government requirements. These clock sources intentionally add
long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 5
considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter
should meet the MPC8533E input cycle-to-cycle jitter requirement. Frequency modulation and spread are
separate concerns, and the MPC8533E is compatible with spread spectrum sources if the recommendations
listed in Table 6 are observed.
Table 6. Spread Spectrum Clock Source Recommendations
At recommended operating conditions. See Table 2.
Parameter
Min
Max
Unit
Notes
Frequency modulation
Frequency spread
Note:
20
0
60
kHz
%
—
1
1.0
1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the
minimum and maximum specifications given in Table 5.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
14
Freescale Semiconductor
Input Clocks
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is
operated at its maximum rated e500 core frequency should avoid violating the stated limits by using
down-spreading only.
4.2
Real-Time Clock Timing
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then
used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter
specification. The minimum pulse width of the RTC signal should be greater than 2 × the period of the
CCB clock. That is, minimum clock high time is 2 × t
, and minimum clock low time is 2 × t
. There
CCB
CCB
is no minimum RTC frequency; RTC may be grounded if not needed.
4.3
eTSEC Gigabit Reference Clock Timing
Table 7 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for
the MPC8533E.
Table 7. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
EC_GTX_CLK125 frequency
Symbol
Min
Typ
Max
Unit
Notes
f
t
—
—
—
125
8
—
—
MHz
ns
—
—
1
G125
G125
EC_GTX_CLK125 cycle time
EC_GTX_CLK rise and fall time
t
/t
—
ns
G125R G125F
0.75
1.0
LV , TV = 2.5 V
DD
DD
LV , TV = 3.3 V
DD
DD
EC_GTX_CLK125 duty cycle
t
/t
—
%
2
G125H G125
45
47
55
53
GMII, TBI
1000Base-T for RGMII, RTBI
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TV = 2.5 V, and from 0.6 and 2.7 V for
DD
L/TVDD = 3.3 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 8.5.4, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T
reference clock.
4.4
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed.
For FIFO GMII mode:
FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 4.2
For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more
than 127 MHz.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
15
RESET Initialization
For FIFO encoded mode:
FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 3.2
For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more
than 167 MHz.
4.5
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,
see the specific section of this document.
5 RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8533E. Table 8 provides the RESET initialization AC timing specifications for the DDR
SDRAM component(s).
1
Table 8. RESET Initialization Timing Specifications
Parameter/Condition
Required assertion time of HREST
Min
Max
Unit
Notes
100
3
—
—
—
μs
SYSCLKs
μs
—
1
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET
negation
100
—
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
4
2
—
—
5
SYSCLKs
SYSCLKs
SYSCLKs
1
1
1
Input hold time for all POR configs (including PLL config) with
respect to negation of HRESET
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
—
Note:
1. SYSCLK is the primary clock input for the MPC8533E.
Table 9 provides the PLL lock times.
Table 9. PLL Lock Times
Min
Parameter/Condition
Core and platform PLL lock times
Max
Unit
Notes
—
—
—
100
50
μs
μs
μs
—
—
—
Local bus PLL
PCI bus lock time
50
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
16
DDR and DDR2 SDRAM
6 DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8533E. Note that DDR SDRAM is GV (typ) = 2.5 V and DDR2 SDRAM is GV (typ) = 1.8 V.
DD
DD
6.1
DDR SDRAM DC Electrical Characteristics
Table 10 provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8533E when GV (typ) = 1.8 V.
DD
Table 10. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V
DD
Max
Parameter/Condition
I/O supply voltage
Symbol
Min
Unit
Notes
GV
MV
1.71
1.89
V
V
1
2
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
MV
– 0.04
+ 0.26
MV
+ 0.04
REF
V
3
REF
REF
V
GV + 0.3
V
—
—
4
IH
DD
Input low voltage
V
I
–0.3
MV
– 0.24
REF
V
IL
Output leakage current
–50
–13.4
13.4
50
μA
mA
mA
OZ
OH
Output high current (V
= 1.26 V)
I
—
—
—
—
OUT
Output low current (V
= 0.33 V)
I
OL
OUT
Notes:
1. GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2. MV
is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver. Peak-to-peak
REF
DD DD
may not exceed ±2% of the DC value.
noise on MV
REF
3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
TT
equal to MV
. This rail should track variations in the DC level of MV
.
REF
REF
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
.
DD
Table 11 provides the DDR2 I/O capacitance when GV (typ) = 1.8 V.
DD
Table 11. DDR2 SDRAM Capacitance for GV (typ) = 1.8 V
DD
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
Delta input/output capacitance: DQ, DQS, DQS
Note:
C
6
8
pF
pF
1
1
IO
C
—
0.5
DIO
1. This parameter is sampled. GV = 1.8 V ± 0.090 V, f = 1 MHz, T = 25°C, V
= GV /2, V
(peak-to-peak) = 0.2 V.
DD
A
OUT
DD
OUT
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
17
DDR and DDR2 SDRAM
Table 12 provides the recommended operating conditions for the DDR SDRAM component(s) when
GV (typ) = 2.5 V.
DD
Table 12. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V
DD
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GV
MV
2.375
2.625
V
V
1
2
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
– 0.04
+ 0.31
MV
+ 0.04
REF
V
3
REF
REF
V
MV
GV + 0.3
V
—
—
4
IH
DD
Input low voltage
V
I
–0.3
MV
– 0.3
V
IL
REF
Output leakage current
–50
–16.2
16.2
50
μA
mA
mA
OZ
OH
Output high current (V
= 1.8 V)
I
—
—
—
—
OUT
Output low current (V
= 0.42 V)
I
OL
OUT
Notes:
1. GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2. MV
is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver. Peak-to-peak
REF
DD DD
may not exceed ±2% of the DC value.
noise on MV
REF
3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
TT
equal to MV
. This rail should track variations in the DC level of MV
.
REF
REF
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
.
DD
Table 13 provides the DDR I/O capacitance when GV (typ) = 2.5 V.
DD
Table 13. DDR SDRAM Capacitance for GV (typ) = 2.5 V
DD
Parameter/Condition
Input/output capacitance: DQ, DQS
Symbol
Min
Max
Unit
Notes
C
6
8
pF
pF
1
1
IO
Delta input/output capacitance: DQ, DQS
C
—
0.5
DIO
Note:
1. This parameter is sampled. GV = 2.5 V ± 0.125 V, f = 1 MHz, T = 25°C, V
= GV /2, V
(peak-to-peak) = 0.2 V.
DD
A
OUT
DD
OUT
Table 14 provides the current draw characteristics for MV
.
REF
Table 14. Current Draw Characteristics for MV
REF
Parameter/Condition
Current draw for MV
Symbol
Min
Max
Unit
Notes
I
—
500
μA
1
REF
MVREF
Note:
1. The voltage regulator for MV
must be able to supply up to 500 μA current.
REF
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
18
DDR and DDR2 SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 15 provides the input AC timing specifications for the DDR SDRAM when GV (typ) = 1.8 V.
DD
Table 15. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions.
Parameter
Symbol
Min
Max
– 0.25
REF
Unit
Notes
AC input low voltage
AC input high voltage
V
—
MV
V
V
—
—
IL
V
MV
+ 0.25
REF
—
IH
Table 16 provides the input AC timing specifications for the DDR SDRAM when GV (typ) = 2.5 V.
DD
Table 16. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions.
Parameter
Symbol
Min
Max
– 0.31
REF
Unit
Notes
AC input low voltage
AC input high voltage
V
—
MV
V
V
—
—
IL
V
MV
+ 0.31
REF
—
IH
Table 17 provides the input AC timing specifications for the DDR SDRAM interface.
Table 17. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions.
Parameter
Symbol
Min
Max
Unit
Notes
Controller skew for MDQS—MDQ/MECC/MDM
t
ps
1, 2
CISKEW
533 MHz
400 MHz
333 MHz
–300
–365
–390
300
365
390
3
—
—
Notes:
1. t
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
CISKEW
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
. This can be
DISKEW
determined by the following equation: t
= ± (T/4 – abs(t
)), where T is the clock period and abs(t
) is the
DISKEW
CISKEW
CISKEW
absolute value of t
. See Figure 3.
CISKEW
3. Maximum DDR1 frequency is 400 MHz.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
19
DDR and DDR2 SDRAM
Figure 3 shows the DDR SDRAM input timing diagram.
MCK[n]
MCK[n]
t
MCK
MDQS[n]
MDQ[x]
D0
D1
t
DISKEW
t
DISKEW
Figure 3. DDR SDRAM Input Timing Diagram (t
)
DISKEW
6.2.2
DDR SDRAM Output AC Timing Specifications
Table 18 provides the output AC timing specifications for the DDR SDRAM interface.
Table 18. DDR SDRAM Output AC Timing Specifications
At recommended operating conditions.
1
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n] cycle time, MCK[n]/MCK[n] crossing
ADDR/CMD output setup with respect to MCK
t
3.75
6
ns
ns
2
3
7
MCK
t
t
t
t
DDKHAS
DDKHAX
DDKHCS
DDKHCX
533 MHz
400 MHz
333 MHz
1.48
1.95
2.40
—
—
—
ADDR/CMD output hold with respect to MCK
ns
ns
ns
ns
3
533 MHz
400 MHz
333 MHz
1.48
1.95
2.40
—
—
—
7
—
—
MCS[n] output setup with respect to MCK
3
533 MHz
400 MHz
333 MHz
1.48
1.95
2.40
—
—
—
7
—
—
MCS[n] output hold with respect to MCK
3
533 MHz
400 MHz
333 MHz
1.48
1.95
2.40
—
—
—
7
—
—
MCK to MDQS Skew
t
–0.6
0.6
4
DDKHMH
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
20
DDR and DDR2 SDRAM
Table 18. DDR SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions.
1
Parameter
Symbol
Min
Max
Unit
Notes
MDQ/MECC/MDM output setup with respect
to MDQS
t
t
ps
5
DDKHDS,
DDKLDS
533 MHz
400 MHz
333 MHz
538
700
900
—
—
—
7
—
—
MDQ/MECC/MDM output hold with respect to
MDQS
t
t
ps
5
DDKHDX,
DDKLDX
533 MHz
400 MHz
333 MHz
538
700
900
—
—
—
7
—
—
MDQS preamble
MDQS postamble
Notes:
t
t
0.75 x tMCK
0.4 x tMCK
—
ns
ns
6
6
DDKHMP
0.6 x tMCK
DDKHME
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. Output hold time can be read as DDR timing
(first two letters of functional block)(reference)(state)(signal)(state)
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H) state until
t
DDKHAS
MCK
outputs (A) are setup (S) or output valid time. Also, t
symbolizes DDR timing (DD) for the time t
memory clock
DDKLDX
MCK
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t follows the symbol conventions described in note 1. For example, t describes the DDR timing
DDKHMH
DDKHMH
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
can be modified through
DDKHMH
control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock
adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been
set to the same adjustment value. See the MPC8533E PowerQUICC III Integrated Communications Processor Reference
Manual, for a description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
symbol conventions described in note 1.
follows the
DDKHMP
7. Maximum DDR1 frequency is 400 MHz.
NOTE
For the ADDR/CMD setup and hold specifications in Table 18, it is
assumed that the clock control register is set to adjust the memory clocks by
½ applied cycle.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
21
DDR and DDR2 SDRAM
Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t
).
DDKHMH
MCK[n]
MCK[n]
t
MCK
t
(max)
= 0.6 ns
DDKHMH
MDQS
MDQS
t
(min)
= –0.6 ns
DDKHMH
Figure 4. Timing Diagram for t
DDKHMH
Figure 5 shows the DDR SDRAM output timing diagram.
MCK
MCK
t
MCK
t
, t
DDKHAS DDKHCS
t
, t
DDKHAX DDKHCX
ADDR/CMD
Write A0
NOOP
t
DDKHMP
t
t
DDKHMH
MDQS[n]
MDQ[x]
t
DDKHME
DDKHDS
t
DDKLDS
D0
D1
t
DDKLDX
t
DDKHDX
Figure 5. DDR and DDR2 SDRAM Output Timing Diagram
Figure 6 provides the AC test load for the DDR bus.
GV /2
Output
Z = 50 Ω
0
DD
R = 50 Ω
L
Figure 6. DDR AC Test Load
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
22
DUART
7 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8533E.
7.1
DUART DC Electrical Characteristics
Table 19 provides the DC electrical characteristics for the DUART interface.
Table 19. DUART DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
Notes
V
2
–0.3
—
OV + 0.3
V
V
—
—
1
IH
DD
Low-level input voltage
V
I
0.8
±5
—
IL
Input current (V = 0 V or V = V
)
μA
V
IN
IN
DD
IN
High-level output voltage (OV = min, I = –2 mA)
V
OH
2.4
—
—
—
DD
OH
Low-level output voltage (OV = min, I = 2 mA)
V
OL
0.4
V
DD
OL
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
7.2
DUART AC Electrical Specifications
Table 20 provides the AC timing parameters for the DUART interface.
Table 20. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
Maximum baud rate
Oversample rate
Notes:
CCB clock/1,048,576
CCB clock/16
16
baud
baud
—
1
2
3
1. CCB clock refers to the platform clock.
2. Actual attainable baud rate will be limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each sixteenth sample.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
23
Enhanced Three-Speed Ethernet (eTSEC), MII Management
8 Enhanced Three-Speed Ethernet (eTSEC),
MII Management
This section provides the AC and DC electrical characteristics for enhanced three-speed and MII
management.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII/FIFO
Electrical Characteristics
The electrical characteristics specified here apply to all gigabit media independent interface (GMII), 8-bit
FIFO interface (FIFO), media independent interface (MII), ten-bit interface (TBI), reduced gigabit media
independent interface (RGMII), reduced ten-bit interface (RTBI), and reduced media independent
interface (RMII) signals except management data input/output (MDIO) and management data clock
(MDC). The 8-bit FIFO interface can operate at 3.3 or 2.5 V. The RGMII and RTBI interfaces are defined
for 2.5 V, while the MII, GMII, TBI, and RMII interfaces can be operated at 3.3 or 2.5 V. Whether the
GMII, MII, or TBI interface is operated at 3.3 or 2.5 V, the timing is compliant with IEEE 802.3. The
RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII)
Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII
Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in
Section 9, “Ethernet Management Interface Electrical Characteristics.”
8.2
eTSEC DC Electrical Characteristics
All GMII, MII, TBI, RGMII, RTBI, RMII, and FIFO drivers and receivers comply with the DC parametric
attributes specified in Table 21 and Table 22. The potential applied to the input of a GMII, MII, TBI, RTBI,
RMII, and FIFO receiver may exceed the potential of the receiver’s power supply (that is, a GMII driver
powered from a 3.6-V supply driving V into a GMII receiver powered from a 2.5-V supply). Tolerance
OH
for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The RGMII
and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 21. GMII, MII, TBI, RMII and FIFO DC Electrical Characteristics
Parameter
Symbol
LV
Min
Max
Unit
Notes
Supply voltage 3.3 V
3.135
3.465
V
1, 2
DD
TV
DD
Output high voltage (LV /TV = Min, I = –4.0 mA)
V
OH
2.4
—
—
0.5
—
V
V
—
—
DD
DD
OH
Output low voltage (LV /TV = Min, I = 4.0 mA)
V
OL
DD
DD
OL
Input high voltage
Input low voltage
V
1.95
—
V
—
IH
V
I
0.90
40
V
—
IL
Input high current (V = LV , V = TV
)
—
μA
1, 2, 3
IN
DD IN
DD
IH
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
24
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 21. GMII, MII, TBI, RMII and FIFO DC Electrical Characteristics (continued)
Parameter
Input low current (V = GND)
Symbol
Min
Max
Unit
Notes
I
–600
—
μA
3
IN
IL
Notes:
1. LV supports eTSEC1.
DD
2. TV supports eTSEC3.
DD
3. The symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2.
IN
IN
IN
Table 22. GMII, MII, RMII, RGMII, RTBI, TBI, and FIFO DC Electrical Characteristics
Parameters
Symbol
LV /TV
Min
Max
Unit
Notes
Supply voltage 2.5 V
Output high voltage (LV /TV = Min, I = –1.0 mA)
2.375
2.0
—
2.625
—
V
V
1, 2
—
DD
DD
V
OH
DD
DD
OH
Output low voltage (LV /TV = Min, I = 1.0 mA)
V
OL
0.4
—
V
—
DD
DD
OL
Input high voltage
Input low voltage
V
1.70
—
V
—
IH
V
I
0.7
±15
V
—
IL
Input current (V = 0, V = LV , V = TV
)
—
μA
1, 2, 3
IN
IN
DD IN
DD
IN
Notes:
1. LV supports eTSEC1.
DD
2. TV supports eTSEC3.
DD
3. The symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2.
IN
IN
IN
8.3
FIFO, GMII,MII, TBI, RGMII, RMII, and RTBI AC Timing
Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this
section.
8.3.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC FIFO modes is the double data rate RGMII and RTBI
specifications, since they have similar performance and are described in a source-synchronous fashion like
FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source-synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
25
Enhanced Three-Speed Ethernet (eTSEC), MII Management
A summary of the FIFO AC specifications appears in Table 23 and Table 24.
Table 23. FIFO Mode Transmit AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
TX_CLK, GTX_CLK clock period
TX_CLK, GTX_CLK duty cycle
TX_CLK, GTX_CLK peak-to-peak jitter
Rise time TX_CLK (20%–80%)
Fall time TX_CLK (80%–20%)
t
—
45
—
8.0
50
—
—
—
—
—
55
ns
%
—
—
—
—
—
1
FIT
t
FITH
t
250
0.75
0.75
3.0
ps
ns
ns
ns
FITJ
t
—
FITR
t
—
FITF
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN
hold time
t
0.5
FITDX
Note:
1. Data valid t
to GTX_CLK Min setup time is a function of clock period and max hold time.
FITDV
(Min setup = Cycle time – Max hold).
Table 24. FIFO Mode Receive AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Parameter/Condition Symbol
RX_CLK clock period
Min
Typ
Max
Unit
Notes
t
—
45
—
8.0
50
—
—
—
—
—
—
55
ns
%
—
—
—
—
—
—
—
FIR
RX_CLK duty cycle
t
/t
FIRH FIRH
RX_CLK peak-to-peak jitter
t
250
0.75
0.75
—
ps
ns
ns
ns
ns
FIRJ
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
t
—
FIRR
t
—
FIRF
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RX_CLK to RXD[7:0], RX_DV, RX_ER hold time
t
1.5
0.5
FIRDV
FIRDX
t
—
Timing diagrams for FIFO appear in Figure 7 and Figure 8.
t
t
FITR
t
FIT
FITF
GTX_CLK
t
FITH
t
t
FITDX
FITDV
TXD[7:0]
TX_EN
TX_ER
Figure 7. FIFO Transmit AC Timing Diagram
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
26
Enhanced Three-Speed Ethernet (eTSEC), MII Management
t
t
FIRR
FIR
RX_CLK
t
t
FIRF
FIRH
RXD[7:0]
RX_DV
RX_ER
Valid Data
t
t
FIRDV
FIRDX
Figure 8. FIFO Receive AC Timing Diagram
8.3.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.3.2.1
GMII Transmit AC Timing Specifications
Table 25 provides the GMII transmit AC timing specifications.
Table 25. GMII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
1
Parameter/Condition
GTX_CLK clock period
Symbol
Min
Typ
Max
Unit
Notes
t
—
0.2
—
8.0
—
—
—
—
ns
ns
ns
ns
—
2
GTX
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK data clock rise time (20%-80%)
GTX_CLK data clock fall time (80%-20%)
Notes:
t
5.0
1.0
1.0
GTKHDX
t
—
—
GTXR
t
—
GTXF
1. The symbols used for timing specifications follow the pattern t
for inputs
(first two letters of functional block)(signal)(state)(reference)(state)
and t
for outputs. For example, t
symbolizes GMII transmit timing
(first two letters of functional block)(reference)(state)(signal)(state)
GTKHDV
(GT) with respect to the t
clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching
GTX
the valid state (V) to state or setup time. Also, t
symbolizes GMII transmit timing (GT) with respect to the t
clock
GTKHDX
GTX
reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention
GTX
is used with the appropriate letter: R (rise) or F (fall).
2. Data valid t
Max delay).
to GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time –
GTKHDV
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
27
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 9 shows the GMII transmit AC timing diagram.
t
t
GTXR
GTX
GTX_CLK
t
t
GTXF
GTXH
TXD[7:0]
TX_EN
TX_ER
t
GTKHDX
t
GTKHDV
Figure 9. GMII Transmit AC Timing Diagram
8.3.2.2
GMII Receive AC Timing Specifications
Table 26 provides the GMII receive AC timing specifications.
Table 26. GMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
1
Parameter/Condition
RX_CLK clock period
Symbol
Min
Typ
Max
Unit
Notes
t
—
35
2.0
0.5
—
8.0
—
—
—
—
—
—
65
—
ns
%
—
—
—
—
—
—
GRX
RX_CLK duty cycle
t
/t
GRXH GRX
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RX_CLK to RXD[7:0], RX_DV, RX_ER hold time
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
t
ns
ns
ns
ns
GRDVKH
t
—
GRDXKH
t
1.0
1.0
GRXR
t
—
GRXF
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes GMII receive
(first two letters of functional block)(reference)(state)(signal)(state)
GRDVKH
timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t clock reference (K)
RX
going to the high state (H) or setup time. Also, t
input signals (D) went invalid (X) relative to the t
symbolizes GMII receive timing (GR) with respect to the time data
clock reference (K) going to the low (L) state or hold time. Note that, in
GRDXKL
GRX
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention
GRX
is used with the appropriate letter: R (rise) or F (fall).
Figure 10 provides the AC test load for eTSEC.
LV /2
Output
Z = 50 Ω
0
DD
R = 50 Ω
L
Figure 10. eTSEC AC Test Load
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
28
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 11 shows the GMII receive AC timing diagram.
t
t
GRXR
GRX
RX_CLK
t
t
GRXF
GRXH
RXD[7:0]
RX_DV
RX_ER
t
GRDXKH
t
GRDVKH
Figure 11. GMII Receive AC Timing Diagram
8.4
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.4.1
MII Transmit AC Timing Specifications
Table 27 provides the MII transmit AC timing specifications.
Table 27. MII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
1
Parameter/Condition
TX_CLK clock period 10 Mbps
Symbol
Min
Typ
Max
Unit
Notes
t
t
—
—
35
1
400
40
—
5
—
—
65
15
ns
ns
%
—
—
—
—
MTX
MTX
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
t
t
MTXH/ MTX
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN
delay
t
ns
MTKHDX
TX_CLK data clock rise (20%–80%)
TX_CLK data clock fall (80%–20%)
Note:
t
1.0
1.0
—
—
4.0
4.0
ns
ns
—
—
MTXR
t
MTXF
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes MII transmit
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
MTX
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
MTX
used with the appropriate letter: R (rise) or F (fall).
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
29
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 12 shows the MII transmit AC timing diagram.
t
t
MTXR
MTX
TX_CLK
t
t
MTXF
MTXH
TXD[3:0]
TX_EN
TX_ER
t
MTKHDX
Figure 12. MII Transmit AC Timing Diagram
8.4.2
MII Receive AC Timing Specifications
Table 28 provides the MII receive AC timing specifications.
Table 28. MII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.or 2.5 V ± 5%.
1
Parameter/Condition
RX_CLK clock period 10 Mbps
Symbol
Min
Typ
Max
Unit
Notes
t
—
—
400
40
—
—
—
ns
ns
%
—
—
—
—
—
—
—
MRX
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
t
MRX
t
/t
35
65
—
MRXH MRX
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
t
10.0
10.0
1.0
1.0
—
ns
ns
ns
ns
MRDVKH
t
—
—
MRDXKH
t
—
4.0
4.0
MRXR
t
—
MRXF
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes MII receive
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K)
MRX
going to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data input
MRDXKL
signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in general,
MRX
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
MRX
with the appropriate letter: R (rise) or F (fall).
Figure 13 provides the AC test load for eTSEC.
LV /2
Output
Z = 50 Ω
0
DD
R = 50 Ω
L
Figure 13. eTSEC AC Test Load
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
30
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 14 shows the MII receive AC timing diagram.
t
t
MRXR
MRX
RX_CLK
t
t
MRXH
MRXF
RXD[3:0]
RX_DV
RX_ER
Valid Data
t
MRDVKH
t
MRDXKL
Figure 14. MII Receive AC Timing Diagram
8.5
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.5.1
TBI Transmit AC Timing Specifications
Table 29 provides the TBI transmit AC timing specifications.
Table 29. TBI Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%..
1
Parameter/Condition
GTX_CLK clock period
Symbol
Min
Typ
Max
Unit
Notes
t
—
0.2
—
8.0
—
—
—
—
ns
ns
ns
ns
—
2
GTX
GTX_CLK to TCG[9:0] delay time
GTX_CLK rise (20%–80%)
GTX_CLK fall time (80%–20%)
Notes:
t
5.0
1.0
1.0
TTKHDX
t
—
—
TTXR
t
—
TTXF
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state )(reference)(state)
inputs and t
for outputs. For example, t
symbolizes the TBI
(first two letters of functional block)(reference)(state)(signal)(state)
TTKHDV
transmit timing (TT) with respect to the time from t
(K) going high (H) until the referenced data signals (D) reach the valid
TTX
state (V) or setup time. Also, t
symbolizes the TBI transmit timing (TT) with respect to the time from t
(K) going
TTKHDX
TTX
high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript
of t
represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate
TTX
letter: R (rise) or F (fall).
2. Data valid t
Max delay).
to GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time –
TTKHDV
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
31
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 15 shows the TBI transmit AC timing diagram.
t
t
TTX
TTXR
GTX_CLK
TCG[9:0]
t
TTXH
t
TTXF
t
TTKHDV
t
TTKHDX
Figure 15. TBI Transmit AC Timing Diagram
8.5.2
TBI Receive AC Timing Specifications
Table 30 provides the TBI receive AC timing specifications.
Table 30. TBI Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
PMA_RX_CLK[0:1] clock period
PMA_RX_CLK[0:1] skew
t
—
16.0
—
—
8.5
60
—
ns
ns
%
—
—
—
—
—
—
—
TRX
t
7.5
40
SKTRX
PMA_RX_CLK[0:1] duty cycle
t
/t
—
TRXH TRX
RCG[9:0] setup time to rising PMA_RX_CLK
PMA_RX_CLK to RCG[9:0] hold time
PMA_RX_CLK[0:1] clock rise time (20%-80%)
PMA_RX_CLK[0:1] clock fall time (80%-20%)
Note:
t
t
2.5
1.5
0.7
0.7
—
ns
ns
ns
ns
TRDVKH
TRDXKH
—
—
t
—
2.4
2.4
TRXR
t
—
TRXF
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes TBI receive
(first two letters of functional block)(reference)(state)(signal)(state)
TRDVKH
timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K)
TRX
going to the high (H) state or setup time. Also, t
symbolizes TBI receive timing (TR) with respect to the time data input
TRDXKH
signals (D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state. Note that, in general, the clock
TRX
reference symbol representation is based on three letters representing the clock of a particular functional. For example, the
subscript of t represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the
TRX
appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that
is being skewed (TRX).
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
32
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 16 shows the TBI receive AC timing diagram.
t
t
TRXR
TRX
PMA_RX_CLK1
t
t
TRXH
TRXF
RCG[9:0]
Valid Data
Valid Data
t
TRDVKH
t
t
SKTRX
TRDXKH
PMA_RX_CLK0
t
t
TRDXKH
TRXH
t
TRDVKH
Figure 16. TBI Receive AC Timing Diagram
8.5.3
TBI Single-Clock Mode AC Specifications
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant
eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1, a 125-MHz TBI receive clock
is supplied on the TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode,
whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied
on the TSEC_GTX_CLK125 pin in all TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in Table 31.
Table 31. TBI Single-Clock Mode Receive AC Timing Specification
Parameter/Condition
RX_CLK clock period
Symbol
Min
Typ
Max
Unit
Notes
t
7.5
40
—
8.0
50
—
—
—
—
—
8.5
60
ns
%
—
—
—
—
—
—
—
TRR
RX_CLK duty cycle
t
t
TRRH
RX_CLK peak-to-peak jitter
t
250
1.0
1.0
—
ps
ns
ns
ns
ns
TRRJ
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RCG[9:0] setup time to RX_CLK rising edge
RCG[9:0] hold time to RX_CLK rising edge
—
TRRR
t
—
TRRF
t
t
2.0
1.0
TRRDV
TRRDX
—
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
33
Enhanced Three-Speed Ethernet (eTSEC), MII Management
A timing diagram for TBI receive appears in Figure 17.
.
t
t
TRR
TRRR
RX_CLK
t
t
TRRF
TRRH
RCG[9:0]
Valid Data
t
t
TRRDX
TRRDV
Figure 17. TBI Single-Clock Mode Receive AC Timing Diagram
8.5.4
RGMII and RTBI AC Timing Specifications
Table 32 presents the RGMII and RTBI AC timing specifications.
Table 32. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with L/TVDD of 2.5 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock period duration
t
–500
1.0
7.2
40
0
—
8.0
50
—
—
500
2.8
ps
ns
ns
%
5
2
SKRGT_TX
t
SKRGT_RX
t
8.8
3
RGT
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
t
/t
60
3, 4
RGTH RGT
t
—
0.75
0.75
ns
ns
RGTR
Fall time (20%–80%)
t
—
RGTF
Notes:
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and
RTBI timing. For example, the subscript of t represents the TBI (T) receive (RX) clock. Note also that the notation for rise
RGT
(R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is
skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal.
3. For 10 and 100 Mbps, t
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
RGT
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three t
of the lowest speed
RGT
transitioned between.
5. Guaranteed by design.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
34
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 18 shows the RGMII and RTBI AC timing and multiplexing diagrams.
t
RGT
t
RGTH
GTX_CLK
(At Transmitter)
t
SKRGT_TX
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
t
SKRGT_RX
TX_CLK
(At PHY)
tRGT
t
RGTH
GTX_CLK
(At Receiver)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
t
SKRGT_TX
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
t
SKRGT_RX
RX_CLK
(At PHY)
Figure 18. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.5.5
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.5.5.1
RMII Transmit AC Timing Specifications
The RMII transmit AC timing specifications are in Table 33.
Table 33. RMII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.
1
Parameter/Condition
REF_CLK clock period
Symbol
Min
Typ
Max
Unit
Notes
t
15.0
35
20.0
50
25.0
65
ns
%
—
—
—
—
—
RMT
REF_CLK duty cycle
t
t
RMTH
REF_CLK peak-to-peak jitter
Rise time REF_CLK (20%–80%)
Fall time REF_CLK (80%–20%)
t
—
—
250
2.0
2.0
ps
ns
ns
RMTJ
RMTR
1.0
1.0
—
t
—
RMTF
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
35
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 33. RMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
REF_CLK to RMII data TXD[1:0], TX_EN delay
t
1.0
—
10.0
ns
—
RMTDX
Note:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes MII transmit
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
MTX
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
MTX
used with the appropriate letter: R (rise) or F (fall).
Figure 19 shows the RMII transmit AC timing diagram.
t
t
RMT
RMTR
REF_CLK
t
t
RMTF
RMTH
TXD[1:0]
TX_EN
TX_ER
t
RMTDX
Figure 19. RMII Transmit AC Timing Diagram
8.5.5.2
RMII Receive AC Timing Specifications
Table 34 shows the RMII receive AC timing specifications.
Table 34. RMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.or 2.5 V ± 5%.
1
Parameter/Condition
REF_CLK clock period
Symbol
Min
Typ
Max
Unit
Notes
t
15.0
35
20.0
50
—
25.0
65
ns
%
—
—
—
—
—
—
RMR
REF_CLK duty cycle
t
t
RMRH
REF_CLK peak-to-peak jitter
Rise time REF_CLK (20%–80%)
Fall time REF_CLK (80%–20%)
t
—
250
2.0
2.0
—
ps
ns
ns
ns
RMRJ
RMRR
1.0
1.0
4.0
—
t
—
RMRF
RXD[1:0], CRS_DV, RX_ER setup time to
REF_CLK rising edge
t
—
RMRDV
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
36
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 34. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.or 2.5 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
rising edge
t
2.0
—
—
ns
—
RMRDX
Note:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes MII receive
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K)
MRX
going to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data input
MRDXKL
signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in general,
MRX
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
MRX
with the appropriate letter: R (rise) or F (fall).
Figure 20 provides the AC test load for eTSEC.
LV /2
Output
Z = 50 Ω
0
DD
R = 50 Ω
L
Figure 20. eTSEC AC Test Load
Figure 21 shows the RMII receive AC timing diagram.
t
t
RMRR
RMR
REF_CLK
t
t
RMRH
RMRF
RXD[1:0]
CRS_DV
RX_ER
Valid Data
t
RMRDV
t
RMRDX
Figure 21. RMII Receive AC Timing Diagram
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
37
Ethernet Management Interface Electrical Characteristics
9 Ethernet Management Interface Electrical
Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
GMII, RGMII, RMII, TBI, and RTBI are specified in “Section 8, “Enhanced Three-Speed Ethernet
(eTSEC), MII Management.”
9.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics
for MDIO and MDC are provided in Table 35.
Table 35. MII Management DC Electrical Characteristics
Parameter
Symbol
OV
Min
Max
Unit
Notes
Supply voltage (3.3 V)
Output high voltage (OV = Min, I = –1.0 mA)
3.135
2.10
GND
1.95
—
3.465
3.60
0.50
—
V
V
—
—
—
—
—
1
DD
V
OH
DD
OH
Output low voltage (OV = Min, I = 1.0 mA)
V
OL
V
DD
OL
Input high voltage
Input low voltage
V
V
IH
V
I
0.90
40
V
IL
Input high current (OV = Max, V = 2.1 V)
—
μA
μA
DD
IN
IH
Input low current (OV = Max, V = 0.5 V)
I
IL
–600
—
—
DD
IN
Note:
1. The symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
9.2
MII Management AC Electrical Specifications
Table 36 provides the MII management AC timing specifications.
Table 36. MII Management AC Timing Specifications
At recommended operating conditions with OVDD is 3.3 V ± 5%.
1
Parameter/Condition
MDC frequency
Symbol
Min
Typ
Max
Unit
Notes
f
t
—
—
32
2.5
400
—
—
—
—
MHz
ns
2
—
MDC
MDC
MDC period
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
t
ns
—
MDCH
t
t
t
(16 × t
) – 3
—
(16 × t
) + 3
ns
3, 4
—
MDKHDX
MDDVKH
MDDXKH
plb_clk
plb_clk
5
—
—
ns
0
—
—
ns
—
t
—
—
10
ns
—
MDCR
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
38
Ethernet Management Interface Electrical Characteristics
Table 36. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
MDC fall time
Notes:
1. The symbols used for timing specifications follow the pattern of t
t
—
—
10
ns
—
MDHF
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes management
(first two letters of functional block)(reference)(state)(signal)(state)
MDKHDX
data timing (MD) for the time t
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
MDC
Also, t
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
MDDVKH
(V) relative to the t
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
MDC
convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of
the MgmtClk Clock EC_MDC).
3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods ±3 ns. For
example, with a platform clock of 333 MHz, the min/max delay is 48 ns ± 3 ns. Similarly, if the platform clock is 400 MHz, the
min/max delay is 40 ns ± 3 ns).
4. t
is the platform (CCB) clock.
plb_clk
Figure 22 shows the MII management AC timing diagram.
t
t
MDCR
MDC
MDC
t
t
MDCH
MDCF
MDIO
(Input)
t
MDDVKH
t
MDDXKH
MDIO
(Output)
t
MDKHDX
Figure 22. MII Management Interface Timing Diagram
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
39
Local Bus
10 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8533E.
10.1 Local Bus DC Electrical Characteristics
Table 37 provides the DC electrical characteristics for the local bus interface operating at
BV = 3.3 V DC.
DD
Table 37. Local Bus DC Electrical Characteristics (3.3 V DC)
Parameter
Symbol
Min
Max
Unit
Notes
High-level input voltage
V
2
–0.3
—
BV + 0.3
V
V
—
—
1
IH
DD
Low-level input voltage
V
I
0.8
±5
—
IL
Input current (BV = 0 V or BV = BOV
)
μA
V
IN
IN
DD
IN
High-level output voltage (BV = min, I = –2 mA)
V
OH
2.4
—
—
—
DD
OH
Low-level output voltage (BV = min, I = 2 mA)
V
OL
0.4
V
DD
OL
Note:
1. The symbol BV , in this case, represents the BV symbol referenced in Table 1 and Table 2.
IN
IN
Table 38 provides the DC electrical characteristics for the local bus interface operating at
BV = 2.5 V DC.
DD
Table 38. Local Bus DC Electrical Characteristics (2.5 V DC)
Parameter
Symbol
Min
Max
Unit
Notes
High-level input voltage
V
1.70
–0.3
—
BV + 0.3
V
V
—
—
1
IH
DD
Low-level input voltage
V
I
0.7
±15
—
IL
Input current (BV = 0 V or BV = BV
)
μA
V
IN
IN
DD
IN
High-level output voltage (BV = min, I = –1 mA)
V
OH
2.0
—
—
—
DD
OH
Low-level output voltage (BV = min, I = 1 mA)
V
OL
0.4
V
DD
OL
Note:
1. The symbol BV , in this case, represents the BV symbol referenced in Table 1 and Table 2.
IN
IN
Table 39 provides the DC electrical characteristics for the local bus interface operating at
BV = 1.8 V DC.
DD
Table 39. Local Bus DC Electrical Characteristics (1.8 V DC)
Parameter
Symbol
Min
Max
Unit
Notes
High-level input voltage
V
1.3
–0.3
—
BV + 0.3
V
V
—
—
1
IH
DD
Low-level input voltage
V
I
0.6
IL
Input current (BV = 0 V or BV = BV
)
±15
μA
IN
IN
DD
IN
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
40
Local Bus
Table 39. Local Bus DC Electrical Characteristics (1.8 V DC) (continued)
Parameter
Symbol
Min
Max
Unit
Notes
High-level output voltage
(BV = min, I = –2 mA)
V
1.35
—
V
—
OH
DD
OH
Low-level output voltage
(BV = min, I = 2 mA)
V
—
0.45
V
—
OL
DD
OL
10.2 Local Bus AC Electrical Specifications
Table 40 describes the general timing parameters of the local bus interface at BV = 3.3 V. For
DD
information about the frequency range of local bus see Section 19.1, “Clock Ranges.”
Table 40. Local Bus General Timing Parameters (BV
= 3.3 V)—PLL Enabled
DD
Min
7.5
1
Parameter
Symbol
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
t
12
57
150
—
ns
%
2
LBK
t
t
43
—
—
LBKH/ LBK
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
t
ps
ns
ns
ns
ns
ns
7, 8
3, 4
3, 4
3, 4
3, 4
6
LBKSKEW
t
t
t
t
2.5
1.85
1.0
1.0
1.5
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
—
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
—
—
LALE output transition to LAD/LDP output transition
(LATCH setup and hold time)
t
—
LBOTOT
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
t
—
—
2.9
2.8
2.7
2.7
—
ns
ns
ns
ns
ns
—
—
3
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
t
t
t
t
—
—
3
Output hold from local bus clock (except LAD/LDP and
LALE)
0.7
3
Output hold from local bus clock for LAD/LDP
t
0.7
—
—
ns
ns
3
5
LBKHOX2
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
t
2.5
LBKHOZ1
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
41
Local Bus
Table 40. Local Bus General Timing Parameters (BV
= 3.3 V)—PLL Enabled (continued)
DD
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus clock to output high impedance for LAD/LDP
t
—
2.5
ns
5
LBKHOZ2
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes local bus
(first two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one (1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to
LBKHOX
LBK
the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
DD
bypass mode to 0.4 × BV of the signal in question for 3.3-V signaling levels.
DD
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. t
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
is
LBOTOT
LBOTOT
programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BV /2.
DD
Table 41 describes the general timing parameters of the local bus interface at BV = 2.5 V.
DD
Table 41. Local Bus General Timing Parameters (BV
= 2.5 V)—PLL Enabled
DD
Min
7.5
1
Parameter
Symbol
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
t
12
57
150
—
ns
%
2
LBK
t
t
43
—
—
LBKH/ LBK
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
t
ps
ns
ns
ns
ns
ns
7
LBKSKEW
t
t
t
t
2.4
1.8
1.1
1.1
1.5
3, 4
3, 4
3, 4
3, 4
6
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
—
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
—
—
LALE output transition to LAD/LDP output transition
(LATCH setup and hold time)
t
—
LBOTOT
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
t
—
—
2.8
2.8
2.8
2.8
—
ns
ns
ns
ns
ns
—
3
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
t
t
t
t
—
3
—
3
Output hold from local bus clock (except LAD/LDP and
LALE)
0.8
3
Output hold from local bus clock for LAD/LDP
t
0.8
—
—
ns
ns
3
5
LBKHOX2
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
t
2.6
LBKHOZ1
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
42
Local Bus
Table 41. Local Bus General Timing Parameters (BV
= 2.5 V)—PLL Enabled (continued)
DD
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus clock to output high impedance for LAD/LDP
t
—
2.6
ns
5
LBKHOZ2
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes local bus
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case
clock reference (K) to go high (H), with respect
LBK
LBK
for clock one (1). Also, t
symbolizes local bus timing (LB) for the t
LBKHOX
to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
DD
bypass mode to 0.4 × BV of the signal in question for 2.5-V signaling levels.
DD
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. t
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
is
LBOTOT
LBOTOT
programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BV /2.
DD
Table 42 describes the general timing parameters of the local bus interface at BV = 1.8 V DC.
DD
Table 42. Local Bus General Timing Parameters (BV = 1.8 V DC)
DD
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
t
7.5
43
12
57
150
—
ns
%
2
LBK
t
t
—
LBKH/ LBK
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
t
—
ps
ns
ns
ns
ns
ns
7
LBKSKEW
t
t
t
t
2.6
1.9
1.1
1.1
1.2
3, 4
3, 4
3, 4
3, 4
6
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
—
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
—
—
LALE output transition to LAD/LDP output transition
(LATCH setup and hold time)
t
—
LBOTOT
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
t
—
—
3.2
3.2
3.2
3.2
—
ns
ns
ns
ns
ns
—
3
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
t
t
t
t
—
3
—
3
Output hold from local bus clock (except LAD/LDP and
LALE)
0.9
3
Output hold from local bus clock for LAD/LDP
t
0.9
—
—
ns
ns
3
5
LBKHOX2
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
t
2.6
LBKHOZ1
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
43
Local Bus
Table 42. Local Bus General Timing Parameters (BV = 1.8 V DC) (continued)
DD
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus clock to output high impedance for LAD/LDP
t
—
2.6
ns
5
LBKHOZ2
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes local bus
(first two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one (1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to
LBKHOX
LBK
the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
DD
bypass mode to 0.4 × BV of the signal in question for 1.8-V signaling levels.
DD
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. t
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
is
LBOTOT
LBOTOT
programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BV /2.
DD
Figure 23 provides the AC test load for the local bus.
BV /2
Output
Z = 50 Ω
0
DD
R = 50 Ω
L
Figure 23. Local Bus AC Test Load
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
44
Local Bus
Figure 24 through Figure 29 show the local bus signals.
LSYNC_IN
t
LBIXKH1
t
LBIVKH1
LBIVKH2
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIXKH2
t
Input Signal:
LGTA
LUPWAIT
t
LBKHOZ1
LBKHOX1
t
t
t
LBKHOV1
LBKHOV2
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
t
LBKHOZ2
LBKHOX2
t
t
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ2
LBKHOX2
t
LBKHOV3
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
t
LBKHOV4
LALE
Figure 24. Local Bus Signals (PLL Enabled)
Table 43 describes the general timing parameters of the local bus interface at V = 3.3 V DC with PLL
DD
disabled.
Table 43. Local Bus General Timing Parameters—PLL Bypassed
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus cycle time
Local bus duty cycle
t
12
—
57
4.9
—
—
—
—
—
ns
%
2
LBK
t
t
43
—
LBKH/ LBK
Internal launch/capture clock to LCLK delay
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
t
1.2
ns
ns
ns
ns
ns
ns
—
LBKHKT
t
7.4
4, 5
4, 5
4, 5
4, 5
6
LBIVKH1
t
6.75
–0.2
–0.2
1.5
LBIVKL2
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
t
LBIXKH1
t
LBIXKL2
LALE output transition to LAD/LDP output transition
(LATCH hold time)
t
LBOTOT
Local bus clock to output valid (except LAD/LDP and LALE)
t
—
1.6
ns
—
LBKLOV1
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
45
Local Bus
Table 43. Local Bus General Timing Parameters—PLL Bypassed (continued)
1
Parameter
Symbol
Min
Max
Unit
Notes
Local bus clock to data valid for LAD/LDP
t
t
t
—
—
1.6
1.6
—
ns
ns
ns
4
4
4
LBKLOV2
LBKLOV3
LBKLOX1
Local bus clock to address valid for LAD, and LALE
Output hold from local bus clock (except LAD/LDP and
LALE)
–4.1
Output hold from local bus clock for LAD/LDP
t
t
–4.1
—
—
ns
ns
4
7
LBKLOX2
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
1.4
LBKLOZ1
Local bus clock to output high impedance for LAD/LDP
t
—
1.4
ns
7
LBKLOZ2
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes local bus
(first two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case
clock reference (K) to go high (H), with respect
LBK
LBK
for clock one (1). Also, t
symbolizes local bus timing (LB) for the t
LBKHOX
to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which proceeds LCLK
by t
.
LBKHKT
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BV /2.
DD
4. All signals are measured from BV /2 of the rising edge of local bus clock for PLL bypass mode to 0.4 × BV of the signal
DD
DD
in question for 3.3-V signaling levels.
5. Input timings are measured at the pin.
6. The value of t
is the measurement of the minimum time between the negation of LALE and any change in LAD.
LBOTOT
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
46
Freescale Semiconductor
Local Bus
Internal Launch/Capture Clock
LCLK[n]
t
LBKHKT
t
LBIVKH1
t
LBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIVKL2
Input Signal:
LGTA
t
LBIXKL2
LUPWAIT
t
LBKLOV1
t
LBKLOZ1
LBKLOZ2
t
LBKLOX1
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
t
t
LBKLOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
t
LBKLOX2
LBKLOV3
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
LALE
Figure 25. Local Bus Signals (PLL Bypass Mode)
NOTE
In PLL bypass mode, LCLK[n] is the inverted version of the internal clock
with the delay of t . In this mode, signals are launched at the rising
LBKHKT
edge of the internal clock and are captured at falling edge of the internal
clock withe the exception of LGTA/LUPWAIT (which is captured on the
rising edge of the internal clock).
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
47
Local Bus
LSYNC_IN
T1
T3
t
t
LBKHOZ1
LBKHOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
GPCM Mode Input Signal:
LGTA
t
t
LBIVKH2
t
LBIXKH2
UPM Mode Input Signal:
LUPWAIT
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIXKH1
t
t
LBKHOV1
LBKHOZ1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Enabled)
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
48
Local Bus
Internal Launch/Capture Clock
T1
T3
LCLK
t
t
LBKLOX1
LBKLOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
LBKLOZ1
GPCM Mode Input Signal:
LGTA
t
LBIVKL2
t
LBIXKL2
UPM Mode Input Signal:
LUPWAIT
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIXKH1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode)
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
49
Local Bus
LSYNC_IN
T1
T2
T3
T4
t
t
LBKHOV1
LBKHOZ1
GPCM Mode Output Signals:
LCS[0:7]/LWE
GPCM Mode Input Signal:
LGTA
t
LBIVKH2
t
LBIXKH2
UPM Mode Input Signal:
LUPWAIT
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIXKH1
t
t
LBKHOV1
LBKHOZ1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Enabled)
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
50
Programmable Interrupt Controller
Internal Launch/Capture Clock
T1
T2
T3
T4
LCLK
t
t
LBKLOX1
LBKLOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
LBKLOZ1
GPCM Mode Input Signal:
LGTA
t
LBIVKL2
t
LBIXKL2
UPM Mode Input Signal:
LUPWAIT
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIXKH1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 29. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Bypass Mode)
11 Programmable Interrupt Controller
In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed
polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods).
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
51
JTAG
12 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8533E.
12.1 JTAG DC Electrical Characteristics
Table 44 provides the DC electrical characteristics for the JTAG interface.
Table 44. JTAG DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
Notes
V
2
–0.3
—
OV + 0.3
V
V
—
—
1
IH
DD
Low-level input voltage
V
I
0.8
±5
—
IL
Input current (OV = 0 V or OV = OV
)
μA
V
IN
IN
DD
IN
High-level output voltage (OV = min, I = –2 mA)
V
OH
2.4
—
—
—
DD
OH
Low-level output voltage (OV = min, I = 2 mA)
V
OL
0.4
V
DD
OL
Note:
1. Note that the symbol V , in this case, represents the OV .
IN
IN
12.2 JTAG AC Electrical Specifications
Table 45 provides the JTAG AC timing specifications as defined in Figure 30 through Figure 33.
1
Table 45. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions (see Table 3).
2
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
f
t
0
33.3
—
MHz
ns
—
—
—
—
3
JTG
30
15
0
JTG
t
—
ns
JTKHKL
t
& t
2
ns
JTGR
JTGF
t
25
—
ns
TRST
Input setup times:
ns
4
t
t
4
0
—
—
Boundary-scan data
JTDVKH
t
TMS, TDI
JTIVKH
Input hold times:
Valid times:
ns
ns
4
5
20
25
—
—
Boundary-scan data
TMS, TDI
JTDXKH
t
JTIXKH
t
t
4
4
20
25
Boundary-scan data
TDO
JTKLDV
JTKLOV
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
52
JTAG
1
Table 45. JTAG AC Timing Specifications (Independent of SYSCLK) (continued)
At recommended operating conditions (see Table 3).
2
Parameter
Symbol
Min
Max
Unit
Notes
Output hold times:
ns
5
t
t
4
4
—
—
Boundary-scan data
TDO
JTKLDX
JTKLOX
JTAG external clock to output high impedance:
Boundary-scan data
TDO
ns
5
t
t
3
3
19
9
JTKLDZ
JTKLOZ
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
to the midpoint of the signal in question.
TCLK
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 30).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes JTAG device
(first two letters of functional block)(reference)(state)(signal)(state)
JTDVKH
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
clock reference (K)
JTG
going to the high (H) state or setup time. Also, t
symbolizes JTAG timing (JT) with respect to the time data input signals
JTDXKH
(D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
JTG
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
.
TCLK
5. Non-JTAG signal output timing with respect to t
.
TCLK
Figure 30 provides the AC test load for TDO and the boundary-scan outputs.
OV /2
Output
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 30. AC Test Load for the JTAG Interface
Figure 31 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
t
VM
VM
t
JTGR
JTKHKL
t
t
JTGF
JTG
VM = Midpoint Voltage (OV /2)
DD
Figure 31. JTAG Clock Input Timing Diagram
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
53
I2C
Figure 32 provides the TRST timing diagram.
TRST
VM
VM
t
TRST
VM = Midpoint Voltage (OV /2)
DD
Figure 32. TRST Timing Diagram
Figure 33 provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
t
JTDVKH
t
JTDXKH
Boundary
Data Inputs
Input
Data Valid
t
JTKLDV
t
JTKLDX
Boundary
Data Outputs
Output Data Valid
t
JTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OV /2)
DD
Figure 33. Boundary-Scan Timing Diagram
13 I2C
2
This section describes the DC and AC electrical characteristics for the I C interfaces of the MPC8533E.
2
13.1 I C DC Electrical Characteristics
2
Table 46 provides the DC electrical characteristics for the I C interfaces.
2
Table 46. I C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
Input low voltage level
Low level output voltage
V
0.7 × OV
OV + 0.3
V
V
—
—
1
IH
DD
DD
V
–0.3
0
0.3 × OV
IL
DD
V
0.2 × OV
V
OL
DD
Pulse width of spikes which must be suppressed by the
input filter
t
0
50
ns
2
I2KHKL
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
54
I2C
2
Table 46. I C DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Input current each I/O pin (input voltage is between
I
–10
10
μA
3
I
0.1 × OV and 0.9 × OV (max)
DD
DD
Capacitance for each I/O pin
C
—
10
pF
—
I
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. Refer to the MPC8533E PowerQUICC III Integrated Communications Host Processor Reference Manual for information on
the digital filter used.
3. I/O pins will obstruct the SDA and SCL lines if OV is switched off.
DD
2
13.2 I C AC Electrical Specifications
2
Table 47 provides the AC timing parameters for the I C interfaces.
2
Table 47. I C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 46).
1
Parameter
Symbol
Min
Max
Unit
Notes
SCL clock frequency
f
0
400
—
kHz
μs
—
—
—
—
—
I2C
Low period of the SCL clock
t
t
1.3
0.6
0.6
0.6
I2CL
High period of the SCL clock
—
μs
I2CH
Setup time for a repeated START condition
t
—
μs
I2SVKH
Hold time (repeated) START condition (after this period,
the first clock pulse is generated)
t
—
μs
I2SXKL
Data setup time
t
100
—
ns
—
2
I2DVKH
Data hold time:
t
μs
I2DXKL
I2OVKL
—
0
—
—
CBUS compatible masters
2
I C bus devices
Data output delay time
t
—
0.6
0.9
—
3
—
4
Set-up time for STOP condition
t
μs
ns
ns
μs
V
I2PVKH
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Bus free time between a STOP and START condition
t
20 + 0.1 C
20 + 0.1 C
1.3
300
300
—
I2CR
b
b
t
4
I2CF
t
—
—
I2KHDX
Noise margin at the LOW level for each connected device
(including hysteresis)
V
0.1 × OV
—
NL
DD
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
55
I2C
2
Table 47. I C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 46).
1
Parameter
Symbol
Min
Max
Unit
Notes
Noise margin at the HIGH level for each connected
device (including hysteresis)
V
0.2 × OV
—
V
—
NH
DD
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
2
inputs and t
for outputs. For example, t
symbolizes I C timing (I2)
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
with respect to the time data input signals (D) reach the valid state (V) relative to the t clock reference (K) going to the high
I2C
2
(H) state or setup time. Also, t
symbolizes I C timing (I2) for the time that the data with respect to the start condition
clock reference (K) going to the low (L) state or hold time. Also, t
I2SXKL
2
(S) went invalid (X) relative to the t
symbolizes I C
I2C
I2PVKH
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t clock
I2C
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. The MPC8533E provides a hold time of at least 300 ns for the SDA signal (referred to the V min of the SCL signal) to bridge
IH
the undefined region of the falling edge of SCL.
3. The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
I2CL
I2DXKL
4. C = capacitance of one bus line in pF.
B
2
Figure 34 provides the AC test load for the I C.
OV /2
Output
Z = 50 Ω
0
DD
R = 50 Ω
L
2
Figure 34. I C AC Test Load
2
Figure 35 shows the AC timing diagram for the I C bus.
SDA
SCL
t
t
t
t
I2CF
I2CF
I2DVKH
I2KHKL
t
t
t
I2CR
I2CL
I2SXKL
t
t
t
t
I2PVKH
I2SXKL
I2CH
I2SVKH
t
t
I2DXKL, I2OXKL
S
Sr
P
S
2
Figure 35. I C Bus AC Timing Diagram
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
56
GPIO
14 GPIO
This section describes the DC and AC electrical specifications for the GPIO interface of the MPC8533E.
14.1 GPIO DC Electrical Characteristics
Table 48 provides the DC electrical characteristics for the GPIO interface.
Table 48. GPIO DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
Notes
V
2
– 0.3
—
OV + 0.3
V
V
—
—
1
IH
DD
Low-level input voltage
V
I
0.8
±5
—
IL
Input current (V = 0 V or V = V
μA
V
IN
IN
DD)
IN
High-level output voltage (OV = mn, I
= –2 mA)
V
OH
2.4
—
—
—
DD
OH
Low-level output voltage (OV = min, I = 2 mA)
V
OL
0.4
V
DD
OL
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
14.2 GPIO AC Electrical Specifications
Table 49 provides the GPIO input and output AC timing specifications.
Table 49. GPIO Input AC Timing Specifications
Parameter
Symbol
Typ
Unit
Notes
GPIO inputs—minimum pulse width
Note:
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
t
20
ns
1
PIWID
external synchronous logic. GPIO inputs are required to be valid for at least t
ns to ensure proper operation.
PIWID
Figure 36 provides the AC test load for the GPIO.
OV /2
Output
Z = 50 Ω
0
DD
R = 50 Ω
L
Figure 36. GPIO AC Test Load
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
57
PCI
15 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8533E.
15.1 PCI DC Electrical Characteristics
Table 50 provides the DC electrical characteristics for the PCI interface.
1
Table 50. PCI DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
Notes
V
2
–0.3
—
OV + 0.3
V
V
—
—
2
IH
DD
Low-level input voltage
V
I
0.8
±5
—
IL
Input current (V = 0 V or V = V
)
μA
V
IN
IN
DD
IN
High-level output voltage (OV = min, I = –2mA)
V
OH
2.4
—
—
—
DD
OH
Low-level output voltage (OV = min, I = 2 mA)
V
OL
0.4
V
DD
OL
Notes:
1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications.
2. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
15.2 PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is
used as the PCI input clock. Table 51 provides the PCI AC timing specifications at 66 MHz.
Table 51. PCI AC Timing Specifications at 66 MHz
1
Parameter
Symbol
Min
Max
Unit
Notes
SYSCLK to output valid
t
t
t
—
2.0
7.4
—
ns
ns
2, 3
2
PCKHOV
PCKHOX
PCKHOZ
Output hold from SYSCLK
SYSCLK to output high impedance
Input setup to SYSCLK
—
14
—
ns
2, 4
2, 5
2, 5
6, 7
7
t
3.7
ns
PCIVKH
PCIXKH
PCRVRH
PCRHRX
Input hold from SYSCLK
t
0.5
—
ns
9
REQ64 to HRESET setup time
t
t
10 × t
—
clocks
ns
SYS
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Rise time (20%–80%)
0
50
—
t
10
0.6
clocks
ns
8
PCRHFV
t
2.1
—
PCICLK
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
58
PCI
Table 51. PCI AC Timing Specifications at 66 MHz (continued)
1
Parameter
Symbol
Min
Max
Unit
Notes
Fall time (20%–80%)
t
0.6
2.1
ns
—
PCICLK
Notes:
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state)(reference)(state)
inputs and t
for outputs. For example, t
symbolizes PCI timing
(first two letters of functional block)(reference)(state)(signal)(state)
PCIVKH
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, t
, reference (K)
SYS
going to the high (H) state or setup time. Also, t
symbolizes PCI timing (PC) with respect to the time hard reset (R)
PCRHFV
went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OV /2 of the rising edge of PCI_SYNC_IN to 0.4 × OV of the signal in question for
DD
DD
3.3-V PCI signaling levels.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The timing parameter t
indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
SYS
system clock period must be kept within the minimum and maximum defined ranges. For values see Section 19, “Clocking.”
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter t
Specifications.
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
PCRHFV
9. The reset assertion timing requirement for HRESET is 100 μs.
Figure 37 provides the AC test load for PCI.
OV /2
Output
Z = 1 KΩ
0
DD
R = 50 Ω
L
Figure 37. PCI AC Test Load
Figure 38 shows the PCI input AC timing conditions.
CLK
t
PCIVKH
t
PCIXKH
Input
Figure 38. PCI Input AC Timing Measurement Conditions
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59
High-Speed Serial Interfaces (HSSI)
Figure 39 shows the PCI output AC timing conditions.
CLK
t
PCKHOV
Output Delay
t
PCKHOZ
High-Impedance
Output
Figure 39. PCI Output AC Timing Measurement Condition
16 High-Speed Serial Interfaces (HSSI)
The MPC8533E features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial
interconnect applications.Both SerDes1 and SerDes2 can be used for PCI Express data transfers
application.This section describes the common portion of SerDes DC electrical specifications, which is the
DC requirement for SerDes Reference Clocks. The SerDes data lane’s transmitter and receiver reference
circuits are also shown.
16.1 Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 40 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for
description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a
receiver input (SDn_RX and SDn_RX). Each signal swings between A Volts and B Volts where A > B.
Using this waveform, the definitions are as follows. To simplify illustration, the following definitions
assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling
environment.
1. Single-Ended Swing
The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and
SDn_RX each have a peak-to-peak swing of A - B Volts. This is also referred as each signal wire’s
Single-Ended Swing.
2. Differential Output Voltage, V (or Differential Output Swing):
OD
The Differential Output Voltage (or Swing) of the transmitter, V , is defined as the difference of
OD
the two complimentary output voltages: V
or negative.
– V
The V value can be either positive
SDn_TX
SDn_TX. OD
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High-Speed Serial Interfaces (HSSI)
3. Differential Input Voltage, V (or Differential Input Swing):
ID
The Differential Input Voltage (or Swing) of the receiver, V , is defined as the difference of the
ID
two complimentary input voltages: V
negative.
– V
The V value can be either positive or
SDn_RX
SDn_RX. ID
4. Differential Peak Voltage, V
DIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal
is defined as Differential Peak Voltage, V = |A – B| Volts.
DIFFp
5. Differential Peak-to-Peak, V
DIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) Volts, the peak-to-peak value of the differential transmitter
output signal or the differential receiver input signal is defined as Differential Peak-to-Peak
Voltage, V
= 2*V
= 2 * |(A – B)| Volts, which is twice of differential swing in
DIFFp-p
DIFFp
amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage
can also be calculated as V
= 2*|V |.
TX-DIFFp-p
OD
6. Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for
example) from the non-inverting signal (SDn_TX, for example) within a differential pair. There is
only one signal trace curve in a differential waveform. The voltage represented in the differential
waveform is not referenced to ground. Refer to Figure 40 as an example for differential waveform.
7. Common Mode Voltage, V
cm
The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor
of a balanced interchange circuit and ground. In this example, for SerDes output, V
=
cm_out
V
+ V
= (A + B) / 2, which is the arithmetic mean of the two complimentary output
SDn_TX
SDn_TX
voltages within a differential pair. In a system, the common mode voltage may often differ from
one component’s output to the other’s input. Sometimes, it may be even different between the
receiver input and driver output circuits within the same component. It is also referred as the DC
offset in some occasions.
SDn_TX or
SDn_RX
A Volts
V
= (A + B) / 2
cm
SDn_TX or
SDn_RX
B Volts
Differential Swing, V or V = A – B
ID
OD
Differential Peak Voltage, V
= |A – B|
DIFFp
Differential Peak-Peak Voltage, V
= 2*V
(not shown)
DIFFp
DIFFpp
Figure 40. Differential Voltage Definitions for Transmitter or Receiver
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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High-Speed Serial Interfaces (HSSI)
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
OD
between 500 mV and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other
OD
phase. The peak differential voltage (V
is 1000 mV p-p.
) is 500 mV. The peak-to-peak differential voltage (V
)
DIFFp
DIFFp-p
16.2 SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for PCI Express1 PCI Express2. SD2_REF_CLK and SD2_REF_CLK for the PCI
Express3. The following sections describe the SerDes reference clock requirements and some application
information.
16.2.1 SerDes Reference Clock Receiver Characteristics
Figure 41 shows a receiver reference diagram of the SerDes reference clocks.
•
•
The supply voltage requirements for XV
are specified in Table 1 and Table 2.
DD_SRDS2
SerDes reference clock receiver reference circuit structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
shown in Figure 41. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
50-Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
differential mode and single-ended mode description below for further detailed requirements.
•
The maximum average current requirement that also determines the common mode voltage range:
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above
SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
a clock driver with output driven by its current source from 0mA to 16mA (0–0.8 V), such that
each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
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Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to
SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it
must be AC-coupled off-chip.
•
The input amplitude requirement
— This requirement is described in detail in the following sections.
50 Ω
SDn_REF_CLK
Input
Amp
SDn_REF_CLK
50 Ω
Figure 41. Receiver of SerDes Reference Clocks
16.2.2 DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8533E SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
•
Differential Mode
— The input amplitude of the differential clock must be between 400 and 1600 mV differential
peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of
the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV.
This requirement is the same for both external DC-coupled or AC-coupled connection.
— For external DC-coupled connection, as described in Section 16.2.1, “SerDes Reference
Clock Receiver Characteristics,” the maximum average current requirements sets the
requirement for average voltage (common mode voltage) to be between 100 and 400 mV.
Figure 42 shows the SerDes reference clock input requirement for DC-coupled connection
scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn). Figure 43 shows the SerDes reference clock
input requirement for AC-coupled connection scheme.
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Freescale Semiconductor
63
High-Speed Serial Interfaces (HSSI)
•
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude
(single-ended swing) must be between 400 and 800 mV peak-peak (from Vmin to Vmax) with
SDn_REF_CLK either left unconnected or tied to ground.
— The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 44 shows
the SerDes reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
AC-coupled externally. For the best noise performance, the reference of the clock could be DC
or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as
the clock input (SDn_REF_CLK) in use.
200 mV < Input Amplitude or Differential Peak < 800 mV
SDn_REF_CLK
Vmax < 800 mV
100 mV < Vcm < 400 mV
Vmin > 0 V
SDn_REF_CLK
Figure 42. Differential Reference Clock Input DC Requirements (External DC-Coupled)
200 mV < Input Amplitude or Differential Peak < 800 mV
SDn_REF_CLK
Vmax < Vcm + 400 mV
Vcm
Vmin > Vcm - 400 mV
SDn_REF_CLK
Figure 43. Differential Reference Clock Input DC Requirements (External AC-Coupled)
400 mV < SDn_REF_CLK Input Amplitude < 800 mV
SDn_REF_CLK
0 V
SDn_REF_CLK
Figure 44. Single-Ended Reference Clock Input DC Requirements
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Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
16.2.3 Interfacing With Other Differential Signaling Levels
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are HCSL
(high-speed current steering logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be
used but may need to be AC-coupled due to the limited common mode input range allowed (100 to
400 mV) for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock
driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to
AC-coupling.
NOTE
Figure 45 through Figure 48 are for conceptual reference only. Due to the
fact that clock driver chip's internal structure, output impedance and
termination requirements are different between various clock driver chip
manufacturers, it is very possible that the clock circuit reference designs
provided by clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the MPC8533E SerDes reference clock receiver requirement
provided in this document.
Figure 45 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with MPC8533E SerDes reference clock
input’s DC requirement.
MPC8533EMP
HCSL CLK Driver Chip
50 Ω
SDn_REF_CLK
CLK_Out
33 Ω
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
33 Ω
SDn_REF_CLK
CLK_Out
50 Ω
Clock driver vendor dependent
source termination resistor
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
Figure 45. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
65
High-Speed Serial Interfaces (HSSI)
Figure 46 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common mode voltage is higher than the MPC8533E SerDes reference clock
input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the
LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter
establishes its own common mode level without relying on the receiver or other external component.
MPC8533E
LVDS CLK Driver Chip
50 Ω
SDn_REF_CLK
10 nF
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
SDn_REF_CLK
CLK_Out
10 nF
50 Ω
Figure 46. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
Figure 47 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with
MPC8533E SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 47
assumes that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL
outputs prior to AC-coupling. Its value could be ranged from 140 to 240 Ω depending on clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8533E SerDes
reference clock’s differential input amplitude requirement (between 200 and 800 mV differential peak).
For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock
input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. Please
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
66
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a
particular clock driver chip.
MPC8533E
LVPECL CLK
Driver Chip
50 Ω
SDn_REF_CLK
CLK_Out
10nF
R2
SerDes Refer.
CLK Receiver
R1
R1
100 Ω differential PWB trace
10nF
Clock Driver
R2
SDn_REF_CLK
CLK_Out
50 Ω
Figure 47. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Figure 48 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with MPC8533E SerDes reference clock
input’s DC requirement.
MPC8533E
Single-Ended
CLK Driver Chip
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
SDn_REF_CLK
33 Ω
Clock Driver
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
SDn_REF_CLK
50 Ω
50
Ω
Figure 48. Single-Ended Connection (Reference Only)
16.2.4 AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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67
High-Speed Serial Interfaces (HSSI)
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 52 describes some AC parameters common to SGMII, and PCI Express protocols.
Table 52. SerDes Reference Clock Common AC Parameters
Parameter
Symbol
Min
Max
Unit
Notes
Rising Edge Rate
Falling Edge Rate
Rise Edge Rate
Fall Edge Rate
1.0
1.0
+200
—
4.0
4.0
—
V/ns
V/ns
mV
mV
%
2, 3
2, 3
2
Differential Input High Voltage
Differential Input Low Voltage
V
IH
V
–200
20
2
IL
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Rise-Fall Matching
—
1, 4
Notes:
1. Measurment taken from single ended waveform.
2. Measurment taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 49.
4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge
rate of SDn_REF_CLK should be compared to the fall edge rate of SDn_REF_CLK, the maximum allowed difference should
not exceed 20% of the slowest edge rate. See Figure 50.
Rise Edge Rage
Fall Edge Rate
V
= +200 mV
0.0 V
IH
V
= –200 mV
IL
SDn_REF_CLK
minus
SDn_REF_CLK
Figure 49. Differential Measurement Points for Rise and Fall Time
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
68
High-Speed Serial Interfaces (HSSI)
T
T
RISE
FALL
SDn_REF_CLK
SDn_REF_CLK
V
V
+ 100 mV
CROSS MEDIAN
V
V
CROSS MEDIAN
CROSS MEDIAN
– 100 mV
CROSS MEDIAN
SDn_REF_CLK
SDn_REF_CLK
Figure 50. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol
based on application usage. Refer to the following sections for detailed information:
•
Section 17.2, “AC Requirements for PCI Express SerDes Clocks”
16.2.4.1 Spread Spectrum Clock
SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to –0.5%
spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,
a source without significant unintended modulation should be used.
SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread
spectrum clock source.
16.3 SerDes Transmitter and Receiver Reference Circuits
Figure 51 shows the reference circuits for SerDes data lane’s transmitter and receiver.
SD1_TXn or
SD2_TXn
SD1_RXn or
SD2_RXn
50 Ω
50 Ω
50 Ω
50 Ω
Receiver
Transmitter
SD1_TXn or
SD2_TXn
SD1_RXn or
SD2_RXn
Figure 51. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in the section below (PCI Express) in this
document based on the application usage:
•
Section 17, “PCI Express”
Please note that external AC Coupling capacitor is required for the above serial transmission protocols
with the capacitor value defined in specification of each protocol section.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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PCI Express
17 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8533E.
17.1 DC Requirements for PCI Express SD_REF_CLK and
SD_REF_CLK
For more information, see Section 16.2, “SerDes Reference Clocks.”
17.2 AC Requirements for PCI Express SerDes Clocks
Table 53 provides the AC requirements for the PCI Express SerDes clocks.
Table 53. SD_REF_CLK and SD_REF_CLK AC Requirements
2
Symbol
Parameter Description
REFCLK cycle time
Min
Typ
Max
Units
Notes
t
—
—
10
—
—
ns
ps
1
REF
t
t
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles
100
—
REFCJ
Phase jitter. Deviation in edge location with respect to
mean edge location
–50
—
50
ps
—
REFPJ
Notes:
1. Typical based on PCI Express Specification 2.0.
2. Guaranteed by characterization.
17.3 Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
17.4 Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer please refer to the
PCI Express Base Specification. Rev. 1.0a.
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PCI Express
17.4.1 Differential Transmitter (TX) Output
Table 54 defines the specifications for the differential output at all transmitters (TXs). The parameters are
specified at the component pins.
Table 54. Differential Transmitter (TX) Output Specifications
Symbol
Parameter
Unit interval
Min
Nom
Max
Unit
Comments
UI
399.88
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not
account for Spread Spectrum Clock
dictated variations. See Note 1.
V
V
Differential peak-to-
peak output voltage
0.8
—
1.2
V
V
= 2*|V
– V
|.
TX-DIFFp-p
TX-DIFFp-p
TX-D+
TX-D–
See Note 2.
De- emphasized
differential output
voltage (ratio)
–3.0
–3.5
–4.0
dB
Ratio of the V
following bits after a transition divided by
the V of the first bit after a
of the second and
TX-DIFFp-p
TX-DE-RATIO
TX-DIFFp-p
transition. See Note 2.
T
T
Minimum TX eye width 0.70
—
—
—
UI
UI
The maximum transmitter jitter can be
TX-EYE
derived as T
= 1 – T
TX-MAX-JITTER
TX-EYE
= 0.3 UI. See Notes 2 and 3.
Maximum time
between the jitter
median and maximum
deviation from the
median.
—
0.15
Jitter is defined as the measurement
TX-EYE-MEDIAN-to-
variation of the crossing points (V
MAX-JITTER
TX-DIFFp-p
= 0 V) in relation to a recovered TX UI. A
recovered TX UI is calculated over 3500
consecutive unit intervals of sample data.
Jitter is measured using all edges of the
250 consecutive UI in the center of the
3500 UI used for calculating the TX UI. See
Notes 2 and 3.
T
, T
D+/D– TX output
rise/fall time
0.125
—
—
—
—
UI
See Notes 2 and 5.
TX-RISE TX-FALL
V
RMS AC peak
common mode output
voltage
20
mV
V
V
= RMS(|V
–
TX-CM-ACp
TX-CM-ACp
TXD+
)
|/2 – V
TXD–
TX-CM-DC
V
V
= DC
of |V
–
TX-CM-DC
(avg)
TX-D+
|/2
TX-D–
See Note 2.
V
Absolute delta of DC
commonmodevoltage
during LO and
0
—
100
mV |V
– V
TX-CM-DC (during LO) TX-CM-Idle-DC
TX-CM-DC-ACTIVE-
|<= 100 mV
IDLE-DELTA
(During Electrical Idle)
V
V
= DC
of |V
TX-D+
–
TX-CM-DC
(avg)
electrical idle
|/2 [LO]
TX-D–
V
V
= DC
|/2 [Electrical Idle]
of |V
–
TX-D+
TX-CM-Idle-DC
(avg)
TX-D–
See Note 2.
V
Absolute delta of DC
common mode
between D+ and D–
0
—
25
mV |V
– V
| <= 25 mV
TX-CM-DC-D–
TX-CM-DC-LINE-DELTA
TX-CM-DC-D+
TX-CM-DC-D+
TX-CM-DC-D–
V
V
= DC
= DC
of |V
of |V
|
TX-D+
(avg)
(avg)
|
TX-D–
See Note 2.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
71
PCI Express
Table 54. Differential Transmitter (TX) Output Specifications (continued)
Symbol
Parameter
Electrical idle
Min
Nom
Max
Unit
Comments
= |V
V
V
0
—
20
mV
V
– V
|
TX-IDLE-D–
TX-IDLE-DIFFp
TX-IDLE-DIFFp
TX-IDLE-D+
differentialpeakoutput
voltage
<= 20 mV
See Note 2.
Amount of voltage
change allowed during
receiver detection
—
—
600
mV The total amount of voltage change that a
transmitter can apply to sense whether a
low impedance receiver is present. See
Note 6.
TX-RCV-DETECT
V
TX DC common mode
voltage
0
—
—
—
3.6
90
—
V
The allowed DC common mode voltage
under any conditions. See Note 6.
TX-DC-CM
I
TX short circuit current
limit
—
50
mA The total current the transmitter can
provide when shorted to its ground.
TX-SHORT
T
T
Minimum time spent in
electrical idle
UI
UI
Minimum time a transmitter must be in
electrical idle utilized by the receiver to
start looking for an electrical idle exit after
successfully receiving an electrical idle
ordered set.
TX-IDLE-MIN
Maximum time to
transition to a valid
electrical idle after
sending an electrical
Idle ordered set
—
—
—
—
20
20
After sending an electrical idle ordered set,
the transmitter must meet all electrical idle
specifications within this time. This is
considered a debounce time for the
transmitter to meet electrical idle after
transitioning from LO.
TX-IDLE-SET-TO-IDLE
T
Maximum time to
transition to valid TX
specifications after
leaving an electrical
idle condition
UI
Maximum time to meet all TX
TX-IDLE-TO-DIFF-DATA
specifications when transitioning from
electrical idle to sending differential data.
This is considered a debounce time for the
TX to meet all TX specifications after
leaving electrical idle.
RL
Differential return loss
12
6
—
—
—
—
dB
dB
Ω
Measured over 50 MHz to 1.25 GHz. See
Note 4.
TX-DIFF
RL
Common mode return
loss
Measured over 50 MHz to 1.25 GHz. See
Note 4.
TX-CM
Z
Z
DC differential TX
impedance
80
40
—
75
100
—
120
—
TX DC differential mode low impedance.
TX-DIFF-DC
TX-DC
Transmitter DC
impedance
Ω
Required TX D+ as well as D– DC
Impedance during all states.
L
Lane-to-lane output
skew
—
500 +
2 UI
ps
nF
Static skew between any two transmitter
lanes within a single link.
TX-SKEW
C
AC coupling capacitor
—
200
All transmitters shall be AC coupled. The
AC coupling is required either within the
media or within the transmitting component
itself.
TX
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
72
PCI Express
Table 54. Differential Transmitter (TX) Output Specifications (continued)
Symbol
Parameter
Min
Nom
Max
Unit
Comments
T
Crosslink random
timeout
0
—
1
ms
This random timeout helps resolve
conflicts in crosslink configuration by
eventually resulting in only one
downstream and one upstream port. See
Note 7.
crosslink
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 54 and measured over
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 52.)
3. A T
= 0.70 UI provides for a total sum of deterministic and random jitter budget of T
= 0.30 UI for the
TX-EYE
TX-JITTER-MAX
transmitter collected over any 250 consecutive TX UIs. The T
median is less than half of the total
TX-EYE-MEDIAN-to-MAX-JITTER
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and
D– line (that is, as measured by a vector network analyzer with 50-Ω probes—see Figure 54.) Note that the series capacitors
C
is optional for the return loss measurement.
TX
5. Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 54 for both V
6. See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.
and V
.
TX-D–
TX-D+
7. See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
17.4.2 Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 52 is specified using the passive compliance/test measurement load (see
Figure 54) in place of any real PCI Express interconnect +RX component.
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ
in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level
of the de-emphasized bit will always be relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the
TX UI.
NOTE
It is recommended that the recovered TX UI is calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
73
PCI Express
V
= 0 mV
V
= 0 mV
TX-DIFF
RX-DIFF
(D+ D– Crossing Point)
(D+ D– Crossing Point)
[Transition Bit]
= 800 mV
V
TX-DIFFp-p-MIN
[De-Emphasized Bit]
566 mV (3 dB ) >= >= 505 mV (4 dB )
V
TX-DIFFp-p-MIN
0.07 UI = UI – 0.3 UI (J
)
TX-TOTAL-MAX
[Transition Bit]
= 800 mV
V
TX-DIFFp-p-MIN
Figure 52. Minimum Transmitter Timing and Voltage Output Compliance Specifications
17.4.3 Differential Receiver (RX) Input Specifications
Table 55 defines the specifications for the differential input at all receivers (RXs). The parameters are
specified at the component pins.
Table 55. Differential Receiver (RX) Input Specifications
Symbol
Parameter
Unit interval
Min
Nom
Max
Units
Comments
UI
399.88
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
V
Differential peak-to- 0.175
peak input voltage
—
—
1.200
—
V
V
= 2*|V
– V
|
RX-D–
RX-DIFFp-p
RX-DIFFp-p
RX-D+
See Note 2.
T
Minimum receiver
eye width
0.4
UI
The maximum interconnect media and
transmitter jitter that can be tolerated by the
RX-EYE
receiver can be derived as T
RX-MAX-JITTER
= 1 – T
= 0.6 UI.
RX-EYE
See Notes 2 and 3.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
74
PCI Express
Table 55. Differential Receiver (RX) Input Specifications (continued)
Symbol
Parameter
Min
Nom
Max
Units
Comments
T
Maximum time
between the jitter
median and
maximum deviation
from the median
—
—
0.3
UI
Jitter is defined as the measurement
variation of the crossing points (V
RX-EYE-MEDIAN-to-MAX
-JITTER
RX-DIFFp-p
= 0 V) in relation to a recovered TX UI. A
recovered TX UI is calculated over 3500
consecutive unit intervals of sample data.
Jitter is measured using all edges of the 250
consecutive UI in the center of the 3500 UI
used for calculating the TX UI. See Notes 2,
3, and 7.
V
AC peak common
mode input voltage
—
—
—
150
—
mV
dB
V
V
= |V
– V
|/2 –
RXD–
RX-CM-ACp
RX-CM-ACp
RX-CM-DC
RXD+
V
= DC
of |V
– V
|/2
RX-D–
RX-CM-DC
(avg)
RX-D+
See Note 2.
RL
Differential return
loss
15
Measured over 50 MHz to 1.25 GHz with the
D+ and D– lines biased at +300 and
–300 mV, respectively. See Note 4.
RX-DIFF
RX-CM
RL
Z
Common mode
return loss
6
—
100
50
—
120
60
dB
Ω
Measured over 50 MHz to 1.25 GHz with the
D+ and D– lines biased at 0 V. See Note 4.
DC differential input
impedance
80
40
RX DC differential mode impedance. See
Note 5.
RX-DIFF-DC
Z
Z
DC input impedance
Ω
Required RX D+ as well as D– DC
impedance (50 ± 20% tolerance).
See Notes 2 and 5.
RX-DC
Powered down DC
input impedance
200 k
65
—
—
—
Ω
Required RX D+ as well as D– DC
impedance when the receiver terminations
do not have power. See Note 6.
RX-HIGH-IMP-DC
V
Electrical idle detect
threshold
175
mV
V
= 2 × |V
– V
|
RX-D–
RX-IDLE-DET-DIFFp-p
RX-IDLE-DET-DIFFp-p
RX-D+
Measured at the package pins of the
receiver.
T
Unexpected
—
—
10
ms
An unexpected electrical idle (V
RX-DIFFp-p
RX-IDLE-DET-DIFF-
electrical idle enter
detect threshold
integration time
< V
) must be recognized
ENTERTIME
RX-IDLE-DET-DIFFp-p
no longer than T
signal an unexpected idle condition.
to
RX-IDLE-DET-DIFF-ENTERING
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
75
PCI Express
Table 55. Differential Receiver (RX) Input Specifications (continued)
Symbol
Parameter
Total skew
Min
Nom
Max
Units
Comments
L
—
—
20
ns
Skew across all lanes on a link. This includes
variation in the length of SKP ordered set (for
example, COM and one to five symbols) at
the RX as well as any delay differences
arising from the interconnect itself.
TX-SKEW
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 54 should be used
as the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 53). If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must
be used as a reference for the eye diagram.
3. A T
= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
RX-EYE
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
4. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to
300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The
reference impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured
by a vector network analyzer with 50-Ω probes, see Figure 54). Note that the series capacitors CTX is optional for the return
loss measurement.
5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5-ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
6. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the RX ground.
7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and
simulated data.
17.5 Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 53 is specified using the passive compliance/test measurement load (see
Figure 54) in place of any real PCI Express RX component.
In general, the minimum receiver eye diagram measured with the compliance/test measurement load (see
Figure 54) will be larger than the minimum receiver eye diagram measured over a range of systems at the
input receiver of any real PCI Express component. The degraded eye diagram at the input receiver is due
to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI Express
component to vary in impedance from the compliance/test measurement load. The input receiver eye
diagram is implementation specific and is not specified. RX component designer should provide additional
margin to adequately compensate for the degraded minimum receiver eye diagram (shown in Figure 53)
expected at the input receiver based on some adequate combination of system simulations and the return
loss measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using
the jitter median to locate the center of the eye diagram.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
76
Freescale Semiconductor
PCI Express
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the
TX UI.
NOTE
The reference impedance for return loss measurements is 50 Ω to ground for
both the D+ and D– line (that is, as measured by a vector network analyzer
with 50-Ω probes, see Figure 53). Note that the series capacitors, CTX, are
optional for the return loss measurement.
V
= 0 mV
V
= 0 mV
RX-DIFF
RX-DIFF
(D+ D– Crossing Point)
(D+ D– Crossing Point)
V
> 175 mV
RX-DIFFp-p-MIN
0.4 UI = T
RX-EYE-MIN
Figure 53. Minimum Receiver Eye Timing and Voltage Compliance Specification
17.5.1 Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test/measurement load shown in Figure 54.
NOTE
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary.
D+ Package
Pin
C = C
TX
TX
Silicon
+ Package
C = C
TX
D– Package
Pin
R = 50 Ω
R = 50 Ω
Figure 54. Compliance Test/Measurement Load
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
77
Package Description
18 Package Description
This section details package parameters, pin assignments, and dimensions.
18.1 Package Parameters for the MPC8533E FC-PBGA
The package parameters for flip chip plastic ball grid array (FC-PBGA) are provided in Table 56.
Table 56. Package Parameters
1
Parameter
Package outline
PBGA
29 mm × 29 mm
783
Interconnects
Ball pitch
1 mm
Ball diameter (typical)
Solder ball (Pb-free)
0.6 mm
96.5% Sn
3.5% Ag
Note:
1. (FC-PBGA) without a lid.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
78
Package Description
18.2 Mechanical Dimensions of the MPC8533E FC-PBGA
Figure 55 shows the mechanical dimensions and bottom surface nomenclature of the MPC8533E,
783 FC-PBGA package without a lid.
Notes:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Parallelism measurement shall exclude any effect of mark on top surface of package.
6. Capacitors may not be present on all parts. Care must be taken not to short exposed metal capacitor pads.
7. All dimensions are symmetric across the package center lines, unless dimensioned otherwise.
Figure 55. Mechanical Dimensions and Bottom Surface Nomenclature
of the MPC8533E FC-PBGA without a Lid
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
79
Package Description
18.3 Pinout Listings
NOTE
The naming convention of TSEC1 and TSEC3 is used to allow the splitting
voltage rails for the eTSEC blocks and to ease the port of existing
PowerQUICC III software.
NOTE
The DMA_DACK[0:1] and TEST_SEL pins must be set to a proper state
during POR configuration. Please refer to Table 57 for more details.
Table 57 provides the pinout listing for the MPC8533E 783 FC-PBGA package.
Table 57. MPC8533E Pinout Listing
Power
Supply
Signal
Package Pin Number
PCI
Pin Type
Notes
PCI1_AD[31:0]
AE8, AD8, AF8, AH12, AG12, AB9, AC9, AE9,
AD10, AE10, AC11, AB11, AB12, AC12, AF12,
AE11, Y14, AE15, AC15, AB15, AA15, AD16,
Y15, AB16, AF18, AE18, AC17, AE19, AD19,
AB17, AB18, AA16
I/O
OV
—
DD
PCI1_C_BE[3:0]
PCI1_GNT[4:1]
PCI1_GNT0
PCI1_IRDY
AC10, AE12, AA14, AD17
I/O
O
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
AE7, AG11,AH11, AC8
4, 8, 24
AE6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
—
2
AF13
PCI1_PAR
AB14
—
2
PCI1_PERR
PCI1_SERR
PCI1_STOP
PCI1_TRDY
PCI1_REQ[4:1]
PCI1_REQ0
PCI1_CLK
AE14
AC14
2
AA13
2
AD13
2
AF9, AG10, AH10, AD6
—
—
—
2
AB8
I/O
I
AH26
AC13
AD12
AG6
PCI1_DEVSEL
PCI1_FRAME
PCI1_IDSEL
I/O
I/O
I
2
—
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
80
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
DDR SDRAM Memory Interface
MDQ[0:63]
A26, B26, C22, D21, D25, B25, D22, E21, A24,
A23, B20, A20, A25, B24, B21, A21, E19, D19,
E16, C16, F19, F18, F17, D16, B18, A18, A15,
B14, B19, A19, A16, B15, D1, F3, G1, H2, E4,
G5, H3, J4, B2, C3, F2, G2, A2, B3, E1, F1, L5,
L4,N3, P3, J3, K4, N4, P4, J1, K1, P1, R1, J2,
K2, N1, R2
I/O
GV
—
DD
MECC[0:7]
MDM[0:8]
MDQS[0:8]
MDQS[0:8]
MA[0:15]
G12, D14, F11, C11, G14, F14,C13, D12
C25, B23, D18, B17, G4, C2, L3, L2, F13
D24, B22, C18, A17, J5, C1, M4, M2, E13
C23, A22, E17, B16, K5, D2, M3, P2, D13
I/O
O
GV
GV
GV
GV
GV
—
21
—
—
—
DD
DD
DD
DD
DD
I/O
I/O
O
B7, G8, C8, A10, D9, C10, A11, F9, E9, B12,
A5, A12, D11, F7, E10, F10
MBA[0:2]
MWE
A4, B5, B13
O
O
O
O
O
O
O
O
O
I/O
I
GV
GV
GV
GV
GV
GV
GV
GV
GV
GV
—
—
—
—
10
—
—
—
—
25
27
17
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
B4
MCAS
E7
MRAS
C5
MCKE[0:3]
MCS[0:3]
MCK[0:5]
MCK[0:5]
MODT[0:3]
MDIC[0:1]
TEST_IN
TEST_OUT
H10, K10, G10, H9
D3, H6, C4, G6
A9, J11, J6, A8, J13, H8
B9, H11, K6, B8, H13, J8
E5, H7, E6, F6
H15, K15
A13
—
A6
O
—
Local Bus Controller Interface
LAD[0:31]
K22, L21, L22, K23, K24, L24, L25, K25, L28,
L27, K28, K27, J28, H28, H27, G27, G26, F28,
F26, F25, E28, E27, E26, F24, E24, C26, G24,
E23, G23, F22, G22, G21
I/O
BV
23
DD
LDP[0:3]
K26, G28, B27, E25
L19
I/O
O
BV
BV
BV
BV
BV
DD
DD
DD
DD
DD
LA[27]
4, 8
4, 6, 8
—
LA[28:31]
K16, K17, H17,G17
K18, G19, H19, H20, G16
H16
O
LCS[0:4]
O
LCS5/DMA_DREQ2
I/O
1
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
81
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
LCS6/DMA_DACK2
LCS7/DMA_DDONE2
LWE0/LBS0/LSDDQM[0]
LWE1/LBS1/LSDDQM[1]
LWE2/LBS2/LSDDQM[2]
LWE3/LBS3/LSDDQM[3]
LALE
J16
L18
J22
H22
H23
H21
J26
J25
J20
K20
G20
H18
L20
O
O
O
O
O
O
O
O
O
O
O
O
I/O
BV
BV
BV
BV
BV
BV
BV
BV
BV
BV
BV
BV
BV
1
1
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
4, 8
4, 8
4, 8
4, 8
4, 7, 8
4, 7, 8
4, 8
4, 8
4, 7, 8
4, 8
—
LBCTL
LGPL0/LSDA10
LGPL1/LSDWE
LGPL2/LOE/LSDRAS
LGPL3/LSDCAS
LGPL4/LGTA/LUPWAIT/
LPBSE
LGPL5
K19
L17
O
O
O
I
BV
BV
BV
BV
BV
4, 8
—
DD
DD
DD
DD
DD
LCKE
LCLK[0:2]
LSYNC_IN
LSYNC_OUT
H24, J24, H25
D27
—
—
D28
O
—
DMA
DMA_DACK[0:1]
DMA_DREQ[0:1]
DMA_DDONE[0:1]
Y13, Y12
O
I
OV
OV
OV
4, 8, 9
—
DD
DD
DD
AA10, AA11
AA7, Y11
O
—
Programmable Interrupt Controller
UDE
AH15
AG18
I
I
I
OV
OV
OV
—
—
—
DD
DD
DD
MCP
IRQ[0:7]
AG22, AF17, AD21, AF19, AG17, AF16, AC23,
AC22
IRQ[8]
AC19
AG20
AE27
AE24
AD14
I
OV
OV
OV
OV
OV
—
1
DD
DD
DD
DD
DD
IRQ[9]/DMA_DREQ3
IRQ[10]/DMA_DACK3
IRQ[11]/DMA_DDONE3
IRQ_OUT
I
I/O
I/O
O
1
1
2
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
82
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
Ethernet Management Interface
EC_MDC
EC_MDIO
AC7
Y9
O
OV
OV
4, 8, 14
—
DD
DD
I/O
Gigabit Reference Clock
EC_GTX_CLK125
T2
I
LV
—
DD
Three-Speed Ethernet Controller (Gigabit Ethernet 1)
TSEC1_RXD[7:0]
TSEC1_TXD[7:0]
TSEC1_COL
U10, U9, T10, T9, U8, T8, T7, T6
I
O
I
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
—
4, 8, 14
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
T5, U5, V5, V3, V2, V1, U2, U1
R5
T4
T1
V7
U7
R9
V6
U4
T3
TSEC1_CRS
I/O
O
I
16
TSEC1_GTX_CLK
TSEC1_RX_CLK
TSEC1_RX_DV
TSEC1_RX_ER
TSEC1_TX_CLK
TSEC1_TX_EN
TSEC1_TX_ER
—
—
I
—
I
4, 8
—
I
O
O
22
—
Three-Speed Ethernet Controller (Gigabit Ethernet 3)
TSEC3_RXD[7:0]
TSEC3_TXD[7:0]
TSEC3_COL
P11, N11, M11, L11, R8, N10, N9, P10
I
O
I
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
—
4, 8, 14
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
M7, N7, P7, M8, L7, R6, P6, M6
M9
TSEC3_CRS
L9
I/O
O
I
16
TSEC3_GTX_CLK
TSEC3_RX_CLK
TSEC3_RX_DV
TSEC3_RX_ER
TSEC3_TX_CLK
TSEC3_TX_EN
TSEC3_TX_ER
R7
—
P9
—
P8
I
—
R11
I
—
L10
I
—
N6
O
O
22
L8
4, 8
DUART
AH8, AF6
AG8, AG9
UART_CTS[0:1]
UART_RTS[0:1]
I
OV
OV
—
—
DD
DD
O
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
83
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
UART_SIN[0:1]
AG7, AH6
AH7, AF7
I
OV
OV
—
—
DD
DD
UART_SOUT[0:1]
O
2
I C interface
IIC1_SCL
IIC1_SDA
IIC2_SCL
IIC2_SDA
AG21
AH21
AG13
AG14
I/O
I/O
I/O
I/O
OV
OV
OV
OV
20
20
20
20
DD
DD
DD
DD
SerDes 1
SD1_RX[0:7]
SD1_RX[0:7]
SD1_TX[0:7]
N28, P26, R28, T26, Y26, AA28, AB26, AC28
I
I
XV
XV
XV
XV
XV
XV
XV
—
—
—
—
17
—
—
—
—
DD
DD
DD
DD
DD
DD
DD
N27, P25, R27, T25, Y25, AA27, AB25, AC27
M23, N21, P23, R21, U21, V23, W21, Y23
O
O
O
I
SD1_TX[0:7]
M22, N20, P22, R20, U20, V22, W20, Y22
SD1_PLL_TPD
SD1_REF_CLK
SD1_REF_CLK
SD1_TST_CLK
SD1_TST_CLK
V28
U28
U27
I
T22
—
T23
—
SerDes 2
AD25
AD1
AB2
AD26
AC1
AA2
AA21
AC4
AA5
AA20
AB4
Y5
SD2_RX[0]
SD2_RX[2]
SD2_RX[3]
SD2_RX[0]
SD2_RX[2]
SD2_RX[3]
SD2_TX[0]
SD2_TX[2]
SD2_TX[3]
SD2_TX[0]
SD2_TX[2]
SD2_TX[3]
SD2_PLL_TPD
SD2_REF_CLK
I
I
XV
—
26
26
—
26
26
—
17
17
—
17
17
17
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
XV
XV
XV
XV
XV
XV
XV
XV
XV
XV
XV
XV
XV
I
I
I
I
O
O
O
O
O
O
O
I
AG3
AE2
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
84
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
SD2_REF_CLK
SD2_TST_CLK
SD2_TST_CLK
AF2
AG4
AF4
I
XV
—
—
—
DD
—
—
—
—
General-Purpose Output
GPOUT[0:7]
GPIN[0:7]
AF22, AH23, AG27, AH25, AF21, AF25, AG26,
AF26
O
I
OV
—
—
DD
DD
General-Purpose Input
AH24, AG24, AD23, AE21, AD22, AF23, AG25,
AE20
OV
System Control
HRESET
AG16
AG15
AG19
AH5
I
O
I
OV
OV
OV
OV
OV
—
21
—
DD
DD
DD
DD
DD
HRESET_REQ
SRESET
CKSTP_IN
CKSTP_OUT
I
—
AA12
Debug
AC5
O
2, 4
TRIG_IN
I
OV
OV
—
DD
DD
TRIG_OUT/READY/
QUIESCE
AB5
O
5, 8, 15,
21
MSRCID[0:1]
MSRCID[2:4]
MDVAL
Y7, W9
AA9, AB6, AD5
Y8
O
O
O
O
OV
OV
OV
OV
4, 5, 8
5, 15, 21
5
DD
DD
DD
DD
CLK_OUT
AE16
10
Clock
RTC
AF15
I
I
OV
OV
—
—
DD
DD
SYSCLK
AH16
JTAG
TCK
TDI
AG28
I
I
OV
OV
OV
OV
OV
—
11
10
11
11
DD
DD
DD
DD
DD
AH28
TDO
TMS
TRST
AF28
O
I
AH27
AH22
I
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
85
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
DFT
Pin Type
Notes
L1_TSTCLK
L2_TSTCLK
LSSD_MODE
TEST_SEL
AC20
AE17
AH19
AH13
I
I
I
I
OV
OV
OV
OV
18
18
18
3
DD
DD
DD
DD
Thermal Management
TEMP_ANODE
Y3
—
—
—
13
13
TEMP_CATHODE
AA3
—
Power Management
ASLEEP
GND
AH17
O
OV
8, 15, 21
—
DD
Power and Ground Signals
D5, M10, F4, D26, D23, C12, C15, E20, D8,
B10, E3, J14, K21, F8, A3, F16, E12, E15, D17,
L1, F21, H1, G13, G15, G18, C6, A14, A7, G25,
H4, C20, J12, J15, J17, F27, M5, J27, K11, L26,
K7, K8, L12, L15, M14, M16, M18, N13, N15,
N17, N2, P5, P14, P16, P18, R13, R15, R17,
T14, T16, T18, U13, U15, U17, AA8, U6, Y10,
AC21, AA17, AC16, V4, AD7, AD18, AE23,
AF11, AF14, AG23, AH9, A27, B28, C27
—
—
OV [1:17]
Y16, AB7, AB10, AB13, AC6, AC18, AD9,
AD11, AE13, AD15, AD20, AE5, AE22, AF10,
AF20, AF24, AF27
Power for PCI
and other
standards
(3.3 V)
OV
—
—
—
—
DD
DD
LV [1:2]
R4, U3
Power for
TSEC1
interfaces
(2.5 V, 3.3 V)
LV
DD
DD
TV [1:2]
N8, R10
Power for
TSEC3
interfaces
(2.5 V, 3.3 V)
TV
DD
DD
GV
B1, B11, C7, C9, C14, C17, D4, D6, R3, D15,
E2, E8,C24, E18, F5, E14, C21, G3, G7, G9,
G11, H5, H12, E22, F15, J10, K3, K12, K14,
H14, D20, E11, M1, N5
Power for DDR1
and DDR2
DRAM I/O
voltage (1.8 V,
2.5 V)
GV
DD
DD
DD
DD
BV
L23, J18, J19, F20, F23, H26, J21, J23
Power for
local bus (1.8 V,
2.5 V, 3.3 V)
BV
—
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
86
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Package Pin Number Pin Type
L16, L14, M13, M15, M17, N12, N14, N16, N18, Power for core
Power
Supply
Signal
Notes
V
V
—
DD
DD
P13, P15, P17, R12, R14, R16, R18, T13, T15,
T17, U12, U14, U16, U18,
(1.0 V)
SVDD_SRDS
SVDD_SRDS2
XVDD_SRDS
XVDD_SRDS2
XGND_SRDS
M27, N25, P28, R24, R26, T24, T27, U25, W24, Core power for
SV
SV
XV
XV
—
—
—
—
—
DD
DD
DD
DD
W26, Y24, Y27, AA25, AB28, AD27
SerDes 1
transceivers
(1.0 V)
AB1, AC26, AD2, AE26, AG2
Core power for
SerDes 2
transceivers
(1.0 V)
M21, N23, P20, R22, T20, U23, V21, W22, Y20 Pad power for
SerDes 1
transceivers
(1.0 V)
Y6, AA6, AA23, AF5, AG5
Pad power for
SerDes 2
transceivers
(1.0 V)
M20, M24, N22, P21, R23, T21, U22, V20, W23,
Y21
—
—
XGND_SRDS2
SGND_SRDS
Y4, AA4, AA22, AD4, AE4, AH4
—
—
—
—
—
—
M28, N26, P24, P27, R25, T28, U24, U26, V24,
W25, Y28, AA24, AA26, AB24, AB27, AC24,
AD28
AGND_SRDS
SGND_SRDS2
AGND_SRDS2
AVDD_LBIU
V27
SerDes PLL
GND
—
—
—
—
—
—
—
19
Y2, AA1, AB3, AC2, AC3, AC25, AD3, AD24,
AE3, AE1, AE25, AF3, AH2
—
AF1
SerDes PLL
GND
C28
Power for local
bus PLL
(1.0 V)
AVDD_PCI1
AH20
Power for PCI
PLL
—
19
(1.0 V)
AVDD_CORE
AVDD_PLAT
AH14
AH18
Power for e500
PLL (1.0 V)
—
—
19
19
Power for CCB
PLL (1.0 V)
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
87
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
AVDD_SRDS
W28
AG1
Power for
SRDSPLL
(1.0 V)
—
—
19
AVDD_SRDS2
Power for
SRDSPLL
(1.0 V)
19
SENSEVDD
SENSEVSS
W11
W10
O
V
12
12
DD
—
—
Analog Signals
MVREF
A28
Reference
voltage signal
for DDR
MVREF
—
SD1_IMP_CAL_RX
SD1_IMP_CAL_TX
SD1_PLL_TPA
M26
AE28
V26
—
—
—
200Ω to GND
100Ω to GND
—
—
17
AVDD_SRDS
ANALOG
SD2_IMP_CAL_RX
SD2_IMP_CAL_TX
SD2_PLL_TPA
AH3
Y1
I
I
200 Ω to GND
100 Ω to GND
—
—
17
AH1
O
AVDD_SRDS2
ANALOG
No Connect Pins
NC
C19, D7, D10, K13, L6, K9, B6, F12, J7, M19,
M25, N19, N24, P19, R19, AB19, T12, W3,
M12, W5, P12, T19, W1, W7, L13, U19, W4, V8,
V9, V10, V11, V12, V13, V14, V15, V16, V17,
V18, V19, W2, W6, W8, T11, U11, W12, W13,
W14, W15, W16, W17, W18, W19, W27, V25,
Y17, Y18, Y19, AA18, AA19, AB20, AB21,
AB22, AB23, J9
—
—
—
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
2. Recommend a weak pull-up resistor (2–10 KΩ) be placed on this pin to OV
.
DD
3. This pin must always be pulled high.
4. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net
at reset, then a pull-up or active driver is needed.
5. Treat these pins as no connects (NC) unless using debug address functionality.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
88
Freescale Semiconductor
Package Description
Table 57. MPC8533E Pinout Listing (continued)
Package Pin Number Pin Type
Power
Supply
Signal
Notes
6. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down
resistors. See Section 19.2, “CCB/SYSCLK PLL Ratio.”
7. The value of LALE, LGPL2, and LBCTL at reset set the e500 core clock to CCB clock PLL ratio. These pins require 4.7-kΩ
pull-up or pull-down resistors. See Section 19.3, “e500 Core PLL Ratio.”
8. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. Therefore, this pin will be described as an I/O for boundary scan.
9. For proper state of these signals during reset, these pins can be left without any pull downs, thus relying on the internal
pullup to get the values to the require 2'b11. However, if there is any device on the net which might pull down the value of
the net at reset, then a pullup is needed.
10. This output is actively driven during reset rather than being three-stated during reset.
11. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
12. These pins are connected to the V /GND planes internally and may be used by the core power supply to improve tracking
DD
and regulation.
13. Anode and cathode of internal thermal diode.
14. Treat pins AC7, T5, V2, and M7 as spare configuration pins cfg_spare[0:3]. The spare pins are unused POR config pins. It
is highly recommended that the customer provide the capability of setting these pins low (that is, pull-down resistor which
is not currently stuffed) in order to support new config options should they arise between revisions.
15. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state
during reset.
16. This pin is only an output in FIFO mode when used as Rx flow control.
17. Do not connect.
18. These are test signals for factory use only and must be pulled up (100 Ω to 1 kΩ) to OV for normal machine operation.
DD
19. Independent supplies derived from board V
.
DD
20. Recommend a pull-up resistor (1 K~) be placed on this pin to OV
.
DD
21. The following pins must not be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE,
MSRCID[2:4], and ASLEEP.
22. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid transmit enable before it is
actively driven.
23. General-purpose POR configuration of user system.
24. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled
down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as No
Connect or terminated through 2–10 kΩ pull-up resistors with the default of internal arbiter if the address pins are not
connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through
POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is
any other PCI device connected on the bus.
25. MDIC0 is grounded through an 18.2-Ω precision 1% resistor and MDIC1 is connected GV through an 18.2-Ω precision
DD
1% resistor. These pins are used for automatic calibration of the DDR IOs.
26. Connect to GND.
27.Connect to GND.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
89
Clocking
19 Clocking
This section describes the PLL configuration of the MPC8533E . Note that the platform clock is identical
to the core complex bus (CCB) clock.
19.1 Clock Ranges
Table 58 provides the clocking specifications for the processor cores and Table 59 provides the clocking
specifications for the memory bus.
Table 58. Processor Core Clocking Specifications
Maximum Processor Core Frequency
Characteristic
667 MHz
800 MHz
1000 MHz
1067 MHz
Unit
Notes
Min
667
Max
Min
667
Max
Min
667
Max
Min
667
Max
e500 core processor frequency
667
800
1000
1067
MHz
1, 2
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings.
2. The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
Table 59. Memory Bus Clocking Specifications
Maximum Processor Core
Frequency
Characteristic
Unit
Notes
667, 800, 1000, 1067 MHz
Min
Max
Memory bus clock speed
166
266
MHz
1, 2
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio
settings.
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
19.2 CCB/SYSCLK PLL Ratio
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform
clock. The frequency of the CCB is set using the following reset signals (see Table 60):
•
•
SYSCLK input signal
Binary value on LA[28:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB
frequency must equal the DDR data rate.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
90
Freescale Semiconductor
Clocking
Table 60. CCB Clock Ratio
Binary Value of
LA[28:31] Signals
Binary Value of
LA[28:31] Signals
CCB:SYSCLK Ratio
CCB:SYSCLK Ratio
0000
0001
0010
0011
0100
0101
0110
0111
16:1
Reserved
Reserved
3:1
1000
1001
1010
1011
1100
1101
1110
1111
8:1
9:1
10:1
Reserved
12:1
4:1
5:1
Reserved
Reserved
Reserved
6:1
Reserved
19.3 e500 Core PLL Ratio
Table 61 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
ratio is determined by the binary value of LBCTL, LALE, and LGPL2 at power up, as shown in Table 61.
Table 61. e500 Core to CCB Clock Ratio
Binary Value of
LBCTL, LALE,
LGPL2 Signals
Binary Value of
LBCTL, LALE,
LGPL2 Signals
e500 core:CCB Clock Ratio
e500 core:CCB Clock Ratio
000
001
010
011
4:1
100
101
110
111
2:1
5:2
3:1
7:2
Reserved
Reserved
3:2
19.4 PCI Clocks
For specifications on the PCI_CLK, refer to the PCI 2.2 Local Bus Specifications.
The use of PCI_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this
range then use of PCI_CLK is required as a separate PCI clock source, asynchronous with respect to
SYSCLK.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
91
Clocking
19.5 Security Controller PLL Ratio
Table 62 shows the SEC frequency ratio.
Table 62. SEC Frequency Ratio
Signal Name
Value (Binary)
CCB CLK:SEC CLK
1
LWE_B
0
1
2:1
2
3:1
Notes:
1. In 2:1 mode the CCB frequency must be operating <= 400 MHz.
2. In 3:1 mode any valid CCB can be used. The 3:1 mode is the default
ratio for security block.
19.6 Frequency Options
19.6.1 SYSCLK to Platform Frequency Options
Table 63 shows the expected frequency values for the platform frequency when using a CCB clock to
SYSCLK ratio in comparison to the memory bus clock speed.
Table 63. Frequency Options of SYSCLK with Respect to Memory Bus Speeds
CCB to SYSCLK
SYSCLK (MHz)
Ratio
33.33
41.66
66.66
83
100
111
133.33
Platform /CCB Frequency (MHz)
2
3
—
—
333
445
400
533
4
—
333
415
500
400
500
5
333
400
533
6
8
333
375
417
500
9
10
12
16
333
400
533
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
92
Thermal
19.6.2 Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed. Refer to Section 4.4,
“Platform to FIFO Restrictions,” for additional information.
Table 64. FIFO Maximum Speed Restrictions
Maximum FIFO Speed for Reference Clocks
TSECn_TX_CLK, TSECn_RX_CLK (MHz)
Platform Speed (MHz)
1
533
400
126
94
Note:
1. FIFO speed should be less than 24% of the platform speed.
20 Thermal
This section describes the thermal specifications of the MPC8533E.
20.1 Thermal Characteristics
Table 65 provides the package thermal characteristics.
Table 65. Package Thermal Characteristics
Characteristic
JEDEC Board
Symbol
Value
Unit
Notes
Junction-to-ambient natural convection
Junction-to-ambient natural convection
Junction-to-ambient (@200 ft/min)
Junction-to-ambient (@200 ft/min)
Junction-to-board thermal
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
—
R
R
R
R
R
26
21
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 2
1, 2
1, 2
3
θJA
θJA
θJA
θJA
θJB
θJC
21
17
12
Junction-to-case thermal
—
R
<0.1
4
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL
SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1°C/W.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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Thermal
Table 66 provides the thermal resistance with heat sink in open flow.
Table 66. Thermal Resistance with Heat Sink in Open Flow
Heat Sink with Thermal Grease
Air Flow
Thermal Resistance (°C/W)
Wakefield 53 × 53 × 25 mm pin fin
Wakefield 53 × 53 × 25 mm pin fin
Aavid 35 × 31 × 23 mm pin fin
Aavid 35 × 31 × 23 mm pin fin
Aavid 30 × 30 × 9.4 mm pin fin
Aavid 30 × 30 × 9.4 mm pin fin
Aavid 43 × 41 × 16.5 mm pin fin
Aavid 43 × 41 × 16.5 mm pin fin
Natural convection
1 m/s
6.1
3.0
8.1
4.3
11.6
6.7
8.3
4.3
Natural convection
1 m/s
Natural convection
1 m/s
Natural convection
1 m/s
Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The
thermal interface material was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease.
For system thermal modeling, the MPC8533E thermal model without a lid is shown in Figure 56. The
substrate is modeled as a block 29 × 29 × 1.18 mm with an in-plane conductivity of 18.0 W/m•K and a
through-plane conductivity of 1.0 W/m•K. The solder balls and air are modeled as a single block
29 × 29 × 0.58 mm with an in-plane conductivity of 0.034 W/m•K and a through plane conductivity of
12.1 W/m•K. The die is modeled as 7.6 × 8.4 mm with a thickness of 0.75 mm. The bump/underfill layer
is modeled as a collapsed thermal resistance between the die and substrate assuming a conductivity of
6.5 W/m•K in the thickness dimension of 0.07 mm. The die is centered on the substrate. The thermal model
uses approximate dimensions to reduce grid. Please refer to Figure 55 for actual dimensions.
20.2 Recommended Thermal Model
Table 67 shows the MPC8533E thermal model.
Table 67. MPC8533EThermal Model
Conductivity
Value
Units
Die (7.6 × 8.4 × 0.75mm)
Silicon
Temperature dependent
—
Bump/Underfill (7.6 × 8.4 × 0.070 mm) Collapsed Thermal Resistance
Kz
6.5
W/m•K
Substrate (29 × 29 × 1.18 mm)
Kx
Ky
Kz
18
18
W/m•K
1.0
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Thermal
Table 67. MPC8533EThermal Model (continued)
Conductivity
Value
Units
Solder and Air (29 × 29 × 0.58 mm)
Kx
Ky
Kz
0.034
0.034
12.1
W/m•K
Bump Underfill
Section A-A
Die
Substrate
Solder/Air
A
A
Top View
Figure 56. System Level Thermal Model for MPC8533E (Not to Scale)
The Flotherm library files of the parts have a dense grid to accurately capture the laminar boundary layer
for flow over the part in standard JEDEC environments, as well as the heat spreading in the board under
the package. In a real system, however, the part will require a heat sink to be mounted on it. In this case,
the predominant heat flow path will be from the die to the heat sink. Grid density lower than currently in
the package library file will suffice for these simulations. The user will need to determine the optimal grid
for their specific case.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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Thermal
20.3 Thermal Management Information
This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA)
package for air-cooled applications. Proper thermal control design is primarily dependent on the
system-level design—the heat sink, airflow, and thermal interface material. The MPC8533E implements
several features designed to assist with thermal management, including the temperature diode. The
temperature diode allows an external device to monitor the die temperature in order to detect excessive
temperature conditions and alert the system; see Section 20.3.4, “Temperature Diode,” for more
information.
The recommended attachment method to the heat sink is illustrated in Figure 57. The heat sink should be
attached to the printed-circuit board with the spring force centered over the die. This spring force should
not exceed 10 pounds force (45 Newton).
FC-PBGA Package
Heat Sink
Heat Sink
Clip
Adhesive or
Thermal Interface Material
Die
Printed-Circuit Board
Figure 57. Package Exploded Cross-Sectional View with Several Heat Sink Options
The system board designer can choose between several types of heat sinks to place on the device. There
are several commercially-available heat sinks from the following vendors:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
603-224-9988
781-769-2800
408-567-8082
Advanced Thermal Solutions
89 Access Road #27.
Norwood, MA02062
Internet: www.qats.com
Alpha Novatech
473 Sapena Ct. #12
Santa Clara, CA 95054
Internet: www.alphanovatech.com
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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Thermal
International Electronic Research Corporation (IERC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
408-436-8770
800-522-6752
603-635-2800
Internet: www.mei-thermal.com
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several
heat sinks offered by Aavid Thermalloy, Advanced Thermal Solutions, Alpha Novatech, IERC, Chip
Coolers, Millennium Electronics, and Wakefield Engineering offer different heat sink-to-ambient thermal
resistances, that will allow the MPC8533E to function in various environments.
20.3.1 Internal Package Conduction Resistance
For the packaging technology, shown in Table 65, the intrinsic internal conduction thermal resistance paths
are as follows:
•
•
The die junction-to-case thermal resistance
The die junction-to-board thermal resistance
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Thermal
Figure 58 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
Internal Resistance
Printed-Circuit Board
Radiation
Convection
External Resistance
(Note the internal versus external package resistance.)
Figure 58. Package with Heat Sink Mounted to a Printed-Circuit Board
The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is
conducted through the silicon and through the heat sink attach material (or thermal interface material), and
finally to the heat sink. The junction-to-case thermal resistance is low enough that the heat sink attach
material and heat sink thermal resistance are the dominant terms.
20.3.2 Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal
contact resistance. For those applications where the heat sink is attached by spring clip mechanism,
Figure 59 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,
graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.
As shown, the performance of these thermal interface materials improves with increasing contact pressure.
The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a
thermal resistance approximately six times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 57). Therefore, the synthetic grease offers the best thermal performance, especially at the low
interface pressure.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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Freescale Semiconductor
Thermal
Silicone Sheet (0.006 in.)
Bare Joint
2
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
1.5
1
0.5
0
0
10
20
30
Contact Pressure (psi)
Figure 59. Thermal Performance of Select Thermal Interface Materials
40
50
60
70
80
The system board designer can choose between several types of thermal interface. There are several
commercially-available thermal interfaces provided by the following vendors:
Chomerics, Inc.
781-935-4850
77 Dragon Ct.
Woburn, MA 01801
Internet: www.chomerics.com
Dow-Corning Corporation
Corporate Center
800-248-2481
P.O.Box 999
Midland, MI 48686-0997
Internet: www.dow.com
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
888-642-7674
800-347-4572
Internet: www.microsi.com
The Bergquist Company
th
18930 West 78 St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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Thermal
Thermagon Inc.
888-246-9050
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
20.3.3 Heat Sink Selection Examples
The following section provides a heat sink selection example using one of the commercially available heat
sinks.
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
T = T + T + (θ + θ
+ θ ) × P
SA D
J
I
R
JC
INT
where
T is the die-junction temperature
J
T is the inlet cabinet ambient temperature
I
T is the air temperature rise within the computer cabinet
R
θ
θ
θ
is the junction-to-case thermal resistance
JC
is the adhesive or interface material thermal resistance
INT
is the heat sink base-to-ambient thermal resistance
SA
P is the power dissipated by the device
D
During operation the die-junction temperatures (T ) should be maintained within the range specified in
J
Table 2. The temperature of air cooling the component greatly depends on the ambient inlet air temperature
and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T )
I
may range from 30° to 40°C. The air temperature rise within a cabinet (T ) may be in the range of 5° to
R
10°C. The thermal resistance of the thermal interface material (θ ) may be about 1°C/W. Assuming a T
INT
I
of 30°C, a T of 5°C, a FC-PBGA package θ = 0.1, and a power consumption (P ) of 5, the following
R
JC
D
expression for T is obtained:
J
Die-junction temperature: T = 30°C + 5°C + (0.1°C/W + 1.0°C/W + θ ) × P
D
J
SA
The heat sink-to-ambient thermal resistance (θ ) versus airflow velocity for a Thermalloy heat sink
SA
#2328B is shown in Figure 60.
Assuming an air velocity of 1 m/s, we have an effective θ
of about 5°C/W, thus
SA+
T = 30° + 5°C + (0.1°C/W + 1.0°C/W + 5°C/W) × 5
J
resulting in a die-junction temperature of approximately 66, which is well within the maximum operating
temperature of the component.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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Freescale Semiconductor
Thermal
8
7
6
5
4
3
2
1
Thermalloy #2328B Pin-fin Heat Sink
(25 × 28 × 15 mm)
0
0.5
1
1.5
2
2.5
3
3.5
Figure 60. Approach Air Velocity (m/s)
20.3.4 Temperature Diode
The MPC8533E has a temperature diode on the microprocessor that can be used in conjunction with other
system temperature monitoring devices (such as Analog Devices, ADT7461™). These devices use the
negative temperature coefficient of a diode operated at a constant current to determine the temperature of
the microprocessor and its environment. It is recommended that each device be individually calibrated.
The following are voltage forward biased range of the on-board temperature diode:
V > 0.40 V
f
V < 0.90 V
f
An approximate value of the ideality may be obtained by calibrating the device near the expected operating
temperature. The ideality factor is defined as the deviation from the ideal diode equation:
qV
f
nKT
I
= I e
– 1
fw
s
Another useful equation is:
KT
q
I
H
V – V = n
ln
H
L
I
L
where:
I
= Forward current
fw
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
101
System Design Information
I = Saturation current
s
V = Voltage at diode
d
V = Voltage forward biased
f
V = Diode voltage while I is flowing
H
H
V = Diode voltage while I is flowing
L
L
I = Larger diode bias current
H
I = Smaller diode bias current
L
–19
q = Charge of electron (1.6 × 10
C)
n = Ideality factor (normally 1.0)
–23
K = Boltzman’s constant (1.38 × 10 Joules/K)
T = Temperature (Kelvins)
The ratio of I to I is usually selected to be 10:1. The above simplifies to the following:
H
L
–4
V – V = 1.986 × 10 × nT
H
L
Solving for T, the equation becomes:
V – V
H
L
nT =
–4
1.986 × 10
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8533E.
21.1 System Clocking
This device includes six PLLs:
•
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in Section 19.2, “CCB/SYSCLK PLL Ratio.”
•
The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e500 core clock and the platform clock is selected using the e500 PLL ratio
configuration bits as described in Section 19.3, “e500 Core PLL Ratio.”
•
•
•
The PCI PLL generates the clocking for the PCI bus.
The local bus PLL generates the clock for the local bus.
There are two PLLs for the SerDes block.
21.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins
(AV _PLAT, AV _CORE, AV _PCI, AV _LBIU, and AV _SRDS, respectively). The AV
DD
DD
DD
DD
DD
DD
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
102
System Design Information
level should always be equivalent to V , and preferably these voltages will be derived directly from V
DD
DD
through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in Figure 61, one to each of the
AV pins. By providing independent filters to each PLL the opportunity to cause noise injection from
DD
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize
DD
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of 783 FC-PBGA the footprint, without the inductance of vias.
DD
Figure 61 shows the PLL power supply filter circuit.
10 Ω
V
AV
DD
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 61. MPC8533E PLL Power Supply Filter Circuit
The AV _SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability
DD
of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
Figure 62. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AV _SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be
DD
near the AV _SRDSn balls. The 0.003-µF capacitor is closest to the balls, followed by the 1-µF
DD
capacitor, and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from
AV _SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant
DD
frequency. All traces should be kept short, wide, and direct.
1.0 Ω
SV
AV _SRDS
DD
DD
1
1
2.2 µF
2.2 µF
0.003 µF
GND
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
Figure 62. SerDes PLL Power Supply Filter Circuit
Note the following:
•
•
AV
SRDS should be a filtered version of SV
.
DD_
DD
Signals on the SerDes interface are fed from the XV power plane.
DD
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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System Design Information
21.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8533E system, and the device
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each V , TV , BV , OV , GV , and LV pin
DD
DD
DD
DD
DD
DD
of the device. These decoupling capacitors should receive their power from separate V , TV , BV ,
DD
DD
DD
OV , GV , and LV ; and GND power planes in the PCB, utilizing short low impedance traces to
DD
DD
DD
minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern.
Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V , TV , BV , OV , GV , and LV planes, to enable quick recharging of the
DD
DD
DD
DD
DD
DD
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor
for best values and types and quantity of bulk capacitors.
21.4 SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (SV and XV ) to ensure low
DD
DD
jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is
outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
•
First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
•
•
Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be
done for all SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
21.5 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to V , TV , BV , OV , GV , and LV as
DD
DD
DD
DD
DD
DD
required. All unused active high inputs should be connected to GND. All NC (no connect) signals must
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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Freescale Semiconductor
System Design Information
remain unconnected. Power and ground connections must be made to all external V , TV , BV ,
DD
DD
DD
OV , GV , and LV , and GND pins of the device.
DD
DD
DD
21.6 Pull-Up and Pull-Down Resistor Requirements
The MPC8533E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins
2
including I C pins and MPIC interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 65. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1] and TEST_SEL pins
must be set to a proper state during POR configuration. Refer to the pinout listing table (Table 57) for more
details. Refer to the PCI 2.2 Local Bus Specifications, for all pullups required for PCI.
21.7 Output Buffer DC Impedance
The MPC8533E drivers are characterized over process, voltage, and temperature. For all buses, the driver
2
is a push-pull single-ended driver type (open drain for I C). To measure Z for the single-ended drivers,
0
an external resistor is connected from the chip pad to OV or GND. Then, the value of each resistor is
DD
varied until the pad voltage is OV /2 (see Figure 63). The output impedance is the average of two
DD
components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed
(SW2 is open) and R is trimmed until the voltage at the pad equals OV /2. R then becomes the
P
DD
P
resistance of the pull-up devices. R and R are designed to be close to each other in value. Then,
P
N
Z = (R + R )/2.
0
P
N
OV
DD
R
N
SW2
SW1
Pad
Data
R
P
OGND
Figure 63. Driver Impedance Measurement
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
105
System Design Information
Table 68 summarizes the signal impedance targets. The driver impedances are targeted at minimum V
,
DD
nominal OV , 90°C.
DD
Table 68. Impedance Characteristics
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
Impedance
PCI
DDR DRAM
Symbol
Unit
R
N
43 Target
43 Target
25 Target
25 Target
20 Target
20 Target
Z
Z
W
W
0
0
R
P
Note: Nominal supply voltages. See Table 1.
21.8 Configuration Pin Muxing
The MPC8533E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
been encoded such that a high voltage level puts the device into the default state and external resistors are
needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up
devices.
21.9 JTAG Configuration Signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 65. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors built on Power Architecture™ technology.
The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does
not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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System Design Information
using only the TCK and TMS signals, generally systems will assert TRST during the power-on reset flow.
Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the
common on-chip processor (COP) function.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic. The arrangement shown in Figure 65 allows the COP port to
independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well.
The COP interface has a standard header, shown in Figure 64, for connection to the target system, and is
based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The
connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. An inexpensive option can be to leave
the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have
been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others
use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as
with an IC). Regardless of the numbering, the signal placement recommended in Figure 64 is common to
all known emulators.
21.9.1 Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following connections:
•
TRST should be tied to HRESET through a 0-kΩ isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in Figure 65. If this is not possible, the isolation resistor will allow future access to TRST
in case a JTAG interface may need to be wired onto the system in future debug situations.
•
No pull-up/pull-down is required for TDI, TMS, or TDO.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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107
System Design Information
2
4
1
3
COP_TDO
COP_TDI
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
COP_RUN/STOP
COP_TCK
5
7
6
8
COP_TMS
9
10
12
NC
NC
COP_SRESET
11
KEY
13
15
COP_HRESET
No pin
GND
COP_CHKSTP_OUT
16
Figure 64. COP Connector Physical Pinout
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
108
System Design Information
OV
DD
10 kΩ
10 kΩ
6
SRESET
HRESET
SRESET
HRESET
From Target
Board Sources
(if any)
1
COP_HRESET
13
11
10 kΩ
10 kΩ
10 kΩ
10 kΩ
COP_SRESET
B
A
5
1
TRST
COP_TRST
4
1
3
2
4
6
8
2
10 Ω
COP_VDD_SENSE
NC
6
5
5
7
COP_CHKSTP_OUT
CKSTP_OUT
15
10 kΩ
9
10
3
14
11
12
10 kΩ
KEY
13
15
COP_CHKSTP_IN
COP_TMS
No pin
CKSTP_IN
TMS
8
9
1
3
16
COP_TDO
COP_TDI
COP_TCK
COP Connector
Physical Pinout
TDO
TDI
7
2
TCK
10 kΩ
NC
NC
10
4
12
16
Notes:
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
in order to fully control the processor as shown here.
2. Populate this with a 10-Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No Connect, some debug tools may use pin 12 as an additional GND pin for
improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL
testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be
closed to position B.
6. Asserting SRESET causes a machine check interrupt to the e500 core.
Figure 65. JTAG Interface Connection
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
109
System Design Information
21.10 Guidelines for High-Speed Interface Termination
21.10.1 SerDes Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in
this section. However, the SerDes must always have power applied to its supply pins.
The following pins must be left unconnected (float):
•
•
SD_TX[0:7]
SD_TX[0:7]
The following pins must be connected to GND:
•
•
•
•
SD_RX[0:7]
SD_RX[0:7]
SD_REF_CLK
SD_REF_CLK
21.10.2 SerDes Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins
should be terminated as described in this section.
The following pins must be left unconnected (float) if not used:
•
•
SD_TX[0:7]
SD_TX[0:7]
The following pins must be connected to GND if not used:
•
•
•
•
SD_RX[0:7]
SD_RX[0:7]
SD_REF_CLK
SD_REF_CLK
21.11 Guideline for PCI Interface Termination
PCI termination if not used at all is done as follows.
Option 1
•
•
•
•
If PCI arbiter is enabled during POR,
All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating.
All PCI control pins can be grouped together and tied to OV through a single 10-kΩ resistor.
It is optional to disable PCI block through DEVDISR register after POR reset.
DD
Option 2
If PCI arbiter is disabled during POR,
•
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
110
Device Nomenclature
•
•
All AD pins will be in the input state. Therefore, all ADs pins need to be grouped together and tied
to OV through a single (or multiple) 10-kΩ resistor(s).
DD
All PCI control pins can be grouped together and tied to OV through a single 10-kΩ resistor.
DD
21.12 Guideline for LBIU Termination
If the LBIU parity pins are not used, the following list shows the termination recommendation:
•
•
For LDP[0:3]: tie them to ground or the power supply rail via a 4.7-kΩ resistor.
For LPBSE: tie it to the power supply rail via a 4.7-kΩ resistor (pull-up resistor).
22 Device Nomenclature
Ordering information for the parts fully covered by this hardware specifications document is provided in
Section 22.3, “Part Marking.” Contact your local Freescale sales office or regional marketing team for
order information.
22.1 Industrial and Commercial Tier Qualification
The MPC8533E device has been tested to meet the commercial tier qualification. Table 69 provides a
description for commercial and industrial qualifications.
Table 69. Commercial and Industrial Description
Typical Application
Use Time
1
Tier
Power-On Hours
Example of Typical Applications
Commercial
Industrial
Note:
5 years
Part-time/ Full-Time PC's, consumer electronics, office automation, SOHO networking,
portable telecom products, PDA's, etc.
10 years
Typically Full-Time Installed telecom equipment, work stations, servers, warehouse
equipment, etc.
1. Refer to Table 2 for operating temperature ranges. Temperature is independent of tier and varies per product.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
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111
Device Nomenclature
22.2 Nomenclature of Parts Fully Addressed by this Document
Table 70 provides the Freescale part numbering nomenclature for the MPC8533E.
Table 70. Device Nomenclature
MPC nnnn
E
C
HX
AA
X
B
Product
Code
Part
Encryption
Processor
Frequency
Platform
Frequency
Revision
Level
1
Temperature Range
Package
2
Identifier Acceleration
MPC
8533
Blank = not
included
Blank = 0° to 90°C
VT = FC-PBGA AL = 667 MHz
(lead free) AN = 800 MHz G = 400 MHz Freescale
F = 333 MHz Contactlocal
E = included
AQ = 1000 MHz J = 533 MHz
AR = 1067 MHz
sales office
Notes:
1. See Section 18, “Package Description,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by part number specifications may support other
maximum core frequencies.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
112
Freescale Semiconductor
Device Nomenclature
22.3 Part Marking
Parts are marked as in the example shown in Figure 66.
MPCnnnnCHXAAXB
MMMMM CCCCC
ATWLYYWW
FC-PBGA
Notes:
MMMMM is the 5-digit mask number.
ATWLYYWW is the traceability code.
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 66. Part Marking for FC-PBGA Device
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
113
Document Revision History
23 Document Revision History
Table 71 provides a revision history for the MPC8533E hardware specification.
Table 71. MPC8533E Document Revision History
Revision
Date
Substantive Change(s)
• Update Section 20.3.4, “Temperature Diode,”
3
11/2009
• Update Table 56 Package Parameters from 95.5%sn to 96.5%sn
2
01/2009
•
• Update power number table to include 1067 MHz/533 MHz power numbers.
• Remove Part number tables from Hardware spec. The part numbers are available on Freescale
web site product page.
• Removed I/O power numbers from the Hardware spec. and added the table to bring-up guide
applacation note
• Updated RX_CLK duty cycle min, and max value to meet the industry standard GMII duty cycle.
• In Table 35, removed note 1 and renumbered remaining note.
• Update paragraph Section 21.3, “Decoupling Recommendations
• Update t
t
in Table 18
DDKHMP, DDKHME
• Update Figure 5 DDR Output Timing Diagram
1
0
06/2008
04/2008
Correction in Table 18 DDR SDRAM Output AC Timing Specifications tMCK Max value
Improvement to Section 16, “High-Speed Serial Interfaces (HSSI)
Update Figure 55 Mechanical Dimensions
Correction in Table 43 Local Bus General Timing Parameters—PLL Bypassed
Initial release.
MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
114
Document Revision History
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115
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Document Number: MPC8533EEC
Rev. 3
11/2009
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