MPXR2010VMM120R [FREESCALE]
PXS20 Microcontroller; PXS20微控制器
| 型号： | MPXR2010VMM120R |
| 厂家： | 
Freescale |
| 描述： | PXS20 Microcontroller |
| 文件： | 总119页 (文件大小：667K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: PXS20
Rev. 1, 09/2011
PXS20
144 LQFP
PXS20 Microcontroller Data
Sheet
257 MAPBGA
(20 x 20 x 1.4 mm)
(14 x 14 x 0.8 mm)
• GPIOs individually programmable as input, output or
special function
• High-performance e200z4d dual core
®
– 32-bit Power Architecture technology CPU
• Three 6-channel general-purpose eTimer units
• 2 FlexPWM units
– Four 16-bit channels per module
• Communications interfaces
– Core frequency as high as 120 MHz
– Dual issue five-stage pipeline core
– Variable Length Encoding (VLE)
– Memory Management Unit (MMU)
– 4 KB instruction cache with error detection code
– Signal processing engine (SPE)
– 2 LINFlexD channels
– 3 DSPI channels with automatic chip select generation
– 2 FlexCAN interfaces (2.0B Active) with 32 message
objects
• Memory available
– 1 MB flash memory with ECC
– FlexRay module (V2.1 Rev. A) with 2 channels, 64
message buffers and data rates up to 10 Mbit/s
• Two 12-bit analog-to-digital converters (ADCs)
– 16 input channels
– 128 KB on-chip SRAM with ECC
– Built-in RWW capabilities for EEPROM emulation
• SIL3/ASILD innovative safety concept: LockStep mode
and Fail-safe protection
– Programmable cross triggering unit (CTU) to
synchronize ADCs conversion with timer and PWM
• Sine wave generator (D/A with low pass filter)
• On-chip CAN/UART bootstrap loader
• Single 3.0 V to 3.6 V voltage supply
• Ambient temperature range –40 °C to 125 °C
• Junction temperature range –40 °C to 150 °C
– Sphere of replication (SoR) for key components (such as
CPU core, eDMA, crossbar switch)
– Fault collection and control unit (FCCU)
– Redundancy control and checker unit (RCCU) on
outputs of the SoR connected to FCCU
– Boot-time Built-In Self-Test for Memory (MBIST) and
Logic (LBIST) triggered by hardware
– Boot-time Built-In Self-Test for ADC and flash memory
triggered by software
– Replicated safety enhanced watchdog
– Replicated junction temperature sensor
– Non-maskable interrupt (NMI)
– 16-region memory protection unit (MPU)
– Clock monitoring units (CMU)
– Power management unit (PMU)
– Cyclic redundancy check (CRC) unit
• Decoupled Parallel mode for high-performance use of
replicated cores
• Nexus Class 3+ interface
• Interrupts
– Replicated 16-priority controller
– Replicated 16-channel eDMA controller
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.5.40 IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . 21
1.5.41 Nexus Port Controller (NPC) . . . . . . . . . . . . . . 22
Package pinouts and signal descriptions . . . . . . . . . . . . . . . 23
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.3 System pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4 Pin muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 73
3.3 Recommended operating conditions. . . . . . . . . . . . . . 74
3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 75
3.4.1 General notes for specifications at maximum
1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.5.1 High-Performance e200z4d Core . . . . . . . . . . . .7
1.5.2 Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . .8
1.5.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . .8
1.5.4 Enhanced Direct Memory Access (eDMA) . . . . .9
1.5.5 On-Chip Flash Memory with ECC . . . . . . . . . . . .9
1.5.6 On-Chip SRAM with ECC . . . . . . . . . . . . . . . . . .9
1.5.7 Platform Flash Memory Controller. . . . . . . . . . .10
1.5.8 Platform Static RAM Controller (SRAMC) . . . . .10
1.5.9 Memory Subsystem Access Time . . . . . . . . . . .11
1.5.10 Error Correction Status Module (ECSM) . . . . . .11
1.5.11 Peripheral Bridge (PBRIDGE) . . . . . . . . . . . . . .11
1.5.12 Interrupt Controller (INTC). . . . . . . . . . . . . . . . .11
1.5.13 System Clocks and Clock Generation . . . . . . . .12
1.5.14 Frequency-Modulated Phase-Locked Loop
2
3
junction temperature. . . . . . . . . . . . . . . . . . . . . 76
3.5 Electromagnetic Interference (EMI) characteristics (cut1) 77
3.6 Electrostatic discharge (ESD) characteristics . . . . . . . 78
3.7 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.8 Voltage regulator electrical characteristics . . . . . . . . . 79
3.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 82
3.10 Supply current characteristics (cut2) . . . . . . . . . . . . . . 83
3.11 Temperature sensor electrical characteristics . . . . . . . 84
3.12 Main oscillator electrical characteristics . . . . . . . . . . . 84
3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 86
3.14 16 MHz RC oscillator electrical characteristics . . . . . . 88
3.15 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 88
3.15.1 Input Impedance and ADC Accuracy . . . . . . . . 88
3.16 Flash memory electrical characteristics . . . . . . . . . . . 93
3.17 SWG electrical characteristics. . . . . . . . . . . . . . . . . . . 94
3.18 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.18.1 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 94
3.19 Reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.19.1 Reset sequence duration . . . . . . . . . . . . . . . . . 96
3.19.2 Reset sequence description. . . . . . . . . . . . . . . 96
3.19.3 Reset sequence trigger mapping . . . . . . . . . . . 98
3.19.4 Reset sequence — start condition . . . . . . . . . 100
3.19.5 External watchdog window. . . . . . . . . . . . . . . 101
3.20 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . 101
3.20.1 RESET pin characteristics . . . . . . . . . . . . . . . 102
3.20.2 WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . 103
3.20.3 IEEE 1149.1 JTAG interface timing . . . . . . . . 103
3.20.4 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.20.5 External interrupt timing (IRQ pin) . . . . . . . . . 107
3.20.6 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 113
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 118
(FMPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5.15 Main Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.16 Internal Reference Clock (RC) Oscillator. . . . . .13
1.5.17 Clock, Reset, Power Mode, and Test Control
Modules (MC_CGM, MC_RGM, MC_PCU, and
MC_ME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.18 Periodic Interrupt Timer Module (PIT) . . . . . . . .13
1.5.19 System Timer Module (STM). . . . . . . . . . . . . . .14
1.5.20 Software Watchdog Timer (SWT) . . . . . . . . . . .14
1.5.21 Fault Collection and Control Unit (FCCU) . . . . .14
1.5.22 System Integration Unit Lite (SIUL) . . . . . . . . . .14
1.5.23 Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . .15
1.5.24 Boot Assist Module (BAM). . . . . . . . . . . . . . . . .15
1.5.25 System Status and Configuration Module (SSCM)15
1.5.26 Controller Area Network Module (CAN) . . . . . .15
1.5.27 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.28 Serial Communication Interface Module (UART)16
1.5.29 Serial Peripheral Interface (SPI) . . . . . . . . . . . .17
1.5.30 Pulse Width Modulator (PWM) . . . . . . . . . . . . .17
1.5.31 eTimer Module. . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5.32 Sine Wave Generator (SWG) . . . . . . . . . . . . . .19
1.5.33 Analog-to-Digital Converter Module (ADC) . . . .19
1.5.34 Junction Temperature Sensor . . . . . . . . . . . . . .20
1.5.35 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . .20
1.5.36 Cyclic Redundancy Checker (CRC) Unit. . . . . .20
1.5.37 Redundancy Control and Checker Unit (RCCU)21
1.5.38 Voltage Regulator / Power Management Unit (PMU)21
1.5.39 Built-In Self-Test (BIST) Capability . . . . . . . . . .21
4
5
6
PXS20 Microcontroller Data Sheet, Rev. 1
2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
1
Introduction
1.1
Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams for the PXS20 series of
microcontroller units (MCUs). For functional characteristics, see the PXS20 Microcontroller Reference Manual. For use of the
PXS20 in a fail-safe system according to safety standard IEC 61508, see the Safety Application Guide for MPC5643L.
The PXS20 MCU series is available in two silicon versions, or “cuts”. These are referred to as “cut1” and “cut2” throughout
this document. Functional differences between the two cuts are clearly identified with the labels “cut1” and “cut2”.
1.2
Description
The PXS20 series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain
enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital
signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital
converter, Controller Area Network, and an enhanced modular input-output system.
The PXS20 family of 32-bit microcontrollers is the latest achievement in integrated safety controllers. The advanced and
cost-efficient host processor core of the PXS20 family complies with the Power Architecture embedded category. It operates at
speeds as high as 120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the
available development infrastructure of current Power Architecture devices and is supported with software drivers, operating
systems and configuration code to assist with users’ implementations.
1.3
Device comparison
Table 1. PXS20 Family Feature Set
Feature
PXS20
CPU
Type
2 × e200z4
(in lock-step or decoupled operation)
Architecture
Harvard
Execution speed
DMIPS intrinsic performance
SIMD (DSP + FPU)
MMU
0 – 120 MHz (+2% FM)
> 240 MIPS
Yes
16 entry
Instruction set PPC
Instruction set VLE
Instruction cache
MPU-16 regions
Yes
Yes
4 KB, EDC
Yes, replicated module
Yes
Semaphore unit (SEMA4)
Core bus
Buses
AHB, 32-bit address, 64-bit data
32-bit address, 32-bit data
Internal periphery bus
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
3
Preliminary—Subject to Change Without Notice
Introduction
Table 1. PXS20 Family Feature Set (continued)
Feature
PXS20
Crossbar
Memory
Master × slave ports
Lock Step Mode: 4 × 3
Decoupled Parallel Mode: 6 × 3
Code/data flash
1 MB, ECC, RWW
128 KB, ECC
Static RAM (SRAM)
Interrupt controller (INTC)
Periodic Interrupt Timer (PIT)
System timer module (STM)
Software watchdog timer (SWT)
eDMA
Modules
16 interrupt levels, replicated module
1 × 4 channels
1 × 4 channels, replicated module
Yes, replicated module
16 channels, replicated module
1 × 64 message buffers, dual channel
2 × 32 message buffers
2
FlexRay
CAN
UART with DMA support
Clock out
Yes
Fault control & collection unit (FCCU)
Cross triggering unit (CTU)
eTimer
Yes
Yes
3 × 6 channels
PWM
2 Module 4 × (2 + 1) channels
Analog-to-digital converter (ADC)
2 × 12-bit ADC, 16 channels per ADC
(3 internal, 4 shared and 9 external)
Modules
(cont.)
Sine-wave generator (SWG)
32 point
Serial peripheral interface (SPI)
3 × SPI
as many as 8 chip selects
Cyclic redundancy checker (CRC) unit
Junction temperature sensor (TSENS)
Digital I/Os
Yes
Yes, replicated module
16
Supply
Device power supply
3.3 V with integrated bypassable ballast transistor
External ballast transistor not needed for bare die
Analog reference voltage
3.0 V – 3.6 V and 4.5 V – 5.5 V
Clocking
Frequency-modulated phase-locked loop (FMPLL)
2
Internal RC oscillator
External crystal oscillator
Nexus
16 MHz
4 – 40 MHz
Level 3+
Debug
Packages
Type
144 LQFP
257 MAPBGA
PXS20 Microcontroller Data Sheet, Rev. 1
4
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
Table 1. PXS20 Family Feature Set (continued)
Feature
PXS20
Temperature
Temperature range (junction)
–40 to 150 °C
–40 to 125 °C
Ambient temperature range using external ballast
transistor (LQFP)
Ambient temperature range using external ballast
transistor (BGA)
TBD
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
5
Preliminary—Subject to Change Without Notice
Introduction
1.4
Block diagram
Figure 1 shows a top-level block diagram of the PXS20 device.
PXS20 Block Diagram
Debug
PMU
SWT
PMU
SWT
e200z4
e200z4
JTAG
Nexus
FPU
VLE
SPE2
VLE
ECSM
STM
ECSM
STM
FlexRay™
MMU
MMU
Cache
INTC
eDMA
INTC
eDMA
Redundancy
Checker
I-Cache
Crossbar Switch (XBAR)
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
Memory Protection Unit (MPU)
PBRIDGE
Redundancy Checker
1 MB Flash (ECC)
Redundancy Checker
128 KB SRAM (ECC)
PBRIDGE
Redundancy Checker
Figure 1. PXS20 block diagram
PXS20 Microcontroller Data Sheet, Rev. 1
6
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
ADC
BAM
CAN
CMU
CRC
CTU
– Analog-to-digital converter
– Boot assist module
– Controller area network controller
– Clock monitoring unit
– Cyclic redundancy check unit
– Cross Triggering Unit
– Error correction code
– Error correction status module
– Enhanced direct memory access controller
– Fault collection and control unit
– Frequency modulated phase locked loop
– Interrupt controller
PMU
PWM
RC
– Power management unit
– Pulse width modulator module
– Redundancy checker
– Real time clock
– Semaphore unit
– System integration unit lite
– Serial peripherals interface controller
– System status and configuration module
– System timer module
– Sine wave generator
– Software watchdog timer
– Temperature sensor
RTC
SEMA4
SIUL
SPI
SSCM
STM
SWG
SWT
TSENS
ECC
ECSM
eDMA
FCCU
FMPLL
INTC
IRCOSC – Internal RC oscillator
UART/LIN – Universal asynchronous receiver/transmitter/
JTAG
MC
– Joint Test Action Group interface
– Mode entry, clock, reset, & power
local interconnect network
– Wakeup unit
– Crystal oscillator
WKPU
XOSC
PBRIDGE – Peripheral I/O bridge
PIT – Periodic interrupt timer
Figure 2. PXS20 block diagram (continued)
1.5
Feature details
1.5.1
High-Performance e200z4d Core
®
The e200z4d Power Architecture core provides the following features:
•
•
2 independent execution units, both supporting fixed-point and floating-point operations
®
Dual issue 32-bit Power Architecture technology compliant
— 5-stage pipeline (IF, DEC, EX1, EX2, WB)
— In-order execution and instruction retirement
®
•
Full support for Power Architecture instruction set and Variable Length Encoding (VLE)
— Mix of classic 32-bit and 16-bit instruction allowed
— Optimization of code size possible
Thirty-two 64-bit general purpose registers (GPRs)
Harvard bus (32-bit address, 64-bit data)
— I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return
— D-Bus interface capable of two transactions outstanding to fill AHB pipe
I-cache and I-cache controller
•
•
•
— 4 KB, 256-bit cache line (programmable for 2- or 4-way)
No data cache
•
•
•
•
•
•
•
16-entry MMU
8-entry branch table buffer
Branch look-ahead instruction buffer to accelerate branching
Dedicated branch address calculator
3 cycles worst case for missed branch
Load/store unit
— Fully pipelined
— Single-cycle load latency
— Big- and little-endian modes supported
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
7
Preliminary—Subject to Change Without Notice
Introduction
— Misaligned access support
— Single stall cycle on load to use
•
•
•
Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication
4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine cycles)
Single precision floating-point unit
— 1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication
— Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division
— Special square root and min/max function implemented
Signal processing support: APU-SPE 1.1
•
— Support for vectorized mode: as many as two floating-point instructions per clock
Vectored interrupt support
•
•
•
Reservation instruction to support read-modify-write constructs
Extensive system development and tracing support via Nexus debug port
1.5.2
Crossbar Switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The
crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers
must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master
port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting
that slave port are stalled until the higher priority master completes its transactions.
The crossbar provides the following features:
•
4 masters and 3 slaves supported per each replicated crossbar
— Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D
access (2 masters), one eDMA, one FlexRay
— Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum
flexibility to handle Instruction and Data array, one redundant SRAM controller with 1 slave port each and 1
redundant peripheral bus bridge
•
•
32-bit address bus and 64-bit data bus
Programmable arbitration priority
— Requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method,
based upon the ID of the last master to be granted access or a priority order can be assigned by software at
application run time
•
Temporary dynamic priority elevation of masters
The XBAR is replicated for each processor.
1.5.3
Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA, FlexRay, CPU) can be
assigned different access rights to each region.
•
•
16-region MPU with concurrent checks against each master access
32-byte granularity for protected address region
The memory protection unit is replicated for each processor.
PXS20 Microcontroller Data Sheet, Rev. 1
8
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
1.5.4
Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is used to minimize the overall block size.
The eDMA module provides the following features:
•
•
•
•
•
•
•
•
•
16 channels supporting 8-, 16-, and 32-bit value single or block transfers
Support variable sized queues and circular buffered queue
Source and destination address registers independently configured to post-increment or stay constant
Support major and minor loop offset
Support minor and major loop done signals
DMA task initiated either by hardware requestor or by software
Each DMA task can optionally generate an interrupt at completion and retirement of the task
Signal to indicate closure of last minor loop
Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processor.
1.5.5
On-Chip Flash Memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile memory (NVM) can be used for instruction
storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory
array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait
state response at 120 MHz.
The flash memory module provides the following features
•
•
•
•
•
1 MB of flash memory in unique multi-partitioned hard macro
Sectorization: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB
EEPROM emulation (in software) within same module but on different partition
16 KB test sector and 16 KB shadow sector for test, censorship device and user option bits
Wait states:
— 3 wait states at 120 MHz
— 2 wait states at 80 MHz
— 1 wait state at 60 MHz
•
•
•
Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)
Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations
1-bit error correction, 2-bit error detection
1.5.6
On-Chip SRAM with ECC
The PXS20 SRAM provides a general-purpose single port memory.
ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic
coverage including the array internal address decoder.
The SRAM module provides the following features:
•
System SRAM: 128 KB
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
9
Preliminary—Subject to Change Without Notice
Introduction
•
ECC on 32-bit word (syndrome of 7 bits)
— ECC covers SRAM bus address
1-bit error correction, 2-bit error detection
Wait states:
•
•
— 1 wait state at 120 MHz
— 0 wait states at 80 MHz and 60 MHz
1.5.7
Platform Flash Memory Controller
The following list summarizes the key features of the flash memory controller:
•
Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within the 32-bit container
are supported. Only aligned word writes are supported.
•
•
Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.
Code flash (bank0) interface provides configurable read buffering and page prefetch support.
— Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized
flash access.
•
•
Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a
least-recently-used replacement algorithm to maximize performance.
Data flash (bank1) interface includes a 128-bit register to temporarily hold a single flash page. This logic supports
single-cycle read responses (0 AHB data-phase wait states) for accesses that hit in the holding register.
— No prefetch support is provided for this bank.
•
•
Programmable response for read-while-write sequences including support for stall-while-write, optional stall
notification interrupt, optional flash operation abort , and optional abort notification interrupt.
Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of
platforms and frequencies.
•
•
•
Support of address-based read access timing for emulation of other memory types.
Support for reporting of single- and multi-bit error events.
Typical operating configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.5.8
Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform SRAM array controller, with integrated error detection and correction.
The main features of the SRAMC provide connectivity for the following interfaces:
•
•
•
XBAR Slave Port (64-bit data path)
ECSM (ECC Error Reporting, error injection and configuration)
SRAM array
The following functions are implemented:
•
•
•
ECC encoding (32-bit boundary for data and complete address bus)
ECC decoding (32-bit boundary and entire address)
Address translation from the AHB protocol on the XBAR to the SRAM array
The platform SRAM controller is replicated for each processor.
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Introduction
1.5.9
Memory Subsystem Access Time
Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower
memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the
slave being accessed is not parked on the requesting master in the crossbar.
Table 2 shows the number of additional data phase wait states required for a range of memory accesses.
Table 2. Platform Memory Access Time Summary
Data phase
wait states
AHB transfer
Description
e200z4d instruction fetch
e200z4d instruction fetch
0
3
Flash memory prefetch buffer hit (page hit)
Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
e200z4d data read
e200z4d data write
e200z4d data write
e200z4d data write
0–1
0
SRAM read
SRAM 32-bit write
0
SRAM 64-bit write (executed as 2 x 32-bit writes)
0–2
SRAM 8-,16-bit write
(Read-modify-Write for ECC)
e200z4d flash memory read
e200z4d flash memory read
0
3
Flash memory prefetch buffer hit (page hit)
Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
of program flash memory controller arbitration)
1.5.10 Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM).
It does not implement the actual ECC calculation. A detected error (double error for flash memory or SRAM) is also reported
to the FCCU. The following errors and indications are reported into the ECSM dedicated registers:
•
•
•
•
ECC error status and configuration for flash memory and SRAM
ECC error reporting for flash memory
ECC error reporting for SRAM
ECC error injection for SRAM
1.5.11 Peripheral Bridge (PBRIDGE)
The PBRIDGE implements the following features:
•
•
•
•
•
Duplicated periphery
Master access right per peripheral (per master: read access enable; write access enable)
Write buffering for peripherals
Checker applied on PBRIDGE output toward periphery
Byte endianess swap capability
1.5.12 Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time
systems.
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Introduction
For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can
be raised temporarily so that all tasks which share the resource can not preempt each other.
The INTC provides the following features:
•
•
•
•
Duplicated periphery
Unique 9-bit vector per interrupt source
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Priority elevation for shared resource
The INTC is replicated for each processor.
1.5.13 System Clocks and Clock Generation
The following list summarizes the system clock and clock generation on this device:
•
•
•
•
•
Lock status continuously monitored by lock detect circuitry
Loss-of-clock (LOC) detection for reference and feedback clocks
On-chip loop filter (for improved electromagnetic interference performance and fewer external components required)
Programmable output clock divider of system clock (1, 2, 4, 8)
PWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock
(with max frequency 120 MHz)
•
•
On-chip crystal oscillator with automatic level control
Dedicated internal 16 MHz internal RC oscillator for rapid start-up
— Supports automated frequency trimming by hardware during device startup and by user application
Auxiliary clock domain for motor control periphery (PWM, eTimer, CTU, ADC, and SWG)
•
1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL)
Each device has two FMPLLs.
Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock.
Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor,
output clock divider ratio are all software configurable. The FMPLLs have the following major features:
•
•
•
Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)
Voltage controlled oscillator (VCO) range: 256–512 MHz
Frequency modulation via software control to reduce and control emission peaks
— Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register
— Modulation frequency: triangular modulation with 25 kHz nominal rate
Option to switch modulation on and off via software interface
Reduced frequency divider (RFD) for reduced frequency operation without re-lock
3 modes of operation
•
•
•
— Bypass mode
— Normal FMPLL mode with crystal reference (default)
— Normal FMPLL mode with external reference
•
Lock monitor circuitry with lock status
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Introduction
•
•
•
•
Loss-of-lock detection for reference and feedback clocks
Self-clocked mode (SCM) operation
On-chip loop filter
Auxiliary FMPLL
— Used for FlexRay due to precise symbol rate requirement by the protocol
— Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies
of operation for PWM and timers and jitter-free control
— Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in
electric motor control loop
— Allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than
the system to ensure higher resolution
1.5.15 Main Oscillator
The main oscillator provides these features:
•
•
•
•
Input frequency range 4–40 MHz
Crystal input mode
External reference clock (3.3 V) input mode
FMPLL reference
1.5.16 Internal Reference Clock (RC) Oscillator
The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap
reference voltage. The RC oscillator is the device safe clock.
The RC oscillator provides these features:
•
•
•
Nominal frequency 16 MHz
±5% variation over voltage and temperature after process trim
Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the
FMPLL
•
RC oscillator is used as the default system clock during startup and can be used as back-up input source of FMPLL(s)
in case XOSC fails
1.5.17 Clock, Reset, Power Mode, and Test Control Modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME)
These modules provide the following:
•
•
•
•
Clock gating and clock distribution control
Halt, stop mode control
Flexible configurable system and auxiliary clock dividers
Various execution modes
— Reset, Idle, Test, Safe
— Various RUN modes with software selectable powered modules
— No stand-by mode implemented (no internal switchable power domains)
1.5.18 Periodic Interrupt Timer Module (PIT)
The PIT module implements the following features:
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Introduction
•
•
•
4 general purpose interrupt timers
32-bit counter resolution
Can be used for software tick or DMA trigger operation
1.5.19 System Timer Module (STM)
The STM implements the following features:
•
Up-counter with 4 output compare registers
The STM is replicated for each processor.
1.5.20 Software Watchdog Timer (SWT)
This module implements the following features:
•
•
•
•
•
Fault tolerant output
Safe internal RC oscillator as reference clock
Windowed watchdog
Program flow control monitor with 16-bit pseudorandom key generation
Allows a high level of safety (SIL3 monitor)
The SWT module is replicated for each processor.
1.5.21 Fault Collection and Control Unit (FCCU)
The FCCU module has the following features:
•
•
•
•
Redundant collection of hardware checker results
Redundant collection of error information and latch of faults from critical modules on the device
Collection of self-test results
Configurable and graded fault control
— Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode entered)
— External reaction (failure is reported to the external/surrounding system via configurable output pins)
1.5.22 System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal
peripheral multiplexing, and system reset operation. The reset configuration block contains the external pin boot configuration
logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform
and discrete input/output control of the I/O pins of the MCU.
The SIU provides the following features:
•
Centralized pad control on a per-pin basis
— Pin function selection
— Configurable weak pull-up/down
— Configurable slew rate control (slow/medium/fast)
— Hysteresis on GPIO pins
— Configurable automatic safe mode pad control
Input filtering for external interrupts
•
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Introduction
1.5.23 Non-Maskable Interrupt (NMI)
The non-maskable interrupt with de-glitching filter supports high-priority core exceptions.
1.5.24 Boot Assist Module (BAM)
The BAM is a block of read-only memory with hard-coded content. The BAM program is executed only if serial booting mode
is selected via boot configuration pins.
The BAM provides the following features:
•
•
•
•
Enables booting via serial mode (CAN or LIN/UART)
Supports programmable 64-bit password protection for serial boot mode
Supports serial bootloading of either classic PowerPC Book E code (default) or Freescale VLE code
Automatic switch to serial boot mode if internal flash memory is blank or invalid
1.5.25 System Status and Configuration Module (SSCM)
The SSCM on this device features the following:
•
•
•
System configuration and status
Debug port status and debug port enable
Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half
Word
•
•
Sets up the MMU to allow user boot code to execute as either classic PowerPC Book E code (default) or as Freescale
VLE code out of flash memory
Triggering of device self-tests during reset phase of device boot
1.5.26 Controller Area Network Module (CAN)
The CAN module is a communication controller implementing the CAN protocol according to Bosch Specification version
2.0B. Although the CAN interface was designed to be used primarily as a vehicle networking bus, it is widely used in industrial
and other transport applications due to its robust operation, time determinism, cost effectiveness, and optional redundant
physical layer implementation.
The CAN module provides the following features:
•
Full implementation of the CAN protocol specification, version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— 0 to 8 bytes data length
— Programmable bit rate as fast as 1Mbit/s
•
•
•
•
•
•
•
•
•
•
32 message buffers of 0 to 8 bytes data length
Each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages
Programmable loop-back mode supporting self-test operation
3 programmable mask registers
Programmable transmit-first scheme: lowest ID or lowest buffer number
Time stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
High immunity to EMI
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Introduction
•
•
Short latency time due to an arbitration scheme for high-priority messages
Transmit features
— Supports configuration of multiple mailboxes to form message queues of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
Receive features
•
•
— Individual programmable filters for each mailbox
— 8 mailboxes configurable as a 6-entry receive FIFO
— 8 programmable acceptance filters for receive FIFO
Programmable clock source
— System clock
— Direct oscillator clock to avoid FMPLL jitter
1.5.27 FlexRay
The FlexRay module provides the following features:
•
•
•
•
•
•
•
•
•
Full implementation of FlexRay Protocol Specification 2.1 Rev. A
64 configurable message buffers can be handled
Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
Message buffers configurable as transmit or receive
Message buffer size configurable
Message filtering for all message buffers based on Frame ID, cycle count, and message ID
Programmable acceptance filters for receive FIFO
Message buffer header, status, and payload data stored in system memory (SRAM)
Internal FlexRay memories have error detection and correction
1.5.28 Serial Communication Interface Module (UART)
The UART module with DMA support on this device features the following:
•
UART features:
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
–
Parity, noise and framing errors
— Interrupt driven operation with 4 interrupts sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— 2 receiver wake-up methods
•
LIN features:
— Autonomous LIN frame handling
— Message buffer to store identifier and up to eight data bytes
— Supports message length of up to 64 bytes
— Detection and flagging of LIN errors
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Introduction
— Sync field; Delimiter; ID parity; Bit, Framing; Checksum and Timeout errors
— Classic or extended checksum calculation
— Configurable Break duration of up to 36-bit times
— Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features
–
–
–
Loop back
Self Test
LIN bus stuck dominant detection
— Interrupt driven operation with 16 interrupt sources
— LIN slave mode features
–
–
–
Autonomous LIN header handling
Autonomous LIN response handling
Discarding of irrelevant LIN responses using up to 16 ID filters
1.5.29 Serial Peripheral Interface (SPI)
The SPI modules provide a synchronous serial interface for communication between the PXS20 and external devices.
A SPI module provides these features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
Programmable data frames from 4 to 16 bits
As many as 8 chip select lines available, depending on package and pin multiplexing
4 clock and transfer attributes registers
Chip select strobe available as alternate function on one of the chip select pins for de-glitching
FIFOs for buffering as many as 5 transfers on the transmit and receive side
Queueing operation possible through use of the eDMA
General purpose I/O functionality on pins when not used for SPI
1.5.30 Pulse Width Modulator (PWM)
The PWM module contains four PWM channels, each of which is configured to control a single half-bridge power stage. Two
modules are included on 257 MAPBGA devices; on the 144 LQFP package, only one module is present. Additionally, four
fault input channels are provided per PWM module.
This PWM is capable of controlling most motor types, including:
•
•
•
•
•
AC induction motors (ACIM)
Permanent Magnet AC motors (PMAC)
Brushless (BLDC) and brush DC motors (BDC)
Switched (SRM) and variable reluctance motors (VRM)
Stepper motors
A PWM module implements the following features:
•
16 bits of resolution for center, edge aligned, and asymmetrical PWMs
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Introduction
•
Maximum operating frequency as high as 120 MHz
— Clock source not modulated and independent from system clock (generated via secondary FMPLL)
Fine granularity control for enhanced resolution of the PWM period
PWM outputs can operate as complementary pairs or independent channels
Ability to accept signed numbers for PWM generation
Independent control of both edges of each PWM output
Synchronization to external hardware or other PWM supported
Double buffered PWM registers
•
•
•
•
•
•
— Integral reload rates from 1 to 16
— Half cycle reload capability
•
•
•
•
•
•
•
•
•
•
•
•
•
Multiple ADC trigger events can be generated per PWM cycle via hardware
Fault inputs can be assigned to control multiple PWM outputs
Programmable filters for fault inputs
Independently programmable PWM output polarity
Independent top and bottom deadtime insertion
Each complementary pair can operate with its own PWM frequency and deadtime values
Individual software control for each PWM output
All outputs can be forced to a value simultaneously
PWMX pin can optionally output a third signal from each channel
Channels not used for PWM generation can be used for buffered output compare functions
Channels not used for PWM generation can be used for input capture functions
Enhanced dual edge capture functionality
Option to supply the source for each complementary PWM signal pair from any of the following:
— External digital pin
— Internal timer channel
— External ADC input, taking into account values set in ADC high- and low-limit registers
DMA support
•
1.5.31 eTimer Module
The PXS20 provides three eTimer modules on the 257 MAPBGA device, and two eTimer modules on the 144 LQFP package.
Six 16-bit general purpose up/down timer/counters per module are implemented with the following features:
•
•
Maximum clock frequency of 120 MHz
Individual channel capability
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
Maximum count rate
•
— Equals peripheral clock divided by 2 for external event counting
— Equals peripheral clock for internal clock counting
Cascadeable counters
•
•
Programmable count modulo
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Introduction
•
•
•
•
•
•
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Preloadable counters
Pins available as GPIO when timer functionality not in use
DMA support
1.5.32 Sine Wave Generator (SWG)
A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver).
•
•
Frequency range from 1 kHz to 50 kHz
Sine wave amplitude from 0.47 V to 2.26 V
1.5.33 Analog-to-Digital Converter Module (ADC)
The ADC module features include:
Analog part:
•
2 on-chip ADCs
— 12-bit resolution SAR architecture
— A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels)
— One channel dedicated to each T-sensor to enable temperature reading during application
— Separated reference for each ADC
— Shared analog supply voltage for both ADCs
— One sample and hold unit per ADC
— Adjustable sampling and conversion time
Digital part:
•
4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in
the appropriate ADC result location
•
•
2 modes of operation: Motor Control Mode or Regular Mode
Regular mode features
— Register based interface with the CPU: one result register per channel
— ADC state machine managing three request flows: regular command, hardware injected command, software
injected command
— Selectable priority between software and hardware injected commands
— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)
— DMA compatible interface
•
•
Motor control mode features
— Triggered mode only
— 4 independent result queues (1 16 entries, 2 8 entries, 1 4 entries)
— Result alignment circuitry (left justified; right justified)
— 32-bit read mode allows to have channel ID on one of the 16-bit parts
— DMA compatible interfaces
Built-in self-test features triggered by software
PXS20 Microcontroller Data Sheet, Rev. 1
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Introduction
1.5.34 Junction Temperature Sensor
The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device
junction temperature.
The key parameters of the junction temperature sensor include:
•
•
Nominal temperature range from –40 to 150 °C
Software temperature alarm via analog ADC comparator possible
1.5.35 Cross Triggering Unit (CTU)
The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without
CPU load during the PWM period and with minimized CPU load for dynamic configuration.
The CTU implements the following features:
•
•
•
•
•
•
•
•
•
•
Cross triggering between ADC, PWM, eTimer, and external pins
Double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers
Maximum operating frequency less than or equal to 120 MHz
Trigger generation unit configurable in sequential mode or in triggered mode
Trigger delay unit to compensate the delay of external low pass filter
Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation
Double buffered ADC command list pointers to minimize ADC-trigger unit update
Double buffered ADC conversion command list with as many as 24 ADC commands
Each trigger capable of generating consecutive commands
ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling,
independent result queue selection
•
DMA support with safety features
1.5.36 Cyclic Redundancy Checker (CRC) Unit
The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to its input register.
The CRC unit has the following features:
•
3 sets of registers to allow 3 concurrent contexts with possibly different CRC computations, each with a selectable
polynomial and seed
•
Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores result in internal register.
The following standard CRC polynomials are implemented:
16
12
5
— x + x + x + 1 [16-bit CRC-CCITT]
32
26
23
22
16
12
11
10
8
7
5
4
2
— x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1
[32-bit CRC-ethernet(32)]
•
•
Key engine to be coupled with communication periphery where CRC application is added to allow implementation of
safe communication protocol
Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic
procedures
•
•
CRC unit connected as peripheral bus on internal peripheral bus
DMA support
1.5.37 Redundancy Control and Checker Unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features:
PXS20 Microcontroller Data Sheet, Rev. 1
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Introduction
•
•
Duplicated module to guarantee highest possible diagnostic coverage (check of checker)
Multiple times replicated IPs are used as checkers on the SoR outputs
1.5.38 Voltage Regulator / Power Management Unit (PMU)
The on-chip voltage regulator module provides the following features:
•
•
Single external rail required
Single high supply required: nominal 3.3 V for packaged option
— Packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but
can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower
frequency of operation)
•
•
All I/Os are at same voltage as external supply (3.3 V nominal)
Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal
operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing
feature)
1.5.39 Built-In Self-Test (BIST) Capability
This device includes the following protection against latent faults:
•
•
•
•
Boot-time Memory Built-In Self-Test (MBIST)
Boot-time scan-based Logic Built-In Self-Test (LBIST)
Run-time ADC Built-In Self-Test (BIST)
Run-time Built-In Self Test of LVDs
1.5.40 IEEE 1149.1 JTAG Controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic
when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block
is compliant with the IEEE standard.
The JTAG controller provides the following features:
•
IEEE Test Access Port (TAP) interface with 5 pins:
— TDI
— TMS
— TCK
— TDO
— JCOMP
•
•
Selectable modes of operation include JTAGC/debug or normal system operation
5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS
— IDCODE
— EXTEST
— SAMPLE
— SAMPLE/PRELOAD
•
•
3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the
boundary scan register is parameterized to support a variety of boundary scan chain lengths.
TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
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Introduction
1.5.41 Nexus Port Controller (NPC)
The NPC module provides real-time development support capabilities for this device in compliance with the IEEE-ISTO
5001-2008 standard. This development support is supplied for MCUs without requiring external address and data pins for
internal visibility.
The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO
5001-2008 Class 3+, including selected features from Class 4 standard.
The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the
®
MCUs internal memory map and access to the Power Architecture internal registers during halt. The Nexus interface also
supports a JTAG only mode using only the JTAG pins. The following features are implemented:
•
•
•
•
•
Full and reduced port modes
MCKO (message clock out) pin
4 or 12 MDO (message data out) pins
2 MSEO (message start/end out) pins
EVTO (event out) pin
1
— Auxiliary input port
•
•
EVTI (event in) pin
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
— Supports JTAG mode
•
Host processor (e200) development support features
— Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool
to trace reads or writes, or both, to selected internal memory resources.
— Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility
of which process ID or operating system task is activated. An ownership trace message is transmitted when a
new process/task is activated, allowing development tools to trace ownership flow.
— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities
(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what
transpires between the discontinuities. Thus, static code may be traced.
— Watchpoint messaging (WPM) via the auxiliary port
— Watchpoint trigger enable of program and/or data trace messaging
— Data tracing of instruction fetches via private opcodes
1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.
PXS20 Microcontroller Data Sheet, Rev. 1
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Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
2
Package pinouts and signal descriptions
2.1
Package pinouts
Figure 3 shows the PXS20 in the 144 LQFP package.
NMI
A[6]
D[1]
F[4]
1
2
3
4
5
6
7
8
A[4]
VPP_TEST
F[12]
D[14]
G[3]
C[14]
G[2]
C[13]
G[4]
108
107
106
105
104
103
102
101
100
F[5]
VDD_HV_IO
VSS_HV_IO
F[6]
MDO0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
99
D[12]
G[6]
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
VSS_LV_COR
VDD_LV_COR
A[3]
VDD_HV_IO
VSS_HV_IO
B[4]
TCK
TMS
B[5]
G[5]
A[2]
G[7]
C[12]
G[8]
C[11]
G[9]
D[11]
G[10]
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
F[7]
144 LQFP package
F[8]
VDD_HV_IO
VSS_HV_IO
F[9]
F[10]
F[11]
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[10]
G[11]
A[1]
A[0]
D[6]
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
Figure 3. PXS20 144 LQFP pinout (top view)
Figure 4 shows the PXS20 in the 257 MAPBGA package.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
23
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
H[2]
A
B
C
D
E
F
V
V
V
H[0]
G[14]
D[3]
C[15]
V
A[12]
H[10]
H[14]
A[10]
B[2]
C[10]
V
V
SS
SS
DD_HV
DD_HV
SS
SS
A[14]
V
V
B[6]
F[3]
D[2]
A[9]
D[4]
D[0]
V
H[12]
E[15]
E[14]
I[1]
B[3]
F[14]
F[15]
F[13]
B[1]
B[0]
V
V
SS
SS
SS
DD_HV
A[4]
SS
FCCU_
F[1]
1
V
NC
V
A[13]
V
V
I[0]
JCOMP H[11]
V
V
F[12]
G[3]
I[3]
DD_HV
SS
DD_HV
DD_HV
SS
PP
F[5]
F[4]
A[15]
D[1]
A[7]
C[5]
C[4]
C[6]
NMI
A[8]
A[6]
A[5]
V
V
F[0]
V
V
A[11]
NC
E[13]
V
D[14]
G[2]
I[2]
SS
DD_LV
DD_HV
SS
DD_HV
_TEST
MDO0
H[1]
F[6]
NC
C[14]
G[12]
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
C[13]
H[13]
G[4]
G[6]
H[6]
H[15]
A[3]
B[4]
H[5]
G[5]
G[7]
G[9]
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
G
H
J
H[3]
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
D[12]
H[9]
DD_HV
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
G[13]
F[7]
V
V
V
V
DD_HV
SS
SS
DD_HV
G[15]
F[8]
V
V
V
V
V
SS
DD_HV
See
DD_HV
DD_LV
DD_HV
K
L
F[9]
C[7]
NC
H[8]
H[7]
H[4]
TMS
A[2]
2
note
F[10]
F[11]
D[9]
D[8]
D[5]
D[6]
NC
NC
NC
TCK
B[5]
M
N
P
R
T
V
V
V
V
V
V
V
DD_LV
C[11]
NC
DD_HV
DD_HV
DD_LV
DD_LV
DD_LV
DD_LV
V
SS_LV_
PLL
XTAL
V
C[12]
G[10]
SS
V
DD_LV_
PLL
V
RESET
V
V
B[8]
NC
V
V
B[14]
B[15]
E[10]
V
V
V
G[8]
D[11]
SS
DD_LV
SS
SS
DD_HV
DD_LV
C[0]
SS
DD_HV
FCCU
_F[0]
V
V
REFP_
REFP_
HV_AD1
EXTAL
V
D[7]
C[1]
B[7]
E[6]
E[7]
B[10]
B[11]
B[13]
E[9]
BCTRL
E[0]
A[1]
V
SS
SS
HV_AD0
V
V
REFN_
REFN_
HV_AD1
V
V
V
NC
E[5]
E[12]
A[0]
D[10]
V
V
V
SS
DD_HV
DD_HV
SS
HV_AD0
U
V
E[4]
4
C[2]
5
E[2]
6
B[9]
B[12]
8
V
V
E[11]
11
NC
12
NC
13
V
G[11]
15
V
SS
SS
SS
DD_HV
SS
DD_HV
SS
NC
3
1
2
7
9
10
14
16
17
1
2
NC = Not connected (the pin is physically not connected to anything on the device)
Pin K3 is NC on cut1 and RDY on cut2/3.
Figure 4. PXS20 257 MAPBGA pinout (top view)
Table 3 and Table 4 provide the pin function summaries for the 144-pin and 257-pin packages, respectively, listing all the
signals multiplexed to each pin.
PXS20 Microcontroller Data Sheet, Rev. 1
24
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary
Pin #
Port/function
Peripheral
Output function
Input function
1
2
NMI
A[6]
—
GPIO[6]
SCK
SIUL
DSPI_1
SIUL
GPIO[6]
SCK
—
EIRQ[6]
GPIO[49]
ETC[2]
—
3
D[1]
SIUL
GPIO[49]
ETC[2]
EXT_TGR
—
eTimer_1
CTU_0
FlexRay
SIUL
CA_RX
GPIO[84]
—
4
5
F[4]
F[5]
GPIO[84]
MDO[3]
GPIO[85]
MDO[2]
—
NPC
SIUL
GPIO[85]
—
NPC
6
7
8
VDD_HV_IO
VSS_HV_IO
F[6]
—
SIUL
NPC
GPIO[86]
MDO[1]
—
GPIO[86]
—
9
MDO0
A[7]
10
SIUL
DSPI_1
SIUL
GPIO[7]
SOUT
—
GPIO[7]
—
EIRQ[7]
GPIO[36]
CS0
11
C[4]
SIUL
GPIO[36]
CS0
DSPI_0
FlexPWM_0
SSCM
SIUL
X[1]
X[1]
DEBUG[4]
—
—
EIRQ[22]
GPIO[8]
SIN
12
13
A[8]
C[5]
SIUL
GPIO[8]
—
DSPI_1
SIUL
—
EIRQ[8]
GPIO[37]
SCK
SIUL
GPIO[37]
SCK
DSPI_0
SSCM
FlexPWM_0
SIUL
DEBUG[5]
—
—
FAULT[3]
EIRQ[23]
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
25
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
14
A[5]
SIUL
DSPI_1
eTimer_1
DSPI_0
SIUL
GPIO[5]
CS0
GPIO[5]
CS0
ETC[5]
CS7
ETC[5]
—
—
EIRQ[5]
GPIO[39]
A[1]
15
C[7]
SIUL
GPIO[39]
A[1]
FlexPWM_0
SSCM
DEBUG[7]
—
—
DSPI_0
SIN
16
17
18
19
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
F[7]
—
—
—
SIUL
NPC
SIUL
NPC
GPIO[87]
MCKO
GPIO[88]
MSEO[1]
—
GPIO[87]
—
20
F[8]
GPIO[88]
—
21
22
23
VDD_HV_IO
VSS_HV_IO
F[9]
—
SIUL
NPC
GPIO[89]
MSEO[0]
GPIO[90]
EVTO
GPIO[91]
EVTI
GPIO[89]
—
24
25
26
F[10]
F[11]
D[9]
SIUL
GPIO[90]
—
NPC
SIUL
GPIO[91]
—
NPC
SIUL
GPIO[57]
X[0]
GPIO[57]
X[0]
FlexPWM_0
LINFlexD_1
TXD
—
27
28
29
30
31
VDD_HV_OSC
VSS_HV_OSC
XTALIN
—
—
—
XTALOUT
RESET
—
—
PXS20 Microcontroller Data Sheet, Rev. 1
26
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
32
D[8]
SIUL
DSPI_1
GPIO[56]
GPIO[56]
—
CS2
eTimer_1
DSPI_0
ETC[4]
ETC[4]
—
CS5
FlexPWM_0
SIUL
—
FAULT[3]
GPIO[53]
—
33
34
D[5]
D[6]
GPIO[53]
DSPI_0
CS3
FlexPWM_0
SIUL
—
FAULT[2]
GPIO[54]
—
GPIO[54]
DSPI_0
CS2
FlexPWM_0
FlexPWM_0
X[3]
X[3]
—
FAULT[1]
35
36
37
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
D[7]
—
—
SIUL
DSPI_1
DSPI_0
SWG
GPIO[55]
GPIO[55]
CS3
—
—
CS4
analog output
—
38
39
40
41
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
C[1]
FCCU
F[0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F[0]
SIUL
ADC_0
SIUL
GPIO[33]
AN[2]
42
43
E[4]
B[7]
GPIO[68]
AN[7]
ADC_0
SIUL
GPIO[23]
RXD
LINFlexD_0
ADC_0
SIUL
AN[0]
44
45
46
E[5]
C[2]
E[6]
GPIO[69]
AN[8]
ADC_0
SIUL
GPIO[34]
AN[3]
ADC_0
SIUL
GPIO[70]
AN[4]
ADC_0
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
27
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
47
B[8]
SIUL
eTimer_0
ADC_0
SIUL
—
—
—
—
—
—
—
—
—
—
—
GPIO[24]
ETC[5]
AN[1]
48
49
E[7]
E[2]
GPIO[71]
AN[6]
ADC_0
SIUL
GPIO[66]
AN[5]
ADC_0
50
51
52
VDD_HV_ADR0
VSS_HV_ADR0
B[9]
SIUL
GPIO[25]
AN[11]
ADC_0
ADC_1
53
54
55
B[10]
B[11]
B[12]
SIUL
—
—
GPIO[26]
AN[12]
ADC_0
ADC_1
SIUL
—
—
GPIO[27]
AN[13]
ADC_0
ADC_1
SIUL
—
—
GPIO[28]
AN[14]
ADC_0
ADC_1
56
57
58
59
60
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
B[13]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIUL
LINFlexD_1
ADC_1
SIUL
GPIO[29]
RXD
AN[0]
61
62
E[9]
GPIO[73]
AN[7]
ADC_1
SIUL
B[15]
GPIO[31]
EIRQ[20]
AN[2]
SIUL
ADC_1
SIUL
63
E[10]
GPIO[74]
AN[8]
ADC_1
PXS20 Microcontroller Data Sheet, Rev. 1
28
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
64
B[14]
SIUL
eTimer_0
SIUL
—
—
GPIO[30]
ETC[4]
EIRQ[19]
AN[1]
—
ADC_1
SIUL
—
65
66
67
68
E[11]
C[0]
—
GPIO[75]
AN[4]
ADC_1
SIUL
—
—
GPIO[32]
AN[3]
ADC_1
SIUL
—
E[12]
E[0]
—
GPIO[76]
AN[6]
ADC_1
SIUL
—
—
GPIO[64]
AN[5]
ADC_1
—
69
70
71
72
73
BCTRL
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
A[0]
—
—
—
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[0]
ETC[0]
SCK
—
GPIO[0]
ETC[0]
SCK
EIRQ[0]
GPIO[1]
ETC[1]
—
74
A[1]
SIUL
GPIO[1]
ETC[1]
SOUT
—
eTimer_0
DSPI_2
SIUL
EIRQ[1]
GPIO[107]
—
75
76
77
G[11]
D[10]
G[10]
SIUL
GPIO[107]
DBG3
—
FlexRay
FlexPWM_0
SIUL
FAULT[3]
GPIO[58]
A[0]
GPIO[58]
A[0]
—
FlexPWM_0
eTimer_0
SIUL
ETC[0]
GPIO[106]
—
GPIO[106]
DBG2
CS3
—
FlexRay
DSPI_2
FlexPWM_0
—
FAULT[2]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
29
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
78
D[11]
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[59]
B[0]
GPIO[59]
B[0]
—
ETC[1]
GPIO[105]
—
79
G[9]
GPIO[105]
DBG1
CS1
FlexRay
DSPI_1
FlexPWM_0
SIUL
—
—
FAULT[1]
EIRQ[29]
GPIO[43]
ETC[4]
—
—
80
81
C[11]
G[8]
SIUL
GPIO[43]
ETC[4]
CS2
eTimer_0
DSPI_2
SIUL
GPIO[104]
DBG0
CS1
GPIO[104]
—
FlexRay
DSPI_0
FlexPWM_0
SIUL
—
—
FAULT[0]
EIRQ[21]
GPIO[44]
ETC[5]
—
—
82
C[12]
SIUL
GPIO[44]
ETC[5]
CS3
eTimer_0
DSPI_2
SIUL
83
84
G[7]
A[2]
GPIO[103]
B[3]
GPIO[103]
B[3]
FlexPWM_0
SIUL
GPIO[2]
ETC[2]
A[3]
GPIO[2]
ETC[2]
A[3]
eTimer_0
FlexPWM_0
DSPI_2
MC_RGM
SIUL
—
SIN
—
ABS[0]
EIRQ[2]
GPIO[101]
X[3]
—
85
86
G[5]
B[5]
SIUL
GPIO[101]
X[3]
FlexPWM_0
DSPI_2
SIUL
CS3
—
GPIO[21]
—
GPIO[21]
TDI
JTAGC
87
88
TMS
TCK
—
—
PXS20 Microcontroller Data Sheet, Rev. 1
30
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
89
B[4]
SIUL
GPIO[20]
TDO
—
GPIO[20]
—
JTAGC
90
91
92
VSS_HV_IO
VDD_HV_IO
A[3]
—
SIUL
eTimer_0
DSPI_2
GPIO[3]
ETC[3]
CS0
GPIO[3]
ETC[3]
CS0
FlexPWM_0
MC_RGM
SIUL
B[3]
B[3]
—
ABS[2]
EIRQ[3]
—
93
94
95
96
97
98
VDD_LV_COR
VSS_LV_COR
VDD_HV_REG_1
VSS_HV_FLA
VDD_HV_FLA
G[6]
—
—
—
—
—
SIUL
FlexPWM_0
SIUL
GPIO[102]
A[3]
GPIO[102]
A[3]
99
D[12]
G[4]
GPIO[60]
X[1]
GPIO[60]
X[1]
FlexPWM_0
LINFlexD_1
SIUL
—
RXD
100
101
GPIO[100]
B[2]
GPIO[100]
B[2]
FlexPWM_0
eTimer_0
SIUL
—
ETC[5]
GPIO[45]
ETC[1]
EXT_IN
EXT_SYNC
GPIO[98]
X[2]
C[13]
GPIO[45]
ETC[1]
—
eTimer_1
CTU_0
FlexPWM_0
SIUL
—
102
103
G[2]
GPIO[98]
X[2]
FlexPWM_0
DSPI_1
CS1
—
C[14]
SIUL
GPIO[46]
ETC[2]
EXT_TGR
GPIO[46]
ETC[2]
—
eTimer_1
CTU_0
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
31
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
104
G[3]
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[99]
A[2]
GPIO[99]
A[2]
—
ETC[4]
GPIO[62]
B[1]
105
106
D[14]
F[12]
GPIO[62]
B[1]
FlexPWM_0
eTimer_0
SIUL
—
ETC[3]
GPIO[92]
ETC[3]
EIRQ[30]
GPIO[92]
ETC[3]
—
eTimer_1
SIUL
1
107
108
VPP_TEST
—
A[4]
SIUL
eTimer_1
DSPI_2
eTimer_0
MC_RGM
SIUL
GPIO[4]
ETC[0]
CS1
GPIO[4]
ETC[0]
—
ETC[4]
—
ETC[4]
FAB
—
EIRQ[4]
GPIO[16]
—
109
110
B[0]
B[1]
SIUL
GPIO[16]
TXD
FlexCAN_0
eTimer_1
SSCM
ETC[2]
DEBUG[0]
—
ETC[2]
—
SIUL
EIRQ[15]
GPIO[17]
ETC[3]
—
SIUL
GPIO[17]
ETC[3]
DEBUG[1]
—
eTimer_1
SSCM
FlexCAN_0
FlexCAN_1
SIUL
RXD
—
RXD
—
EIRQ[16]
GPIO[42]
—
111
112
C[10]
F[13]
SIUL
GPIO[42]
CS2
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
A[3]
A[3]
—
FAULT[1]
GPIO[93]
ETC[4]
EIRQ[31]
GPIO[93]
ETC[4]
—
eTimer_1
SIUL
PXS20 Microcontroller Data Sheet, Rev. 1
32
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
113
F[15]
SIUL
LINFlexD_1
SIUL
GPIO[95]
—
GPIO[95]
RXD
114
B[2]
GPIO[18]
TXD
GPIO[18]
—
LINFlexD_0
SSCM
DEBUG[2]
—
—
SIUL
EIRQ[17]
GPIO[94]
—
115
116
F[14]
B[3]
SIUL
GPIO[94]
TXD
LINFlexD_1
SIUL
GPIO[19]
DEBUG[3]
—
GPIO[19]
—
SSCM
LINFlexD_0
SIUL
RXD
117
118
E[13]
A[10]
GPIO[77]
ETC[5]
CS3
GPIO[77]
ETC[5]
—
eTimer_0
DSPI_2
SIUL
—
EIRQ[25]
GPIO[10]
CS0
SIUL
GPIO[10]
CS0
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
B[0]
B[0]
X[2]
X[2]
—
EIRQ[9]
GPIO[78]
ETC[5]
EIRQ[26]
GPIO[11]
SCK
119
120
E[14]
A[11]
SIUL
GPIO[78]
ETC[5]
—
eTimer_1
SIUL
SIUL
GPIO[11]
SCK
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
A[0]
A[0]
A[2]
A[2]
—
EIRQ[10]
GPIO[79]
—
121
E[15]
SIUL
GPIO[79]
CS1
DSPI_0
SIUL
—
EIRQ[27]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
33
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
122
A[12]
SIUL
DSPI_2
GPIO[12]
SOUT
A[2]
GPIO[12]
—
FlexPWM_0
FlexPWM_0
SIUL
A[2]
B[2]
B[2]
—
EIRQ[11]
JCOMP
GPIO[47]
—
123
124
JCOMP
C[15]
—
—
SIUL
GPIO[47]
CA_TR_EN
ETC[0]
A[1]
FlexRay
eTimer_1
FlexPWM_0
CTU_0
ETC[0]
A[1]
—
EXT_IN
EXT_SYNC
GPIO[48]
—
FlexPWM_0
SIUL
—
125
D[0]
GPIO[48]
CA_TX
ETC[1]
B[1]
FlexRay
eTimer_1
FlexPWM_0
ETC[1]
B[1]
126
127
128
VDD_HV_IO
VSS_HV_IO
D[3]
—
—
SIUL
FlexRay
GPIO[51]
CB_TX
ETC[4]
A[3]
GPIO[51]
—
eTimer_1
FlexPWM_0
SIUL
ETC[4]
A[3]
129
D[4]
GPIO[52]
CB_TR_EN
ETC[5]
B[3]
GPIO[52]
—
FlexRay
eTimer_1
FlexPWM_0
ETC[5]
B[3]
130
131
132
133
VDD_HV_REG_2
VDD_LV_COR
VSS_LV_COR
F[0]
—
—
—
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[80]
A[1]
GPIO[80]
A[1]
—
ETC[2]
EIRQ[28]
—
PXS20 Microcontroller Data Sheet, Rev. 1
34
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
134
A[9]
SIUL
GPIO[9]
CS1
GPIO[9]
—
DSPI_2
FlexPWM_0
FlexPWM_0
B[3]
B[3]
—
FAULT[0]
135
136
VDD_LV_COR
A[13]
—
SIUL
FlexPWM_0
DSPI_2
GPIO[13]
B[2]
GPIO[13]
B[2]
—
SIN
FlexPWM_0
SIUL
—
FAULT[0]
EIRQ[12]
—
137
138
VSS_LV_COR
B[6]
—
SIUL
MC_CGM
DSPI_2
SIUL
GPIO[22]
clk_out
CS2
GPIO[22]
—
—
—
EIRQ[18]
GPIO[83]
—
139
140
F[3]
D[2]
SIUL
GPIO[83]
CS6
DSPI_0
SIUL
GPIO[50]
ETC[3]
X[3]
GPIO[50]
ETC[3]
X[3]
eTimer_1
FlexPWM_0
FlexRay
FCCU
—
CB_RX
F[1]
141
142
FCCU_F[1]
C[6]
F[1]
SIUL
GPIO[38]
SOUT
B[1]
GPIO[38]
—
DSPI_0
FlexPWM_0
SSCM
B[1]
DEBUG[6]
—
—
SIUL
EIRQ[24]
GPIO[14]
—
143
A[14]
SIUL
GPIO[14]
TXD
FlexCAN_1
eTimer_1
SIUL
ETC[4]
—
ETC[4]
EIRQ[13]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
35
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
144
A[15]
SIUL
GPIO[15]
ETC[5]
—
GPIO[15]
ETC[5]
RXD
eTimer_1
FlexCAN_1
FlexCAN_0
SIUL
—
RXD
—
EIRQ[14]
1
VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 4. 257 MAPBGA pin function summary
Pin #
Port/function
Peripheral
Output function
Input function
A1
A2
A3
A4
VSS_HV_IO_RING
VSS_HV_IO_RING
VDD_HV_IO_RING
H[2]
—
—
—
SIUL
NPC
GPIO[114]
MDO[5]
GPIO[112]
MDO[7]
GPIO[110]
MDO[9]
GPIO[51]
CB_TX
ETC[4]
A[3]
GPIO[114]
—
A5
A6
A7
H[0]
G[14]
D[3]
SIUL
GPIO[112]
—
NPC
SIUL
GPIO[110]
—
NPC
SIUL
GPIO[51]
—
FlexRay
eTimer_1
FlexPWM_0
SIUL
ETC[4]
A[3]
A8
C[15]
GPIO[47]
CA_TR_EN
ETC[0]
A[1]
GPIO[47]
—
FlexRay
eTimer_1
FlexPWM_0
CTU_0
FlexPWM_0
ETC[0]
A[1]
—
EXT_IN
EXT_SYNC
—
A9
VDD_HV_IO_RING
A[12]
—
A10
SIUL
DSPI_2
GPIO[12]
SOUT
A[2]
GPIO[12]
—
FlexPWM_0
FlexPWM_0
SIUL
A[2]
B[2]
B[2]
—
EIRQ[11]
PXS20 Microcontroller Data Sheet, Rev. 1
36
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
A11
H[10]
SIUL
FlexPWM_1
eTimer_2
SIUL
GPIO[122]
X[2]
GPIO[122]
X[2]
ETC[2]
GPIO[126]
A[3]
ETC[2]
GPIO[126]
A[3]
A12
A13
H[14]
A[10]
FlexPWM_1
eTimer_2
SIUL
ETC[4]
GPIO[10]
CS0
ETC[4]
GPIO[10]
CS0
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
B[0]
B[0]
X[2]
X[2]
—
EIRQ[9]
GPIO[18]
—
A14
A15
B[2]
SIUL
GPIO[18]
TXD
LINFlexD_0
SSCM
DEBUG[2]
—
—
SIUL
EIRQ[17]
GPIO[42]
—
C[10]
SIUL
GPIO[42]
CS2
DSPI_2
FlexPWM_0
FlexPWM_0
A[3]
A[3]
—
FAULT[1]
A16
A17
B1
VSS_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
B[6]
—
—
—
B2
—
B3
SIUL
MC_CGM
DSPI_2
SIUL
GPIO[22]
clk_out
CS2
GPIO[22]
—
—
—
EIRQ[18]
GPIO[14]
—
B4
B5
A[14]
F[3]
SIUL
GPIO[14]
TXD
FlexCAN_1
eTimer_1
SIUL
ETC[4]
—
ETC[4]
EIRQ[13]
GPIO[83]
—
SIUL
GPIO[83]
CS6
DSPI_0
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
37
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
B6
A[9]
SIUL
DSPI_2
GPIO[9]
CS1
GPIO[9]
—
FlexPWM_0
FlexPWM_0
SIUL
B[3]
B[3]
—
FAULT[0]
GPIO[52]
—
B7
B8
D[4]
D[0]
GPIO[52]
CB_TR_EN
ETC[5]
B[3]
FlexRay
eTimer_1
FlexPWM_0
SIUL
ETC[5]
B[3]
GPIO[48]
CA_TX
ETC[1]
B[1]
GPIO[48]
—
FlexRay
eTimer_1
FlexPWM_0
ETC[1]
B[1]
B9
VSS_HV_IO_RING
H[12]
—
B10
SIUL
FlexPWM_1
SIUL
GPIO[124]
B[2]
GPIO[124]
B[2]
B11
B12
B13
B14
B15
E[15]
E[14]
B[3]
GPIO[79]
CS1
GPIO[79]
—
DSPI_0
SIUL
—
EIRQ[27]
GPIO[78]
ETC[5]
EIRQ[26]
GPIO[19]
—
SIUL
GPIO[78]
ETC[5]
—
eTimer_1
SIUL
SIUL
GPIO[19]
DEBUG[3]
—
SSCM
LINFlexD_0
SIUL
RXD
F[13]
B[0]
GPIO[93]
ETC[4]
—
GPIO[93]
ETC[4]
EIRQ[31]
GPIO[16]
—
eTimer_1
SIUL
SIUL
GPIO[16]
TXD
FlexCAN_0
eTimer_1
SSCM
ETC[2]
DEBUG[0]
—
ETC[2]
—
SIUL
EIRQ[15]
B16
B17
C1
VDD_HV_IO_RING
VSS_HV_IO_RING
VDD_HV_IO_RING
—
—
—
PXS20 Microcontroller Data Sheet, Rev. 1
38
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
C2
C3
C4
C5
Not connected
VSS_HV_IO_RING
FCCU_F[1]
D[2]
—
—
FCCU
SIUL
F[1]
F[1]
GPIO[50]
ETC[3]
X[3]
GPIO[50]
ETC[3]
X[3]
eTimer_1
FlexPWM_0
FlexRay
SIUL
—
CB_RX
GPIO[13]
B[2]
C6
A[13]
GPIO[13]
B[2]
FlexPWM_0
DSPI_2
—
SIN
FlexPWM_0
SIUL
—
FAULT[0]
EIRQ[12]
—
C7
C8
C9
VDD_HV_REG_2
VDD_HV_REG_2
I[0]
—
—
SIUL
eTimer_2
DSPI_0
FlexPWM_1
—
GPIO[128]
ETC[0]
CS4
GPIO[128]
ETC[0]
—
—
FAULT[0]
JCOMP
GPIO[123]
A[2]
C10
C11
JCOMP
H[11]
—
SIUL
GPIO[123]
A[2]
FlexPWM_1
SIUL
C12
I[1]
GPIO[129]
ETC[1]
CS5
GPIO[129]
ETC[1]
—
eTimer_2
DSPI_0
FlexPWM_1
SIUL
—
FAULT[1]
GPIO[94]
—
C13
C14
F[14]
B[1]
GPIO[94]
TXD
LINFlexD_1
SIUL
GPIO[17]
ETC[3]
DEBUG[1]
—
GPIO[17]
ETC[3]
—
eTimer_1
SSCM
FlexCAN_0
FlexCAN_1
SIUL
RXD
—
RXD
—
EIRQ[16]
C15
VSS_HV_IO_RING
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
39
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
C16
A[4]
SIUL
eTimer_1
DSPI_2
eTimer_0
MC_RGM
SIUL
GPIO[4]
ETC[0]
CS1
GPIO[4]
ETC[0]
—
ETC[4]
—
ETC[4]
FAB
—
EIRQ[4]
GPIO[92]
ETC[3]
EIRQ[30]
GPIO[85]
—
C17
F[12]
SIUL
GPIO[92]
ETC[3]
—
eTimer_1
SIUL
D1
D2
D3
F[5]
F[4]
SIUL
GPIO[85]
MDO[2]
GPIO[84]
MDO[3]
GPIO[15]
ETC[5]
—
NPC
SIUL
GPIO[84]
—
NPC
A[15]
SIUL
GPIO[15]
ETC[5]
RXD
eTimer_1
FlexCAN_1
FlexCAN_0
SIUL
—
RXD
—
EIRQ[14]
GPIO[38]
—
D4
C[6]
SIUL
GPIO[38]
SOUT
B[1]
DSPI_0
FlexPWM_0
SSCM
B[1]
DEBUG[6]
—
—
SIUL
EIRQ[24]
D5
D6
D7
VSS_LV_CORE_RING
VDD_LV_CORE_RING
F[0]
—
—
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[80]
A[1]
GPIO[80]
A[1]
—
ETC[2]
EIRQ[28]
—
D8
D9
VDD_HV_IO_RING
VSS_HV_IO_RING
Not connected
—
—
D10
—
PXS20 Microcontroller Data Sheet, Rev. 1
40
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
D11
A[11]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
GPIO[11]
SCK
GPIO[11]
SCK
A[0]
A[0]
A[2]
A[2]
—
EIRQ[10]
GPIO[77]
ETC[5]
—
D12
D13
E[13]
SIUL
GPIO[77]
ETC[5]
CS3
eTimer_0
DSPI_2
SIUL
—
EIRQ[25]
GPIO[95]
RXD
F[15]
SIUL
GPIO[95]
—
LINFlexD_1
D14
D15
D16
VDD_HV_IO_RING
—
1
VPP_TEST
—
D[14]
SIUL
GPIO[62]
B[1]
GPIO[62]
B[1]
FlexPWM_0
eTimer_0
SIUL
—
ETC[3]
GPIO[99]
A[2]
D17
G[3]
GPIO[99]
A[2]
FlexPWM_0
eTimer_0
—
ETC[4]
E1
E2
MDO0
F[6]
—
SIUL
NPC
GPIO[86]
MDO[1]
GPIO[49]
ETC[2]
EXT_TGR
—
GPIO[86]
—
E3
D[1]
SIUL
GPIO[49]
ETC[2]
—
eTimer_1
CTU_0
FlexRay
CA_RX
E4
NMI
Not connected
C[14]
—
E14
E15
—
SIUL
eTimer_1
CTU_0
GPIO[46]
ETC[2]
EXT_TGR
GPIO[98]
X[2]
GPIO[46]
ETC[2]
—
E16
G[2]
SIUL
GPIO[98]
X[2]
FlexPWM_0
DSPI_1
CS1
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
41
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
E17
I[3]
SIUL
eTimer_2
DSPI_0
CTU_0
FlexPWM_1
SIUL
GPIO[131]
ETC[3]
CS7
GPIO[131]
ETC[3]
—
EXT_TGR
—
—
FAULT[3]
GPIO[113]
—
F1
F2
F3
H[1]
G[12]
A[7]
GPIO[113]
MDO[6]
GPIO[108]
MDO[11]
GPIO[7]
SOUT
—
NPC
SIUL
GPIO[108]
—
NPC
SIUL
GPIO[7]
—
DSPI_1
SIUL
EIRQ[7]
GPIO[8]
SIN
F4
A[8]
SIUL
GPIO[8]
—
DSPI_1
SIUL
—
EIRQ[8]
F6
F7
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
Not connected
—
—
F8
—
F9
—
F10
F11
F12
F14
F15
—
—
—
—
C[13]
SIUL
eTimer_1
CTU_0
GPIO[45]
ETC[1]
—
GPIO[45]
ETC[1]
EXT_IN
EXT_SYNC
GPIO[130]
ETC[2]
FlexPWM_0
SIUL
—
F16
F17
I[2]
GPIO[130]
ETC[2]
CS6
eTimer_2
DSPI_0
—
FlexPWM_1
SIUL
—
FAULT[2]
GPIO[100]
B[2]
G[4]
GPIO[100]
B[2]
FlexPWM_0
eTimer_0
—
ETC[5]
PXS20 Microcontroller Data Sheet, Rev. 1
42
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
G1
H[3]
SIUL
NPC
GPIO[115]
MDO[4]
—
GPIO[115]
—
G2
G3
VDD_HV_IO_RING
C[5]
SIUL
DSPI_0
SSCM
GPIO[37]
SCK
GPIO[37]
SCK
DEBUG[5]
—
—
FlexPWM_0
SIUL
FAULT[3]
EIRQ[23]
GPIO[6]
SCK
—
G4
A[6]
SIUL
GPIO[6]
SCK
DSPI_1
SIUL
—
EIRQ[6]
G6
G7
VDD_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VDD_LV_CORE_RING
D[12]
—
—
G8
—
G9
—
G10
G11
G12
G14
—
—
—
SIUL
FlexPWM_0
LINFlexD_1
SIUL
GPIO[60]
X[1]
GPIO[60]
X[1]
—
RXD
G15
G16
H[13]
H[9]
GPIO[125]
X[3]
GPIO[125]
X[3]
FlexPWM_1
eTimer_2
SIUL
ETC[3]
GPIO[121]
B[1]
ETC[3]
GPIO[121]
B[1]
FlexPWM_1
DSPI_0
CS7
—
G17
H1
G[6]
G[13]
SIUL
GPIO[102]
A[3]
GPIO[102]
A[3]
FlexPWM_0
SIUL
GPIO[109]
MDO[10]
—
GPIO[109]
—
NPC
H2
VSS_HV_IO_RING
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
43
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
H3
C[4]
SIUL
DSPI_0
FlexPWM_0
SSCM
GPIO[36]
GPIO[36]
CS0
CS0
X[1]
X[1]
DEBUG[4]
—
SIUL
—
EIRQ[22]
GPIO[5]
CS0
H4
A[5]
SIUL
GPIO[5]
DSPI_1
eTimer_1
DSPI_0
SIUL
CS0
ETC[5]
ETC[5]
—
CS7
—
EIRQ[5]
H6
H7
VDD_LV
VSS_LV
—
—
H8
VSS_LV
—
H9
VSS_LV
—
H10
H11
H12
H14
H15
H16
H17
VSS_LV
—
VSS_LV
—
VDD_LV
—
VSS_LV
—
VDD_HV_REG_1
VDD_HV_FLA
H[6]
—
—
GPIO[118]
B[0]
SIUL
FlexPWM_1
DSPI_0
SIUL
GPIO[118]
B[0]
CS5
—
J1
J2
F[7]
GPIO[87]
MCKO
GPIO[111]
MDO[8]
—
GPIO[87]
—
NPC
G[15]
SIUL
GPIO[111]
—
NPC
J3
J4
VDD_HV_REG_0
VDD_HV_REG_0
VDD_LV
—
J6
—
J7
VSS_LV
—
J8
VSS_LV
—
J9
VSS_LV
—
J10
J11
VSS_LV
—
VSS_LV
—
PXS20 Microcontroller Data Sheet, Rev. 1
44
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
J12
J14
J15
J16
J17
VDD_LV
VDD_LV
—
—
VDD_HV_REG_1
VSS_HV_FLA
H[15]
—
—
SIUL
FlexPWM_1
eTimer_2
SIUL
GPIO[127]
B[3]
GPIO[127]
B[3]
ETC[5]
GPIO[89]
MSEO[0]
GPIO[88]
MSEO[1]
—
ETC[5]
GPIO[89]
—
K1
K2
F[9]
F[8]
NPC
SIUL
GPIO[88]
—
NPC
K3
(cut1)
Not connected
RDY
K3
(cut2)
NPC
SIUL
RDY
—
GPIO[132]
GPIO[39]
A[1]
GPIO[132]
K4
C[7]
SIUL
GPIO[39]
FlexPWM_0
SSCM
A[1]
DEBUG[7]
—
DSPI_0
—
SIN
K6
K7
VDD_LV
VSS_LV
—
—
—
K8
VSS_LV
K9
VSS_LV
—
K10
K11
K12
K14
K15
VSS_LV
—
VSS_LV
—
VDD_LV
—
Not connected
H[8]
—
SIUL
FlexPWM_1
DSPI_0
GPIO[120]
A[1]
GPIO[120]
A[1]
CS6
GPIO[119]
X[1]
—
K16
H[7]
SIUL
GPIO[119]
X[1]
FlexPWM_1
eTimer_2
ETC[1]
ETC[1]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
45
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
K17
A[3]
SIUL
eTimer_0
DSPI_2
FlexPWM_0
MC_RGM
SIUL
GPIO[3]
ETC[3]
CS0
B[3]
GPIO[3]
ETC[3]
CS0
B[3]
—
ABS[2]
EIRQ[3]
GPIO[90]
—
—
L1
L2
L3
F[10]
F[11]
D[9]
SIUL
GPIO[90]
EVTO
GPIO[91]
EVTI
GPIO[57]
X[0]
NPC
SIUL
GPIO[91]
—
NPC
SIUL
GPIO[57]
X[0]
FlexPWM_0
LINFlexD_1
TXD
—
—
L4
L6
Not connected
VDD_LV
—
L7
VSS_LV
—
L8
VSS_LV
—
L9
VSS_LV
—
L10
L11
L12
L14
L15
L16
VSS_LV
—
VSS_LV
—
VDD_LV
—
Not connected
TCK
—
—
H[4]
SIUL
FlexPWM_1
eTimer_2
SIUL
GPIO[116]
X[0]
GPIO[116]
X[0]
ETC[0]
GPIO[20]
TDO
—
ETC[0]
GPIO[20]
—
L17
B[4]
JTAGC
M1
M2
M3
VDD_HV_OSC
VDD_HV_IO_RING
D[8]
—
SIUL
DSPI_1
GPIO[56]
CS2
ETC[4]
CS5
—
GPIO[56]
—
eTimer_1
DSPI_0
ETC[4]
—
FlexPWM_0
FAULT[3]
PXS20 Microcontroller Data Sheet, Rev. 1
46
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
M4
M6
Not connected
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
C[11]
—
—
M7
—
M8
—
M9
—
M10
M11
M12
M14
—
—
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[43]
ETC[4]
CS2
GPIO[21]
—
GPIO[43]
ETC[4]
—
M15
B[5]
GPIO[21]
TDI
JTAGC
M16
M17
TMS
H[5]
—
SIUL
GPIO[117]
A[0]
GPIO[117]
A[0]
FlexPWM_1
DSPI_0
CS4
—
—
N1
N2
N3
XTALIN
VSS_HV_IO_RING
D[5]
—
SIUL
GPIO[53]
CS3
—
GPIO[53]
—
DSPI_0
FlexPWM_0
FAULT[2]
N4
VSS_LV_PLL0_PLL1
Not connected
C[12]
—
N14
N15
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[44]
ETC[5]
CS3
GPIO[2]
ETC[2]
A[3]
GPIO[44]
ETC[5]
—
N16
A[2]
GPIO[2]
ETC[2]
A[3]
eTimer_0
FlexPWM_0
DSPI_2
MC_RGM
SIUL
—
SIN
—
ABS[0]
EIRQ[2]
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
47
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
N17
G[5]
SIUL
GPIO[101]
GPIO[101]
X[3]
FlexPWM_0
DSPI_2
X[3]
CS3
—
P1
P2
P3
VSS_HV_OSC
RESET
D[6]
—
—
SIUL
GPIO[54]
GPIO[54]
—
DSPI_0
CS2
FlexPWM_0
FlexPWM_0
X[3]
X[3]
—
FAULT[1]
P4
P5
P6
P7
VDD_LV_PLL0_PLL1
VDD_LV_CORE_RING
VSS_LV_CORE_RING
B[8]
—
—
—
SIUL
—
GPIO[24]
ETC[5]
AN[1]
eTimer_0
ADC_0
—
—
P8
P9
Not connected
VSS_HV_IO_RING
VDD_HV_IO_RING
B[14]
—
—
P10
P11
—
SIUL
eTimer_0
SIUL
—
GPIO[30]
ETC[4]
—
—
EIRQ[19]
AN[1]
ADC_1
—
P12
P13
P14
P15
VDD_LV_CORE_RING
VSS_LV_CORE_RING
VDD_HV_IO_RING
G[10]
—
—
—
SIUL
FlexRay
DSPI_2
FlexPWM_0
SIUL
GPIO[106]
DBG2
CS3
—
GPIO[106]
—
—
FAULT[2]
GPIO[104]
—
P16
G[8]
GPIO[104]
DBG0
CS1
—
FlexRay
DSPI_0
FlexPWM_0
SIUL
—
FAULT[0]
EIRQ[21]
—
PXS20 Microcontroller Data Sheet, Rev. 1
48
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
P17
G[7]
SIUL
GPIO[103]
GPIO[103]
B[3]
FlexPWM_0
B[3]
R1
R2
R3
R4
XTALOUT
FCCU_F[0]
VSS_HV_IO_RING
D[7]
—
FCCU
F[0]
F[0]
—
SIUL
DSPI_1
DSPI_0
SWG
GPIO[55]
GPIO[55]
—
CS3
CS4
—
analog output
—
R5
R6
B[7]
E[6]
SIUL
—
—
—
—
—
—
—
—
GPIO[23]
RXD
LINFlexD_0
ADC_0
SIUL
AN[0]
GPIO[70]
AN[4]
ADC_0
R7
R8
VDD_HV_ADR0
B[10]
SIUL
GPIO[26]
AN[12]
ADC_0
ADC_1
R9
VDD_HV_ADR1
B[13]
—
—
R10
SIUL
LINFlexD_1
ADC_1
SIUL
GPIO[29]
RXD
—
—
AN[0]
R11
R12
B[15]
C[0]
—
GPIO[31]
EIRQ[20]
AN[2]
SIUL
—
ADC_1
SIUL
—
—
GPIO[32]
AN[3]
ADC_1
—
R13
R14
BCTRL
A[1]
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[1]
ETC[1]
SOUT
—
GPIO[1]
ETC[1]
—
EIRQ[1]
R15
VSS_HV_IO_RING
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
49
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
R16
D[11]
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[59]
GPIO[59]
B[0]
B[0]
—
ETC[1]
GPIO[105]
—
R17
G[9]
GPIO[105]
FlexRay
DSPI_1
DBG1
CS1
—
—
FlexPWM_0
SIUL
FAULT[1]
EIRQ[29]
—
T1
T2
T3
T4
VSS_HV_IO_RING
VDD_HV_IO_RING
Not connected
C[1]
—
—
—
SIUL
ADC_0
SIUL
—
GPIO[33]
AN[2]
—
T5
T6
E[5]
E[7]
—
GPIO[69]
AN[8]
ADC_0
SIUL
—
—
GPIO[71]
AN[6]
ADC_0
—
T7
T8
VSS_HV_ADR0
B[11]
—
SIUL
—
GPIO[27]
AN[13]
ADC_0
ADC_1
—
T9
VSS_HV_ADR1
E[9]
—
—
T10
SIUL
ADC_1
SIUL
GPIO[73]
AN[7]
—
T11
T12
T13
T14
E[10]
E[12]
E[0]
—
GPIO[74]
AN[8]
ADC_1
SIUL
—
—
GPIO[76]
AN[6]
ADC_1
SIUL
—
—
GPIO[64]
AN[5]
ADC_1
SIUL
—
A[0]
GPIO[0]
ETC[0]
SCK
—
GPIO[0]
ETC[0]
SCK
eTimer_0
DSPI_2
SIUL
EIRQ[0]
PXS20 Microcontroller Data Sheet, Rev. 1
50
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
T15
D[10]
SIUL
GPIO[58]
A[0]
—
GPIO[58]
A[0]
FlexPWM_0
eTimer_0
ETC[0]
T16
T17
U1
VDD_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
Not connected
E[4]
—
—
—
U2
—
U3
—
U4
SIUL
ADC_0
SIUL
—
GPIO[68]
AN[7]
—
U5
U6
U7
C[2]
E[2]
B[9]
—
GPIO[34]
AN[3]
ADC_0
SIUL
—
—
GPIO[66]
AN[5]
ADC_0
SIUL
—
—
GPIO[25]
AN[11]
ADC_0
ADC_1
—
U8
B[12]
SIUL
—
—
GPIO[28]
AN[14]
ADC_0
ADC_1
U9
VDD_HV_ADV
VSS_HV_ADV
E[11]
—
U10
U11
—
SIUL
—
GPIO[75]
AN[4]
ADC_1
—
U12
U13
U14
U15
Not connected
Not connected
VDD_HV_PMU
G[11]
—
—
—
GPIO[107]
DBG3
—
SIUL
GPIO[107]
—
FlexRay
FlexPWM_0
FAULT[3]
U16
U17
VSS_HV_IO_RING
VSS_HV_IO_RING
—
—
1
VPP_TEST should always be tied to ground (VSS) for normal operations.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
51
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
2.2
Supply pins
Table 5. Supply pins
Supply
Pin #
144
257
pkg
Symbol
Description
pkg
VREG control and power supply pins
BCTRL
Voltage regulator external NPN ballast base control pin
69
70
71
72
R13
VDD_LV1
VSS_LV2
U14
VDD_LV_COR Core logic supply
VSS_LV_COR Core regulator ground
VDD_HV_PMU Voltage regulator supply
ADC_0/ADC_1 reference voltage and ADC supply
VDD_HV_ADR0 ADC_0 high reference voltage
VSS_HV_ADR0 ADC_0 low reference voltage
VDD_HV_ADR1 ADC_1 high reference voltage
VSS_HV_ADR1 ADC_1 low reference voltage
VDD_HV_ADV ADC voltage supply for ADC_0 and ADC_1
VSS_HV_ADV ADC ground for ADC_0 and ADC_1
Power supply pins (3.3 V)
50
51
56
57
58
59
R7
T7
R9
T9
U9
U10
VDD_HV_IO
VSS_HV_IO
3.3 V Input/Output supply voltage
3.3 V Input/Output ground
6
7
VDD_HV3
VSS_HV4
J3
VDD_HV_REG_0 VDD_HV_REG_0
VDD_HV_IO 3.3 V Input/Output supply voltage
VSS_HV_IO 3.3 V Input/Output ground
16
21 VDD_HV3
22 VSS_HV4
VDD_HV_OSC Crystal oscillator amplifier supply voltage
VSS_HV_OSC Crystal oscillator amplifier ground
27
28
M1
P1
VSS_HV_IO
VDD_HV_IO
3.3 V Input/Output ground
90 VSS_HV4
91 VDD_HV3
3.3 V Input/Output supply voltage
VDD_HV_REG_1 VDD_HV_REG_1
VSS_HV_FLA VSS_HV_FLA
VDD_HV_FLA VDD_HV_FLA
95
96
97
H15
J16
H16
VDD_HV_IO
VSS_HV_IO
VDD_HV_IO
VSS_HV_IO
126 VDD_HV3
127 VSS_HV4
VDD_HV_REG_2 VDD_HV_REG_2
130
C7
Power supply pins (1.2 V)
VSS_LV_COR VSS_LV_COR
17 VSS_HV2
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
PXS20 Microcontroller Data Sheet, Rev. 1
52
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 5. Supply pins (continued)
Supply
Pin #
144
pkg
257
pkg
Symbol
Description
VDD_LV_COR VDD_LV_COR
18
35
36
39
40
70
71
93
94
VDD_LV1
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
VSS 1V2
VSS_LV_PLL0_PLL1 /
N4
1.2 V Decoupling pins for on-chip FMPLL modules. Decoupling capacitor
must be connected between this pin and VDD_LV_PLL.
VDD 1V2
VDD_LV_PLL0_PLL1
P4
Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must
be connected between this pin and VSS_LV_PLL.
VDD_LV_COR VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
VDD_LV1
VSS_LV2
VDD_LV1
VSS_LV2
VDD_LV1
VSS_LV2
VSS_LV_COR VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
VDD_LV_COR VDD_LV_COR
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VSS_LV_REGCOR.
VSS_LV_COR VSS_LV_REGCOR0
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VDD_LV_REGCOR.
VDD_LV_COR VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
VSS_LV_COR VSS_LV_COR
/ 1.2 V Decoupling pins for core logic. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV_COR pin.
VDD 1V2
VSS 1V2
VDD 1V2
VSS 1V2
VDD_LV_COR
131 VDD_LV1
132 VSS_LV2
135 VDD_LV1
137 VSS_LV2
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
VDD_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
VSS_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
1
2
3
4
VDD_LV balls are tied together on the 257 MAPBGA substrate.
VSS_LV balls are tied together on the 257 MAPBGA substrate.
VDD_HV balls are tied together on the 257 MAPBGA substrate.
VSS_HV balls are tied together on the 257 MAPBGA substrate.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
53
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
2.3
System pins
Table 6. System pins
Pin #
Symbol
Description
Direction
144 257
pkg pkg
Dedicated pins
MDO01
NMI2
Nexus Message Data Output — line 0
Output only
Input only
Input only
Output only
Input only
Input only
Input only
9
1
E1
E4
N1
R1
Non Maskable Interrupt
XTAL
Input for oscillator amplifier circuit and internal clock generator
Oscillator amplifier output
JTAG state machine control
JTAG clock
29
30
EXTAL
TMS2
87 M16
88 L15
123 C10
TCK2
JCOMP3
JTAG compliance select
Reset pin
RESET
Bidirectional reset with Schmitt-Trigger characteristics and noise filter. Bidirectional
This pin has medium drive strength.
31
P2
Test pin
VPP TEST
Pin for testing purpose only. To be tied to ground in normal
operating mode.
107 D15
1
2
3
This pad is configured for Fast (F) pad speed.
This pad contains a weak pull-up.
This pad contains a weak pull-down.
2.4
Pin muxing
Table 7 defines the pin list and muxing for this device.
Each entry of Table 7 shows all the possible configurations for each pin, via the alternate functions. The default function
assigned to each pin after reset is indicated by ALT0.
NOTE
Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or
voltage may cause unpredictable device behavior or damage.
Pins labeled “Reserved” are to be tied to ground. Not doing so may cause unpredictable
device behavior.
PXS20 Microcontroller Data Sheet, Rev. 1
54
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Table 7. Pin muxing
Input
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
PCR
Peripheral
Input mux select
144 257
pkg pkg
functions
= 1
= 0
Port A
A[0]
A[1]
A[2]
PCR[0]
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[0]
ETC[0]
SCK
—
ALT0
ALT1
ALT2
—
GPIO[0]
ETC[0]
SCK
—
Pull down
Pull down
Pull down
M
S
73
T14
PSMI[35]; PADSEL=0
PSMI[1]; PADSEL=0
EIRQ[0]
GPIO[1]
ETC[1]
—
—
PCR[1]
PCR[2]
SIUL
GPIO[1]
ETC[1]
SOUT
—
ALT0
ALT1
ALT2
—
—
M
M
S
S
74 R14
eTimer_0
DSPI_2
SIUL
PSMI[36]; PADSEL=0
—
EIRQ[1]
GPIO[2]
ETC[2]
A[3]
—
SIUL
GPIO[2]
ETC[2]
A[3]
ALT0
ALT1
ALT3
—
—
84 N16
eTimer_0
FlexPWM_0
DSPI_2
MC_RGM
SIUL
PSMI[37]; PADSEL=0
PSMI[23]; PADSEL=0
—
SIN
PSMI[2]; PADSEL=0
—
—
ABS[0]
EIRQ[2]
GPIO[3]
ETC[3]
CS0
—
—
—
—
A[3]
PCR[3]
SIUL
GPIO[3]
ETC[3]
CS0
ALT0
ALT1
ALT2
ALT3
—
—
Pull down
M
S
92 K17
eTimer_0
DSPI_2
FlexPWM_0
MC_RGM
SIUL
PSMI[38]; PADSEL=0
PSMI[3]; PADSEL=0
PSMI[27]; PADSEL=0
—
B[3]
B[3]
—
ABS[2]
EIRQ[3]
—
—
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
A[4]
PCR[4]
SIUL
eTimer_1
DSPI_2
eTimer_0
MC_RGM
SIUL
GPIO[4]
ETC[0]
CS1
ALT0
ALT1
ALT2
ALT3
—
GPIO[4]
ETC[0]
—
—
Pull down
M
S
108 C16
PSMI[9]; PADSEL=0
—
ETC[4]
—
ETC[4]
FAB
PSMI[7]; PADSEL=0
—
—
—
EIRQ[4]
GPIO[5]
CS0
—
A[5]
PCR[5]
SIUL
GPIO[5]
CS0
ALT0
ALT1
ALT2
ALT3
—
—
Pull down
M
S
14
H4
DSPI_1
eTimer_1
DSPI_0
SIUL
—
ETC[5]
CS7
ETC[5]
—
PSMI[14]; PADSEL=0
—
—
EIRQ[5]
GPIO[6]
SCK
—
A[6]
A[7]
A[8]
A[9]
PCR[6]
PCR[7]
PCR[8]
PCR[9]
SIUL
GPIO[6]
SCK
—
ALT0
ALT1
—
—
Pull down
Pull down
Pull down
Pull down
M
M
M
M
S
S
S
S
2
G4
F3
F4
DSPI_1
SIUL
—
EIRQ[6]
GPIO[7]
—
—
SIUL
GPIO[7]
SOUT
—
ALT0
ALT1
—
—
10
12
DSPI_1
SIUL
—
EIRQ[7]
GPIO[8]
SIN
—
SIUL
GPIO[8]
—
ALT0
—
—
DSPI_1
SIUL
—
—
—
EIRQ[8]
GPIO[9]
—
—
SIUL
GPIO[9]
CS1
ALT0
ALT1
ALT3
—
—
134 B6
DSPI_2
FlexPWM_0
FlexPWM_0
—
B[3]
B[3]
PSMI[27]; PADSEL=1
PSMI[16]; PADSEL=0
—
FAULT[0]
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
A[10]
A[11]
A[12]
A[13]
A[14]
PCR[10]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
GPIO[10]
CS0
ALT0
ALT1
ALT2
ALT3
—
GPIO[10]
CS0
—
Pull down
Pull down
Pull down
Pull down
Pull down
M
S
118 A13
120 D11
122 A10
136 C6
143 B4
PSMI[3]; PADSEL=1
B[0]
B[0]
PSMI[24]; PADSEL=0
X[2]
X[2]
PSMI[29]; PADSEL=0
—
EIRQ[9]
GPIO[11]
SCK
—
PCR[11]
PCR[12]
PCR[13]
PCR[14]
SIUL
GPIO[11]
SCK
A[0]
ALT0
ALT1
ALT2
ALT3
—
—
M
M
M
M
S
S
S
S
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
PSMI[1]; PADSEL=1
A[0]
PSMI[20]; PADSEL=0
A[2]
A[2]
PSMI[22]; PADSEL=0
—
EIRQ[10]
GPIO[12]
—
—
SIUL
GPIO[12]
SOUT
A[2]
ALT0
ALT1
ALT2
ALT3
—
—
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
—
A[2]
PSMI[22]; PADSEL=1
B[2]
B[2]
PSMI[26]; PADSEL=0
—
EIRQ[11]
GPIO[13]
B[2]
—
SIUL
GPIO[13]
B[2]
ALT0
ALT2
—
—
FlexPWM_0
DSPI_2
FlexPWM_0
SIUL
PSMI[26]; PADSEL=1
—
SIN
PSMI[2]; PADSEL=1
—
—
FAULT[0]
EIRQ[12]
GPIO[14]
—
PSMI[16]; PADSEL=1
—
—
—
SIUL
GPIO[14]
TXD
ETC[4]
—
ALT0
ALT1
ALT2
—
—
FlexCAN_1
eTimer_1
SIUL
—
ETC[4]
EIRQ[13]
PSMI[13]; PADSEL=0
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
A[15]
PCR[15]
SIUL
GPIO[15]
ETC[5]
—
ALT0
ALT2
—
GPIO[15]
ETC[5]
RXD
—
Pull down
M
S
144 D3
eTimer_1
FlexCAN_1
FlexCAN_0
SIUL
PSMI[14]; PADSEL=1
PSMI[34]; PADSEL=0
PSMI[33]; PADSEL=0
—
—
—
RXD
—
—
EIRQ[14]
Port B
B[0]
B[1]
PCR[16]
PCR[17]
SIUL
FlexCAN_0
eTimer_1
SSCM
GPIO[16]
TXD
ALT0
ALT1
ALT2
ALT3
—
GPIO[16]
—
—
Pull down
M
M
S
S
109 B15
—
ETC[2]
DEBUG[0]
—
ETC[2]
—
PSMI[11]; PADSEL=0
—
SIUL
EIRQ[15]
GPIO[17]
ETC[3]
—
—
SIUL
GPIO[17]
ETC[3]
DEBUG[1]
—
ALT0
ALT2
ALT3
—
—
Pull down
110 C14
eTimer_1
SSCM
PSMI[12]; PADSEL=0
—
FlexCAN_0
FlexCAN_1
SIUL
RXD
PSMI[33]; PADSEL=1
—
—
RXD
PSMI[34]; PADSEL=1
—
—
EIRQ[16]
GPIO[18]
—
—
B[2]
B[3]
PCR[18]
PCR[19]
SIUL
GPIO[18]
TXD
ALT0
ALT1
ALT3
—
—
Pull down
Pull down
M
M
S
S
114 A14
LINFlex_0
SSCM
—
DEBUG[2]
—
—
—
SIUL
EIRQ[17]
GPIO[19]
—
—
SIUL
GPIO[19]
DEBUG[3]
—
ALT0
ALT3
—
—
116 B13
SSCM
—
LINFlex_0
RXD
PSMI[31]; PADSEL=0
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
B[4]2
B[5]
B[6]
PCR[20]
PCR[21]
PCR[22]
SIUL
JTAGC
SIUL
GPIO[20]
ALT0
ALT1
ALT0
—
GPIO[20]
—
—
Pull down
Pull up
F
S
89
L17
TDO
—
GPIO[21]
GPIO[21]
TDI
—
M
F
S
S
86 M15
138 B3
JTAGC
SIUL
—
GPIO[22]
clk_out
CS2
—
—
ALT0
ALT1
ALT2
GPIO[22]
—
—
Pull down
MC_CGM
DSPI_2
SIUL
—
—
—
EIRQ[18]
GPI[23]
RXD
—
B[7]
B[8]
PCR[23]
PCR[24]
SIUL
—
ALT0
—
—
—
—
—
—
—
—
43
47
R5
P7
LINFlex_0
ADC_0
SIUL
—
PSMI[31]; PADSEL=1
—
—
AN[0]3
GPI[24]
ETC[5]
AN[1]3
GPI[25]
AN[11]3
—
—
ALT0
—
—
eTimer_0
ADC_0
SIUL
—
PSMI[8]; PADSEL=2
—
—
—
—
—
B[9]
PCR[25]
PCR[26]
PCR[27]
PCR[28]
—
ALT0
—
—
—
—
—
—
—
—
—
—
—
—
—
52
53
54
55
U7
R8
T8
U8
ADC_0
ADC_1
—
B[10]
B[11]
B[12]
SIUL
—
—
ALT0
—
GPI[26]
AN[12]3
—
—
ADC_0
ADC_1
SIUL
—
—
ALT0
—
GPI[27]
AN[13]3
—
—
ADC_0
ADC_1
SIUL
—
—
ALT0
—
GPI[28]
AN[14]3
—
—
ADC_0
ADC_1
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
B[13]
B[14]
PCR[29]
SIUL
LINFlex_1
ADC_1
SIUL
—
—
—
—
—
—
—
—
—
—
ALT0
—
GPI[29]
RXD
—
—
—
—
60 R10
PSMI[32]; PADSEL=0
—
AN[0]3
—
PCR[30]
PCR[31]
ALT0
—
GPI[30]
ETC[4]
EIRQ[19]
AN[1]3
—
—
—
—
—
—
64 P11
eTimer_0
SIUL
PSMI[7]; PADSEL=2
—
—
—
—
—
—
ADC_1
SIUL
—
B[15]
ALT0
—
GPI[31]
EIRQ[20]
AN[2]3
—
62 R11
SIUL
ADC_1
—
Port C
C[0]
C[1]
C[2]
C[4]
PCR[32]
PCR[33]
PCR[34]
PCR[36]
SIUL
ADC_1
SIUL
—
ALT0
—
GPI[32]
AN[3]3
GPI[33]
AN[2]3
GPI[34]
AN[3]3
GPIO[36]
CS0
—
—
—
—
—
—
M
—
—
—
S
66 R12
—
—
—
ALT0
—
—
41
45
11
T4
U5
H3
ADC_0
SIUL
—
—
—
ALT0
—
—
—
ADC_0
SIUL
—
—
GPIO[36]
CS0
X[1]
ALT0
ALT1
ALT2
ALT3
—
—
Pull down
DSPI_0
FlexPWM_0
SSCM
SIUL
—
X[1]
PSMI[28]; PADSEL=0
DEBUG[4]
—
—
—
—
EIRQ[22]
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
C[5]
PCR[37]
SIUL
DSPI_0
SSCM
GPIO[37]
SCK
ALT0
ALT1
ALT3
—
GPIO[37]
SCK
—
Pull down
M
S
13
G3
—
DEBUG[5]
—
—
—
FlexPWM_0
SIUL
FAULT[3]
EIRQ[23]
GPIO[38]
—
PSMI[19]; PADSEL=0
—
—
—
C[6]
PCR[38]
SIUL
GPIO[38]
SOUT
B[1]
ALT0
ALT1
ALT2
ALT3
—
—
Pull down
M
S
142 D4
DSPI_0
FlexPWM_0
SSCM
—
B[1]
PSMI[25]; PADSEL=0
DEBUG[6]
—
—
—
SIUL
EIRQ[24]
GPIO[39]
A[1]
—
C[7]
PCR[39]
PCR[42]
SIUL
GPIO[39]
A[1]
ALT0
ALT2
ALT3
—
—
Pull down
Pull down
M
M
S
S
15
K4
FlexPWM_0
SSCM
PSMI[21]; PADSEL=0
DEBUG[7]
—
—
—
DSPI_0
SIUL
SIN
—
C[10]
GPIO[42]
CS2
ALT0
ALT1
ALT3
—
GPIO[42]
—
—
111 A15
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
—
A[3]
A[3]
PSMI[23]; PADSEL=1
—
FAULT[1]
GPIO[43]
ETC[4]
—
PSMI[17]; PADSEL=0
C[11]
C[12]
PCR[43]
PCR[44]
GPIO[43]
ETC[4]
CS2
ALT0
ALT1
ALT2
ALT0
ALT1
ALT2
—
Pull down
Pull down
M
M
S
S
80 M14
82 N15
eTimer_0
DSPI_2
SIUL
PSMI[7]; PADSEL=1
—
GPIO[44]
ETC[5]
CS3
GPIO[44]
ETC[5]
—
—
eTimer_0
DSPI_2
PSMI[8]; PADSEL=0
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
C[13]
PCR[45]
SIUL
eTimer_1
CTU_0
GPIO[45]
ETC[1]
—
ALT0
ALT1
—
GPIO[45]
ETC[1]
EXT_IN
EXT_SYNC
GPIO[46]
ETC[2]
—
—
Pull down
M
S
101 F15
PSMI[10]; PADSEL=0
PSMI[0]; PADSEL=0
PSMI[15]; PADSEL=0
—
FlexPWM_0
SIUL
—
—
C[14]
C[15]
PCR[46]
PCR[47]
GPIO[46]
ETC[2]
EXT_TGR
GPIO[47]
CA_TR_EN
ETC[0]
A[1]
ALT0
ALT1
ALT2
ALT0
ALT1
ALT2
ALT3
—
Pull down
Pull down
M
S
S
103 E15
124 A8
eTimer_1
CTU_0
PSMI[11]; PADSEL=1
—
SIUL
GPIO[47]
—
—
SYM
FlexRay
eTimer_1
FlexPWM_0
CTU_0
—
ETC[0]
A[1]
PSMI[9]; PADSEL=1
PSMI[21]; PADSEL=1
PSMI[0]; PADSEL=1
PSMI[15]; PADSEL=1
—
EXT_IN
EXT_SYNC
Port D
FlexPWM_0
—
—
D[0]
D[1]
PCR[48]
PCR[49]
SIUL
FlexRay
eTimer_1
FlexPWM_0
SIUL
GPIO[48]
CA_TX
ETC[1]
B[1]
ALT0
ALT1
ALT2
ALT3
ALT0
ALT2
ALT3
—
GPIO[48]
—
—
Pull down
Pull down
SYM
S
S
125 B8
—
ETC[1]
B[1]
PSMI[10]; PADSEL=1
PSMI[25]; PADSEL=1
GPIO[49]
ETC[2]
EXT_TGR
—
GPIO[49]
ETC[2]
—
—
M
3
E3
eTimer_1
CTU_0
PSMI[11]; PADSEL=2
—
—
FlexRay
CA_RX
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
D[2]
D[3]
D[4]
PCR[50]
SIUL
eTimer_1
FlexPWM_0
FlexRay
SIUL
GPIO[50]
ETC[3]
X[3]
ALT0
ALT2
ALT3
—
GPIO[50]
ETC[3]
X[3]
—
Pull down
Pull down
Pull down
M
S
140 C5
128 A7
129 B7
PSMI[12]; PADSEL=1
PSMI[30]; PADSEL=0
—
CB_RX
GPIO[51]
—
—
PCR[51]
PCR[52]
GPIO[51]
CB_TX
ETC[4]
A[3]
ALT0
ALT1
ALT2
ALT3
ALT0
ALT1
ALT2
ALT3
ALT0
ALT1
—
—
SYM
SYM
S
S
FlexRay
eTimer_1
FlexPWM_0
SIUL
—
ETC[4]
A[3]
PSMI[13]; PADSEL=1
PSMI[23]; PADSEL=2
GPIO[52]
CB_TR_EN
ETC[5]
B[3]
GPIO[52]
—
—
FlexRay
eTimer_1
FlexPWM_0
SIUL
—
ETC[5]
B[3]
PSMI[14]; PADSEL=2
PSMI[27]; PADSEL=2
D[5]
D[6]
PCR[53]
PCR[54]
GPIO[53]
CS3
GPIO[53]
—
—
Pull down
Pull down
M
M
S
S
33
34
N3
P3
DSPI_0
FlexPWM_0
SIUL
—
—
FAULT[2]
GPIO[54]
—
PSMI[18]; PADSEL=0
GPIO[54]
CS2
ALT0
ALT1
ALT3
—
—
DSPI_0
FlexPWM_0
FlexPWM_0
SIUL
—
X[3]
X[3]
PSMI[30]; PADSEL=1
—
FAULT[1]
GPIO[55]
—
PSMI[17]; PADSEL=1
D[7]
PCR[55]
GPIO[55]
CS3
ALT0
ALT1
ALT3
—
—
—
—
—
Pull down
M
S
37
R4
DSPI_1
DSPI_0
SWG
CS4
—
analog output
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
D[8]
PCR[56]
SIUL
DSPI_1
GPIO[56]
CS2
ALT0
ALT1
ALT2
ALT3
—
GPIO[56]
—
—
Pull down
M
S
32
M3
—
eTimer_1
DSPI_0
ETC[4]
CS5
ETC[4]
—
PSMI[13]; PADSEL=2
—
FlexPWM_0
SIUL
—
FAULT[3]
GPIO[57]
X[0]
PSMI[19]; PADSEL=1
D[9]
PCR[57]
PCR[58]
PCR[59]
PCR[60]
PCR[62]
GPIO[57]
X[0]
ALT0
ALT1
ALT2
ALT0
ALT1
—
—
Pull down
Pull down
Pull down
Pull down
Pull down
M
M
M
M
M
S
S
S
S
S
26
76
L3
FlexPWM_0
LINFlexD_1
SIUL
—
TXD
—
—
D[10]
D[11]
D[12]
D[14]
GPIO[58]
A[0]
GPIO[58]
A[0]
—
T15
FlexPWM_0
eTimer_0
SIUL
PSMI[20]; PADSEL=1
PSMI[35]; PADSEL=1
—
—
ETC[0]
GPIO[59]
B[0]
GPIO[59]
B[0]
ALT0
ALT1
—
78 R16
99 G14
105 D16
FlexPWM_0
eTimer_0
SIUL
PSMI[24]; PADSEL=1
PSMI[36]; PADSEL=1
—
ETC[1]
GPIO[60]
X[1]
GPIO[60]
X[1]
ALT0
ALT1
—
FlexPWM_0
LINFlexD_1
SIUL
PSMI[28]; PADSEL=1
PSMI[32]; PADSEL=1
—
—
RXD
GPIO[62]
B[1]
ALT0
ALT1
—
GPIO[62]
B[1]
FlexPWM_0
eTimer_0
PSMI[25]; PADSEL=2
PSMI[38]; PADSEL=1
—
ETC[3]
Port E
E[0]
E[2]
PCR[64]
PCR[66]
SIUL
ADC_1
SIUL
—
—
—
—
ALT0
—
GPI[64]
AN[5]3
GPI[66]
AN[5]3
—
—
—
—
—
—
—
—
—
—
68
49
T13
U6
ALT0
—
ADC_0
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
E[4]
E[5]
PCR[68]
PCR[69]
PCR[70]
PCR[71]
PCR[73]
PCR[74]
PCR[75]
PCR[76]
PCR[77]
SIUL
ADC_0
SIUL
—
ALT0
—
GPI[68]
AN[7]3
—
—
—
—
42
44
46
48
61
63
U4
—
—
—
ALT0
—
GPI[69]
AN[8]3
—
—
—
—
—
—
—
—
—
M
—
—
—
—
—
—
—
S
T5
ADC_0
SIUL
—
—
E[6]
—
ALT0
—
GPI[70]
AN[4]3
—
—
R6
ADC_0
SIUL
—
—
E[7]
—
—
ALT0
—
GPI[71]
AN[6]3
—
—
T6
ADC_0
SIUL
—
E[9]
—
ALT0
—
GPI[73]
AN[7]3
—
—
T10
T11
ADC_1
SIUL
—
—
E[10]
E[11]
E[12]
E[13]
—
ALT0
—
GPI[74]
AN[8]3
—
—
—
ADC_1
SIUL
—
—
—
ALT0
—
GPI[75]
AN[4]3
—
65 U11
ADC_1
SIUL
—
—
—
ALT0
—
GPI[76]
AN[6]3
—
—
67
T12
ADC_1
SIUL
—
—
GPIO[77]
ETC[5]
CS3
—
ALT0
ALT1
ALT2
—
GPIO[77]
ETC[5]
—
—
Pull down
117 D12
eTimer_0
DSPI_2
SIUL
PSMI[8]; PADSEL=1
—
EIRQ[25]
GPIO[78]
ETC[5]
EIRQ[26]
—
E[14]
PCR[78]
SIUL
GPIO[78]
ETC[5]
—
ALT0
ALT1
—
—
Pull down
M
S
119 B12
eTimer_1
SIUL
PSMI[14]; PADSEL=3
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
E[15]
PCR[79]
SIUL
DSPI_0
SIUL
GPIO[79]
CS1
ALT0
ALT1
—
GPIO[79]
—
—
—
—
Pull down
M
S
121 B11
133 D7
139 B5
—
EIRQ[27]
Port F
F[0]
PCR[80]
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[80]
A[1]
ALT0
ALT1
—
GPIO[80]
A[1]
—
Pull down
M
S
PSMI[21]; PADSEL=2
—
ETC[2]
EIRQ[28]
GPIO[83]
—
PSMI[37]; PADSEL=1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F[3]
F[4]
F[5]
F[6]
F[7]
F[8]
F[9]
F[10]
PCR[83]
PCR[84]
PCR[85]
PCR[86]
PCR[87]
PCR[88]
PCR[89]
PCR[90]
SIUL
GPIO[83]
CS6
ALT0
ALT1
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
M
F
F
F
F
F
F
F
S
S
S
S
S
S
S
S
DSPI_0
SIUL
GPIO[84]
MDO[3]
GPIO[85]
MDO[2]
GPIO[86]
MDO[1]
GPIO[87]
MCKO
GPIO[84]
—
4
5
D2
D1
E2
J1
NPC
SIUL
GPIO[85]
—
NPC
SIUL
GPIO[86]
—
8
NPC
SIUL
GPIO[87]
—
19
20
23
24
NPC
SIUL
GPIO[88]
MSEO[1]
GPIO[89]
MSEO[0]
GPIO[90]
EVTO
GPIO[88]
—
K2
K1
L1
NPC
SIUL
GPIO[89]
—
NPC
SIUL
GPIO[90]
—
NPC
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
F[11]
F[12]
PCR[91]
PCR[92]
SIUL
NPC
GPIO[91]
EVTI
ALT0
ALT2
ALT0
ALT1
—
GPIO[91]
—
—
Pull down
Pull down
M
S
25
L2
—
SIUL
GPIO[92]
ETC[3]
—
GPIO[92]
ETC[3]
EIRQ[30]
GPIO[93]
ETC[4]
EIRQ[31]
GPIO[94]
—
—
M
M
S
S
106 C17
112 B14
eTimer_1
SIUL
PSMI[12]; PADSEL=2
—
F[13]
PCR[93]
SIUL
GPIO[93]
ETC[4]
—
ALT0
ALT1
—
—
Pull down
eTimer_1
SIUL
PSMI[13]; PADSEL=3
—
F[14]
F[15]
PCR[94]
PCR[95]
SIUL
GPIO[94]
TXD
ALT0
ALT1
ALT0
—
—
Pull down
Pull down
M
M
S
S
115 C13
113 D13
LINFlexD_1
SIUL
—
GPIO[95]
—
GPIO[95]
RXD
—
LINFlexD_1
PSMI[32]; PADSEL=2
FCCU
FCCU_
F[0]
—
—
FCCU
FCCU
F[0]
F[1]
ALT0
ALT0
F[0]
—
—
—
—
S
S
S
S
38
R2
FCCU_
F[1]
F[1]
141 C4
102 E16
Port G
G[2]
G[3]
PCR[98]
PCR[99]
SIUL
FlexPWM_0
DSPI_1
GPIO[98]
X[2]
ALT0
ALT1
ALT2
ALT0
ALT1
—
GPIO[98]
X[2]
—
Pull down
Pull down
M
M
S
S
PSMI[29]; PADSEL=1
—
CS1
—
SIUL
GPIO[99]
A[2]
GPIO[99]
A[2]
—
104 D17
FlexPWM_0
eTimer_0
PSMI[22]; PADSEL=2
PSMI[7]; PADSEL=3
—
ETC[4]
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
G[4]
G[5]
PCR[100]
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[100]
B[2]
ALT0
ALT1
—
GPIO[100]
B[2]
—
Pull down
M
S
100 F17
85 N17
PSMI[26]; PADSEL=2
—
ETC[5]
GPIO[101]
X[3]
PSMI[8]; PADSEL=3
PCR[101]
GPIO[101]
X[3]
ALT0
ALT1
ALT2
ALT0
ALT1
ALT0
ALT1
ALT0
ALT1
ALT2
—
—
Pull down
M
S
FlexPWM_0
DSPI_2
SIUL
PSMI[30]; PADSEL=2
CS3
—
—
G[6]
G[7]
G[8]
PCR[102]
PCR[103]
PCR[104]
GPIO[102]
A[3]
GPIO[102]
A[3]
—
Pull down
Pull down
Pull down
M
M
M
S
S
S
98 G17
83 P17
81 P16
FlexPWM_0
SIUL
PSMI[23]; PADSEL=3
GPIO[103]
B[3]
GPIO[103]
B[3]
FlexPWM_0
SIUL
PSMI[27]; PADSEL=3
GPIO[104]
DBG0
CS1
GPIO[104]
—
—
FlexRay
DSPI_0
FlexPWM_0
SIUL
—
—
—
—
FAULT[0]
EIRQ[21]
GPIO[105]
—
PSMI[16]; PADSEL=2
—
—
—
G[9]
PCR[105]
SIUL
GPIO[105]
DBG1
CS1
ALT0
ALT1
ALT2
—
—
Pull down
M
M
S
S
79 R17
FlexRay
DSPI_1
FlexPWM_0
SIUL
—
—
—
—
FAULT[1]
EIRQ[29]
GPIO[106]
—
PSMI[17]; PADSEL=2
—
—
—
G[10] PCR[106]
SIUL
GPIO[106]
DBG2
CS3
ALT0
ALT1
ALT2
—
—
Pull down
77 P15
FlexRay
DSPI_2
FlexPWM_0
—
—
—
—
FAULT[2]
PSMI[18]; PADSEL=1
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
G[11] PCR[107]
SIUL
FlexRay
FlexPWM_0
SIUL
GPIO[107]
DBG3
ALT0
ALT1
—
GPIO[107]
—
—
Pull down
M
S
75 U15
—
—
FAULT[3]
GPIO[108]
—
PSMI[19]; PADSEL=2
G[12] PCR[108]
G[13] PCR[109]
G[14] PCR[110]
G[15] PCR[111]
GPIO[108]
MDO[11]
GPIO[109]
MDO[10]
GPIO[110]
MDO[9]
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
—
—
—
—
—
—
—
—
Pull down
Pull down
Pull down
Pull down
F
F
F
F
S
S
S
S
—
—
—
—
F2
H1
A6
J2
NPC
SIUL
GPIO[109]
—
NPC
SIUL
GPIO[110]
—
NPC
SIUL
GPIO[111]
MDO[8]
GPIO[111]
—
NPC
Port H
H[0]
H[1]
H[2]
H[3]
H[4]
PCR[112]
PCR[113]
PCR[114]
PCR[115]
PCR[116]
SIUL
NPC
GPIO[112]
MDO[7]
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT1
ALT2
GPIO[112]
—
—
Pull down
Pull down
Pull down
Pull down
Pull down
F
F
S
S
S
S
S
—
—
—
—
—
A5
F1
—
SIUL
GPIO[113]
MDO[6]
GPIO[113]
—
—
NPC
—
SIUL
GPIO[114]
MDO[5]
GPIO[114]
—
—
F
A4
NPC
—
SIUL
GPIO[115]
MDO[4]
GPIO[115]
—
—
F
G1
L16
NPC
—
SIUL
GPIO[116]
X[0]
GPIO[116]
X[0]
—
M
FlexPWM_1
eTimer_2
—
ETC[0]
ETC[0]
PSMI[39]; PADSEL=0
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
H[5]
H[6]
H[7]
H[8]
H[9]
PCR[117]
SIUL
FlexPWM_1
DSPI_0
GPIO[117]
A[0]
ALT0
ALT1
ALT3
ALT0
ALT1
ALT3
ALT0
ALT1
ALT2
ALT0
ALT1
ALT3
ALT0
ALT1
ALT3
ALT0
ALT1
ALT2
ALT0
ALT1
ALT0
ALT1
ALT0
ALT1
ALT2
GPIO[117]
A[0]
—
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
M
S
—
—
—
—
—
—
M17
H17
K16
K15
G16
A11
—
CS4
—
—
PCR[118]
PCR[119]
PCR[120]
PCR[121]
SIUL
GPIO[118]
B[0]
GPIO[118]
B[0]
—
M
M
M
M
M
S
S
S
S
S
FlexPWM_1
DSPI_0
—
CS5
—
—
SIUL
GPIO[119]
X[1]
GPIO[119]
X[1]
—
FlexPWM_1
eTimer_2
SIUL
—
ETC[1]
GPIO[120]
A[1]
ETC[1]
GPIO[120]
A[1]
PSMI[40]; PADSEL=0
—
FlexPWM_1
DSPI_0
—
CS6
—
—
SIUL
GPIO[121]
B[1]
GPIO[121]
B[1]
—
FlexPWM_1
DSPI_0
—
CS7
—
—
H[10] PCR[122]
SIUL
GPIO[122]
X[2]
GPIO[122]
X[2]
—
FlexPWM_1
eTimer_2
SIUL
—
ETC[2]
GPIO[123]
A[2]
ETC[2]
GPIO[123]
A[2]
—
H[11] PCR[123]
H[12] PCR[124]
H[13] PCR[125]
—
Pull down
Pull down
Pull down
M
M
M
S
S
S
—
—
—
C11
B10
G15
FlexPWM_1
SIUL
—
GPIO[124]
B[2]
GPIO[124]
B[2]
—
FlexPWM_1
SIUL
—
GPIO[125]
X[3]
GPIO[125]
X[3]
—
FlexPWM_1
eTimer_2
—
ETC[3]
ETC[3]
PSMI[42]; PADSEL=0
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
H[14] PCR[126]
H[15] PCR[127]
SIUL
GPIO[126]
A[3]
ALT0
ALT1
ALT2
ALT0
ALT1
ALT2
GPIO[126]
A[3]
—
—
—
—
—
—
Pull down
M
S
—
—
A12
FlexPWM_1
eTimer_2
SIUL
ETC[4]
GPIO[127]
B[3]
ETC[4]
GPIO[127]
B[3]
Pull down
M
M
M
M
S
S
S
S
J17
FlexPWM_1
eTimer_2
ETC[5]
ETC[5]
Port I
I[0]
I[1]
I[2]
PCR[128]
PCR[129]
PCR[130]
SIUL
eTimer_2
DSPI_0
GPIO[128]
ETC[0]
CS4
ALT0
ALT1
ALT2
—
GPIO[128]
ETC[0]
—
—
Pull down
Pull down
Pull down
—
—
—
C9
C12
F16
PSMI[39]; PADSEL=1
—
FlexPWM_1
SIUL
—
FAULT[0]
GPIO[129]
ETC[1]
—
—
GPIO[129]
ETC[1]
CS5
ALT0
ALT1
ALT2
—
—
eTimer_2
DSPI_0
PSMI[40]; PADSEL=1
—
FlexPWM_1
SIUL
—
FAULT[1]
GPIO[130]
ETC[2]
—
—
GPIO[130]
ETC[2]
CS6
ALT0
ALT1
ALT2
—
—
eTimer_2
DSPI_0
PSMI[41]; PADSEL=1
—
—
FlexPWM_1
—
FAULT[2]
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
PCR
Peripheral
Input mux select
144 257
pkg pkg
= 1
= 0
I[3]
PCR[131]
SIUL
eTimer_2
DSPI_0
CTU_0
FlexPWM_1
SIUL
GPIO[131]
ETC[3]
CS7
ALT0
ALT1
ALT2
ALT3
—
GPIO[131]
ETC[3]
—
—
Pull down
M
S
—
E17
PSMI[42]; PADSEL=1
—
—
—
—
—
EXT_TGR
—
—
FAULT[3]
GPIO[132]
—
RDY
PCR[132]
GPIO[132]
RDY
ALT0
ALT2
Pull down
F
S
—
K3
(cut2
only)
(cut2 (cut2 only)
only)
NPC
1
Programmable via the SRC (Slew Rate Control) bit in the respective Pad Configuration Register; S = Slow, M = Medium, F = Fast, SYM = Symmetric (for
FlexRay)
2
3
The default function of this pin out of reset is ALT1 (TDO).
Analog
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for this device.
This device is designed to operate at 120 MHz. The electrical specifications are preliminary and are from previous designs,
design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the
product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
The “Symbol” column of the electrical parameter and timings tables contains an additional column containing “SR”, “CC”, “P”,
“C”, “T”, or “D”.
•
•
•
“SR” identifies system requirements—conditions that must be provided to ensure normal device operation. An
example is the input voltage of a voltage regulator.
“CC” identifies controller characteristics—indicating the characteristics and timing of the signals that the chip
provides.
“P”, “C”, “T”, or “D” apply only to controller characteristics—specifications that define normal device operation.
They specify how each characteristic is guaranteed.
— P: parameter is guaranteed by production testing of each individual device.
— C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant
sample size across process variations.
— T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical
conditions unless otherwise noted. All values are shown in the typical (“typ”) column are within this category.
— D: parameters are derived mainly from simulations.
3.2
Absolute maximum ratings
1
Table 8. Absolute maximum ratings
Symbol
Parameter
Conditions
Min
Max2
Unit
VDD_HV_REG SR 3.3 V voltage regulator supply voltage
VSS_HV_REG SR 3.3 V voltage regulator reference voltage
—
—
—
—
—
—
—
–0.3
–0.1
–0.3
–0.1
–0.3
–0.1
–0.3
4.03, 4
V
V
V
V
V
V
V
0.1
VDD_HV_IOx
VSS_HV_IOx
SR 3.3 V input/output supply voltage
SR Input/output ground voltage
3.63, 4
0.1
VDD_HV_FLA SR 3.3 V flash supply voltage
VSS_HV_FLA SR Flash memory ground
3.63, 4
0.1
VDD_HV_OSC SR 3.3 V crystal oscillator amplifier supply
voltage
4.03, 4
VSS_HV_OSC SR 3.3 V crystal oscillator amplifier reference
voltage
—
—
—
—
–0.1
–0.3
–0.1
–0.3
0.1
6.0
V
V
V
V
5
VDD_HV_ADR0 SR 3.3 V / 5.0 V ADC_0 high reference voltage
VDD_HV_ADR1
3.3 V / 5.0 V ADC_1 high reference voltage
VSS_HV_ADR0 SR ADC_0 ground and low reference voltage
VSS_HV_ADR1 ADC_1 ground and low reference voltage
0.1
VDD_HV_ADV SR 3.3 V ADC supply voltage
4.03, 4
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
73
Preliminary—Subject to Change Without Notice
Electrical characteristics
Symbol
1
Table 8. Absolute maximum ratings (continued)
Parameter
Conditions
Min
Max2
Unit
VSS_HV_ADV SR 3.3 V ADC supply ground
—
—
–0.1
0.5
0.1
V
TVDD
SR Slope characteristics on all VDD during
3.0 × 106 V/µs
(3.0 V/sec)
power up
VIN
SR Voltage on any pin with respect to ground
—
Relative to VDD
—
–0.3
–0.3
–10
6.0
VDD + 0.36
10
V
(VSS_HV_IOx
)
IINJPAD
IINJSUM
TSTG
SR Injected input current on any pin during
overload condition
mA
mA
°C
SR Absolute sum of all injected input currents
during overload condition
—
—
–50
–55
50
SR Storage temperature
150
1
2
Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device
stress have not yet been determined.
3
4
5
5.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining.
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated be operated at different voltages, and need to be supplied by
the same voltage source.
6
Only when VDD < 5.2 V.
3.3
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Symbol
Parameter
Conditions
Min
Max1 Unit
VDD_HV_REG
VSS_HV_REG
VDD_HV_IOx
VSS_HV_IOx
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_OSC
VSS_HV_OSC
SR 3.3 V voltage regulator supply voltage
SR 3.3 V voltage regulator reference voltage
SR 3.3 V input/output supply voltage
SR Input/output ground voltage
—
—
—
—
—
—
—
—
—
3.0
0
3.6
0
V
V
V
V
V
V
V
V
V
3.0
0
3.6
0
SR 3.3 V flash supply voltage
3.0
0
3.6
0
SR Flash memory ground
SR 3.3 V crystal oscillator amplifier supply voltage
SR 3.3 V crystal oscillator amplifier reference voltage
3.0
0
3.6
0
2
VDD_HV_ADR0
VDD_HV_ADR1
SR 3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
4.5 to 5.5 or
3.0 to 3.6
VDD_HV_ADV
SR 3.3 V ADC supply voltage
—
—
3.0
3.6
0
V
V
VSS_HV_AD0
VSS_HV_AD1
SR ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
0
VSS_HV_ADV
SR 3.3 V ADC supply ground
—
—
0
0
V
V
3
VDD_LV_REGCOR SR Internal supply voltage
—
—
PXS20 Microcontroller Data Sheet, Rev. 1
74
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 9. Recommended operating conditions (3.3 V) (continued)
Symbol
Parameter
Conditions
Min
Max1 Unit
4
VSS_LV_REGCOR SR Internal reference voltage
—
—
—
—
—
0
—
0
0
—
0
V
V
2
VDD_LV_CORx
SR Internal supply voltage
3
VSS_LV_CORx
SR Internal reference voltage
SR Internal supply voltage
V
2
VDD_LV_PLL
—
0
—
0
V
3
VSS_LV_PLL
SR Internal reference voltage
SR Ambient temperature under bias
SR Junction temperature under bias
V
TA
TJ
fCPU
120 MHz
—
–40
–40
125
150
°C
°C
1
2
3
4
Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics
and I/Os DC electrical specification may not be guaranteed.
VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same
voltage source.
Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced
by an on-chip voltage regulator.
For the device to function properly, the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds
(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one
is used.
3.4
Thermal characteristics
1
Table 10. Thermal characteristics for 144 LQFP package
Symbol
Parameter
Conditions
Value Unit
RJA
D
Thermal resistance, junction-to-ambient natural Single layer board – 1s
42 °C/W
34
convection2
Four layer board – 2s2p
RJMA
D
Thermal resistance, junction-to-ambient forced Single layer board – 1s
34 °C/W
28
convection at 200 ft/min
Four layer board – 2s2p
RJB
RJC
JT
D
D
D
Thermal resistance junction-to-board3
Thermal resistance junction-to-case4
Junction-to-package-top natural convection5
—
—
—
22 °C/W
8
3
°C/W
°C/W
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3
4
5
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
75
Preliminary—Subject to Change Without Notice
Electrical characteristics
Symbol
1
Table 11. Thermal characteristics for 257 MAPBGA package
Parameter Conditions
Value Unit
RJA
D
Thermal resistance junction-to-ambient natural Single layer board – 1s
46 °C/W
26
convection2
Four layer board – 2s2p
RJMA
D
Thermal resistance, junction-to-ambient forced Single layer board – 1s
37 °C/W
22
convection at 200 ft/min
Four layer board – 2s2p
RJB
RJC
JT
D
D
D
Thermal resistance junction-to-board3
Thermal resistance junction-to-case4
Junction-to-package-top natural convection5
—
—
—
13 °C/W
8
2
°C/W
°C/W
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3
4
5
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
3.4.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, T , can be obtained from Equation 1:
J
T = T + (R
× P )
Eqn. 1
J
A
JA
D
where:
o
T
= ambient temperature for the package ( C)
A
o
R
= junction to ambient thermal resistance ( C/W)
= power dissipation in the package (W)
JA
P
D
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance
and a case to ambient thermal resistance:
R
= R
+ R
CA
Eqn. 2
JA
JC
where:
R
R
R
= junction to ambient thermal resistance (°C/W)
= junction to case thermal resistance (°C/W)
= case to ambient thermal resistance (°C/W)
JA
JC
CA
PXS20 Microcontroller Data Sheet, Rev. 1
76
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
R
is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
JC
ambient thermal resistance, R
. For instance, the user can change the size of the heat sink, the air flow around the device, the
CA
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at
JT
the top center of the package case using Equation 3:
T = T + ( × P )
Eqn. 3
J
T
JT
D
where:
T
= thermocouple temperature on top of the package (°C)
= thermal characterization parameter (°C/W)
= power dissipation in the package (W)
T
JT
P
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
3.4.1.1
References
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134 USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
3.5
Electromagnetic Interference (EMI) characteristics (cut1)
The characteristics in Table 13 were measured using:
•
•
•
Device configuration, tet conditions, and EM testing per standard IEC61967-2
Supply voltage of 3.3 V DC
Ambient temperature of 25 C
The configuration information referenced in Table 13 is explained in Table 12.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
77
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 12. EMI configuration summary
Description
Configuration name
Configuration A
• High emission = all pads have max slew rate, LVDS pads running at 40 MHz
• Oscillator frequency = 40 MHz
• System bus frequency = 80 MHz
• No PLL frequency modulation
• IEC level I ( 36 dBV)
Configuration B
• Reference emission = pads use min, mid and max slew rates, LVDS pads disabled
• Oscillator frequency = 40 MHz
• System bus frequency = 80 MHz
• 2% PLL frequency modulation
• IEC level K( 30 dBV)
Table 13. EMI emission testing specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VEME CC Radiated emissions
Configuration A; frequency range
150 kHz–50 MHz
—
16
—
dBV
Configuration A; frequency range
50–150 MHz
—
—
—
—
—
—
—
16
32
25
15
21
30
24
—
—
—
—
—
—
—
Configuration A; frequency range
150–500 MHz
Configuration A; frequency range
500–1000 MHz
Configuration B; frequency range
50–150 MHz
Configuration B; frequency range
50–150 MHz
Configuration B; frequency range
150–500 MHz
Configuration B; frequency range
500–1000 MHz
3.6
Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin).
This test conforms to the AEC-Q100-002/-003/-011 standard.
PXS20 Microcontroller Data Sheet, Rev. 1
78
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
1, 2
Table 14. ESD ratings
No.
Symbol
Parameter
Conditions
Class Max value3
Unit
1
VESD(HBM)
SR Electrostatic discharge TA = 25 °C
H1C
2000
V
(Human Body Model)
conforming to AEC-Q100-002
2
3
VESD(MM)
SR Electrostatic discharge TA = 25 °C
M2
200
V
V
(Machine Model)
conforming to AEC-Q100-003
VESD(CDM)
SR Electrostatic discharge TA = 25 °C
C3A
500
(Charged Device Model) conforming to AEC-Q100-011
750 (corners)
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
3
Data based on characterization results, not tested in production.
3.7
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 15. Latch-up results
No.
Symbol
LU
Parameter
SR Static latch-up class
Conditions
Class
1
TA = 125 °C conforming to JESD 78
II level A
3.8
Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
•
•
•
•
•
•
•
•
•
•
High power regulator HPREG1 (internal ballast to support core current)
High power regulator HPREG2 (external NPN to support core current)
Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (V
)
DDIO
Low voltage detector (LVD_MAIN_2) for 3.3 V supply (V
)
DDREG
Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (V
)
DDFLASH
Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPV
)
DD
Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN
High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPV
)
DD
High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.
Power on Reset (POR)
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when external NPN transistor is present on
board to supply core current. The PXS20 always powers up using HPREG1 if an external NPN transistor is present. Then the
PXS20 makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational, the
controller part of HPREG1 is switched off. The following bipolar transistors are supported:
•
BCP68 from ON Semiconductor
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
79
Preliminary—Subject to Change Without Notice
Electrical characteristics
BCX68 from Infineon
•
Table 16. Voltage regulator electrical specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SR External decoupling/
Min, max values shall be
granted with respect to
tolerance, voltage,
temperature, and aging
variations.
12
—
40
µF
stability capacitor
SR Combined ESR of
external capacitor
—
0.01
5
—
—
0.10
—
SR Number of pins for
external decoupling/
stability capacitor
—
—
CV1V2 SR Total capacitance on
1.2 V pins
Ceramic capacitors,
taking into account
300
—
900
nF
tolerance, aging, voltage
and temperature variation
tSU
—
Start-up time after main
supply stabilization
Cload = 10 µF × 4
—
—
—
—
2.5
2.9
ms
V
Main High Voltage Power -
Low Voltage Detection,
upper threshold
—
—
—
D
D
Main supply low voltage
detector, lower threshold
—
2.6
—
—
—
V
V
Digitalsupplyhighvoltage Before a destructive reset
Cut2: 1.355
Cut1: 1.5
detector upper threshold
initialization phase
completion
Cut2: 1.495
After a destructive reset
initialization phase
completion
Cut1: 1.32
Cut2: 1.43
—
—
—
—
—
—
Cut1: 1.4
Cut2: 1.47
—
D
Digitalsupplyhighvoltage Before a destructive reset
Cut1: 1.330
Cut2: 1.315
Cut1: 1.4
Cut2: 1.455
V
detector lower threshold
initialization phase
completion
After a destructive reset
initialization phase
completion
Cut2: 1.39
1.080
Cut2: 1.43
—
—
—
D
D
D
Digital supply low voltage After a destructive reset
Cut1: 1.110
Cut2: 1.12
V
V
V
detector lower threshold
initialization phase
completion
Digital supply low voltage After a destructive reset
Cut1: 1.17
Cut2: 1.16
Cut1: 1.19
Cut2: 1.20
detector upper threshold
initialization phase
completion
POR rising/ falling supply
threshold voltage
—
1.6
2.6
PXS20 Microcontroller Data Sheet, Rev. 1
80
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 16. Voltage regulator electrical specifications (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
—
SR Supply ramp rate
—
3
—
—
0.5 ×106
—
V/s
µs
D
D
D
LVD_MAIN: Time
constant of RC filter at
LVD input
3.3V noise rejection at the
input of
1.1
LVD comparator
—
—
HVD_DIG: Time constant 1.2V noise rejection at the
of RC filter at LVD input
0.1
0.1
—
—
—
—
µs
µs
input of
LVD comparator
LVD_DIG: Time constant
of RC filter at LVD input
1.2V noise rejection at the
input of
LVD comparator
VDD
BCP68
BCRTL
V1V2 ring on board
Lb
Rb
ESR
Rs
C
v1v2
Cext
Cint
V1V2 pin
PXS20
Figure 5. BCP68 board schematic example
NOTE
The combined ESR of the capacitors used on 1.2 V pins (V1V2 in the picture) shall be in
the range of 30 m to 150 m. The minimum value of the ESR is constrained by the
resonance caused by the external components, bonding inductance, and internal
decoupling. The minimum ESR is required to avoid the resonance and make the regulator
stable.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
81
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.9
DC electrical characteristics
Table 17 gives the DC electrical characteristics at 3.3 V (3.0 V < V
< 3.6 V).
DD_HV_IOx
1
Table 17. DC electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIL
D Minimum low level input voltage
P Maximum level input voltage
P Minimum high level input voltage
D Maximum high level input voltage
T Schmitt trigger hysteresis
—
–0.12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
V
—
—
0.35 VDD_HV_IOx
VIH
—
0.65 VDD_HV_IOx
—
V
VIH
—
—
—
0.1 VDD_HV_IOx
—
VDD_HV_IOx + 0.12
V
VHYS
VOL_S
VOH_S
VOL_M
VOH_M
VOL_F
VOH_F
—
0.5
—
V
P Slow, low level output voltage
P Slow, high level output voltage
P Medium, low level output voltage
P Medium, high level output voltage
P Fast, high level output voltage
P Fast, high level output voltage
IOL = 1.5 mA
V
IOH = –1.5 mA VDD_HV_IOx – 0.8
IOL = 2 mA
IOH = –2 mA VDD_HV_IOx – 0.8
IOL = 1.5 mA
IOH = –1.5 mA VDD_HV_IOx – 0.8
V
—
0.5
—
V
V
—
0.5
—
V
V
VOL_SYM P Symmetric, high level output voltage IOL = 1.5 mA
—
0.5
—
V
VOH_SYM P Symmetric, high level output voltage IOH = –1.5 mA VDD_HV_IOx – 0.8
V
IINJ
IPU
T DC injection current per pin
P Equivalent pull-up current
—
–1
–130
—
1
mA
µA
VIN = VIL
VIN = VIH
VIN = VIL
VIN = VIH
—
–10
—
IPD
P Equivalent pull-down current
10
µA
—
130
1
IIL
P Input leakage current
(all bidirectional ports)
TJ = –40 to
+150 °C
-1
A
Input leakage current
(all ADC input-only ports)
-0.5
-1
—
—
0.5
1
Input leakage current
(shared ADC input-only ports)
VILR
VIHR
VHYSR
VOLR
IPD
P RESET, low level input voltage
P RESET, high level input voltage
D RESET, Schmitt trigger hysteresis
D RESET, low level output voltage
D RESET, equivalent pull-down current
—
—
–0.12
—
—
—
—
—
—
0.35 VDD_HV_IOx
V
V
0.65 VDD_HV_IOx
VDD_HV_IOx+0.12
—
0.1 VDD_HV_IOx
—
0.5
—
V
IOL = 2 mA
VIN = VIL
VIN = VIH
—
10
—
V
µA
130
1
2
These specifications are design targets and subject to change per device characterization.
“SR” parameter values must not exceed the absolute maximum ratings shown in Table 8.
PXS20 Microcontroller Data Sheet, Rev. 1
82
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.10 Supply current characteristics (cut2)
Current consumption data is given in Table 18. These specifications are design targets and are subject to change per device
characterization.
Table 18. Current consumption characteristics
Symbol
Parameter
Conditions
1.2 V supplies
Min
Typ
Max
Unit
IDD_LV_FULL
+ IDD_LV_PLL
T Operating current
—
—
50 mA+
2.18 mA*fCPU[MHz]
mA
TJ = ambient
VDD_LV_COR = 1.32 V
1.2 V supplies
TJ = 150 C
VDD_LV_COR = 1.32 V
—
—
—
—
—
—
—
—
—
—
—
—
80 mA+
2.50 mA*fCPU[MHz]
IDD_LV_TYP
+ IDD_LV_PLL
T Operating current
P Operating current
T Operating current
1.2 V supplies
TJ = ambient
VDD_LV_COR = 1.32 V
26 mA+
2.10 mA*fCPU[MHz]
mA
mA
mA
1.2 V supplies
TJ = 150 C
VDD_LV_COR = 1.32 V
41 mA+
2.30 mA*fCPU[MHz]
IDD_LV_TYP
+ IDD_LV_PLL
1.2 V supplies
TJ = ambient
VDD_LV_COR = 1.32 V
279 mA
318 mA
TBD
1
1.2 V supplies
TJ = 150 C
VDD_LV_COR = 1.32 V
IDD_LV_BIST
1.2 V supplies during
LBIST (full LBIST
configuration)
+ IDD_LV_PLL
TJ = ambient
VDD_LV_COR = 1.32 V
1.2 V supplies
—
—
TBD
TJ = 150 C
VDD_LV_COR = 1.32 V
IDD_LV_STOP
T Operating current in TJ = ambient
DD STOP mode DD_LV_COR = 1.32 V
—
—
—
—
—
—
—
—
—
—
—
—
50
57
80
58
64
72
mA
mA
V
V
T
TJ = 55 C
VDD_LV_COR = 1.32 V
P
TJ = 150 C
VDD_LV_COR = 1.32 V
IDD_LV_HALT
T Operating current in TJ = ambient
DD HALT mode DD_LV_COR = 1.32 V
V
V
T
TJ = 55 C
VDD_LV_COR = 1.32 V
P
TJ = 150 C
VDD_LV_COR = 1.32 V
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
83
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 18. Current consumption characteristics (continued)
Symbol
Parameter
Conditions
TJ = 150 C
Min
Typ
Max
Unit
2,3
IDD_HV_ADC
T Operating current
—
—
10
mA
120 MHz
ADC operating at 60 MHz
VDD_HV_ADC = 3.6 V
3
IDD_HV_AREF
T Operating current
TJ = 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_REF = 3.6 V
—
—
—
—
3
5
mA
TJ = 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_REF = 5.5 V
IDD_HV_OSC
T Operating current
T Operating current
TJ = 150 C
3.3 V supplies
120 MHz
—
—
—
—
900
4
A
4
IDD_HV_FLASH
TJ = 150 C
3.3 V supplies
120 MHz
mA
1
2
Enabled Modules in 'Typical mode': FlexPWM0, ETimer0/1/2, CTU, SWG, DMA, FlexCAN0/1, LINFlex, ADC1, DSPI0/1, PIT,
CRC, PLL0/1, I/O supply current excluded
Internal structures hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the maximum
injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications.
3
4
This value is the total current for both ADCs.
VFLASH is only available in the calibration package.
3.11 Temperature sensor electrical characteristics
Table 19. Temperature sensor electrical characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
—
P
Accuracy
TJ = –40 °C to TA = 25 °C
TJ = TA to 125 °C
—
–10
–7
4
10
7
°C
°C
µs
TS
D
Minimum sampling period
—
3.12 Main oscillator electrical characteristics
The device provides an oscillator/resonator driver. Figure 6 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
PXS20 Microcontroller Data Sheet, Rev. 1
84
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
EXTAL
C
L
R
EXTAL
P
XTAL
C
L
DEVICE
V
DD
I
EXTAL
R
XTAL
DEVICE
XTAL
DEVICE
Figure 6. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
MTRANS
1
0
V
XTAL
1/f
XOSCHS
V
XOSCHS
90%
10%
V
XOSCHSOP
T
valid internal clock
XOSCHSSU
Figure 7. Main oscillator electrical characteristics
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
85
Preliminary—Subject to Change Without Notice
Electrical characteristics
×
Table 20. Main oscillator electrical characteristics
Value
Typ
Symbol
Parameter
Conditions1
Unit
Min
Max
fXOSCHS SR Oscillator frequency
—
4.0
4.5
—
—
40.0
MHz
gmXOSCHS P Oscillator
transconductance
VDD = 3.3 V ±10%
13.25
mA/V
VXOSCHS
D Oscillation amplitude
fOSC = 4, 8, 10, 12, 16 MHz
1.3
1.1
—
—
—
—
—
—
V
V
fOSC = 40 MHz
—
VXOSCHSOP D Oscillation operating
point
0.82
IXOSCHS
D Oscillator consumption
—
—
—
—
—
—
3.5
mA
ms
TXOSCHSSU
T
Oscillator start-up time fOSC = 4, 8, 10, 12 MHz2
OSC = 16, 40 MHz2
—
—
6
2
f
VIH
VIL
SR Input high level CMOS
Schmitt Trigger
Oscillator bypass mode
0.65 × VDD
VDD + 0.4
V
V
SR Input low level CMOS
Schmitt Trigger
Oscillator bypass mode
–0.4
—
0.35 × VDD
1
2
VDD = 3.3 V ±10%, TJ = –40 to +150 °C, unless otherwise specified.
The recommended configuration for maximizing the oscillator margin are:
XOSC_MARGIN = 0 for 4 MHz quartz
XOSC_MARGIN = 1 for 8/16/40 MHz quartz
3.13 FMPLL electrical characteristics
Table 21. FMPLL electrical characteristics
Symbol
Parameter
Conditions
Crystal reference
Min
Typ
Max Unit
fREF_CRYSTAL D FMPLL reference frequency
fREF_EXT
4
—
40 MHz
range1
fPLL_IN
D Phase detector input frequency
range (after pre-divider)
—
—
4
—
—
—
16 MHz
1202 MHz
150 MHz
fFMPLLOUT D Clock frequency range in normal
mode
4
fFREE
P Free running frequency
Measured using clock division
20
(typically 16)
fsys
D On-chip FMPLL frequency2
D System clock period
—
16
—
—
—
—
—
—
—
120 MHz
1 / fsys ns
3.7 MHz
56
tCYC
—
Lower limit
Upper limit
—
fLORL
fLORH
D Loss of reference frequency
window3
1.6
24
20
—
fSCM
D Self-clocked mode frequency4,5
P Lock time
TBD MHz
tLOCK
Stable oscillator (fPLLIN = 4 MHz),
stable VDD
200
µs
PXS20 Microcontroller Data Sheet, Rev. 1
86
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 21. FMPLL electrical characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
tlpll
tdc
D FMPLL lock time 6, 7
—
—
—
40
–6
—
—
—
200
60
6
s
%
D Duty cycle of reference
CJITTER T CLKOUT period jitter8,9,10,11
Long-term jitter (avg. over 2 ms
interval), fSYS maximum
ns
tPKJIT T Single period jitter (peak to peak) PHI @ 120 MHz,
—
—
—
—
—
—
—
—
175
185
200
±6
ps
ps
ps
ns
Input clock @ 4 MHz
PHI @ 100 MHz,
Input clock @ 4 MHz
PHI @ 80 MHz,
Input clock @ 4 MHz
—
tLTJIT
T Long term jitter
PHI @ 16 MHz,
Input clock @ 4 MHz
—
fLCK
D Frequency LOCK range
D Frequency un-LOCK range
D Modulation Depth
—
–6
–18
6
%
fsys
fUL
—
18
%
fsys
fCS
fDS
Center spread
Down Spread
—
±0.25
–0.5
—
—
—
—
±2.012
-8.0
%
fsys
fMOD
D Modulation frequency13
100 kHz
1
2
3
Considering operation with FMPLL not bypassed.
With FM; the value does not include a possible +2% modulation
“Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self
clocked mode.
4
5
Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls
outside the fLOR window.
fVCO is the frequency at the output of the VCO; its range is 256–512 MHz.
fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.
fSYS = fVCOODF
This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this FMPLL, load capacitors should not exceed these limits.
6
7
This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control
bits in the synthesizer control register (SYNCR).
8
9
This value is determined by the crystal manufacturer and board design.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
10 Proper PC board layout procedures must be followed to achieve specifications.
11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
12 This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
13 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
87
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.14 16 MHz RC oscillator electrical characteristics
Table 22. RC oscillator electrical characteristics
Symbol
Parameter
Conditions
TJ = 25 °C
Min
Typ
Max Unit
fRC
P
P
RC oscillator frequency
—
—
16
—
—
MHz
%
RCMVAR
Fast internal RC oscillator variation with
—
±5
respect to fRC
.
3.15 ADC electrical characteristics
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
(2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
(5)
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal
)
Offset Error OSE
Figure 8. ADC characteristics and error definitions
3.15.1 Input Impedance and ADC Accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge
during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
PXS20 Microcontroller Data Sheet, Rev. 1
88
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being
S
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330 k is obtained
S
(R = 1 / (f C ), where fc represents the conversion rate at the considered channel). To minimize the error induced by the
EQ
C
S
voltage partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external
S
S
F
L
SW
AD
circuit must be designed to respect the Equation 4:
R + R + R + R
+ R
S
F
L
SW
AD
1
2
--------------------------------------------------------------------------
V
-- LSB
Eqn. 4
A
R
EQ
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (R
SW
and R ) can be neglected with respect to external resistances.
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
P2
A
F
P1
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 9. Input Equivalent Circuit
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are
F
P1
P2
initially charged at the source voltage V (refer to the equivalent circuit reported in Figure 9): A charge sharing phenomenon is
A
installed when the sampling phase is started (A/D switch close).
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
89
Preliminary—Subject to Change Without Notice
Electrical characteristics
Voltage Transient on CS
V
CS
V
A
V <0.5 LSB
V
A2
1
2
1 < (RSW + RAD) CS << TS
V
A1
2 = RL (CS + CP1 + CP2)
T
t
S
Figure 10. Transient Behavior during Sampling Phase
In particular two different transient periods can be distinguished:
• A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C
S
P1
P2
S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,
P2
P1
P
P1
P2
P
S
and the time constant is
C C
P
S
--------------------
= R
+ R
Eqn. 5
1
SW
AD
C + C
P
S
Equation 5 can again be simplified considering only C as an additional worst condition. In reality, the transient is
S
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T
is always much longer than the internal time constant:
S
R
+ R
C « T
Eqn. 6
1
SW
AD
S
S
The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance
P1
P2
S
A1
according to Equation 7:
V
C + C + C = V C + C
Eqn. 7
A1
S
P1
P2
A
P1
P2
•
A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance
F
R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality
L
P2
S
P1
would be faster), the time constant is:
R C + C + C
P1 P2
Eqn. 8
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time T , a constraints on R sizing is obtained:
S
L
10 = 10 R C + C + C T
P1 P2 S
Eqn. 9
2
L
S
PXS20 Microcontroller Data Sheet, Rev. 1
90
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Of course, R shall be sized also according to the current limitation constraints, in combination with R (source
L
S
impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V
F
F
P1 P2
S
A2
(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge
A1
balance assuming now C already charged at V ):
S
A1
V
C + C + C + C = V C + V C + C + C
P1 P2 A1 P1 P2
Eqn. 10
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to
F
F
provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of
S
A
F F
the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.
S
Analog Source Bandwidth (V )
A
T
f
2 R C (Conversion Rate vs. Filter Pole)
F F
C
Noise
f (Anti-aliasing Filtering Condition)
F
0
2 f f (Nyquist)
0
C
f
0
f
Anti-Aliasing Filter (f = RC Filter pole)
Sampled Signal Spectrum (f = conversion Rate)
C
F
f
f
f
C
F
0
f
f
Figure 11. Spectral representation of input signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),
0
F
according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater
C
0
than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T ,
C
C
S
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the
F
F
sampling time T , so the charge level on C cannot be modified by the analog signal source during the time in which the
S
S
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
S
voltage on C :
S
Eqn. 11
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A
P1
F
V
C
+ C + C + C
A2
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of
A
half a count, a constraint is evident on C value:
F
Eqn. 12
C
2048 C
F
S
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
91
Preliminary—Subject to Change Without Notice
Electrical characteristics
Symbol
Table 23. ADC conversion characteristics
Parameter
Conditions1
Min Typ Max Unit
fCK
SR ADC Clock frequency (depends on ADC
configuration)
—
3
—
60
MHz
(The duty cycle depends on AD_CK2
frequency)
fs
SR Sampling frequency
—
—
383
625
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.003 MHz
tsample
tconv
D Sample time4
60 MHz
TBD
—
—
ns
ns
D Conversion time5
6
CS
D ADC input sampling capacitance
D ADC input pin capacitance 1
D ADC input pin capacitance 2
D Internal resistance of analog source
—
—
—
7.32
5(7)
0.8
0.3
875
825
2
pF
6
CP1
—
pF
6
CP2
—
pF
6
RSW1
VREF range = 4.5 to 5.5 V
—
k
V
REF range = 3.0 to 3.6 V
—
6
RAD
D Internal resistance of analog source
P Integral non linearity
—
—
INL
DNL
OFS
GNE
—
–2
–1
–6
–6
LSB
LSB
LSB
LSB
P Differential non linearity8
—
2
T Offset error
—
6
T
Gain error
—
(single ADC channel)
150C
6
IS1WINJ
(cut2 only)
Max leakage
—
—
—
250
3
nA
Max positive/negative injection
–3
mA
IS1WWINJ
(cut2 only)
(double ADC channel)
150C
Max leakage
—
—
—
300
3.6
nA
Max positive/negative injection
|Vref_ad0 - Vref_ad1| <
150mV
–3.6
mA
SNR
THD
T
T
Signal-to-noise ratio
—
67
TBD
65
—
—
—
—
—
—
—
—
—
—
—
—
6
dB
dB
Total harmonic distortion
—
SINAD
ENOB
T Signal-to-noise and distortion
Effective number of bits
—
dB
T
—
10.5
–6
bits
LSB
LSB
LSB
LSB
TUEIS1WINJ P Total unadjusted error for IS1WINJ
(cut2 only)
Without current injection
With current injection
Without current injection
With current injection
T
–8
8
TUEIS1WWINJ P Total unadjusted error for IS1WWINJ
(cut2 only)
–8
8
T
–10
10
1
2
3
VDD = 3.3 V, TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF
.
AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
This is the maximum frequency that the analog portion of the ADC can attain. A sustained conversion at this frequency is not
possible.
PXS20 Microcontroller Data Sheet, Rev. 1
92
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
4
5
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance
of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time
tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample
depend on programming.
This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
6
7
8
See Figure 9.
For the 144-pin package.
No missing codes.
3.16 Flash memory electrical characteristics
Table 24. Flash memory program and erase electrical specifications
Factory Initial Lifetime
No.
Symbol
Parameter
Min Typ1
Unit
Avg2 Max3 Max4
5
5
5
5
5
5
5
1
2
3
4
5
6
7
TDWPROGRAM
TPPROGRAM
*
*
*
*
*
*
*
Double word (64 bits) program time6
Page(128 bits) program time6
—
—
—
—
—
—
—
39
48
—
—
500
500
µs
µs
53
100
T16KPPERASE
T48KPPERASE
T64KPPERASE
T128KPPERASE
T256KPPERASE
16 KB block pre-program and erase time
48 KB block pre-program and erase time
64 KB block pre-program and erase time
128 KB block pre-program and erase time
256 KB block pre-program and erase time
TBD TBD 500 5000
TBD TBD 750 5000
TBD TBD 900 5000
TBD TBD 1300 7500
ms
ms
ms
ms
TBD TBD 2600 15000 ms
1
2
Typical program and erase times assume nominal supply values and operation at TJ = 25 °C. These values are
characterized, but not tested.
Factory Average program and erase times represent the effective performance averaged over > 1024 pages or blocks,
and are provided for factory throughput estimation assuming < 100 program/erase cycles, nominal supply values and
operation at TJ = 25 °C. These values are characterized, but not tested.
3
4
Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100
program/erase cycles, nominal supply values and operation at TJ = 25 °C. These values are verified at production test.
Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These
values are characterized, but not tested.
5
6
See Notes for individual specifications, as shown in column headings.
Actual hardware programming times. These do not include software overhead.
Table 25. Flash memory timing
Value
Symbol
Parameter
Unit
Min
Typ
Max
TRES
D Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low
—
—
100
ns
ns
TDONE D Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared
—
—
5
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
93
Preliminary—Subject to Change Without Notice
Electrical characteristics
No. Symbol
Table 26. Flash memory module life
Parameter
Value
Unit
Min
Typ
Max
1
2
3
P/E
P/E
C Number of program/erase cycles per block for 16 KB, 48 KB, 100000
and 64 KB blocks over the operating temperature range1
—
—
cycles
cycles
C Number of program/erase cycles per block for 128 KB and
256 KB blocks over the operating temperature range1
1000 1000002
—
Retention C Minimum data retention at 85 °C average ambient temperature3
Blocks with 0–1,000 P/E cycles
years
20
10
5
—
—
—
—
—
—
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
1
2
3
Operating temperature range is TJ from –40 °C to 150 °C. Typical endurance is evaluated at 25 C. Product
qualification is performed to the minimum specification. For additional information on the Freescale definition of
Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
Typical P/E cycles is 100,000 cycles for 128 KB and 256 KB blocks. For additional information on the Freescale
definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
3.17 SWG electrical characteristics
Table 27. SWG electrical characteristics
Symbol
SINAD
Parameter
Min
Max
Unit
D
Signal-to-noise ratio plus distortion
50
—
dB
3.18 AC specifications
3.18.1 Pad AC specifications
1
Table 28. Pad AC specifications (3.3 V , IPP_HVE = 0 )
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew3
(mA/ns)
Load drive
No.
Pad
(pF)
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
1
Slow
T
3
3
3
3
—
—
—
—
40
40
40
40
—
—
—
—
—
—
—
—
40
50
—
—
—
—
—
—
—
—
4
2
2
2
0.01
0.01
0.01
0.01
—
—
—
—
2
2
2
2
25
50
75
100
200
100
PXS20 Microcontroller Data Sheet, Rev. 1
94
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 28. Pad AC specifications (3.3 V , IPP_HVE = 0 ) (continued)
1
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew3
(mA/ns)
Load drive
(pF)
No.
Pad
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
2
Medium
T
T
1
1
—
—
—
—
—
—
—
—
—
—
15
15
15
15
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12
25
40
70
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40
20
13
7
2.5
2.5
2.5
2.5
3
—
—
—
—
—
—
—
—
—
—
7
7
25
50
1
7
100
200
25
1
7
3
Fast
1
72
55
40
25
50
—
40
40
40
40
25
—
1
6
7
7
50
1
6
12
18
5
7
100
200
25
1
6
7
4
5
Symmetric
T
1
8
3
Pull Up/Down
(3.6 V max)
D
—
—
TBD
—
50
1
2
3
Propagation delay from VDD_HV_IOx/2 of internal signal to Pchannel/Nchannel switch-on condition.
Slope at rising/falling edge.
Data based on characterization results, not tested in production.
VDDE/2
Pad
Data Input
Rising
Edge
Falling
Edge
Output
Delay
Output
Delay
VOH
Pad
Output
VOL
Figure 12. Pad output delay
3.19 Reset sequence
This section shows the duration for different reset sequences. It describes the different reset sequences and it specifies the start
conditions and the end indication for the reset sequences.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
95
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.19.1 Reset sequence duration
Table 29 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in
Section 3.19.2, Reset sequence description.
Table 29. RESET sequences
TReset
No.
Symbol
Parameter
Conditions
Unit
Min
Typ
Max1
1
TDRB
CC
Destructive Reset Sequence, BIST enabled
cut1
cut2
—
52
40
500
52
41
35
1
60
47
65
51
ms
ms
s
2
3
TDR
CC
CC
Destructive Reset Sequence, BIST disabled
External Reset Sequence Long, BIST enabled
4200
57
5000
65
TERLB
cut1
cut2
—
ms
ms
s
45
49
4
5
TFRL
TFRS
CC
CC
Functional Reset Sequence Long
Functional Reset Sequence Short
150
4
400
10
—
s
1
The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET
by an external reset generator.
3.19.2 Reset sequence description
The figures in this section show the internal states of the chip during the five different reset sequences. The doted lines in the
figures indicate the starting point and the end point for which the duration is specified in Table 29. The start point and end point
conditions as well as the reset trigger mapping to the different reset sequences is specified in Section 3.19.3, Reset sequence
trigger mapping.
With the beginning of DRUN mode the first instruction is fetched and executed. At this point application execution starts and
the internal reset sequence is finished.
The figures below show the internal states of the chip during the execution of the reset sequence and the possible states of the
signal pin RESET.
NOTE
RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an
external reset generator or by the chip internal reset circuitry. A high level on this pin can
only be generated by an external pull up resistor which is strong enough to overdrive the
weak internal pull down resistor. The rising edge on RESET in the following figures
indicates the time when the device stops driving it low. The reset sequence durations given
in table Table 29 are applicable only if the internal reset sequence is not prolonged by an
external reset generator keeping RESET asserted low beyond the last PHASE3.
PXS20 Microcontroller Data Sheet, Rev. 1
96
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE0
PHASE1,2
PHASE3
BIST
PHASE1,2
PHASE3
DRUN
Establish IRC
and PWR
Device
Config
Self Test
Setup
Device
Config
Application
Execution
Flash init
MBIST
LBIST
Flash init
TDRB, min < TReset < TDRB, max
Figure 13. Destructive Reset Sequence, BIST enabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE0
PHASE1,2
PHASE3
DRUN
Establish IRC
and PWR
Device
Config
Application
Execution
Flash init
TDR, min < TReset < TDR, max
Figure 14. Destructive Reset Sequence, BIST disabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
PHASE3
BIST
PHASE1,2
PHASE3
DRUN
Device
Config
Self Test
Setup
Device
Config
Application
Execution
Flash init
MBIST
LBIST
Flash init
TERLB, min < TReset < TERLB, max
Figure 15. External Reset Sequence Long, BIST enabled
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
97
Preliminary—Subject to Change Without Notice
Electrical characteristics
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
PHASE3
DRUN
Device
Config
Application
Execution
Flash init
TFRL, min < TReset < TFRL, max
Figure 16. Functional Reset Sequence Long
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE3
DRUN
Application
Execution
TFRS, min < TReset < TFRS, max
Figure 17. Functional Reset Sequence Short
The reset sequences shown in Figure 16 and Figure 17 are triggered by functional reset events. RESET is driven low during
these two reset sequences only if the corresponding functional reset source (which triggered the reset sequence) was enabled to
1
drive RESET low for the duration of the internal reset sequence .
3.19.3 Reset sequence trigger mapping
The following table shows the possible trigger events for the different reset sequences. It specifies the reset sequence start
conditions as well as the reset sequence end indications that are the basis for the timing data provided in Table 29.
1.See RGM_FBRE register for more details.
PXS20 Microcontroller Data Sheet, Rev. 1
98
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 30. Reset sequence trigger — reset sequence
Reset Sequence
Reset
Sequence
Start
Reset
Sequence
End
Destructiv
e Reset
Sequence, Sequence, Sequenc
Destructiv
e Reset
External
Reset
Functiona Functiona
Reset
Sequence
Trigger
l Reset
Sequenc
e Long
l Reset
Sequenc
e Short
Condition
Indication
BIST
BIST
e Long,
BIST
enabled1
disabled1
enabled
All internal
destructivereset
sources
(LVDsorinternal
HVD during
power-up and
during
Section 3.1
9.4.1,
Destructive
reset
Release of
RESET2
triggers
cannot
trigger
cannot
trigger
cannot
trigger
operation)
Assertion of
RESET3
Section 3.1
9.4.2,
External
reset via
RESET
cannot trigger
cannot trigger
cannot trigger
triggers4
triggers5
triggers
triggers6
All internal
functional reset
sources
configured for
long reset
Sequence
starts with
internal
reset
Release of
RESET7
cannot
trigger
cannot
trigger
trigger
All internal
functional reset
sources
cannot
trigger
cannot
trigger
triggers
configured for
short reset
1
2
Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM.
End of the internal reset sequence (as specified in Table 29) can only be observed by release of RESET if it is not
held low externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 till
RESET is released externally.
3
The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before.
RESET does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST
disabled. However, it can prolong these sequences if RESET is held low externally beyond the end of the internal
sequence (beyond PHASE3).
4
5
If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the
shadow sector of the NVM.
If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the
shadow sector of the NVM.
6
7
If RESET is configured for short reset
Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for
the functional reset source which triggered the reset sequence.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
99
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.19.4 Reset sequence — start condition
The impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage
rails / signals ramp up with a very slow slew rate compared to the overall reset sequence duration.
3.19.4.1 Destructive reset
Figure 18 shows the voltage threshold that determines the start of the Destructive Reset Sequence, BIST enabled and the start
for the Destructive Reset Sequence, BIST disabled.
V
Supply Rail
Vmax
Vmin
t
TReset, max starts here
TReset, min starts here
Figure 18. Reset sequence start for Destructive Resets
Table 31. Voltage Thresholds
Variable name
Value
Vmin
Refer to Table 16
Vmax
Refer to Table 16
VDD_HV_PMU
Supply Rail
3.19.4.2 External reset via RESET
Figure 19 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of RESET as
specified in Table 30.
PXS20 Microcontroller Data Sheet, Rev. 1
100
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
V
RESET
0.65 * VDD_HV_IO
0.35 * VDD_HV_IO
t
TReset, max starts here
TReset, min starts here
Figure 19. Reset sequence start via RESET assertion
3.19.5 External watchdog window
If the application design requires the use of an external watchdog the data provided in Section 3.19, Reset sequence can be used
to determine the correct positioning of the trigger window for the external watchdog. Figure 20 shows the relationships between
the minimum and the maximum duration of a given reset sequence and the position of an external watchdog trigger window.
Watchdog needs to be triggered within this window
TWDStart, min
External Watchdog Window Closed
TWDStart, max
External Watchdog Window Open
External Watchdog Window Closed
External Watchdog Window Open
Watchdog trigger
Basic Application Init
TReset, min
Application Running
Basic Application Init
TReset, max
Application Running
Application time required to
prepare watchdog trigger
Earliest
Application
Start
Latest
Application
Start
Internal Reset Sequence
Start condition (signal or voltage rail)
Figure 20. Reset sequence - External watchdog trigger window position
3.20 AC timing characteristics
AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows:
• TJ = –40 to 150 C
• Supply voltages as specified in Table 9
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
101
Preliminary—Subject to Change Without Notice
Electrical characteristics
• Input conditions: All Inputs: tr, tf = 1 ns
• Output Loading: All Outputs: 50 pF
3.20.1 RESET pin characteristics
The PXS20 implements a dedicated bidirectional RESET pin.
V
DD
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
device start-up phase
Figure 21. Start-up reset requirements
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
Figure 22. Noise filtering on reset signal
PXS20 Microcontroller Data Sheet, Rev. 1
102
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 32. RESET electrical characteristics
No. Symbol
Parameter
Conditions1
Min
Typ
Max
Unit
1
Ttr
D Output transition time output pin2
CL = 25pF
CL = 50pF
CL = 100pF
—
—
—
—
—
—
—
—
12
25
40
40
—
ns
—
2
3
WFRST P nRESET input filtered pulse
—
ns
ns
WNFRST P nRESET input not filtered pulse
—
500
1
2
VDD = 3.3 V ± 10%, TJ = –40 to +150 °C, unless otherwise specified
CL includes device and package capacitance (CPKG < 5 pF).
3.20.2 WKUP/NMI timing
Table 33. WKUP/NMI glitch filter
No. Symbol
Parameter
Min
Typ
Max
Unit
1
2
WFNMI D NMI pulse width that is rejected
WNFNMI D NMI pulse width that is passed
—
—
—
45
—
ns
ns
205
3.20.3 IEEE 1149.1 JTAG interface timing
Table 34. JTAG pin AC electrical characteristics
No.
Symbol
Parameter
Conditions
Min Max Unit
1
2
tJCYC
tJDC
D
D
D
D
D
D
D
D
D
D
D
D
D
TCK cycle time
—
—
—
—
—
—
—
—
—
—
—
—
—
62.5
—
ns
%
TCK clock pulse width (measured at VDDE/2)
TCK rise and fall times (40%–70%)
TMS, TDI data setup time
40 60
3
tTCKRISE
—
5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
tTMSS, TDIS
TMSH, tTDIH
tTDOV
tTDOI
tTDOHZ
tBSDV
t
—
—
20
—
20
50
50
50
—
—
5
t
TMS, TDI data hold time
25
—
0
6
TCK low to TDO data valid
7
TCK low to TDO data invalid
8
TCK low to TDO high impedance
—
—
—
—
50
50
11
12
13
14
15
TCK falling edge to output valid
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
103
Preliminary—Subject to Change Without Notice
Electrical characteristics
TCK
2
3
3
2
1
Figure 23. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 24. JTAG test access port timing
PXS20 Microcontroller Data Sheet, Rev. 1
104
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 25. JTAG boundary scan timing
3.20.4 Nexus timing
1
Table 35. Nexus debug port timing
No.
Symbol
Parameter
Conditions Min Max Unit
1
2
tMCYC
tMDC
D MCKO Cycle Time
—
—
—
—
—
—
—
—
15.6
40
—
ns
%
D MCKO Duty Cycle
60
3
tMDOV
tEVTIPW
tEVTOPW
tTCYC
D MCKO Low to MDO, MSEO, EVTO Data Valid2
–0.1 0.25 tMCYC
4
D EVTI Pulse Width
4.0
1
—
tTCYC
tMCYC
ns
5
D EVTO Pulse Width
6
D TCK Cycle Time3
62.5
40
8
—
60
—
—
25
7
tTDC
D TCK Duty Cycle
%
8
t
NTDIS, tNTMSS D TDI, TMS Data Setup Time
ns
9
tNTDIH, NTMSH
t
D TDI, TMS Data Hold Time
5
ns
10
tJOV
D TCK Low to TDO/RDY Data Valid
0
ns
1
2
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is
measured from 50% of MCKO and 50% of the respective signal.
For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
105
Preliminary—Subject to Change Without Notice
Electrical characteristics
3
The system clock frequency needs to be four times faster than the TCK frequency.
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
4
EVTI
Figure 26. Nexus output timing
MCKO
MDO, MSEO
MDO/MSEO data are valid during MCKO rising and falling edge
Figure 27. Nexus Double Data Rate (DDR) Mode output timing
PXS20 Microcontroller Data Sheet, Rev. 1
106
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
6
7
TCK
8
9
TMS, TDI
10
TDO/RDY
Figure 28. Nexus TDI, TMS, TDO timing
3.20.5 External interrupt timing (IRQ pin)
Table 36. External interrupt timing
No.
Symbol
Parameter
IRQ pulse width low
Conditions
Min Max Unit
1
2
3
tIPWL
tIPWH
tICYC
D
D
D
—
—
—
3
3
6
—
—
—
tCYC
tCYC
tCYC
IRQ pulse width high
IRQ edge to edge time1
1
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
107
Preliminary—Subject to Change Without Notice
Electrical characteristics
IRQ
1
2
3
Figure 29. External interrupt timing
3.20.6 DSPI timing
Table 37. DSPI timing
No. Symbol
Parameter
Conditions
Master (MTFE = 0)
Min
Max
Unit
1
tSCK
D
D
D
D
D
D
D
D
D
D
D
DSPI cycle time
62
62
16
16
16
—
—
—
—
—
ns
Slave (MTFE = 0)
Slave Receive Only Mode1
2
3
4
5
6
7
8
9
tCSC
tASC
tSDC
tA
PCS to SCK delay
After SCK delay
—
ns
ns
—
—
SCK duty cycle
tSCK/2 - 10 tSCK/2 + 10 ns
Slave access time
Slave SOUT disable time
PCSx to PCSS time
PCSS to PCSx time
Data setup time for inputs
SS active to SOUT valid
SS inactive to SOUT High-Z or invalid
—
—
—
13
13
20
2
40
10
—
—
—
—
—
—
—
—
—
—
4
ns
ns
ns
ns
ns
tDIS
tPCSC
tPASC
tSUI
—
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
5
20
–5
4
10
tHI
D
D
Data hold time for inputs
ns
ns
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
11
–5
—
—
—
—
11 tSUO
Data valid (after SCK edge)
23
12
4
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
PXS20 Microcontroller Data Sheet, Rev. 1
108
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 37. DSPI timing (continued)
Conditions
No. Symbol
12 tHO
Parameter
Data hold time for outputs
Min
Max
Unit
D
Master (MTFE = 0)
–2
6
—
—
—
—
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
6
–2
1
Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data
on SIN, but no valid data is transmitted on SOUT.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
Last Data
SIN
First Data
First Data
Data
Data
12
11
Last Data
SOUT
Note: The numbers shown are referenced in Table 37.
Figure 30. DSPI classic SPI timing — master, CPHA = 0
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
109
Preliminary—Subject to Change Without Notice
Electrical characteristics
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Note: The numbers shown are referenced in Table 37.
Figure 31. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
9
10
First Data
Data
Last Data
SIN
Note: The numbers shown are referenced in Table 37.
Figure 32. DSPI classic SPI timing — slave, CPHA = 0
PXS20 Microcontroller Data Sheet, Rev. 1
110
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Note: The numbers shown are referenced in Table 37.
Figure 33. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
Last Data
Last Data
Data
12
11
SOUT
First Data
Data
Note: The numbers shown are referenced in Table 37.
Figure 34. DSPI modified transfer format timing — master, CPHA = 0
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
111
Preliminary—Subject to Change Without Notice
Electrical characteristics
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Note: The numbers shown are referenced in Table 37.
Figure 35. DSPI modified transfer format timing — master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Note: The numbers shown are referenced in Table 37.
Figure 36. DSPI modified transfer format timing – slave, CPHA = 0
PXS20 Microcontroller Data Sheet, Rev. 1
112
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Note: The numbers shown are referenced in Table 37.
Figure 37. DSPI modified transfer format timing — slave, CPHA = 1
8
7
PCSS
PCSx
Note: The numbers shown are referenced in Table 37.
Figure 38. DSPI PCS strobe (PCSS) timing
4
Package characteristics
4.1
Package mechanical data
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
113
Preliminary—Subject to Change Without Notice
Package characteristics
Figure 39. 144 LQFP package mechanical drawing (1 of 2)
PXS20 Microcontroller Data Sheet, Rev. 1
114
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package characteristics
Figure 40. 144 LQFP package mechanical drawing (2 of 2)
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
115
Preliminary—Subject to Change Without Notice
Package characteristics
Figure 41. 257 MAPBGA package mechanical drawing (1 of 2)
PXS20 Microcontroller Data Sheet, Rev. 1
116
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package characteristics
Figure 42. 257 MAPBGA package mechanical drawing (2 of 2)
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
117
Preliminary—Subject to Change Without Notice
Ordering information
5
Ordering information
M PX
S 20 10 V MM 120 R
Qualification status
Brand
Family
Class
Flash memory size
Temperature range
Package identifier
Operating frequency
Tape and reel indicator
Qualification status
Family
Flash Memory Size
D = Display Graphics
N = Connectivity/Network
R = Performance/Real Time Control
S = Safety
05 = 512 KB
10 = 1 MB
P = Pre-qualification (engineering samples)
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Temperature range
Package identifier
Operating frequency
Tape and reel status
V = –40 °C to 105 °C
(ambient)
LQ = 144 LQFP
MM = 257 MAPBGA
80 = 80 MHz
120 = 120 MHz
R = Tape and reel
(blank) = Trays
Note: Not all options are available on all devices. See Table 38 for more information.
Figure 43. PXS20 orderable part number description
Table 38. PXS20 orderable part number summary
Speed
(MHz)
Part number
Flash/SRAM
Package
MPXS2005VLQ80
MPXS2010VLQ80
MPXS2010VMM80
MPXS2010VLQ120
MPXS2010VMM120
512 KB / 128 KB
1 MB / 128 KB
1 MB / 128 KB
1 MB / 128 KB
1 MB / 128 KB
144 LQFP (20 mm x 20 mm)
144 LQFP (20 mm x 20 mm)
257 MAPBGA (14 mm x 14 mm)
144 LQFP (20 mm x 20 mm)
257 MAPBGA (14 mm x 14 mm)
80
80
80
120
120
6
Document revision history
Table 39 summarizes revisions to this document.
Table 39. Revision history
Revision
Date
Description of Changes
1
30 Sep 2011 Initial release.
PXS20 Microcontroller Data Sheet, Rev. 1
118
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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PXS20
Rev. 1
09/2011
相关型号：
MPXR2020VMG116R
32-bit Power Architecture® Dual Core Microcontrollers for Industrial Networking
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