MRF1550FNT1

更新时间:2024-09-18 05:58:05
品牌:FREESCALE
描述:RF Power Field Effect Transistors N-Channel Enhancement-Mode Lateral MOSFETs

MRF1550FNT1 概述

RF Power Field Effect Transistors N-Channel Enhancement-Mode Lateral MOSFETs 射频功率场效应晶体管N沟道增强模式横向的MOSFET

MRF1550FNT1 数据手册

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Document Number: MRF1550N  
Rev. 11, 9/2006  
Freescale Semiconductor  
Technical Data  
RF Power Field Effect Transistors  
MRF1550NT1  
MRF1550FNT1  
N-Channel Enhancement-Mode Lateral MOSFETs  
Designed for broadband commercial and industrial applications with frequen-  
cies to 175 MHz. The high gain and broadband performance of these devices  
make them ideal for large-signal, common source amplifier applications in  
12.5 volt mobile FM equipment.  
175 MHz, 50 W, 12.5 V  
LATERAL N-CHANNEL  
BROADBAND  
Specified Performance @ 175 MHz, 12.5 Volts  
Output Power — 50 Watts  
Power Gain — 12 dB  
RF POWER MOSFETs  
Efficiency — 50%  
Capable of Handling 20:1 VSWR, @ 15.6 Vdc, 175 MHz, 2 dB Overdrive  
Features  
Excellent Thermal Stability  
Characterized with Series Equivalent Large-Signal Impedance Parameters  
Broadband-Full Power Across the Band: 135-175 MHz  
Broadband Demonstration Amplifier Information Available  
CASE 1264-09, STYLE 1  
TO-272-6 WRAP  
PLASTIC  
Upon Request  
200_C Capable Plastic Package  
MRF1550NT1  
N Suffix Indicates Lead-Free Terminations. RoHS Compliant.  
In Tape and Reel. T1 Suffix = 500 Units per 44 mm, 13 inch Reel.  
CASE 1264A-02, STYLE 1  
TO-272-6  
PLASTIC  
MRF1550FNT1  
Table 1. Maximum Ratings  
Rating  
Symbol  
Value  
-0.5, +40  
20  
Unit  
Vdc  
Vdc  
Adc  
Drain-Source Voltage  
Gate-Source Voltage  
V
DSS  
V
GS  
Drain Current — Continuous  
I
12  
D
(1)  
Total Device Dissipation @ T = 25°C  
P
165  
W
C
D
Derate above 25°C  
0.50  
W/°C  
Storage Temperature Range  
Operating Junction Temperature  
Table 2. Thermal Characteristics  
T
- 65 to +150  
200  
°C  
°C  
stg  
T
J
(2)  
Characteristic  
Symbol  
Value  
Unit  
Thermal Resistance, Junction to Case  
Table 3. Moisture Sensitivity Level  
Test Methodology  
R
0.75  
°C/W  
θ
JC  
Rating  
Package Peak Temperature  
Unit  
Per JESD 22-A113, IPC/JEDEC J-STD-020  
1
260  
°C  
T
T
C
J –  
1. Calculated based on the formula P  
=
D
R
θJC  
2. MTTF calculator available at http://www.freescale.com/rf. Select Tools/Software/Application Software/Calculators to access  
the MTTF calculators by product.  
NOTE - CAUTION - MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and  
packaging MOS devices should be observed.  
© Freescale Semiconductor, Inc., 2006. All rights reserved.  
Table 4. Electrical Characteristics (T = 25°C unless otherwise noted)  
C
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
Off Characteristics  
Zero Gate Voltage Drain Current  
I
I
1
μAdc  
μAdc  
DSS  
(V = 60 Vdc, V = 0 Vdc)  
DS  
GS  
Gate-Source Leakage Current  
0.5  
GSS  
(V = 10 Vdc, V = 0 Vdc)  
GS  
DS  
On Characteristics  
Gate Threshold Voltage  
(V = 12.5 Vdc, I = 800 μA)  
V
1
3
0.5  
1
Vdc  
Ω
GS(th)  
DS(on)  
DS(on)  
DS  
D
Drain-Source On-Voltage  
(V = 5 Vdc, I = 1.2 A)  
R
V
GS  
D
Drain-Source On-Voltage  
(V = 10 Vdc, I = 4.0 Adc)  
Vdc  
GS  
D
Dynamic Characteristics  
Input Capacitance (Includes Input Matching Capacitance)  
C
500  
250  
35  
pF  
pF  
pF  
iss  
(V = 12.5 Vdc, V = 0 V, f = 1 MHz)  
DS  
GS  
Output Capacitance  
C
oss  
(V = 12.5 Vdc, V = 0 V, f = 1 MHz)  
DS  
GS  
Reverse Transfer Capacitance  
(V = 12.5 Vdc, V = 0 V, f = 1 MHz)  
C
rss  
DS  
GS  
RF Characteristics (In Freescale Test Fixture)  
Common-Source Amplifier Power Gain  
G
14.5  
55  
dB  
%
ps  
(V = 12.5 Vdc, P = 50 Watts, I  
= 500 mA)  
= 500 mA)  
f = 175 MHz  
f = 175 MHz  
DD  
out  
DQ  
Drain Efficiency  
η
(V = 12.5 Vdc, P = 50 Watts, I  
DD  
out  
DQ  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
2
V
GG  
+
V
DD  
+
C10  
C9  
C8  
R4  
C20  
C19  
C18  
C21  
R3  
R2  
L5  
C7  
N2  
Z6 Z7  
Z8  
L3  
Z9  
L4  
Z10  
Z11 C17  
R1  
C6  
RF  
OUTPUT  
DUT  
N1  
Z1  
C2  
L1  
Z2  
C4  
Z3  
C5  
L2  
Z4  
Z5  
RF  
INPUT  
C13  
C14  
C15 C16  
C11 C12  
C1  
C3  
B1  
C1  
C2  
C3  
C4, C16  
C5  
C6  
C7, C17  
C8, C18  
C9, C19  
C10  
C11, C12  
C13  
C14  
C15  
C20  
L1  
Ferroxcube #VK200  
L4  
L5  
N1, N2  
R1  
R2  
R3  
R4  
Z1  
Z2  
Z3  
Z4  
Z5, Z6  
Z7  
Z8  
1 Turn, #26 AWG, 0.240ID  
3 Turn, #24 AWG, 0.180ID  
Type N Flange Mounts  
180 pF, 100 mil Chip Capacitor  
10 pF, 100 mil Chip Capacitor  
33 pF, 100 mil Chip Capacitor  
24 pF, 100 mil Chip Capacitors  
160 pF, 100 mil Chip Capacitor  
240 pF, 100 mil Chip Capacitor  
300 pF, 100 mil Chip Capacitors  
10 μF, 50 V Electrolytic Capacitors  
0.1 μF, 100 mil Chip Capacitors  
470 pF, 100 mil Chip Capacitor  
200 pF, 100 mil Chip Capacitors  
22 pF, 100 mil Chip Capacitor  
30 pF, 100 mil Chip Capacitor  
6.8 pF, 100 mil Chip Capacitor  
1,000 pF, 100 mil Chip Capacitor  
18.5 nH, Coilcraft #A05T  
5.1 Ω, 1/4 W Chip Resistor  
39 Ω Chip Resistor (0805)  
1 kΩ, 1/8 W Chip Resistor  
33 kΩ, 1/4 W Chip Resistor  
1.000x 0.080Microstrip  
0.400x 0.080Microstrip  
0.200x 0.080Microstrip  
0.200x 0.080Microstrip  
0.100x 0.223Microstrip  
0.160x 0.080Microstrip  
0.260x 0.080Microstrip  
0.280x 0.080Microstrip  
0.270x 0.080Microstrip  
0.730x 0.080Microstrip  
Z9  
Z10  
Z11  
Board  
®
L2  
5 nH, Coilcraft #A02T  
Glass Teflon , 31 mils  
L3  
1 Turn, #24 AWG, 0.250ID  
Figure 1. 135 - 175 MHz Broadband Test Circuit  
TYPICAL CHARACTERISTICS  
0
80  
70  
60  
135 MHz  
V
= 12.5 Vdc  
DD  
−5  
175 MHz  
50  
40  
30  
20  
10  
155 MHz  
175 MHz  
−10  
135 MHz  
−15  
155 MHz  
40  
V
= 12.5 Vdc  
5.0  
DD  
−20  
10  
0
0
1.0  
2.0  
3.0  
4.0  
6.0  
20  
30  
50  
60  
70  
80  
P , INPUT POWER (WATTS)  
in  
P
, OUTPUT POWER (WATTS)  
out  
Figure 2. Output Power versus Input Power  
Figure 3. Input Return Loss  
versus Output Power  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
3
TYPICAL CHARACTERISTICS  
16  
15  
14  
13  
80  
175 MHz  
70  
155 MHz  
135 MHz  
60  
155 MHz  
175 MHz  
135 MHz  
50  
40  
12  
11  
10  
V
= 12.5 Vdc  
70  
V
= 12.5 Vdc  
70 80  
DD  
DD  
30  
10  
10  
20  
30  
40  
50  
60  
80  
20  
30  
P , OUTPUT POWER (WATTS)  
out  
40  
50  
60  
P
, OUTPUT POWER (WATTS)  
out  
Figure 4. Gain versus Output Power  
Figure 5. Drain Efficiency versus Output Power  
80  
70  
70  
65  
60  
155 MHz  
135 MHz  
175 MHz  
135 MHz  
175 MHz  
60  
50  
40  
155 MHz  
55  
50  
V
P
= 12.5 Vdc  
= 35 dBm  
V
P
= 12.5 Vdc  
DD  
= 35 dBm  
DD  
in  
in  
200  
400  
600  
800  
1000  
1200  
200  
400  
600  
I , BIASING CURRENT (mA)  
DQ  
800  
1000  
1200  
I , BIASING CURRENT (mA)  
DQ  
Figure 6. Output Power versus Biasing Current  
Figure 7. Drain Efficiency versus  
Biasing Current  
90  
80  
70  
60  
155 MHz  
80  
70  
60  
175 MHz  
135 MHz  
155 MHz  
135 MHz  
175 MHz  
50  
40  
30  
50  
40  
I
= 500 mA  
= 35 dBm  
I
= 500 mA  
P = 35 dBm  
in  
DQ  
DQ  
P
in  
10  
11  
12  
13  
14  
15  
10  
11  
12  
V , SUPPLY VOLTAGE (VOLTS)  
DD  
13  
14  
15  
V
, SUPPLY VOLTAGE (VOLTS)  
DD  
Figure 8. Output Power versus Supply Voltage  
Figure 9. Drain Efficiency versus Supply Voltage  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
4
TYPICAL CHARACTERISTICS  
11  
10  
10  
10  
9
10  
8
10  
90 100 110 120 130 140 150 160 170 180 190 200 210  
T , JUNCTION TEMPERATURE (°C)  
J
2
This above graph displays calculated MTTF in hours x ampere  
drain current. Life tests at elevated temperatures have correlated to  
better than 10% of the theoretical prediction for metal failure. Divide  
2
MTTF factor by I for MTTF in a particular application.  
D
Figure 10. MTTF Factor versus Junction Temperature  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
5
Z = 10 Ω  
o
f = 175 MHz  
f = 175 MHz  
Z
in  
Z
*
OL  
f = 135 MHz  
f = 135 MHz  
V
= 12.5 V, I = 500 mA, P = 50 W  
DQ out  
DD  
f
Z
Z
*
OL  
in  
MHz  
135  
155  
175  
Ω
Ω
4.1 + j0.5  
4.2 + j1.7  
3.7 + j2.3  
1.0 + j0.6  
1.2 + j.09  
0.7 + j1.1  
Z
= Complex conjugate of source  
impedance.  
in  
Z
* = Complex conjugate of the load  
OL  
impedance at given output power,  
voltage, frequency, and η > 50 %.  
D
Output  
Device  
Input  
Matching  
Network  
Matching  
Network  
Under Test  
Z
Z
*
OL  
in  
Figure 11. Series Equivalent Input and Output Impedance  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
6
Table 5. Common Source Scattering Parameters (VDD = 12.5 Vdc)  
IDQ = 500 mA  
S
S
S
S
S
S
S
S
S
S
S
S
11  
11  
11  
21  
12  
12  
12  
22  
22  
22  
f
|S  
|
∠ φ  
|S  
|
∠ φ  
80  
69  
61  
54  
51  
47  
46  
43  
43  
43  
41  
41  
|S  
|
∠ φ  
-39  
-3  
|S |  
22  
∠ φ  
MHz  
11  
21  
12  
50  
0.93  
0.94  
0.95  
0.95  
0.96  
0.97  
0.97  
0.98  
0.98  
0.98  
0.99  
0.98  
-178  
-178  
-178  
-178  
-178  
-178  
-178  
-178  
-178  
-178  
-177  
-178  
4.817  
2.212  
1.349  
0.892  
0.648  
0.481  
0.370  
0.304  
0.245  
0.209  
0.178  
0.149  
0.009  
0.009  
0.008  
0.006  
0.005  
0.004  
0.005  
0.001  
0.005  
0.003  
0.007  
0.010  
0.86  
0.88  
0.90  
0.92  
0.93  
0.95  
0.95  
0.97  
0.97  
0.97  
0.98  
0.96  
-176  
-175  
-174  
-174  
-174  
-174  
-174  
-174  
-174  
-174  
-175  
-175  
100  
150  
200  
250  
300  
350  
400  
450  
500  
550  
600  
-8  
-13  
-7  
-8  
4
15  
81  
84  
70  
106  
IDQ = 2.0 mA  
21  
f
|S  
|
11  
∠ φ  
|S  
|
21  
∠ φ  
80  
69  
61  
54  
51  
47  
46  
43  
43  
44  
41  
41  
|S  
|
12  
∠ φ  
-119  
4
|S |  
22  
∠ φ  
MHz  
50  
0.93  
0.94  
0.95  
0.95  
0.96  
0.97  
0.97  
0.98  
0.98  
0.98  
0.99  
0.98  
-177  
-178  
-178  
-178  
-178  
-178  
-178  
-178  
-178  
-177  
-177  
-178  
4.81  
2.20  
1.35  
0.89  
0.65  
0.48  
0.37  
0.30  
0.25  
0.21  
0.18  
0.15  
0.003  
0.006  
0.003  
0.004  
0.001  
0.004  
0.006  
0.007  
0.006  
0.006  
0.002  
0.004  
0.93  
0.93  
0.93  
0.93  
0.94  
0.94  
0.95  
0.96  
0.97  
0.97  
0.97  
0.96  
-178  
-178  
-177  
-176  
-176  
-175  
-175  
-174  
-174  
-174  
-175  
-174  
100  
150  
200  
250  
300  
350  
400  
450  
500  
550  
600  
-1  
18  
28  
77  
85  
53  
74  
84  
106  
116  
IDQ = 4.0 mA  
21  
f
|S  
|
∠ φ  
|S  
|
∠ φ  
87  
82  
77  
74  
71  
68  
67  
|S  
|
∠ φ  
-116  
42  
|S |  
22  
∠ φ  
MHz  
11  
21  
12  
50  
0.97  
0.96  
0.96  
0.96  
0.97  
0.97  
0.97  
-179  
-179  
-179  
-179  
-179  
-179  
-179  
5.04  
2.43  
1.60  
1.14  
0.89  
0.71  
0.57  
0.002  
0.006  
0.004  
0.003  
0.004  
0.006  
0.006  
0.94  
0.94  
0.94  
0.95  
0.95  
0.95  
0.97  
-179  
-178  
-177  
-176  
-175  
-175  
-174  
100  
150  
200  
250  
300  
350  
13  
43  
65  
68  
74  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
7
Table 5. Common Source Scattering Parameters (VDD = 12.5 Vdc) (continued)  
IDQ = 4.0 mA (continued)  
S
S
S
S
22  
11  
21  
12  
f
|S  
|
∠ φ  
|S  
|
∠ φ  
63  
63  
62  
58  
58  
|S  
|
∠ φ  
58  
|S |  
22  
∠ φ  
MHz  
11  
21  
12  
400  
450  
500  
550  
600  
0.97  
0.98  
0.98  
0.98  
0.98  
-179  
-178  
-178  
-178  
-178  
0.49  
0.41  
0.36  
0.32  
0.27  
0.005  
0.005  
0.003  
0.004  
0.009  
0.97  
0.98  
0.98  
0.99  
0.98  
-173  
-173  
-173  
-174  
-174  
73  
128  
57  
83  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
8
APPLICATIONS INFORMATION  
DESIGN CONSIDERATIONS  
This device is a common-source, RF power, N-Channel  
enhancement mode, Lateral Metal-Oxide Semiconductor  
Field-Effect Transistor (MOSFET). Freescale Application  
Note AN211A, “FETs in Theory and Practice”, is suggested  
reading for those not familiar with the construction and char-  
acteristics of FETs.  
This surface mount packaged device was designed pri-  
marily for VHF and UHF mobile power amplifier applications.  
Manufacturability is improved by utilizing the tape and reel  
capability for fully automated pick and placement of parts.  
However, care should be taken in the design process to in-  
sure proper heat sinking of the device.  
drain-source voltage under these conditions is termed  
DS(on). For MOSFETs, VDS(on) has a positive temperature  
coefficient at high temperatures because it contributes to the  
power dissipation within the device.  
BVDSS values for this device are higher than normally re-  
quired for typical applications. Measurement of BVDSS is not  
recommended and may result in possible damage to the de-  
vice.  
V
GATE CHARACTERISTICS  
The gate of the RF MOSFET is a polysilicon material, and  
is electrically isolated from the source by a layer of oxide.  
The DC input resistance is very high - on the order of 109 Ω  
— resulting in a leakage current of a few nanoamperes.  
Gate control is achieved by applying a positive voltage to  
the gate greater than the gate-to-source threshold voltage,  
The major advantages of Lateral RF power MOSFETs in-  
clude high gain, simple bias systems, relative immunity from  
thermal runaway, and the ability to withstand severely mis-  
matched loads without suffering damage.  
VGS(th)  
.
Gate Voltage Rating — Never exceed the gate voltage  
rating. Exceeding the rated VGS can result in permanent  
damage to the oxide layer in the gate region.  
MOSFET CAPACITANCES  
The physical structure of a MOSFET results in capacitors  
between all three terminals. The metal oxide gate structure  
determines the capacitors from gate-to-drain (Cgd), and  
gate-to-source (Cgs). The PN junction formed during fab-  
rication of the RF MOSFET results in a junction capacitance  
from drain-to-source (Cds). These capacitances are charac-  
terized as input (Ciss), output (Coss) and reverse transfer  
(Crss) capacitances on data sheets. The relationships be-  
tween the inter-terminal capacitances and those given on  
data sheets are shown below. The Ciss can be specified in  
two ways:  
Gate Termination — The gates of these devices are es-  
sentially capacitors. Circuits that leave the gate open-cir-  
cuited or floating should be avoided. These conditions can  
result in turn-on of the devices due to voltage build-up on  
the input capacitor due to leakage currents or pickup.  
Gate Protection — These devices do not have an internal  
monolithic zener diode from gate-to-source. If gate protec-  
tion is required, an external zener diode is recommended.  
Using a resistor to keep the gate-to-source impedance low  
also helps dampen transients and serves another important  
function. Voltage transients on the drain can be coupled to  
the gate through the parasitic gate-drain capacitance. If the  
gate-to-source impedance and the rate of voltage change  
on the drain are both high, then the signal coupled to the gate  
may be large enough to exceed the gate-threshold voltage  
and turn the device on.  
1. Drain shorted to source and positive voltage at the gate.  
2. Positive voltage of the drain in respect to source and zero  
volts at the gate.  
In the latter case, the numbers are lower. However, neither  
method represents the actual operating conditions in RF ap-  
plications.  
DC BIAS  
Since this device is an enhancement mode FET, drain cur-  
rent flows only when the gate is at a higher potential than the  
source. RF power FETs operate optimally with a quiescent  
drain current (IDQ), whose value is application dependent.  
This device was characterized at IDQ = 150 mA, which is the  
suggested value of bias current for typical applications. For  
special applications such as linear amplification, IDQ may  
have to be selected to optimize the critical parameters.  
The gate is a dc open circuit and draws no current. There-  
fore, the gate bias circuit may generally be just a simple re-  
sistive divider network. Some special applications may  
require a more elaborate bias system.  
Drain  
C
gd  
C
C
C
= C + C  
gd gs  
Gate  
iss  
= C + C  
gd ds  
C
oss  
rss  
ds  
= C  
gd  
C
gs  
Source  
GAIN CONTROL  
DRAIN CHARACTERISTICS  
Power output of this device may be controlled to some de-  
gree with a low power dc control signal applied to the gate,  
thus facilitating applications such as manual gain control,  
ALC/AGC and modulation systems. This characteristic is  
very dependent on frequency and load line.  
One critical figure of merit for a FET is its static resistance  
in the full-on condition. This on-resistance, RDS(on), occurs  
in the linear region of the output characteristic and is speci-  
fied at a specific gate-source voltage and drain current. The  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
9
AMPLIFIER DESIGN  
Impedance matching networks similar to those used with  
bipolar transistors are suitable for this device. For examples  
see Freescale Application Note AN721, “Impedance  
Matching Networks Applied to RF Power Transistors.”  
Large-signal impedances are provided, and will yield a good  
first pass approximation.  
Since RF power MOSFETs are triode devices, they are not  
unilateral. This coupled with the very high gain of this device  
yields a device capable of self oscillation. Stability may be  
achieved by techniques such as drain loading, input shunt  
resistive loading, or output to input feedback. The RF test fix-  
ture implements a parallel resistor and capacitor in series  
with the gate, and has a load line selected for a higher effi-  
ciency, lower gain, and more stable operating region.  
Two - port stability analysis with this device’s  
S-parameters provides a useful tool for selection of loading  
or feedback circuitry to assure stable operation. See Free-  
scale Application Note AN215A, “RF Small-Signal Design  
Using Two-Port Parameters” for a discussion of two port  
network theory and stability.  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
10  
PACKAGE DIMENSIONS  
A
E1  
B
r1  
DRAIN ID  
NOTE 6  
4
5
4X b2  
1
6
5
3
M
aaa  
D A  
D1  
DRAIN ID  
M
aaa  
D A  
2X b1  
2
3
2
1
D
M
aaa  
D A  
4X  
e
6
4
4X  
b3  
E2  
E
VIEW Y-Y  
NOTES:  
1. CONTROLLING DIMENSION: INCH .  
SEATING  
PLANE  
2. INTERPRET DIMENSIONS AND TOLERANCES  
PER ASME Y14.5M, 1994.  
C
3. DATUM PLANE −H− IS LOCATED AT TOP OF LEAD  
AND IS COINCIDENT WITH THE LEAD WHERE  
THE LEAD EXITS THE PLASTIC BODY AT THE  
TOP OF THE PARTING LINE.  
4. DIMENSION D AND E1 DO NOT INCLUDE MOLD  
PROTRUSION. ALLOWABLE PROTRUSION IS  
0.006 PER SIDE. DIMENSION D AND E1 DO  
INCLUDE MOLD MISMATCH AND ARE  
A
DATUM  
PLANE  
H
E2  
DETERMINED AT DATUM PLANE −H−.  
Y
Y
5. DIMENSIONS b1 AND b3 DO NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.005 TOTAL IN EXCESS  
OF THE b1 AND b2 DIMENSIONS AT MAXIMUM  
MATERIAL CONDITION.  
SEATING  
PLANE  
D
6. CROSSHATCHING REPRESENTS THE EXPOSED  
AREA OF THE HEAT SLUG.  
INCHES  
DIM MIN MAX  
0.098  
A1 0.000  
A2 0.100  
MILLIMETERS  
A1  
L
MIN  
2.49  
0.00  
2.54  
MAX  
2.74  
0.10  
2.64  
23.67  
20.68  
7.72  
6.40  
6.22  
1.78  
5.05  
2.13  
2.39  
0.28  
A
0.108  
0.004  
0.104  
q
D
0.928  
D1 0.806  
0.296  
0.932 23.57  
0.814 20.47  
A2  
STYLE 1:  
PIN 1. SOURCE (COMMON)  
2. DRAIN  
E
0.304  
0.252  
0.245  
0.070  
0.199  
0.084  
0.094  
0.011  
7.52  
6.30  
6.12  
1.52  
4.90  
1.98  
2.24  
0.18  
E1 0.248  
E2 0.241  
3. SOURCE (COMMON)  
4. SOURCE (COMMON)  
5. GATE  
L
0.060  
b1 0.193  
b2 0.078  
b3 0.088  
c1  
e
c1  
6. SOURCE (COMMON)  
0.007  
0.193 BSC  
4.90 BSC  
r1  
q
0.063  
0
0.068  
6
1.60  
0
1.73  
6
CASE 1264-09  
ISSUE K  
_
_
_
_
aaa  
0.004  
0.10  
TO-272-6 WRAP  
PLASTIC  
MRF1550NT1  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
11  
A
E1  
E2  
B
2X  
P
M
aaa  
D A B  
DRAIN ID  
NOTE 5  
4X b2  
4
5
6
1
2
3
6
5
3
M
aaa  
D A  
DRAIN ID  
2X b1  
2
1
D
D2  
M
aaa  
D A  
4X  
e
4
4X  
b3  
D1  
bbb C A  
B
M
aaa  
D A  
E
VIEW Y-Y  
NOTES:  
1. CONTROLLING DIMENSION: INCH.  
2. INTERPRET DIMENSIONS AND TOLERANCES  
PER ASME Y14.5M, 1994.  
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD  
PROTRUSION. ALLOWABLE PROTRUSION IS  
0.006 PER SIDE. DIMENSIONS D AND E1 DO  
INCLUDE MOLD MISMATCH AND ARE  
c1  
DETERMINED AT DATUM PLANE −H−.  
A
4. DIMENSIONS b1 AND b3 DO NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.005 TOTAL IN EXCESS  
OF THE b1 AND b2 DIMENSIONS AT MAXIMUM  
MATERIAL CONDITION.  
SEATING  
PLANE  
F
D
A1  
ZONE "J"  
Y
Y
5. CROSSHATCHING REPRESENTS THE EXPOSED  
AREA OF THE HEAT SLUG.  
6. DIMENSION A2 APPLIES WITHIN ZONE J ONLY.  
A2  
6
INCHES  
DIM MIN MAX  
0.098  
A1 0.038  
A2 0.040  
MILLIMETERS  
MIN  
2.49  
0.96  
1.02  
MAX  
2.69  
1.12  
1.07  
23.72  
A
0.106  
0.044  
0.042  
D
D1  
D2  
E
0.926  
0.810 BSC  
0.608 BSC  
0.492 0.500 12.50  
0.254 6.25  
0.170 BSC 4.32 BSC  
0.025 BSC 0.64 BSC  
0.934 23.52  
20.57 BSC  
15.44 BSC  
12.70  
6.45  
STYLE 1:  
PIN 1. SOURCE (COMMON)  
2. DRAIN  
E1 0.246  
E2  
F
3. SOURCE (COMMON)  
4. SOURCE (COMMON)  
5. GATE  
P
0.126  
0.134  
0.199  
0.084  
0.094  
3.20  
3.40  
5.05  
2.13  
2.39  
b1 0.193  
b2 0.078  
b3 0.088  
4.90  
1.98  
2.24  
6. SOURCE (COMMON)  
c1  
e
0.007  
0.193 BSC  
0.011 0.178  
0.279  
4.90 BSC  
aaa  
bbb  
0.004  
0.008  
0.10  
0.20  
CASE 1264A-02  
ISSUE C  
TO-272-6  
PLASTIC  
MRF1550FNT1  
MRF1550NT1 MRF1550FNT1  
RF Device Data  
Freescale Semiconductor  
12  
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Document Number: MRF1550N  
Rev.11,9/2006

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