PC10XS3435BPNA [FREESCALE]
Quad High Side Switch (Dual 10mΩ, Dual 35mΩ); 四通道高边开关（双为10mΩ ， 35mΩ双）
| 型号： | PC10XS3435BPNA |
| 厂家： | 
Freescale |
| 描述： | Quad High Side Switch (Dual 10mΩ, Dual 35mΩ) |
| 文件： | 总50页 (文件大小：1456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC10XS3435
Rev. 5.0, 10/2008
Freescale Semiconductor
Advance Information
Quad High Side Switch
(Dual 10mΩ, Dual 35mΩ)
10XS3435
The 10XS3435 is one in a family of devices designed for low-voltage
automotive lighting applications. Its four low RDS(ON) MOSFETs (dual
10mΩ/dual 35mΩ) can control four separate 55W / 28W bulbs, and/or
Xenon modules, and/or LEDs.
HIGH SIDE SWITCH
Programming, control and diagnostics are accomplished using a
16-bit SPI interface. Its output with selectable slew-rate improves
electromagnetic compatibility (EMC) behavior. Additionally, each
output has its own parallel input or SPI control for pulse-width
modulation (PWM) control if desired. The 10XS3435 allows the user to
program via the SPI the fault current trip levels and duration of
acceptable lamp inrush. The device has fail-safe mode to provide fail-
safe functionality of the outputs in case of MCU damaged.
Features
• Four protected 10mΩ and 35mΩ high side switches (at 25°C)
• Operating voltage range of 6.0V to 20V with sleep current <
5.0μA, extended mode from 4.0V to 28V
• 8MHz 16-bit 3.3V and 5V SPI control and status reporting with
daisy chain capability
PNA SUFFIX (PB-FREE)
98ARL10596D
24-PIN PQFN
• PWM module using external clock or calibratable internal
oscillator with programmable outputs delay management
• Smart over-current shutdown, severe short-circuit, over-
temperature protections with time limited autoretry, and fail-safe
mode in case of MCU damage
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
A
• Output OFF or ON open-load detection compliant to bulbs or leds
and short to battery detection. analog current feedback with
selectable ratio and board temperature feedback.
PC10XS3435BPNA
-40°C to 125°C
24 PQFN
V
V
V
V
V
PWR
DD
DD
PWR
DD
10XS3435
VDD
VPWR
HS0
WAKE
FS
LOAD
I/O
SCLK
CS
SCLK
CS
SO
RST
SI
IN0
IN1
IN2
IN3
CSNS
FSI
HS1
HS2
HS3
SI
LOAD
LOAD
LOAD
I/O
SO
I/O
I/O
I/O
MCU
I/O
A/D
GND
GND
Figure 1. 10XS3435 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
VPWR
Voltage Clamp
Internal
Regulator
Over/Under-voltage
Protections
Vdd Failure
Detection
Charge
Pump
POR
I
UP
VREG
CS
SCLK
Selectable Slew Rate
Gate Driver
I
DWN
Selectable Over-current
Detection
HS0
SO
SI
RST
WAKE
FS
Severe Short-circuit
Detection
Logic
Short to VPWR
Detection
IN0
Over-temperature
Detection
IN1
IN2
IN3
Open-Load
Detections
HS0
R
R
I
DWN
DWN
DWN
HS1
HS1
HS2
HS3
PWM
Module
Calibratable
Oscillator
HS2
HS3
VREG
Programmable
Watchdog
FSI
Temperature
Feedback
Selectable Output
Current Recopy
Over-temperature
Prewarning
Analog MUX
VDD
GND
CSNS
Figure 2. 10XS3435 Simplified Internal Block Diagram
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
PIN CONNECTIONS
PIN CONNECTIONS
Transparent Top View of Package
13 12 11 10
9
8
7
6
5
4
3
2
1
SO
16
17
24
FSI
GND
23
GND
14
GND
HS3
18
22
HS2
15
VPWR
19
20
21
HS0
HS1
NC
Figure 3. 10XS3435 Pin Connections
Table 1. 10XS3435 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.
Pin
Number
Pin
Function
Pin Name
Formal Name
Definition
This pin reports an analog value proportional to the designated HS[0:3] output
current or the temperature of the GND flag (pin 14). It is used externally to
generate a ground-referenced voltage for the microcontroller (MCU) . Current
recopy and temperature feedback is SPI programmable.
1
CSNS
Output
Input
Output Current
Monitoring
Each direct input controls the device mode. The IN[0:3] high side input pins
are used to directly control HS0:HS3 high side output pins.
2
3
5
6
IN0
IN1
IN2
IN3
Direct Inputs
The PWM frequency can be generated from IN0 pin to PWM module in case
of external clock is set.
This pin is an open drain configured output requiring an external pull-up
resistor to VDD for fault reporting.
7
FS
Output
Fault Status
(Active Low)
This input pin controls the device mode.
8
9
WAKE
RST
Input
Input
Wake
Reset
This input pin is used to initialize the device configuration and fault registers,
as well as place the device in a low-current sleep mode.
This input pin is connected to a chip select output of a master microcontroller
(MCU).
10
11
12
13
CS
SCLK
SI
Input
Input
Chip Select
(Active Low)
This input pin is connected to the MCU providing the required bit shift clock for
SPI communication.
Serial Clock
This pin is a command data input pin connected to the SPI Serial Data Output
of the MCU or to the SO pin of the previous device of a daisy-chain of devices.
Input
Serial Input
This pin is an external voltage input pin used to supply power interfaces to the
SPI bus.
VDD
Power
Digital Drain Voltage
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 10XS3435 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.
Pin
Number
Pin
Function
Pin Name
Formal Name
Definition
These pins, internally shorted, are the ground for the logic and analog circuitry
of the device. These ground pins must be also shorted in the board.
14, 17, 23
GND
Ground
Power
Output
Output
Ground
This pin connects to the positive power supply and is the source of operational
power for the device.
15
16
VPWR
SO
Positive Power Supply
Serial Output
This output pin is connected to the SPI Serial Data Input pin of the MCU or to
the SI pin of the next device of a daisy-chain of devices.
Protected 10mΩ (HS0 and HS1) 35mΩ (HS2 and HS3) high side power output
pins to the load.
18
19
21
22
HS3
HS1
HS0
HS2
High Side Outputs
These pins may not be connected.
4, 20
24
NC
FSI
N/A
No Connect
This input enables the watchdog timeout feature.
Input
Fail-safe Input
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
VPWR Supply Voltage Range
Load Dump at 25°C (400 ms)
Maximum Operating Voltage
Reverse Battery
VPWR(SS)
V
41
28
-18
VDD Supply Voltage Range
Input/Output Voltage
VDD
-0.3 to 5.5
V
V
(4)
-0.3 to VDD+0.3
WAKE Input Clamp Current
CSNS Input Clamp Current
ICL(WAKE)
ICL(CSNS)
VHS[0:3]
2.5
2.5
mA
mA
V
HS [0:3] Voltage
Positive
41
Negative
-24
Output Current(1)
IHS[0:3]
ECL[0:1]
ECL[2:3]
6.0
100
35
A
mJ
mJ
V
HS[0,1] Output Clamp Energy using single pulse method(2)
HS[2,3] Output Clamp Energy using single pulse method(2)
ESD Voltage(3)
Human Body Model (HBM) for HS[0:3], VPWR and GND
Human Body Model (HBM) for other pins
Charge Device Model (CDM)
VESD1
VESD2
±8000
±2000
Corner Pins (1, 13, 19, 21)
VESD3
VESD4
±750
±500
All Other Pins (2-12, 14-18, 20, 22-24)
THERMAL RATINGS
Operating Temperature
Ambient
°C
°C
TA
TJ
-40 to 125
-40 to 150
Junction
Storage Temperature
TSTG
-55 to 150
Notes
1. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output
current using package thermal resistance is required.
2. Active clamp energy using single-pulse method (L = 2mH, R = 0Ω, V
= 14V, T = 150°C initial).
J
L
PWR
3. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500Ω), the Machine Model (MM)
(CZAP = 200pF, RZAP = 0Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).
4. Input / Output pins are: IN[0:3], RSTB, FSI, CSNS, SI, SCLK, CSB, SO, FSB
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
THERMAL RESISTANCE
Thermal Resistance(5)
Junction to Case
°C/W
RθJC
RθJA
<1.0
30
Junction to Ambient
Peak Pin Reflow Temperature During Solder Mounting(6)
TSOLDER
245
°C
Notes
5. Device mounted on a 2s2p test board per JEDEC JESD51-2. 15 °C/W of RθJA can be reached in a real application case (4 layers board).
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUTS
Battery Supply Voltage Range
Fully Operational
VPWR
V
6.0
4.0
–
–
20
28
Extended mode(7)
Battery Clamp Voltage(8)
VPWR(CLAMP)
IPWR(ON)
41
47
53
V
VPWR Operating Supply Current
mA
Outputs commanded ON, HS[0:3] open,
IN[0:3] > VIH
–
6.5
20
VPWR Supply Current
IPWR(SBY)
mA
Outputs commanded OFF, OFF Open-load Detection Disabled, HS[0:3]
shorted to the ground with VDD= 5.5V
–
6.5
7.5
WAKE > VIH or RST > VIH and IN[0:3] < VIL
Sleep State Supply Current
IPWR(SLEEP)
μA
VPWR = 12V, RST = WAKE = IN[0:3] < VIL, HS[0:3] shorted to the ground
TA = 25°C
TA = 85°C
–
–
1.0
–
5.0
30
VDD Supply Voltage
VDD(ON)
IDD(ON)
3.0
–
5.5
V
VDD Supply Current at VDD = 5.5V
No SPI Communication
mA
–
–
1.6
5.0
2.2
–
8.0 MHz SPI Communication(9)
VDD Sleep State Current at VDD = 5.5V
Over-voltage Shutdown Threshold
Over-voltage Shutdown Hysteresis
Under-voltage Shutdown Threshold(10)
VPWR and VDD Power on Reset Threshold
Recovery Under-voltage Threshold
IDD(SLEEP)
VPWR(OV)
VPWR(OVHYS)
VPWR(UV)
–
–
5.0
36
μA
28
32
0.8
3.9
–
V
0.2
3.3
0.5
3.4
2.2
1.5
4.3
0.9
4.5
2.8
V
V
VSUPPLY(POR)
VPWR(UV)_UP
VDD(FAIL)
VPWR(UV)
4.1
2.5
V
V
VDD Supply Failure Threshold ( for VPWR > VPWR(UV)
)
Notes
7. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0V to 6.0V voltage range, the device is
only protected with the thermal shutdown detection.
8. Measured with the outputs open.
9. Typical value guaranteed per design.
10. Output will automatically recover with time limited autoretry to instructed state when VPWR voltage is restored to normal as long as the
VPWR degradation level did not go below the under-voltage power-ON reset threshold. This applies to all internal device logic that is
supplied by VPWR and assumes that the external VDD supply is within specification.
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS HS0 TO HS3
HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0A, TA = 25°C)
RDS_01(ON)
mΩ
VPWR = 4.5V
VPWR = 6.0V
VPWR = 10V
VPWR = 13V
–
–
–
–
–
–
–
–
36
16
10
10
HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0A, TA = 150°C)
RDS_01(ON)
mΩ
VPWR = 4.5V
VPWR = 6.0V
VPWR = 10V
VPWR = 13V
–
–
–
–
–
–
–
–
62
27
17
17
HS[0,1] Output Source-to-Drain ON Resistance (IHS = -5.0 A, VPWR= -18)(11)
RSD_01(ON)
mΩ
mΩ
TA = 25°C
–
–
–
–
15
20
TA = 150°C
HS[2,3] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 25°C)
RDS_23(ON)
VPWR = 4.5V
VPWR = 6.0V
VPWR = 10V
VPWR = 1.0 V
–
–
–
–
–
–
–
–
126
56
35
35
HS[2,3] Output Drain-to-Source ON Resistance (IHS = 5.0A, TA = 150°C)
RDS_23(ON)
mΩ
mΩ
VPWR = 4.5V
VPWR = 6.0V
VPWR = 10V
VPWR = 13V
–
–
–
–
–
–
–
–
217
94.5
59.5
59.5
HS[2,3] Output Source-to-Drain ON Resistance (IHS = -5.0A, VPWR= -18) (11)
RSD_23(ON)
TA = 25°C
–
–
–
–
52.5
70
TA = 150°C
HS[0,1] Maximum Severe Short-Circuit Impedance Detection(12)
HS[2,3] Maximum Severe Short-Circuit Impedance Detection(12)
Notes
RSHORT_01
RSHORT_23
28
70
64
100
200
mΩ
mΩ
160
11. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V
12. Short-circuit impedance calculated from HS[0:3] to GND pins. Value guaranteed per design.
.
PWR
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise
noted.
Characteristic
OUTPUTS HS0 TO HS3 (CONTINUED)
Symbol
Min
Typ
Max
Unit
HS[0,1] Output Over-current Detection Levels (6.0V < VHS[0:3] < 20V)
28W bit = 0
A
OCHI1_0
OCHI2_0
OC1_0
78
94.0
60.0
52.5
45.0
37.5
30.0
22.5
15.0
12.0
8.0
110
70
50
44.1
37.8
31.5
25.2
18.9
12.6
10.0
6.4
60.9
52.2
43.5
34.8
26.1
17.4
14.0
9.6
OC2_0
OC3_0
OC4_0
OCLO4_0
OCLO3_0
OCLO2_0
OCLO1_0
OCHI1_1
OCHI2_1
OC1_1
39
25
47.0
30.0
26.2
22.5
18.7
15.0
6.0
55
35
28W bit = 1
22.0
18.9
15.7
12.6
4.5
30.5
26.1
21.8
17.4
7.5
OC2_1
OC3_1
OC4_1
OCLO4_1
OCLO3_1
OCLO2_1
OCLO1_1
4.5
6.0
7.5
4.5
6.0
7.5
3.0
4.0
5.0
HS[0,1] Current Sense Ratio (6.0 V < HS[0:3] < 20V, CSNS < 5.0V)(13)
–
28W bit = 0
CSNS_ratio bit = 0
CSNS_ratio bit = 1
28W bit = 1
CSR0_0
CSR1_0
CSR0_1
CSR1_1
–
–
–
–
1/8900
1/53000
1/4450
–
–
–
–
CSNS_ratio bit = 0
CSNS_ratio bit = 1
1/26500
HS[0,1] Current Sense Ratio (CSR0) Accuracy (6.0V < VHS[0:3] < 20V)
with 28W bit=0
CSR0_0_ACC
%
Output Current
12.5A
-12
-13
-16
-20
–
–
–
–
12
13
16
20
5.0A
3.0A
1.5A
Notes
13. Current sense ratio = ICSNS / IHS[0:3]
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise
noted.
Characteristic
OUTPUTS HS0 TO HS3 (CONTINUED)
Symbol
Min
Typ
Max
Unit
HS[0,1] Current Sense Ratio (CSR0) Accuracy (6.0V < VHS < 20V)
with 28W bit=1
CSR0_1_ACC
%
Output Current
3.0A
-16
-20
–
–
16
20
1.5A
HS[0,1] Current Recopy Accuracy with one calibration point (6.0V < VHS[0:3]
20V)(14)
<
CSR0_0_ACC(
-5.0
–
5.0
%
%/°C
%
CAL)
Output Current
5.0A
HS[0,1] CSR0 Current Recopy Temperature Drift (6.0V < VHS[0:3] < 20V)
with 28W bit=0(15)
Δ(CSR0_0)/
Δ(T)
Output Current
5.0A
0.04
HS[0,1] Current Sense Ratio (CSR1) Accuracy (6.0V < VHS[0:3] < 20V)
with 28W bit=0
CSR1_0_ACC
Output Current
12.5A
-17
-12
–
–
+17
+12
75A
Current Sense Clamp Voltage
VCL(CSNS)
V
CSNS Open; IHS[0:3] = 5.0 A with CSR0 ratio
VDD+0.2
5
–
VDD+1.0
OFF Open-Load Detection Source Current(16)
OFF Open-Load Fault Detection Voltage Threshold
ON Open-Load Fault Detection Current Threshold
IOLD(OFF)
VOLD(THRES)
IOLD(ON)
30
2.0
100
–
100
4.0
μA
V
3.0
300
600
mA
mA
ON Open-Load Fault Detection Current Threshold with LED
VHS[0:3] = VPWR - 0.75V
IOLD(ON_LED)
2.5
5.0
10
Output Short to VPWR Detection Voltage Threshold
Output programmed OFF
VOSD(THRES)
V
VPWR
1.2
-
VPWR-0.8 VPWR-0.4
Output Negative Clamp Voltage
VCL
V
0.5A < IHS[0:3] < 5.0A, Output programmed OFF
-22
155
–
-16
Output Over-temperature Shutdown for 4.5V < VPWR < 28V
TSD
175
195
°C
Notes
14. Based on statistical analysis. It is not production tested.
15. Based on statistical data: delta(C
No production tested.
)/delta(T)={(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}.
SR0
16. Output OFF Open-Load Detection Current is the current required to flow through the load for the purpose of detecting the existence
of an open-load condition when the specific output is commanded OFF. Pull-up current is measured for VHS=VOLD(THRES)
10XS3435
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise
noted.
Characteristic
OUTPUTS HS0 TO HS3 (CONTINUED)
Symbol
Min
Typ
Max
Unit
HS[2,3] Output Over-current Detection Levels (6.0V < VHS[0:3] < 20V)
A
OCHI1_1
OCHI2_1
OC1_1
39.5
25.2
22.0
18.9
15.7
12.6
9.4
47.0
30.0
26.2
22.5
18.7
15.0
11.2
7.5
54.5
34.8
30.5
26.1
21.7
17.4
13.0
8.7
OC2_1
OC3_1
OC4_1
OCLO4_1
OCLO3_1
OCLO2_1
OCLO1_1
6.3
5.0
6.0
7.0
3.2
4.0
4.8
HS[2,3] Current Sense Ratio (6.0V < HS[0:3] < 20V, CSNS < 5.0V)(17)
–
CSNS_ratio bit = 0
CSNS_ratio bit = 1
CSR0_1
CSR1_1
–
–
1/4350
–
–
1/25500
HS[2,3] Current Sense Ratio (CSR0) Accuracy (6.0V < VHS[0:3] < 20V)
CSR0_0_ACC
%
Output Current
6.25A
-12
-13
-16
-20
–
–
–
–
12
13
16
20
2.5A
1.5A
0.75A
HS[2,3] Current Recopy Accuracy with one calibration point (6.0V < VHS[0:3]
20V)(18)
<
CSR0_0_ACC(
-5.0
–
5.0
%
CAL)
Output Current
2.5A
Notes
17. Current sense ratio = ICSNS / IHS[0:3]
18. Based on statistical analysis. It is not production tested.
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE
Input Logic High Voltage(19)
Input Logic Low Voltage(19)
V
2.0
-0.3
5.0
5.0
–
–
–
VDD+0.3
0.8
V
V
IH
V
IL
Input Logic Pull-down Current (SCLK, SI)(22)
Input Logic Pull-up Current (CS) (23)
SO, FS Tri-State Capacitance(20)
I
–
20
μA
μA
pF
kΩ
pF
V
DWN
I
–
20
UP
C
–
20
SO
Input Logic Pull-down Resistor (RST, WAKE and IN[0:3])
Input Capacitance(20)
R
125
–
250
4.0
500
12
DWN
C
IN
Wake Input Clamp Voltage(21)
V
CL(WAKE)
I
< 2.5mA
18
25
–
32
-0.3
–
CL(WAKE)
Wake Input Forward Voltage
= -2.5mA
V
V
V
F(WAKE)
I
-2.0
CL(WAKE)
SO High-State Output Voltage
= 1.0mA
V
SOH
I
V
-0.4
–
OH
DD
SO and FS Low-State Output Voltage
= -1.0mA
V
V
SOL
I
–
–
0.4
2.0
OL
SO, CSNS and FS Tri-State Leakage Current
I
μA
kΩ
SO(LEAK)
RFS
CS = VIH and 0 V < VSO < VDD, or FS = 5.5V, or CSNS=0.0V
-2.0
0
FSI External Pull-down Resistance(24)
Watchdog Disabled
–
0
1.0
–
Watchdog Enabled
10
Infinite
Notes
19. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3] and WAKE input signals. The WAKE and RST
signals may be supplied by a derived voltage referenced to V
.
PWR
20. Input capacitance of SI, CS, SCLK, RST, IN[0:3] and WAKE. This parameter is guaranteed by process monitoring but is not production
tested.
21. The current must be limited by a series resistance when using voltages > 7.0V.
22. Pull-down current is with VSI > 1.0V and VSCLK > 1.0V.
23. Pull-up current is with VCS < 2.0V. CS has an active internal pull-up to V
.
DD
24. In Fail-Safe HS[0:3] depends respectively on ON[0:3]. FSI has an active internal pull-up to V
~ 3.0V.
REG
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING HS0 TO HS3
Output Rising Medium Slew Rate (medium speed slew rate / SR[1:0]=00)(25)
VPWR = 14V
SRR_00
SRR_01
SRR_10
SRF_00
SRF_01
SRF_10
tDLY_23
tDLY_12
ΔSR
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
μs
0.15
0.07
0.3
0.3
0.15
0.6
0.3
0.15
0.6
60
0.6
0.3
1.2
0.6
0.3
1.2
85
Output Rising Slow Slew Rate (low speed slew rate / SR[1:0]=01)(25)
VPWR = 14V
Output Falling Fast Slew Rate (high speed slew rate / SR[1:0]=10)(25)
VPWR = 14V
Output Falling Medium Slew Rate (medium speed slew rate / SR[1:0]=00)(25)
VPWR = 14V
0.15
0.07
0.3
Output Falling Slow Slew Rate (low speed slew rate / SR[1:0]=01)(25)
VPWR = 14V
Output Rising Fast Slew Rate (high speed slew rate / SR[1:0]=10)(25)
VPWR = 14V
HS[2:3] Outputs Turn-ON and OFF Delay Times(26)(27)
VPWR = 14V for medium speed slew rate (SR[1:0]=00)
35
HS[0:1] Outputs Turn-ON and OFF Delay Times(26)(27)
VPWR = 14V for medium speed slew rate (SR[1:0]=00)
μs
45
70
95
Driver Output Matching Slew Rate (SRR /SRF)
0.8
1.0
1.2
V
PWR = 14V @ 25°C and for medium speed slew rate (SR[1:0]=00)
HS[0:1] Driver Output Matching Time (tDLY(ON) - tDLY(OFF)
)
ΔtRF_01
μs
μs
VPWR = 14V, fPWM = 240Hz, PWM duty cycle = 50%, @ 25°C for medium
speed slew rate (SR[1:0]=00)
-25
-20
0
5
25
30
HS[2:3] Driver Output Matching Time (tDLY(ON) - tDLY(OFF)
)
ΔtRF_23
VPWR = 14V, fPWM = 240Hz, PWM duty cycle = 50%, @ 25°C for medium
speed slew rate (SR[1:0]=00)
Notes
25. Rise and Fall Slew Rates measured across a 5.0Ω resistive load at high side output = 30% to 70% (see Figure 4, page 20).
26. Turn-ON delay time measured from rising edge of any signal (IN[0:3] and CS) that would turn the output ON to V
= V
/ 2 with
PWR
HS[0:3]
R = 5.0Ω resistive load.
L
27. Turn-OFF delay time measured from falling edge of any signal (IN[0:3] and CS) that would turn the output OFF to V
=V
/ 2
PWR
HS[0:3]
with R = 5.0Ω resistive load.
L
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED)
Fault Detection Blanking Time(28)
Output Shutdown Delay Time(29)
tFAULT
tDETECT
tCNSVAL
tWDTO
1.0
–
5.0
7.0
70
20
30
μs
μs
CSNS Valid Time(30)
–
100
400
195
μs
Watchdog Time-out(31)
217
105
310
150
ms
ms
ON Open-Load Fault Cyclic Detection Time with LED
T
OLD(LED)
Notes
28. Time necessary to report the fault to FS pin.
29. Time necessary to switch-off the output in case of OT or OC or SC or UV fault detection (from negative edge of FS pin to HS voltage =
50% of VPWR
30. Time necessary for CSNS to be within ±5% of the targeted value (from HS voltage = 50% of VPWR to ±5% of the targeted CSNS value).
31. For FSI open, the Watchdog timeout delay measured from the rising edge of RST, to HS[0,2] output state depend on the corresponding
input command.
10XS3435
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED)
HS[0,1] Output Over-current Time Step for 28W bit = 0
OC[1:0]=00 (slow by default)
ms
tOC1_00
tOC2_00
tOC3_00
tOC4_00
tOC5_00
tOC6_00
tOC7_00
4.40
1.62
2.10
2.88
4.58
10.16
73.2
6.30
2.32
8.02
3.00
3.00
3.90
4.12
5.36
6.56
8.54
14.52
104.6
18.88
134.0
OC[1:0]=01 (fast)
tOC1_01
tOC2_01
tOC3_01
tOC4_01
tOC5_01
tOC6_01
tOC7_01
1.10
0.40
0.52
0.72
1.14
2.54
18.2
1.57
0.58
0.75
1.03
1.64
3.63
26.1
2.00
0.75
0.98
1.34
2.13
4.72
34.0
OC[1:0]=10 (medium)
tOC1_10
tOC2_10
tOC3_10
tOC4_10
tOC5_10
tOC6_10
tOC7_10
2.20
0.81
1.05
1.44
2.29
5.08
36.6
3.15
1.16
1.50
2.06
3.28
7.26
52.3
4.01
1.50
1.95
2.68
4.27
9.44
68.0
OC[1:0]=11 (very slow)
tOC1_11
tOC2_11
tOC3_11
tOC4_11
tOC5_11
tOC6_11
tOC7_11
8.8
3.2
12.6
4.6
16.4
21.4
7.8
4.2
6.0
5.7
8.2
10.7
17.0
37.7
272.0
9.1
13.1
29.0
209.2
20.3
146.4
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED)
HS[0,1] Output Over-current Time Step for 28W bit = 1
HS[2,3] Output Over-current Time Step
OC[1:0]=00 (slow by default)
ms
tOC1_00
tOC2_00
tOC3_00
tOC4_00
tOC5_00
tOC6_00
tOC7_00
3.4
1.1
1.4
2.0
3.4
8.5
62.4
4.9
1.6
6.4
2.1
2.1
2.8
2.9
3.8
4.9
6.4
12.2
89.2
15.9
116.0
tOC1_01
tOC2_01
tOC3_01
tOC4_01
tOC5_01
tOC6_01
tOC7_01
0.86
0.28
0.36
0.51
0.78
2.14
20.2
1.24
0.40
0.52
0.74
1.12
3.06
22.2
1.61
0.52
0.68
0.96
1.46
3.98
28.9
OC[1:0]=01 (fast)
tOC1_10
tOC2_10
tOC3_10
tOC4_10
tOC5_10
tOC6_10
tOC7_10
1.7
0.5
0.7
1.0
1.7
4.2
31.2
2.5
0.8
1.0
1.5
2.5
6.1
44.6
3.3
1.0
1.3
2.0
3.3
6.0
58.0
OC[1:0]=10 (medium)
tOC1_11
tOC2_11
tOC3_11
tOC4_11
tOC5_11
tOC6_11
tOC7_11
6.8
2.2
9.8
3.2
12.8
16.7
5.5
OC[1:0]=11 (very slow)
2.9
4.2
4.0
5.8
7.6
6.8
9.8
12.8
31.8
232.0
17.0
124.8
24.4
178.4
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED)
HS[0,1] Bulb Cooling Time Step for 28W bit = 0
CB[1:0]=00 or 11 (medium)
ms
tBC1_00
tBC2_00
tBC3_00
tBC4_00
tBC5_00
tBC6_00
242
126
140
158
181
211
347
181
200
226
259
302
452
236
260
294
337
393
CB[1:0]=01 (fast)
tBC1_01
tBC2_01
tBC3_01
tBC4_01
tBC5_01
tBC6_01
121
63
173
90
226
118
130
147
169
197
70
100
113
129
151
79
90
105
CB[1:0]=10 (slow)
tBC1_10
tBC2_10
tBC3_10
tBC4_10
tBC5_10
tBC6_10
484
252
280
316
362
422
694
362
400
452
518
604
1904
472
520
588
674
786
HS[0,1] for 28W bit = 1 or for HS2-HS3
CB[1:0]=00 or 11 (medium)
tBC1_00
tBC2_00
tBC3_00
tBC4_00
tBC5_00
tBC6_00
291
156
178
208
251
314
417
224
255
298
359
449
542
292
332
388
467
584
CB[1:0]=01 (fast)
tBC1_01
tBC2_01
tBC3_01
tBC4_01
tBC5_01
tBC6_01
146
78
209
112
127
145
180
324
272
146
166
189
234
422
88
101
126
226
CB[1:0]=10 (slow)
tBC1_10
tBC2_10
tBC3_10
tBC4_10
tBC5_10
tBC6_10
583
312
357
417
501
628
834
448
510
596
717
898
1085
582
665
775
933
1170
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
PWM MODULE TIMING
Input PWM Clock Range on IN0
fIN0
7.68
1.0
100
–
–
2.0
–
30.72
4.0
400
1.0
+10
156
26
kHz
kHz
kHz
Hz
%
Input PWM Clock Low Frequency Detection Range on IN0(33)
Input PWM Clock High Frequency Detection Range on IN0(33)
Output PWM Frequency Range using external clock on IN0
Output PWM Frequency Accuracy using Calibrated Oscillator
Default Output PWM Frequency using Internal Oscillator
CS Calibration Low Minimum Time Detection Range
CS Calibration Low Maximum Tine Detection Range
Output PWM Duty-Cycle Range for fpwm = 1kHz for high speed slew rate(33)
Output PWM Duty-Cycle Range for fpwm = 400Hz(33)
Output PWM Duty-Cycle Range for fpwm = 200Hz(33)
INPUT TIMING
fIN0(LOW)
fIN0(HIGH)
fPWM
–
AFPWM(CAL)
fPWM(0)
-10
84
–
120
20
200
Hz
μs
tCSB(MIN)
tCSB(MAX)
RPWM_1k
RPWM_400
RPWM_200
14
140
10
260
94
μs
%
6.0
5.0
98
%
98
%
Direct Input Toggle Time-out
tIN
175
105
250
150
325
195
ms
ms
AUTORETRY TIMING
Autoretry Period
tAUTO
TEMPERATURE ON THE GND FLAG
Thermal Prewarning Detection(34)
TOTWAR
TFEED
110
1.15
-3.5
125
1.20
-3.7
140
1.25
-3.9
°C
V
Analog Temperature Feedback at TA = 25°C with RCSNS=2.5kΩ
Analog Temperature Feedback Derating with RCSNS=2.5kΩ(35)
Notes
DTFEED
mV/°C
32. Clock Fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0].
33. The PWM ratio is measured at VHS = 50% of VPWR and for the default SR value. It is possible to put the device fully-on (PWM duty-cycle
100%) and fully-off (duty-cycle 0%). For values outside this range, a calibration is needed between the PWM duty-cycle programming
and the PWM on the output with R = 5.0Ω resistive load.
L
34. Typical value guaranteed per design.
35. Value guaranteed per statistical analysis.
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
SPI INTERFACE CHARACTERISTICS(36)
Symbol
Min
Typ
Max
Unit
Maximum Frequency of SPI Operation
fSPI
tWRST
tCS
–
10
–
–
–
–
–
–
–
–
–
–
–
8.0
–
MHz
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
Required Low State Duration for RST(37)
Rising Edge of CS to Falling Edge of CS (Required Setup Time)(38)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)(38)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(38)
Required High State Duration of SCLK (Required Setup Time)(38)
Required Low State Duration of SCLK (Required Setup Time)(38)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(38)
SI to Falling Edge of SCLK (Required Setup Time)(39)
1.0
5.0
500
50
50
60
37
49
tENBL
–
tLEAD
–
tWSCLKh
tWSCLKl
tLAG
–
–
–
tSI(SU)
tSI(HOLD)
tRSO
–
Falling Edge of SCLK to SI (Required Setup Time)(39)
–
SO Rise Time
CL = 80 pF
–
–
13
SO Fall Time
CL = 80 pF
tFSO
ns
–
–
13
SI, CS, SCLK, Incoming Signal Rise Time(39)
tRSI
tFSI
tSO(EN)
tSO(DIS)
–
–
–
–
–
–
–
–
13
13
60
60
ns
ns
ns
ns
SI, CS, SCLK, Incoming Signal Fall Time(39)
Time from Falling Edge of CS to SO Low Impedance(40)
Time from Rising Edge of CS to SO High Impedance(41)
Notes
36. Parameters guaranteed by design.
37. RST low duration measured with outputs enabled and going to OFF or disabled condition.
38. Maximum setup time required for the 10XS3435 is the minimum guaranteed time needed from the microcontroller.
39. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
40. Time required for output status data to be available for use at SO. 1.0kΩ on pull-up on CS.
41. Time required for output status data to be terminated at SO. 1.0kΩ on pull-up on CS.
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
IN[0:3]
High logic level
Low logic level
Time
Time
Time
or
CS
High logic level
Low logic level
VHS[0:3]
V
PWR
R
PWM
50%V
PWR
tDLY(OFF)
tDLY(ON)
VHS[0:3]
70% V
PWR
SRF
SRR
30% V
PWR
Time
Figure 4. Output Slew Rate and Time Delays
I
OCH1
I
I
OCH2
OC1
OC2
Load
Current
I
I
I
OC3
OC4
I
I
I
OCLO4
OCLO3
OCLO2
I
OCLO1
Time
t
t
t
t
OC7
OC3
OC1
t
OC5
t
OC6
t
OC4
OC2
Figure 5. Over-current Shutdown Protection
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
I
OCH1
OCH2
I
I
OC1
OC2
I
I
I
I
I
OC3
OC4
OCLO4
OCLO3
I
I
OCLO2
OCLO1
Previous OFF duration
(toff)
t
t
t
B
C5
B
B
C3
C1
t
B
C6
t
B
C4
t
B
C2
Figure 6. Bulb Cooling Management
V
IH
RST
10% VDD
0.2 VDD
VIL
tCS
t
ENBL
t
WRST
90% V
DD
V
IH
CS
10%V
DD
V
IL
t
RSI
TrSI
t
WSCLKH
t
LEAD
t
LAG
90% VDD
V
IH
SCLK
10% VDD
V
IL
t
SI(SU)
t
WSCLKl
t
FSI
t
SI(HOLD)
V
IH
90%V
DD
Don’t Care
Don’t Care
Don’t Care
Valid
Valid
SI
10%V
DD
V
IH
Figure 7. Input Timing Switching Characteristics
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
t
t
FSI
RSI
VOH
90% V
DD
50%
SCLK
10% VDD
VOL
tSO(EN)
10%VDD
VOH
90% V
DD
SO
VOL
Low to High
tRSO
tVALID
tFSO
SO
VOH
90% V
DD
High to Low
10% VDD
VOL
tSO(DIS)
Figure 8. SCLK Waveform and Valid SO Data Delay Time
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 10XS3435 is one in a family of devices designed for
low-voltage automotive lighting applications. Its four low
RDS(ON) MOSFETs (dual 10mΩ, dual 35 mΩ) can control four
separate 55W / 28W bulbs and/or Xenon modules.
Additionally, each output has its own parallel input or SPI
control for pulse-width modulation (PWM) control if desired.
The 10XS3435 allows the user to program via the SPI the
fault current trip levels and duration of acceptable lamp
inrush. The device has fail-safe mode to provide fail-safe
functionality of the outputs in case of MCU damaged.
Programming, control and diagnostics are accomplished
using a 16-bit SPI interface. Its output with selectable slew-
rate improves electromagnetic compatibility (EMC) behavior.
FUNCTIONAL PIN DESCRIPTION
the device is capable of transferring information to, and
receiving information from, the MCU. The 10XS3435 latches
in data from the Input Shift registers to the addressed
registers on the rising edge of CS. The device transfers status
information from the power output to the Shift register on the
falling edge of CS. The SO output driver is enabled when CS
is logic [0]. CS should transition from a logic [1] to a logic [0]
state only when SCLK is a logic [0]. CS has an active internal
OUTPUT CURRENT MONITORING (CSNS)
The Current Sense pin provides a current proportional to
the designated HS0:HS3 output or a voltage proportional to
the temperature on the GND flag. That current is fed into a
ground-referenced resistor (2.5kΩ typical) and its voltage is
monitored by an MCU's A/D. The output type is selected via
the SPI. This pin can be tri-stated through the SPI.
pull-up from VDD, IUP
.
DIRECT INPUTS (IN0, IN1, IN2, IN3)
SERIAL CLOCK (SCLK)
Each IN input wakes the device. The IN0:IN3 high side
input pins are also used to directly control HS0:HS3 high side
output pins. In case of the outputs are controlled by PWM
module, the external PWM clock is applied to IN0 pin. These
pins are to be driven with CMOS levels, and they have a
The SCLK pin clocks the internal shift registers of the
10XS3435 device. The serial input (SI) pin accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output (SO) pin shifts data information out of
the SO line driver on the rising edge of the SCLK signal. It is
important the SCLK pin be in a logic low state whenever CS
makes any transition. For this reason, it is recommended the
SCLK pin be in a logic [0] whenever the device is not
accessed (CS logic [1] state). SCLK has an active internal
pull-down. When CS is logic [1], signals at the SCLK and SI
pins are ignored and SO is tri-stated (high impedance) (see
Figure 10, page 26). SCLK input has an active internal pull-
passive internal pull-down, RDWN
.
FAULT STATUS (FS)
This pin is an open drain configured output requiring an
external pull-up resistor to VDD for fault reporting. If a device
fault condition is detected, this pin is active LOW. Specific
device diagnostics and faults are reported via the SPI SO pin.
down, IDWN
.
WAKE
The wake input wakes the device. An internal clamp
protects this pin from high damaging voltages with a series
resistor (10kΩ typ). This input has a passive internal pull-
SERIAL INPUT (SI)
This is a serial interface (SI) command data input pin.
Each SI bit is read on the falling edge of SCLK. A 16-bit
stream of serial data is required on the SI pin, starting with
D15 (MSB) to D0 (LSB). The internal registers of the
10XS3435 are configured and controlled using a 5-bit
addressing scheme described in Table 9, page 34. Register
addressing and configuration are described in Table 10,
down, RDWN
.
RESET (RST)
The reset input wakes the device. This is used to initialize
the device configuration and fault registers, as well as place
the device in a low-current sleep mode. The pin also starts
the watchdog timer when transitioning from logic [0] to
page 34. SI input has an active internal pull-down, IDWN
.
DIGITAL DRAIN VOLTAGE (VDD)
logic [1]. This pin has a passive internal pull-down, RDWN
.
This pin is an external voltage input pin used to supply
power to the SPI circuit. In the event VDD is lost (VDD Failure),
the device goes to Fail-safe mode.
CHIP SELECT (CS)
The CS pin enables communication with the master
microcontroller (MCU). When this pin is in a logic [0] state,
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
GROUND (GND)
HIGH SIDE OUTPUTS (HS3, HS1, HS0, HS2)
These pins are the ground for the device.
Protected 10mΩ and 12mΩ high side power outputs to the
load.
POSITIVE POWER SUPPLY (VPWR)
FAIL-SAFE INPUT (FSI)
This pin connects to the positive power supply and is the
source of operational power for the device. The VPWR
contact is the backside surface mount tab of the package.
This pin incorporates an active internal pull-up current
source from internal supply (VREG). This enables the
watchdog time-out feature.
SERIAL OUTPUT (SO)
When the FSI pin is opened, the Watchdog circuit is
enabled. After a Watchdog timeout occurs, the output states
depends on IN[0:3].
The SO data pin is a tri-stateable output from the shift
register. The SO pin remains in a high impedance state until
the CS pin is put into a logic [0] state. The SO data is capable
of reporting the status of the output, the device configuration,
the state of the key inputs, etc. The SO pin changes state on
the rising edge of SCLK and reads out on the falling edge of
SCLK. SO reporting descriptions are provided in Table 22,
page 38.
When the FSI pin is connected to GND, the Watchdog
circuit is disabled. The output states depends on IN[0:3] in
case of VDD Failure condition, in case VDD failure detection
is activated (VDD_FAIL_en bit sets to logic [1]).
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC10XS3435 - Functional Block Diagram
Power Supply
MCU Interface & Output Control
SPI Interface
Self-Protected
High-Side
Switches
HS0-HS3
Parallel Control Inputs
PWM Controller
MCU
Interface
Supply
MCU Interface & Output Control
Self-Protected High-Side Switches
Figure 9. Functional Block Diagram
loads demanding multiple switching, an external
POWER SUPPLY
recirculation device must be used to maintain the device in its
Safe Operating Area.
The 10XS3412B is designed to operate from 4.0V to 28V
on the VPWR pin. Characteristics are provided from 6.0 V to
20V for the device. The VPWR pin supplies power to internal
regulator, analog, and logic circuit blocks. The VDD supply is
used for Serial Peripheral Interface (SPI) communication in
order to configure and diagnose the device. This IC
architecture provides a low quiescent current sleep mode.
Applying VPWR and VDD to the device will place the device in
the Normal mode. The device will transit to Fail-safe mode in
case of failures on the SPI or/and on VDD voltage.
MCU INTERFACE AND OUTPUT CONTROL
In Normal mode, each bulb is controlled directly from the
MCU through SPI. A pulse width modulation control module
allows improvement of lamp lifetime with bulb power
regulation (PWM frequency range from 100Hz to 400Hz) and
addressing the dimming application (day running light). An
analog feedback output provides a current proportional to the
load current or the temperature of the board. The SPI is used
to configure and to read the diagnostic status (faults) of high
side outputs. The reported fault conditions are: open-load,
short-circuit to battery, short-circuit to ground (over-current
and severe short-circuit), thermal shut-down, and under/
over-voltage. Thanks to accurate and configurable over-
current detection circuitry and wire-harness optimization, the
vehicle is lighter.
HIGH SIDE SWITCHES: HS0–HS3
These pins are the high side outputs controlling
automotive lamps located for the front of vehicle, such as
65W/55W bulbs and Xenon-HID modules. Those N-channel
MOSFETs with 10mΩ & 35mΩ RDS(ON) are self-protected
and present extended diagnostics in order to detect bulb
outage and short-circuit fault condition. The HS output is
actively clamped during turn off of inductive loads and
inductive battery line. When driving DC motor or Solenoid
In Fail-safe mode, each lamp is controlled with dedicated
parallel input pins. The device is configured in default mode.
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL DEVICE OPERATION
The SI/SO pins of the 10XS3435 follow a first-in first-out
(D15 to D0) protocol, with both input and output words
transferring the most significant bit (MSB) first. All inputs are
compatible with 5.0V or 3.3V CMOS logic levels.
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK),
and Chip Select (CS).
CS
SCLK
SI
D15
D14
D13
D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Notes 1. RST is a logic [1] state during the above operation.
2. D15 D0 relate to the most recent ordered entry of data into the device.
:
3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device.
Figure 10. Single 16-Bit Word SPI Communication
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
OPERATIONAL MODES
The 10XS3435 has four operating modes: Sleep, Normal,
Fail-Safe and Fault. Table 5 and Figure 12 summarize details
contained in succeeding paragraphs.
Table 5. 10XS3435 Operating Modes
Mode wake-up fail fault
Comments
The Figure 11 describes an internal signal called IN_ON[x]
depending on IN[x] input.
Sleep
0
x
x
Device is in Sleep mode. All
outputs are OFF.
Normal
1
0
0
Device is currently in Normal
mode. Watchdog is active if
enabled.
tIN
IN[x]
Fail-Safe
1
1
1
0
1
Device is currently in Fail-safe
mode due to Watchdog time-
out or VDD Failure conditions.
The output states are defined
with the RFS resistor
IN_ON[x]
Figure 11. IN_ON[x] internal signal
connected to FSI.
The 10XS3435 transits to operating modes according to
the following signals:
Fault
X
Device is currently in fault
mode. The faulted output(s) is
(are) OFF. The safe autoretry
circuitry is active to turn-on
again the output(s).
• wake-up = RST or WAKE or IN_ON[0] or IN_ON[1] or
IN_ON[2] or IN_ON[3],
• fail = (VDD Failure and VDD_FAIL_en) or (Watchdog
time-out and FSI input not shorted to ground),
• fault = OC[0:3] or OT[0:3] or SC[0:3] or UV or (OV and
OV_dis).
x = Don’t care.
(fail=0) and (wake-up=1) and (fault=0)
(wake-up=0)
Sleep
(wake-up=0)
(wake-up=1) and
(fail=1)
and (fault=0)
(wake-up=1)
and (fault=1)
(wake-up=0)
(fail=1) and
(wake-up=1)
and (fault=1)
(fail=0) and
(wake-up=1)
and (fault=1)
Fault
Normal
(fail=0) and
(wake-up=1)
and (fault=0)
(fail=1) and
(wake-up=1)
and (fault=0)
Fail-Safe
(fail=0) and (wake-up=1) and (fault=0)
(fail=1) and (wake-up=1) and (fault=0)
Figure 12. Operating Modes
10XS3435
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Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
the range of 5% to 98% with a resolution of 7 bits of duty cycle
(Table 6). The state of other IN pin is ignored.
SLEEP MODE
The 10XS3435 is in Sleep mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 0,
• fail = X,
Table 6. Output PWM Resolution
On bit
Duty cycle
X
Output state
OFF
• fault = X.
0
1
1
1
1
1
This is the Default mode of the device after first applying
battery voltage (VPWR) prior to any I/O transitions. This is
also the state of the device when the WAKE and RST and
IN_ON[0:3] are logic [0]. In the Sleep mode, the output and
all unused internal circuitry, such as the internal regulator, are
off to minimize draw current. In addition, all SPI-configurable
features of the device are as if set to logic [0].
0000000
0000001
0000010
n
PWM (1/128 duty cycle)
PWM (2/128 duty cycle)
PWM (3/128 duty cycle)
PWM ((n+1)/128 duty cycle)
fully ON
1111111
In the event of an external VPWR supply disconnect, an
unexpected current consumption may sink on the VDD
supply pin (In Sleep State). This current leakage is about
70mA instead of 5.0µA and it may impact the device
reliability. The device recovers its normal operational mode
once VPWR is reconnected.
The timing includes seven programmable PWM switching
delay (number of PWM clock rising edges) to improve overall
EMC behavior of the light module (Table 7).
Table 7. Output PWM Switching Delay
To avoid this unexpected current leakage on the VDD
supply pin, maintain the device in Normal Mode with RST pin
set to logic[1]. This will allow diagnosis of the battery
disconnection event through UV fault reporting in SPI. Then,
apply 0V on VDD supply pin to switch the device to Sleep
State.
Delay bits
Output delay
000
001
010
011
100
101
110
111
no delay
16 PWM clock periods
32 PWM clock periods
48 PWM clock periods
64 PWM clock periods
80 PWM clock periods
96 PWM clock periods
112 PWM clock periods
NORMAL MODE
The 10XS3435 is in Normal mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = 0,
• fault = 0.
The clock frequency from IN0 is permanently monitored in
order to report a clock failure in case of the frequency is out
a specified frequency range (from fIN0(LOW) to fIN0(HIGH)). In
In this mode, the NM bit is set to lfault_contrologic [1] and
the outputs HS[0:3] are under control, as defined by hson
signal:
case of clock failure, no PWM feature is provided, the On bit
defines the outputs state and the CLOCK_fail bit reports [1].
hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en
) or (On bit [x] and Duty_cycle[x] and PWM_en).
Calibratable internal clock
In this mode and also in Fail-safe, the fault condition reset
depends on fault_control signal, as defined below:
The internal clock can vary as much as +/-30 percent
corresponding to typical fPWM(0) output switching period.
fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en )
or (On bit [x]).
Using the existing SPI inputs and the precision timing
reference already available to the MCU, the 10XS3435
allows clock period setting within +/-10 percent of accuracy.
Calibrating the internal clock is initiated by defined word to
CALR register. The calibration pulse is provided by the MCU.
The pulse is sent on the CS pin after the SPI word is
launched. At the moment, the CS pin transitions from logic [1]
to [0] until from logic [0] to [1] determine the period of internal
clock with a multiplicative factor of 128.
Programmable PWM module
The outputs HS[0:3] are controlled by the programmable
PWM module if PWM_en and On bits are set to logic [1].
The clock frequency from IN0 input pin or from internal
clock is the factor 27 (128) of the output PWM frequency
(CLOCK_sel bit). The outputs HS[0:3] can be controlled in
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
During the Fail-safe mode, the outputs will depend on the
corresponding input. The SPI register content is reset to their
default value (except POR bit) and fault protections are fully
operational.
CS
SI
The Fail-safe mode can be detected by monitoring the NM
bit is set to [0].
NORMAL & FAIL-SAFE MODE TRANSITIONS
Transition Fail-safe to Normal mode
SI command
ignored
CALR
To leave the Fail-safe mode, VDD must be in nominal
voltage and the microcontroller has to send a SPI command
with WDIN bit set to logic [1] ; the other bits are not
considered. The previous latched faults are reset by the
transition into Normal mode (autoretry included).
Internal
clock duration
In case of negative CS pulse is outside a predefined time
range (from tCSB(MIN) to tCSB(MAX)), the calibration event will
Moreover, the device can be brought out of the Fail-safe
mode due to watchdog timeout issue by forcing the FSI pin to
logic [0].
be ignored and the internal clock will be unaltered or reset to
default value (fPWM(0)) if this was not calibrated before.
The calibratable clock is used, instead of the clock from
IN0 input, when CLOCK_sel is set to [1].
Transition Normal to Fail-Safe mode
To leave the Normal mode, a fail-safe condition must
occurred (fail=1). The previous latched faults are reset by the
transition into Fail-safe mode (autoretry included).
FAIL-SAFE MODE
The 10XS3435 is in Fail-safe mode when:
• VPWR is within the normal voltage range,
• wake-up = 1,
• fail = 1,
• fault = 0.
FAULT MODE
The 10XS3435 is in Fault mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = X,
• fault=1.
Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or IN_ON[0:3] or
RST input pin transitions from logic [0] to logic [1]. The WAKE
input is capable of being pulled up to VPWR with a series of
limiting resistance limiting the internal clamp current
according to the specification.
This device indicates the faults below as they occur by
driving the FS pin to logic [0] for RST input is pulled up:
•Over-temperature fault,
•Over-current fault,
•Severe short-circuit fault,
The Watchdog timeout is a multiple of an internal
oscillator. As long as the WD bit (D15) of an incoming SPI
message is toggled within the minimum watchdog timeout
period (WDTO), the device will operate normally.
•Output(s) shorted to VPWR fault in OFF state,
•Open-load fault in OFF state,
•Over-voltage fault (enabled by default),
•Under-voltage fault.
Fail-Safe conditions
The FS pin will automatically return to logic [1] when the
fault condition is removed, except for over-current, severe
short-circuit, over-temperature and under-voltage which will
be reset by a new turn-on command (each fault_control
signal to be toggled).
If an internal watchdog time-out occurs before the WD bit
for FSI open (Table 8) or in case of VDD failure condition
(VDD< VDD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the
device will revert to a Fail-safe mode until the WD bit is written
to logic [1] (see fail-safe to normal mode transition paragraph)
and VDD is within the normal voltage range.
Fault information is retained in the SPI fault register and is
available (and reset) via the SO pin during the first valid SPI
communication.
Table 8. SPI Watchdog Activation
The Open load fault in ON state is only reported through
SPI register without effect on the corresponding output state
(HS[x]) and the FS pin.
Typical RFSI (Ω)
Watchdog
0 (shorted to ground)
(open)
Disabled
Enable
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
START-UP SEQUENCE
The 10XS3435 enters in Normal mode after start-up if
following sequence is provided:
•VPWR and VDD power supplies must be above their
under-voltage thresholds,
•generate wake-up event (wake-up=1) from 0 to 1 on
RSTB. The device switches to normal mode with SPI
register content is reset (as defined in Table 10 and
Table 22). All features of the 10XS3435 will be available
after 50μs typical, and all SPI registers are set to default
values (set to logic [0]).
•toggle WD bit from 0 to 1.
And, in case of the PWM module is used (PWM_en bit is
set to logic [1]) with an external reference clock:
•apply PWM clock on IN0 input pin after maximum 200μs
(min. 50μs).
If the correct start-up sequence is not provided, the PWM
function is not guaranteed.
PROTECTION AND DIAGNOSTIC FEATURES
or an autoretry define this event. In this case, the over-current
protection will be fitted to inrush current, as shown in
Figure 5. This over-current protection is programmable:
OC[1:0] bits select over-current slope speed and OCHI1
current step can be removed in case of OCHI bit is set to [1].
PROTECTIONS
Over-temperature Fault
The 10XS3435 incorporates over-temperature detection
and shutdown circuitry for each output structure.
Two cases need to be considered when the output
temperature is higher than TSD
:
Over-current thresholds
•If the output command is ON: the corresponding output is
latched OFF. FS will be also latched to logic [0]. To
delatch the fault and be able to turn ON again the
outputs, the failure condition must disappear and the
autoretry circuitry must be active or the corresponding
output must be commanded OFF and then ON (toggling
fault_control signal of corresponding output) or
VSUPPLY(POR) condition if VDD = 0.
fault_control
•If the output command is OFF: FS will go to logic [0] till
the corresponding output temperature will be below
hson
TSD
.
For both cases, the fault register OT[0:3] bit into the status
register will be set to [1]. The fault bits will be cleared in the
status register after a SPI read command.
In steady state, the wire harness will be protected by
OCLO2 current level by default. Three other DC over-current
levels are available: OCLO1 or OCLO3 or OCLO4 based on
the state of the OCLO[1,0] bits.
Over-current Fault
The 10XS3435 incorporates output shutdown in order to
protect each output structure against resistive short-circuit
condition. This protection is composed by eight predefined
current levels (time dependent) to fit Xenon-HID manners by
default or, 55W or 28W bulb profiles, selectable separately
by Xenon bit and 28W bits (as illustrated Figure 14, page 36).
If the load current level ever reaches the over-current
detection level, the corresponding output will latch the output
OFF and FS will be also latched to logic [0]. To delatch the
fault and be able to turn ON again the corresponding output,
the failure condition must disappear and the autoretry
circuitry must be active or the corresponding output must be
commanded OFF and then ON (toggling fault_control signal
In the first turn-on, the lamp filament is cold and the current
will be huge. fault_control signal transition from logic [0] to [1]
10XS3435
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Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
of corresponding output) or VSUPPLY(POR) condition if VDD
0.
=
during an over-voltage fault condition on the VPWR pin
(VPWR > VPWR(OV)). The outputs remain in the OFF state until
the over-voltage condition is removed (VPWR < VPWR(OV)
-
The SPI fault report (OC[0:3] bits) is removed after a read
operation.
VPWR(OVHYS)). When experiencing this fault, the OVF fault bit
is set to logic [1] and cleared after either a valid SPI read.
In Normal mode using internal PWM module, the
10XS3435 incorporates also a cooling bulb filament
management if OC_mode and Xenon are set to logic [1]. In
this case, the 1st step of multi-step over-current protection will
depend to the previous OFF duration, as illustrated in
Figure 6. The following figure illustrates the current level will
be used in function to the duration of previous OFF state
(toff). The slope of cooling bulb emulator is configurable with
OCOFFCB[1:0] bits.
The over-voltage protection can be disabled through SPI
(OV_dis bit is disabled set to logic [1]). The fault register
reflects any over-voltage condition (VPWR > VPWR(OV)). This
over-voltage diagnosis, as a warning, is removed after a read
operation, if the fault condition disappears. The HS[0:3]
outputs are not commanded in RDS(ON) above the OV
threshold.
Under-voltage Fault
The output(s) will latch off at some battery voltage below
VPWR(UV). As long as the VDD level stays within the normal
Depending on toff
specified range, the internal logic states within the device will
remain (configuration and reporting).
Over-current thresholds
Cooling
In the case where battery voltage drops below the under-
voltage threshold (VPWR < VPWR(UV)), the outputs will turn off,
FS will go to logic [0], and the fault register UV bit will be set
to [1].
toff
fault_control
Two cases need to be considered when the battery level
recovers (VPWR > VPWR(UV)_UP):
•
If outputs command are low, FS will go to logic [1] but
the UV bit will remain set to 1 until the next read
operation (warning report).
hson
•
If the output command is ON, FS will remain at logic [0].
To delatch the fault and be able to turn ON again the
outputs, the failure condition must disappear and the
autoretry circuitry must be active or the corresponding
output must be commanded OFF and then ON
(toggling fault_control signal of corresponding output)
or VSUPPLY(POR) condition if VDD = 0.
Severe Short-Circuit Fault
The 10XS3435 provides output shutdown in order to
protect each output in case of severe short-circuit during of
the output switching.
In extended mode, the output is protected by over-
temperature shutdown circuitry. All previous latched faults,
occurred when VPWR was within the normal voltage range,
are guaranteed if VDD is within the operational voltage range
or until VSUPPLY(POR) if VDD = 0. Any new OT fault is
detected (VDD failure included) and reported through SPI
above VPWR(UV). The output state is not changed as long as
the VPWR voltage does not drop any lower than 3.5 V typical.
If the short-circuit impedance is below R
, the device
SHORT
will latch the output OFF, FS will go to logic [0] and the fault
register SC[0:3] bit will be set to [1]. To delatch the fault and
be able to turn ON again the outputs, the failure condition
must disappear and the corresponding output must be
commanded OFF and then ON (toggling fault_control signal
of corresponding output) or VSUPPLY(POR) condition if VDD
=
0.
All latched faults (over-temperature, over-current, severe
short-circuit, over and under-voltage) are reset if:
• VDD < VDD(FAIL) with VPWR in nominal voltage range,
•VDD and VPWR supplies is below VSUPPLY(POR) voltage
value.
The SPI fault report (SC[0:3] bits) is removed after a read
operation.
Over-voltage Fault (Enabled by default)
By default, the over-voltage protection is enabled. The
10XS3435 shuts down all outputs and FS will go to logic [0]
10XS3435
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Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
(fault_control=0)
(OpenloadON=1)
(OpenloadOFF=1
or ShortVpwr=1
or OV=1)
(OpenloadOFF=1
or ShortVpwr=1
or OV=1)
(fault_control=1 and OV=0)
OFF
if hson=0
(SC=1)
ON
Latched
if hson=1
(fault_control=0 or OV=1)
(fault_control=0)
OFF
(count=16)
(Retry=1)
(SC=1)
(OpenloadON=1)
(after Retry Period and OV=0)
(OV=1)
Autoretry
OFF
Autoretry
ON
if hson=1
(Retry=1)
=> count=count+1
(OpenloadOFF=1
or ShortVpwr=1
or OV=1)
(fault_control=0)
Figure 13. Auto-retry State Machine
status register after the internal gate voltage is pulled low
enough to turn OFF the output. The OS[0:3] and
OL_OFF[0:3] fault bits are set in the status register and FS
pin reports in real time the fault. If the output shorted to
VPWR fault is removed, the status register will be cleared
after reading the register.
AUTO-RETRY
The auto-retry circuitry is used to reactivate the output(s)
automatically in case of over-current or over-temperature or
under-voltage failure conditions to provide a high availability
of the load.
Auto-retry feature is available in Fault mode. It is activated
in case of internal retry signal is set to logic [1]:
The open output shorted to VPWR protection can be
disabled through SPI (OS_DIS[0:3] bit).
retry[x] = OC[x] or OT[x] or UV.
Open-Load Faults
The feature retries to switch-on the output(s) after one
auto-retry period (tAUTO) with a limitation in term of number of
The 10XS3435 incorporates three dedicated open-load
detection circuitries on the output to detect in OFF and in ON
state.
occurrence (16 for each output). The counter of retry
occurrences is reset in case of Fail-safe to Normal or Normal
to Fail-safe mode transitions. At each auto-retry, the over-
current detection will be set to default values in order to
sustain the inrush current.
Open-load Detection In Off State
The OFF output open-load fault is detected when the
output voltage is higher than VOLD(THRES) pulled up with
The Figure 13 describes the auto-retry state machine.
internal current source (IOLD(OFF)) and reported as a fault
condition when the output is disabled (OFF). The OFF Output
open-load fault is latched into the status register or when the
internal gate voltage is pulled low enough to turn OFF the
output. The OL_OFF[0:3] fault bit is set in the status register.
If the open load fault is removed (FS output pin goes to high),
the status register will be cleared after reading the register.
DIAGNOSTIC
Output Shorted to VPWR Fault
The 10XS3435 incorporates output shorted to VPWR
detection circuitry in OFF state. Output shorted to VPWR fault
is detected if output voltage is higher than V
and
OSD(THRES)
The OFF output open-load protection can be disabled
through SPI (OLOFF_DIS[0:3] bit).
reported as a fault condition when the output is disabled
(OFF). The output shorted to VPWR fault is latched into the
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
32
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Open-load Detection In On State
GROUND DISCONNECT PROTECTION
The ON output open-load current thresholds can be
chosen by SPI to detect a standard bulbs or LEDs
(OLLED[0:3] bit set to logic [1]). In the case where load
current drops below the defined current threshold OLON bit
is set to logic [1], the output stays ON and FS is not disturbed.
In the event the 10XS3435 ground is disconnected from
load ground, the device protects itself and safely turns OFF
the output regardless of the state of the output at the time of
disconnection (maximum VPWR = 16V). A 10kΩ resistor
needs to be added between the MCU and each digital input
pin in order to ensure that the device turns off in case of
ground disconnect and to prevent this pin from exceeding
maximum ratings.
Open-load Detection In On State For Led
Open load for LEDs only (OLLED[0:3] set to logic [1]) is
detected periodically each tOLLED (fully-on, D[6:0]=7F). To
LOSS OF SUPPLY LINES
Loss of VDD
detect OLLED in fully-on state, the output must be ON at least
tOLLED.
To delatch the diagnosis, the condition should be removed
and SPI read operation is needed (OL_ON[0:3] bit). The ON
output open-load protection can be disabled through SPI
(OLON_DIS[0:3] bit).
If the external VDD supply is disconnected (or not within
specification: VDD < VDD(FAIL)) with VDD_FAIL_en bit is set
to logic [1]), all SPI register content is reset.
The outputs can still be driven by the direct inputs IN[0:3]
if VPWR is within specified voltage range. The 10XS3435
Analog Current Recopy and Temperature Feedbacks
The CSNS pin is an analog output reporting a current
proportional to the designed output current or a voltage
proportional to the temperature of the GND flag (pin #14).
The routing is SPI programmable (TEMP_en, CSNS_en,
CSNS_s[1,0] and CSNS_ratio_s bits).
uses the battery input to power the output MOSFET-related
current sense circuitry and any other internal logic providing
Fail-safe device operation with no VDD supplied. In this state,
the over-temperature, over-current, severe short-circuit,
short to VPWR and OFF open-load circuitry are fully
operational with default values corresponding to all SPI bits
are set to logic [0]. No current is conducted from VPWR to
In case the current recopy is active, the CSNS output
delivers current only during ON time of the output switch
without overshoot. The maximum current is 2mA typical. The
typical value of external CSNS resistor connected to the
ground is 2.5kΩ.
VDD
.
Loss of VPWR
The current recopy is not active in Fail-safe Mode.
If the external VPWR supply is disconnected (or not within
specification), the SPI configuration, reporting, and daisy
chain features are provided for RST to set to logic [1] under
Temperature Prewarning Detection
In Normal mode, the 10XS3435 provides a temperature
prewarning reported via SPI in case of the temperature of the
GND flag is higher than TOTWAR. This diagnosis (OTW bit set
V
DD in nominal conditions. This fault condition can be
diagnosed with UV fault in SPI STATR_s registers. The SPI
pull-up and pull-down current sources are not operational.
The previous device configuration is maintained. No current
is conducted from VDD to VPWR.
to [1]) is latched in the SPI DIAGR0 register. To delatch, a
read SPI command is needed.
ACTIVE CLAMP ON VPWR
Loss of VPWR and VDD
If the external VPWR and VDD supplies are disconnected
(or not within specification: (VDD and VPWR) <
The device provides an active gate clamp circuit in order
to limit the maximum transient VPWR voltage at
VPWR(CLAMP). In case of overload on an output the
corresponding output is turned off which leads to high voltage
at VPWR with an inductive VPWR line. When VPWR voltage
exceeds VPWR(CLAMP) threshold, the turn-off on the
corresponding output is deactivated and all HS[0:3] outputs
are switched ON automatically to demagnetize the inductive
Battery line.
VSUPPLY(POR)), all SPI register contents are reset with default
values corresponding to all SPI bits are set to logic [0] and all
latched faults are also reset.
EMC PERFORMANCES
All following tests are performed on Freescale evaluation
board in accordance with the typical application schematic.
The device is protected in case of positive and negative
transients on the VPWR line (per ISO 7637-2).
REVERSE BATTERY ON VPWR
The output survives the application of reverse voltage as
low as -18 V. Under these conditions, the ON resistance of
the output is 2 times higher than typical ohmic value in
forward mode. No additional passive components are
required except on VDD current path.
The 10XS3435 successfully meets the Class 5 of the
CISPR25 emission standard and 200V/m or BCI 200mA
injection level for immunity tests.
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
remaining nine bits, D8:D0, are used to configure and control
SERIAL INPUT COMMUNICATION
the outputs and their protection features.
SPI communication is accomplished using 16-bit
messages. A message is transmitted by the MCU starting
with the MSB D15 and ending with the LSB, D0 (Table 9).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB,
D15, is the watchdog bit (WDIN). In some cases, output
selection is done with bits D14:D13. The next three bits,
D12:D10, are used to select the command register. The
Multiple messages can be transmitted in succession to
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
The 10XS3435 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 10 summarizes the SI registers.
Table 9. SI Message Bit Assignment
Bit Sig
SI Msg Bit
Message Bit Description
MSB
D15
D14:D13
D12:D10
D9
Watchdog in: toggled to satisfy watchdog requirements.
Register address bits used in some cases for output selection (Table 12).
Register address bits.
Not used (set to logic [0]).
LSB
D8:D0
Used to configure the inputs, outputs, and the device protection features and SO status content.
Table 10. Serial Input Address and Configuration Bit Map
SI Data
D5
SI Register
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D4
D3
D2
D1
D0
STATR_s WDIN
PWMR_s WDIN
CONFR0_s WDIN
CONFR1_s WDIN
X
X
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
ON_s
0
0
PWM6_s
0
0
SOA4
PWM4_s
SR1_s
SOA3
PWM3_s
SR0_s
SOA2
SOA1
SOA0
A
A
28W_s
PWM5_s
DIR_dis_s
Retry_dis_s
PWM2_s
DELAY2_s
PWM1_s
DELAY1_s
PWM0_s
DELAY0_s
1
1
1
0
0
0
A
A
A
A
0
0
0
Retry_
OS_dis_s
OLON_dis_s OLOFF_dis_s OLLED_en_s CSNS_ratio_s
unlimited_s
OCR_s
GCR
WDIN
WDIN
A
A
1
1
0
0
0
1
0
0
Xenon_s
BC1_s
BC0_s
OC1_s
OC0_s
OCHI_s
CSNS1
OLCO1_s
CSNS0
OLCO0_s
X
OC_mode_s
OV_dis
1
0
0
0
VDD_FAI PWM_en
L_en
CLOCK_sel
TEMP_en
CSNS_en
CALR
WDIN
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
Register
state after
RST=0 or
X
X
X
V
or
DD(FAIL)
V
SUPPLY(PO
condition
R)
x=Don’t care.
s=Output selection with the bits A1A0 as defined in Table 11.
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the PWMR_s, CONFR0_s,
CONFR1_s, OCR_s, GCR and CALR registers (Refer to the
section entitled Serial Output Communication (Device Status
Return Data) on page 37.
DEVICE REGISTER ADDRESSING
The following section describes the possible register
addresses (D[14:10]) and their impact on device operation.
ADDRESS XX000—STATUS REGISTER
(STATR_S)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
ADDRESS A A 001—OUTPUT PWM CONTROL
ADDRESS A A 011—OUTPUT CONFIGURATION
1 0
1
0
REGISTER (PWMR_S)
REGISTER (CONFR1_S)
The PWMR_s register allows the MCU to control the state
of corresponding output through the SPI. Each output “s” is
independently selected for configuration based on the state
The CONFR1_s register allows the MCU to configure
corresponding output fault management through the SPI.
Each output “s” is independently selected for configuration
based on the state of the D14:D13 bits (Table 11).
of the D14:D13 bits (Table 11).
A logic [1] on bit D6 (RETRY_unlimited_s) disables the
autoretry counter for the selected output, the default value [1]
corresponds to enable auto-retry feature without time
limitation.
Table 11. Output Selection
A1 (D14)
A0 (D13)
HS Selection
0
0
1
1
0
1
0
1
HS0 (default)
HS1
A logic [1] on bit D5 (RETRY_dis_s) disables the auto-retry
for the selected output, the default value [0] corresponds to
enable this feature.
HS2
HS3
A logic [1] on bit D4 (OS_dis_s) disables the output hard
shorted to VPWR protection for the selected output, the
default value [0] corresponds to enable this feature.
A logic [1] on bit D8 (28W_s) selects the 28W over-current
protection profile: the over-current thresholds are divided by
2 and, the inrush and cooling responses are dedicated to
28W lamps for HS[0,1] outputs. This bit it not taken into
account for HS[2,3] outputs.
A logic [1] on bit D3 (OLON_dis_s) disables the ON output
open-load detection for the selected output, the default value
[0] corresponds to enable this feature (Table 13).
A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF
output open-load detection for the selected output, the
default value [0] corresponds to enable this feature.
Bit D7 sets the output state. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF (if IN
input is also pulled down). Bits D6:D0 set the output PWM
duty-cycle to one of 128 levels for PWM_en is set to logic [1],
as shown Table 6, page 28.
A logic [1] on bit D1 (OLLED_en_s) enables the ON output
open-load detection for LEDs for the selected output, the
default value [0] corresponds to ON output open-load
detection is set for bulbs (Table 13).
ADDRESS A A 010—OUTPUT CONFIGURATION
1
0
REGISTER (CONFR0_S)
Table 13. ON Open-load Selection
The CONFR0_s register allows the MCU to configure
corresponding output switching through the SPI. Each output
“s” is independently selected for configuration based on the
state of the D14:D13 bits (Table 11).
OLON_dis_s (D3) OLLED_en_s (D1) ON OpenLoad detection
0
0
enable with bulb threshold
(default)
For the selected output, a logic [0] on bit D5 (DIR_DIS_s)
will enable the output for direct control. A logic [1] on bit D5
will disable the output from direct control (in this case, the
output is only controlled by On bit).
0
1
1
enable with LED threshold
disable
X
A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio
on the CSNS pin for the corresponding output. The default
value [0] is the low ratio (Table 14).
D4:D3 bits (SR1_s and SR0_s) are used to select the high
or medium or low speed slew rate for the selected output, the
default value [00] corresponds to the medium speed slew rate
(Table 12).
Table 14. Current Sense Ratio Selection
Table 12. Slew Rate Speed Selection
CSNS_high_s (D0)
Current Sense Ratio
SR1_s (D4)
SR0_s (D3)
Slew Rate Speed
0
1
CRS0 (default)
CRS1
0
0
1
1
0
1
0
1
medium (default)
low
ADDRESS A A 100—OUTPUT OVER-CURRENT
1
0
high
REGISTER (OCR)
Not used
The OCR_s register allows the MCU to configure
corresponding output over-current protection through the
SPI. Each output “s” is independently selected for
configuration based on the state of the D14:D13 bits (Table
11).
Incoming message bits D2:D0 reflect the desired output
that will be delayed of predefined PWM clock rising edges
number, as shown Table 7, page 28 (only available for
PWM_en bit is set to logic [1]).
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
A logic [1] on bit D8 (Xenon_s) disables enables the
Xenon 55W or 28W bulb over-current profile, as described
Figure 14.
Table 16. Inrush Curve Selection
OC1_s (D5)
OC0_s (D4)
Profile Curves Speed
slow (default)
fast
0
0
1
1
0
1
0
1
Xenon bit set to logic [0]:
medium
I
OCH1
very slow
I
OCH2
I
I
OC1
OC2
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is
replaced by OCHI2 during tOC1, as shown Figure 15.
I
OCLO4
OCLO3
OCLO2
OCLO1
I
I
I
Time
I
OCH1
t
t
t
t
t
t
OC7
OC1
OC3 OC4 OC5
OC2
OC6
t
I
OCH2
I
OC1
I
OC2
OC3
I
I
OC4
Xenon bit set to logic [1]:
I
I
OCL4
OCL3
I
I
OCL2
OCL1
I
I
OCH1
Time
t
t
t
t
t
t
OC7
OC1
OC3 OC4 OC5
OC6
OCH2
t
OC2
I
OC1
I
OC2
OC3
Figure 15. Over-current profile with OCHI bit set to ‘1’
I
I
OC4
The wire harness is protected by one of four possible
I
I
I
I
OCL4
current levels in steady state, as defined in Table 17.
OC
L3
OCL2
OCL1
Table 17. Output Steady State Selection
Time
t
t
t
t
t
t
OC7
OC1
t
OC3 OC4 OC5
OC6
OC2
OCLO1 (D2) OCLO0 (D1)
Steady State Current
Figure 14. Over-current profile depending on Xenon bit
0
0
1
1
0
1
0
1
OCLO2 (default)
OCLO3
D[7:6] bits allow to MCU to programmable bulb cooling
curve and D[5:4] bits inrush curve for selected output, as
shown Table 15 and Table 16.
OCLO4
OCLO1
Table 15. Cooling Curve Selection
Bit D0 (OC_mode_sel) allows to select the over-current
mode, as described Table 18.
BC1_s (D7)
BC0_s (D6)
Profile Curves Speed
0
0
1
1
0
1
0
1
medium (default)
slow
Table 18. Over-current Mode Selection
OC_mode_s (D0)
Over-current Mode
fast
0
1
only inrush current management (default)
medium
inrush current and bulb cooling
management
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
36
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
ADDRESS 00101—GLOBAL CONFIGURATION
REGISTER (GCR)
ADDRESS 00111—CALIBRATION REGISTER
(CALR)
The GCR register allows the MCU to configure the device
through the SPI.
The CALR register allows the MCU to calibrate internal
clock, as explained in Figure 13.
Bit D8 allows the MCU to enable or disable the VDD failure
detector. A logic [1] on VDD_FAIL_en bit allows switch of the
outputs HS[0:3] with PWMR register device in Fail-safe mode
in case of VDD < VDD(FAIL).
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN DATA)
When the CS pin is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB- (OD15-)
first as the new message data is clocked into the SI pin. The
first sixteen bits of data clocking out of the SO, and following
a CS transition, is dependent upon the previously written SPI
word.
Bit D7 allows the MCU to enable or disable the PWM
module. A logic [1] on PWM_en bit allows control of the
outputs HS[0:3] with PWMR register (the direct input states
are ignored).
Bit D6 (CLOCK_sel) allows to select the clock used as
reference by PWM module, as described in the following
Table 19.
Any bits clocked out of the Serial Output (SO) pin after the
first 16 bits will be representative of the initial message bits
clocked into the SI pin since the CS pin first transitioned to a
logic [0]. This feature is useful for daisy-chaining devices as
well as message verification.
Table 19. PWM Module Selection
PWM_en (D7) CLOCK_sel (D6)
PWM module
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the
data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
0
1
1
X
0
1
PWM module disabled
(default)
PWM module enabled with
external clock from IN0
PWM module enabled with
internal calibrated clock
SO data will represent information ranging from fault
status to register contents, user selected by writing to the
STATR bits OD4, OD3, OD2, OD1, and OD0. The value of
the previous bits SOA4 and SOA3 will determine which
output the SO information applies to for the registers which
are output specific; viz., Fault, PWMR, CONFR0, CONFR1
and OCR registers.
Bits D5:D4 allow the MCU to select one of two analog
feedback on CSNS output pin, as shown in Table 20.
Table 20. CSNS Reporting Selection
TEMP_en CSNS_en
CSNS reporting
Note that the SO data will continue to reflect the
(D5)
(D4)
information for each output (depending on the previous
SOA4, SOA3 state) that was selected during the most recent
STATR write until changed with an updated STATR write.
0
X
1
0
1
0
CSNS tri-stated (default)
current recopy of selected output (D3:2] bits)
temperature on GND flag
The output status register correctly reflects the status of
the STATR-selected register data at the time that the CS is
pulled to a logic [0] during SPI communication, and/or for the
period of time since the last valid SPI communication, with
the following exception:
Table 21. Output Current Recopy Selection
CSNS1 (D3) CSNS0 (D2)
CSNS reporting
•The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
•The VPWR voltage is below 4.0V, the status must be
ignored by the MCU.
0
0
1
1
0
1
0
1
HS0 (default)
HS1
HS2
HS3
SERIAL OUTPUT BIT ASSIGNMENT
The GCR register disables the over-voltage protection
(D0). When this bits is [0], the over-voltage is enabled (default
value).
The 16 bits of serial output data depend on the previous
serial input message, as explained in the following
paragraphs. Table 22, summarizes SO returned data for bits
OD15:OD0.
• Bit OD15 is the MSB; it reflects the state of the
Watchdog bit from the previously clocked-in message.
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
• Bits OD14:OD10 reflect the state of the bits
SOA4:SOA0 from the previously clocked in message.
• Bit OD9 is set to logic [1] in Normal mode (NM).
• The contents of bits OD8:OD0 depend on bits D4:D0
from the most recent STATR command SOA4:SOA0
as explained in the paragraphs following Table 22.
Table 22. Serial Output Bit Map Description
Previous STATR
SO Returned Data
SO SO SO SO SO OD
A4 A3 A2 A1 A0 15
OD
14
OD
13
OD
12
OD
11
OD
10
OD9 OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
OLOFF_
s
STATR_s
PWMR_s
A
A
A
A
A
A
0
0
0
0
0
1
0
1
0
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM POR
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM 28W_s
UV
OV
OLON_s
OS_s
OT_s
SC_s
OC_s
1
1
1
0
0
0
ON_s PWM6_s PWM5_s PWM4_s
PWM3_s
SR0_s
PWM2_s
PWM1_s
PWM0_s
DIR_dis_ SR1_s
DELAY2_s
DELAY1_s DELAY0_s
CONFR0
_s
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
X
X
X
X
X
s
Retry_ Retry_dis OS_dis_ OLON_dis_s
OLOFF_dis_s OLLED_en_ CSNS_ratio_
CONFR1
_s
A
A
A
0
1
1
_s
s
s
s
1
1
0
0
unlimited
_s
BC0_s
OC1_s OC0_s
OCHI_s
CSNS1
OCLO1_s
CSNS0
OCLO0_s OC_mode_s
Xenon
_s
OCR_s
GCR
A
1
1
0
0
0
1
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
BC1_s
VDD_F PWM_ CLOCK_ TEMP_e CSNS_e
X
OV_dis
0
0
AIL_en en
sel
n
n
X
IN2
X
CLOCK_fail
DIAGR0
DIAGR1
DIAGR2
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
X
X
X
X
X
X
X
0
X
X
X
CAL_fail
OTW
IN1
0
X
X
0
X
X
0
IN3
X
IN0
1
WD_en
1
0
Register
state
0
0
N/A N/A N/A N/A N/A
0
0
0
0
0
0
0
0
0
after
RST=0or
V
DD(FAIL)
or
V
SUPPLY(
POR)
conditio
n
s=Output selection with the bits A1A0 as defined in Table 11
• POR: power on reset detection.
PREVIOUS ADDRESS SOA4:SOA0=A A 000
1
0
(STATR_S)
The FS pin reports all faults. For latched faults, this pin is
reset by a new Switch OFF command (toggling fault_control
signal).
The returned data OD8 reports logic [1] in case of previous
Power ON Reset condition (VSUPPLY(POR)). This bit is only
reset by a read operation.
PREVIOUS ADDRESS SOA4:SOA0=A A 001
(PWMR_S)
1
0
Bits OD7:OD0 reflect the current state of the Fault register
(FLTR) corresponding to the output previously selected with
the bits SOA4:SOA3 = A1A0 (Table 22).
The returned data contains the programmed values in the
PWMR register for the output selected with A1A0.
• OC_s: over-current fault detection for a selected output,
• SC_s: severe short-circuit fault detection for a selected
output,
PREVIOUS ADDRESS SOA4:SOA0=A A 010
1
0
(CONFR0_S)
• OS_s: output shorted to VPWR fault detection for a
selected output,
• OLOFF_s: open-load in OFF state fault detection for a
selected output,
The returned data contains the programmed values in the
CONFR0 register for the output selected with A1A0.
• OLON_s: openload in ON state fault detection (depending
on current level threshold: bulb or LED) for a selected
output,
PREVIOUS ADDRESS SOA4:SOA0=A A 011
(CONFR1_S)
1
0
• OV: over-voltage fault detection,
• UV: under-voltage fault detection
The returned data contains the programmed values in the
CONFR1 register for the output selected with A1A0.
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
38
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
PREVIOUS ADDRESS SOA4:SOA0=A A 100
1
0
(OCR_S)
Table 23. Watchdog activation report
The returned data contains the programmed values in the
OCR register for the output selected with A1A0.
WD_en (OD0)
SPI Watchdog
0
1
disabled
enabled
PREVIOUS ADDRESS SOA4:SOA0=00101 (GCR)
The returned data contains the programmed values in the
GCR register.
PREVIOUS ADDRESS SOA4:SOA0=10111
(DIAGR2)
PREVIOUS ADDRESS SOA4:SOA0=00111
(DIAGR0)
The returned data is the product ID. Bits OD2:OD0 are set
to 011 for Protected Dual 10mΩ and 35mΩ high side
Switches.
The returned data OD2 reports logic [1] in case of PWM
clock on IN0 pin is out of specified frequency range.
DEFAULT DEVICE CONFIGURATION
The returned data OD1 reports logic [1] in case of
calibration failure.
The default device configuration is explained below:
• HS output is commanded by corresponding IN input or On
bit through SPI. The medium slew-rate is used,
• HS output is fully protected by the Xenon over-current
profile by default, the severe short-circuit protection, the
under-voltage and the over-temperature protection. The
auto-retry feature is enabled,
• Open-load in ON and OFF state and HS shorted to VPWR
detections are available,
• No current recopy and no analog temperature feedback
active,
The returned data OD0 reports logic [1] in case of over-
temperature prewarning (temperature of GND flag is above
TOTWAR).
PREVIOUS ADDRESS SOA4:SOA0=01111
(DIAGR1)
The returned data OD4: OD1 report in real time the state
of the direct input IN[3:0].
The OD0 indicates if the watchdog is enabled (set to logic
[1]) or not (set to logic [0]). OD4:OD1 report the output state
in case of Fail-safe state due to watchdog time-out as
explained in the following Table 23.
• Over-voltage protection is enabled,
• SO reporting fault status from HS0,
• VDD failure detection is disabled.
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
FUNCTIONAL DEVICE OPERATION
TYPICAL APPLICATION
TYPICAL APPLICATION
The following figure shows a typical automotive lighting
application (only one vehicle corner) using an external PWM
clock from the main MCU. A redundancy circuitry has been
implemented to substitute light control (from MCU to
watchdog) in case of a Fail-safe condition.
It is recommended to locate a 22nF decoupling capacitor
to the module connector.
VPWR
VDD
Voltage regulator
10µF
100nF
10µF
100nF
VPWR
VDD
VDD
VPWR
ignition
switch
VDD
VPWR
VDD
100nF
100nF
10k
10k
100nF
VDD
WAKE
HS0
HS1
HS2
22nF
I/O
I/O
FS
10k
LOAD 0
IN0
IN1
IN2
IN3
MCU
22nF
22nF
22nF
10XS3435
10k
LOAD 1
LOAD 2
LOAD 3
SCLK
10k
CS
SCLK
CS
RST
10k
I/O
10k
SO
SI
SI
SO
HS3
A/D
CSNS
FSI
10k
GND
22nF
2.5k
VPWR
Watchdog
direct light commands (pedal, comodo, ...)
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
40
PACKAGING
SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
The 10XS3435 is packaged in a surface mount power
package intended to be soldered directly on the printed circuit
board.
peak temperature during the soldering process should not
exceed 245 for 10 seconds maximum duration.
The AN2469 provides guidelines for Printed Circuit Board
design and assembly.
The 10XS3435 was qualified in accordance with JEDEC
standards J-STD-020C Sn-Pb reflow profile. The maximum
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARL10596D listed below.
PNA SUFFIX
24-PIN PQFN
NONLEADED PACKAGE
98ARL10596D
REV. D
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
PACKAGING
PACKAGE DIMENSIONS
PNA SUFFIX
24-PIN PQFN
NONLEADED PACKAGE
98ARL10596D
REV. D
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
42
PACKAGING
PACKAGE DIMENSIONS
PNA SUFFIX
24-PIN PQFN
NONLEADED PACKAGE
98ARL10596D
REV. D
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
PACKAGING
PACKAGE DIMENSIONS
PNA SUFFIX
24-PIN PQFN
NONLEADED PACKAGE
98ARL10596D
REV. D
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
44
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
ADDITIONAL DOCUMENTATION
10XS3435PNA
THERMAL ADDENDUM (REV 1.0)
Introduction
This thermal addendum is provided as a supplement to the 10XS3435
technical data sheet. The addendum provides thermal performance
information that may be critical in the design and development of system
applications. All electrical, application and packaging information is
provided in the data sheet.
24-PIN
PQFN
Package and Thermal Considerations
This 10XS3435 is a dual die package. There are two heat sources in the
package independently heating with P1 and P2. This results in two junction
temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn
.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the
reference temperature while only heat source 1 is heating with P1.
PNA SUFFIX (PB-FREE)
98ARL10596D
24-PIN PQFN (12 x 12)
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies
to RθJ21 and RθJ22, respectively.
Note For package dimensions, refer to
the 10XS3435 data sheet.
RθJA11 RθJA12
RθJA21 RθJA22
TJ1
TJ2
P1
P2
.
=
The stated values are solely for a thermal performance comparison of
one package to another in a standardized environment. This methodology is not meant to and will not predict the performance
of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to
the standards listed below.
Standards
Table 24. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
Resistance
(1)(2)
RθJAmn
RθJBmn
RθJAmn
RθJCmn
27.13
14.31
47.77
1.38
18.31
6.54
35.53
23.61
54.35
0.91
(2)(3)
(1)(4)
(5)
0.2mm
36.90
0.00
Notes:
0.2mm
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
0.5mm dia.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
Figure 16. Detail of Copper Traces Under Device with
Thermal Vias
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
76.2mm
76.2mm
Figure 18. 2s2p JDEC Thermal Test Board
(Red - Top Layer, Yellow - Two Buried Layers)
Figure 17. 1s JEDEC Thermal Test Board Layout
Transparent Top View
13 12 11 10
9
8
7
6
5
4
3
2
1
SO
16
17
24
FSI
GND
23
GND
14
GND
HS3
18
22
HS2
15
VPWR
MC10XS3435 Pin Connections
24-PIN PQFN (12 x 12)
0.9 mm Pitch
12.0mm 12.0mm Body
19
20
21
HS0
HS1
NC
Figure 19. Pin Connections
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
46
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
Device on Thermal Test Board
Table 25. Thermal Resistance Performance
Material:
Single layer printed circuit board
1 = Power Chip, 2 = Logic Chip (°C/W)
FR4, 1.6 mm thickness
Area A
(mm2)
Thermal
Resistance
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
Cu traces, 0.07 mm thickness
Cu buried traces thickness 0.035mm
0
47.77
42.90
40.95
39.85
38.96
36.90
33.21
31.78
30.89
30.21
54.35
51.07
49.63
48.61
47.90
Outline:
76.2mm x 114.3mm board area,
including edge connector for thermal
testing, 74mm x 74mm buried layers
area
150
300
450
600
RθJAmn
Area A:
Cu heat-spreading areas on board
surface
RθJA is the thermal resistance between die junction and
ambient air.
Ambient Conditions: Natural convection, still air
This device is a dual die package. Index m indicates the
die that is heated. Index n refers to the number of the die
where the junction temperature is sensed.
65.00
60.00
55.00
50.00
45.00
40.00
35.00
30.00
25.00
0
100
200
300
400
500
600
Heat spreading area [sqmm]
RJA11
RJA12=RJA21
RJA22
Figure 20. Steady State Thermal Resistance in Dependence on Heat Spreading Area;
1s JEDEC Thermal Test Board with Spreading Areas
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
100
10
1
0.1
0.00001
0.001
0.1
Time[s]
10
1000
Figure 21. Transient Thermal 1W Step Response; Device on
1s JEDEC Standard Thermal Test Board with Heat Spreading Areas 600 Sq. mm
100
10
1
0.1
0.00001
0.001
0.1
Time [s]
10
1000
Figure 22. Transient Thermal 1W Step Response;
Device on 2s2p JEDEC Standard Thermal Test Board
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
48
REVISION HISTORY
REVISION HISTORY
REVISION
4.0
DATE
DESCRIPTION OF CHANGES
9/2008
10/2008
•
Initial release
•
•
Revised wording of VPWR Supply Voltage Range in Maximum Rating Table on page 5.
Changed parameters for VPWR and VDD Power on Reset Threshold in Static Electrical
Characteristics Table on page 7.
5.0
•
•
•
•
•
Changed Maximum rating for Output Source-to-Drain ON Resistance in Static Electrical
Characteristics Table on page 8.
Changed Typical rating for HS[0,1] Current Sense Ratio (6.0 V < HS[0:3] < 20V, CSNS < 5.0V) in
Static Electrical Characteristics Table on page 9.
Further defined Output Over-Temperature Shutdown parameter in Static Electrical Characteristics
Table on page 10.
Changed Typical parameter for HS[2,3] Current Sense Ratio (6.0V < HS[0:3] < 20V, CSNS < 5.0V)
in Static Electrical Characteristics Table on page 11.
Changed parameters for Wake Input Clamp Voltage in Static Electrical Characteristics Table on
page 12.
•
•
Added explanation for recovering to Normal Mode on page 28.
Added HS[2:3] Driver Output Matching Time (tDLY(ON) - tDLY(OFF)
)
10XS3435
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
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10XS3435
Rev. 5.0
10/2008
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