PPC5602CEVLQ [FREESCALE]
Microcontroller; 微控制器
| 型号： | PPC5602CEVLQ |
| 厂家： | 
Freescale |
| 描述： | Microcontroller |
| 文件： | 总98页 (文件大小：894K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5606S
Rev. 1, 10/2008
MPC5606S
LQFP–144
20 mm x 20 mm
LQFP–176
24 mm x 24 mm
MPC560xS Microcontroller
Data Sheet
32-bit MCU for cluster applications with stepper motor, TFT
graphic controller and LCD driver
The MPC5606S family of devices is designed to enable the development of automotive instrument cluster applications by
providing a single-chip solution capable of hosting real-time applications and driving a TFT display directly using an on-chip
color TFT display controller.
MPC5606S devices incorporate a cost-efficient host processor core compliant with the Power Architecture™ embedded
category. The processor is 100% user-mode compatible with the original PowerPC user instruction set architecture (UISA) and
TM
capitalizes on the available development infrastructure of current Power Architecture devices with full support from
available software drivers, operating systems and configuration code to assist with users' implementations.
Offering high performance processing at speeds up to 64 MHz, the MPC5606S family is optimized for low power consumption
and supports a range of on-chip SRAM and internal flash memories. The 1 MB flash version (MPC5606S) features 160 KB of
on-chip graphics SRAM.
Refer to Table 1 for specific memory and feature sets of the product family members.
This document describes the features of the MPC5606S family of microcontrollers and highlights important electrical and
physical characteristics of the devices. For functional characteristics, refer to the MPC5606S Microcontroller Reference
Manual.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
2
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3.6.2 I/O Input DC Characteristics . . . . . . . . . . . . . . 50
3.6.3 I/O Output DC Characteristics . . . . . . . . . . . . . 51
3.6.4 I/O Pad Current Specification. . . . . . . . . . . . . . 55
3.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . 57
3.8 Main Oscillator Electrical Characteristics . . . . . . . . . . 59
3.9 Low Power Oscillator Electrical Characteristics. . . . . . 61
3.10 FMPLL Electrical Characteristics. . . . . . . . . . . . . . . . . 62
3.11 Main RC Oscillator Electrical Characteristics . . . . . . . 63
3.12 Low Power RC Oscillator Electrical Characteristics . . 64
3.13 Flash Memory Electrical Characteristics . . . . . . . . . . . 64
3.14 Analog to Digital Converter (ADC) Electrical Characteristics
65
3.14.1 Input Impedance and ADC Accuracy . . . . . . . . 66
3.14.2 ADC Electrical Characteristics . . . . . . . . . . . . . 70
3.15 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.15.1 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 72
3.16 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.16.1 IEEE 1149.1 Interface Timing . . . . . . . . . . . . . 74
3.16.2 Nexus Debug Interface. . . . . . . . . . . . . . . . . . . 77
3.16.3 Interface to TFT LCD Panels . . . . . . . . . . . . . . 78
3.16.4 External Interrupt (IRQ) and Non-Maskable
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 MPC5606S Features. . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 MPC5606S Series Blocks. . . . . . . . . . . . . . . . . . . . . . . .6
1.3.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3.2 Block Summary . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pinout and Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . .9
2.1 144 LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . .10
2.2 176 LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . .11
2.3 208 MAPBGA Package Pinout . . . . . . . . . . . . . . . . . . .11
2.4 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.4.1 Pad Configuration during Reset Phases . . . . . .13
2.4.2 Voltage Supply Pins. . . . . . . . . . . . . . . . . . . . . .13
2.4.3 Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.4.4 System Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.4.5 Nexus Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.4.6 Functional Ports A, B, C, D, E, F, G, H, I, J, K . .18
2.4.7 Signal Details. . . . . . . . . . . . . . . . . . . . . . . . . . .36
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .39
3.1.1 Recommended Operating Conditions . . . . . . . .41
3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .44
3.2.1 General Notes for Specifications at Maximum
3
Interrupt (NMI) Timing . . . . . . . . . . . . . . . . . . . 81
3.16.5 Enhanced Modular I/O Subsystem (eMIOS) Timing
82
Junction Temperature . . . . . . . . . . . . . . . . . . . .45
3.3 EMI (Electromagnetic Interference) Characteristics . . .47
3.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.4.1 Voltage Regulator Electrical Characteristics . . .47
3.4.2 Voltage monitor electrical characteristics. . . . . .48
3.4.3 Low voltage domain power consumption. . . . . .49
3.5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .50
3.6 I/O Pad Electrical Characteristics . . . . . . . . . . . . . . . . .50
3.6.1 I/O Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.16.6 FlexCAN Timing . . . . . . . . . . . . . . . . . . . . . . . . 82
3.16.7 Deserial Serial Peripheral Interface (DSPI) . . . 83
3.16.8 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.16.9 Mechanical Outline Drawings. . . . . . . . . . . . . . 89
3.17 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.18 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
2
Freescale Semiconductor
Overview
1
Overview
The following sections provide high-level descriptions of the features found on the MPC5606S.
1.1
Device Comparison
..
Table 1. MPC5606S Family
Feature
MPC5602S
MPC5604S
MPC5606S
CPU
e200z0h
Static - 64 MHz
512 KB
Execution Speed
Flash (ECC)
256 KB
1 MB
EEPROMEmulationBlock
(ECC)
4 × 16 KB
RAM (ECC)
24 KB
No
48 KB
No
48 KB
Graphics RAM
160 KB
MPU
12 entry
16 channels
No
eDMA
Display Control Unit
Parallel Data Interface
Stepper Motor Controller
Stepper Motor Stall Detect
Sound Generation
LCD Segment Driver
No
No
Yes
Yes
No
6 motors
Yes
Yes
Yes
Using eMIOS
64 × 6
64 × 6
Yes
40 × 4, 38 × 61
32 kHz External Crystal
Oscillator
Real Time Counter and
Autonomous Periodic
Interrupt
Yes
Yes
Yes
Periodic Interrupt Timer
System Watchdog Timer
System Timer Module
Timed I/O2
4 ch, 32-bit
Yes
4 ch, 32-bit
8 ch, 16-bit IC/OC
16 ch, 16-bit OPWM/IC/OC
16 channels, 10-bit
2 × FlexCAN
Yes
ADC3
CAN (64 Mailboxes)
1 × FlexCAN
2 × FlexCAN
CAN Sampler
SCI
SPI
2 × LINFlex
2 × DSPI
2 × DSPI
No
34 × DSPI
Yes
QuadSPI Serial Flash
Interface
No
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
3
Overview
Table 1. MPC5606S Family (continued)
Feature
MPC5602S
MPC5604S
MPC5606S
I2C
2
2
4
GPIO
Debug
Package
105
105
105 / 132
Nexus 2+5
Nexus 1
144 LQFP
Nexus 1
144 LQFP
144 LQFP6
176 LQFP
208 MAPBGA7
1
2
3
4
5
6
7
Configuration is software-programmable
IC-Input Capture, OC-Output Compare, OPWM-Output Pulse Width Modulation
Support for external multiplexer enabling up to 23 channels
QuadSPI serial Flash controller can be optionally used as a third DSPI
Nexus2+ available on 176 LQFP as alternate pin function and on 208 MAPBGA
Not all features are available simultaneously in 144 LQFP package option
The 208-pin package is not a production package; it is available in limited quantities for tool
development only.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
1.2
MPC5606S Features
Single issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z0h)
•
— Compatible with classic PowerPC instruction set
— Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of
mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over
conventional Book E compliant code
•
On-chip ECC flash memory with flash controller
— Up to 1 MB primary flash—two 512 KB modules with prefetch buffer and 128-bit data access port
— 64 KB data flash—separate 4×16 KB flash block for EEPROM Emulation with prefetch buffer and 128-bit data
access port
•
•
•
Up to 48 KB on-chip ECC SRAM with SRAM controller
Up to 160 KB on-chip non-ECC graphics SRAM with SRAM controller
Memory protection unit (MPU) with up to 12 region descriptors and 32-byte region granularity to provide basic
memory access permission
•
•
Interrupt controller (INTC) with up to 127 peripheral interrupt sources and eight software interrupts
Two frequency-modulated phase-locked loops (FMPLLs)
— Primary FMPLL provides a 64 MHz system clock
— Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS
modules and as alternate clock to the DCU for pixel clock generation
•
•
•
•
Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus
masters (AMBA 2.0 v6 AHB)
16-channel enhanced direct memory access controller (eDMA) with multiple transfer request sources using a DMA
channel multiplexer
Boot assist module (BAM) for embedded boot code supports boot options including download of code via a serial link
(CAN or SPI)
Display control unit to drive TFT LCD displays. It includes processing of up to four planes that can be blended together
and offers a direct un-buffered hardware bit-blitter of up to 16 software-configurable dynamic layers in order to
drastically minimize graphic memory requirements and provide fast animations. Programmable display resolutions are
available up to WVGA.
•
•
Parallel Data Interface for digital video input
The LCD segment driver module has two software programmable configurations:
— Up to 40 front plane drivers and 4 backplane drivers
— Up to 38 frontplane drivers and 6 backplane drivers
•
Stepper Motor Controller module with high-current drivers for up to six instrument cluster gauges driven in full dual
H-Bridge configuration including full diagnostics for short circuit detection
•
•
•
•
Stepper motor return-to-zero and stall detection module
Sound generation and playback utilizing PWM channels and eDMA; supports monotonic and polyphonic sound
24 eMIOs channels providing up to 16 PWM and 24 input capture / output compare channels
10-bit analog-to-digital converter (ADC) with a maximum conversion time of 1μs
— 16 internal channels
— Extendable to eight multiplexed external channels
•
•
•
Up to three DSPI (Deserial Serial Peripheral Interface) modules for full-duplex, synchronous, communications with
external devices
QuadSPI serial flash memory controller supporting single, dual and quad modes of operation to interface to external
serial flash memory or optionally can be configured to function as another DSPI module (MPC5606S only)
Two Local Interconnect Network (LIN) controller modules capable of autonomous message handling (master),
autonomous header handling (slave mode), and UART support. Compliant with LIN protocol rev 2.1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
Overview
•
•
•
•
Two full CAN 2.0B controllers with 64 configurable buffers each; the bit rate can be programmed up to 1 Mb/s
2
Up to four Inter-integrated circuit (I C) internal bus controllers with master/slave bus interface
Up to 132 configurable general purpose pins supporting input and output operations
Real Time Counter (RTC). Clock sources are:
— Internal 128 kHz or 16 MHz RC oscillator supporting autonomous wake-up with 1 ms resolution with maximum
timeout of 2 seconds
— External 32 kHz crystal oscillator, supporting wake-up with 1 s resolution and maximum timeout of one hour
— External 4 - 16 MHz oscillator
•
System Timers:
— 4-channel 32-bit System Timer Module (STM)—included in processor platform
— 4-channel 32-bit Periodic Interrupt Timer (PIT) module
— System watchdog timer
•
•
System Integration Unit (SIU) module to manage resets, external interrupts, GPIO and pad control
System Status and Configuration Module (SSCM) to provide information for identification of the device, last boot
mode, or debug status and provides an entry point for the censorship password mechanism
•
•
•
Clock Generation Module (CGM) to generate system clock sources and provide a unified register interface, enabling
access to all clock sources
Clock Monitor Unit (CMU) to monitor the integrity of the main crystal oscillator and the PLL and act as a frequency
meter, measuring the frequency of one clock source and comparing it to a reference clock
Mode Entry Module (MEM) to control the device power mode, i.e., RUN, HALT, STOP, or STANDBY, control mode
transition sequences, and manage the power control, voltage regulator, clock generation and clock management
modules
•
•
•
•
Reset Generation Module (RGM) to manage reset assertion and release to the device at initial power-up
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard
Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator controller for regulating the 3.3 or 5 V supply voltage down to 1.2 V for core logic (requires
external ballast transistor)
1
•
The MPC5606S microcontrollers are offered in the following packages:
— 144 LQFP, 0.5 mm pitch, 20 mm × 20 mm outline
— 176 LQFP, 0.5 mm pitch, 24 mm × 24 mm outline
— 208 MAPBGA, 1.0 mm pitch, 17 mm × 17 mm outline
1.3
MPC5606S Series Blocks
Block Diagram
1.3.1
Figure 1 shows a top-level block diagram of the MPC5606S series.
1. See the device comparison table or orderable parts summary for package offerings for each device in the family.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
NMI
Nexus Port JTAG Port
Video
SRAM
SRAM
SRAM
FLASH
FLASH
Test Controller
JTAG
Nexus
Port
Controller
SRAM
Controller Controller Controller
IRC
16 MHz
NMI
Instructions
SIU
e200z0h
Data
IRC
128 kHz
Nexus 2+
XTAL/
EXTAL
Voltage
Regulator
XOSC
4-16 MHz
Data
and
XTAL32/
EXTAL32
DMA
Clock
QuadSPI
XOSC
External
Interrupts from
Peripheral
Blocks
Interrupt
Controller
(INTC)
32 kHz
RGB TFT
Output
DCU
2 ×
FMPLL
Parallel
Data
Power
Control
Unit
Clock
Generation
Module
Interface
speaker/
buzzer
STM
4×PIT
SSCM
(PDI)
Sound
Generation
Mode
Entry
Module
Reset
40 × 4
LCD
Generation
Module
RTC/
API
SWT
BAM
LCD FP
and
BP signals
Peripheral Bridge
Six Gauge
Drivers
with
SIU
Reset Control
16 ch.
10-bit
ADC
2 x
2 ×
FlexCAN
2 ×
LINFlex
2 ×
2
eMIOS
4 × I C
DSPI
External
Stepper
16 + 8 ch.
Interrupts
External
Interrupt
Request
Stall Detect
(SSD)
IMUX
GPIO &
Pad Control
. . .
. . .
. . .
. . .
. . .
. . .
I/O
Figure 1. MPC5606S Series Block Diagram
1.3.2
Block Summary
Table 2 summarizes the functions of all blocks present in the MPC5606S series microcontrollers. Please note that the presence
and number of blocks varies by device and package.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
Overview
Table 2. MPC5606S Series Block Summary
Block
Function
16-channel 2nd-generation Direct Memory
Access (eDMA)
Second-generation platform module capable of performing complex
data transfers with minimal intervention from a host processor via “n”
programmable channels
AHB crossbar switch “lite” (XBAR-Lite)
Analog-to-digital converter (ADC)
Boot assist module (BAM)
Internal busmaster
16-channel, 10-bit analog to digital converter
A block of read-only memory containing VLE code which is executed
according to the boot mode of the device
Clock generation module (CGM)
Provides logic and control required for the generation of system and
peripheral clocks
Clock monitor unit (CMU)
Display control unit (DCU)
Monitors clock source (internal and external) integrity
Generates all signals required to drive a TFT LCD display, allowing
blending of data of up to 16 layers; can also display digital
video/graphics in the background plane
Deserial serial peripheral interface (DSPI)
QuadSPI (QSPI)
Provides a synchronous serial interface for communication with
external devices
Provides a synchronous serial bus for communication with external
serial flash memory and is optionally configurable as a third DSPI
module
Enhanced modular input output system
(eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and
variables
FlexCAN (controller area network)
Supports the standard CAN communications protocol
FMPLL (frequency-modulated phase-locked Two FMPLLs generate high-speed system clocks and support
loop)
programmable frequency modulation
Inter-integrated circuit (I2C™) bus
A two wire bidirectional serial bus that provides a simple and efficient
method of data exchange between devices
Interrupt controller (INTC)
JTAG controller
Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode
LCD driver module
Provides 40 × 4 (frontplane drivers × backplane drivers) or 6 × 38
driver configuration for driving LCD segments
LINflex controller
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Memory protection unit (MPU)
Error Correction Status Module (ECSM)
Provides hardware access control for all memory references
generated in a device
Provides miscellaneous control functions including program-visible
information about the platform configuration and revision levels, a
reset status register, wakeup control for exiting sleep modes, and
generic access error information for the processor core
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
8
Freescale Semiconductor
Pinout and Signal Descriptions
Table 2. MPC5606S Series Block Summary (continued)
Block
Function
Mode entry module (MEM)
Provides a mechanism for controlling the device operational mode
and mode transition sequences in all functional states; also manages
the power control unit, reset generation module and clock generation
module, and holds the configuration, control and status registers
accessible for applications
Nexus development interface (NDI) level
Provides real-time development support capabilities in compliance
with the IEEE-ISTO 5001-2003 standard
Peripheral interrupt timer (PIT)
Power control unit (PCU)
Produces periodic interrupts and triggers
Reduces the overall power consumption by disconnecting parts of the
device from the power supply via a power switching device; device
components are grouped into sections called “power domains” which
are controlled by the PCU
Static random-access memory (SRAM)
Reset generation module (RGM)
Provides storage for program code, constants, and variables
Centralizes reset sources and manages the device reset sequence of
the device
Real time counter (RTC)
A free running counter used for time keeping applications, the RTC
can be configured to generate an interrupt at a pre-defined interval
independent of the mode of operation (run mode or low-power mode)
Sound generation logic (SGL)
Stepper motor controller (SMC)
Provides monotonic and polyphonic sound generation capability
A PWM motor controller suitable for driving instruments in a cluster
configuration or any other loads requiring a PWM signal
Stepper stall detect (SDD)
The SSD module connects to one stepper (SM) motor with 2 coils and
is used to monitor the movement of the SM to detect that the attached
gauge pointer has reached the stall position of the scale
System integration unit (SIU)
Provides control over all the electrical pad controls and up 32 ports
with 16 bits of bidirectional, general-purpose input and output signals
and supports up to 32 external interrupts with trigger event
configuration
System status configuration module (SSCM) Provides system configuration and status data, e.g., memory size and
status, device mode and security status, DMA status, etc., device
identification data, debug status port enable and selection, and bus
and peripheral abort enable/disable
System timer (STM)
Provides a set of output compare events to support AutoSAR and
operating system tasks
System watchdog timer (SWT)
Test control unit (TCU)
Provides protection from runaway code
An extension of the JTAG controller module, the TCU provides the
means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
2
Pinout and Signal Descriptions
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
Pinout and Signal Descriptions
2.1
144 LQFP Package Pinout
Figure 2 shows the pinout for the 144-pin LQFP package.
WARNING
Any pins labeled “NC” must not be connected to any external circuit.
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
1
2
3
4
5
6
7
8
FP13/eMIOSB20/DCU_G2/PA10
FP12/eMIOSA13/DCU_G3/PA11
FP11/eMIOSA12/DCU_G4/PA12
FP10/eMIOSA11/DCU_G5/PA13
FP9/eMIOSA10/DCU_G6/PA14
FP8/eMIOSA9/DCU_G7/PA15
VDDE_A
PB11/CNTX_B/PDI3/eMIOSA16
PB10/CNRX_B/PDI2/eMIOSA23
PB0/CNTX_A/PDI1
PB1/CNRX_A/PDI0
VSS12
VDD12
PE7/M5C1P/SSD5_3/eMIOSA8
PE6/M5C1M/SSD5_2/eMIOSA9
PE5/M5C0P/SSD5_1/eMIOSA10
PE4/M5C0M/SSD5_0/eMIOSA11
VSSMC
VSSE_A
9
FP7/SOUND/SCL_D/DCU_B0/PG0
FP6/SDA_D/DCU_B1/PG1
FP5/eMIOSB19/DCU_B2/PG2
FP4/eMIOSB21/DCU_B3/PG3
FP3/eMIOSB17/DCU_B4/PG4
FP2/eMIOSA8/DCU_B5/PG5
FP1/DCU_B6/PG6
FP0/DCU_B7/PG7
BP0/DCU_VSYNC/PG8
BP1/DCU_HSYNC/PG9
BP2/DCU_DE/PG10
BP3/DCU_PCLK/PG11
VLCD/PH5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VDDMC
PE3/M4C1P/SSD4_3/eMIOSA12
PE2/M4C1M/SSD4_2/eMIOSA13
PE1/M4C0P/SSD4_1/eMIOSA14
PE0/M4C0M/SSD4_0/eMIOSA15
PD15/M3C1P/SSD3_3
PD14/M3C1M/SSD3_2
PD13/M3C0P/SSD3_1
PD12/M3C0M/SSD3_0
VSSMB
144-Pin
LQFP
VDDR
VSSR
RESET
VRC_CTRL
VPP
XTAL
VSSOSC
EXTAL
VSSPLL
VDDPLL
NC
TDI/PH1
TDO/PH2
TMS/PH3
TCK/PH0
VDDMB
PD11/M2C1P/SSD2_3
PD10/M2C1M/SSD2_2
PD9/M2C0P/SSD2_1
PD8/M2C0M/SSD2_0
PD7/M1C1P/SSD1_3/eMIOSB16
PD6/M1C1M/SSD1_2/eMIOSB17
PD5/M1C0P/SSD1_1/eMIOSB18
PD4/M1C0M/SSD1_0/eMIOSB19
VSSMA
VDDMA
PD3/M0C1P/SSD0_3/eMIOSB20
PD2/M0C1M/SSD0_2/eMIOSB21
PD1/M0C0P/SSD0_1/eMIOSB22
PD0/M0C0M/SSD0_0/eMIOSB23
74
73
Figure 2. 144-pin LQFPPinout
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
10
Freescale Semiconductor
Pinout and Signal Descriptions
2.2
176 LQFP Package Pinout
Figure 3 shows the pinout for the 176-pin LQFP package.
WARNING
Any pins labeled “NC” must not be connected to any external circuit.
FP13/eMIOSB20/DCU_G2/PA10
PB11/CNTX_B/PDI3/eMIOSA16
PB10/CNRX_B/PDI2/eMIOSA23
PB0/CNTX_A/PDI1
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
FP12/eMIOSA13/DCU_G3/PA11
FP11/eMIOSA12/DCU_G4/PA12
FP10/eMIOSA11/DCU_G5/PA13
FP9/eMIOSA10/DCU_G6/PA14
FP8/eMIOSA9/DCU_G7/PA15
VDDE_A
2
3
PB1/CNRX_A/PDI0
4
PJ11/PDI7
5
PJ10/PDI6
6
PJ9/PDI5
7
VSSE_A
PJ8/PDI4
8
FP7/SOUND/SCL_D/DCU_B0/PG0
FP6/SDA_D/DCU_B1/PG1
FP5/eMIOSB19/DCU_B2/PG2
FP4/eMIOSB21/DCU_B3/PG3
FP3/eMIOSB17/DCU_B4/PG4
FP2/eMIOSA8/DCU_B5/PG5
FP1/DCU_B6/PG6
FP0/DCU_B7/PG7
BP0/DCU_VSYNC/PG8
BP1/DCU_HSYNC/PG9
BP2/DCU_DE/PG10
BP3/DCU_PCLK/PG11
VLCD/PH5
VSS12
9
VDD12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PJ3/PDI_PCLK
PJ2/PDI_VSYNC
PJ1/PDI_HSYNC
PJ0/PDI_DE
PE7/M5C1P/SSD5_3/eMIOSA8
PE6/M5C1M/SSD5_2/eMIOSA9
PE5/M5C0P/SSD5_1/eMIOSA10
PE4/M5C0M/SSD5_0/eMIOSA11
VSSMC
VDDMC
PE3/M4C1P/SSD4_3/eMIOSA12
PE2/M4C1M/SSD4_2/eMIOSA13
PE1/M4C0P/SSD4_1/eMIOSA14
PE0/M4C0M/SSD4_0/eMIOSA15
PD15/M3C1P/SSD3_3
PD14/M3C1M/SSD3_2
PD13/M3C0P/SSD3_1
PD12/M3C0M/SSD3_0
VSSMB
176-Pin
LQFP
VDDR
VSSR
RESET
VRC_CTRL
VPP
XTAL
VSSOSC
EXTAL
VSSPLL
VDDMB
VDDPLL
PD11/M2C1P/SSD2_3
PD10/M2C1M/SSD2_2
PD9/M2C0P/SSD2_1
PD8/M2C0M/SSD2_0
PD7/M1C1P/SSD1_3/eMIOSB16
PD6/M1C1M/SSD1_2/eMIOSB17
PD5/M1C0P/SSD1_1/eMIOSB18
PD4/M1C0M/SSD1_0/eMIOSB19
VSSMA
NC
PDI10/MCKO/PK2
PDI11/MSEO/PK3
PDI12/EVTO/PK4
TDI/PH1
98
97
PDI13/EVTI/PK5
PDI14/MDO0/PK6
TDO/PH2
PDI15/MDO1/PK7
TMS/PH3
PDI16/MDO2/PK8
TCK/PH0
PDI17/MDO3/PK9
96
95
94
VDDMA
93
PD3/M0C1P/SSD0_3/eMIOSB20
PD2/M0C1M/SSD0_2/eMIOSB21
PD1/M0C0P/SSD0_1/eMIOSB22
PD0/M0C0M/SSD0_0/eMIOSB23
92
91
90
89
Figure 3. 176-pin LQFP Pinout
2.3
208 MAPBGA Package Pinout
Figure 4 shows the pinout for the 208-pin BGA package.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
11
WARNING
Any pins labeled “NC” must not be connected to any external circuit.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PA0
PJ0
PJ1
PJ3
PJ5
PJ7
PJ14
PF0
PF5
PK9
PK5
NC
NC
PF10
PF11
PF12
A
B
PA1
PA2
VDDE_A
PA3
PJ2
PJ4
PJ9
PJ6
PJ8
PJ15
PK0
PF1
PF3
PF6
PF7
NC
PK6
PK7
PK2
PK3
NC
NC
NC
VDDE_E
NC
PF13
PF14
VDDE_A
PJ10
PJ12
NC
VDDE_
E
C
PA4
PA6
PA5
PA7
PG0
PG1
PG3
PG5
PA15
VDD12
PG2
PJ11
PJ13
PK1
PF4
VDD12
PG12
PK8
PK4
VDD12
NC
NC
NC
NC
PF15
NC
D
E
F
G
H
J
NC
PA8
PA9
PG4
NC
NC
NC
NC
PA10
PA11
PG6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
PE7
PE6
PE2
PD13
PD12
PE1
NC
PA12
PA13
PG7
PE5
PE4
PE3
PD15
VDDMC
PE0
VSSMC
PD8
RESET
EXTAL
VSSPLL
PA14
PG8
PG9
NMI/PF2
PG10
PG11
MDO3
VDDE_A
VDDPLL
PD9
VDDMB
PD7
K
VSSM
B
L
XTAL
VPP
PH3
VREG
BYPASS
PD14
PD11
PD5
PD6
M
N
P
VDDR
VLCD
PH2
VDD12
PK11
PK10
PB8
PB7
PB5
PB4
PC13
PC12
PC9
PC8
PC6
PC5
PB11
PC3
VDDMA
PB10
PD10
NC
PD4
PD2
PD3
PD1
VRC_
CTRL
PH1
VDDE_B
MDO2 MDO1
PB13
PH0
VDDE_B
EVTO
EVTI
PF9
PF8
PH4
PB12
PB9
PB6
PC15
PC14
PC11
PC10
PC7
PC4
PC2
PC1
PB3
PC0
PB2
PB1
VDDE_B
PB0
PD0
R
T
MCKO MSEO
MDO0
VDDE_C
VSSA
VDDA
VSSMA
Figure 4. 208-pin MAPBGA Pinout
2.4
Signal Description
Pinout and Signal Descriptions
The following sections provide signal descriptions and related information about the functionality and configuration.
2.4.1
Pad Configuration during Reset Phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are floating with the following exceptions:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Analog input pins AN[0:9] are pull-up
EVTI (208-pin package only) is pull-up.
PB[6] (FAB) is pull-up. Without external strong pull-up the device starts fetching from flash
RESET pad is driven low. This is released only after PHASE2 reset completion.
Main oscillator pads (EXTAL, XTAL) are tristate.
PA[0] DCU_R0 is pull-up
PB[1] CNRX_A is pull-up
PB[10] CNRX_B is pull-up
PB[12] RXD_B is pull-up
PB[3] RXD_A is pull-up
PB[4] SCK_B is pull-up
PF[0] eMIOSA13 is pull-up
PF[11] eMIOSB23 is pull-up
PF[13] SIN_C is pull-up
PF[2] NMI is pull-up
PF[3] eMIOSA11 is pull-up
PF[5] eMIOSA9 is pull-up
PF[6] SDA_A is pull-up
PF[8] SDA_B is pull-up
PH[0] TCK is pull-up
PH[1] TDI is pull-up
PH[3] TMS is pull-up
PJ[4] PDI0 is pull-up
PJ[6] PDI2 is pull-up
PK[9] MDO3 is pull-up
2.4.2
Voltage Supply Pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
Pinout and Signal Descriptions
Table 3. Voltage Supply Pin Descriptions
Pin Number
176 LQFP
42, 51, 103, 118, 50, 67, 123, 148, D4, D9, D13, N4
Supply pin
Function
144 LQFP
208 MAPBGA
1
VDD12
VSS12
VSS
1.2 V core supply (1.08 V - 1.32 V)
Low voltage ground for core domain
Low voltage ground
133 163
43, 52, 104, 119, 51, 68, 124, 149,
—
134
164
—
—
G7, G8, G9, G10,
H7, H8, H9, H10,
J7, J8, J9, J10,
K7, K8, K9, K10
VDDA
VSSA
3.3 V/5 V reference voltage and analog
supply for A/D converter
53
54
69
70
T11
Reference ground and analog ground for
A/D converter
T10
VDDR
VSSR
Voltage regulator VREG supply
Voltage regulator ground
22
23
22
23
N1
—
VDDE_A
3.3 V/5 V I/O supply. This supply is
shared with internal flash and 16 MHz
IRC oscillator.
7, 124
7, 154, 170
B2, C3, K2
VSSE_A
VDDE_B
3.3 V/5 V I/O supply ground
8, 125
38
8, 155, 171
46, 64
—
3.3 V/5 V I/O supply. 4-16 MHz crystal
oscillator shares this supply.
P3, R2, R15
VSSE_B
VDDE_C
3.3 V/5 V I/O supply ground
39
63
47, 65
79
—
3.3 V/5 V I/O supply. 32 KHz oscillator
shares this supply with ADC.
T7
VSSE_C
VDDE_E
VSSE_E
3.3 V/5 V I/O supply ground
3.3 V/5 V I/O supply
64
109
110
77
80
133
134
93
—
B15, C14
—
3.3 V/5 V I/O supply ground
2
VDDMA
Stepper motor 5 V pad supply. SSD
shares this supply.
N13
VSSMA
Stepper motor ground
78
87
94
T16
L15
2
VDDMB
Stepper motor 5 V pad supply. SSD
shares this supply.
103
VSSMB
Stepper motor ground
88
97
104
113
L16
2
VDDMC
Stepper motor 5 V pad supply. SSD
shares this supply.
H15
VSSMC
VDDPLL
Stepper motor ground
1.2 V PLL supply
98
31
114
31
H16
L2
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
14
Freescale Semiconductor
Pinout and Signal Descriptions
Table 3. Voltage Supply Pin Descriptions (continued)
Pin Number
Supply pin
Function
144 LQFP
176 LQFP
208 MAPBGA
VSSPLL
VSSOSC
PLL ground
30
28
21
26
30
28
21
26
L1
—
Oscillator ground
3
VLCD
LCD supply option
N2
M2
4
VPP
9 V - 12 V flash test analog write signal
1
2
3
4
Decoupling capacitors must be connected between these pins and the nearest VSS12 pin.
All stepper motor supplies need to be at same level (3.3 V or 5 V).
Refer to LCD segment of Reference manual for usage of VLCD as supply/reference voltage source.
This signal needs to be connected to ground during normal operation.
2.4.3
Pad Types
In the device the following types of pads are available for system pins and functional port pins:
1
S = Slow
1,2
M = Medium
1,2
F = Fast
1
I = Input only with analog feature
J = Input/Output with analog feature
X = Oscillator
2.4.4
System Pins
The system pins are listed in Table 4.
1. Refer to Section 3.6, “I/O Pad Electrical Characteristics, for details
2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (refer to
PCR.SRC in the device reference manual, Pad Configuration Registers (PCR0 - PCR120)).
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Pinout and Signal Descriptions
Table 4. System Pin Descriptions
Pin Number
I/O
Pad
RESET
System pin
Function
direction type configuration
144 LQFP 176 LQFP 208 MAPBGA
RESET
Bidirectional reset with
Schmitt-Trigger
characteristics and noise
filter.
I/O
O
M
X
Input, weak pull
up
24
24
J1
EXTAL
XTAL
Analog output of the
oscillator amplifier circuit.
Input for the clock
generator in bypass
mode.
—
—
29
29
K1
Analog input of the
oscillator amplifier circuit.
Needs to be grounded if
oscillator bypass mode is
used.
I
X
27
27
M1
EXTAL32 Analog input of the 32KHz
oscillator amplifier circuit.
O
I
—
—
56
55
72
71
—
—
XTAL32 Analog output of the 32
KHz oscillator amplifier
circuit. Input for the clock
generator in bypass
mode.
NMI
Non-Maskable Interrupt
I/O
Input, weak pull
up
37
25
45
25
L3
VRC_CTRL Voltage Regulator
external NPN Ballast
base control pin
—
P1
2.4.5
Nexus Pins
Table 5. Nexus Pins
Pin Number
System pin
Function
144 LQFP 176 LQFP 208 MAPBGA
EVTI
Nexus Event In
—
—
—
—
37
35
33
38
T3
R3
T1
T5
EVTO
MCKO
MDO[0]
Nexus Event Out
Nexus Msg Clock Out
Nexus Msg Data Out
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
16
Freescale Semiconductor
Pinout and Signal Descriptions
Table 5. Nexus Pins (continued)
Function
Pin Number
System pin
144 LQFP 176 LQFP 208 MAPBGA
MDO[1]
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Start/End Out
—
—
—
—
40
42
44
34
P5
P4
L4
T2
MDO[2]
MDO[3]
MSE0
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
17
2.4.6
Functional Ports A, B, C, D, E, F, G, H, I, J, K
The functional port pins are listed in Table 6.
Table 6. Port Pin Summary
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PA[0]
PCR[0]
PCR[1]
PCR[2]
PCR[3]
PCR[4]
PCR[5]
PCR[6]
PCR[7]
Option 0 GPIO[0]
Option 1 DCU_R0
Option 2 eMIOSA[[22]
Option 3 SOUND
FP23
SIU
DCU
PWM/Timer
Sound
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
Input,
Pull Up
135
136
137
138
139
140
141
142
165
166
167
168
169
172
173
174
A1
B1
C1
C2
D1
D2
E1
E2
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
PA[6]
PA[7]
Option 0 GPIO[1]
Option 1 DCU_R1
Option 2 eMIOSA[21]
FP22
FP21
FP20
FP19
FP18
FP17
FP16
SIU
DCU
PWM/Timer
—
M
M
M
M
M
M
M
None,
None
Option 3
—
Option 0 GPIO[2]
Option 1 DCU_R2
Option 2 eMIOSA[20]
SIU
DCU
PWM/Timer
—
None,
None
Option 3
—
Option 0 GPIO[3]
Option 1 DCU_R3
Option 2 eMIOSA[19]
SIU
DCU
PWM/Timer
—
None,
None
Option 3
—
Option 0 GPIO[4]
Option 1 DCU_R4
Option 2 eMIOSA[18]
SIU
DCU
PWM/Timer
—
None,
None
Option 3
—
Option 0 GPIO[5]
Option 1 DCU_R5
Option 2 eMIOSA[17]
SIU
DCU
PWM/Timer
—
None,
None
Option 3
—
Option 0 GPIO[6]
Option 1 DCU_R6
Option 2 eMIOSA[15]
SIU
DCU
PWM/Timer
—
None,
None
Option 3
—
Option 0 GPIO[7]
Option 1 DCU_R7
Option 2 eMIOSA[16]
SIU
DCU
PWM/Timer
—
None,
None
Option 3
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PA[8]
PA[9]
PCR[8]
PCR[9]
Option 0 GPIO[8]
Option 1 DCU_G0
Option 2 eMIOSB[23]
Option 3 SCL_C
FP15
SIU
DCU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
None,
None
143
144
1
175
176
1
F1
F2
G1
G2
H1
H2
J2
PWM/Timer
I2C_2
Option 0 GPIO[9]
Option 1 DCU_G1
Option 2 eMIOSB[18]
Option 3 SDA_C
FP14
FP13
FP12
FP11
FP10
FP9
SIU
DCU
M
M
M
M
M
M
M
None,
None
PWM/Timer
I2C_2
PA[10] PCR[10] Option 0 GPIO[10]
Option 1 DCU_G2
SIU
DCU
PWM/Timer
—
None,
None
Option 2 eMIOSB[20]
Option 3
—
PA[11] PCR[11] Option 0 GPIO[11]
Option 1 DCU_G3
SIU
DCU
PWM/Timer
—
None,
None
2
2
Option 2 eMIOSA[13]
Option 3
—
PA[12] PCR[12] Option 0 GPIO[12]
Option 1 DCU_G4
SIU
DCU
PWM/Timer
—
None,
None
3
3
Option 2 eMIOSA[12]
Option 3
—
PA[13] PCR[13] Option 0 GPIO[13]
Option 1 DCU_G5
SIU
DCU
PWM/Timer
—
None,
None
4
4
Option 2 eMIOSA[11]
Option 3
—
PA[14] PCR[14] Option 0 GPIO[14]
Option 1 DCU_G6
SIU
DCU
PWM/Timer
—
None,
None
5
5
Option 2 eMIOSA[10]
Option 3
—
PA[15] PCR[15] Option 0 GPIO[15]
Option 1 DCU_G7
FP8
SIU
DCU
None,
None
6
6
H3
Option 2 eMIOSA[9]
PWM/Timer
—
Option 3
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PB[0] PCR[16] Option 0 GPIO[16]
Option 1 CANTX_A
—
—
—
—
—
—
—
—
SIU
CAN-A
PDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
None,
None
106
105
112
111
48
130
129
140
139
62
T15
T14
R14
R13
P8
Option 2 PDI1
Option 3
—
—
PB[1] PCR[17] Option 0 GPIO[17]
Option 1 CANRX_A
SIU
CAN-A
PDI
S
S
S
M
M
S
S
Input,
Pull Up
Option 2 PDI0
Option3
—
—
PB[2] PCR[18] Option 0 GPIO[18]
Option 1 TXD_A
SIU
LIN_A
—
None,
None
Option 2
Option3
—
—
—
PB[3] PCR[19] Option 0 GPIO[19]
Option 1 RXD_A
SIU
LIN_A
—
Input,
Pull Up
Option 2
Option3
—
—
—
PB[4] PCR[20] Option 0 GPIO[20]
Option 1 SCK_B
SIU
Input,
Pull Up
SPI_1
ADC
—
Option 2 MA0
Option 3
—
PB[5] PCR[21] Option 0 GPIO[21]
Option 1 SOUT_B
SIU
SPI_1
ADC
Input,
Pull
Down
49
63
N8
Option 2 MA1
Option 3 FABM
Control
PB[6] PCR[22] Option 0 GPIO[22]
Option 1 SIN_B
SIU
SPI_1
ADC
Input,
Pull Up
50
66
R7
Option 2 MA2
Option 3 ABS[0]
Control
PB[7] PCR[23] Option 0 GPIO[23]
Option 1 SIN_A
SIU
None,
None
46
56
P7
SPI_A
PWM/Timer
—
Option 2 eMIOSB[22]
Option 3
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PB[8] PCR[24] Option 0 GPIO[24]
Option 1 SOUT_A
—
—
—
—
—
—
SIU
I/O
I/O
I/O
I/O
I/O
I/O
M
None,
None
45
55
N7
SPI_A
PWM/Timer
—
Option 2 eMIOSB[21]
Option 3
—
PB[9] PCR[25] Option 0 GPIO[25]
Option 1 SCK_A
SIU
M
S
M
S
S
Input,
Pull Up
44
54
T6
SPI_A
PWM/Timer
—
Option 2 eMIOSB[20]
Option 3
—
PB[10] PCR[26] Option 0 GPIO[26]
Option 1 CNRX_B
SIU
CAN-B
PDI
Input,
Pull Up
107
108
40
131
132
48
P13
N12
R6
Option 2 PDI2
Option 3 eMIOSA[23]
PWM/Timer
PB[11] PCR[27] Option 0 GPIO[27]
Option 1 CNTX_B
SIU
CAN-B
PDI
None,
None
Option 2 PDI3
Option 3 eMIOSA[16]
PWM/Timer
PB[12] PCR[28] Option 0 GPIO[28]
Option 1 RXD_B
SIU
LIN_B
PWM/Timer
SPI_0
Input,
Pull Up
Option 2 eMIOSB[19]
Option 3 PCS_A2
PB[13] PCR[29] Option 0 GPIO[29]
Option 1 TXD_B
SIU
LIN_B
None,
None
41
49
P6
Option 2 eMIOSB[18]
Option 3 PCS_A1
PWM/Timer
SPI_0
PB[14]
PB[15]
—
—
—
—
Reserved
Reserved
—
—
—
—
—
—
—
—
A
—
—
—
—
72
—
—
88
A11
—
—
PC[0] PCR[30] Option 0 GPIO[30]
Option 1 AN[0]
SIU
ADC
—
I
Input,
Pull Up
T13
Option 2
Option 3
—
—
—
PC[1] PCR[31] Option 0 GPIO[31]
Option 1 AN[1]
—
SIU
ADC
—
I
A
Input,
Pull Up
71
87
T12
Option 2
Option 3
—
—
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PC[2] PCR[32] Option 0 GPIO[32]
Option 1 AN[2]
—
—
—
—
—
—
—
—
SIU
ADC
—
I
A
Input,
Pull Up
70
69
68
67
66
65
62
61
86
85
84
83
82
81
78
77
R12
P12
R11
P11
N11
R10
P10
N10
Option 2
Option 3
—
—
—
PC[3] PCR[33] Option 0 GPIO[33]
Option 1 AN[3]
SIU
ADC
—
I
I
I
I
I
I
I
A
A
A
A
A
A
A
Input,
Pull Up
Option 2
Option 3
—
—
—
PC[4] PCR[34] Option 0 GPIO[34]
Option 1 AN[4]
SIU
ADC
—
Input,
Pull Up
Option 2
Option 3
—
—
—
PC[5] PCR[35] Option 0 GPIO[35]
Option 1 AN[5]
SIU
ADC
—
Input,
Pull Up
Option 2
Option 3
—
—
—
PC[6] PCR[36] Option 0 GPIO[36]
Option 1 AN[6]
SIU
ADC
—
Input,
Pull Up
Option 2
Option 3
—
—
—
PC[7] PCR[37] Option 0 GPIO[37]
Option 1 AN[7]
SIU
ADC
—
Input,
Pull Up
Option 2
Option 3
—
—
—
PC[8] PCR[38] Option 0 GPIO[38]
Option 1 AN[8]
SIU
ADC
—
Input,
Pull Up
Option 2
Option 3
—
—
—
PC[9] PCR[39] Option 0 GPIO[39]
Option 1 AN[9]
SIU
ADC
—
Input,
Pull Up
Option 2
Option 3
—
—
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PC[10] PCR[40] Option 0 GPIO[40]
Option 1 AN[10]
—
—
—
—
—
—
—
—
SIU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
Input,
Pull Up
60
59
58
57
56
55
73
74
76
75
74
73
72
71
89
90
T9
ADC
Sound
—
Option 2 SOUND
Option 3
—
PC[11] PCR[41] Option 0 GPIO[41]
Option 1 AN[11]
SIU
S
S
S
S
S
None,
None
R9
ADC
ADC
SPI_B
Option 2 MA0
Option 3 PCS_B2
PC[12] PCR[42] Option 0 GPIO[42]
Option 1 AN[12]
SIU
None,
None
P9
ADC
ADC
SPI_B
Option 2 MA1
Option 3 PCS_B1
PC[13] PCR[43] Option 0 GPIO[43]
Option 1 AN[13]
SIU
None,
None
N9
ADC
ADC
SPI_B
Option 2 MA2
Option 3 PCS_B0
PC[14] PCR[44] Option 0 GPIO[44]
Option 1 AN[14]
SIU
ADC
Osc
—
None,
None
T8
Option 2 EXTAL32
Option 3
—
PC[15] PCR[45] Option 0 GPIO[45]
Option 1 AN[15]
SIU
ADC
Osc
—
None,
None
R8
Option 2 XTAL32
Option 3
—
PD[0] PCR[46] Option 0 GPIO[46]
Option 1 M0C0M
SIU
SMD
SSD
PWM/Timer
SMD None,
None
R16
P16
Option 2 SSD0_0
Option 3 eMIOSB[23]
PD[1] PCR[47] Option 0 GPIO[47]
Option 1 M0C0P
SIU
SMD
SMD None,
None
Option 2 SSD0_1
SSD
Option 3 eMIOSB[22]
PWM/Timer
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PD[2] PCR[48] Option 0 GPIO[48]
Option 1 M0C1M
—
—
—
—
—
—
—
—
SIU
SMD
SSD
PWM/Timer
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SMD None,
None
75
76
79
80
81
82
83
84
91
92
95
96
97
98
99
100
P15
N16
N15
M15
M16
K16
J16
Option 2 SSD0_2
Option 3 eMIOSB[21]
PD[3] PCR[49] Option 0 GPIO[49]
Option 1 M0C1P
SIU
SMD
SSD
PWM/Timer
SMD None,
None
Option 2 SSD0_3
Option 3 eMIOSB[20]
PD[4] PCR[50] Option 0 GPIO[50]
Option 1 M1C0M
SIU
SMD
SSD
PWM/Timer
SMD None,
None
Option 2 SSD1_0
Option 3 eMIOSB[19]
PD[5] PCR[51] Option 0 GPIO[51]
Option 1 M1C0P
SIU
SMD
SSD
PWM/Timer
SMD None,
None
Option 2 SSD1_1
Option 3 eMIOSB[18]
PD[6] PCR[52] Option 0 GPIO[52]
Option 1 M1C1M
SIU
SMD
SSD
PWM/Timer
SMD None,
None
Option 2 SSD1_2
Option 3 eMIOSB[17]
PD[7] PCR[53] Option 0 GPIO[53]
Option 1 M1C1P
SIU
SMD
SSD
PWM/Timer
SMD None,
None
Option 2 SSD1_3
Option 3 eMIOSB[16]
PD[8] PCR[54] Option 0 GPIO[54]
Option 1 M2C0M
SIU
SMD
SSD
—
SMD None,
None
Option 2 SSD2_0
Option 3
—
PD[9] PCR[55] Option 0 GPIO[55]
Option 1 M2C0P
SIU
SMD
SSD
—
SMD None,
None
K15
Option 2 SSD2_1
Option 3
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PD[10] PCR[56] Option 0 GPIO[56]
Option 1 M2C1M
—
—
—
—
—
—
—
—
SIU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SMD None,
None
85
86
89
90
91
92
93
94
101
102
105
106
107
108
109
110
N14
M14
L14
K14
M13
L13
J15
SMD
SSD
—
Option 2 SSD2_2
Option 3
—
PD[11] PCR[57] Option 0 GPIO[57]
Option 1 M2C1P
SIU
SMD
SSD
—
SMD None,
None
Option 2 SSD2_3
Option 3
—
PD[12] PCR[58] Option 0 GPIO[58]
Option 1 M3C0M
SIU
SMD
SSD
—
SMD None,
None
Option 2 SSD3_0
Option 3
—
PD[13] PCR[59] Option 0 GPIO[59]
Option 1 M3C0P
SIU
SMD
SSD
—
SMD None,
None
Option 2 SSD3_1
Option 3
—
PD[14] PCR[60] Option 0 GPIO[60]
Option 1 M3C1M
SIU
SMD
SSD
—
SMD None,
None
Option 2 SSD3_2
Option 3
—
PD[15] PCR[61] Option 0 GPIO[61]
Option 1 M3C1P
SIU
SMD
SSD
—
SMD None,
None
Option 2 SSD3_3
Option 3
—
PE[0] PCR[62] Option 0 GPIO[62]
Option 1 M4C0M
SIU
SMD
SSD
PWM/Timer
SMD None,
None
Option 2 SSD4_0
Option 3 eMIOSA[15]
PE[1] PCR[63] Option 0 GPIO[63]
Option 1 M4C0P
SIU
SMD
SMD None,
None
G15
Option 2 SSD4_1
SSD
Option 3 eMIOSA[14]
PWM/Timer
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PE[2] PCR[64] Option 0 GPIO[64]
Option 1 M4C1M
—
—
—
—
—
—
SIU
SMD
SSD
PWM/Timer
I/O
I/O
I/O
I/O
I/O
I/O
SMD None,
None
95
111
112
115
116
117
118
J14
K13
J13
Option 2 SSD4_2
Option 3 eMIOSA[13]
PE[3] PCR[65] Option 0 GPIO[65]
Option 1 M4C1P
SIU
SMD
SSD
PWM/Timer
SMD None,
None
96
Option 2 SSD4_3
Option 3 eMIOSA[12]
PE[4] PCR[66] Option 0 GPIO[66]
Option 1 M5C0M
SIU
SMD
SSD
PWM/Timer
SMD None,
None
99
Option 2 SSD5_0
Option 3 eMIOSA[11]
PE[5] PCR[67] Option 0 GPIO[67]
Option 1 M5C0P
SIU
SMD
SSD
PWM/Timer
SMD None,
None
100
101
102
H13
H14
G14
Option 2 SSD5_1
Option 3 eMIOSA[10]
PE[6] PCR[68] Option 0 GPIO[68]
Option 1 M5C1M
SIU
SMD
SSD
PWM/Timer
SMD None,
None
Option 2 SSD5_2
Option 3 eMIOSA[9]
PE[7] PCR[69] Option 0 GPIO[69]
Option 1 M5C1P
SIU
SMD
SMD None,
None
Option 2 SSD5_3
SSD
Option 3 eMIOSA[8]
PWM/Timer
PE[8]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PE[9]
—
PE[10]
PE[11]
PE[12]
PE[13]
PE[14]
PE[15]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PCR[70] Option 0 GPIO[70]
Option 1 eMIOSA[13]
Option 2 PDI4
FP39
SIU
PWM/Timer
PDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
Input,
Pull Up
113
114
37
143
144
45
A8
B8
L3
Option 3 eMIOSA[22]
PWM/Timer
PCR[71] Option 0 GPIO[71]
Option 1 eMIOSA[12]
Option 2 PDI5
FP38
SIU
PWM/Timer
PDI
S
S
None,
None
Option 3 eMIOSA[21]
PWM/Timer
PCR[72] Option 0 GPIO[72]
Option 1 NMI
—
SIU
NMI
—
Input,
Pull Up
Option 2
Option 3
—
—
—
PCR[73] Option 0 GPIO[73]
Option 1 eMIOSA[11]
Option 2 PDI6
FP37
FP36
FP35
FP34
FP33
SIU
PWM/Timer
PDI
—
M
M
M
S
Input,
Pull Up
115
116
117
120
121
145
146
147
150
151
C8
D8
A9
B9
C9
Option 3
—
PCR[74] Option 0 GPIO[74]
Option 1 eMIOSA[10]
Option 2 PDI7
SIU
PWM/Timer
PDI
—
None,
None
Option 3
—
PCR[75] Option 0 GPIO[75]
Option 1 eMIOSA[9]
SIU
PWM/Timer
DCU
Input,
Pull Up
Option 2 DCU_TAG
Option 3
—
—
PCR[76] Option 0 GPIO[76]
Option 1 SDA_A
SIU
I2C_A
—
Input,
Pull Up
Option 2
Option 3
—
—
—
PCR[77] Option 0 GPIO[77]
Option 1 SCL_A
SIU
S
None,
None
I2C_A
SPI_B
—
Option 2 PCS_B2
Option 3
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PF[8]
PF[9]
PCR[78] Option 0 GPIO[78]
Option 1 SDA_B
FP32
SIU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
Input,
Pull Up
122
123
127
128
129
130
131
132
152
153
157
158
159
160
161
162
T4
I2C_B
SPI_B
LIN_B
Option 2 PCS_B1
Option 3 RXD_B
PCR[79] Option 0 GPIO[79]
Option 1 SCL_B
FP31
FP29
FP28
FP27
FP26
FP25
FP24
SIU
S
M
M
M
M
M
F
None,
None
R4
I2C_B
SPI_B
LIN_B
Option 2 PCS_B0
Option 3 TXD_B
PF[10] PCR[80] Option 0 GPIO[80]
Option 1 eMIOSA[16]
SIU
None,
None
A14
A15
A16
B16
C16
D16
PWM/Timer
SPI_C
—
Option 2 PCS_C0
Option 3
—
PF[11] PCR[81] Option 0 GPIO[81]
Option 1 eMIOSB[23]
SIU
Input,
Pull Up
PWM/Timer
SPI_C
—
Option 2 PCS_C1
Option 3
—
PF[12] PCR[82] Option 0 GPIO[82]
Option 1 eMIOSB[16]
SIU
None,
None
PWM/Timer
SPI_C
—
Option 2 PCS_C2
Option 3
—
PF[13] PCR[83] Option 0 GPIO[83]
Option 1 SIN_C
SIU
Input,
Pull Up
SPI_C
CAN_B
—
Option 2 CNRX_B
Option 3
—
PF[14] PCR[84] Option 0 GPIO[84]
Option 1 SOUT_C
SIU
None,
None
SPI_C
CAN_B
—
Option 2 CANTX_B
Option 3
—
PF[15] PCR[85] Option 0 GPIO[85]
Option 1 SCK_C
SIU
SPI_C
—
None,
None
Option 2
Option 3
—
—
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PG[0] PCR[86] Option 0 GPIO[86]
Option 1 DCU_B0
FP7
SIU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
None,
None
9
9
D3
E3
E4
F3
F4
G3
G4
H4
DCU
Option 2 SCL_D
Option 3 SOUND
I2C_3
Sound
PG[1] PCR[87] Option 0 GPIO[87]
Option 1 DCU_B1
FP6
FP5
FP4
FP3
FP2
FP1
FP0
SIU
M
M
M
M
M
M
M
None,
None
10
11
12
13
14
15
16
10
11
12
13
14
15
16
DCU
I2C_3
—
Option 2 SDA_D
Option 3
—
PG[2] PCR[88] Option 0 GPIO[88]
Option 1 DCU_B2
SIU
DCU
PWM/Timer
—
None,
None
Option 2 eMIOSB[19]
Option 3
—
PG[3] PCR[89] Option 0 GPIO[89]
Option 1 DCU_B3
SIU
DCU
PWM/Timer
—
None,
None
Option 2 eMIOSB[21]
Option 3
—
PG[4] PCR[90] Option 0 GPIO[90]
Option 1 DCU_B4
SIU
DCU
PWM/Timer
—
None,
None
Option 2 eMIOSB[17]
Option 3
—
PG[5] PCR[91] Option 0 GPIO[91]
Option 1 DCU_B5
SIU
DCU
PWM/Timer
—
None,
None
Option 2 eMIOSA[8]
Option 3
—
PG[6] PCR[92] Option 0 GPIO[92]
Option 1 DCU_B6
SIU
DCU
—
None,
None
Option 2
Option 3
—
—
—
PG[7] PCR[93] Option 0 GPIO[93]
Option 1 DCU_B7
SIU
DCU
—
None,
None
Option 2
Option 3
—
—
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PG[8] PCR[94] Option 0 GPIO[94]
Option 1 DCU_VSYNC
BP0
SIU
DCU
—
I/O
I/O
I/O
I/O
I/O
M
Input,
Pull Up
17
17
J3
Option 2
Option 3
—
—
—
PG[9] PCR[95] Option 0 GPIO[95]
Option 1 DCU_HSYNC
BP1
BP2
BP3
FP30
SIU
DCU
—
M
M
M
S
Input,
Pull Up
18
18
K3
Option 2
Option 3
—
—
—
PG[10] PCR[96] Option 0 GPIO[96]
Option 1 DCU_DE
SIU
DCU
—
None,
None
19
19
J4
Option 2
Option 3
—
—
—
PG[11] PCR[97] Option 0 GPIO[97]
Option 1 DCU_PCLK
SIU
DCU
—
None,
None
20
20
K4
Option 2
Option 3
—
—
—
PG[12] PCR[98] Option 0 GPIO[98]
Option 1 eMIOSA[23]
SIU
PWM/Timer
Sound
None,
None
126
156
D10
Option 2 SOUND
Option 3 eMIOSA[8]
PWM/Timer
PG[13]
PG[14]
PG[15]
—
—
—
—
—
—
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
S
—
—
—
—
—
—
36
—
—
—
43
—
—
—
—
PH[0]4 PCR[99] Option 0 GPIO[99]
Option 1 TCK
SIU
JTAG
—
I/O
Input,
Pull Up
R1
Option 2
Option 3
—
—
—
PH[1]4 PCR[100] Option 0 GPIO[100]
Option 1 TDI
—
SIU
JTAG
—
I/O
S
Input,
Pull Up
33
36
P2
Option 2
Option 3
—
—
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PH[2]4 PCR[101] Option 0 GPIO[101]
Option 1 TDO
—
—
—
—
SIU
JTAG
—
I/O
I/O
I/O
M
Output,
None
34
35
47
21
39
41
61
21
N3
M3
R5
—
Option 2
Option 3
—
—
—
PH[3]4 PCR[102] Option 0 GPIO[102]
Option 1 TMS
SIU
JTAG
—
S
F
Input,
Pull Up
Option 2
Option 3
—
—
—
PH[4] PCR[103] Option 0 GPIO[103]
Option 1 PCS_A0
SIU
SPI_0
PWM/Timer
Control
None,
None
Option 2 eMIOSB[16]
Option 3 CLKOUT
PH[5] PCR[104] Option 0 GPIO[104]
Option 1 VLCD
SIU
LCD
—
Option 2
Option 3
—
—
—
PH[6]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
S
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
119
—
—
—
—
—
—
—
—
—
—
A2
PH[7]
PH[8]
—
PH[9]
—
PH[10]
PH[11]
PH[12]
PH[13]
PH[14]
PH[15]
PJ[0]
—
—
—
—
—
—
PCR[105] Option 0 GPIO[105]
Option 1 PDI_DE
SIU
PDI
—
I/O
None,
None
Option 2
Option 3
—
—
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PJ[1]
PJ[2]
PJ[3]
PJ[4]
PJ[5]
PJ[6]
PJ[7]
PJ[8]
PCR[106] Option 0 GPIO[106]
Option 1 PDI_HSYNC
—
—
—
—
—
—
—
—
SIU
PDI
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
None,
None
—
—
—
—
—
—
—
—
120
121
122
57
A3
B3
A4
B4
A5
B5
A6
B6
Option 2
Option 3
—
—
—
PCR[107] Option 0 GPIO[107]
Option 1 PDI_VSYNC
SIU
PDI
—
S
M
S
None,
None
Option 2
Option 3
—
—
—
PCR[108] Option 0 GPIO[108]
Option 1 PDI_PCLK
SIU
PDI
—
None,
None
Option 2
Option 3
—
—
—
PCR[109] Option 0 GPIO[109]
Option 1 PDI[0]
SIU
PDI
CAN-A
—
Input,
Pull Up
Option 2 CNRX_A
Option 3
—
PCR[110] Option 0 GPIO[110]
Option 1 PDI[1]
SIU
PDI
CAN-A
—
M
S
None,
None
58
Option 2 CNTX_A
Option 3
—
PCR[111] Option 0 GPIO[111]
Option 1 PDI[2]
SIU
PDI
CAN-B
PWM/Timer
Input,
Pull Up
59
Option 2 CNRX_B
Option 3 eMIOSA[22]
PCR[112] Option 0 GPIO[112]
Option 1 PDI[3]
SIU
PDI
CAN-B
PWM/Timer
M
S
None,
None
60
Option 2 CNTX_B
Option 3 eMIOSA[21]
PCR[113] Option 0 GPIO[113]
Option 1 PDI[4]
SIU
PDI
—
None,
None
125
Option 2
Option 3
—
—
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PJ[9]
PCR[114] Option 0 GPIO[114]
Option 1 PDI[5]
—
—
—
—
—
—
—
—
SIU
PDI
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
None,
None
—
—
—
—
—
—
—
—
126
127
128
135
136
137
138
141
C4
C5
D5
C6
D6
A7
B7
C7
Option 2
Option 3
—
—
—
PJ[10] PCR[115] Option 0 GPIO[115]
Option 1 PDI[6]
SIU
PDI
—
S
S
None,
None
Option 2
Option 3
—
—
—
PJ[11] PCR[116] Option 0 GPIO[116]
Option 1 PDI[7]
SIU
PDI
—
None,
None
Option 2
Option 3
—
—
—
PJ[12] PCR[117] Option 0 GPIO[117]
Option 1 PDI[8]
SIU
PDI
PWM/Timer
—
M
M
M
M
M
None,
None
Option 2 eMIOSB[17]
Option 3
—
PJ[13] PCR[118] Option 0 GPIO[118]
Option 1 PDI[9]
SIU
PDI
PWM/Timer
—
None,
None
Option 2 eMIOSB[20]
Option 3
—
PJ[14] PCR[119] Option 0 GPIO[119]
Option 1 PDI[10]
SIU
PDI
PWM/Timer
—
None,
None
Option 2 eMIOSA[20]
Option 3
—
PJ[15] PCR[120] Option 0 GPIO[120]
Option 1 PDI[11]
SIU
PDI
PWM/Timer
—
None,
None
Option 2 eMIOSA[19]
Option 3
—
PK[0]
PCR[121] Option 0 GPIO[121]
Option 1 PDI[12]
SIU
PDI
None,
None
Option 2 eMIOSA[18]
Option 3 DCU_TAG
PWM/Timer
DCU
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PK[1]
PK[2]
PK[3]
PK[4]
PK[5]
PK[6]
PK[7]
PK[8]
PCR[122] Option 0 GPIO[122]
Option 1 PDI[13]
—
—
—
—
—
—
—
—
SIU
PDI
PWM/Timer
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
None,
None
—
—
—
—
—
—
—
—
142
33
34
35
37
38
40
42
D7
B12
C12
D12
—
Option 2 eMIOSA[17]
Option 3
—
PCR[123] Option 0 GPIO[123]
Option 1 MCKO
SIU
Nexus
PDI
—
F
None,
None
Option 2 PDI[10]
Option 3
—
PCR[124] Option 0 GPIO[124]
Option 1 MSEO
SIU
Nexus
PDI
—
M
M
M
M
M
M
None,
None
Option 2 PDI[11]
Option 3
—
PCR[125] Option 0 GPIO[125]
Option 1 EVTO
SIU
Nexus
PDI
—
None,
None
Option 2 PDI[12]
Option 3
—
PCR[126] Option 0 GPIO[126]
Option 1 EVTI
SIU
Nexus
PDI
—
None,
None
Option 2 PDI[13]
Option 3
—
PCR[127] Option 0 GPIO[127]
Option 1 MDO0
SIU
Nexus
PDI
—
None,
None
B11
C11
D11
Option 2 PDI[14]
Option 3
—
PCR[128] Option 0 GPIO[128]
Option 1 MDO1
SIU
Nexus
PDI
—
None,
None
Option 2 PDI[15]
Option 3
—
PCR[129] Option 0 GPIO[129]
Option 1 MDO2
SIU
Nexus
PDI
—
None,
None
Option 2 PDI[16]
Option 3
—
Table 6. Port Pin Summary (continued)
Port
Pin
Pad RESET
Type Config.
Pin Number
PCR
Alternate
Special
Function
I/O
Direction
Function
Peripheral
Register Function1
2
3
144 LQFP 176 LQFP 208 MAPBGA
PK[9]
PCR[130] Option 0 GPIO[130]
Option 1 MDO3
—
—
—
SIU
I/O
I/O
I/O
M
Input,
Pull Up
—
—
—
44
52
53
A10
Nexus
PDI
—
Option 2 PDI[17]
Option 3
—
PK[10] PCR[131] Option 0 GPIO[131]
Option 1 SDA_B
SIU
S
S
None,
None
N6
I2C_B
PWM/Timer
—
Option 2 eMIOSA[15]
Option 3
—
PK[11] PCR[132] Option 0 GPIO[132]
Option 1 SCL_B
SIU
None,
None
N5
I2C_B
PWM/Timer
—
Option 2 eMIOSA[14]
Option 3
—
PK[12]
PK[13]
PK[14]
PK[15]
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module. PCR.PA = 00 -> Option 0; PCR.PA = 01 -> Option
1; PCR.PA = 10 -> Option 2; PCR.PA = 11-> Option 3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE
bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function
is reported as “—”.
2
3
4
A=A, S=Slow, M=Medium, F=Fast, SMD=Stepper Motor Driver
Reset configuration is given as I/O direction and pull, e.g., “Input, pullup”.
Out of reset pins PH[0:3] are available as JTAG pins (TCK, TDI, TDO and TMS respectively). It is up to the user to configure pins PH[0:3] when
needed.
Pinout and Signal Descriptions
2.4.7
Signal Details
Table 7. Signal Details
Signal
ABS[0]
Peripheral
Description
BAM
Alternate Boot Select. gives an option to boot by downloading code via
CAN or LIN.
AN[0:15]
FABM
Analog-to-digital
conversion (ADC)
Inputs used to bring into the device sensor-based signals for A/D
conversion.
Force Alternate Boot mode. Forces the device to boot from the external
bus (Can or LIN). If not asserted, the device boots up from the lowest
flash sector containing a valid boot signature.
Display Control Unit Indicates that valid pixels are present when high; otherwise low to allow
a sub frame display for pixels.
DCU_DE
DCU_HSYNC,
DCU_PCLK
Display Control Unit Horizontal sync pulse for TFT-LCD display.
Display Control Unit Output pixel clock for TFT-LCD display
DCU_R[0:7],
DCU_G[0:7]
DCU_B[0:7]
Display Control Unit Red, green and blue color 8 bit Pixel values for TFT-LCD displays.
DCU_TAG
Display Control Unit High indicates certain pixels that can be called as tagged pixels, upon
which internal CRC has been calculated based on pixel values and pixel
position.
DCU_VSYNC
Display Control Unit Vertical sync pulse for TFT-LCD display.
PCS_A[0:2],
PCS_B[0:2],
PCS_C[0:2}
DSPI
DSPI
DSPI
DSPI
eMIOS
Peripheral chip selects when device is in Master mode; not used in slave
modes.
SCK_A,
SCK_B,
SCK_C
SPI clock signal - bi-directional.
SPI data input signal.
SIN _A,
SIN _B,
SIN _C
SOUT _A,
SOUT _B,
SOUT _C
SPI data output signal.
eMIOSA[0:23],
eMIOSB[0:23]
Enhanced Modular Input Output System. 16+9 channel eMIOS for timed
input or output functions.
CNRX_A, CNRX_B FlexCAN
CNTX_A, CNTX_B FlexCAN
Receive (RX) pins for the CAN bus transceiver.
Transmit (TX) pins for the CAN bus transceiver.
Bidirectional serial clock compatible with I2C specifications.
SCL_A,
SCL_B,
SCL_C,
SCL_D
I2C
SDA_A,
SDA_B,
SDA_C,
SDA_D
I2C
Bidirectional serial data compatible with I2C specifications.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
36
Freescale Semiconductor
Pinout and Signal Descriptions
Table 7. Signal Details (continued)
Peripheral Description
JTAG
Signal
TCK
TDI
Debug port serial clock as per JTAG specifications.
JTAG
JTAG
JTAG
Debug port serial data input port as per JTAG standards specifications.
Debug port serial data output port as per JTAG standards specifications.
TDO
TMS
Debug port Test Mode Select signal for the JTAG TAP controller state
machine and indicates various state transitions for the TAP controller in
the device.
BP[0:3]
LCD
Back plane signals from the LCD controlling the back plane reference
voltage for the LCD display.
FP[0:39]
EVTI
LCD
Front plane signals for LCD segments.
Nexus2+ event input trigger.
Nexus
Nexus
Nexus
Nexus
EVTO
Nexus2+ event output trigger.
MCKO
MDO[0:3]
Output clock for the development tool
Message output port pins that send information bits to the development
tools for messages such as Branch Trace Message (BTM), Ownership
Trace Message (OTM), Data Trace Message (DTM). Only available in
reduced port mode.
MSEO
Nexus
Output pin. Indicates the start or end of the variable length message on
the MDO pins.
PDI[0:17]
PDI_DE
Parallel Display
Interface
Video/graphic data in various RGB modes input to the DCU.
Parallel Display
Interface
Input signal indicates the validity of pixel data on the Input PDI data bus.
For valid Pixel Data this is high, otherwise low.
PDI_HSYNC
PDI_PCLK
PDI_VSYNC
RXD_A
Parallel Display
Interface
Input indicates the timing reference for the start of each frame line for the
PDI Input data.
Parallel Display
Interface
Output pixel clock for PDI.
Parallel Display
Interface
Input indicates the timing reference for the start of a frame for the PDI
input data.
LINFlex-UART
SCI/LIN Receive data signal. This port is used to download the code for
the BAM boot sequence
RXD_B
LINFlex-UART
SCI/LIN Receive data signal. Input pad for the LIN SCI module.
Connects to the internal LIN second port.
TXD_A
TXD_B
LINFlex-UART
LINFlex-UART
This port is used to download the code for the BAM boot sequence
SCI/LIN Transmit data signal. Transmit (output) port for the second LIN
module in the chip .
SOUND
Sound generation
logic (SGL)
Sound signal to the speaker/buzzer.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
37
Pinout and Signal Descriptions
Table 7. Signal Details (continued)
Peripheral Description
Signal
SSD[0..5]_0
SSD[0..5]_1
SSD[0..5]_2
SSD[0..5]_3
SSD (Stepper Stall Bidirectional SSD inputs and control signals
Detect) Interface
M[0:5]C0M
M[0:5]C0P
M[0:5]C1M
M[0:5]C1P
Stepper Motor
Control (SMC)
Interface
Controls stepper motors in Dual H bridge configuration.
CLKOUT
Clock generation
module (CGM)
Output clock. It can be selected from several internal clocks of the device
from the clock generation module.
MA[0:2]
ADC
These three control bits are output to enable the selection for an external
Analog Mux for expansion channels.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
38
Freescale Semiconductor
Electrical Characteristics
3
Electrical Characteristics
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This could be done by
DD
SS
internal pull up and pull down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
3.1
Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings
Value
Max
Symbol
Parameter
Conditions
Unit
Min
VDDA
SR Voltage on VDDA pin (ADC reference) with respect
to ground (VSSA
-0.3
+5.5
V
)
Relative to VDD VDD-0.3
VSS-0.1
VDD+0.3
VSS+0.1
VSSA
SR Voltage on VSSA (ADC reference) pin with respect
VSS
V
V
VDDPLL
CC Voltage on VDDPLL (1.2 V PLL supply) pin with
1.08
Relative to VDD VDD-0.3
VSS-0.1
1.32
respect to ground (VSSPLL
)
VDD+0.3
VSS+0.1
VSSPLL
VDDR
SR Voltage on VSSMC (stepper motor supply ground)
pin with respect to VSS
V
V
SR Voltage on VDDR pin (regulator supply) with respect
-0.3
Relative to VDD VDD-0.3
VSS-0.1
+5.5
to ground (VSSR
)
VDD+0.3
VSS+0.1
VSSR
VDD12
VSS12
SR Voltage on VSSR (regulator ground) pin with
respect to VSS
V
V
CC Voltage on VDD12 pin with respect to ground
1.08
1.4
(VSS12
)
CC Voltage on VSS12 pin with respect to VSS
VSS-0.1
-0.3
VSS+0.1
+5.5
V
V
1
VDDE_A
VDDE_B
VDDE_C
VDDE_E
SR Voltage on VDDE_A (I/O supply) pin with respect to
ground (VSSE_A
)
1
1
1
SR Voltage on VDDE_B (I/O supply) pin with respect to
-0.3
-0.3
-0.3
+5.5
+5.5
+5.5
V
V
V
ground (VSSE_B
)
SR Voltage on VDDE_C (I/O supply) pin with respect to
ground (VSSE_C
)
SR Voltage on VDDE_E (I/O supply) pin with respect to
ground (VSSE_E
)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
39
Electrical Characteristics
Table 8. Absolute Maximum Ratings (continued)
Value
Max
Symbol
Parameter
Conditions
Unit
Min
1
VDDMA
SR Voltage on VDDMA (stepper motor supply) pin with
respect to ground (VSSMA
-0.3
+5.5
+5.5
+5.5
V
V
V
)
1
1
VDDMB
SR Voltage on VDDMB (stepper motor supply) pin with
respect to ground (VSSMB
-0.3
-0.3
)
VDDMC
SR Voltage on VDDMC (stepper motor supply) pin with
respect to ground (VSSMC
)
2
VSS
SR I/O supply ground
0
0
V
V
VSSOSC SR Voltage on VSSOSC (oscillator ground) pin with
respect to VSS
VSS-0.1
VSS+0.1
VLCD
SR Voltage on VLCD (LCD supply) pin with respect to
VSS
0
VDDE_A +0.3
V
V
VIN
SR Voltage on any GPIO pin with respect to ground
-0.3
-0.3
-10
+5.5
VDD+0.3
10
(VSS
)
Relative to VDD
IINJPAD
IINJSUM
SR Injected input current on any pin during overload
condition
mA
SR Absolute sum of all injected input currents during
overload condition
-50
-55
50
TSTORAGE SR Storage temperature
150
°C
V
ESDHBM SR ESD Susceptibility (Human Body Model)
2000
1
2
Throughout the remainder of this document VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B
VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC, unless otherwise noted.
,
Throughout the remainder of this document VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A
,
VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC, unless otherwise noted.
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (V > V or
IN
DD
V
< V ), the voltage on pins with respect to ground (V ) must not exceed the
IN
SS SS
recommended values.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
40
Freescale Semiconductor
Electrical Characteristics
3.1.1
Recommended Operating Conditions
Table 9. Recommended Operating Conditions (3.3 V)
Value
Unit
Symbol
Parameter
Conditions
Min
Max
1
VDDA
SR Voltage on VDDA pin (ADC reference) with respect
+3.0
+3.6
V
to ground (VSS
)
Relative to VDD VDD-0.1
VSS-0.1
VDD+0.1
VSS+0.1
VSSA
SR Voltage on VSSA (ADC reference) pin with respect
VSS
V
V
V
V
VDDPLL CC Voltage on VDDPLL (1.2 V PLL supply) pin with
respect to ground (VSSPLL
1.08
1.32
)
VSSPLL SR Voltage on VSSMC (stepper motor supply ground)
pin with respect to VSS
VSS-0.1
VSS+0.1
2
VDDR
SR Voltage on VDDR pin (regulator supply) with respect
to ground (VSSR
+3.0
Relative to VDD VDD-0.1
VSS-0.1
+3.6
)
VDD+0.1
VSS+0.1
VSSR
SR Voltage on VSSR (regulator ground) pin with
respect to VSS
V
V
3,4
VDD12
CC Voltage on VDD12 pin with respect to ground
1.08
1.4
(VSS12
)
VSS12 CC Voltage on VSS12 pin with respect to VSS
VSS-0.1
+3.0
VSS+0.1
+3.6
V
V
5,6,7
VDD
SR Voltage on VDD pins (VDDE_A, VDDE_B,
VDDE_C, VDDE_E, VDDMA, VDDMB, VDDMC)
with respect to ground (VSS
)
8
VSS
SR I/O supply ground
0
0
V
V
VDDE_A SR Voltage on VDDE_A (I/O supply) pin with respect to
ground (VSSE_A
+3.0
+3.6
)
VDDE_B SR Voltage on VDDE_B (I/O supply) pin with respect to
ground (VSSE_B
+3.0
+3.0
+3.0
+3.0
+3.0
+3.0
0
+3.6
+3.6
+3.6
+3.6
+3.6
+3.6
0
V
V
V
V
V
V
V
)
9
VDDE_C SR Voltage on VDDE_C (I/O supply) pin with respect to
ground (VSSE_C
)
VDDE_E SR Voltage on VDDE_E (I/O supply) pin with respect to
ground (VSSE_E
)
VDDMA SR Voltage on VDDMA (stepper motor supply) pin with
respect to ground (VSSMA
)
VDDMB SR Voltage on VDDMB (stepper motor supply) pin with
respect to ground (VSSMB
)
VDDMC SR Voltage on VDDMC (stepper motor supply) pin with
respect to ground (VSSMC
)
VSSOSC SR Voltage on VSSOSC (oscillator ground) pin with
respect to VSS
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
41
Electrical Characteristics
Table 9. Recommended Operating Conditions (3.3 V) (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VLCD
SR Voltage on VLCD (LCD supply) pin with respect to
VSS
0
VDDE_A +0.3
V
TVDD
TA
SR VDD slope to ensure correct power up10
SR Ambient temperature under bias
SR Junction temperature under bias
0.25
+105
+150
V/µs
°C
-40
-40
TJ
1
2
3
4
5
6
7
100 nF capacitance needs to be provided between VDDA/VSSA pair.
200 μF capacitance must be connected between VDDR and VSS12
.
VDD12 cannot be used to drive any external component.
Each VDD12/VSS12 supply pair should have a 10 μF capacitor. Absolute combined maximum capacitance is 40 μF.
VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC
.
100 nF capacitance needs to be provided between each VDD/VSS pair
Full electrical specification cannot be guaranteed when voltage drops below 3.0V. In particular, ADC electrical
characteristics and I/O’s DC electrical specification may not be guaranteed.
When voltage drops below VLVDHVL device is reset.
8
9
VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and
VSSMC) unless otherwise noted.
VDDE_C should not be less than VDDA
.
10 Guaranteed by device validation
Table 10. Recommended Operating Conditions (5.0 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
1
VDDA
SR Voltage on VDDA pin (ADC reference) with respect
+4.5
+3.0
+5.5
+5.5
V
to ground (VSS
)
Voltage drop2
Relative to VDD VDD-0.1
VSS-0.1
VDD+0.1
VSS+0.1
VSSA
SR Voltage on VSSA (ADC reference) pin with respect
VSS
V
V
V
V
VDDPLL CC Voltage on VDDPLL (1.2 V PLL supply) pin with
respect to ground (VSSPLL
1.08
VSS-0.1
+4.5
1.32
)
VSSPLL SR Voltage on VSSMC (stepper motor supply ground)
pin with respect to VSS
VSS+0.1
3
VDDR
SR Voltage on VDDR pin (regulator supply) with
respect to ground (VSSR
+5.5
+5.5
)
Voltage drop2
+3.0
Relative to VDD VDD-0.1
VSS-0.1
VDD+0.1
VSS+0.1
VSSR
SR Voltage on VSSR (regulator ground) pin with
respect to VSS
V
V
4,5
VDD12
CC Voltage on VDD12 pin with respect to ground
1.08
1.4
(VSS12
)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
42
Freescale Semiconductor
Electrical Characteristics
Table 10. Recommended Operating Conditions (5.0 V) (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS12
CC Voltage on VSS12 pin with respect to VSS
VSS-0.1
+4.5
VSS+0.1
+5.5
V
V
6,7
VDD
SR Voltage on VDD pins (VDDE_A, VDDE_B,
VDDE_C, VDDE_E, VDDMA, VDDMB, VDDMC)
Voltage drop2
with respect to ground (VSS
)
8
VSS
SR I/O supply ground
0
0
V
V
VDDE_A SR Voltage on VDDE_A (I/O supply) pin with respect
to ground (VSSE_A
+4.5
+5.5
)
VDDE_B SR Voltage on VDDE_B (I/O supply) pin with respect
to ground (VSSE_B
+4.5
+4.5
+4.5
+4.5
+4.5
+4.5
0
+5.5
+5.5
V
V
V
V
V
V
V
V
)
9
VDDE_C SR Voltage on VDDE_C (I/O supply) pin with respect
to ground (VSSE_C
)
VDDE_E SR Voltage on VDDE_E (I/O supply) pin with respect
to ground (VSSE_E
+5.5
)
VDDMA SR Voltage on VDDMA (stepper motor supply) pin
with respect to ground (VSSMA
+5.5
)
VDDMB SR Voltage on VDDMB (stepper motor supply) pin
with respect to ground (VSSMB
+5.5
)
VDDMC SR Voltage on VDDMC (stepper motor supply) pin
with respect to ground (VSSMC
+5.5
)
VSSOSC SR Voltage on VSSOSC (oscillator ground) pin with
respect to VSS
0
VLCD
SR Voltage on VLCD (LCD supply) pin with respect to
VSS
0
VDDE_A +0.3
TVDD
TA
SR VDD slope to ensure correct power up10
0.25
+105
+105
+150
V/µs
°C
SR Ambient temperature under bias
-40
-40
-40
TJ
SR Junction temperature under bias
1
2
100 nF capacitance needs to be provided between VDDA/VSSA pair.
Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical
characteristics may not be guaranteed below 4.5 V during the voltage drop sequence.
3
4
5
6
7
8
200 μF capacitance must be connected between VDDR and VSS12
VDD12 cannot be used to drive any external component.
.
Each VDD12/VSS12 supply pair should have a 10 μF capacitor. Absolute combined maximum capacitance is 40 μF.
VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC
.
100 nF capacitance needs to be provided between each VDD/VSS pair
VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and
VSSMC) unless otherwise noted.
9
VDDE_C should not be less than VDDA
.
10 Guaranteed by device validation
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
43
Electrical Characteristics
3.2
Thermal Characteristics
1
Table 11. Thermal Characteristics for 144-pin LQFP
Symbol
RθJA
Parameter
Conditions
Value
Unit
CC Junction to Ambient Natural Convection2
CC Junction to Ambient Natural Convection2
CC Junction to Ambient2
Single layer board - 1s
Four layer board - 2s2p
50
41
41
°C/W
°C/W
°C/W
RθJA
RθJMA
@200 ft./min., single layer
board - 1s
RθJMA
CC Junction to Ambient2
@200 ft./min., four layer
board- 2s2p
35
°C/W
RθJB
RθJCtop
ΨJT
CC Junction to Board3
CC Junction to Case4
29
10
2
°C/W
°C/W
°C/W
CC Junction to Package Top Natural
Convection5
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3
4
5
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
1
Table 12. Thermal Characteristics for 176-pin LQFP
Symbol
RθJA
Parameter
Conditions
Value
Unit
CC Junction to Ambient Natural Convection2
CC Junction to Ambient Natural Convection2
CC Junction to Ambient2
Single layer board - 1s
Four layer board - 2s2p
43
35
35
°C/W
°C/W
°C/W
RθJA
RθJMA
@200 ft./min., single layer
board - 1s
RθJMA
CC Junction to Ambient2
@200 ft./min., Four layer
board - 2s2p
30
°C/W
RθJB
RθJCtop
ΨJT
CC Junction to Board3
CC Junction to Case (Top)4
24
9
°C/W
°C/W
°C/W
CC Junction to Package Top Natural
Convection5
2
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3
4
5
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
44
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimate of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
* P )
Eqn. 1
J
A
θJA
D
where:
T = ambient temperature for the package ( C)
o
A
o
R
= junction to ambient thermal resistance ( C/W)
θJA
P = power dissipation in the package (W)
D
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a
four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance
is not a constant. The thermal resistance depends on the:
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit
board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components are well separated
Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the
ambient temperature varies widely within the application. For many natural convection and especially closed box applications,
the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the
device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R
* P )
Eqn. 2
J
B
θJB
D
where:
o
T = board temperature for the package perimeter ( C)
B
o
R
= junction-to-board thermal resistance ( C/W) per JESD51-8S
θJB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction
temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to
a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal
resistance:
R
= R
+ R
θCA
Eqn. 3
θJA
θJC
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
45
Electrical Characteristics
where:
o
R
R
R
R
= junction to ambient thermal resistance ( C/W)
θJA
θJC
θCA
θJC
o
= junction to case thermal resistance ( C/W)
o
= case to ambient thermal resistance ( C/W)
s device related and is not affected by other factors. The thermal environment can be controlled to change the
case-to-ambient thermal resistance, R
. For example, change the air flow around the device, add a heat sink, change the
θCA
mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding
the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat
sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the
junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the
thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple
estimations and for computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization
parameter (Ψ ) to determine the junction temperature by measuring the temperature at the top center of the package case using
JT
the following equation:
T = T + (Ψ x P )
Eqn. 4
J
T
JT
D
where:
o
T = thermocouple temperature on top of the package ( C)
T
o
Ψ = thermal characterization parameter ( C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests
on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from
the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling
effects of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
Middlefield Rd.
CA 94043
805 East
Mountain View,
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
46
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.3
EMI (Electromagnetic Interference) Characteristics
1
Table 13. EMI Testing Specifications
Value
typ
Symbol
Parameter
Unit
min
max
—
SR
SR
SR
SR
SR
SR
Scan Range
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MHz
MHz
V
—
—
—
—
—
Operating Frequency
VDD12, VDDPLL Operating Voltages
VDD, VDDA Operating Voltages
Maximum Amplitude
V
dBuV
oC
Operating Temperature
1
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03.
3.4
Power Management
3.4.1
Voltage Regulator Electrical Characteristics
The internal voltage regulator requires an external NPN (BCP56 or BCP68) ballast to be connected as shown in Figure 5 as well
as an external capacitance (C ) to be connected to the device in order to provide a stable low voltage digital supply to the
REG
device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit
the serial inductance of the board to less than 15 nH.
For the MPC5606S microcontroller , 10 µF should be placed between each of the three V
/V
supply pairs and also
DD12 SS12
between the V
/V
pair. Additionally, 200 μF should be placed between the V
pin and the adjacent V pin.
DDPLL SSPLL
DDR SS
V
= 3.0 V to 3.6 V / 4.5 V to 5.5 V, T = -40 to 105 °C, unless otherwise specified.
A
DDR
V
DDR
VRC_CTRL
V
DD12
Figure 5. External NPN Ballast Connections
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
47
Electrical Characteristics
1
Table 14. Voltage Regulator Electrical Characteristics
No.
Symbol
Parameter Conditions
Min
Max Unit
1
VDDR SR Power supply
3.0
5.5
V
2
3
TJ
SR Junction temperature
CC Current consumption
-40
—
150
°C
IREG
Reference included,
@ 55 °C No load
@ Full load
mA
2
11
4
5
IL
CC Output current capacity
DC load current
—
—
200
mA
V
VDD12 CC Output voltage (value @ IL = 0 @ 27°C)
Pre-trimming sigma
< 7 mV
1.330
Post-trimming
Post-trimming
1.270 1.280
Output voltage (value @ IL = Imax)
1.145
10 * 4
—
6
SR External decoupling/stability capacitor
4 capacitances of
10 µF each
µF
ESR of external cap
0.05
0.2
0.2
1
ohm
ohm
1 bond wire R + 1
pad R
7
8
LBOND CC Bonding Inductance for Bipolar Base Control pad
0
15
nH
dB
CC Power supply rejection
@ DC @ no load
@ 200 kHz @ no load
@ DC @ 400 mA
Cload = 10 µF * 4
—
-30
-100
-30
@ 200 kHz @ 400 mA
-30
9
CC
CC
Load current transient
Cload = 10 µF * 4
Cload = 10 µF * 4
—
—
10% to 90%
of IL (max) in
100 ns
10
tSU
Start-up time after input supply stabilizes2
500
µs
1
2
All values in this table are PRELIMINARY.
Time after the input supply to the voltage regulator has ramped up (VDDR) and the voltage regulator has asserted
the Power OK signal.
3.4.2
Voltage monitor electrical characteristics
The device implements a Power On Reset module to ensure correct power-up initialization, as well as four low voltage detectors
to monitor the V and the V voltage while device is supplied:
DD
DD12
•
•
•
•
•
POR monitors V during the power-up phase to ensure device is maintained in a safe reset state
DD
LVDHV3 monitors V to ensure device reset below minimum functional supply
DD
LVDHV5 monitors V when application uses device in the 5.0V ± 10% range
DD
LVDLVCOR monitors power domain No. 1
LVDLVBKP monitors power domain No. 0
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
48
Freescale Semiconductor
Electrical Characteristics
Table 15. Low voltage monitor electrical characteristics
Value2
Symbol
Parameter
Conditions1
Unit
Min
Typ Max
VPORH
CC Power-on reset threshold
TA = 25°C,
after trimming
1.5
—
—
—
—
—
—
—
—
2.7
2.8
V
VLVDHV3H CC LVDHV3 low voltage detector high threshold
VLVDHV3L CC LVDHV3 low voltage detector low threshold
VLVDHV5H CC LVDHV5 low voltage detector high threshold
VLVDHV5L CC LVDHV5 low voltage detector low threshold
VLVDLVCORH CC LVDLVCOR low voltage detector high threshold
VLVDLVCORL CC LVDLVCOR low voltage detector low threshold
2.7
—
—
4.37
—
4.2
—
1.185
—
1.095
1
2
VDD = 3.3V 10% / 5.0V 10%, TA = -40 / +105°C, unless otherwise specified
All values need to be confirmed during device validation.
3.4.3
Low voltage domain power consumption
Table 16 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 16. DC electrical characteristics
Value2
Symbol
Parameter
Conditions1
Unit
Min
Typ
Max
IDDMAX SR Maximum current
—
—
—
4.5
—
—
—
—
—
—
130
30
135 mA
3
IDDRUN
CC RUN mode current
—
—
12
—
—
—
—
—
mA
mA
mA
mA
µA
IDDWAIT CC WAIT mode current
IDDHALT CC HALT mode current
IDDSTOP CC STOP mode current
IDDSTOP CC STOP mode current
IDDSTOP CC STOP mode current
IDDSTDBY CC STANDBY mode current
IDDSTDBY CC STANDBY mode current
—
IRC 16 MHz oscillator off
HPVREG off
1.5
800
4
IRC 16 MHz oscillator on
IRC 16 MHz oscillator off
IRC 16 MHz oscillator on
mA
µA
29
300
µA
1
2
3
VDD = 3.3V 10% / 5.0V 10%, TA = -40 / +125 °C
All values need to be confirmed during device validation.
Value is for maximum peripherals turned on. May vary significantly based on different configurations, active
peripherals, operating frequency, etc.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
49
Electrical Characteristics
3.5
DC Electrical Specifications
3.6
I/O Pad Electrical Characteristics
3.6.1
I/O Pad Types
The device provides four main I/O pad types depending of the associated alternate functions:
•
•
•
Slow pads are the most common pads, providing a good compromise between transition time and low electromagnetic
emission.
Medium pads provide fast enough transition for the serial communication channels with controlled current to reduce
electromagnetic emission.
Fast pads provide maximum speed. There are used for improved NEXUS debugging capability.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
3.6.2
I/O Input DC Characteristics
Table 17 provides input DC electrical characteristics as described in Figure 6.
V
IN
V
DD
V
IH
V
HYS
V
IL
V
INTERNAL
(SIU register)
Figure 6. I/O Input DC Electrical Characteristics Definition
Table 17. I/O Input DC Electrical Characteristics
Conditions1
Value2
Typ
Symbol
Parameter
Unit
Min
Max
VIH
VIL
SR Input high level CMOS
Schmitt Trigger
0.65VDD
VDD+0.4
V
SR Input low level CMOS
Schmitt Trigger
-0.4
0.35VDD
VHYS
CC3 Input hysteresis CMOS
Schmitt Trigger
0.1VDD
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
50
Freescale Semiconductor
Electrical Characteristics
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C.
All values need to be confirmed during device validation.
Parameter value guaranteed by design.
3.6.3
I/O Output DC Characteristics
The following tables provide DC characteristics for bidirectional pads:
•
•
•
•
Table 18 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 19 provides output driver characteristics for I/O pads when in SLOW configuration.
Table 20 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 21 provides output driver characteristics for I/O pads when in FAST configuration.
Table 18. I/O Pull-up/Pull-down DC Electrical Characteristics
Value2
Symbol
Parameter
Conditions1
Unit
Min Typ Max
|IWPU
|IWPD
|
|
CC Weak pull-up current absolute value
CC Weak pull-down current absolute value
10
10
—
—
µA
1
2
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified.
All values need to be confirmed during device validation.
Table 19. SLOW Configuration Output Buffer Electrical Characteristics
Value2
Symbol
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC Output high level
SLOW configuration
Push Pull, IOH = -2mA,
VDD = 5.0V 10%, ipp_hve = 0
(recommended)
0.8VDD
V
Push Pull, IOH = -2mA,
0.8VDD
VDD = 5.0V 10%, ipp_hve = 13
Push Pull, IOH = -1mA,
VDD = 3.3V 10%, ipp_hve = 1
(recommended)
VDD-0.
8
VOL CC Output low level
SLOW configuration
Push Pull, IOL = 2mA,
VDD = 5.0V 10%, ipp_hve = 0
(recommended)
0.1VDD
V
Push Pull, IOL = 2mA,
0.1VDD
0.5
VDD = 5.0V 10%, ipp_hve = 13
Push Pull, IOL = 1mA,
VDD = 3.3V 10%, ipp_hve = 1
(recommended)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
51
Electrical Characteristics
Table 19. SLOW Configuration Output Buffer Electrical Characteristics (continued)
Value2
Typ
Symbol
Parameter
Conditions1
Unit
Min
Max
Ttr CC4 Output transition time output pin5 CL = 25pF,
506
ns
SLOW configuration
VDD = 5.0V 10%, ipp_hve = 0
CL = 50pF,
1006
1254
406
506
754
2
V
DD = 5.0V 10%, ipp_hve = 0
CL = 100pF,
VDD = 5.0V 10%, ipp_hve = 0
CL = 25pF,
VDD = 3.3V 10%, ipp_hve = 1
CL = 50pF,
VDD = 3.3V 10%, ipp_hve = 1
CL = 100pF,
VDD = 3.3V 10%, ipp_hve = 1
ΔItr50 CC4 Current slew at CL = 50pF
recommended configuration at
VDD = 5.0V 10%, ipp_hve = 0,
VDD = 3.3V 10%, ipp_hve = 1
mA/ns
SLOW configuration
VDD = 5.0V 10%, ipp_hve = 1
7
1
2
3
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified
All values need to be confirmed during device validation.
This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are
configured in input or in high impedance state.
4
5
6
Data based on characterization results, not tested in production
CL calculation should include device and package capacitances (CPKG < 5pF).
Data based on simulation results, not tested in production
Table 20. MEDIUM Configuration Output Buffer Electrical Characteristics
Value2
Symbol
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC Output high level
MEDIUM configuration
Push Pull, IOH = -2mA,
VDD = 5.0V 10%, ipp_hve = 0
(recommended)
0.8VDD
V
Push Pull, IOH = -1mA,
V
0.8VDD
DD = 5.0V 10%, ipp_hve = 13
Push Pull, IOH = -1mA,
VDD = 3.3V 10%, ipp_hve = 1
(recommended)
VDD-0.8
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
52
Freescale Semiconductor
Electrical Characteristics
Table 20. MEDIUM Configuration Output Buffer Electrical Characteristics (continued)
Value2
Typ
Symbol
Parameter
Conditions1
Unit
Min
Max
VOL CC Output low level
MEDIUM configuration
Push Pull, IOL = 2mA,
VDD = 5.0V 10%, ipp_hve = 0
(recommended)
0.1VDD
V
Push Pull, IOL = 1mA,
0.1VDD
0.5
VDD = 5.0V 10%, ipp_hve = 13
Push Pull, IOL = 1mA,
VDD = 3.3V 10%, ipp_hve = 1
(recommended)
Ttr CC4 Output transition time output CL = 25pF,
10
20
40
12
25
40
7
ns
pin5
VDD = 5.0V 10%, ipp_hve = 0
MEDIUM configuration
CL = 50pF,
VDD = 5.0V 10%, ipp_hve = 0
CL = 100pF,
VDD = 5.0V 10%, ipp_hve = 0
CL = 25pF,
VDD = 3.3V 10%, ipp_hve = 1
CL = 50pF,
VDD = 3.3V 10%, ipp_hve = 1
CL = 100pF,
VDD = 3.3V 10%, ipp_hve = 1
ΔItr50 CC4 Current slew at CL = 50pF
recommended configuration at
VDD = 5.0V 10%, ipp_hve = 0
VDD = 3.3V 10%, ipp_hve = 1
mA/ns
MEDIUM configuration
VDD = 5.0V 10%, ipp_hve = 1
16
1
2
3
VDD = 3.3V 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified
All values need to be confirmed during device validation.
This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are
configured in input or in high impedance state.
4
5
Data based on characterization results, not tested in production
CL calculation should include device and package capacitance (CPKG < 5pF).
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
53
Electrical Characteristics
Table 21. FAST Configuration Output Buffer Electrical Characteristics
Value2
Typ
Symbol
Parameter
Conditions1
Unit
Min
Max
VOH CC Output high level
FAST configuration
Push Pull, IOH = -14mA,
VDD = 5.0V 10%, ipp_hve = 0
(recommended)
0.8VDD
V
Push Pull, IOH = -7mA,
0.8VDD
VDD = 5.0V 10%, ipp_hve = 13
Push Pull, IOH = -11mA,
VDD = 3.3V 10%, ipp_hve = 1
(recommended)
VDD-0.8
VOL CC Output low level
FAST configuration
Push Pull, IOL = 14mA,
VDD = 5.0V 10%, ipp_hve = 0
(recommended)
0.1VDD
V
Push Pull, IOL = 7mA,
0.1VDD
0.5
VDD = 5.0V 10%, ipp_hve = 13
Push Pull, IOL = 11mA,
VDD = 3.3V 10%, ipp_hve = 1
(recommended)
Ttr CC4 Output transition time output CL = 25pF,
4
6
ns
pin5
VDD = 5.0V 10%, ipp_hve = 0
FAST configuration
CL = 50pF,
VDD = 5.0V 10%, ipp_hve = 0
CL = 100pF,
VDD = 5.0V 10%, ipp_hve = 0
12
4
CL = 25pF,
VDD = 3.3V 10%, ipp_hve = 1
CL = 50pF,
7
VDD = 3.3V 10%, ipp_hve = 1
CL = 100pF,
VDD = 3.3V 10%, ipp_hve = 1
12
55
40
100
4
ΔItr50 CC Current slew at CL = 50pF
VDD = 5.0V 10%, ipp_hve = 0
(recommended configuration)
mA/n
s
FAST configuration
VDD = 3.3V 10%, ipp_hve = 1
(recommended configuration)
VDD = 5.0V 10%, ipp_hve = 1
1
VDD = 3.3V 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified
All values need to be confirmed during device validation.
2
3
This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are
configured in input or in high impedance state.
4
5
Data based on characterization results, not tested in production
CL calculation should include device and package capacitance (CPKG < 5pF).
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
54
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.6.4
I/O Pad Current Specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V /V supply pair as
DD SS
described in Table 22.
Table 23 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I
maximum value.
AVGSEG
In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain
below the I
maximum value.
DYNSEG
Table 22. I/O Supply Segment
Supply segment
Package
A1
B2
C3,4
D5
E6
144 LQFP
176 LQFP
pins 1 - 21
pins 113 - 144
pins 22 - 52
pins 53 - 72
pins 73 - 102
pins 103 - 112
pins 1 - 21
pins 22 - 68
pins 69 - 88
pins 89 - 118
pins 119 - 142
pins 143 - 176
1
2
3
4
5
6
LCD pad segment containing pad supplies VDDE_A
Misc. pad segment containing pad supplies VDDE_B
ADC pad segment containing pad supplies VDDE_C
ADC VDDA and VDDE_C should be at the same voltage level
Stepper Motor pad segment containing I/O supplies VDDMA, VDDMB, VDDMC
Misc pad segment containing pad supplies VDDE_E
Table 23. I/O Consumption
Value2
Symbol
Parameter
Conditions1
Unit
Min Typ Max
ISWTSLW CC3 Dynamic I/O current for SLOW
configuration
CL = 25pF,
VDD = 5.0V 10%, ipp_hve = 0
20 mA
CL = 25pF,
16
VDD = 3.3V 10%, ipp_hve = 1
ISWTMED CC3 Dynamic I/O current for MEDIUM
configuration
CL = 25pF,
VDD = 5.0V 10%, ipp_hve = 0
29 mA
17
CL = 25pF,
VDD = 3.3V 10%, ipp_hve = 1
3
ISWTFST CC3 Dynamic I/O current for FAST
CL = 25pF,
VDD = 5.0V 10%, ipp_hve = 0
110 mA
50
configuration
CL = 25pF,
VDD = 3.3V 10%, ipp_hve = 1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
55
Electrical Characteristics
Symbol
Table 23. I/O Consumption (continued)
Conditions1
Value2
Parameter
Unit
Min Typ Max
IRMSSLW CC RMS I/O current for SLOW
configuration
CL = 25 pF, 2 MHz
VDD = 5.0 V 10%, ipp_hve = 0
2.33 mA
CL = 25 pF, 4 MHz
3.23
VDD = 5.0 V 10%, ipp_hve = 0
CL = 100 pF, 2 MHz
6.64
VDD = 5.0 V 10%, ipp_hve = 0
CL = 25 pF, 2 MHz
1.63
VDD = 3.3 V 10%, ipp_hve = 1
CL = 25 pF, 4 MHz
2.33
VDD = 3.3 V 10%, ipp_hve = 1
CL = 100 pF, 2 MHz
4.74
VDD = 3.3 V 10%, ipp_hve = 1
IRMSMED CC Average I/O current for SLOW
configuration
CL = 25 pF, 2 MHz
VDD = 5.0 V 10%, ipp_hve = 0
6.63 mA
13.43
18.34
5.03
CL = 25 pF, 4 MHz
VDD = 5.0 V 10%, ipp_hve = 0
CL = 100 pF, 2 MHz
VDD = 5.0 V 10%, ipp_hve = 0
CL = 25 pF, 2 MHz
VDD = 3.3 V 10%, ipp_hve = 1
CL = 25 pF, 4 MHz
8.53
VDD = 3.3 V 10%, ipp_hve = 1
CL = 100 pF, 2 MHz
VDD = 3.3 V 10%, ipp_hve = 1
11.04
22.03 mA
33.03
56.04
14.03
20.03
25.04
IRMSFST CC Average I/O current for SLOW
configuration
CL = 25 pF, 2 MHz
VDD = 5.0V 10%, ipp_hve = 0
CL = 25 pF, 4 MHz
VDD = 5.0V 10%, ipp_hve = 0
CL = 100 pF, 2 MHz
VDD = 5.0V 10%, ipp_hve = 0
CL = 25 pF, 2 MHz
VDD = 3.3V 10%, ipp_hve = 1
CL = 25 pF, 4 MHz
VDD = 3.3 V 10%, ipp_hve = 1
CL = 100 pF, 2 MHz
VDD = 3.3 V 10%, ipp_hve = 1
IDYNSEG SR Sum of all the dynamic and static I/O VDD = 5.0 V 10%, ipp_hve = 0
current within a supply segment
110 mA
65
V
DD = 3.3 V 10%, ipp_hve = 1
IAVGSEG SR Sum of all the static I/O current within VDD = 5.0 V 10%, ipp_hve = 0
a supply segment
70 mA
65
V
DD = 3.3 V 10%, ipp_hve = 1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
56
Freescale Semiconductor
Electrical Characteristics
1
2
3
4
VDD = 3.3 V 10% / 5.0 V ± 10%, TA = -40 to +105°C, unless otherwise specified
All values need to be confirmed during device validation.
Data based on simulation results, not tested in production
Data based on characterization results, not tested in production
3.7
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
Figure 7. Start-up reset requirements
V
DD
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
device start-up phase
T
RSTREM
Figure 8. Noise filtering on reset signal
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
57
Electrical Characteristics
Table 24. Reset electrical characteristics
Value2
Typ
Symbol
Parameter
Conditions1
Unit
Min
Max
VIH
VIL
SR Input High Level CMOS
0.65VDD
VDD+0.4
V
V
V
V
Schmitt Trigger
SR Input low Level CMOS
Schmitt Trigger
-0.4
0.35VDD
VHYS CC3 Input hysteresis CMOS
Schmitt Trigger
0.1VDD
VOL
CC4 Output low level
Push Pull, IOL = 2mA,
0.1VDD
VDD = 5.0V 10%, ipp_hve = 0
(recommended)
Push Pull, IOL = 1mA,
V
0.1VDD
0.5
DD = 5.0V 10%, ipp_hve = 15
Push Pull, IOL = 1mA,
VDD = 3.3V 10%, ipp_hve = 1
(recommended)
Ttr
CC4 Output transition time output CL = 25pF,
10
20
40
12
25
40
ns
pin6
VDD = 5.0V 10%, ipp_hve = 0
MEDIUM configuration
CL = 50pF,
VDD = 5.0V 10%, ipp_hve = 0
CL = 100pF,
VDD = 5.0V 10%, ipp_hve = 0
CL = 25pF,
VDD = 3.3V 10%, ipp_hve = 1
CL = 50pF,
VDD = 3.3V 10%, ipp_hve = 1
CL = 100pF,
VDD = 3.3V 10%, ipp_hve = 1
WFRST SR RESET Input Filtered Pulse
WNFRS SR RESET Input Not Filtered
-
40
-
ns
ns
1000
-
Pulse
T
|IWPU
|
CC4 Weak pull-up current absolute
value
10
µA
1
2
3
4
5
VDD = 3.3V 10% / 5.0V 10%, TA = -40 / +105oC, unless otherwise specified
All values need to be confirmed during device validation.
Data based on characterization results, not tested in production
Guaranteed by design simulation.
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
the reference manual).
6
CL calculation should include device and package capacitance (CPKG < 5pF).
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
58
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.8
Main Oscillator Electrical Characteristics
The device provides an oscillator/resonator driver. Figure 9 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
EXTAL
C
C
L
EXTAL
R
P
XTAL
L
DEVICE
V
DD
I
R
EXTAL
XTAL
DEVICE
XTAL
DEVICE
Figure 9. Crystal Oscillator and Resonator Connection Scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
59
Electrical Characteristics
V
DD
V
DDMIN
V
XTAL
1/f
XOSCHS
V
XOSCHS
90%
10%
V
XOSCHSOP
T
valid internal clock
XOSCHSSU
Figure 10. Main Oscillator Electrical Characteristics
Table 25. Main Oscillator Electrical Characteristics
Value2
Symbol
Parameter
Conditions1
Unit
Min
Typ
Max
fXOSCHS
SR Oscillator frequency
4.0
—
16.0
7.38
MHz
gmXOSCHS CC3 Oscillator
VDD = 3.3 V 10%,
4.11
5.59
mA/V
transconductance
OSCILLATOR_MARGIN = 0
VDD = 5.0 V 10%,
OSCILLATOR_MARGIN = 0
3.67
4.93
4.54
2.51
1.68
4.74
3.02
5.04
6.70
6.22
—
6.73
8.86
8.31
—
VDD = 3.3 V 10%,
OSCILLATOR_MARGIN = 1
VDD = 5.0 V 10%,
OSCILLATOR_MARGIN = 1
VXOSCHS CC3 Oscillation amplitude
fOSC = 4 MHz,
VDD = 3.3 V 10%
V
fOSC = 16 MHz,
—
—
VDD = 3.3 V 10%
fOSC = 4 MHz,
—
—
VDD = 5.0 V 10%
fOSC = 16 MHz,
—
—
VDD = 5.0 V 10%
VXOSCHSOP CC3 Oscillation operating
point
VDD = 3.3 V 10% VEXTAL
VXTAL
0.894
0.894
0.904
0.904
—
—
—
—
1.143
1.146
1.166
1.169
V
VDD = 5.0 V 10% VEXTAL
VXTAL
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
60
Freescale Semiconductor
Electrical Characteristics
Table 25. Main Oscillator Electrical Characteristics (continued)
Value2
Symbol
Parameter
Conditions1
Unit
Min
Typ
Max
IXOSCHS
CC3 Oscillator consumption
fOSC = 4 MHz
OSC = 16 MHz
—
—
—
—
—
—
2.43
2.52
6.0
mA
f
TXOSCHSSU CC3 Oscillator start-up time
fOSC = 4 MHz,
ms
OSCILLATOR_MARGIN = 0
fOSC = 16 MHz,
—
—
1.8
OSCILLATOR_MARGIN = 1
VIH
VIL
SR Input high level CMOS
Schmitt Trigger
Oscillator bypass mode
0.65VDD
-0.4
VDD+0.4
0.35VDD
V
V
SR Input low level CMOS
Schmitt Trigger
Oscillator bypass mode
1
2
3
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to +105 °C, unless otherwise specified
All values need to be confirmed during device validation.
Data based on simulation results, not tested in production
3.9
Low Power Oscillator Electrical Characteristics
The device provides a low power oscillator/resonator driver.
PC[15]
PC[15]
PC[14]
C
X
R
F
PC[14]
C
Y
DEVICE
DEVICE
Figure 11. Crystal Oscillator and Resonator Connection Scheme
NOTE
PC[14]/PC[15] must not be directly used to drive external circuits.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
61
Electrical Characteristics
V
DD
V
DDMIN
V
XTAL
1/f
XOSCLP
V
XOSCLP
90%
10%
T
valid internal clock
XOSCLPSU
Figure 12. Low Power Oscillator Electrical Characteristics
Table 26. Low Power Oscillator Electrical Characteristics
Value2
Typ
Symbol
Parameter
Conditions1
Unit
Min
Max
fXOSCLP
SR Oscillator frequency
32
-
40
1.74
1.74
5
kHz
V
VXOSCLP CC3 Oscillation amplitude
V
DD=3.3V±10%,
1.12
1.12
1.33
1.37
VDD=5.0V±10%,
IXOSCLP
TXOSCLPSU CC3 Oscillator start-up time
CC3 Oscillator consumption
µA
s
2
VIH
SR Input high level CMOS
Schmitt Trigger
Oscillator bypass mode 0.65VDD
Oscillator bypass mode -0.4
VDD+0.4
V
VIL
SR Input low level CMOS
Schmitt Trigger
0.35VDD
V
1
2
3
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to +105 °C, unless otherwise specified
All values need to be confirmed during device validation.
Granted by device validation
3.10 FMPLL Electrical Characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
62
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 27. FMPLL Electrical Characteristics
Value2
Unit
Symbol
Parameter
Conditions1
Min
Typ
Max
fPLLIN
ΔPLLIN
SR PLL reference clock3
4
64 MHz
SR PLL reference clock duty cycle3
40
16
60
%
fPLLOUT CC4 PLL output clock frequency
fCPU
CC4 System clock frequency
64 MHz
645 MHz
TLOCK CC4 PLL lock time
Stable oscillator (fPLLIN = 16 MHz)
fPLLIN = 16 MHz (resonator)
fPLLIN = 16 MHz (resonator)
TA = 25°C
200
500
1.5
4
µs
ps
ΔTPKJIT CC4 PLL jitter (pk to pk)
ΔTLTJIT CC4 PLL long term jitter
ns
IPLL
CC6 Oscillator consumption
mA
1
2
3
VDDPLL = 1.2 V 10%, TA = -40 to +105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
PLLIN clock retrieved directly from XOSCHS clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN
Data based on device simulation.
.
4
5
6
fCPU 64 MHz can be achieved only at up to 105 °C
Data based on characterization results, not tested in production
3.11 Main RC Oscillator Electrical Characteristics
The device provides a 16 MHz internal RC oscillator. This is used as the default clock at the power-up of the device.
Table 28. Main RC Oscillator Electrical Characteristics
Value2
Symbol
Parameter
Conditions1
Unit
Min
Typ Max
fRCM
CC3 RC oscillator high frequency
TA = 25 °C, trimmed
TA = 25 °C, trimmed
16
MHz
IRCMRUN CC3 RC oscillator high frequency current in
running mode
200 µA
IRCMPWD CC3 RC oscillator high frequency current in power TA = 25 °C
down mode
10
+1
+5
µA
%
ΔRCMTRI CC3 RC oscillator precision after trimming of fRC TA = 25 °C
-1
-5
M
ΔRCMVAR CC4 RC oscillator variation in temperature and
supply with respect to fRC at TA = 55 °C in
high-frequency configuration
%
1
2
3
4
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to +105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
Guaranteed by device simulation, not tested in production
Guaranteed by device characterization, not tested in production
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
63
Electrical Characteristics
3.12 Low Power RC Oscillator Electrical Characteristics
The device provides a low power internal RC oscillator. This can be used as the reference clock for the RTC module.
Table 29. Low Power RC Oscillator Electrical Characteristics
Value2
Symbol
Parameter
Conditions1
Unit
Min
Typ Max
fRCL
IRCL
CC3 RC oscillator low frequency
TA = 25 °C, trimmed
TA = 25 °C, trimmed
128
kHz
µA
%
CC3 RC oscillator low frequency current
5
ΔRCLTRIM CC3 RC oscillator precision after trimming of fRCL TA = 25 °C
ΔRCLVAR3 CC3 RC oscillator variation in temperature and
High frequency
-2
+2
-10
+10
%
supply with respect to fRC at TA = 55 °C in high configuration
frequency configuration
1
2
3
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to +105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
Guaranteed by device simulation, not tested in production
3.13 Flash Memory Electrical Characteristics
Table 30. Program and Erase Specifications
Typical
Value1
Initial
Symbol
Parameter
Min Value
Max3
Unit
Max2
Tdwprogram Double Word (64 bits) Program Time4
T16kpperase 16 KB Block Pre-program and Erase Time
T32kpperase 32 KB Block Pre-program and Erase Time
T128kpperase 128 KB Block Pre-program and Erase Time
—
—
—
—
22
500
600
1300
500
μs
ms
ms
ms
5000
5000
7500
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
3
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program & erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
64
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 31. Flash Module Life
Value
Unit
Typ
Symbol
Parameter
Conditions
Min
P/E
Number of program/erase cycles per block for
16 Kbyte blocks over the operating
temperature range (TJ)
—
—
—
100,000
10,000
1,000
—
cycles
P/E
P/E
Number of program/erase cycles per block for
32 Kbyte blocks over the operating
temperature range (TJ)
100,000 cycles
(TBD)
Number of program/erase cycles per block for
128 Kbyte blocks over the operating
temperature range (TJ)
100,000 cycles
(TBD)
Retention Minimum data retention at 85 °C average
ambient temperature1
Blocks with 0 - 1,000 P/E
cycles
20
10
—
—
—
years
years
years
Blocks with 10,000 P/E
cycles
Blocks with 100,000 P/E
cycles
1 - 5
(TBD)
1
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
3.14 Analog to Digital Converter (ADC) Electrical Characteristics
The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
65
Electrical Characteristics
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = V
/ 1024
DDA
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
(LSB
V
)
ideal
in(A)
Offset Error OSE
Figure 13. ADC Characteristics and Error Definitions
3.14.1 Input Impedance and ADC Accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
66
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being
S
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330kΩ is obtained (R
=
S
EQ
1 / (fc*C ), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
S
partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external circuit
S
S
F
L
SW
AD
must be designed to respect the Equation 5:
Eqn. 5
R + R + R + R
+ R
S
F
L
SW
AD
1
2
--------------------------------------------------------------------------
V •
< -- LSB
A
R
EQ
Equation 5 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (R
SW
and R ) can be neglected with respect to external resistances.
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
C
S
A
F
P1
P2
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
Pin Capacitance (two contributions, C and C
P1
Sampling Capacitance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
)
P2
S
Figure 14. Input Equivalent Circuit (Precise Channels)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
67
Electrical Characteristics
EXTERNAL CIRCUIT
Filter
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Selection
Extended
Switch
Sampling
Source
R
Current Limiter
R
R
R
F
R
L
R
AD
SW2
S
SW1
C
S
C
V
C
F
C
C
P2
A
P1
P3
R
R
C
R
R
R
C
C
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions R
Sampling Switch Impedance
S
F
F
L
and R
)
SW2
SW
AD
P
SW1
Pin Capacitance (three contributions, C , C and C )
Sampling Capacitance
P1
P2
P3
S
Figure 15. Input Equivalent Circuit (Extended Channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are
F
P1
P2
initially charged at the source voltage V (refer to the equivalent circuit reported in Figure 14): A charge sharing phenomenon
A
is installed when the sampling phase is started (A/D switch close).
Voltage Transient on CS
V
CS
V
A
ΔV < 0.5 LSB
V
A2
1
2
τ1 < (RSW + RAD) CS << TS
V
A1
τ2 = RL (CS + CP1 + CP2)
T
t
S
Figure 16. Transient Behavior during Sampling Phase
In particular two different transient periods can be distinguished:
A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C
S
•
P1
P2
S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,
P2
P1
P
P1
P2
P
S
and the time constant is
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
68
Freescale Semiconductor
Electrical Characteristics
Eqn. 6
C • C
P
S
--------------------
) •
τ
= (R
+ R
1
SW
AD
C + C
P
S
Equation 6 can again be simplified considering only C as an additional worst condition. In reality, the transient is
S
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T
is always much longer than the internal time constant:
S
Eqn. 7
τ < (R
+ R
) • C « T
1
SW
AD
S
S
The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance
P1
P2
S
A1
according to Equation 8:
Eqn. 8
V
• (C + C + C ) = V • (C + C
)
A1
S
P1
P2
A
P1
P2
•
A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance
F
R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality
L
P2
S
P1
would be faster), the time constant is:
Eqn. 9
τ < R • (C + C + C
P1 P2
)
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time T , a constraints on R sizing is obtained:
S
L
Eqn. 10
10 • τ = 10 • R • (C + C + C ) < T
P1 P2 S
2
L
S
Of course, R shall be sized also according to the current limitation constraints, in combination with R (source
L
S
impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V
F
F
P1 P2
S
A2
(at the end of the charge transfer transient) will be much higher than V . Equation 11 must be respected (charge
A1
balance assuming now C already charged at V ):
S
A1
Eqn. 11
V
• (C + C + C + C ) = V • C + V • (C + C + C )
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to
F
F
provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of
S
A
F F
the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.
S
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
69
Electrical Characteristics
Analog Source Bandwidth (V )
A
T
≤ 2 R C (Conversion Rate vs. Filter Pole)
F F
C
Noise
f
= f (Anti-aliasing Filtering Condition)
0
F
2 f ≤ f (Nyquist)
0
C
f
0
f
Anti-Aliasing Filter (f = RC Filter pole)
Sampled Signal Spectrum (f = conversion Rate)
C
F
f
f
f
C
F
0
f
f
Figure 17. Spectral Representation of Input Signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),
0
F
according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater
C
0
than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T ,
C
C
S
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the
F
F
sampling time T , so the charge level on C cannot be modified by the analog signal source during the time in which the
S
S
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on C ; from the two charge balance equations above, it is simple to derive Equation 12 between the ideal and real sampled
S
voltage on C :
S
Eqn. 12
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A
P1
F
V
C
+ C + C + C
A2
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5V), assuming to accept a maximum error of
A
half a count, a constraint is evident on C value:
F
Eqn. 13
C
> 2048 • C
F
S
3.14.2 ADC Electrical Characteristics
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
70
Freescale Semiconductor
Electrical Characteristics
Table 32. ADC Electrical Characteristics
Conditions1
Value2
Typ
Symbol
Parameter
Unit
Min
Max
VSSA
SR Voltage on VSSA (ADC
reference) pin with
-0.1
0.1
V
3
respect to ground (VSS
)
VDDA
SR Voltage on VDDA pin
(ADC reference) with
VDD-0.1
VDD+0.1
V
respect to ground (VSS
)
VAINx
fADC
SR Analog input voltage4
VSSA-0.1
6
VDDA+0.1
32
V
MHz
µs
SR ADC analog frequency
tADC_PU SR ADC power up delay
tADC_S CC5 Sample time6
1.5
fADC = 32 MHz,
0.5
µs
ADC_conf_sample_input = 17
fADC = 6 MHz,
ADC_conf_sample_input =
127
21
tADC_C CC5 Conversion time7
fADC = 32 MHz,
ADC_conf_comp = 2
0.625
µs
pF
pF
pF
pF
kΩ
kΩ
kΩ
mA
CS
CC5 ADC input sampling
capacitance
3
3
CP1
CP2
CP3
CC5 ADC input pin
capacitance 1
CC5 ADC input pin
capacitance 2
1
CC5 ADC input pin
capacitance 3
1
RSW1 CC5 Internal resistance of
analog source
3
RSW2 CC5 Internal resistance of
analog source
2
RAD
CC5 Internal resistance of
analog source
0.1
10
IINJ
SR Input current Injection
Current injection on one ADC
input, different from the
converted one
-10
INL
CC5 Integral Non Linearity
No overload
-1.5
-1.0
-1.0
-1.0
1.5
1.0
1.0
1.0
LSB
LSB
LSB
LSB
DNL CC5 Differential Non Linearity No overload
OFS CC5 Offset error
GNE CC5 Gain error
After offset cancellation
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
71
Electrical Characteristics
Symbol
Table 32. ADC Electrical Characteristics (continued)
Value2
Typ
Parameter
Conditions1
Unit
Min
Max
TUEP CC5 Total Unadjusted Error for No overload
-2
2
LSB
LSB
precise channels, input
only pins
overload conditions on
adjacent channel
TUEX CC5 Total Unadjusted Error for No overload
extended channel,
-3
3
LSB
LSB
overload conditions on
adjacent channel
1
2
3
4
VDDA = 3.3 V 10% / 5.0 V 10%, TA = -40 to +105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSSA and VDDA limits, remaining on absolute maximum ratings, but the results of the conversion
will be clamped respectively to 0x000 or 0x3FF
5
6
Guaranteed by design
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
7
This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
3.15 AC Specifications
3.15.1 Pad AC Specifications
1
Table 33. Pad AC specifications (5.0 V, IPP_HVE=1)
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew3
(mA/ns)
Load drive
(pF)
Num
Pad
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
1
Slow
1.5
1.5
1.5
1.5
1
-
-
-
-
-
-
-
-
30
30
30
30
15
15
15
15
6
9
-
-
-
-
-
-
-
-
50
100
125
150
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
2
0.04
0.04
0.04
0.04
2.5
-
-
-
-
-
-
-
-
2
2
2
2
7
7
8
8
25
50
12
16
3
2
100
200
25
2
2
Medium
40
20
13
7
1
5
20
2.5
50
1
9
40
2.5
100
200
1
12
70
2.5
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
72
Freescale Semiconductor
Electrical Characteristics
Table 33. Pad AC specifications (5.0 V, IPP_HVE=1) (continued)
1
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew3
(mA/ns)
Load drive
(pF)
Num
Pad
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
3
Fast
1
1
1
1
1
-
-
-
-
-
-
-
6
6
6
6
5
-
1
1.5
3
-
-
-
-
-
-
4
6
-
-
-
-
-
-
-
-
-
-
-
-
100
80
40
25
50
-
18
18
18
18
10
-
-
-
-
-
-
-
55
55
55
55
25
-
25
50
12
16
4
100
200
25
5
4
5
Symmetric
1
Pull Up/Down
(5.5 V max)
-
5000
50
1
2
3
Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition
Slope at rising/falling edge
Data based on characterization results, not tested in production
1
Table 34. Pad AC specifications (3.3 V, IPP_HVE=0)
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew3
(mA/ns)
Load drive
(pF)
Num
Pad
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
1
2
3
Slow
3
3
3
3
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
40
40
40
40
15
15
15
15
6
4
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
40
50
75
100
12
25
40
70
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
2
0.01
0.01
0.01
0.01
2.5
2.5
2.5
2.5
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
25
50
10
14
2
2
2
100
200
25
2
2
Medium
Fast
40
20
13
7
7
4
7
50
8
7
100
200
25
14
1
7
72
55
40
25
50
-
40
40
40
40
25
-
6
1.5
3
7
3
50
6
12
18
6
3
100
200
25
6
5
3
4
5
Symmetric
6
2
3
Pull Up/Down
(3.6 V max)
-
-
7500
-
50
1
2
3
Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition
Slope at rising/falling edge
Data based on characterization results, not tested in production
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
73
Electrical Characteristics
VDD/2
Pad
Data Input
Rising
Edge
Falling
Edge
Output
Delay
Output
Delay
VOH
VOL
Pad
Output
Figure 18. Pad Output Delay
3.16 AC Timing
3.16.1 IEEE 1149.1 Interface Timing
1
Table 35. JTAG Interface Timing
Num
Symbol
tJCYC
Characteristic
Min
Max
Unit
1
2
CC2 TCK Cycle Time
100
40
—
5
—
60
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJDC
CC2 TCK Clock Pulse Width (Measured at VDD/2)
CC2 TCK Rise and Fall Times (40% – 70%)
CC2 TMS, TDI Data Setup Time
3
tTCKRISE
4
tTMSS, TDIS
tTMSH, TDIH
tTDOV
tTDOI
tTDOHZ
tBSDV
t
—
—
35
—
30
35
50
5
t
CC2 TMS, TDI Data Hold Time
25
—
0
6
CC2 TCK Low to TDO Data Valid
7
CC2 TCK Low to TDO Data Invalid
CC2 TCK Low to TDO High Impedance
CC2 TCK Falling Edge to Output Valid
8
—
—
—
9
10
tBSDVZ
CC2 TCK Falling Edge to Output Valid out of High
Impedance
11
12
13
tBSDHZ
tBSDST
tBSDHT
CC2 TCK Falling Edge to Output High Impedance
CC2 Boundary Scan Input Valid to TCK Rising Edge
CC2 TCK Rising Edge to Boundary Scan Input Invalid
—
50
50
50
—
—
ns
ns
ns
1
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 3.0 V to 5.5 V, TA = -40 to
105 °C, and CL = 50 pF with SRC = 0b11.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
74
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
2
Parameter values guaranteed by design.
TCK
2
3
3
2
1
Figure 19. JTAG Test Clock Input Timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 20. JTAG Test Access Port Timing
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
75
Electrical Characteristics
TCK
9
11
Output
Signals
10
Output
Signals
12
13
Input
Signals
Figure 21. JTAG Boundary Scan Timing
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
76
Freescale Semiconductor
Electrical Characteristics
3.16.2 Nexus Debug Interface
1
Table 36. Nexus Debug Port Timing
Num
Symbol
tMCYC
tMDC
tMDOV
tMSEOV
tEVTOV
Characteristic
CC2 MCKO Cycle Time
Min
Max
Unit
1
2
22
40
–2
–2
–2
4
—
60
14
14
14
—
—
—
60
—
—
35
ns
%
CC2 MCKO Duty Cycle
3
CC2 MCKO Low to MDO Data Valid3
CC2 MCKO Low to MSEO Data Valid3
CC2 MCKO Low to EVTO Data Valid3
CC2 EVTI Pulse Width
ns
4
ns
5
ns
6
tEVTIPW
tEVTOPW
tTCYC
tTCYC
tMCYC
ns
7
CC2 EVTO Pulse Width
1
8
CC2 TCK Cycle Time4
100
40
25
5
9
tTDC
CC2 TCK Duty Cycle
%
10
11
12
t
NTDIS, tNTMSS
CC2 TDI, TMS Data Setup Time
CC2 TDI, TMS Data Hold Time
CC2 TCK Low to TDO Data Valid
ns
tNTDIH, NTMSH
t
ns
tJOV
0
ns
1
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is
measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 3.0 V to 5.5V, TA
= -40 to 105 °C, and CL = 50 pF (Cl=30 pF on MCKO), with SRC = 0b11.
2
3
4
Parameter values guaranteed by design.
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
The system clock frequency needs to be three times faster that the TCK frequency.
Figure 22. Nexus Clock Timing
1
2
MCKO
3
4
5
MDO
MSEO
EVTO
Output Data Valid
Figure 23. Nexus Output Timing
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
77
Electrical Characteristics
TCK
9
8
9
Figure 24. Nexus TCK Timing
TCK
10
11
TMS, TDI
12
TDO
Figure 25. Nexus TDI, TMS, TDO Timing
3.16.3 Interface to TFT LCD Panels
Figure 26 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with
positive polarity. The sequence of events for active matrix interface timing is:
•
DCU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode,
DCU_CLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on the panel type.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
78
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
DCU_HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.
•
•
•
DCU_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
DCU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display.
When disabled, the data is invalid and the trace is off.
DCU_VSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
DCU_HSYNC
DCU_HSYNC
DCU_DE
1
2
3
m-1
m
DCU_CLK
DCU_LD[23:0]
1
Figure 26. TFT LCD InterfaceTiming Overview
3.16.3.1 Interface to TFT LCD Panels—Pixel Level Timings
Figure 27 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and data. All parameters
shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DCU_CLK signal
(meaning the data and sync signals change on the rising edge) and active-high polarity of the DCU_HSYNC, DCU_VSYNC
and DCU_DE signals. The user can select the polarity of the DCU_HSYNC and DCU_VSYNC signals via the SYN_POL
register, whether active-high or active-low. The default is active-high. The DCU_DE signal is always active-high.
Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are programmed via the DCU
Clock Confide Register (DCCR) in the system clock module.
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H, BP_H and FP_H
parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the
VSYN_PARA register.
Table 37. LCD Interface Timing Parameters—Horizontal and Vertical
Num
Symbol
Characteristic
Value
Unit
1
2
3
4
5
tPCP
tPWH
tBPH
tFPH
tSW
CC1 Display pixel clock period
CC1 HSYNC pulse width
CC1 HSYNC back porch width
CC1 HSYNC front porch width
CC1 Screen width
31.25
ns
ns
ns
ns
ns
PW_H * tPCP
BP_H * tPCP
FP_H * tPCP
DELTA_X * tPCP
1. In Figure 26, the “DCU_LD[23:0]” signal is an aggregation of the DCU’s RGB signals—DCU_R[0:7], DCU_G[0:7] and
DCU_B[0:7].
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
79
Electrical Characteristics
Table 37. LCD Interface Timing Parameters—Horizontal and Vertical (continued)
Num
Symbol
Characteristic
Value
Unit
6
tHSP
CC1 HSYNC (line) period
(PW_H + BP_H + FP_H + DELTA_X ) *
tPCP
ns
7
8
tPWV
tBPV
tFPV
tSH
CC1 VSYNC pulse width
CC1 VSYNC back porch width
CC1 VSYNC front porch width
CC1 Screen height
PWV * tHSP
BP_V * tHSP
FP_V * tHSP
ns
ns
ns
ns
ns
DELTA_Y * tHSP
tVSP
CC1 VSYNC (frame) period
(PW_V + BP_V + FP_V + DELTA_Y ) *
tHSP
1
Parameter values guaranteed by design.
tHSP
tFPH
tPWH
tBPH
tSW
Start of line
DCU_CLK
tPCP
Invalid Data
Invalid Data
2
3
1
DELTA_X
DCU_LD[23:0]
DCU_HSYNC
DCU_DE
Figure 27. Horizontal Sync Timing
t
VSP
t
t
t
t
SH
FPV
BPV
PWV
Start of Frame
DCU_HSYNC
t
HCP
DCU_LD[23:0]
(Line Data)
2
DELTA_Y
Invalid Data
1
3
Invalid Data
DCU_HSYNC
DCU_DE
Figure 28. Vertical Sync Pulse
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
80
Freescale Semiconductor
Electrical Characteristics
3.16.3.2 Interface to TFT LCD Panels—Access Level
1,2,3,4
Table 38. LCD Interface Timing Parameters
—Access Level
Min.
Value
Typical
Value
Num
Symbol
Characteristic
Max. Value
Unit
1
2
tCKP CC5 PDI Clock Period
tCHD CC5 Duty cycle
tDSU CC5 interface data setup time
tDHD CC5 PDI interface data access hold time
tCSU CC5 PDI interface control signal setup time
tCHD CC5 PDI interface control signal hold time
CC5 TFT interface data valid after pixel clock
CC5 TFT interface HSYNC valid after pixel clock
CC5 TFT interface VSYNC valid after pixel clock
CC5 TFT interface DE valid after pixel clock
31.25
—
—
—
—
—
—
—
—
—
—
—
ns
%
40
6
60
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
1
5
3
6
1
7
6
8
5
9
5.5
5.6
10
11
CC5 TFT interface hold time for data and control
2
bits
12
CC5 Relative skew between the data bits
—
3.7
ns
1
The characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data
on -ve edge
2
3
4
5
Intra bit skew is less than 2 ns
Load CL = 50 pf for frequency up to 20 MHz
Load CL = 25 pf for display freq from 20 to 32 MHz
Parameter values guaranteed by design.
tCHD tCSU
DCU_HSYNC
DCU_VSYNC
DCU_DE
DCU_CLK
tCKH
tCKL
tDSU tDHD
DCU_LD[23:0]
Figure 29. LCD Interface Timing Parameters—Access Level
3.16.4 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Timing
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
81
Electrical Characteristics
Table 39. IRQ and NMI Timing
Characteristic
Min.
Value
Max.
Value
Num
Symbol
Unit
1
2
3
tIPWL
tIPWH
tICYC
CC1 IRQ/NMI Pulse Width Low
CC1 IRQ/NMI Pulse Width High
CC1 IRQ/NMI Edge to Edge Time2
200
200
400
—
—
—
ns
ns
ns
1
2
Parameter values guaranteed by design.
Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
1,2
1,2
3
Figure 30. IRQ and NMI Timing
3.16.5 Enhanced Modular I/O Subsystem (eMIOS) Timing
1
Table 40. eMIOS Timing
Min.
Max.
Value
Num
Symbol
Characteristic
Unit
Value2
1
2
tMIPW
tMOPW
CC3 eMIOS Input Pulse Width
CC3 eMIOS Output Pulse Width
4
1
—
—
tCYC
tCYC
1
2
3
eMIOS timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = -40 to 105 °C,
and CL = 50 pF with SRC = 0b00
There is no limitation on the peripheral for setting the minimum pulse width, the actual width is restricted by the pad
delays. Refer to the pad specification section for the details.
Parameter values guaranteed by design.
3.16.6 FlexCAN Timing
The CAN functions are available as TX pins at normal IO pads and as RX pins at the always on domain. There is no filter for
the wakeup dominant pulse. Any high-to-low edge can cause wakeup if configured.
1
Table 41. FlexCAN Timing
Min.
Value
Max.
Value
Num
Symbol
tCANOV
tCANSU
Characteristic
Unit
1
CC2 CTNX Output Valid after CLKOUT Rising Edge (Output
Delay)
CC2 CNRX Input Valid to CLKOUT Rising Edge (Setup
—
22.48
ns
2
—
12.46
ns
Time)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
82
Freescale Semiconductor
Electrical Characteristics
1
2
FlexCAN timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = -40 to 105 °C,
and CL = 50 pF with SRC = 0b00.
Parameter values guaranteed by design.
3.16.7 Deserial Serial Peripheral Interface (DSPI)
1
Table 42. DSPI Timing
Num
Symbol
Characteristic
Min
Max
Unit
1
2
3
4
tSCK
CC2 SCK Cycle TIme3,4
60
-
—
—
—
ns
ns
ns
ns
tCSC
tASC
tSDC
CC2 PCS to SCK Delay5
CC2 After SCK Delay6
CC2 SCK Duty Cycle
20
tSCK/2
–2ns
tSCK/2
+ 2ns
5
6
7
tA
CC2 Slave Access Time
—
25
25
ns
ns
(PCSx active to SOUT driven)
tDIS
tSUI
CC2 Slave SOUT Disable Time
—
(PCSx inactive to SOUT High-Z or invalid)
CC2 Data Setup Time for Inputs
Master (MTFE = 0)
35
5
5
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
35
8
9
tHI
tSUO
tHO
CC2 Data Hold Time for Inputs
Master (MTFE = 0)
–4
10
26
–4
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
CC2 Data Valid (after SCK edge)
Master (MTFE = 0)
—
—
—
—
15
35
30
15
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
10
CC2 Data Hold Time for Outputs
Master (MTFE = 0)
–15
5.5
0
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–15
1
2
3
4
5
DSPI timing specified at VDDE_x = 3.0 V to 5.5V, TA = -40 to 105 °C, and CL = 50 pF with SRC = 0b11.
Parameter values guaranteed by design.
The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate.
The actual minimum SCK Cycle Time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK=2 &
CSSCK = 2
6
7
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
This delay value is corresponding to SMPL_PT=00b which is bit field 9 and 8 of DSPI_MCR register.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
83
Electrical Characteristics
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
8
7
Last Data
SIN
First Data
Data
Data
10
9
First Data
Last Data
SOUT
Figure 31. DSPI Classic SPI Timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
8
SCK Output
(CPOL=1)
7
Data
Data
First Data
Last Data
SIN
10
9
SOUT
Last Data
First Data
Figure 32. DSPI Classic SPI Timing — Master, CPHA = 1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
84
Freescale Semiconductor
Electrical Characteristics
3
2
PCSx
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
9
10
Data
6
First Data
Last Data
SOUT
7
8
Data
Last Data
First Data
SIN
Figure 33. DSPI Classic SPI Timing — Slave, CPHA = 0
PCSx
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
9
5
6
10
Last Data
Data
Data
SOUT
SIN
First Data
8
7
Last Data
First Data
Figure 34. DSPI Classic SPI Timing — Slave, CPHA = 1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
85
Electrical Characteristics
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
7
8
SIN
First Data
Last Data
Last Data
Data
10
9
SOUT
First Data
Data
Figure 35. DSPI Modified Transfer Format Timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
8
7
SIN
Last Data
First Data
Data
10
Data
9
First Data
Last Data
SOUT
Figure 36. DSPI Modified Transfer Format Timing — Master, CPHA = 1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
86
Freescale Semiconductor
Electrical Characteristics
3
2
PCSx
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
10
9
6
5
First Data
7
Data
Data
Last Data
8
SOUT
Last Data
First Data
SIN
Figure 37. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
PCSx
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
9
5
6
10
Last Data
First Data
8
Data
Data
SOUT
SIN
7
First Data
Last Data
Figure 38. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
87
Electrical Characteristics
3.16.8 I2C Timing
2
Table 43. I C Input Timing Specifications—SCL and SDA
Characteristic Min. Value Max. Value
CC1 Start condition hold time
Num
Symbol
Unit
1
2
4
6
7
8
—
2
8
—
—
—
—
—
—
IP-Bus Cycle2
IP-Bus Cycle2
ns
—
—
—
—
—
CC1 Clock low time
CC1 Data hold time
CC1 Clock high time
CC1 Data setup time
0.0
4
IP-Bus Cycle2
0.0
2
ns
CC1 Start condition setup time (for repeated start
condition only)
IP-Bus Cycle2
9
—
CC1 Stop condition setup time
2
—
IP-Bus Cycle2
1
2
Parameter values guaranteed by design.
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
2
Table 44. I C Output Timing Specifications—SCL and SDA
Num
Symbol
Characteristic
Min. Value
Max. Value
Unit
11
21
34
41
51
61
71
81
—
CC2 Start condition hold time
6
10
—
7
—
—
IP-Bus Cycle3
IP-Bus Cycle2
ns
—
—
—
—
—
—
—
CC2 Clock low time
CC2 SCL/SDA rise time
CC2 Data hold time
CC2 SCL/SDA fall time
CC2 Clock high time
CC2 Data setup time
99.6
—
IP-Bus Cycle2
—
10
2
99.5
—
ns
IP-Bus Cycle2
IP-Bus Cycle2
IP-Bus Cycle2
—
CC2 Start condition setup time (for repeated start
condition only)
20
—
91
—
CC2 Stop condition setup time
10
—
IP-Bus Cycle2
2
1
Programming IBFD (I C bus Frequency Divider) with the maximum frequency results in the minimum output
timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed in IFDR.
2
3
4
Parameter values guaranteed by design.
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
88
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
5
6
2
SCL
SDA
3
8
4
7
9
1
2
Figure 39. I C Input/Output Timing
3.16.9 Mechanical Outline Drawings
3.17 144 LQFP
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
89
Electrical Characteristics
Figure 40. LQFP144 Mechanical Drawing (Part 1 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
90
Freescale Semiconductor
Electrical Characteristics
Figure 41. LQFP144 Mechanical Drawing (Part 2 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
91
Electrical Characteristics
Figure 42. LQFP144 Mechanical Drawing (Part 3 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
92
Freescale Semiconductor
Electrical Characteristics
3.18 176 LQFP
Figure 43. LQFP176 Mechanical Drawing (Part 1 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
93
Electrical Characteristics
Figure 44. LQFP176 Mechanical Drawing (Part 2 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
94
Freescale Semiconductor
Electrical Characteristics
Figure 45. LQFP176 Mechanical Drawing (Part 3 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
95
Ordering Information
4
Ordering Information
Table 45 shows the orderable part numbers for the MPC5606S series.
Table 45. Orderable Part Number Summary
Speed
(MHz)
Part Number
Flash/SRAM
Package
MPC5602SEMLQ 256 KB/24 KB
MPC5604SEMLQ 512 KB/48 KB
MPC5604SEMLQ 512 KB/48 KB
MPC5606SEMLQ 1 MB/48 KB1
MPC5606SEMLU 1 MB/48 KB1
144 LQFP
144 LQFP
144 LQFP
144 LQFP
176 LQFP
64
64
64
64
64
1
Device also includes 160 KB of graphics SRAM.
Figure 46. Commercial product code structure
Example code:
M
PC
56
0
4
S
E
M
LL
R
Qualification Status
PowerPC Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
Temperature spec.
Package Code
R = Tape & Reel (blank if Tray)
Qualification Status
M = MC status
Flash Size (z0 core)
2 = 256 KB
Temperature spec.
C = –40° C to 85°C
V = –40° C to 105°C
M = –40° C to 125°C
S = Auto qualified
P = PC status
4 = 512 KB
6 = 1024 KB
Automotive Platform
56 = PPC in 90nm
Product
B = Body
Package Code
LQ = 144 LQFP
LU = 176 LQFP
57 = PPC in 65nm
C = Gateway
1
MG = 208 MAPBGA
1
208 MAPBGA available only as development package for Nexus2+
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
96
Freescale Semiconductor
Ordering Information
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
97
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
Semiconductor was negligent regarding the design or manufacture of the part.
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
The Power Architecture and Power.org word marks and the Power and Power.org logos
and related marks are trademarks and service marks licensed by Power.org.
Beijing 100022
China
+86 10 5879 8000
support.asia@freescale.com
© Freescale Semiconductor, Inc. 2008. All rights reserved.
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Document Number: MPC5606S
Rev. 1
10/2008
Preliminary—Subject to Change Without Notice
相关型号：
©2020 ICPDF网 联系我们和版权申明