PPC8567ECVTAQGGA_技术文档

Document Number: MPC8568EEC

Rev. 1, 10/2010

Freescale Semiconductor

Technical Data

MPC8568E/MPC8567E

PowerQUICC III

Integrated Processor

Hardware Specifications

Contents

Due to feature similarities, this document covers both the

1. MPC8568E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 10

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14

4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 18

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8. Ethernet Interface and MII Management . . . . . . . . . . 26

9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11. I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

13. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . 61

14. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

15. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

16. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

17. PIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

18. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

19. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

20. UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

MPC8568E and MPC8567E features. For simplicity,

MPC8568 may only be mentioned throughout the document.

The MPC8567E feature differences are as follows:

•

The MPC8567E PCI-Express supports x1/x2/x4, but

does not have x8 support.

•

Does not have eTSEC1, eTSEC2, or TLU

Note that both the MPC8568E and MPC8567E have their

own pin assignment tables.

21. HDLC, BISYNC, Transparent and

Synchronous UART . . . . . . . . . . . . . . . . . . . . . . . . . . 96

22. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 99

23. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

24. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

25. System Design Information . . . . . . . . . . . . . . . . . . . 130

26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 136

27. Document Revision History . . . . . . . . . . . . . . . . . . 138

MPC8568E Overview

1 MPC8568E Overview

This section provides a high-level overview of MPC8568E features. Figure 1 shows the major functional

units within the MPC8568E.

512-Kbyte

L2 Cache/

SRAM

DDR

SDRAM

MPC8568

e500 Core

DDR/DDR2/

Memory Controller

Flash

SDRAM

ZBT RAM

e500

Coherency

Module

32-KbyteL1

Instruction

Cache

32-Kbyte

L1 Data

Cache

Local Bus Controller

Core Complex

Bus

Table Lookup Unit

Serial RapidIO

and/or

PCI Express

4x/1x RapidIO and/or

x4/x2/x1 PCI Express

or x8 PCI Express

Programmable Interrupt

Controller (PIC)

OceaN

Switch

Fabric

IRQs

Serial

DUART

PCI 32-bit

66 MHz

32-bit PCI Bus Interface

2

I C Controller

I C

4-Channel DMA

Controller

2

I C Controller

I C

QUICC Engine™

Multi-User

MII, GMII, TBI,

RTBI, RGMII,

RMII

eTSEC

10/100/1Gb

Accelerators

RAM

Baud Rate

Serial DMA

&

2 Virtual

DMAs

Generators

MII, GMII, TBI,

RTBI, RGMII,

RMII

eTSEC

Dual 32-bit RISC CP

10/100/1Gb

Parallel I/O

Security

Engine

XOR

Engine

Time Slot Assigner

Serial Interface

8 MII/

RMII

3 GMII/

2 RGMII/TBI/RTBI

2 UL2/POS

8 TDM Ports

Figure 1. MPC8568E Block Diagram

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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MPC8568E Overview

1.1

MPCP8568E Key Features

•

High-performance, Power Architecture® e500v2 core with 36-bit physical addressing

•

512 Kbytes of level-2 cache

QUICC Engine (QE)

Integrated security engine with XOR acceleration

Two integrated 10/100/1Gb enhanced three-speed Ethernet controllers (eTSECs) with TCP/IP

acceleration and classification capabilities

•

DDR/DDR2 memory controller

Table lookup unit (TLU) to access application-defined routing topology and control tables

32-bit PCI controller

A 1x/4x Serial RapidIO® and/or x1/x2/x4 PCI Express interface. If x8 PCI Express is needed, then

RapidIO is not available due to the limitation of the pin multiplexing.

•

Programmable interrupt controller (PIC)

2

Four-channel DMA controller, two I C controllers, DUART, and local bus controller (LBC)

NOTE

The MPC8568E and MPC8567E are also available without a security

engine in a configuration known as the MPC8568 and MPC8567. All

specifications other than those relating to security apply to the MPC8568

and MPC8567 exactly as described in this document.

1.2

1.2.1

MPC8568E Architecture Overview

e500 Core and Memory Unit

The MPC8568E contains a high-performance, 32-bit, Book E–enhanced e500v2 Power Architecture core.

In addition to 36-bit physical addressing, this version of the e500 core includes the following:

•

Double-precision floating-point APU—Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs

•

Embedded vector and scalar single-precision floating-point APUs—Provide an instruction set for

single-precision (32-bit) floating-point instructions

The MPC8568E also contains 512 Kbytes of L2 cache/SRAM, as follows:

•

Eight-way set-associative cache organization with 32-byte cache lines

Flexible configuration (can be configured as part cache, part SRAM)

External masters can force data to be allocated into the cache through programmed memory ranges

or special transaction types (stashing).

•

SRAM features include the following:

— I/O devices access SRAM regions by marking transactions as snoopable (global).

— Regions can reside at any aligned location in the memory map.

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MPC8568E Overview

— Byte-accessible ECC uses read-modify-write transaction accesses for smaller-than-cache-line

accesses.

1.2.2

e500 Coherency Module (ECM) and Address Map

The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus

between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable

memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be

routed or dispatched to target modules on the device.

The MPC8568E supports a flexible 36-bit physical address map. Conceptually, the address map consists of

local space and external address space. The local address map is supported by eight local access windows

that define mapping within the local 36-bit (64-Gbyte) address space.

The MPC8568E can be made part of a larger system address space through the mapping of translation

windows. This functionality is included in the address translation and mapping units (ATMUs). Both

inbound and outbound translation windows are provided. The ATMUs allows the MPC8568E to be part of

larger address maps such as the PCI or PCI Express 64-bit address environment and the RapidIO

environment.

1.2.3

QUICC Engine

•

Integrated 8-port L2 Ethernet switch

— 8 connection ports of 10/100 Mbps MII/RMII & one CPU internal port

— Each port supports four priority levels

— Priority levels used with VLAN tags or IP TOS field to implement QoS

— QoS types of traffic, such as voice, video, and data

Includes support for the following protocols:

•

— ATM SAR up to 622 Mbps (OC-12) full duplex, with ATM traffic shaping (ATF TM4.1) for

up to 64K ATM connections

— ATM AAL1 structured and unstructured Circuit Emulation Service (CES 2.0)

— IMA and ATM Transmission convergence sub-layer

— ATM OAM handling features compatible with ITU-T I.610

— PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the

following RFCs: 1661, 1662, 1990, 2686 and 3153

— IP termination support for IPv4 and IPv6 packets including TOS, TTL and header checksum

processing

— ATM (AAL2/AAL5) to Ethernet (IP) interworking

— Extensive support for ATM statistics and Ethernet RMON/MIB statistics.

— 256 channels of HDLC/Transparent or 128 channels of SS#7

Includes support for the following serial interfaces:

•

— Two UL2/POS-PHY interfaces with 124 Multi-PHY addresses on UTOPIA interface each or

31 Multi-PHY addresses on the POS interface each.

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MPC8568E Overview

— Three 1-Gbps Ethernet interfaces using three GMII, two RGMII/TBI/RTBI

— Up to eight 10/100-Mbps Ethernet interfaces using MII or RMII

— Up to eight T1/E1/J1/E3 or DS-3 serial interfaces

1.2.4

Integrated Security Engine (SEC)

The SEC is a modular and scalable security core optimized to process all the algorithms associated with

IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is

designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of

the data. The version of the SEC used in the MPC8568E is specifically capable of performing single-pass

security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and 802.11i.

•

Optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and

3GPP

•

Compatible with code written for the Freescale MPC8541E and MPC8555E devices

XOR engine for parity checking in RAID storage applications.

Four crypto-channels, each supporting multi-command descriptor chains

Cryptographic execution units:

— PKEU—public key execution unit

— DEU—Data Encryption Standard execution unit

— AESU—Advanced Encryption Standard unit

— AFEU—ARC four execution unit

— MDEU—message digest execution unit

— KEU—Kasumi execution unit

— RNG—Random number generator

1.2.5

Enhanced Three-Speed Ethernet Controllers

The MPC8568E has two on-chip enhanced three-speed Ethernet controllers (eTSECs). The eTSECs

incorporate a media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps

Ethernet/802.3 networks with MII, RMII, GMII, RGMII, TBI, and RTBI physical interfaces. The eTSECs

include 2-Kbyte receive and 10-Kbyte transmit FIFOs and DMA functions.

The MPC8568E eTSECs support programmable CRC generation and checking, RMON statistics, and

jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache

to speed classification or other frame processing. They are IEEE Std 802.3™, IEEE 802.3u, IEEE 802.3x,

IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab-compatible.

The buffer descriptors are based on the MPC8260 and MPC860T 10/100 Ethernet programming models.

Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with

minimal change.

Some of the key features of these controllers include:

•

Flexible configuration for multiple PHY interface configurations. Table 1 lists available

configurations.

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MPC8568E Overview

1

Table 1. Supported eTSEC1 and eTSEC2 Configurations

Mode Option

eTSEC1

eTSEC2

Ethernet standard interfaces

Ethernet reduced interfaces

FIFO and mixed interfaces

TBI, GMII, or MII

RTBI, RGMII, or RMII

8-bit FIFO

TBI, GMII, or MII

RTBI, RGMII, or RMII

TBI, GMII, MII, RTBI, RGMII, RMII,

or 8-bit FIFO

TBI, GMII, MII, RTBI, RGMII, RMII,

or 8-bit FIFO

8-bit FIFO

16-bit FIFO

Not used/not available

1

Both interfaces must use the same voltage (2.5 or 3.3 V).

•

TCP/IP acceleration and QoS features:

— IP v4 and IP v6 header recognition on receive

— IP v4 header checksum verification and generation

— TCP and UDP checksum verification and generation

— Per-packet configurable acceleration

— Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS stacks,

and ESP/AH IP-security headers

— Supported in all FIFO modes

— Transmission from up to eight physical queues

— Reception to up to eight physical queues

•

Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):

— IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or

software-programmed PAUSE frame generation and recognition)

•

IEEE Std 802.1™ virtual local area network (VLAN) tags and priority

VLAN insertion and deletion

– Per-frame VLAN control word or default VLAN for each eTSEC

– Extracted VLAN control word passed to software separately

Programmable Ethernet preamble insertion and extraction of up to 7 bytes

MAC address recognition

•

Ability to force allocation of header information and buffer descriptors into L2 cache

1.2.6

DDR SDRAM Controller

The MPC8568E supports DDR SDRAM and DDR2 SDRAM. The memory interface controls main

memory accesses and provides for a maximum of 16 Gbytes of main memory.

The MPC8568E supports a variety of SDRAM configurations. SDRAM banks can be built using DIMMs

or directly-attached memory devices. Sixteen multiplexed address signals provide for device densities of

64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbits, 2 Gbits and 4 Gbits. Four chip select signals support

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MPC8568E Overview

up to four banks of memory. The MPC8568E supports bank sizes from 64 Mbytes to 4 Gbytes. Nine

column address strobes (MDM[0:8]) are used to provide byte selection for memory bank writes.

The MPC8568E can be configured to retain the currently active SDRAM page for pipelined burst accesses.

Page mode support of up to 16 simultaneously open pages (32 for DDR2) can dramatically reduce access

latencies for page hits. Depending on the memory system design and timing parameters, using page mode

can save 3 to 4 clock cycles from subsequent burst accesses that hit in an active page.

Using ECC, the MPC8568E detects and corrects all single-bit errors and detects all double-bit errors and

all errors within a nibble.

The MPC8568E can invoke a level of system power management by asserting the MCKE SDRAM signal

on-the-fly to put the memory into a low-power sleep mode.

1.2.7

Table Lookup Unit (TLU)

The table lookup unit (TLU) provides access to application-defined routing topology and control tables in

external memory. It accesses an external memory array attached to the local bus controller (LBC).

Communication between the CPU and the TLU occurs via messages passed through the TLU’s

memory-mapped configuration and status registers.

The TLU provides resources for efficient generation of table entry addresses in memory, hash generation

of addresses, and binary table searching algorithms for both exact-match and longest-prefix-match

strategies.It supports the following TLU complex table types:

•

Hash-Trie-Key table for hash-based exact-match algorithms

Chained-Hash table for partially indexed and hashed exact-match algorithms

Longest-prefix-match algorithm

Flat-Data table for retrieving search results and simple indexed algorithms

1.2.8

PCI Controller

The MPC8568E supports one 32-bit PCI controller, which supports speeds of up to 66 MHz. Other features

include:

•

Compatible with the PCI Local Bus Specification, Revision 2.2, supporting 32- and 64-bit

addressing

•

Can function as host or agent bridge interface

As a master, supports read and write operations to PCI memory space, PCI I/O space, and PCI

configuration space

•

Can generate PCI special-cycle and interrupt-acknowledge commands. As a target, it supports read

and write operations to system memory as well as configuration accesses.

Supports PCI-to-memory and memory-to-PCI streaming, memory prefetching of PCI read

accesses, and posting of processor-to-PCI and PCI-to-memory writes

PCI 3.3-V compatible with selectable hardware-enforced coherency

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MPC8568E Overview

1.2.9

High Speed I/O Interfaces

The MPC8568E supports two high-speed I/O interface standards: serial RapidIO and PCI Express. It can

be configured as x1/x4 SRIO and 1x/2x/4x PCI Express simultaneously with the following limitation:

•

Both SRIO and PCI-Express are limited to use the same clock and are limited to 2.5G.

Spread spectrum clocking can not be used because SRIO doesn't support this (PCI-Express does

support it).

If x8 PCI Express is needed, then SRIO is not available due to the pin multiplex limitation.

1.2.10 Serial RapidIO

The serial RapidIO interface is based on the RapidIO Interconnect Specification, Revision 1.2. RapidIO is

a high-performance, point-to-point, low-pin-count, packet-switched system-level interconnect that can be

used in a variety of applications as an open standard. The RapidIO architecture has a rich variety of

features including high data bandwidth, low-latency capability, and support for high-performance I/O

devices, as well as support for message-passing and software-managed programming models. Key features

of the serial RapidIO interface unit include:

•

Support for RapidIO Interconnect Specification, Revision 1.2 (all transaction flows and priorities)

Both 1x and 4x LP-serial link interfaces, with transmission rates of 1.25, 2.5, and 3.125 Gbaud

(data rates of 1.0, 2.0, and 2.5 Gbps) per lane

•

Auto detection of 1x or 4x mode operation during port initialization

34-bit addressing and up to 256-byte data payload

Receiver-controlled flow control

Support for RapidIO error injection

The RapidIO messaging unit supports two inbox/outbox mailboxes (queues) for data and one doorbell

message structure. Both chaining and direct modes are provided for the outbox, and messages can hold up

to 16 packets of 256 bytes, or a total of 4 Kbytes.

1.2.11 PCI Express Interface

The MPC8568E supports a PCI Express interface compatible with the PCI Express Base Specification

Revision 1.0a. It is configurable at boot time to act as either root complex or endpoint.The physical layer

of the PCI Express interface operates at a 2.5-Gbaud data rate per lane.

Other features of the PCI Express interface include:

•

x8, x4, x2, and x1 link widths supported

Selectable operation as root complex or endpoint

Both 32- and 64-bit addressing and 256-byte maximum payload size

Full 64-bit decode with 32-bit wide windows

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MPC8568E Overview

1.2.12 Programmable Interrupt Controller (PIC)

The MPC8568E PIC implements the logic and programming structures of the OpenPIC architecture,

providing for external interrupts (with fully nested interrupt delivery), message interrupts, internal-logic

driven interrupts, and global high-resolution timers. Up to 16 programmable interrupt priority levels are

supported.

The PIC can be bypassed to allow use of an external interrupt controller.

1.2.13 DMA Controller, I²C, DUART, and Local Bus Controller

The MPC8568E provides an integrated four-channel DMA controller, which can transfer data between any

of its I/O or memory ports or between two devices or locations on the same port. The DMA controller also:

•

Allows chaining (both extended and direct) through local memory-mapped chain descriptors.

Scattering, gathering, and misaligned transfers are supported. In addition, stride transfers and

complex transaction chaining are supported.

•

Local attributes such as snoop and L2 write stashing can be specified.

2

There are two I C controllers. These synchronous, multimaster buses can be connected to additional

devices for expansion and system development.

The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550

programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.

The MPC8568E local bus controller (LBC) port allows connections with a wide variety of external

memories, DSPs, and ASICs. Three separate state machines share the same external pins and can be

programmed separately to access different types of devices. The general-purpose chip select machine

(GPCM) controls accesses to asynchronous devices using a simple handshake protocol. The user

programmable machine (UPM) can be programmed to interface to synchronous devices or custom ASIC

interfaces. The SDRAM controller provides access to standard SDRAM. Each chip select can be configured

so that the associated chip interface can be controlled by the GPCM, UPM, or SDRAM controller. All may

exist in the same system. The local bus controller supports the following features:

•

Multiplexed 32-bit address and data bus operating at up to 133 MHz

Eight chip selects support eight external slaves

Up to eight-beat burst transfers

32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

Three protocol engines available on a per-chip-select basis

Parity support

Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)

Supports zero-bus-turnaround (ZBT) RAM

1.2.14 Power Management

In addition to low-voltage operation and dynamic power management, which automatically minimizes

power consumption of blocks when they are idle, four power consumption modes are supported: full on,

doze, nap, and sleep.

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Electrical Characteristics

1.2.15 System Performance Monitor

The performance monitor facility supports eight 32-bit counters that can count up to 512 counter-specific

events. It supports duration and quantity threshold counting and a burstiness feature that permits counting

of burst events with a programmable time between bursts.

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8568E. This device is currently targeted to these specifications. Some of these specifications are

independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer

design specifications.

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

1

Table 2. Absolute Maximum Ratings

Characteristic Symbol

Max Value

Unit Notes

Core supply voltage

PLL supply voltage

V

–0.3 to 1.21

V

—

DD

AV

_

,

DD PLAT

AV

_

DD CORE,

AV

_

DD CE,

AV

_

DD PCI,

AV

_

DD LBIU,

AV

_

DD SRDS

Core power supply for SerDes transceiver

Pad power supply for SerDes transceiver

DDR and DDR2 DRAM I/O voltage

SCOREVDD

–0.3 to 1.21

V

—

XV

DD

GV

–0.3 to 2.75

–0.3 to 1.98

eTSEC1, eTSEC2 I/O Voltage

LV

–0.3 to 3.63

–0.3 to 2.75

V

—

3

DD

QE UCC1/UCC2 Ethernet Interface I/O Voltage

TV

OV

BV

–0.3 to 3.63

–0.3 to 2.75

DD

2

PCI, DUART, system control and power management, I C, and JTAG

I/O voltage

–0.3 to 3.63

Local bus I/O voltage

–0.3 to 3.63

–0.3 to 2.75

3

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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Electrical Characteristics

1

Table 2. Absolute Maximum Ratings (continued)

Characteristic Symbol

MV

Max Value

–0.3 to (GV + 0.3)

Unit Notes

Input voltage

DDR/DDR2 DRAM signals

DDR/DDR2 DRAM reference

Three-speed Ethernet signals

V

2, 5

4, 5

IN

DD

MV

–0.3 to (GV + 0.3)

DD

REF

LV

–0.3 to (LV + 0.3)

DD

IN

TV

–0.3 to (TV + 0.3)

IN

DD

Local bus signals

BV

–0.3 to (BV + 0.3)

—

5

IN

DD

DUART, SYSCLK, system control and power

OV

–0.3 to (OV + 0.3)

V

IN

DD

2

management, I C, and JTAG signals

PCI

–0.3 to (OV + 0.3)

V

6

IN

DD

Storage temperature range

T

–55 to 150

•C

—

STG

Notes:

1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Caution: MV must not exceed GV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

IN

DD

power-on reset and power-down sequences.

3. Caution: OV must not exceed OV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

IN

DD

power-on reset and power-down sequences.

4. Caution: L/TV must not exceed L/TV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

IN

DD

power-on reset and power-down sequences.

5. (M,L,O)V and MV may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

IN

REF

6. OV on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as

IN

shown in Figure 2.

2.1.2

Recommended Operating Conditions

Table 3 provides the recommended operating conditions for this device. Note that the values in Table 3 are

the recommended and tested operating conditions. Proper device operation outside these conditions is not

guaranteed.

Table 3. Recommended Operating Conditions

Recommended

Characteristic

Symbol

Unit Notes

Value

Core supply voltage

PLL supply voltage

V

1.1 V 55 mV

V

—

DD

AV

_

,

DD PLAT

AV

_

DD CORE,

AV

_

DD CE,

AV

_

DD PCI,

AV

_

DD LBIU,

AV

_

DD SRDS

Core power supply for SerDes transceiver

Pad power supply for SerDes transceiver

DDR and DDR2 DRAM I/O voltage

SCOREVDD

XV

1.1 V 55 mV

V

—

DD

GV

2.5 V 125 mV

1.8 V 90 mV

DD

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

11

Electrical Characteristics

Table 3. Recommended Operating Conditions (continued)

Recommended

Value

Characteristic

Three-speed Ethernet I/O voltage

Symbol

Unit Notes

LV

TV

3.3 V 165 mV

2.5 V 125 mV

V

—

DD

2

PCI, DUART, system control and power management, I C, and JTAG I/O

voltage

OV

BV

3.3 V 165 mV

DD

Local bus I/O voltage

3.3 V 165 mV

2.5 V 125 mV

DD

Input voltage

DDR and DDR2 DRAM signals

DDR and DDR2 DRAM reference

Three-speed Ethernet signals

MV

GND to GV

V

—

IN

DD

MV

GND to GV /2

DD

REF

LV

GND to LV

DD

IN

TV

GND to TV

GND to BV

GND to OV

IN

DD

Local bus signals

BV

V

—

IN

PCI, DUART, SYSCLK, system control and power

OV

IN

2

management, I C, and JTAG signals

o

Junction temperature range

Tj

0 to105

C

—

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8568E.

B/G/L/T/OV + 20%

DD

B/G/L/T/OV + 5%

DD

B/G/L/T/OV

V

DD

IH

GND

GND – 0.3 V

V

IL

GND – 0.7 V

Not to Exceed 10%

1

of t

CLOCK

Note:

1. Note that t

refers to the clock period associated with the respective interface

CLOCK

For I2C and JTAG, t

references SYSCLK.

CLOCK

For DDR, t

references MCLK.

CLOCK

For eTSEC, tCLOCK references EC_GTX_CLK125.

For LBIU, t references LCLK.

CLOCK

For PCI, t

references PCI_CLK or SYSCLK.

CLOCK

For SerDes, t

references SD_REF_CLK.

CLOCK

2. Note that with the PCI overshoot allowed (as specified above), the device

does not fully comply with the maximum AC ratings and device protection guideline

outlined in the PCI rev. 2.2 standard (section 4.2.2.3)

Figure 2. Overshoot/Undershoot Voltage for BV /GV /LV /TV /OV

DD

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

12

Electrical Characteristics

The core voltage must always be provided at nominal 1.1V. (See Table 3 for actual recommended core

voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must

be provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the

associated I/O supply voltage. OV and LV based receivers are simple CMOS I/O circuits and satisfy

DD

appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential

receiver referenced the externally supplied MV

the SSTL2 electrical signaling standard.

signal (nominally set to GV /2) as is appropriate for

REF

DD

2.1.3

Output Driver Characteristics

Table 4 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

Table 4. Output Drive Capability

Programmable

Supply

Driver Type

Output Impedance

Notes

Voltage

(Ω)

Local bus interface utilities signals

25

BV = 3.3 V

1

DD

BV = 2.5 V

DD

45(default)

BV = 3.3 V

DD

BV = 2.5 V

DD

PCI signals

25

42 (default)

20

OV = 3.3 V

2

DD

DDR signal

GV = 2.5 V

—

DD

DDR2 signal

16

GV = 1.8 V

DD

32 (half strength mode)

eTSEC 10/100/1000 signals

42

L/TV = 2.5/3.3 V

—

DD

DUART, system control, JTAG

OV = 3.3 V

DD

I2C

150

OV = 3.3 V

DD

Notes:

1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.

2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT[1] signal at reset.

2.2

Power Sequencing

The MPC8568E requires its power rails to be applied in specific sequence in order to ensure proper device

operation. These requirements are as follows for power up:

1. V , AV _n, BV , SCOREV , LV , TV , XV , OV

DD

2. GV

DD

All supplies must be at their stable values within 50 ms.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

13

Power Characteristics

NOTE

Items on the same line have no ordering requirement with respect to one

another. Items on separate lines must be ordered sequentially such that

voltage rails on a previous step must reach 90% of their value before the

voltage rails on the current step reach 10% of theirs.

In order to guarantee MCKE low during power-up, the above sequencing for

GVDD is required. If there is no concern about any of the DDR signals

being in an indeterminate state during power-up, then the sequencing for

GVDD is not required.

3 Power Characteristics

The power dissipation of V for various core complex bus (CCB) versus the core and QE frequency for

DD

MPC8568E is shown in Table 5. Note that this is based on the design estimate only. More accurate power

number will be available after we have done the measurement on the silicon.

Table 5. MPC8568E Power Dissipation

CCB Frequency

Core Frequency

QE Frequency

Typical 65°C Typical 105°C

Maximum

Unit

400

533

800

1000

1200

1333

400

533

8.7

8.9

12.0

12.3

15.7

17.2

13.0

13.6

16.9

18.7

W

11.3

12.4

Notes:

1. CCB Frequency is the SoC platform frequency which corresponds to DDR data rate.

2. Typical 65 °C based on V =1.1V, Tj=65.

DD

3. Typical 105 °C based on V =1.1V, Tj=105.

DD

4. Maximum based on V =1.1V, Tj=105.

DD

Table 6. Typical MPC8568E I/O Power Dissipation

GV BV LV TV

DD

Interface

Parameters

OV

XV

Unit

Comment

DD

2.5 V 1.8 V 3.3 V 2.5 V

3.3 V 2.5 V 3.3 V 2.5 V

W

333 MHz

400 MHz

533 MHz

0.76 0.50

0.56

Data rate

64-bit with

ECC

DDR/DDR2

60% utilization

0.68

33 MHz, 32b

66 MHz, 32b

133 MHz, 32b

33 MHz

0.07 0.04

0.13 0.07

0.24 0.14

W

—

Local Bus

PCI

0.04

0.07

66 MHz

SRIO

4x, 3.125G

8x, 2.5G

0.49

0.71

PCI Express

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

14

Input Clocks

Comment

Table 6. Typical MPC8568E I/O Power Dissipation (continued)

GV BV LV TV

DD

Interface

Parameters

OV

XV

Unit

DD

2.5 V 1.8 V 3.3 V 2.5 V

3.3 V 2.5 V 3.3 V 2.5 V

MII

0.01

0.07

0.04

0.20

0.16

0.11

0.08

0.01

0.07

0.04

W

Multiply with

number of the

interfaces

eTSEC

Ethernet

GMII/TBI

RGMII/RTBI

16b, 200 MHz

16b, 155 MHz

8b, 200 MHz

8b, 155 MHz

MII/RMII

Multiply with

number of the

interfaces

eTSEC

FIFO I/O

Multiply with

number of the

interfaces

QE UCC

GMII/TBI

RGMII/RTBI

If UCC is

programmed

for other

protocols,

scale Ethernet

power

dissipation to

the number of

signals and the

clock rate

Note: This is the power for each individual interface. The power must be calculated for each interface being utilized.

4 Input Clocks

4.1

System Clock Timing

Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8568E.

Table 7. SYSCLK AC Timing Specifications

At recommended operating conditions (see Table 3) with OV = 3.3 V 165 mV.

DD

Parameter/Condition

SYSCLK frequency

Symbol

Min

Typical

Max

Unit

Notes

f

t

—

6.0

0.6

40

—

166

—

MHz

ns

1

—

2

SYSCLK

SYSCLK cycle time

SYSCLK rise and fall time

SYSCLK duty cycle

t

, t

1.0

—

2.3

60

ns

KH KL

t

/t

%

3

KHK SYSCLK

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

15

Input Clocks

Table 7. SYSCLK AC Timing Specifications (continued)

At recommended operating conditions (see Table 3) with OV = 3.3 V 165 mV.

DD

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

SYSCLK jitter

Notes:

—

+/– 150

ps

4, 5

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the

resulting SYSCLK frequency, e500 core frequency, and CCB clock frequency do not exceed their respective

maximum or minimum operating frequencies. Refer to Section 23.2, “CCB/SYSCLK PLL Ratio and Section 23.3,

“e500 Core PLL Ratio,” for ratio settings.

2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

4.2

PCI Clock Timing

Table 8 provides the PCI clock (PCI_CLK) AC timing specifications for the MPC8568E.

Table 8. PCI_CLK AC Timing Specifications

At recommended operating conditions (see Table 3) with OV = 3.3 V 165 mV.

DD

Parameter/Condition

PCI_CLK frequency

Symbol

Min

Typical

Max

Unit

Notes

f

t

—

15

0.6

40

—

66.7

—

MHz

ns

—

1

PCI_CLK

PCI_CLK cycle time

PCI_CLK rise and fall time

PCI_CLK duty cycle

PCI_CLK jitter

t

, t

1.0

—

2.3

ns

KH KL

t

/t

60

%

2

KHK PCI_CLK

—

+/– 150

ps

3,4

Notes:

1. Rise and fall times for PCI_CLK are measured at 0.4 V and 2.7 V.

2. Timing is guaranteed by design and characterization.

3. This represents the total input jitter—short term and long term—and is guaranteed by design.

4. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

4.3

Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then

used as an input to the counters of the PIC and the Time Base unit of the e500. There is no need for jitter

specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB

clock. That is, minimum clock high time is 2 × t

, and minimum clock low time is 2 × t

. There is

CCB

no minimum RTC frequency. RTC may be grounded if not needed.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

16

Input Clocks

4.4

eTSEC Gigabit Reference Clock Timing

Table 9 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for

the MPC8568E.

Table 9. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

EC_GTX_CLK125 frequency

EC_GTX_CLK125 cycle time

EC_GTX_CLK125 rise and fall time

f

t

—

125

8

—

MHz

ns

—

G125

t

ns

G125R, G125F

—

0.75

1.0

L/TVDD = 2.5 V

L/TVDD = 3.3 V

EC_GTX_CLK125 duty cycle

t

/t

—

%

1, 2

G125H G125

45

47

55

53

GMII, TBI

1000Base-T for RGMII, RTBI

Notes:

1. Timing is guaranteed by design and characterization.

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation.

EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle

generated by the eTSEC GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle

for 10Base-T and 100Base-T reference clock.

3. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TVDD = 2.5 V, and from 0.6 and 2.7

V for L/TVDD = 3.3 V.

4.5

FIFO Clock Speed Restrictions

Note the following FIFO maximum speed restrictions based on the platform speed.

For FIFO GMII mode:

FIFO TX/RX clock frequency <= platform clock frequency / 4.2

For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no higher

than 127 MHz.

For FIFO encoded mode:

FIFO TX/RX clock frequency <= platform clock frequency / 3.2

For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no higher

than 167 MHz

4.6

Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,

see the specific section of this document.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

17

RESET Initialization

5 RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8568E. Table 10 provides the RESET initialization AC timing specifications for the DDR

SDRAM component(s).

Table 10. RESET Initialization Timing Specifications

Parameter/Condition

Required assertion time of HRESET

Min

Max

Unit

Notes

100

3

—

μs

—

1

Minimum assertion time for SRESET

SYSCLKs

μs

PLL input setup time with stable SYSCLK before HRESET negation

100

4

—

1

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

SYSCLKs

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

2

—

5

SYSCLKs

1

Maximum valid-to-high impedance time for actively driven POR configs with

respect to negation of HRESET

—

Notes:

1. SYSCLK is the primary clock input for the MPC8568E.

Table 11 provides the PLL lock times.

Table 11. PLL Lock Times

Parameter/Condition

Platform PLL lock times

Min

Max

Unit

Notes

—

100

μs

—

QE PLL lock times

CPU PLL lock times

PCI PLL lock times

Local bus PLL

6 DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8568E. Note that DDR SDRAM is GV (typ) = 2.5 V and DDR2 SDRAM is GV (typ) = 1.8 V.

DD

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

18

DDR and DDR2 SDRAM

6.1

DDR SDRAM DC Electrical Characteristics

Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

MPC8568E when GV (typ) = 1.8 V.

DD

Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V

DD

Parameter/Condition

I/O supply voltage

Symbol

Min

Max

Unit

Notes

GV

MV

1.7

1.9

V

1

2

DD

I/O reference voltage

I/O termination voltage

Input high voltage

0.49 × GV

0.51 × GV

DD

REF

TT

DD

V

MV

– 0.04

MV

+ 0.04

REF

V

3

REF

V

MV

+ 0.125

GV + 0.3

V

—

4

IH

REF

DD

Input low voltage

V

I

–0.3

MV

– 0.125

REF

V

IL

Output leakage current

–10

–13.4

13.4

10

μA

mA

OZ

OH

Output high current (V

= 1.420 V)

I

—

OUT

Output low current (V

= 0.280 V)

I

OL

OUT

Notes:

1. GV is expected to be within 50 mV of the DRAM GV at all times.

DD

2. MV

is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver.

REF

DD DD

may not exceed 2% of the DC value.

Peak-to-peak noise on MV

REF

3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

TT

equal to MV . This rail should track variations in the DC level of MV

.

REF

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV

.

DD

Table 13 provides the DDR capacitance when GV (typ) = 1.8 V.

DD

Table 13. DDR2 SDRAM Capacitance for GV (typ)=1.8 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

Note:

C

6

8

pF

1

IO

C

—

0.5

DIO

1. This parameter is sampled. GV = 1.8 V 0.090 V, f = 1 MHz, T = 25°C, V

= GV /2, V

DD OUT

DD

A

OUT

(peak-to-peak) = 0.2 V.

Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when

GV (typ) = 2.5 V.

DD

Table 14. DDR SDRAM DC Electrical Characteristics for GV

(typ) = 2.5 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GV

MV

2.3

2.7

V

1

2

DD

I/O reference voltage

I/O termination voltage

Input high voltage

0.49 × GV

0.51 × GV

DD

REF

TT

DD

V

MV

– 0.04

+ 0.15

MV

+ 0.04

REF

3

REF

V

GV + 0.3

—

IH

DD

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

19

DDR and DDR2 SDRAM

Table 14. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V (continued)

DD

Parameter/Condition

Symbol

Min

Max

– 0.15

REF

Unit

Notes

Input low voltage

Output leakage current

Output high current (V

V

I

–0.3

–10

MV

V

—

4

IL

10

—

μA

mA

OZ

OH

= 1.95 V)

I

–16.2

16.2

—

OUT

Output low current (V

= 0.35 V)

I

OL

OUT

Notes:

1. GV is expected to be within 50 mV of the DRAM GV at all times.

DD

2. MV

is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver.

REF

DD DD

may not exceed 2% of the DC value.

Peak-to-peak noise on MV

REF

3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

TT

equal to MV . This rail should track variations in the DC level of MV

.

REF

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV

.

DD

Table 15 provides the DDR capacitance when GV_DD(typ)=2.5 V.

Table 15. DDR SDRAM Capacitance for GV (typ) = 2.5 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

Note:

C

6

8

pF

1

IO

C

—

0.5

DIO

1. This parameter is sampled. GV = 2.5 V 0.125 V, f = 1 MHz, T = 25°C, V = GVDD/2,

DD

A

OUT

V

(peak-to-peak) = 0.2 V.

OUT

Table 16 provides the current draw characteristics for MV

.

REF

Table 16. Current Draw Characteristics for MV

REF

Parameter / Condition

Symbol

Min

Max

500

Unit

Note

Current draw for MV

I

—

μA

1

REF

MVREF

1. The voltage regulator for MV

must be able to supply up to 500 μA current.

REF

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

20

DDR and DDR2 SDRAM

6.2

DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1

DDR SDRAM Input AC Timing Specifications

Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GV (typ)=1.8 V.

DD

Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions

Parameter

Symbol

Min

Max

– 0.25

REF

Unit

Notes

AC input low voltage

AC input high voltage

V

—

MV

V

—

IL

V

MV

+ 0.25

REF

—

IH

Table 18 provides the input AC timing specifications for the DDR SDRAM when GV (typ)=2.5 V.

DD

Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions.

Parameter

Symbol

Min

Max

– 0.31

REF

Unit

Notes

AC input low voltage

AC input high voltage

V

—

MV

V

—

IL

V

MV

+ 0.31

REF

—

IH

Table 19 provides the input AC timing specifications for the DDR SDRAM interface.

Table 19. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions.

Parameter

Controller Skew for

Symbol

Min

Max

Unit

Notes

t

ps

1, 2

CISKEW

MDQS—MDQ/MECC/MDM

533 MHz

400 MHz

333 MHz

–300

–365

–390

300

365

390

3

—

Note:

1. t

represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding

CISKEW

bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t

.This can be

DISKEW

determined by the following equation: t

=+/-(T/4 – abs(t

)) where T is the clock period and abs(t

)

DISKEW

CISKEW

is the absolute value of t

.

CISKEW

3. Maximum DDR1 frequency is 400 MHz.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

21

DDR and DDR2 SDRAM

Figure 3 provides the input timing diagram for the DDR SDRAM interface. t

can be calculated

DISKEW

from t

. See Table 19 footnote 2.

CISKEW

MCK[n]

t

MCK

MDQS[n]

MDQ[x]

D0

D1

t

DISKEW

t

DISKEW

Figure 3. DDR SDRAM Input Timing Diagram

6.2.2

DDR SDRAM Output AC Timing Specifications

Table 20. DDR SDRAM Output AC Timing Specifications

At recommended operating conditions.

1

Parameter

Symbol

Min

Max

Unit

Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing

ADDR/CMD output setup with respect to MCK

t

3.75

10

ns

2

3

7

MCK

t

DDKHAS

DDKHAX

DDKHCS

533 MHz

1.48

1.95

2.40

—

400 MHz

333 MHz

ADDR/CMD output hold with respect to MCK

t

ns

3

7

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MCS[n] output setup with respect to MCK

t

3

7

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

22

DDR and DDR2 SDRAM

Table 20. DDR SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions.

1

Parameter

Symbol

Min

Max

Unit

Notes

MCS[n] output hold with respect to MCK

t

ns

3

7

DDKHCX

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

–0.6

—

MCK to MDQS Skew

t

0.6

ns

ps

4

5

DDKHMH

MDQ/MECC/MDM output setup with respect to

MDQS

t

DDKHDS,

t

DDKLDS

533 MHz

400 MHz

333 MHz

538

700

900

—

7

MDQ/MECC/MDM output hold with respect to

MDQS

t

ps

5

7

DDKHDX,

DDKLDX

533 MHz

538

700

900

—

400 MHz

333 MHz

MDQS preamble start

t

–0.5 × t

– 0.6

–0.5 × t +0.6

MCK

ns

6

DDKHMP

DDKHME

MCK

MDQS epilogue end

–0.6

0.6

Note:

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state) (reference)(state)

inputs and t

for outputs. Output hold time can be read as DDR timing

(first two letters of functional block)(reference)(state)(signal)(state)

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H) state until

t

DDKHAS

MCK

outputs (A) are setup (S) or output valid time. Also, t

symbolizes DDR timing (DD) for the time t

memory clock

DDKLDX

MCK

reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.

4. Note that t follows the symbol conventions described in note 1. For example, t describes the DDR timing

DDKHMH

(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t

can be modified through

DDKHMH

control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock

adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set

to the same adjustment value. See the MPC8568E Integrated Communications Processor Reference Manual for a

description and understanding of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t

symbol conventions described in note 1.

follows the

DDKHMP

7. Maximum DDR1 frequency is 400 MHz

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

23

DDR and DDR2 SDRAM

NOTE

For the ADDR/CMD setup and hold specifications in Table 20, it is

assumed that the Clock Control register is set to adjust the memory clocks

by 1/2 applied cycle.

Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).

MCK[n]

t

MCK

t

DDKHMHmax) = 0.6 ns

MDQS

t

DDKHMH(min) = –0.6 ns

Figure 4. Timing Diagram for tDDKHMH

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

24

Freescale Semiconductor

DUART

Figure 5 shows the DDR SDRAM output timing diagram.

MCK[n]

t

MCK

t

,t

DDKHAS DDKHCS

t

,t

DDKHAX DDKHCX

ADDR/CMD

Write A0

NOOP

t

DDKHMP

t

DDKHMH

MDQS[n]

MDQ[x]

t

DDKHME

t

DDKHDS

t

DDKLDS

D0

D1

t

DDKLDX

t

DDKHDX

Figure 5. DDR SDRAM Output Timing Diagram

Figure 6 provides the AC test load for the DDR bus.

GV /2

Output

Z = 50 Ω

0

DD

R = 50 Ω

L

Figure 6. DDR AC Test Load

7 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the

MPC8568E.

7.1

DUART DC Electrical Characteristics

Table 21 provides the DC electrical characteristics for the DUART interface.

Table 21. DUART DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

V

2

OV + 0.3

V

IH

DD

V

– 0.3

0.8

IL

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

25

Ethernet Interface and MII Management

Table 21. DUART DC Electrical Characteristics (continued)

Parameter

Symbol

Min

Max

Unit

Input current

I

—

10

μA

IN

1

(V

= 0 V or V = V

IN DD)

IN

High-level output voltage

(OV = min, I = –100 μA)

V

OV – 0.2

—

V

OH

DD

OH

Low-level output voltage

V

—

0.2

OL

(OV = min, I = 100 μA)

DD

OL

Note:

1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 2 and Table 3.

IN

7.2

DUART AC Electrical Specifications

Table 22 provides the AC timing parameters for the DUART interface.

Table 22. DUART AC Timing Specifications

Parameter

Value

Unit

Notes

Minimum baud rate

Maximum baud rate

Oversample rate

Notes:

CCB clock/1,048,576

CCB clock/16

16

baud

—

1,2

1,3

1,4

1. Guaranteed by design

2. CCB clock refers to the platform clock.

3. Actual attainable baud rate will be limited by the latency of interrupt processing.

th

4. The middle of a start bit is detected as the 8 sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

th

sampled each 16 sample.

8 Ethernet Interface and MII Management

This section provides the AC and DC electrical characteristics for eTSEC, MII management and Ethernet

interface inside QUICC Engine. Note that eTSEC and QE Ethernet have the same DC/AC characteristics.

8.1

GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics

The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media

independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface

(RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals

except management data input/output (MDIO) and management data clock (MDC). The RGMII and RTBI

interfaces are defined for 2.5 V, while the GMII and TBI interfaces can be operated at 3.3 or 2.5 V. Whether

the GMII, MII, or TBI interface is operated at 3.3 or 2.5 V, the timing is compatible with the IEEE 802.3

standard. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface

(RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

26

Freescale Semiconductor

Ethernet Interface and MII Management

Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in

Section 8, “Ethernet Interface and MII Management.”

8.1.1

Ethernet Interface DC Electrical Characteristics

All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric

attributes specified in Table 23 and Table 24. The potential applied to the input of a GMII, MII, TBI,

RGMII, RMII or RTBI receiver may exceed the potential of the receiver’s power supply (that is, a GMII

driver powered from a 3.6-V supply driving V into a GMII receiver powered from a 2.5-V supply).

OH

Tolerance for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The

RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC

EIA/JESD8-5.

Table 23. GMII, MII, RMII, and TBI DC Electrical Characteristics

Parameter

Symbol

LV

Min

Max

Unit

Notes

Supply voltage 3.3 V

Output high voltage

3.135

3.465

V

1, 2

DD

TV

DD

VOH

VOL

2.40

LV /TV + 0.3

V

—

DD

(LV /TV = Min, IOH = –4.0 mA)

DD

Output low voltage

(LV /TV = Min, IOL = 4.0 mA)

GND

0.50

DD

Input high voltage

Input low voltage

V

2.0

LV /TV + 0.3

V

—

IH

DD

V

–0.3

0.90

IL

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

27

Ethernet Interface and MII Management

Table 23. GMII, MII, RMII, and TBI DC Electrical Characteristics (continued)

Parameter

Symbol

Min

Max

Unit

Notes

Input high current

(V = LV , V = TV )

DD

I

—

40

μA

1, 2, 3

IH

IN

DD IN

Input low current

I

–600

—

μA

3

IL

(V = GND)

IN

Notes:

1. LV supports eTSECs 1 and 2.

DD

2. TV supports QE UCC1 and UCC2 ethernet ports.

DD

3. The symbol V , in this case, represents the LV and TV symbols referenced in Table 2 and Table 3.

IN

Table 24. GMII, MII, RMII, RGMII, RTBI, TBI and FIFO DC Electrical Characteristics

Parameters

Symbol

LV /TV

Min

Max

Unit

Notes

Supply voltage 2.5 V

Output high voltage

(LV /TV = Min, IOH = –1.0 mA)

2.37

2.00

2.63

V

1, 2

—

DD

V

LV /TV + 0.3

DD DD

OH

DD

Output low voltage

(LV /TV = Min, I = 1.0 mA)

V

GND – 0.3

0.40

V

—

OL

DD

OL

Input high voltage

Input low voltage

Input high current

V

1.70

–0.3

—

LV /TV + 0.3

V

—

IH

DD

V

I

0.70

IL

10

μA

1, 2, 3

IH

(V = LV , V = TV )

DD

IN

DD IN

Input low current

I

–15

—

μA

3

IL

(V = GND)

IN

Note:

1. LV supports eTSECs 1 and 2.

DD

2. TV supports QE UCC1 and UCC2 ethernet ports.

DD

3. Note that the symbol V , in this case, represents the LV and TV symbols referenced in Table 2 and Table 3.

IN

8.2

FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing

Specifications

The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this

section.

8.2.1

FIFO AC Specifications

The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI

specifications, since they have similar performance and are described in a source-synchronous fashion like

FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and

source clock in GMII fashion.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

28

Freescale Semiconductor

Ethernet Interface and MII Management

When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the

relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,

while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit

clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out

onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is

intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a

source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since

the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is

relationship between the maximum FIFO speed and the platform speed. For more information see Section

4.4, “Platform to FIFO restrictions.

A summary of the FIFO AC specifications appears in Table 25 and Table 26.

Table 25. FIFO Mode Transmit AC Timing Specification

Parameter/Condition

TX_CLK, GTX_CLK clock period

Symbol

Min

Typ

Max

Unit

t

5.0

45

—

8.0

50

100

55

ns

%

FIT

TX_CLK, GTX_CLK duty cycle

t

FITH

TX_CLK, GTX_CLK peak-to-peak jitter

Rise time TX_CLK (20%–80%)

t

—

250

1.5

—

ps

ns

FITJ

t

—

0.75

—

FITR

Fall time TX_CLK (80%–20%)

t

—

FITF

FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK

GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time

t

2.0

FITDV

FITDX

1

t

0.5

—

3.0

Table 26. FIFO Mode Receive AC Timing Specification

Parameter/Condition

RX_CLK clock period

Symbol

Min

Typ

Max

Unit

t

5.0

45

—

8.0

50

100

55

ns

%

FIR

RX_CLK duty cycle

t

/t

FIRH FIRH

RX_CLK peak-to-peak jitter

t

—

250

1.5

—

ps

ns

FIRJ

Rise time RX_CLK (20%–80%)

Fall time RX_CLK (80%–20%)

t

—

0.75

—

FIRR

t

—

FIRF

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

t

1.5

0.5

FIRDV

FIRDX

t

—

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

29

Ethernet Interface and MII Management

Timing diagrams for FIFO appear in Figure 7 and Figure 8.

.

t

FITR

FITF

t

FIT

GTX_CLK

t

FITDX

FITH

FITDV

TXD[7:0]

TX_EN

TX_ER

Figure 7. FIFO Transmit AC Timing Diagram

t

FIRR

t

FIR

RX_CLK

t

FIRH

t

FIRF

RXD[7:0]

RX_DV

RX_ER

valid data

t

FIRDV

FIRDX

Figure 8. FIFO Receive AC Timing Diagram

8.2.2

GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

8.2.2.1

GMII Transmit AC Timing Specifications

Table 27 provides the GMII transmit AC timing specifications.

Table 27. GMII Transmit AC Timing Specifications

At recommended operating conditions with LV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

GTX_CLK clock period

t

—

45

2.5

0.5

—

8.0

—

55

ns

%

GTX

GTX_CLK duty cycle

t

/t

GTXH GTX

GMII data TXD[7:0], TX_ER, TX_EN setup time

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay

GTX_CLK data clock rise time (20%-80%)

GTX_CLK data clock fall time (80%-20%)

EC_GTX_CLK125 clock rise time (20%-80%)

EC_GTX_CLK125 clock fall time (80%-20%)

t

—

ns

GTKHDV

t

—

5.0

2.0

GTKHDX

2

t

1.0

GTXR

2

t

—

GTXF

t

—

G125R

t

—

G125F

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

30

Ethernet Interface and MII Management

Table 27. GMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

/t

Min

Typ

Max

Unit

EC_GTX_CLK125 duty cycle

Notes:

1. The symbols used for timing specifications herein follow the pattern t

t

45

55

ns

G125H G125

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

for outputs. For example, t

symbolizes GMII

(first two letters of functional block)(reference)(state)(signal)(state)

GTKHDV

transmit timing (GT) with respect to the t

clock reference (K) going to the high state (H) relative to the time date input

GTX

signals (D) reaching the valid state (V) to state or setup time. Also, t

symbolizes GMII transmit timing (GT) with respect

GTKHDX

to the t

clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold

GTX

time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a

particular functional. For example, the subscript of t represents the GMII(G) transmit (TX) clock. For rise and fall times,

GTX

the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design

Figure 9 shows the GMII transmit AC timing diagram.

t

GTX

GTXR

GTX_CLK

t

GTXF

GTXH

TXD[7:0]

TX_EN

TX_ER

t

GTKHDX

t

GTKHDV

Figure 9. GMII Transmit AC Timing Diagram

8.2.2.2

GMII Receive AC Timing Specifications

Table 28 provides the GMII receive AC timing specifications.

Table 28. GMII Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

RX_CLK clock period

t

—

40

2.0

0.5

—

8.0

—

60

—

ns

GRX

RX_CLK duty cycle

t

/t

GRXH GRX

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise (20%-80%)

t

—

GRDVKH

t

—

GRDXKH

2

t

1.0

2.0

GRXR

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

31

Ethernet Interface and MII Management

Table 28. GMII Receive AC Timing Specifications (continued)

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

2

RX_CLK clock fall time (80%-20%)

t

—

1.0

2.0

ns

GRXF

Note:

1. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

for outputs. For example, t

symbolizes GMII

(first two letters of functional block)(reference)(state)(signal)(state)

GRDVKH

receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t clock

RX

reference (K) going to the high state (H) or setup time. Also, t

the time data input signals (D) went invalid (X) relative to the t

symbolizes GMII receive timing (GR) with respect to

clock reference (K) going to the low (L) state or hold time.

GRDXKL

GRX

Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For example, the subscript of t represents the GMII (G) receive (RX) clock. For rise and fall times, the latter

GRX

convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design

Figure 10 provides the AC test load for eTSEC.

LV /2

Output

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 10. eTSEC AC Test Load

Figure 11 shows the GMII receive AC timing diagram.

t

GRX

GRXR

RX_CLK

t

GRXF

GRXH

RXD[7:0]

RX_DV

RX_ER

t

GRDXKH

t

GRDVKH

Figure 11. GMII Receive AC Timing Diagram

8.2.3

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

32

Freescale Semiconductor

Ethernet Interface and MII Management

8.2.3.1

MII Transmit AC Timing Specifications

Table 29 provides the MII transmit AC timing specifications.

Table 29. MII Transmit AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

2

TX_CLK clock period 10 Mbps

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

t

—

400

40

—

5

—

ns

%

MTX

t

MTX

t

35

1

65

15

4.0

MTXH/ MTX

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

TX_CLK data clock rise (20%-80%)

TX_CLK data clock fall (80%-20%)

Note:

t

ns

MTKHDX

2

t

1.0

—

MTXR

2

t

MTXF

1. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

for outputs. For example, t

symbolizes MII

(first two letters of functional block)(reference)(state)(signal)(state)

MTKHDX

transmit timing (MT) for the time t

clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

MTX

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter

MTX

convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Figure 12 shows the MII transmit AC timing diagram.

t

MTXR

MTX

TX_CLK

t

MTXH

MTXF

TXD[3:0]

TX_EN

TX_ER

t

MTKHDX

Figure 12. MII Transmit AC Timing Diagram

8.2.3.2

MII Receive AC Timing Specifications

Table 30 provides the MII receive AC timing specifications.

Table 30. MII Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

2

RX_CLK clock period 10 Mbps

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

t

—

35

400

40

—

65

ns

%

MRX

t

MRX

t

/t

—

MRXH MRX

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

33

Ethernet Interface and MII Management

Table 30. MII Receive AC Timing Specifications (continued)

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise (20%-80%)

RX_CLK clock fall time (80%-20%)

Note:

t

10.0

1.0

—

ns

MRDVKH

t

MRDXKH

2

t

4.0

MRXR

2

1.0

MRXF

1. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

for outputs. For example, t

symbolizes MII receive

(first two letters of functional block)(reference)(state)(signal)(state)

MRDVKH

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

clock reference (K)

MRX

going to the high (H) state or setup time. Also, t

symbolizes MII receive timing (GR) with respect to the time data input

MRDXKL

signals (D) went invalid (X) relative to the t

clock reference (K) going to the low (L) state or hold time. Note that, in general,

MRX

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For

example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used

MRX

with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Figure 13 provides the AC test load for eTSEC.

LV /2

Output

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 13. eTSEC AC Test Load

Figure 14 shows the MII receive AC timing diagram.

t

MRXR

MRX

RX_CLK

t

MRXH

MRXF

RXD[3:0]

RX_DV

RX_ER

Valid Data

t

MRDVKH

t

MRDXKL

Figure 14. MII Receive AC Timing Diagram

8.2.4

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

34

Freescale Semiconductor

Ethernet Interface and MII Management

8.2.4.1

TBI Transmit AC Timing Specifications

Table 31 provides the TBI transmit AC timing specifications.

Table 31. TBI Transmit AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

GTX_CLK clock period

t

—

47

2.0

1.0

—

8.0

—

53

ns

%

TTX

GTX_CLK duty cycle

t

/t

TTXH TTX

TCG[9:0] setup time GTX_CLK going high

TCG[9:0] hold time from GTX_CLK going high

GTX_CLK rise (20%–80%)

t

—

ns

TTKHDV

3

t

—

TTKHDX

2

t

1.0

—

2.0

55

TTXR

2

GTX_CLK fall time (80%–20%)

EC_GTX_CLK125 clock rise time (20%-80%)

EC_GTX_CLK125 clock fall time (80%-20%)

EC_GTX_CLK125 duty cycle

Notes:

t

—

TTXF

t

—

G125R

t

—

G125F

t

/t

45

G125H G125

1. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state

for inputs and t

for outputs. For example,

)(reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

t

symbolizes the TBI transmit timing (TT) with respect to the time from t

(K) going high (H) until the

TTKHDV

TTX

referenced data signals (D) reach the valid state (V) or setup time. Also, t

symbolizes the TBI transmit timing

TTKHDX

(TT) with respect to the time from t

(K) going high (H) until the referenced data signals (D) reach the invalid state

TTX

(X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters

representing the clock of a particular functional. For example, the subscript of t represents the TBI (T) transmit

TTX

(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

Figure 15 shows the TBI transmit AC timing diagram.

t

TTX

TTXR

GTX_CLK

TCG[9:0]

t

TTXH

t

TTXF

t

TTXF

t

TTXR

TTKHDV

t

TTKHDX

Figure 15. TBI Transmit AC Timing Diagram

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

35

Ethernet Interface and MII Management

8.2.4.2

TBI Receive AC Timing Specifications

Table 32 provides the TBI receive AC timing specifications.

Table 32. TBI Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

PMA_RX_CLK[0:1] clock period

PMA_RX_CLK[0:1] skew

t

—

7.5

40

16.0

—

8.5

60

ns

%

TRX

t

SKTRX

PMA_RX_CLK[0:1] duty cycle

t

/t

—

TRXH TRX

RCG[9:0] setup time to rising PMA_RX_CLK

RCG[9:0] hold time to rising PMA_RX_CLK

PMA_RX_CLK[0:1] clock rise time (20%-80%)

PMA_RX_CLK[0:1] clock fall time (80%-20%)

Note:

t

2.5

1.5

0.7

—

ns

TRDVKH

t

—

TRDXKH

2

t

—

2.4

TRXR

2

t

—

TRXF

1. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state)

for inputs and t

for outputs. For example,

(reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

t

symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V)

TRDVKH

relative to the t

clock reference (K) going to the high (H) state or setup time. Also, t

symbolizes TBI

TRX

TRDXKH

receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the t

clock reference

TRX

(K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three

letters representing the clock of a particular functional. For example, the subscript of t represents the TBI (T)

TRX

receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).

2. Guaranteed by design.

Figure 16 shows the TBI receive AC timing diagram.

t

TRX

TRXR

PMA_RX_CLK1

RCG[9:0]

t

TRXH

TRXF

Valid Data

t

TRDVKH

t

SKTRX

TRDXKH

PMA_RX_CLK0

t

TRXH

TRDXKH

t

TRDVKH

Figure 16. TBI Receive AC Timing Diagram

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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36

Ethernet Interface and MII Management

8.2.5

TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant

eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1 a 125-MHz TBI receive clock

is supplied on TSECn TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode,

whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied

on the TSEC_GTX_CLK125 pin in all TBI modes.

A summary of the single-clock TBI mode AC specifications for receive appears in Table 33.

Table 33. TBI single-clock Mode Receive AC Timing Specification

Parameter/Condition

RX_CLK clock period

Symbol

Min

Typ

Max

Unit

t

7.5

40

—

8.0

50

—

8.5

60

ns

%

TRR

RX_CLK duty cycle

t

TRRH

RX_CLK peak-to-peak jitter

t

250

2.0

—

ps

ns

TRRJ

TRRR

Rise time RX_CLK (20%–80%)

Fall time RX_CLK (80%–20%)

RCG[9:0] setup time to RX_CLK rising edge

RCG[9:0] hold time to RX_CLK rising edge

—

1.0

—

t

—

TRRF

t

2.0

1.0

TRRDV

TRRDX

t

—

A timing diagram for TBI receive appears in Figure 17.

.

t

TRRR

t

TRR

RX_CLK

RCG[9:0]

t

TRRH

t

TRRF

valid data

t

TRRDV

TRRDX

Figure 17. TBI Single-Clock Mode Receive AC Timing Diagram

8.2.6

RGMII and RTBI AC Timing Specifications

Table 34 presents the RGMII and RTBI AC timing specifications.

Table 34. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LV_DDof 2.5 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

5

6

Data to clock output skew (at transmitter)

t

–500

1.0

0

500

ps

ns

SKRGT

2

Data to clock input skew (at receiver)

t

—

2.8

8.8

SKRGT

5

3

Clock period duration

t

7.2

8.0

RGT

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

37

Ethernet Interface and MII Management

Table 34. RGMII and RTBI AC Timing Specifications (continued)

At recommended operating conditions with LV_DDof 2.5 V 5%.

3, 4

5

Duty cycle for 10BASE-T and 100BASE-TX

t

/t

40

—

47

50

60

1.5

53

%

ns

RGTH RGT

5

Rise time (20%–80%)

t

0.75

RGTR

5

Fall time (20%–80%)

t

RGTF

EC_GTX_CLK125 clock rise time (20%-80%)

EC_GTX_CLK125 clock fall time (80%-20%)

t

G125R

t

G125F

6

EC_GTX_CLK125 duty cycle

t

/t

G125H G125

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to

represent RGMII and RTBI timing. For example, the subscript of t represents the TBI (T) receive (RX) clock. Note

RGT

also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols

representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than

1.5 ns will be added to the associated clock signal.

3. For 10 and 100 Mbps, t

scales to 400 ns 40 ns and 40 ns 4 ns, respectively.

RGT

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains

as long as the minimum duty cycle is not violated and stretching occurs for no more than three t

transitioned between.

of the lowest speed

RGT

5. Guaranteed by characterization

6. EC_GTX_CLK125 is used to generate GTX_CLK for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125

duty cycle can be loosen from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC

GTX_CLK.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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Freescale Semiconductor

Ethernet Interface and MII Management

Figure 18 shows the RGMII and RTBI AC timing and multiplexing diagrams.

t

RGT

t

RGTH

GTX_CLK

(At Transmitter)

t

SKRGT

TXD[8:5][3:0]

TXD[7:4][3:0]

TXD[8:5]

TXD[7:4]

TXD[3:0]

TXD[9]

TXERR

TXD[4]

TXEN

TX_CTL

t

SKRGT

TX_CLK

(At PHY)

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[8:5]

RXD[7:4]

RXD[3:0]

t

SKRGT

RXD[9]

RXERR

RXD[4]

RXDV

RX_CTL

t

SKRGT

RX_CLK

(At PHY)

Figure 18. RGMII and RTBI AC Timing and Multiplexing Diagrams

8.2.7

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.7.1

RMII Transmit AC Timing Specifications

The RMII transmit AC timing specifications are in Table 35.

Table 35. RMII Transmit AC Timing Specifications

At recommended operating conditions with LV_DDof 3.3 V 5%.

1

Parameter/Condition

REF_CLK clock period

Symbol

Min

15.0

35

Typ

20.0

50

Max

25.0

65

Unit

ns

t

RMT

t

REF_CLK duty cycle

%

RMTH

t

REF_CLK peak-to-peak jitter

Rise time REF_CLK (20%–80%)

Fall time REF_CLK (80%–20%)

—

250

2.0

ps

RMTJ

t

1.0

—

ns

RMTR

t

—

2.0

ns

RMTF

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

39

Ethernet Interface and MII Management

Table 35. RMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LV_DDof 3.3 V 5%.

1

Parameter/Condition

REF_CLK to RMII data TXD[1:0], TX_EN delay

Note:

Symbol

Min

Typ

Max

Unit

t

1.0

—

10.0

ns

RMTDX

1. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state)

for inputs and t

for outputs. For example,

(reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

t

symbolizes MII transmit timing (MT) for the time t

clock reference (K) going high (H) until data outputs

MTX

MTKHDX

(D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters

representing the clock of a particular functional. For example, the subscript of t represents the MII(M) transmit

MTX

(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

Figure 19 shows the RMII transmit AC timing diagram.

t

RMTR

RMT

REF_CLK

t

RMTH

RMTF

TXD[1:0]

TX_EN

TX_ER

t

RMTDX

Figure 19. RMII Transmit AC Timing Diagram

8.2.7.2

RMII Receive AC Timing Specifications

Table 36. RMII Receive AC Timing Specifications

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

t

REF_CLK clock period

15.0

35

20.0

50

—

25.0

65

ns

%

RMR

t

REF_CLK duty cycle

RMRH

t

REF_CLK peak-to-peak jitter

Rise time REF_CLK (20%–80%)

Fall time REF_CLK (80%–20%)

—

250

2.0

ps

ns

RMRJ

t

1.0

—

RMRR

t

—

RMRF

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK

rising edge

t

4.0

—

ns

RMRDV

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

40

Ethernet Interface and MII Management

Table 36. RMII Receive AC Timing Specifications (continued)

At recommended operating conditions with L/TV_DDof 3.3 V 5%.

1

Parameter/Condition

Symbol

Min

Typ

Max

Unit

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK

rising edge

t

2.0

—

ns

RMRDX

Note:

1. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state)

for inputs and t

for outputs. For example,

(reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

t

symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V)

MRDVKH

relative to the t

clock reference (K) going to the high (H) state or setup time. Also, t

symbolizes MII

MRX

MRDXKL

receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the t

clock reference

MRX

(K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based

on three letters representing the clock of a particular functional. For example, the subscript of t represents the

MRX

MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise)

or F (fall).

Figure 20 provides the AC test load for eTSEC.

LV /2

Output

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 20. eTSEC AC Test Load

Figure 21 shows the RMII receive AC timing diagram.

t

RMR

RMRR

REF_CLK

t

RMRF

RMRH

RXD[1:0]

CRS_DV

RX_ER

Valid Data

t

RMRDV

t

RMRDX

Figure 21. RMII Receive AC Timing Diagram

8.3

Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock).

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

41

Ethernet Interface and MII Management

8.3.1

MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics

for MDIO and MDC are provided in Table 37.

Table 37. MII Management DC Electrical Characteristics

Parameters

Symbol

OV

Min

Max

Unit

Supply voltage 3.3 V

Output high voltage

(OV = Min, I = –1.0 mA)

3.13

2.10

3.47

V

DD

V

OV + 0.3

OH

DD

OH

Output low voltage

(OV = Min, I = 1.0 mA)

V

GND

0.50

V

OL

DD

OL

Input high voltage

Input low voltage

Input high current

V

2.0

—

0.90

40

V

IH

V

I

IL

—

μA

IH

1

(OV = Max, V = 2.1 V)

DD

IN

Input low current

I

–600

—

μA

IL

1

(OV = Max, V = 0.5 V)

DD

IN

Note:

1. The symbol V , in this case, represents the OV symbols referenced in Table 2 and Table 3.

IN

8.3.2

MII Management AC Electrical Characteristics

Table 38 provides the MII management AC timing specifications.

Table 38. MII management AC timing specifications

Parameters

MDC frequency

Symbol

Min

Max

Unit

Notes

f

—

2.5

MHz

2

MDC

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

42

Ethernet Interface and MII Management

Table 38. MII management AC timing specifications (continued)

Parameters

Symbol

Min

Max

Unit

Notes

MDC period

t

400

32

—

ns

2

—

3, 5

—

4

MDC

MDC clock pulse width high

MDC to MDIO delay

MDIO to MDC setup time

MDIO to MDC hold time

MDC rise time

t

MDCH

t

(16*t

)-3

(16*t

)+3

MDKHDX

MDDVKH

MDDXKH

plb_clk

5

—

0

—

10

t

—

MDCR

MDC fall time

t

4

MDCF

Note:

1. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state)

for inputs and t

for outputs. For example,

(first two letters of functional block)(reference)(state)(signal)(state)

(reference)(state)

t

symbolizes management data timing (MD) for the time t

from clock reference (K) high (H) until data

MDKHDX

MDC

outputs (D) are invalid (X) or data hold time. Also, t

symbolizes management data timing (MD) with respect

MDDVKH

to the time data input signals (D) reach the valid state (V) relative to the t

clock reference (K) going to the high

MDC

(H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F

(fall).

2. IEEE 802.3 standard specifies that the max MDC frequency to be 2.5MHz. The frequency is programmed through

MIIMCFG[MgmtClk].

3. This parameter is dependent on the platform clock speed. The delay is equal to 16 platform clock periods +/-3ns. With a

platform clock of 333MHz, the min/max delay is 48ns +/- 3ns.

4. Guaranteed by design

5. t

is the platform (CCB) clock period.

plb_clk

6. MDC to MDIO data valid t

time – Max delay).

is a function of clock period and max delay time (t

). (Min Setup time = Cycle

MDKHDV

MDKHDX

Figure 22 shows the MII management AC timing diagram.

Figure 22. MII Management Interface Timing Diagram

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

43

Local Bus

9 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the MPC8568.

9.1

Local Bus DC Electrical Characteristics

Table 39 provides the DC electrical characteristics for the local bus interface operating at BV = 3.3 V

DD

DC.

Table 39. Local Bus DC Electrical Characteristics (3.3 V DC)

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

V

2

BV + 0.3

V

IH

DD

V

I

–0.3

—

0.8

5

IL

Input current

μA

IN

1

(V

= 0 V or V = BV

)

DD

IN

High-level output voltage

(BV = min, I = –2 mA)

V

2.4

—

V

OH

DD

OH

Low-level output voltage

V

0.4

OL

(BV = min, I = 2 mA)

DD

OL

Note:

1. The symbol V , in this case, represents the BV symbol referenced in Table 2 and Table 3.

IN

Table 40 provides the DC electrical characteristics for the local bus interface operating at BV = 2.5 V

DD

DC.

Table 40. Local Bus DC Electrical Characteristics (2.5 V DC)

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

V

1.70

–0.3

—

BV + 0.3

V

IH

DD

V

I

0.7

10

IL

Input current

μA

IH

1

(V

= 0 V or V = BV

)

DD

IN

I

–15

—

IL

High-level output voltage

(BV = min, I = –1 mA)

V

2.0

—

V

OH

DD

OH

Low-level output voltage

V

0.4

OL

(BV = min, I = 1 mA)

DD

OL

Note:

1. The symbol V , in this case, represents the BV symbol referenced in Table 2 and Table 3.

IN

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

44

Local Bus

9.2

Local Bus AC Electrical Specifications

Table 41 describes the timing parameters of the local bus interface at BV = 3.3 V. For information about

DD

the frequency range of local bus see Section 23.1, “Clock Ranges.”

Table 41. Local Bus Timing Parameters (BV = 3.3 V)—PLL Enabled

DD

1

Parameter

Symbol

Min

Max

Unit Notes

Local bus cycle time

Local bus duty cycle

t

7.5

43

12

57

ns

%

2

—

7, 8

3, 4

6

LBK

t

LBKH/ LBK

LCLK[n] skew to LCLK[m] or LSYNC_OUT

t

—

150

—

ps

ns

LBKSKEW

Input setup to local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input setup to local bus clock

t

1.8

1.7

1.0

1.5

—

LBIVKH1

LBIVKH2

LBIXKH1

LBIXKH2

—

Input hold from local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input hold from local bus clock

LALE output transition to LAD/LDP output transition (LATCH hold time)

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

—

t

—

LBOTOT

t

3.0

3.2

—

3

LBKHOV1

t

—

LBKHOV2

Local bus clock to address valid for LAD

t

—

3

LBKHOV3

Local bus clock to LALE assertion

t

—

3

LBKHOV4

Output hold from local bus clock (except LAD/LDP and LALE)

Output hold from local bus clock for LAD/LDP

t

0.7

—

3

LBKHOX1

t

—

3

LBKHOX2

Local bus clock to output high Impedance (except LAD/LDP and LALE)

Local bus clock to output high impedance for LAD/LDP

t

2.5

5

LBKHOZ1

t

—

5

LBKHOZ2

Note:

1. The symbols used for timing specifications herein follow the pattern of t

(First two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

for outputs. For example, t

symbolizes local bus

(First two letters of functional block)(reference)(state)(signal)(state)

LBIXKH1

timing (LB) for the input (I) to go invalid (X) with respect to the time the t

clock reference (K) goes high (H), in this case for

LBK

clock one(1). Also, t

symbolizes local bus timing (LB) for the t

clock reference (K) to go high (H), with respect to the

LBKHOX

LBK

output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

DD

bypass mode to 0.4 × BV of the signal in question for 3.3-V signaling levels.

DD

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

6. t

is a measurement of the minimum time between the negation of LALE and any change in LAD. t

is

LBOTOT

programmed with the LBCR[AHD] parameter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BV /2.

DD

8. Guaranteed by design.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

45

Local Bus

Table 42 describes the timing parameters of the local bus interface at BV = 2.5 V.

DD

Table 42. Local Bus Timing Parameters (BV = 2.5 V)—PLL Enabled

DD

1

Parameter

Local bus cycle time

Symbol

Min

Max

Unit

Notes

t

7.5

43

—

12

57

ns

%

2

LBK

Local bus duty cycle

t

—

LBKH/ LBK

LCLK[n] skew to LCLK[m] or LSYNC_OUT

t

150

—

ps

ns

7, 8

3, 4

LBKSKEW

Input setup to local bus clock (except

LGTA/UPWAIT)

t

1.9

LBIVKH1

LGTA/LUPWAIT input setup to local bus clock

t

1.8

1.1

—

ns

3, 4

LBIVKH2

Input hold from local bus clock (except

LGTA/LUPWAIT)

t

LBIXKH1

LGTA/LUPWAIT input hold from local bus clock

t

1.1

1.5

—

ns

3, 4

6

LBIXKH2

LALE output transition to LAD/LDP output

transition (LATCH hold time)

t

LBOTOT

Local bus clock to output valid (except

LAD/LDP and LALE)

t

—

3.0

ns

—

LBKHOV1

Local bus clock to data valid for LAD/LDP

Local bus clock to address valid for LAD

Local bus clock to LALE assertion

t

—

3.2

—

ns

3

LBKHOV2

t

LBKHOV3

t

—

LBKHOV4

LBKHOX1

Output hold from local bus clock (except

LAD/LDP and LALE)

0.8

Output hold from local bus clock for LAD/LDP

t

0.8

—

ns

3

5

LBKHOX2

Local bus clock to output high Impedance

(except LAD/LDP and LALE)

t

2.6

LBKHOZ1

Local bus clock to output high impedance for

LAD/LDP

t

—

2.6

ns

5

LBKHOZ2

Note:

1. The symbols used for timing specifications herein follow the pattern of t

(First two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

for outputs. For example, t

symbolizes local bus

(First two letters of functional block)(reference)(state)(signal)(state)

LBIXKH1

timing (LB) for the input (I) to go invalid (X) with respect to the time the t

clock reference (K) goes high (H), in this case for

LBK

clock one(1). Also, t

symbolizes local bus timing (LB) for the t

clock reference (K) to go high (H), with respect to the

LBKHOX

LBK

output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BV /2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

DD

bypass mode to 0.4 × BV of the signal in question for 3.3-V signaling levels.

DD

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through

the component pin is less than or equal to the leakage current specification.

6. t

is a measurement of the minimum time between the negation of LALE and any change in LAD. t

is programmed

LBOTOT

with the LBCR[AHD] parameter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

DD

complementary signals at BV /2.

8. Guaranteed by design.

Figure 23 provides the AC test load for the local bus.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

46

Freescale Semiconductor

Local Bus

Output

BV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 23. Local Bus AC Test Load

NOTE

PLL bypass mode is required when LBIU frequency is at or below 83 MHz.

When LBIU operates above 83 MHz, LBIU PLL is recommended to be

enabled.

Figure 24 to Figure 29 show the local bus signals.

LSYNC_IN

t

LBIXKH1

t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIXKH2

LBIVKH2

Input Signal:

LGTA

LUPWAIT

t

LBKHOZ1

LBKHOX1

t

LBKHOV1

LBKHOV2

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

t

LBKHOZ2

LBKHOX2

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t

LBKHOZ2

LBKHOX2

t

LBKHOV3

Output (Address) Signal:

LAD[0:31]

t

LBOTOT

t

LBKHOV4

LALE

Figure 24. Local Bus Signals (PLL Enabled)

Table 43 describes the timing parameters of the local bus interface at BV = 3.3 V with PLL disabled.

DD

Table 43. Local Bus Timing Parameters—PLL Bypassed

1

Parameter

Symbol

Min

Max

Unit Notes

Local bus cycle time

Local bus duty cycle

t

12

43

—

ns

%

2

LBK

t

57

—

LBKH/ LBK

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

47

Local Bus

Table 43. Local Bus Timing Parameters—PLL Bypassed (continued)

1

Parameter

Symbol

Min

Max

Unit Notes

Internal launch/capture clock to LCLK delay

t

2.3

6.2

6.1

–1.8

–1.3

1.5

—

4.4

—

ns

8

4, 5

6

LBKHKT

Input setup to local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input setup to local bus clock

t

LBIVKH1

t

—

LBIVKL2

LBIXKH1

Input hold from local bus clock (except LGTA/LUPWAIT)

LGTA/LUPWAIT input hold from local bus clock

t

—

t

—

LBIXKL2

LALE output transition to LAD/LDP output transition (LATCH hold time)

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

t

—

LBOTOT

t

-0.3

-0.1

0

—

4

LBKLOV1

t

—

LBKLOV2

Local bus clock to address valid for LAD

t

—

4

LBKLOV3

Local bus clock to LALE assertion

t

—

0

4

LBKLOV4

Output hold from local bus clock (except LAD/LDP and LALE)

Output hold from local bus clock for LAD/LDP

t

–3.7

—

4

LBKLOX1

LBKLOX2

LBKLOZ1

LBKLOZ2

—

4

Local bus clock to output high Impedance (except LAD/LDP and LALE)

Local bus clock to output high impedance for LAD/LDP

0.2

7

—

7

Notes:

1. The symbols used for timing specifications herein follow the pattern of t

(First two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

for outputs. For example, t

symbolizes local bus

(First two letters of functional block)(reference)(state)(signal)(state)

LBIXKH1

timing (LB) for the input (I) to go invalid (X) with respect to the time the t

clock reference (K) goes high (H), in this case for

LBK

clock one(1). Also, t

symbolizes local bus timing (LB) for the t

clock reference (K) to go high (H), with respect to the

LBKHOX

LBK

output (O) going invalid (X) or output hold time.

2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus

clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK

by t

.

LBKHKT

3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BV /2.

DD

4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal

in question for 3.3-V signaling levels.

5. Input timings are measured at the pin.

6. The value of t

is the measurement of the minimum time between the negation of LALE and any change in LAD

LBOTOT

7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through

the component pin is less than or equal to the leakage current specification.

8. Guaranteed by characterization.

9. Guaranteed by design.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

48

Freescale Semiconductor

Local Bus

Internal launch/capture clock

LCLK[n]

t

LBKHKT

t

LBIVKH1

t

LBIXKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIVKL2

Input Signal:

LGTA

t

LBIXKL2

LUPWAIT

t

LBKLOV1

t

LBKLOZ1

LBKLOZ2

t

LBKLOX1

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

t

LBKLOV2

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t

LBKLOX2

LBKLOV3

Output (Address) Signal:

LAD[0:31]

t

LBKLOV4

LBOTOT

LALE

Figure 25. Local Bus Signals (PLL Bypass Mode)

NOTE

In PLL bypass mode, LCLK[n] is the inverted version of the internal clock

with the delay of t_LBKHKT.In this mode, signals are launched at the rising edge

of the internal clock and are captured at falling edge of the internal clock

with the exception of LGTA/LUPWAIT (which is captured on the rising

edge of the internal clock).

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

49

Local Bus

LSYNC_IN

T1

T3

t

LBKHOZ1

LBKHOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

GPCM Mode Input Signal:

LGTA

t

LBIVKH2

t

LBIXKH2

UPM Mode Input Signal:

LUPWAIT

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIXKH1

t

LBKHOV1

LBKHOZ1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Enabled)

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

50

Local Bus

Internal launch/capture clock

T1

T3

LCLK

t

LBKLOX1

LBKLOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

t

LBKLOZ1

GPCM Mode Input Signal:

LGTA

t

LBIVKL2

t

LBIXKL2

UPM Mode Input Signal:

LUPWAIT

t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIXKH1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode)

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

51

Local Bus

LSYNC_IN

T1

T2

T3

T4

t

LBKHOV1

LBKHOZ1

GPCM Mode Output Signals:

LCS[0:7]/LWE

GPCM Mode Input Signal:

LGTA

t

LBIVKH2

t

LBIXKH2

UPM Mode Input Signal:

LUPWAIT

t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIXKH1

t

LBKHOV1

LBKHOZ1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Enabled)

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

52

Local Bus

Internal launch/capture clock

T1

T2

T3

T4

LCLK

t

LBKLOX1

LBKLOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

t

LBKLOZ1

GPCM Mode Input Signal:

LGTA

t

LBIVKL2

t

LBIXKL2

UPM Mode Input Signal:

LUPWAIT

t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t

LBIXKH1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 29. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Bypass Mode)

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

53

JTAG

10 JTAG

This section describes the DC and AC electrical specifications for the IEEE Std 1149.1™ (JTAG) interface

of the MPC8568E.

10.1 JTAG DC Electrical Characteristics

Table provides the DC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8568E.

Table 44. JTAG DC Electrical Characteristics

Parameter

Output high voltage

Symbol

Condition

Min

Max

Unit

V

I

= -6.0 mA

= 6.0 mA

= 3.2 mA

—

2.4

—

V

OH

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

0.5

0.4

OL

—

V

OL

V

2.5

-0.3

—

OV + 0.3

V

IH

DD

V

—

0.8

10

V

IL

I

0 < V < OV

DD

uA

IN

10.2 JTAG AC Electrical Characteristics

Table 45 provides the JTAG AC timing specifications as defined in Figure 31 through Figure 33.

1

Table 45. JTAG AC Timing Specifications (Independent of SYSCLK)

At recommended operating conditions (see Table 3).

2

Parameter

Symbol

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time

f

0

33.3

—

MHz

ns

—

6

JTG

t

30

15

0

t

—

ns

JTKHKL

t

& t

2

ns

JTGR

JTGF

t

25

—

ns

3

TRST

Input setup times:

ns

t

4

0

—

4

5

Boundary-scan data

JTDVKH

t

TMS, TDI

JTIVKH

Input hold times:

Valid times:

ns

20

25

—

Boundary-scan data

TMS, TDI

JTDXKH

t

JTIXKH

t

4

20

25

Boundary-scan data

TDO

JTKLDV

JTKLOV

Output hold times:

t

30

—

Boundary-scan data

TDO

JTKLDX

JTKLOX

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

54

JTAG

1

Table 45. JTAG AC Timing Specifications (Independent of SYSCLK) (continued)

At recommended operating conditions (see Table 3).

2

Parameter

Symbol

Min

Max

Unit

Notes

JTAG external clock to output high impedance:

ns

t

3

19

9

5, 6

Boundary-scan data

TDO

JTKLDZ

t

JTKLOZ

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t

to the midpoint of the signal in question.

TCLK

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 30).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

for outputs. For example, t

symbolizes JTAG

(first two letters of functional block)(reference)(state)(signal)(state)

JTDVKH

device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

clock reference

JTG

(K) going to the high (H) state or setup time. Also, t

symbolizes JTAG timing (JT) with respect to the time data input

JTDXKH

signals (D) went invalid (X) relative to the t

clock reference (K) going to the high (H) state. Note that, in general, the clock

JTG

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t

.

TCLK

5. Non-JTAG signal output timing with respect to t

6. Guaranteed by design

.

TCLK

Figure 30 provides the AC test load for TDO and the boundary-scan outputs.

Z = 50 Ω

OV /2

Output

0

DD

R = 50 Ω

L

Figure 30. AC Test Load for the JTAG Interface

Figure 31 provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

t

JTKHKL

JTGR

t

JTGF

JTG

VM = Midpoint Voltage (OV /2)

DD

Figure 31. JTAG Clock Input Timing Diagram

Figure 32 provides the TRST timing diagram.

TRST

VM

t

TRST

VM = Midpoint Voltage (OV /2)

DD

Figure 32. TRST Timing Diagram

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

55

I²C

Figure 33 provides the boundary-scan timing diagram.

JTAG

VM

External Clock

t

JTDVKH

t

JTDXKH

Boundary

Data Inputs

Input

Data Valid

t

JTKLDV

t

JTKLDX

Boundary

Data Outputs

Output Data Valid

t

JTKLDZ

Boundary

Data Outputs

Output Data Valid

VM = Midpoint Voltage (OV /2)

DD

Figure 33. Boundary-Scan Timing Diagram

11 I²C

2

This section describes the DC and AC electrical characteristics for the I C interfaces of the MPC8568E.

2

Note that I C2 is multiplexed with QE Port C.

PC[18] IIC2_SCL

PC[19] IIC2_SDA

2

11.1 I C DC Electrical Characteristics

2

Table 46 provides the DC electrical characteristics for the I C interfaces.

2

Table 46. I C DC Electrical Characteristics

At recommended operating conditions with OV_DDof 3.3 V 5%.

Parameter

Symbol

Min

Max

Unit Notes

Input high voltage level

Input low voltage level

Low level output voltage

V

0.7 × OV

OV + 0.3

V

—

1

IH

DD

V

–0.3

0

0.3 × OV

IL

DD

V

0.4

50

10

V

OL

Pulse width of spikes which must be suppressed by the input filter

t

0

ns

μA

2

I2KHKL

Input current each I/O pin (input voltage is between 0.1 × OV and

I

–10

3

DD

I

0.9 × OV (max)

DD

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

56

I²C

2

Table 46. I C DC Electrical Characteristics (continued)

At recommended operating conditions with OV_DDof 3.3 V 5%.

Parameter

Symbol

Min

Max

Unit Notes

pF

Capacitance for each I/O pin

C

—

10

—

I

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. Refer to the MPC8568E PowerQUICC III Integrated Communications Processor Reference Manual for information on the

digital filter used.

3. I/O pins will obstruct the SDA and SCL lines if OV is switched off.

DD

2

11.2 I C AC Electrical Specifications

2

Table 47 provides the AC timing parameters for the I C interfaces.

2

Table 47. I C AC Electrical Specifications

At recommended operating conditions with OV_DDof 3.3V 5%. All values refer to V_IH(min) and V_IL(max) levels (see Table 46).

1

Parameter

Symbol

Min

Max

Unit

SCL clock frequency

f

0

400

—

kHz

μs

I2C

Low period of the SCL clock

High period of the SCL clock

t

1.3

0.6

I2CL

t

—

μs

I2CH

Setup time for a repeated START condition

t

—

μs

I2SVKH

Hold time (repeated) START condition (after this period, the first clock

pulse is generated)

t

—

μs

I2SXKL

Data setup time

t

100

—

ns

I2DVKH

Data input hold time:

t

μs

I2DXKL

I2OVKL

—

CBUS compatible masters

2

0

I C bus devices

3

Data output delay time

t

—

0.6

0.9

μs

V

Set-up time for STOP condition

t

—

I2PVKH

Bus free time between a STOP and START condition

t

1.3

I2KHDX

Noise margin at the LOW level for each connected device (including

hysteresis)

V

0.1 × OV

NL

DD

Noise margin at the HIGH level for each connected device (including

hysteresis)

V

0.2 × OV

—

V

NH

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

57

I²C

2

Table 47. I C AC Electrical Specifications (continued)

At recommended operating conditions with OV_DDof 3.3V 5%. All values refer to V_IH(min) and V_IL(max) levels (see Table 46).

1

Parameter

Capacitive load for each bus line

Symbol

Min

Max

Unit

C

—

400

pF

b

Note:

1.The symbols used for timing specifications herein follow the pattern t

for

(first two letters of functional block)(signal)(state) (reference)(state)

2

inputs and t

for outputs. For example, t

symbolizes I C timing (I2)

(first two letters of functional block)(reference)(state)(signal)(state)

I2DVKH

with respect to the time data input signals (D) reach the valid state (V) relative to the t clock reference (K) going to the high

I2C

2

(H) state or setup time. Also, t

(S) went invalid (X) relative to the t

symbolizes I C timing (I2) for the time that the data with respect to the START condition

clock reference (K) going to the low (L) state or hold time. Also, t

I2SXKL

2

symbolizes I C

I2C

I2PVKH

timing (I2) for the time that the data with respect to the STOP condition (P) reaching the valid state (V) relative to the t

clock reference (K) going to the high (H) state or setup time.

I2C

2. As a transmitter, the MPC8568 provides a delay time of at least 300 ns for the SDA signal (referred to the V min of the SCL

IH

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP condition.

2

When the MPC8568 acts as the I C bus master while transmitting, the MPC8568 drives both SCL and SDA. As long as the

load on SCL and SDA are balanced, the MPC8568 would not cause unintended generation of START or STOP condition.

Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay

time is required for the MPC8568 as transmitter, application note AN2919 referred to in note 4 below is recommended.

3. The maximum t

has only to be met if the device does not stretch the LOW period (t

) of the SCL signal.

I2CL

I2DXKL

2

4.The requirements for I C frequency calculation must be followed. Refer to Freescale application note AN2919, Determining

2

the I C Frequency Divider Ratio for SCL

2

Figure 30 provides the AC test load for the I C.

Output

OV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

2

Figure 34. I C AC Test Load

2

Figure 35 shows the AC timing diagram for the I C bus.

SDA

t

I2KHKL

I2DVKH

t

I2SXKL

I2CL

SCL

t

I2CH

I2SVKH

I2SXKL

I2PVKH

t

I2DXKL

S

Sr

P

S

2

Figure 35. I C Bus AC Timing Diagram

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

58

PCI

12 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the MPC8568E.

12.1 PCI DC Electrical Characteristics

Table 48 provides the DC electrical characteristics for the PCI interface.

1

Table 48. PCI DC Electrical Characteristics

Parameter

Symbol

Min

Max

OV + 0.3

Unit

High-level input voltage

Low-level input voltage

V

0.5*OV

–0.5

—

V

IH

DD

V

I

0.3*OV

10

IL

DD

Input current

μA

IN

1

(V

= 0 V or V = V

)

DD

IN

High-level output voltage

(OV = min, I = –500 μA)

V

0.9*OV

—

V

OH

DD

OH

Low-level output voltage

V

0.1*OV

OL

DD

(OV = max, I = 1500 μA)

DD

OL

Notes:

1. The symbol V , in this case, represents the OV symbol referenced in Table 2 and Table 3.

IN

12.2 PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is

used as the PCI input clock. Table 49 provides the PCI AC timing specifications at 66 MHz.

Table 49. PCI AC Timing Specifications at 66 MHz

1

Parameter

SYSCLK to output valid

Symbol

Min

Max

Unit

Notes

t

—

2.0

—

6.0

—

ns

2, 3

PCKHOV

PCKHOX

PCKHOZ

Output hold from SYSCLK

SYSCLK to output high impedance

Input setup to SYSCLK

2, 10

14

—

2, 4, 11

2, 5, 10

t

3.0

0

PCIVKH

PCIXKH

Input hold from SYSCLK

t

—

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

59

PCI

Table 49. PCI AC Timing Specifications at 66 MHz (continued)

1

Parameter

Symbol

Min

Max

Unit

Notes

HRESET high to first FRAME assertion

Notes:

t

10

—

clocks

8, 11

PCRHFV

1. Note that the symbols used for timing specifications herein follow the pattern of t

(first two letters of functional

for inputs and t

for outputs. For

block)(signal)(state) (reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

example, t

symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)

PCIVKH

relative to the SYSCLK clock, t

, reference (K) going to the high (H) state or setup time. Also, t

symbolizes

SYS

PCRHFV

PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the

valid (V) state.

2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.

3. All PCI signals are measured from OV /2 of the rising edge of PCI_CLK to 0.4 × OV of the signal in question

DD

for 3.3-V PCI signaling levels.

4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current

delivered through the component pin is less than or equal to the leakage current specification.

5. Input timings are measured at the pin.

6. The timing parameter t

indicates the minimum and maximum CLK cycle times for the various specified

SYS

frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values

see Section 23, “Clocking.”

7. The setup and hold time is with respect to the rising edge of HRESET.

8. The timing parameter t

is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local

PCRHFV

Bus Specifications.

9. The reset assertion timing requirement for HRESET is 100 μs.

10.Guaranteed by characterization

11.Guaranteed by design

Figure 30 provides the AC test load for PCI.

OV /2

Output

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 36. PCI AC Test Load

Figure 37 shows the PCI input AC timing conditions.

CLK

t

PCIVKH

t

PCIXKH

Input

Figure 37. PCI Input AC Timing Measurement Conditions

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High-Speed Serial Interfaces (HSSI)

Figure 38 shows the PCI output AC timing conditions.

CLK

t

PCKHOV

Output Delay

t

PCKHOZ

High-Impedance

Output

Figure 38. PCI Output AC Timing Measurement Condition

13 High-Speed Serial Interfaces (HSSI)

The MPC8568E features one Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial

interconnect applications. It can be used for PCI Express and/or Serial RapidIO data transfers.

This section describes the common portion of SerDes DC electrical specifications, which is the DC

requirement for SerDes Reference Clocks. The SerDes data lane’s transmitter and receiver reference

circuits are also shown.

13.1 Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms

used in the description and specification of differential signals.

Figure 39 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for

description. The figure shows waveform for either a transmitter output (SD_TX and SD_TX) or a receiver

input (SD_RX and SD_RX). Each signal swings between A Volts and B Volts where A > B.

Using this waveform, the definitions are as follows. To simplify illustration, the following definitions

assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling

environment.

1. Single-Ended Swing

The transmitter output signals and the receiver input signals SD_TX, SD_TX, SD_RX and SD_RX

each have a peak-to-peak swing of A – B Volts. This is also referred as each signal wire’s

Single-Ended Swing.

2. Differential Output Voltage, V (or Differential Output Swing):

OD

The Differential Output Voltage (or Swing) of the transmitter, V , is defined as the difference of

OD

the two complimentary output voltages: V

or negative.

– V

The V value can be either positive

SD_TX

SD_TX. OD

3. Differential Input Voltage, V (or Differential Input Swing):

ID

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High-Speed Serial Interfaces (HSSI)

The Differential Input Voltage (or Swing) of the receiver, V , is defined as the difference of the

ID

two complimentary input voltages: V

negative.

– V

The V value can be either positive or

SD_RX

SD_RX. ID

4. Differential Peak Voltage, V

DIFFp

The peak value of the differential transmitter output signal or the differential receiver input signal

is defined as Differential Peak Voltage, V = |A – B| Volts.

DIFFp

5. Differential Peak-to-Peak, V

DIFFp-p

Since the differential output signal of the transmitter and the differential input signal of the receiver

each range from A – B to –(A – B) Volts, the peak-to-peak value of the differential transmitter

output signal or the differential receiver input signal is defined as Differential Peak-to-Peak

Voltage, V

= 2*V

= 2 * |(A – B)| Volts, which is twice of differential swing in

DIFFp-p

DIFFp

amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage

can also be calculated as V = 2*|V |.

TX-DIFFp-p

OD

6. Common Mode Voltage, V

cm

The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor

of a balanced interchange circuit and ground. In this example, for SerDes output, V = V

cm_out

SD_TX

+ V

= (A + B) / 2, which is the arithmetic mean of the two complimentary output voltages

SD_TX

within a differential pair. In a system, the common mode voltage may often differ from one

component’s output to the other’s input. Sometimes, it may be even different between the receiver

input and driver output circuits within the same component. It is also referred as the DC offset in

some occasion.

SD_TX or

SD_RX

A Volts

V

= (A + B) / 2

cm

SD_TX or

SD_RX

B Volts

Differential Swing, V or V = A – B

ID

OD

Differential Peak Voltage, V

= |A – B|

DIFFp

Differential Peak-Peak Voltage, V

= 2*V

(not shown)

DIFFp

DIFFpp

Figure 39. Differential Voltage Definitions for Transmitter or Receiver

To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD

or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since

the differential signaling environment is fully symmetrical, the transmitter output’s differential swing

(V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges

OD

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between 500 mV and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other

OD

phase. The peak differential voltage (V

is 1000 mV p-p.

) is 500 mV. The peak-to-peak differential voltage (V

)

DIFFp

DIFFp-p

13.2 SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by

the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK and

SD_REF_CLK.

The following sections describe the SerDes reference clock requirements and some application

information.

13.2.1 SerDes Reference Clock Receiver Characteristics

Figure 40 shows a receiver reference diagram of the SerDes reference clocks.

•

The supply voltage requirements for SCOREVDD and XVDD are specified in Table 2 and Table 3.

SerDes Reference Clock Receiver Reference Circuit Structure

— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown

in Figure 40. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-Ω

termination to SCOREGND followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. Refer to the

Differential Mode and Single-ended Mode description below for further detailed requirements.

•

The maximum average current requirement that also determines the common mode voltage range

— When the SerDes reference clock differential inputs are DC coupled externally with the clock

driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the

exact common mode input voltage is not critical as long as it is within the range allowed by the

maximum average current of 8 mA (refer to the following bullet for more detail), since the

input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4V

(0.4V/50 = 8mA) while the minimum common mode input level is 0.1V above SCOREGND.

For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output

driven by its current source from 0mA to 16mA (0-0.8V), such that each phase of the

differential input has a single-ended swing from 0V to 800mV with the common mode voltage

at 400mV.

— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 ohms to

SCOREGND DC, or it exceeds the maximum input current limitations, then it must be

AC-coupled off-chip.

•

The input amplitude requirement

— This requirement is described in detail in the following sections.

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High-Speed Serial Interfaces (HSSI)

50 Ω

SD_REF_CLK

Input

Amp

50 Ω

Figure 40. Receiver of SerDes Reference Clocks

13.2.2 DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC8568E SerDes reference clock inputs is different depending on the

signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described

below.

•

Differential Mode

— The input amplitude of the differential clock must be between 400mV and 1600mV differential

peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire

of the differential pair must have a single-ended swing less than 800mV and greater than

200mV. This requirement is the same for both external DC-coupled or AC-coupled connection.

— For external DC-coupled connection, as described in section 13.2.1, the maximum average

current requirements sets the requirement for average voltage (common mode voltage) to be

between 100 mV and 400 mV. Figure 41 shows the SerDes reference clock input requirement

for DC-coupled connection scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

SCOREGND. Each signal wire of the differential inputs is allowed to swing below and above

the command mode voltage (SCOREGND). Figure 42 shows the SerDes reference clock input

requirement for AC-coupled connection scheme.

•

Single-ended Mode

— The reference clock can also be single-ended. The SD_REF_CLK input amplitude

(single-ended swing) must be between 400mV and 800mV peak-peak (from Vmin to Vmax)

with SD_REF_CLK either left unconnected or tied to ground.

— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 43 shows

the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC or

AC-coupled externally. For the best noise performance, the reference of the clock could be DC

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High-Speed Serial Interfaces (HSSI)

or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as

the clock input (SD_REF_CLK) in use.

200 mV < Input Amplitude or Differential Peak < 800 mV

SD_REF_CLK

Vmax < 800 mV

100 mV < Vcm < 400 mV

Vmin > 0 V

SD_REF_CLK

Figure 41. Differential Reference Clock Input DC Requirements (External DC-Coupled)

200 mV < Input Amplitude or Differential Peak < 800 mV

SD_REF_CLK

Vmax < Vcm + 400 mV

Vcm

Vmin > Vcm − 400 mV

SD_REF_CLK

Figure 42. Differential Reference Clock Input DC Requirements (External AC-Coupled)

400 mV < SD_REF_CLK Input Amplitude < 800 mV

SD_REF_CLK

0 V

SD_REF_CLK

Figure 43. Single-Ended Reference Clock Input DC Requirements

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High-Speed Serial Interfaces (HSSI)

13.2.3 Interfacing With Other Differential Signaling Levels

•

With on-chip termination to SCOREGND, the differential reference clocks inputs are HCSL

(High-Speed Current Steering Logic) compatible DC-coupled.

•

Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling)

can be used but may need to be AC-coupled due to the limited common mode input range allowed

(100 to 400 mV) for DC-coupled connection.

•

LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at

clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in

addition to AC-coupling.

NOTE

Figure 44 to Figure 47 below are for conceptual reference only. Due to the

fact that clock driver chip's internal structure, output impedance and

termination requirements are different between various clock driver chip

manufacturers, it is very possible that the clock circuit reference designs

provided by clock driver chip vendor are different from what is shown

below. They might also vary from one vendor to the other. Therefore,

Freescale Semiconductor can neither provide the optimal clock driver

reference circuits, nor guarantee the correctness of the following clock

driver connection reference circuits. The system designer is recommended

to contact the selected clock driver chip vendor for the optimal reference

circuits with the MPC8568 SerDes reference clock receiver requirement

provided in this document.

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Figure 44 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with MPC8568 SerDes reference clock

input’s DC requirement.

MPC8568E

HCSL CLK Driver Chip

50 Ω

SD_REF_CLK

CLK_Out

33 Ω

SerDes Refer.

CLK Receiver

100 Ω differential PWB trace

Clock Driver

CLK_Out

SD_REF_CLK

50 Ω

Clock driver vendor dependent

source termination resistor

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

Figure 44. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

Figure 45 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common mode voltage is higher than the MPC8568 SerDes reference clock

input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the

LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter

establishes its own common mode level without relying on the receiver or other external component.

MPC8568E

LVDS CLK Driver Chip

50 Ω

SD_REF_CLK

10 nF

CLK_Out

SerDes Refer.

CLK Receiver

100 Ω differential PWB trace

Clock Driver

CLK_Out

SD_REF_CLK

10 nF

50 Ω

Figure 45. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

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High-Speed Serial Interfaces (HSSI)

Figure 46 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

MPC8568 SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 46

assumes that the LVPECL clock driver’s output impedance is 50Ω. R1 is used to DC-bias the LVPECL

outputs prior to AC-coupling. Its value could be ranged from 140Ω to 240Ω depending on clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination

resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8568 SerDes

reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak).

For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock

input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25Ω. Consult

clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular

clock driver chip.

LVPECL CLK

Driver Chip

MPC8568E

50 Ω

SD_REF_CLK

CLK_Out

10 nF

R2

SerDes Refer.

CLK Receiver

R1

100 Ω differential PWB trace

10 nF

Clock Driver

R2

SD_REF_CLK

CLK_Out

50 Ω

Figure 46. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

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High-Speed Serial Interfaces (HSSI)

Figure 47 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with MPC8568E SerDes reference clock

input’s DC requirement.

Single-Ended

CLK Driver Chip

MPC8568E

Total 50 Ω. Assume clock driver’s

output impedance is about 16 Ω.

50 Ω

SD_REF_CLK

33 Ω

Clock Driver

CLK_Out

SerDes Refer.

CLK Receiver

100 Ω differential PWB trace

SD_REF_CLK

50 Ω

Figure 47. Single-Ended Connection (Reference Only)

13.2.4 AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the

transmission line and reduce reflections which are a source of noise to the system.

The detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based

on application usage. Refer to the following sections for detailed information:

•

Section 14.2, “AC Requirements for PCI Express SerDes Clocks”

Section 15.2, “AC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK”

13.2.4.1 Spread Spectrum Clock

SD_REF_CLK/SD_REF_CLK were designed to work with a spread spectrum clock (+0 to –0.5%

spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,

a source without significant unintended modulation should be used.

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13.3 SerDes Transmitter and Receiver Reference Circuits

Figure 48 shows the reference circuits for SerDes data lane’s transmitter and receiver.

SD_RXn

SD_TXn

50 Ω

Receiver

Transmitter

SD_TXn

SD_RXn

Figure 48. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below

(PCI Express, Serial Rapid IO or SGMII) in this document based on the application usage:

•

Section 14, “PCI Express”

Section 15, “Serial RapidIO”

Note that external AC Coupling capacitor is required for the above three serial transmission protocols with

the capacitor value defined in specification of each protocol section.

14 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8568E.

14.1 DC Requirements for PCI Express SD_REF_CLK and

SD_REF_CLK

For more information, see Section 13, “High-Speed Serial Interfaces (HSSI).”

14.2 AC Requirements for PCI Express SerDes Clocks

Table 50 lists AC requirements.

Table 50. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typical

Max

Units

Notes

t

REFCLK cycle time

—

10

—

ns

ps

1

REF

t

REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles

100

—

REFCJ

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Table 50. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typical

Max

Units

Notes

t

Phase jitter. Deviation in edge location with respect to mean

edge location

–50

—

50

ps

—

REFPJ

Notes:

1. Typical based on PCI Express Specification 2.0.

14.3 Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.

14.4 Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the Transport and Data Link layer please use the PCI

EXPRESS Base Specification. REV. 1.0a document.

14.4.1 Differential Transmitter (TX) Output

Table 51 defines the specifications for the differential output at all transmitters (TXs). The parameters are

specified at the component pins.

Table 51. Differential Transmitter (TX) Output Specifications

Symbol

Parameter

Min

Nom

Max Units

Comments

UI

Unit Interval

399.88 400 400.12 ps Each UI is 400 ps 300 ppm. UI does not account for

Spread Spectrum Clock dictated variations. See Note 1.

V

Differential

Peak-to-Peak

Output Voltage

0.8

—

1.2

V

= 2*|V

– V

| See Note 2.

TX-D-

TX-DIFFp-p

TX-D+

De- Emphasized –3.0

Differential

–3.5

–4.0

dB Ratio of the V

of the second and following bits

TX-DIFFp-p

TX-DE-RATIO

after a transition divided by the V

of the first bit

TX-DIFFp-p

Output Voltage

(Ratio)

after a transition. See Note 2.

T

Minimum TX Eye 0.70

Width

—

UI The maximum Transmitter jitter can be derived as

= 1 – T = 0.3 UI.

TX-EYE

T

TX-MAX-JITTER

TX-EYE

See Notes 2 and 3.

Maximum time

between the jitter

median and

—

0.15

UI Jitter is defined as the measurement variation of the

TX-EYE-MEDIAN-to-

crossing points (V = 0 V) in relation to a

MAX-JITTER

TX-DIFFp-p

recovered TX UI. A recovered TX UI is calculated over

3500 consecutive unit intervals of sample data. Jitter is

measured using all edges of the 250 consecutive UI in

the center of the 3500 UI used for calculating the TX UI.

See Notes 2 and 3.

maximum

deviation from

the median.

T

, T

D+/D- TX Output 0.125

Rise/Fall Time

—

UI See Notes 2 and 5

TX-RISE TX-FALL

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Table 51. Differential Transmitter (TX) Output Specifications (continued)

Symbol

Parameter

Min

Nom

Max Units

Comments

V

RMS AC Peak

Common Mode

Output Voltage

—

20

mV

V

= RMS(|V

+ V

|/2 – V

)

TX-CM-DC

TX-CM-ACp

TXD+

TXD-

= DC

of |V

+ V

|/2

TX-D-

TX-CM-DC

(avg)

TX-D+

See Note 2

V

Absolute Delta of

DC Common

Mode Voltage

During L0 and

Electrical Idle

0

—

100

mV |V

V

TX-CM-DC (during L0) – TX-CM-Idle-DC (During Electrical

|<=100 mV

TX-CM-DC-ACTIVE-

IDLE-DELTA

Idle)

V

= DC

of |V

+ V

|/2 [L0]

TX-D-

TX-CM-DC

(avg)

TX-D+

= DC

of |V

+ V

|/2 [Electrical

TX-CM-Idle-DC

(avg)

TX-D+

TX-D-

Idle]

See Note 2.

V

Absolute Delta of

DC Common

Mode between

D+ and D–

25

mV |V

V

| <= 25 mV

TX-CM-DC-LINE-DELTA

TX-CM-DC-D+ – TX-CM-DC-D-

V

= DC

of |V

|

TX-CM-DC-D+

(avg)

TX-D+

= DC

of |V

|

TX-D-

TX-CM-DC-D-

(avg)

See Note 2.

V

Electrical Idle

differential Peak

Output Voltage

0

—

20

mV

V

= |V

-V

| <= 20 mV

TX-IDLE-D-

TX-IDLE-DIFFp

TX-IDLE-D+

See Note 2.

The amount of

voltage change

allowed during

Receiver

—

600

mV The total amount of voltage change that a transmitter

can apply to sense whether a low impedance Receiver

is present. See Note 6.

TX-RCV-DETECT

Detection

V

The TX DC

Common Mode

Voltage

0

—

3.6

V

The allowed DC Common Mode voltage under any

conditions. See Note 6.

TX-DC-CM

I

TX Short Circuit

Current Limit

—

50

—

90

—

mA The total current the Transmitter can provide when

shorted to its ground

TX-SHORT

T

Minimum time

spent in

Electrical Idle

UI Minimum time a Transmitter must be in Electrical Idle

Utilized by the Receiver to start looking for an Electrical

Idle Exit after successfully receiving an Electrical Idle

ordered set

TX-IDLE-MIN

T

Maximum time to

transition to a

valid Electrical

idle after sending

an Electrical Idle

ordered set

—

10

—

20

—

UI After sending an Electrical Idle ordered set, the

Transmitter must meet all Electrical Idle Specifications

within this time. This is considered a debounce time for

the Transmitter to meet Electrical Idle after transitioning

from L0.

TX-IDLE-SET-TO-IDLE

T

Maximum time to

transition to valid

TXspecifications

after leaving an

Electrical idle

condition

UI Maximum time to meet all TX specifications when

transitioning from Electrical Idle to sending differential

data. This is considered a debounce time for the TX to

meet all TX specifications after leaving Electrical Idle

TX-IDLE-TO-DIFF-DATA

RL

Differential

dB Measured over 50 MHz to 1.25 GHz. See Note 4

TX-DIFF

Return Loss

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Table 51. Differential Transmitter (TX) Output Specifications (continued)

Symbol

Parameter

Min

Nom

Max Units

Comments

RL

Common Mode

Return Loss

6

—

120

—

dB Measured over 50 MHz to 1.25 GHz. See Note 4

TX-CM

Z

DC Differential

TX Impedance

80

40

—

75

100

—

Ω

TX DC Differential mode Low Impedance

TX-DIFF-DC

Transmitter DC

Impedance

Required TX D+ as well as D- DC Impedance during all

states

TX-DC

L

Lane-to-Lane

Output Skew

—

500 +

2 UI

ps Static skew between any two Transmitter Lanes within a

single Link

TX-SKEW

C

AC Coupling

Capacitor

—

200

nF All Transmitters shall be AC coupled. The AC coupling is

required either within the media or within the

transmitting component itself. See note 8.

TX

T

Crosslink

Random

Timeout

0

—

1

ms This random timeout helps resolve conflicts in crosslink

configuration by eventually resulting in only one

crosslink

Downstream and one Upstream Port. See Note 7.

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 51 and measured over

any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 49)

3. A T

= 0.70 UI provides for a total sum of deterministic and random jitter budget of T

= 0.30 UI for the

TX-EYE

TX-JITTER-MAX

Transmitter collected over any 250 consecutive TX UIs. The T

median is less than half of the total

TX-EYE-MEDIAN-to-MAX-JITTER

TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.

The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed

to the averaged time value.

4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode

return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement

applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and

D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes—see Figure 51). Note that the series capacitors

C

is optional for the return loss measurement.

TX

5. Measured between 20-80% at transmitter package pins into a test load as shown in Figure 51 for both V

6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a

and V

.

TX-D-

TX-D+

7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a

8. MPC8568E SerDes transmitter does not have C built-in. An external AC Coupling capacitor is required.

TX

14.4.2 Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 49 is specified using the passive compliance/test measurement load (see

Figure 51) in place of any real PCI Express interconnect + RX component.

There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in

time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ

in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level

of the de-emphasized bit will always be relative to the transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

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A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

It is recommended that the recovered TX UI is calculated using all edges in

the 3500 consecutive UI interval with a fit algorithm using a minimization

merit function (that is, least squares and median deviation fits).

Figure 49. Minimum Transmitter Timing and Voltage Output Compliance Specifications

14.4.3 Differential Receiver (RX) Input Specifications

Table 52 defines the specifications for the differential input at all receivers (RXs). The parameters are

specified at the component pins.

Table 52. Differential Receiver (RX) Input Specifications

Symbol

Parameter

Min

Nom

Max

Units

Comments

UI

Unit Interval

399.8

8

400

400.12

ps

Each UI is 400 ps 300 ppm. UI does not

account for Spread Spectrum Clock dictated

variations. See Note 1.

V

Differential

0.175

—

1.200

V

= 2*|V

– V

|

RX-D-

RX-DIFFp-p

RX-D+

Peak-to-Peak

Output Voltage

See Note 2.

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Table 52. Differential Receiver (RX) Input Specifications (continued)

Symbol

Parameter

Minimum

Min

Nom

Max

Units

Comments

T

0.4

—

UI

The maximum interconnect media and

RX-EYE

Receiver Eye

Width

Transmitter jitter that can be tolerated by the

Receiver can be derived as T

=

RX-MAX-JITTER

1 – T

= 0.6 UI.

RX-EYE

See Notes 2 and 3.

Maximum time

between the jitter

median and

maximum

deviation from

the median.

—

0.3

UI

Jitter is defined as the measurement variation

RX-EYE-MEDIAN-to-MAX

of the crossing points (V = 0 V) in

-JITTER

RX-DIFFp-p

relation to a recovered TX UI. A recovered TX

UI is calculated over 3500 consecutive unit

intervals of sample data. Jitter is measured

using all edges of the 250 consecutive UI in

the center of the 3500 UI used for calculating

the TX UI. See Notes 2, 3 and 7.

V

AC Peak

Common Mode

Input Voltage

—

10

—

150

—

mV

dB

V

= |V

+ V

|/2 – V

RXD- RX-CM-DC

RX-CM-ACp

RXD+

= DC

of |V

+ V

|/2

RX-D-

RX-CM-DC

(avg)

RX-D+

See Note 2

RL

Differential

Return Loss

Measured over 50 MHz to 1.25 GHz with the

D+ and D- lines biased at +300 mV and -300

mV, respectively.

RX-DIFF

See Note 4

RL

Z

Common Mode

Return Loss

6

80

—

100

50

—

120

60

dB

Ω

Measured over 50 MHz to 1.25 GHz with the

D+ and D- lines biased at 0 V. See Note 4

RX-CM

DC Differential

Input Impedance

RX DC Differential mode impedance. See

Note 5

RX-DIFF-DC

Z

DC Input

Impedance

40

Ω

Required RX D+ as well as D- DC Impedance

(50 20% tolerance). See Notes 2 and 5.

RX-DC

Powered Down

DC Input

Impedance

200 k

—

Ω

Required RX D+ as well as D- DC Impedance

when the Receiver terminations do not have

power. See Note 6.

RX-HIGH-IMP-DC

V

Electrical Idle

Detect Threshold

65

—

175

10

mV

ms

V

= 2*|V

-V

|

RX-D-

RX-IDLE-DET-DIFFp-p

RX-D+

Measured at the package pins of the Receiver

T

Unexpected

Electrical Idle

Enter Detect

Threshold

An unexpected Electrical Idle (V

V

longer than T

signal an unexpected idle condition.

<

RX-DIFFp-p

RX-IDLE-DET-DIFF-

) must be recognized no

ENTERTIME

RX-IDLE-DET-DIFFp-p

to

RX-IDLE-DET-DIFF-ENTERING

Integration Time

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Table 52. Differential Receiver (RX) Input Specifications (continued)

Symbol

Parameter

Total Skew

Min

Nom

Max

Units

Comments

L

—

20

ns

Skew across all lanes on a Link. This includes

variation in the length of SKP ordered set (for

example, COM and one to five Symbols) at

the RX as well as any delay differences

arising from the interconnect itself.

TX-SKEW

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 51 should be used

as the RX device when taking measurements (also refer to the Receiver compliance eye diagram shown in Figure 50). If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as a reference for the eye diagram.

3. A T

= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and

RX-EYE

interconnect collected any 250 consecutive UIs. The T

specification ensures a jitter distribution in

RX-EYE-MEDIAN-to-MAX-JITTER

which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any

250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point

in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as the reference for the eye diagram.

4. The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to

300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)

over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The

reference impedance for return loss measurements for is 50 ohms to ground for both the D+ and D- line (that is, as measured

by a Vector Network Analyzer with 50 ohm probes—see Figure 51). Note: that the series capacitors CTX is optional for the

return loss measurement.

5. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM)

there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port.

6. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps

ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be

measured at 300 mV above the RX ground.

7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm

using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated

data.

14.5 Receiver Compliance Eye Diagrams

The RX eye diagram in Figure 50 is specified using the passive compliance/test measurement load (see

Figure 51) in place of any real PCI Express RX component.

Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement

load (see Figure 51) will be larger than the minimum Receiver eye diagram measured over a range of

systems at the input Receiver of any real PCI Express component. The degraded eye diagram at the input

Receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the

real PCI Express component to vary in impedance from the compliance/test measurement load. The input

Receiver eye diagram is implementation specific and is not specified. RX component designer should

provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram

(shown in Figure 50) expected at the input Receiver based on some adequate combination of system

simulations and the Return Loss measured looking into the RX package and silicon. The RX eye diagram

must be aligned in time using the jitter median to locate the center of the eye diagram.

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The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

The reference impedance for return loss measurements is 50. to ground for

both the D+ and D- line (that is, as measured by a Vector Network Analyzer

with 50. probes—see Figure 51). Note that the series capacitors, CTX, are

optional for the return loss measurement.

Figure 50. Minimum Receiver Eye Timing and Voltage Compliance Specification

14.5.1 Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2

inches of the package pins, into a test/measurement load shown in Figure 51.

NOTE

The allowance of the measurement point to be within 0.2 inches of the

package pins is meant to acknowledge that package/board routing may

benefit from D+ and D– not being exactly matched in length at the package

pin boundary.

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Figure 51. Compliance Test/Measurement Load

15 Serial RapidIO

This section describes the DC and AC electrical specifications for the RapidIO interface of the

MPC8568E, for the LP-Serial physical layer. The electrical specifications cover both single and

multiple-lane links. Two transmitters (short run and long run) and a single receiver are specified for each

of three baud rates, 1.25, 2.50, and 3.125 GBaud.

Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to

driving two connectors across a backplane. A single receiver specification is given that will accept signals

from both the short run and long run transmitter specifications.

The short run transmitter should be used mainly for chip-to-chip connections on either the same printed

circuit board or across a single connector. This covers the case where connections are made to a mezzanine

(daughter) card. The minimum swings of the short run specification reduce the overall power used by the

transceivers.

The long run transmitter specifications use larger voltage swings that are capable of driving signals across

backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications

allow a distance of at least 50 cm at all baud rates.

All unit intervals are specified with a tolerance of +/– 100 ppm. The worst case frequency difference

between any transmit and receive clock will be 200 ppm.

To ensure interoperability between drivers and receivers of different vendors and technologies, AC

coupling at the receiver input must be used.

15.1 DC Requirements for Serial RapidIO SD_REF_CLK and

SD_REF_CLK

For more information, see Section 13.2, “SerDes Reference Clocks.”

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15.2 AC Requirements for Serial RapidIO SD_REF_CLK and

SD_REF_CLK

Table 50 lists AC requirements.

Table 53. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

REFCLK cycle time

Min Typical Max Units

Comments

t

—

10(8)

—

80

40

ns

ps

8 ns applies only to serial RapidIO

with 125-MHz reference clock

REF

t

REFCLK cycle-to-cycle jitter. Difference in the

period of any two adjacent REFCLK cycles

—

REFCJ

t

Phase jitter. Deviation in edge location with

respect to mean edge location

–40

—

REFPJ

15.3 Signal Definitions

LP-Serial links use differential signaling. This section defines terms used in the description and

specification of differential signals. Figure 52 shows how the signals are defined. The figures show

waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal

swings between A Volts and B Volts where A > B. Using these waveforms, the definitions are as follows:

7. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a

peak-to-peak swing of A – B Volts

8. The differential output signal of the transmitter, V , is defined as V –V

TD

OD

TD

9. The differential input signal of the receiver, V , is defined as V -V

ID

RD RD

10. The differential output signal of the transmitter and the differential input signal of the receiver

each range from A – B to –(A – B) Volts

11. The peak value of the differential transmitter output signal and the differential receiver input

signal is A – B Volts

12. The peak-to-peak value of the differential transmitter output signal and the differential receiver

input signal is 2 * (A – B) Volts

TD or RD

A Volts

TD or RD

B Volts

Differential Peak-Peak = 2 * (A-B)

Figure 52. Differential Peak-Peak Voltage of Transmitter or Receiver

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To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)

transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of the signals TD

and TD is 500 mV p-p. The differential output signal ranges between 500 mV and –500 mV. The peak

differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.

15.4 Equalization

With the use of high speed serial links, the interconnect media will cause degradation of the signal at the

receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss

can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.

To negate a portion of these effects, equalization can be used. The most common equalization techniques

that can be used are:

•

A passive high pass filter network placed at the receiver. This is often referred to as passive

equalization.

•

The use of active circuits in the receiver. This is often referred to as adaptive equalization.

15.5 Explanatory Note on Transmitter and Receiver Specifications

AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at

three baud rates (a total of six cases) are described.

The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified

in Clause 47 of IEEE 802.3ae-2002.

XAUI has similar application goals to serial RapidIO, as described in Section 8.1. The goal of this standard

is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for

applications at the baud intervals and reaches described herein.

15.6 Transmitter Specifications

LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.

The differential return loss, S11, of the transmitter in each case shall be better than

•

–10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and

–10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ Freq(f) ≤ Baud Frequency

The reference impedance for the differential return loss measurements is 100 Ohm resistive. Differential

return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components

related to the driver. The output impedance requirement applies to all valid output levels.

It is recommended that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output,

in each case have a minimum value 60 ps.

It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals

that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB and 15 ps at 3.125 GB.

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Table 54. Short Run Transmitter AC Timing Specifications—1.25 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage,

V

Volts

Voltage relative to COMMON

of either signal comprising a

differential pair

O

Differential Output Voltage

Deterministic Jitter

V

500

1000

0.17

mV p-p

UI p-p

—

DIFFPP

J

—

D

Total Jitter

0.35

UI p-p

ps

—

T

Multiple output skew

S

1000

Skew at the transmitter output

between lanes of a multilane

link

MO

Unit Interval

UI

800

ps

+/– 100 ppm

Table 55. Short Run Transmitter AC Timing Specifications—2.5 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage,

V

Volts

Voltage relative to COMMON

of either signal comprising a

differential pair

O

Differential Output Voltage

Deterministic Jitter

V

500

1000

0.17

mV p-p

UI p-p

—

DIFFPP

J

—

D

Total Jitter

0.35

UI p-p

ps

—

T

Multiple Output skew

S

1000

Skew at the transmitter output

between lanes of a multilane

link

MO

Unit Interval

UI

400

ps

+/– 100 ppm

Table 56. Short Run Transmitter AC Timing Specifications—3.125 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage,

V

Volts

Voltage relative to COMMON

of either signal comprising a

differential pair

O

Differential Output Voltage

Deterministic Jitter

V

500

1000

0.17

mV p-p

UI p-p

—

DIFFPP

J

—

D

Total Jitter

0.35

UI p-p

—

T

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Table 56. Short Run Transmitter AC Timing Specifications—3.125 GBaud (continued)

Range

Characteristic

Symbol

Unit

Notes

Min

Max

1000

Multiple output skew

S

—

ps

Skew at the transmitter output

between lanes of a multilane

link

MO

Unit Interval

UI

320

ps

+/– 100 ppm

Table 57. Long Run Transmitter AC Timing Specifications—1.25 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage,

V

Volts

Voltage relative to COMMON

of either signal comprising a

differential pair

O

Differential Output Voltage

Deterministic Jitter

V

800

1600

0.17

mV p-p

UI p-p

—

DIFFPP

J

—

D

Total Jitter

0.35

UI p-p

ps

—

T

Multiple output skew

S

1000

Skew at the transmitter output

between lanes of a multilane

link

MO

Unit Interval

UI

800

ps

+/–100 ppm

Table 58. Long Run Transmitter AC Timing Specifications—2.5 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage,

V

Volts

Voltage relative to COMMON

of either signal comprising a

differential pair

O

Differential Output Voltage

Deterministic Jitter

V

800

1600

0.17

mV p-p

UI p-p

—

DIFFPP

J

—

D

Total Jitter

0.35

UI p-p

ps

—

T

Multiple output skew

S

1000

Skew at the transmitter output

between lanes of a multilane

link

MO

Unit Interval

UI

400

ps

+/– 100 ppm

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Table 59. Long Run Transmitter AC Timing Specifications—3.125 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

–0.40

Max

2.30

Output Voltage,

V

Volts

Voltage relative to COMMON

of either signal comprising a

differential pair

O

Differential Output Voltage

Deterministic Jitter

V

800

1600

0.17

mV p-p

UI p-p

—

DIFFPP

J

—

D

Total Jitter

0.35

UI p-p

ps

—

T

Multiple output skew

S

1000

Skew at the transmitter output

between lanes of a multilane

link

MO

Unit Interval

UI

320

ps

+/– 100 ppm

For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the

transmitter shall fall entirely within the unshaded portion of the Transmitter Output Compliance Mask

shown in Figure 53 with the parameters specified in Table 60 when measured at the output pins of the

device and the device is driving a 100 Ohm +/–5% differential resistive load. The output eye pattern of an

LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol

interference) need only comply with the Transmitter Output Compliance Mask when pre-emphasis is

disabled or minimized.

V

max

min

DIFF

V

DIFF

0

-VDIFF min

-VDIFF max

0

A

B

1-B

1-A

1

Time in UI

Figure 53. Transmitter Output Compliance Mask

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Table 60. Transmitter Differential Output Eye Diagram Parameters

V

min

(mV)

V

max

DIFF

(mV)

DIFF

Transmitter Type

A (UI)

B (UI)

1.25 GBaud short range

1.25 GBaud long range

2.5 GBaud short range

2.5 GBaud long range

3.125 GBaud short range

3.125 GBaud long range

250

400

250

400

250

400

500

800

500

800

500

800

0.175

0.39

15.7 Receiver Specifications

LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section.

Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode

return loss better than 6 dB from 100 MHz to (0.8)*(Baud Frequency). This includes contributions from

on-chip circuitry, the chip package and any off-chip components related to the receiver. AC coupling

components are included in this requirement. The reference impedance for return loss measurements is

100 Ω resistive for differential return loss and 25 Ω resistive for common mode.

Table 61. Receiver AC Timing Specifications—1.25 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

1600

Differential Input Voltage

V

200

mV p-p

Measured at receiver

IN

Deterministic Jitter Tolerance

J

0.37

0.55

—

UI p-p

Measured at receiver

D

Combined Deterministic and Random

Jitter Tolerance

DR

1

Total Jitter Tolerance

J

0.65

—

UI p-p

ns

Measured at receiver

T

Multiple Input Skew

S

—

24

10

Skew at the receiver input

between lanes of a multilane

link

MI

–12

Bit Error Rate

Unit Interval

Note:

BER

UI

—

ps

—

800

+/– 100 ppm

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 54. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

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Table 62. Receiver AC Timing Specifications—2.5 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

1600

Differential Input Voltage

V

200

mV p-p

Measured at receiver

IN

Deterministic Jitter Tolerance

J

0.37

0.55

—

UI p-p

Measured at receiver

D

Combined Deterministic and Random

Jitter Tolerance

DR

1

Total Jitter Tolerance

J

0.65

—

UI p-p

ns

Measured at receiver

T

Multiple Input Skew

S

—

24

10

Skew at the receiver input

between lanes of a multilane

link

MI

–12

Bit Error Rate

Unit Interval

Note:

BER

UI

—

ps

—

400

+/– 100 ppm

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 54. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

Table 63. Receiver AC Timing Specifications—3.125 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

1600

Differential Input Voltage

V

200

mV p-p

Measured at receiver

IN

Deterministic Jitter Tolerance

J

0.37

0.55

—

UI p-p

Measured at receiver

D

Combined Deterministic and Random

Jitter Tolerance

DR

1

Total Jitter Tolerance

J

0.65

—

UI p-p

ns

Measured at receiver

T

Multiple Input Skew

S

—

22

10

Skew at the receiver input

between lanes of a multilane

link

MI

-12

Bit Error Rate

Unit Interval

Note:

BER

UI

—

ps

—

320

+/- 100 ppm

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 54. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

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8.5 UI p-p

Sinusoidal

Jitter

Amplitude

0.10 UI p-p

22.1 kHz

Frequency

1.875 MHz

20 MHz

Figure 54. Single Frequency Sinusoidal Jitter Limits

15.8 Receiver Eye Diagrams

For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the

corresponding Bit Error Rate specification (Table 61, Table 62, Table 63) when the eye pattern of the

receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver

Input Compliance Mask shown in Figure 55 with the parameters specified in Table . The eye pattern of the

receiver test signal is measured at the input pins of the receiving device with the device replaced with a

100 Ω +/– 5% differential resistive load.

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V

max

min

DIFF

0

-V

min

DIFF

-V

max

DIFF

0

1

A

B

1-B

1-A

Time (UI)

Figure 55. Receiver Input Compliance Mask

Table 64. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter

Receiver Type

1.25 GBaud

V

min (mV)

V

max (mV)

DIFF

A (UI)

B (UI)

DIFF

100

800

0.275

0.400

2.5 GBaud

3.125 GBaud

15.9 Measurement and Test Requirements

Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause

47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided by

Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE 802.3ae-2002 is specified as

the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE 802.3ae-2002 is

recommended as a reference for additional information on jitter test methods.

15.9.1 Eye Template Measurements

For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point

at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the

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87

Serial RapidIO

Continuous Jitter Test Pattern (CJPAT) defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial

link shall be active in both the transmit and receive directions, and opposite ends of the links shall use

asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane

implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The

-12

amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10

The eye pattern shall be measured with AC coupling and the compliance template centered at 0 Volts

.

differential. The left and right edges of the template shall be aligned with the mean zero crossing points of

the measured data eye. The load for this test shall be 100 Ohms resistive +/– 5% differential to 2.5 GHz.

15.9.2 Jitter Test Measurements

For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (Baud

Frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter

Test Pattern (CJPAT) pattern defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial link shall

be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous

clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations

shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured

with AC coupling and at 0 Volts differential. Jitter measurement for the transmitter (or for calibration of a

jitter tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that

described in Annex 48B of IEEE 802.3ae.

15.9.3 Transmit Jitter

Transmit jitter is measured at the driver output when terminated into a load of 100 Ohms resistive +/– 5%

differential to 2.5 GHz.

15.9.4 Jitter Tolerance

Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first

producing the sum of deterministic and random jitter defined in and then adjusting the signal amplitude

until the data eye contacts the 6 points of the minimum eye opening of the receive template shown in and

. Note that for this to occur, the test signal must have vertical waveform symmetry about the average value

and have horizontal symmetry (including jitter) about the mean zero crossing. Eye template measurement

requirements are as defined above. Random jitter is calibrated using a high pass filter with a low frequency

corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter specified in is then

added to the signal and the test load is replaced by the receiver being tested.

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Timers

16 Timers

This section describes the DC and AC electrical specifications for the timers of the MPC8568E.

16.1 Timers DC Electrical Characteristics

Table 65 provides the DC electrical characteristics for the MPC8568E timers pins, including TIN, TOUT,

TGATE and RTC_CLK.

Table 65. Timers DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

= –6.0 mA

OH

Min

Max

Unit

V

I

2.4

—

V

OH

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 6.0 mA

= 3.2 mA

—

0.5

0.4

OL

V

I

—

V

OL

V

2.0

-0.3

—

OV +0.3

V

IH

DD

V

—

0.8

10

V

IL

I

0 V ≤ V ≤ OV

DD

μA

IN

16.2 Timers AC Timing Specifications

Table 66 provides the timers input and output AC timing specifications.

1

Table 66. Timers Input AC Timing Specifications

2

Characteristic Symbol

Typ

Unit

ns

Timers inputs—minimum pulse width

Notes:

t

20

TIWID

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.

Timings are measured at the pin.

2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use

by any external synchronous logic. Timers inputs are required to be valid for at least t

operation

ns to ensure proper

TIWID

Figure 56 provides the AC test load for the timers.

OV /2

Output

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 56. Timers AC Test Load

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89

PIC

17 PIC

This section describes the DC and AC electrical specifications for the external interrupt pins of the

MPC8568E.

17.1 PIC DC Electrical Characteristics

Table 67 provides the DC electrical characteristics for the external interrupt pins of the MPC8568E.

Table 67. PIC DC Electrical Characteristics

Characteristic

Input high voltage

Symbol

Condition

Min

Max

Unit

V

—

2.0

OV +0.3

V

IH

DD

Input low voltage

Input current

V

I

-0.3

0.8

10

IL

μA

V

IN

Output low voltage

Notes:

V

I

= 6.0 mA

= 3.2 mA

OL

—

0.5

0.4

OL

V

I

V

OL

1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT, and CE ports Interrupts.

2. IRQ_OUT and MCP_OUT are open drain pins, thus V is not relevant for those pins.

OH

17.2 PIC AC Timing Specifications

Table 68 provides the PIC input and output AC timing specifications.

1

Table 68. PIC Input AC Timing Specifications

2

Characteristic

Symbol

Min

Unit

ns

IPIC inputs—minimum pulse width

Notes:

t

20

PIWID

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.

Timings are measured at the pin.

2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by

any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation

when working in edge triggered mode.

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SPI

18 SPI

This section describes the DC and AC electrical specifications for the SPI of the MPC8568E.

18.1 SPI DC Electrical Characteristics

Table 69 provides the DC electrical characteristics for the MPC8568E SPI.

Table 69. SPI DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

= –6.0 mA

OH

Min

Max

Unit

V

I

2.4

—

V

OH

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 6.0 mA

= 3.2 mA

—

0.5

0.4

OL

I

—

V

OL

V

2.0

-0.3

—

OV +0.3

V

IH

DD

V

—

0.8

10

V

IL

I

0 V ≤ V ≤ OV

DD

μA

IN

18.2 SPI AC Timing Specifications

Table 70 and provide the SPI input and output AC timing specifications.

1

Table 70. SPI AC Timing Specifications

2

Characteristic

Symbol

Min

Max

Unit

SPI outputs—Master mode (internal clock) delay

SPI outputs—Slave mode (external clock) delay

SPI inputs—Master mode (internal clock) input setup time

SPI inputs—Master mode (internal clock) input hold time

SPI inputs—Slave mode (external clock) input setup time

SPI inputs—Slave mode (external clock) input hold time

Notes:

t

0

2

4

0

4

2

6

ns

NIKHOV

t

8

NEKHOV

t

—

NIIVKH

t

NIIXKH

t

NEIVKH

NEIXKH

t

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)

for inputs and t

for outputs. For example,

(reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

t

symbolizes the NMSI outputs internal timing (NI) for the time t

memory clock reference (K) goes from

NIKHOV

SPI

the high state (H) until outputs (O) are valid (V).

Figure 57 provides the AC test load for the SPI.

Output

OV /2

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 57. SPI AC Test Load

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91

TDM/SI

Figure 58 through Figure 59 represent the AC timing from Table 72. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 58 shows the SPI timing in Slave mode (external clock).

SPICLK (input)

t

NEIXKH

t

NEIVKH

Input Signals:

SPIMOSI

(See Note)

t

NEKHOV

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

Figure 58. SPI AC Timing in Slave mode (External Clock) Diagram

Figure 59 shows the SPI timing in Master mode (internal clock).

SPICLK (output)

t

NIIXKH

t

NIIVKH

Input Signals:

SPIMISO

(See Note)

t

NIKHOV

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

Figure 59. SPI AC Timing in Master mode (Internal Clock) Diagram

19 TDM/SI

This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial

interface of the MPC8568E.

19.1 TDM/SI DC Electrical Characteristics

Table 71 provides the DC electrical characteristics for the MPC8568E TDM/SI.

Table 71. TDM/SI DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

= –2.0 mA

OH

Min

Max

Unit

V

I

2.4

—

V

OH

Output low voltage

Input high voltage

V

I

= 3.2 mA

—

0.5

OL

V

2.0

OV +0.3

DD

IH

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TDM/SI

Table 71. TDM/SI DC Electrical Characteristics (continued)

Characteristic

Symbol

Condition

Min

Max

Unit

Input low voltage

Input current

V

I

—

-0.3

—

0.8

10

V

IL

0 V ≤ V ≤ OV

μA

IN

DD

19.2 TDM/SI AC Timing Specifications

Table 72 provides the TDM/SI input and output AC timing specifications.

1

Table 72. TDM/SI AC Timing Specifications

2

Characteristic

Symbol

Min

Max

Unit

TDM/SI outputs—External clock delay

TDM/SI outputs—External clock High Impedance

TDM/SI inputs—External clock input setup time

TDM/SI inputs—External clock input hold time

Notes:

t

2

5

2

11

10

—

ns

SEKHOV

SEKHOX

t

SEIVKH

SEIXKH

t

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)

for inputs and t

for outputs. For example,

(reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

t

symbolizes the TDM/SI outputs external timing (SE) for the time t

memory clock reference (K) goes

SEKHOX

TDM/SI

from the high state (H) until outputs (O) are invalid (X).

Figure 60 provides the AC test load for the TDM/SI.

OV /2

Output

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 60. TDM/SI AC Test Load

Figure 61 represents the AC timing from Table 72. Note that although the specifications generally

reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the

active edge.

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93

UTOPIA/POS

Figure 61 shows the TDM/SI timing with external clock.

TDM/SICLK (input)

t

SEIXKH

t

SEIVKH

Input Signals:

TDM/SI

(See Note)

t

SEKHOV

Output Signals:

TDM/SI

(See Note)

t_SEKHOX

Note: The clock edge is selectable on TDM/SI

Figure 61. TDM/SI AC Timing (External Clock) Diagram

20 UTOPIA/POS

This section describes the DC and AC electrical specifications for the UTOPIA-packet over sonnet of the

MPC8568E.

20.1 UTOPIA/POS DC Electrical Characteristics

Table 73 provides the DC electrical characteristics for the MPC8568E UTOPIA.

Table 73. Utopia DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

= –8.0 mA

OH

Min

Max

Unit

V

I

2.4

—

V

OH

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 8.0 mA

OL

0.5

OL

V

—

2.0

-0.3

—

OV +0.3

V

IH

DD

V

I

0.8

10

V

IL

0 V ≤ V ≤ OV

DD

μA

IN

20.2 Utopia/POS AC Timing Specifications

Table 74 provides the UTOPIA input and output AC timing specifications.

1

Table 74. Utopia AC Timing Specifications

2

Characteristic

Symbol

Min

Max

Unit

Utopia outputs—Internal clock delay

t

0

1

0

1

8.0

10.0

8.0

ns

UIKHOV

Utopia outputs—External clock delay

t

UEKHOV

Utopia outputs—Internal clock High Impedance

Utopia outputs—External clock High Impedance

t

UIKHOX

UEKHOX

t

10.0

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94

UTOPIA/POS

Unit

1

Table 74. Utopia AC Timing Specifications (continued)

2

Characteristic

Symbol

Min

Max

Utopia inputs—Internal clock input setup time

Utopia inputs—External clock input setup time

Utopia inputs—Internal clock input Hold time

Utopia inputs—External clock input hold time

Notes:

t

6

4

0

1

—

ns

UIIVKH

t

UEIVKH

t

UIIXKH

t

UEIXKH

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)

for inputs and t

for outputs. For example,

(reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

t

symbolizes the Utopia outputs internal timing (UI) for the time t

memory clock reference (K) goes

Utopia

UIKHOX

from the high state (H) until outputs (O) are invalid (X).

Figure 62 provides the AC test load for the Utopia.

OV /2

Output

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 62. Utopia AC Test Load

Figure 63 through Figure 64 represent the AC timing from Table 74. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 63 shows the Utopia timing with external clock.

UtopiaCLK (input)

t

UEIXKH

t

UEIVKH

Input Signals:

Utopia

t

UEKHOV

Output Signals:

Utopia

t_UEKHOX

Figure 63. Utopia AC Timing (External Clock) Diagram

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95

HDLC, BISYNC, Transparent and Synchronous UART

Figure 64 shows the Utopia timing with internal clock.

UtopiaCLK (output)

t

UIIXKH

t

UIIVKH

Input Signals:

Utopia

t

UIKHOV

Output Signals:

Utopia

t

UIKHOX

Figure 64. Utopia AC Timing (Internal Clock) Diagram

21 HDLC, BISYNC, Transparent and Synchronous UART

This section describes the DC and AC electrical specifications for the high level data link control (HDLC),

BISYNC, transparent and synchronous UART of the MPC8568E.

21.1 HDLC, BISYNC, Transparent and Synchronous UART DC Electrical

Characteristics

Table 75 provides the DC electrical characteristics for the MPC8568E HDLC, BISYNC, Transparent and

Synchronous UART protocols.

Table 75. HDLC, BiSync, Transparent and Synchronous UART DC Electrical Characteristics

Characteristic

Output high voltage

Symbol

Condition

= –2.0 mA

OH

Min

Max

Unit

V

I

2.4

—

V

OH

Output low voltage

Input high voltage

Input low voltage

Input current

V

I

= 3.2 mA

OL

0.5

OL

V

—

2.0

-0.3

—

OV +0.3

V

IH

DD

V

I

0.8

10

V

IL

0 V ≤ V ≤ OV

DD

μA

IN

21.2 HDLC, BISYNC, Transparent and Synchronous UART AC Timing

Specifications

Table 76 provides the input and output AC timing specifications for HDLC, BiSync, Transparent and

Synchronous UART protocols.

1

Table 76. HDLC, BiSync, Transparent AC Timing Specifications

2

Characteristic

Symbol

Min

Max

Unit

Outputs—Internal clock delay

Outputs—External clock delay

t

0

1

6.5

8

ns

HIKHOV

t

HEKHOV

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HDLC, BISYNC, Transparent and Synchronous UART

1

Table 76. HDLC, BiSync, Transparent AC Timing Specifications (continued)

2

Characteristic

Symbol

Min

Max

Unit

Outputs—Internal clock High Impedance

Outputs—External clock High Impedance

Inputs—Internal clock input setup time

Inputs—External clock input setup time

Inputs—Internal clock input Hold time

Inputs—External clock input hold time

Notes:

t

0

1

6

4

0

1

5.5

8

ns

HIKHOX

t

HEKHOX

t

—

HIIVKH

t

HEIVKH

t

HIIXKH

t

HEIXKH

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)

for inputs and t

for outputs. For example,

(reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

t

symbolizes the outputs internal timing (HI) for the time t

memory clock reference (K) goes from the

HIKHOX

serial

high state (H) until outputs (O) are invalid (X).

Table 77. Synchronous UART AC Timing Specifications

2

Characteristic

Outputs—Internal clock delay

Symbol

Min

Max

Unit

t

0

1

0

1

6

8

0

1

11

14

11

14

—

ns

HIKHOV

Outputs—External clock delay

t

HEKHOV

Outputs—Internal clock High Impedance

Outputs—External clock High Impedance

Inputs—Internal clock input setup time

Inputs—External clock input setup time

Inputs—Internal clock input Hold time

Inputs—External clock input hold time

Notes:

t

HIKHOX

t

HEKHOX

t

HIIVKH

t

HEIVKH

t

HIIXKH

t

HEIXKH

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)

for inputs and t

for outputs. For example,

(reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

t

symbolizes the outputs internal timing (HI) for the time t

memory clock reference (K) goes from the

HIKHOX

serial

high state (H) until outputs (O) are invalid (X).

Figure 65 provides the AC test load.

OV /2

Output

Z = 50 Ω

DD

0

R = 50 Ω

L

Figure 65. AC Test Load

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HDLC, BISYNC, Transparent and Synchronous UART

Figure 66 through Figure 67 represent the AC timing from Table 76. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 66 shows the timing with external clock.

Serial CLK (input)

t

HEIXKH

t

HEIVKH

Input Signals:

(See Note)

t

HEKHOV

Output Signals:

(See Note)

t_HEKHOX

Note: The clock edge is selectable

Figure 66. AC Timing (External Clock) Diagram

Figure 67 shows the timing with internal clock.

Serial CLK (output)

t

HIIXKH

t

HIIVKH

Input Signals:

(See Note)

t

HIKHOV

Output Signals:

(See Note)

t

HIKHOX

Note: The clock edge is selectable

Figure 67. AC Timing (Internal Clock) Diagram

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Freescale Semiconductor

Package and Pinout

22 Package and Pinout

This section details package parameters, pin assignments, and dimensions.

22.1 Package Parameters for the MPC8568E FC-PBGA

The package parameters are as provided in the following list. The package type is 33mm × 33mm, 1023

flip chip plastic ball grid array (FC-PBGA).

Package outline

Interconnects

Pitch

33 mm × 33 mm

1023

1 mm

Module height

Solder Balls

2.23 – 2.75 mm

96.5% Sn 3.5% Ag

0.6 mm

Ball diameter (typical)

22.2 Mechanical Dimensions of the MPC8568E FC-PBGA

Figure 68 shows the top view, bottom and side view of the MPC8568E 1023 FC-PBGA package.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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99

Package and Pinout

Figure 68. Top, Bottom, Side Views

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. All dimensions are symmetric across the package center lines, unless dimensioned otherwise.

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Package and Pinout

4. Maximum solder ball diameter measured parallel to datum A.

5. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.

6. ParalleUsm measurement shall exclude any effect of mark on top surface of package

7. Capacitors may not be present on all devices.

8. Caution must be taken not to short capacitors or exposed metal capacitor pads on top of package.

22.3 Pinout Listings

Some of the non-QE signals are multiplexed with QE port pins, as follows:

PC[0]

PC[1]

PC[2]

PC[3]

UART_SOUT[1]

UART_RTS[1]

UART_CTS[1]

UART_SIN[1]

PC[11]

IRQ[8]

PC[12] IRQ[9]/DMA_DREQ[3]

PC[13] IRQ[10]/DMA_DACK[3]

PC[14] IRQ[11]/DMA_DDONE[3]

PC[15] DMA_DREQ[1]

PC[16] DMA_DACK[1]

PC[17] DMA_DDONE[1]

PC[18] IIC2_SCL

PC[19] IIC2_SDA

PD[28]

PD[29]

PD[30]

PD[31]

UART_SOUT[1]

UART_RTS[1]

UART_CTS[1]

UART_SIN[1]

This applies to both MPC8568E and MPC8568E. Note that for DUART1, there are two options. DUART0

is multiplexed with PCI Req/Grant pins.

PCI_REQ[3]

PCI_REQ[4]

PCI_GNT[3]

PCI_GNT[4]

UART_CTS[0]

UART_SIN[0]

UART_RTS[0]

UART_SOUT[0]

For MPC8568E, GPIO is multiplexed with the TSEC2 interface:

TSEC2_TXD[7:0] GPOUT[0:7]

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Package and Pinout

TSEC2_RXD[7:0]

Other muxing includes:

GPIN[0:7]

LCS[5]

LCS[6]

LCS[7]

DMA_DREQ[2]

DMA_DACK[2]

DMA_DDONE[2]

Table 79 provides the pin-out listing for the MPC8568E 1023 FC-PBGA package.

Table 78. MPC8568E Pinout Listing

Power

Supply

Signal

Package Pin Number

PCI

Pin Type

Notes

PCI_AD[31:0]

AE19, AG20, AF19, AB20, AC20, AG21, AG22,

AB21, AF22, AH22, AE22, AF20, AB22, AE20,

AE23, AJ23, AJ24, AF27, AJ26, AE29, AH24,

AD24, AE25, AE26, AH27, AG27, AJ25, AE30,

AF26, AG26, AF28, AH26

I/O

OV

—

DD

PCI_C_BE[3:0]

PCI_GNT[4:1]

PCI_GNT0

PCI_IRDY

AC22, AD20, AE28, AH25

I/O

O

OV

—

5,9,35

—

DD

AF29, AB18, AC18, AD18

AE18

I/O

I

AF23

2

PCI_PAR

AJ22

PCI_PERR

PCI_SERR

PCI_STOP

PCI_TRDY

PCI_REQ[4:1]

PCI_REQ[0]

PCI_CLK

AF24

2

2,4

2

AD22

AE24

AK24

2

AG29, AJ27, AH29, AB17

—

39

2

AC17

AM26

AK23

AE21

AB19

I/O

I

PCI_DEVSEL

PCI_FRAME

PCI_IDSEL

I/O

I

2

—

DDR SDRAM Memory Interface

MDQ[0:63]

B22, C22, E20, A19, C23, A22, A20, C20, G22, E22,

E16, F16, E23, F23, F17, H17, A18, A17, B16, C16,

B19, C19, E17, A16, A13, A14, A12, C12, A15, B15,

B13, C13, G12, G11, H8, F8, D13, F12, E9, F9, A7,

B7, C5, E5, C8, E8, D6, A5, E6, G6, E1, F1, G7, E7,

E2, D1, C4, A3, B1, C1, A4, B4, C2, D2

I/O

GV

—

DD

MECC[0:7]

MDM[0:8]

C11, E11, D9, A8, D12, A11, A9, C9

I/O

O

GV

—

DD

A21, E21, D18, B14, F11, A6, G5, A2, A10

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

102

Package and Pinout

Table 78. MPC8568E Pinout Listing (continued)

Package Pin Number

Power

Notes

Signal

Pin Type

Supply

MDQS[0:8]

MA[0:15]

D21, G20, C17, D14, E10, C6, F4, C3, C10

C21, G21, C18, D15, F10, C7, F5, D3, B10

I/O

O

GV

—

DD

K7, H7, L7, J8, K8, L10, H9, K9, H10, G10, L6, K10,

K11, H3, J11, J12

MBA[0:2]

MWE

K4, H6, L13

O

GV

—

11

—

36

DD

K3

MCAS

L3

O

MRAS

K6

O

MCKE[0:3]

MCS[0:3]

MCK[0:5]

MODT[0:3]

MDIC[0:1]

L14, G13, K12, J13

J5, H2, K5, K2,

G15, F20, E4, F14, E19, G3

G14, F19, E3, F13, E18, G2

G4, J1, J4, K1

O

G1, H1

I/O

Local Bus Controller Interface

LAD[0:31]

M26, C30, F31, L24, G26, D30, M25, L26, D29,

G32, G28, K26, B32, M24, G29, L25, E29, J23, B30,

A31, J24, K23, H25, H23, F26, C28, B29, E25, D26,

G24, A29, E27,

I/O

BV

—

DD

LDP[0:3]

LA[27]

LA[28:31]

LALE

G30, J26, H28, E26

I/O

O

I/O

O

BV

—

5,9

5,7,9

8

DD

F29

H24, C32, F30, H26

G31

BVdd

LBCTL

LCS[0:4]

LCS5

L27

8

M27, H32, J28, J30, B31

BV

—

DD

G25

C29

A30

H30

E28

E32

G27

E30

J27

1

LCS6

1

LCS7

1

LWE[0]

LWE[1]

LWE[2]

LWE[3]

LGPL0

LGPL1

LGPL2

5,9

5,9,46

5,8,9

D32

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

103

Package and Pinout

Table 78. MPC8568E Pinout Listing (continued)

Package Pin Number

Power

Supply

Signal

Pin Type

Notes

LGPL3

J25

O

I/O

O

I

BV

5,9

49

5,9

—

DD

LGPL4

C25

LGPL5

F32

LCKE

C31

LCLK[0:2]

LSYNC_IN

LSYNC_OUT

C27, C26, D25

—

A28

A27

—

O

—

DMA

DMA_DACK[0]

DMA_DREQ[0]

DMA_DDONE[0]

AM27

AK28

AK26

O

I

OV

5,9,46

—

DD

O

—

Programmable Interrupt Controller

UDE

AG32

AF32

I

OV

—

DD

MCP

IRQ[0:7]

AD30, AG31, AL30, AF31, AD29, AK30, AG30,

AF30

IRQ_OUT

AD28

O

OV

2,4

DD

Interface

EC_MDC

EC_MDIO

AE17

AF17

O

OV

5,9

—

DD

I/O

DD

Gigabit Reference Clock

AM14

EC_GTX_CLK125

TSEC1_RXD[7:0]

I

LV

—

DD

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

AE14, AM11, AK11, AF11, AJ14, AJ13, AD12,

AE13

TSEC1_TXD[7]

TSEC1_TXD[6:1]

TSEC1_TXD[0]

TSEC1_COL

AH12

O

I

LV

5, 9

—

DD

AL13, AL11, AK13, AH13, AG11, AD13

AM13

AG13

AB13

AG12

AE11

AH11

AM12

5, 9

—

TSEC1_CRS

I/O

O

I

20

—

TSEC1_GTX_CLK

TSEC1_RX_CLK

TSEC1_RX_DV

TSEC1_RX_ER

—

I

—

I

—

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

104

Package and Pinout

Table 78. MPC8568E Pinout Listing (continued)

Package Pin Number

Power

Notes

Signal

TSEC1_TX_CLK

Pin Type

Supply

AJ11

AC13

AL12

I

LV

—

30

5,9

DD

TSEC1_TX_EN

TSEC1_TX_ER

O

Three-Speed Ethernet Controller (Gigabit Ethernet 2)

TSEC2_RXD[7:0]

AC14, AD15, AB14, AH15, AD14, AH17, AE15,

AC15

I

LV

—

DD

TSEC2_TXD[7]

TSEC2_TXD[6:1]

TSEC2_TXD[0]

TSEC2_COL

AM16

O

I

LV

5, 9

—

DD

AJ15, AJ17, AF13, AK17, AH16, AG17

AL15

AB15

AB16

AJ16

AE16

AG15

AF15

AH14

AM15

AK15

5, 9

—

TSEC2_CRS

I/O

O

I

20

—

TSEC2_GTX_CLK

TSEC2_RX_CLK

TSEC2_RX_DV

TSEC2_RX_ER

TSEC2_TX_CLK

TSEC2_TX_EN

TSEC2_TX_ER

—

I

—

I

—

I

—

O

30

—

2

I C interface

IIC1_SCL

IIC1_SDA

AE32

AD32

I/O

OV

4,27

DD

SerDes

SD_RX[0:7]

SD_TX[0:7]

L30, M32, N30, P32, U30, V32, W30, Y32

I

SCOREVDD 43,44

L29, M31, N29, P31, U29, V31, W29, Y31

P26, R24, T26, U24, W24, Y26, AA24, AB26

O

I

XV

44

DD

SD_TX[0:7]

P27, R25, T27, U25, W25, Y27, AA25, AB27

SD_PLL_TPD

SD_RX_CLK

SD_RX_FRM_CTL

Reserved

R32

U28

V28

V26

V27

T32

T31

SCOREVDD

24

XV

41,44

48

DD

I

—

I

—

Reserved

—

48

SD_REF_CLK

SCOREVDD

44

I

44

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

105

Package and Pinout

Table 78. MPC8568E Pinout Listing (continued)

Package Pin Number

Power

Supply

Signal

Pin Type

Notes

QUICC Engine

PA[0:4]

PA[5]

M1, M2, M5, M4, M3

N3

I/O

OV

5,17

29

DD

PA[6:31]

M6, M7, M8, N5, M10, N1, M11, M9, P1, N9, N7, R6,

R2, P7, P5, R4, P3, P11, P10, P9, R8, R7, R5, R3,

R1, T2

—

PB[4:31]

PC[0:31]

T1, R11, R9, T6, T5, T4, T3, U10, T9, T8, T7, U5,

U3, U1, T11, V1, U11, U9, U7, V5, W4, V3, W2, V9,

W8, V7, W6, W3

I/O

OV

—

DD

W1, V11, V10, W11, W9, W7, W5, Y4, Y3, Y2, Y1,

Y8, Y7, Y6, Y5, AA1, Y11, AA10, Y9, AA9, AA7,

AA5, AA3, AB3, AC2, AB1, AA11, AB7, AC6, AB5,

AC4, AB9

PD[4:31]

AC8, AD1, AC1, AC7, AB10, AC5, AD3, AD2, AC3,

AE4, AF1, AE3, AE1, AD6, AG2, AG1, AD5, AD7,

AD4, AH1, AK3, AD8, AF5, AM4, AC9, AL2, AE5,

AF3

I/O

OV

—

DD

PE[5:7]

AM6, AL5, AL9

I/O

TV

—

5

DD

PE[8:10]

PE[11:19]

PE[20]

AM9, AM10, AL10

AJ9, AH10, AM8, AK9, AL7, AL8, AH9, AM7, AH8

—

5

AH6

OV

DD

PE[21:23]

PE[24]

AM1, AE10, AG5

AJ1

5

PE[25:31]

PF[7]

AH2, AM2, AE9, AH5, AL1, AD9, AL4

—

5

AG9

TV

PF[8:10]

PF[11:19]

PF[20]

AF10, AK7, AJ6

AH7, AF9, AJ7, AJ5, AF7, AG8, AG7, AM5, AK5

—

5,33

—

AK1

OV

DD

PF[21:22]

PF[23:31]

AH3, AL3

AB11, AE7, AJ3, AC11, AG6, AG3, AH4, AM3,

AD11

System Control

HRESET

AL21

AL23

AK18

AL17

AM17

I

O

I

OV

—

29

—

DD

HRESET_REQ

SRESET

CKSTP_IN

CKSTP_OUT

I

—

O

2,4

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

106

Package and Pinout

Table 78. MPC8568E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Debug

Pin Type

Supply

TRIG_IN

AL29

I

OV

—

DD

TRIG_OUT

AM29

O

6,9,19

,29

DD

MSRCID[0:1]

MSRCID[2:4]

AK29, AJ29

O

OV

5,6,9

DD

AM28, AL28, AK27

6,19,2

9

DD

MDVAL

AJ28

AF18

O

OV

6

DD

CLK_OUT

11

DD

Clock

RTC

AH20

AK22

I

OV

—

DD

SYSCLK

DD

JTAG

TCK

TDI

AH18

AH19

AJ18

AK19

AK20

I

OV

—

12

11

12

DD

TDO

TMS

TRST

O

I

DFT

L1_TSTCLK

L2_TSTCLK

LSSD_MODE

TEST_SEL

AJ20

AJ19

AH31

AJ31

I

OV

25

DD

Thermal Management

THERM0

THERM1

AB30

AB31

—

14

—

Power Management

ASLEEP

AK21

O

OV

9,19,2

9

DD

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

107

Package and Pinout

Table 78. MPC8568E Pinout Listing (continued)

Package Pin Number

Power

Supply

Signal

Pin Type

Notes

Power and Ground Signals

GND

A23, A26, A32, B3, B6, B9, B12, B18, B21, B23,

B24, B25, B26, B27, C15, C24, D5, D8, D11, D17,

D20, D23, D24, D28, E13, E14, E24, E31, F3, F7,

F15, F18, F22, F24, F27, G8, G16, G19, G23, H5,

H12, H13, H15, H16, H18, H19, H21, H22, J2, J7,

J10, J14, J15, J16, J17, J18, J19, J20, J21, J22,

J29, J31, J32, K14, K15, K16, K17, K18, K19, K20,

K21, K22, K24, L1, L4, L9, L12, L15, L16, L17, L18,

L19, L20, L21, L22, L23, M12, M13, M18, M20, M21,

M23, N4, N8, N11, N13, N15, N17, N19, N21, N23,

P2, P6, P12, P14, P16, P18, P20, P22, P23, R10,

R13, R15, R17, R19, R21, R23, T12, T14, T16, T18,

T20, T22, T23, U4, U8, U13, U15, U17, U19, U21,

U23, V2, V6, V12, V14, V16, V18, V20, V22, V23,

W10, W13, W15, W17, W19, W21, W23, Y12, Y14,

Y16, Y18, Y20, Y22, Y23, AA4, AA8, AA12, AA13,

AA15, AA17, AA19, AA21, AA22, AA23, AB2, AB6,

AB12, AB23, AB29, AB32, AC10, AC23, AC24,

AC25, AC28, AC29, AC30, AC31, AC32, AD16,

AD17, AD19, AD21, AD25, AD26, AD27, AD31,

AE8, AE12, AF2, AF4, AF6, AF16, AF21, AF25,

AG10, AG14, AG18, AG24, AG28, AH23, AJ4, AJ8,

AJ12, AJ21, AJ30, AJ32, AK2, AK10, AK16, AK32,

AL6, AL14, AL18, AL19, AL20, AL22, AL24, AL25,

AL26, AL31, AL32, AM19, AM21, AM23, AM25,

AM30, AM31, AM32

—

SCOREGND

XGND

K28, K29, K30, L28, L31, M28, M30, N32, P28, P30, Ground for

—

R28, T29, U32, V30, W28, W31, Y28, Y29, AA29,

AA30, AA32, AB28

SerDes

receiver

N24, N26, P25, R27, T24, U26, V25, W27, Y24,

AA26, AB25, AC27

Ground for

SerDes

transmitter

OVDD

N2, N6, N10, P4, P8, T10, U2, U6, V4, V8, Y10,

AA2, AA6, AB4, AB8, AC19, AC21, AD10, AD23,

AE2, AE6, AE27, AE31, AG4, AG19, AG23, AG25,

AH21, AH28, AH30, AH32, AJ2, AK4, AK25, AK31,

AL27

Power for

PCI and

other

standards

(3.3V)

OVDD

LVDD

TVDD

AC12, AC16, AF12, AF14, AG16, AK12, AK14,

AL16

Power for

eTSEC1 and

eTSEC2

LVDD

TVDD

—

(2.5V,3.3V)

AF8, AJ10, AK6, AK8

Power for QE

UCC1 and

UCC2

Ethernet

Interface

(2,5V,3.3V)

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

108

Package and Pinout

Table 78. MPC8568E Pinout Listing (continued)

Package Pin Number

Power

Notes

Signal

Pin Type

Supply

GVDD

B2, B5, B8, B11, B17, B20, C14, D4, D7, D10, D16,

D19, D22, E12, E15, F2, F6, F21, G9, G17, G18,

H4, H11, H14, H20, J3, J6, J9, K13, L2, L5, L8, L11

Power for

DDR1 and

DDR2

GVDD

—

DRAM I/O

voltage

(1.8V,2.5V)

BVDD

VDD

B28, D27, D31, F25, F28, H27, H29, H31, K25, K27

Power for

Local Bus

(1.8V, 2.5V,

3.3V)

BVDD

VDD

—

M14, M15, M19, M22, N12, N14, N16, N18, N20,

N22, P13, P15, P17, P19, P21, R12, R14, R16, R18,

R20, R22, T13, T15, T17, T19, T21, U12, U14, U16,

U18, U20, U22, V13, V15, V17, V19, V21, W12,

W14, W16, W18, W20, W22, Y13, Y15, Y17, Y19,

Y21, AA14, AA16, AA18, AA20

Power for

Core (1.1)

SCOREVDD

XVDD

K31, L32, M29, N28, N31, P29, T28, T30, U31, V29, Core Power SCOREVDD

—

W32, Y30, AA31

for SerDes

transceivers

(1.1V)

N25, N27, P24, R26, T25, U27, V24, W26, Y25,

AA27, AB24, AC26

Pad Power

for SerDes

transceivers

(1.1V)

XVDD

AV

A25

Power for

local bus PLL

(1.1V)

—

26

DD_LBIU

DD_PCI

AM22

AM18

AM24

AM20

R29

Power for

PCI PLL

(1.1V)

Power for QE

PLL

DD_CE

(1.1V)

Power for

e500 PLL

(1.1V)

DD_CORE

DD_PLAT

DD_SRDS

Power for

CCB PLL

(1.1V)

Power for

SRDSPLL

(1.1V)

AGND_SRDS

SENSEVDD

R31

M17

Ground for

SRDSPLL

—

O

V

13

DD

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

109

Package and Pinout

Table 78. MPC8568E Pinout Listing (continued)

Package Pin Number

Power

Supply

Signal

Pin Type

Notes

SENSEVSS

MVREF

M16

—

13

Analog Signals

A24

I

MVREF

—

Reference

voltage

signal for

DDR

SD_IMP_CAL_RX

SD_IMP_CAL_TX

SD_PLL_TPA

K32

I

200Ω to GND

100Ω to GND

—

24

AA28

R30

O

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

110

Package and Pinout

Table 78. MPC8568E Pinout Listing (continued)

Package Pin Number

Power

Notes

Signal

Pin Type

Supply

Notes:

1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the local

bus controller section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2.

2. Recommend a weak pull-up resistor (2–10 KΩ) be placed on this pin to OV

.

DD

4. This pin is an open drain signal.

5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the

reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if the

signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset,

then a pullup or active driver is needed.

6. Treat these pins as no connects (NC) unless using debug address functionality.

7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down

resistors. See Section 23.2, “CCB/SYSCLK PLL Ratio.”

8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ

pull-up or pull-down resistors. See the Section 23.3, “e500 Core PLL Ratio.”

9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or

because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.

11.This output is actively driven during reset rather than being three-stated during reset.

12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.

13.These pins are connected to the V /GND planes internally and may be used by the core power supply to improve tracking

DD

and regulation.

14.Internal thermally sensitive resistor. These two pins are not ESD protected.

17.. The value of PA[0:4] during reset set the QE clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down

resistors. See Section 23.4, “QE/SYSCLK PLL Ratio.”

19. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state

during reset.

20. This pin is only an output in FIFO mode when used as Rx Flow Control.

24. Do not connect.

25.These are test signals for factory use only and must be pulled up (100 - 1 K) to OVDD for normal machine operation.

26. Independent supplies derived from board VDD.

27. Recommend a pull-up resistor (~1 K.) be placed on this pin to OV

.

DD

29. The following pins must NOT be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE,

MSRCID[2:4], ASLEEP, PA[5]

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

111

Package and Pinout

Table 78. MPC8568E Pinout Listing (continued)

Package Pin Number

Power

Supply

Signal

Pin Type

Notes

30. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively

driven.

33. PF[21:22] are multiplexed as cfg_dram_type[0:1]. THEY MUST BE VALID AT POWER-UP, EVEN BEFORE HRESET

ASSERTION.

35. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled

down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCIn_AD pins as "No

Connect" or terminated through 2–10 KΩ pull-up resistors with the default of internal arbiter if the PCIn_AD pins are not

connected to any other PCI device. The PCI block will drive the PCIn_AD pins if it is configured to be the PCI arbiter—through

POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any

other PCI device connected on the bus.

36.MDIC[0] is grounded through an 18.2-Ω precision 1% resistor and MDIC[1] is connected to GV through an 18.2-Ω precision

DD

1% resistor. These pins are used for automatic calibration of the DDR IOs.

39. If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCI_CLK . Otherwise the processor

will not boot up.

41.These pins should be tied to SCOREGND through a 300 ohm resistor if the high speed interface is used.

43. It is highly recommended that unused SD_RX/SD_RX lanes should be powered down with lane_x_pd. Otherwise the

receivers will burn extra power and the internal circuitry may develop long term reliability problems.

44. See Section 25.9, “Guidelines for High-Speed Interface Termination.”

46. Must be high during HRESET. It is recommended to leave the pin open during HRESET since it has internal pullup resistor.

47. Must be pulled down with 4.7-kΩ resistor.

48. This pin must be left no connect.

49. A pull-up on LGPL4 is required for systems that boot from local bus (GPCM)-controlled NOR Flash.

Table 79 provides the pin-out listing for the MPC8567E 1023 FC-PBGA package.

Table 79. MPC8567E Pinout Listing

Power

Supply

Signal

Package Pin Number

PCI

Pin Type

Notes

PCI_AD[31:0]

AE19, AG20, AF19, AB20, AC20, AG21, AG22,

AB21, AF22, AH22, AE22, AF20, AB22, AE20,

AE23, AJ23, AJ24, AF27, AJ26, AE29, AH24,

AD24, AE25, AE26, AH27, AG27, AJ25, AE30,

AF26, AG26, AF28, AH26

I/O

OV

—

DD

PCI_C_BE[3:0]

PCI_GNT[4:1]

PCI_GNT0

PCI_IRDY

AC22, AD20, AE28, AH25

I/O

O

OV

—

5,9,35

—

DD

AF29, AB18, AC18, AD18

AE18

AF23

AJ22

AF24

AD22

AE24

AK24

I/O

2

PCI_PAR

—

PCI_PERR

PCI_SERR

PCI_STOP

PCI_TRDY

2

2,4

2

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

112

Package and Pinout

Table 79. MPC8567E Pinout Listing (continued)

Package Pin Number

Power

Notes

Signal

Pin Type

Supply

PCI_REQ[4:1]

PCI_REQ[0]

PCI_CLK

AG29, AJ27, AH29, AB17

I

OV

—

39

2

DD

AC17

AM26

AK23

AE21

AB19

I/O

I

PCI_DEVSEL

PCI_FRAME

PCI_IDSEL

I/O

I

2

—

DDR SDRAM Memory Interface

MDQ[0:63]

B22, C22, E20, A19, C23, A22, A20, C20, G22, E22,

E16, F16, E23, F23, F17, H17, A18, A17, B16, C16,

B19, C19, E17, A16, A13, A14, A12, C12, A15, B15,

B13, C13, G12, G11, H8, F8, D13, F12, E9, F9, A7,

B7, C5, E5, C8, E8, D6, A5, E6, G6, E1, F1, G7, E7,

E2, D1, C4, A3, B1, C1, A4, B4, C2, D2

I/O

GV

—

DD

MECC[0:7]

MDM[0:8]

MDQS[0:8]

MA[0:15]

C11, E11, D9, A8, D12, A11, A9, C9

I/O

O

GV

—

DD

A21, E21, D18, B14, F11, A6, G5, A2, A10

D21, G20, C17, D14, E10, C6, F4, C3, C10

C21, G21, C18, D15, F10, C7, F5, D3, B10

I/O

O

K7, H7, L7, J8, K8, L10, H9, K9, H10, G10, L6, K10,

K11, H3, J11, J12

MBA[0:2]

MWE

K4, H6, L13

O

GV

—

11

—

36

DD

K3

MCAS

L3

O

MRAS

K6

O

MCKE[0:3]

MCS[0:3]

MCK[0:5]

MODT[0:3]

MDIC[0:1]

L14, G13, K12, J13

J5, H2, K5, K2,

G15, F20, E4, F14, E19, G3

G14, F19, E3, F13, E18, G2

G4, J1, J4, K1

O

G1, H1

I/O

Local Bus Controller Interface

LAD[0:31]

M26, C30, F31, L24, G26, D30, M25, L26, D29,

G32, G28, K26, B32, M24, G29, L25, E29, J23, B30,

A31, J24, K23, H25, H23, F26, C28, B29, E25, D26,

G24, A29, E27,

I/O

BV

—

DD

LDP[0:3]

LA[27]

G30, J26, H28, E26

F29

I/O

O

BV

—

5,9

DD

LA[28:31]

H24, C32, F30, H26

O

5,7,9

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

113

Package and Pinout

Table 79. MPC8567E Pinout Listing (continued)

Package Pin Number

Power

Supply

Signal

Pin Type

Notes

LALE

G31

O

I/O

O

I/O

O

I

BVdd

8

LBCTL

LCS[0:4]

LCS5

L27

M27, H32, J28, J30, B31

BV

—

DD

G25

C29

1

LCS6

1

LCS7

A30

1

LWE[0]

LWE[1]

LWE[2]

LWE[3]

LGPL0

LGPL1

LGPL2

LGPL3

LGPL4

LGPL5

LCKE

H30

5,9

5,9,46

5,8,9

5,9

49

E28

E32

G27

E30

J27

D32

J25

C25

F32

5,9

—

C31

LCLK[0:2]

LSYNC_IN

LSYNC_OUT

C27, C26, D25

A28

—

A27

O

—

DMA

DMA_DACK[0]

DMA_DREQ[0]

DMA_DDONE[0]

AM27

AK28

AK26

O

I

OV

5,9,47

—

DD

O

—

Programmable Interrupt Controller

UDE

AG32

AF32

I

OV

—

DD

MCP

IRQ[0:7]

AD30, AG31, AL30, AF31, AD29, AK30, AG30,

AF30

IRQ_OUT

GPIN[0:7]

AD28

O

I

OV

2,4

—

DD

GPIO

AC14, AD15, AB14, AH15, AD14, AH17, AE15,

AC15

LV

DD

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

114

Package and Pinout

Table 79. MPC8567E Pinout Listing (continued)

Package Pin Number

Power

Notes

Signal

Pin Type

Supply

GPOUT[0:7]

AM16, AJ15, AJ17, AF13, AK17, AH16, AG17,

AL15

O

LV

—

DD

2

I C interface

IIC1_SCL

IIC1_SDA

AE32

AD32

I/O

OV

4,27

DD

SerDes

SD_RX[0:7]

SD_TX[0:7]

SD_PLL_TPD

SD_RX_CLK

L30, M32, N30, P32, U30, V32, W30, Y32

I

SCOREVDD 43,44

L29, M31, N29, P31, U29, V31, W29, Y31

P26, R24, T26, U24, W24, Y26, AA24, AB26

O

I

XV

44

DD

P27, R25, T27, U25, W25, Y27, AA25, AB27

R32

U28

V28

V26

V27

T32

T31

SCOREVDD

24

XV

41,44

48

DD

SD_RX_FRM_CTL

Reserved

I

—

I

—

Reserved

—

48

SD_REF_CLK

SCOREVDD

44

I

44

QUICC Engine

PA[0:4]

PA[5]

M1, M2, M5, M4, M3

N3

I/O

OV

5,17

29

DD

PA[6:31]

M6, M7, M8, N5, M10, N1, M11, M9, P1, N9, N7, R6,

R2, P7, P5, R4, P3, P11, P10, P9, R8, R7, R5, R3,

R1, T2

—

PB[4:31]

PC[0:31]

T1, R11, R9, T6, T5, T4, T3, U10, T9, T8, T7, U5,

U3, U1, T11, V1, U11, U9, U7, V5, W4, V3, W2, V9,

W8, V7, W6, W3

I/O

OV

—

DD

W1, V11, V10, W11, W9, W7, W5, Y4, Y3, Y2, Y1,

Y8, Y7, Y6, Y5, AA1, Y11, AA10, Y9, AA9, AA7,

AA5, AA3, AB3, AC2, AB1, AA11, AB7, AC6, AB5,

AC4, AB9

PD[4:31]

AC8, AD1, AC1, AC7, AB10, AC5, AD3, AD2, AC3,

AE4, AF1, AE3, AE1, AD6, AG2, AG1, AD5, AD7,

AD4, AH1, AK3, AD8, AF5, AM4, AC9, AL2, AE5,

AF3

I/O

OV

—

DD

PE[5:7]

AM6, AL5, AL9

I/O

TV

—

5

DD

PE[8:10]

PE[11:19]

AM9, AM10, AL10

AJ9, AH10, AM8, AK9, AL7, AL8, AH9, AM7, AH8

—

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

115

Package and Pinout

Table 79. MPC8567E Pinout Listing (continued)

Package Pin Number

Power

Supply

Signal

Pin Type

Notes

PE[20]

AH6

I/O

OV

TV

OV

—

5

DD

PE[21:23]

PE[24]

AM1, AE10, AG5

AJ1

5

PE[25:31]

PF[7]

AH2, AM2, AE9, AH5, AL1, AD9, AL4

—

5

AG9

PF[8:10]

PF[11:19]

PF[20]

AF10, AK7, AJ6

AH7, AF9, AJ7, AJ5, AF7, AG8, AG7, AM5, AK5

—

5,33

—

AK1

PF[21:22]

PF[23:31]

AH3, AL3

AB11, AE7, AJ3, AC11, AG6, AG3, AH4, AM3,

AD11

System Control

HRESET

AL21

AL23

AK18

AL17

AM17

I

O

I

OV

—

29

—

DD

HRESET_REQ

SRESET

CKSTP_IN

CKSTP_OUT

I

—

O

2,4

Debug

TRIG_IN

AL29

I

OV

—

DD

TRIG_OUT

AM29

O

6,9,19,

29

MSRCID[0:1]

MSRCID[2:4]

MDVAL

AK29, AJ29

AM28, AL28, AK27

AJ28

O

OV

5,6,9

6,19,29

6

DD

CLK_OUT

AF18

11

Clock

RTC

AH20

AK22

I

OV

—

DD

SYSCLK

JTAG

TCK

TDI

AH18

AH19

AJ18

AK19

AK20

I

OV

—

12

11

12

DD

TDO

TMS

TRST

O

I

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

116

Package and Pinout

Table 79. MPC8567E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

DFT

Pin Type

Supply

L1_TSTCLK

L2_TSTCLK

LSSD_MODE

TEST_SEL

AJ20

AJ19

AH31

AJ31

I

OV

25

DD

Thermal Management

THERM0

THERM1

AB30

AB31

—

14

—

Power Management

AK21

ASLEEP

GND

O

OV

9,19,29

—

DD

Power and Ground Signals

A23, A26, A32, B3, B6, B9, B12, B18, B21, B23,

B24, B25, B26, B27, C15, C24, D5, D8, D11, D17,

D20, D23, D24, D28, E13, E14, E24, E31, F3, F7,

F15, F18, F22, F24, F27, G8, G16, G19, G23, H5,

H12, H13, H15, H16, H18, H19, H21, H22, J2, J7,

J10, J14, J15, J16, J17, J18, J19, J20, J21, J22,

J29, J31, J32, K14, K15, K16, K17, K18, K19, K20,

K21, K22, K24, L1, L4, L9, L12, L15, L16, L17, L18,

L19, L20, L21, L22, L23, M12, M13, M18, M20, M21,

M23, N4, N8, N11, N13, N15, N17, N19, N21, N23,

P2, P6, P12, P14, P16, P18, P20, P22, P23, R10,

R13, R15, R17, R19, R21, R23, T12, T14, T16, T18,

T20, T22, T23, U4, U8, U13, U15, U17, U19, U21,

U23, V2, V6, V12, V14, V16, V18, V20, V22, V23,

W10, W13, W15, W17, W19, W21, W23, Y12, Y14,

Y16, Y18, Y20, Y22, Y23, AA4, AA8, AA12, AA13,

AA15, AA17, AA19, AA21, AA22, AA23, AB2, AB6,

AB12, AB23, AB29, AB32, AC10, AC23, AC24,

AC25, AC28, AC29, AC30, AC31, AC32, AD16,

AD17, AD19, AD21, AD25, AD26, AD27, AD31,

AE8, AE12, AF2, AF4, AF6, AF16, AF21, AF25,

AG10, AG14, AG18, AG24, AG28, AH23, AJ4, AJ8,

AJ12, AJ21, AJ30, AJ32, AK2, AK10, AK16, AK32,

AL6, AL14, AL18, AL19, AL20, AL22, AL24, AL25,

AL26, AL31, AL32, AM19, AM21, AM23, AM25,

AM30, AM31, AM32

—

SCOREGND

XGND

K28, K29, K30, L28, L31, M28, M30, N32, P28, P30, Ground for

—

R28, T29, U32, V30, W28, W31, Y28, Y29, AA29,

AA30, AA32, AB28

SerDes

receiver

N24, N26, P25, R27, T24, U26, V25, W27, Y24,

AA26, AB25, AC27

Ground for

SerDes

transmitter

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

117

Package and Pinout

Table 79. MPC8567E Pinout Listing (continued)

Package Pin Number

Power

Supply

Signal

Pin Type

Notes

OVDD

N2, N6, N10, P4, P8, T10, U2, U6, V4, V8, Y10,

AA2, AA6, AB4, AB8, AC19, AC21, AD10, AD23,

AE2, AE6, AE27, AE31, AG4, AG19, AG23, AG25,

Power for

PCI and

other

OVDD

—

AH21, AH28, AH30, AH32, AJ2, AK4, AK25, AK31, standards

AL27

(3.3V)

LVDD

TVDD

AC12, AC16, AF12, AF14, AG16, AK12, AK14,

AL16

Power for

GPIO

LVDD

TVDD

—

AF8, AJ10, AK6, AK8

Power for

QE UCC1

and UCC2

Ethernet

Interface

(2,5V,3.3V)

GVDD

B2, B5, B8, B11, B17, B20, C14, D4, D7, D10, D16,

D19, D22, E12, E15, F2, F6, F21, G9, G17, G18,

H4, H11, H14, H20, J3, J6, J9, K13, L2, L5, L8, L11

Power for

DDR1 and

DDR2

GVDD

—

DRAM I/O

voltage

(1.8V,2.5V)

BVDD

VDD

B28, D27, D31, F25, F28, H27, H29, H31, K25, K27 Power for

BVDD

VDD

—

Local Bus

(1.8V, 2.5V,

3.3V)

M14, M15, M19, M22, N12, N14, N16, N18, N20,

Power for

N22, P13, P15, P17, P19, P21, R12, R14, R16, R18, Core (1.1)

R20, R22, T13, T15, T17, T19, T21, U12, U14, U16,

U18, U20, U22, V13, V15, V17, V19, V21, W12,

W14, W16, W18, W20, W22, Y13, Y15, Y17, Y19,

Y21, AA14, AA16, AA18, AA20

SCOREVDD

XVDD

K31, L32, M29, N28, N31, P29, T28, T30, U31, V29, Core Power SCOREVDD

—

26

W32, Y30, AA31

for SerDes

transceivers

(1.1V)

N25, N27, P24, R26, T25, U27, V24, W26, Y25,

AA27, AB24, AC26

Pad Power

for SerDes

transceivers

(1.1V)

XVDD

—

AV

A25

Power for

local bus

PLL

DD_LBIU

(1.1V)

AV

AM22

AM18

Power for

PCI PLL

(1.1V)

—

26

DD_PCI

DD_CE

Power for

QE PLL

(1.1V)

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

118

Package and Pinout

Table 79. MPC8567E Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

AV

AM24

Power for

e500 PLL

(1.1V)

—

26

DD_CORE

DD_PLAT

DD_SRDS

AM20

R29

Power for

CCB PLL

(1.1V)

Power for

SRDSPLL

(1.1V)

AGND_SRDS

R31

Ground for

SRDSPLL

SENSEVDD

SENSEVSS

M17

M16

O

V

13

DD

—

Analog Signals

MVREF

A24

I

MVREF

—

Reference

voltage

signal for

DDR

SD_IMP_CAL_RX

SD_IMP_CAL_TX

SD_PLL_TPA

K32

I

200Ω to GND

100Ω to GND

—

24

AA28

R30

O

Reserved Pins

Reserved

AE17, AH12, AL13, AL11, AK13, AH13, AG11,

AD13, AM13, AG12, AC13, AL12, AJ16, AM15,

AK15

N/A

42

45

AF17, AM14, AE14, AM11, AK11, AF11, AJ14,

AJ13, AD12, AE13, AG13, AB13, AE11, AH11,

AM12, AJ11, AB15, AB16, AE16, AG15, AF15,

AH14

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

119

Package and Pinout

Table 79. MPC8567E Pinout Listing (continued)

Package Pin Number

Power

Supply

Signal

Pin Type

Notes

Notes:

1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the local

bus controller section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2.

2. Recommend a weak pull-up resistor (2–10 KΩ) be placed on this pin to OV

.

DD

4. This pin is an open drain signal.

5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the

reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if the

signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset,

then a pullup or active driver is needed.

6. Treat these pins as no connects (NC) unless using debug address functionality.

7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down

resistors. See Section 23.2, “CCB/SYSCLK PLL Ratio.”

8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ

pull-up or pull-down resistors. See the Section 23.3, “e500 Core PLL Ratio.”

9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or

because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.

11.This output is actively driven during reset rather than being three-stated during reset.

12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.

13.These pins are connected to the V /GND planes internally and may be used by the core power supply to improve tracking

DD

and regulation.

14.Internal thermally sensitive resistor. These two pins are not ESD protected.

17.. The value of PA[0:4] during reset set the QE clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down

resistors. See Section 23.4, “QE/SYSCLK PLL Ratio.”

19. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state

during reset.

20. This pin is only an output in FIFO mode when used as Rx Flow Control.

24. Do not connect.

25.These are test signals for factory use only and must be pulled up (100 - 1 K) to OVDD for normal machine operation.

26. Independent supplies derived from board VDD.

27. Recommend a pull-up resistor (~1 K.) be placed on this pin to OV

.

DD

29. The following pins must NOT be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE,

MSRCID[2:4], ASLEEP, PA[5].

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

120

Freescale Semiconductor

Clocking

Notes

Table 79. MPC8567E Pinout Listing (continued)

Package Pin Number

Power

Supply

Signal

Pin Type

30. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively

driven.

33. PF[21:22] are multiplexed as cfg_dram_type[0:1]. THEY MUST BE VALID AT POWER-UP, EVEN BEFORE HRESET

ASSERTION.

35. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled down

to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCIn_AD pins as "No Connect"

or terminated through 2–10 KΩ pull-up resistors with the default of internal arbiter if the PCIn_AD pins are not connected to any

other PCI device. The PCI block will drive the PCIn_AD pins if it is configured to be the PCI arbiter—through POR config

pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any other PCI

device connected on the bus.

36.MDIC[0] is grounded through an 18.2-Ω precision 1% resistor and MDIC[1] is connected to GV through an 18.2-Ω precision

DD

1% resistor. These pins are used for automatic calibration of the DDR IOs.

39. If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCI_CLK . Otherwise the processor

will not boot up.

41.These pins should be tied to SCOREGND through a 300 ohm resistor if the high speed interface is used.

43. It is highly recommended that unused SD_RX/SD_RX lanes should be powered down with lane_x_pd. Otherwise the receivers

will burn extra power and the internal circuitry may develop long term reliability problems.

44. See Section 25.9, “Guidelines for High-Speed Interface Termination.”

46. Must be high during HRESET. It is recommended to leave the pin open during HRESET since it has internal pullup resistor.

47. Must be pulled down with 4.7-kΩ resistor.

48. This pin must be left no connect.

49. A pull-up on LGPL4 is required for systems that boot from local bus (GPCM)-controlled NOR Flash.

23 Clocking

This section describes the PLL configuration of the MPC8568E. Note that the platform clock is identical

to the core complex bus (CCB) clock.

23.1 Clock Ranges

Table 80 provides the clocking specifications for the processor cores and Table 81 provides the clocking

specifications for the DDR/DDR2 memory bus. Table 82 provides the clocking specifications for the local

bus.

Table 80. Processor Core Clocking Specifications

Maximum Processor Core Frequency

Characteristic

800 MHz

1000 MHz

1333 MHz

Unit

Notes

Min

533

Max

Min

533

Max

Min

533

Max

e500 core processor frequency

800

1000

1333

MHz

1, 2

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 23.2, “CCB/SYSCLK PLL Ratio,” and Section 23.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

121

Clocking

Table 81. DDR/DDR2 Memory Bus Clocking Specifications

Maximum Processor Core Frequency

Characteristic

800, 1000, 1333 MHz

Unit

Notes

Min

166

Max

DDR/DDR2 Memory bus clock frequency

Notes:

266

MHz

1, 2

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the

resulting SYSCLK frequency, e500 core frequency, and CCB clock frequency do not exceed their respective maximum

or minimum operating frequencies.

2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the platform clock frequency.

Table 82. Local Bus Clocking Specifications

Maximum Processor Core Frequency

Characteristic

800, 1000, 1333 MHz

Unit

Notes

Min

25

Max

Local bus clock speed (for Local Bus Controller)

166

MHz

1

Notes:

1. The Local bus clock speed on LCLK[0:2] is determined by CCB clock divided by the Local Bus PLL ratio programmed

in LCCR[CLKDIV]. See the reference manual for more information on this.

23.2 CCB/SYSCLK PLL Ratio

The CCB clock is the clock that drives the e500 core complex bus (CCB) and is also called the platform

clock. The frequency of the CCB is set using the following reset signals, as shown in Table 83:

•

SYSCLK input signal

Binary value on LA[28:31] at power up

Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note

that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB

frequency must equal the DDR data rate.

For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.

Table 83. CCB Clock Ratio

Binary Value of

LA[28:31] Signals

Binary Value of

LA[28:31] Signals

CCB:SYSCLK Ratio

0000

0001

0010

0011

0100

16:1

Reserved

2:1

1000

1001

1010

1011

1100

8:1

9:1

10:1

3:1

Reserved

12:1

4:1

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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Clocking

Table 83. CCB Clock Ratio (continued)

Binary Value of

LA[28:31] Signals

Binary Value of

CCB:SYSCLK Ratio

LA[28:31] Signals

0101

0110

0111

5:1

6:1

1101

1110

1111

20:1

Reserved

23.3 e500 Core PLL Ratio

Table 84 describes the clock ratio between the e500 core complex bus (CCB)platform and the e500 core

clock. This ratio is determined by the binary value of LBCTL, LALE and LGPL2 at power up, as shown

in Table 84.

Table 84. e500 Core to CCB Clock Ratio

Binary Value of

LBCTL, LALE,

LGPL2 Signals

Binary Value of

LBCTL, LALE,

LGPL2 Signals

e500 core:CCB Clock Ratio

000

001

010

011

4:1

9:2

100

101

110

111

2:1

5:2

3:1

7:2

Reserved

3:2

23.4 QE/SYSCLK PLL Ratio

The QE clock is defined by a multiplier and divisor applied to the SYSCLK input signal, as shown in the

following equation:

QE clock = SYSCLK * cfg_ce_pll[0:4].

The multiplier and divisor is determined by the binary value of PA[0:4] at power up.

Table 85. QE Clock Multiplier cfg_ce_pll[0:4]

Binary Value of

PA[0:4] Signals

Binary Value of

PA[0:4] Signals

cfg_ce_pll[0:4]

0_0000

0_0001

0_0010

0_0011

0_0100

0_0101

0_0110

0_0111

16

1_0000

1_0001

1_0010

1_0011

1_0100

1_0101

1_0110

1_0111

16

17

18

19

20

21

22

23

Reserved

2

3

4

5

6

7

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

123

Clocking

Table 85. QE Clock Multiplier cfg_ce_pll[0:4] (continued)

Binary Value of

PA[0:4] Signals

Binary Value of

PA[0:4] Signals

cfg_ce_pll[0:4]

0_1000

0_1001

0_1010

0_1011

0_1100

0_1101

0_1110

0_1111

8

1_1000

1_1001

1_1010

1_1011

1_1100

1_1101

1_1110

1_1111

24

25

26

27

28

29

30

31

9

10

11

12

13

14

15

23.5 Frequency Options

23.5.1 SYSCLK to Platform Frequency Options

Table 86 shows the expected frequency values for the platform frequency when using a CCB clock to

SYSCLK ratio in comparison to the memory bus clock speed.

Table 86. Frequency Options of SYSCLK with Respect to Memory Bus Speeds

CCB clock to

SYSCLK (MHz)

SYSCLK Ratio

16.66

25

33.33

41.66

66.66

83

100

111

133.33

166

Platform /CCB clock Frequency (MHz)

2

3

333

500

333

445

400

533

4

333

415

500

400

500

5

333

400

533

6

8

333

375

417

500

9

10

12

16

20

333

400

533

400

500

333

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

124

Thermal

23.5.2 Minimum Platform Frequency Requirements for PCI Express, SRIO,

PCI interfaces Operation

For proper PCI Express operation, the CCB clock frequency must be greater than:

527 MHz × (PCI Express link width)

----------------------------------------------------------------------------------------------

8

Note that the “PCI Express link width” in the above equation refers to the negotiated link width as the

result of PCI Express link training, which may or may not be the same as the link width POR selection.

For proper Serial RapidIO operation, the CCB clock frequency must be greater than:

2 × (0.80) × (serial RapidIO interface frequency) × (serial RapidIO link width)

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

64

For proper PCI operation in synchronous mode, the minimum CCB:SYSCLK ratio is 6:1.

24 Thermal

This section describes the thermal specifications of the MPC8568E.

24.1 Thermal Characteristics

Table 87 provides the package thermal characteristics.

Table 87. Package Thermal Characteristics

Characteristic

Symbol

Value

Unit

Notes

Junction-to-ambient Natural Convection on single layer board (1s)

Junction-to-ambient Natural Convection on four layer board (2s2p)

Junction-to-ambient (@200 ft/min or 1 m/s) on single layer board (1s)

Junction-to-ambient (@200 ft/min or 1 m/s) on four layer board (2s2p)

Junction-to-board

R

21

17

°C/W

•C/W

1, 2

3

θJA

θJB

θJC

16

13

9

Junction-to-case

<0.1

4

Notes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance

2. Per JEDEC JESD51-6 with the board horizontal.

3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL

SPEC-883, Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 °C/W.

24.2 Thermal Management Information

This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA)

package for air-cooled applications. Proper thermal control design is primarily dependent on the

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

125

Thermal

system-level design—the heat sink, airflow, and thermal interface material. The recommended attachment

method to the heat sink is illustrated in Figure 69. The heat sink should be attached to the printed-circuit

board with the spring force centered over the die. This spring force should not exceed 10 pounds force.

FC-PBGA Package

Heat Sink

Clip

Thermal Interface Material

Die

Printed-Circuit Board

Figure 69. Package Exploded Cross-Sectional View with Several Heat Sink Options

The system board designer can choose between several types of heat sinks to place on the device. There

are several commercially-available heat sinks from the following vendors:

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

603-224-9988

781-769-2800

408-749-7601

Advanced Thermal Solutions

89 Access Road #27.

Norwood, MA02062

Internet: www.qats.com

Alpha Novatech

473 Sapena Ct. #15

Santa Clara, CA 95054

Internet: www.alphanovatech.com

International Electronic Research Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

Millennium Electronics (MEI)

Loroco Sites

408-436-8770

671 East Brokaw Road

San Jose, CA 95112

Internet: www.mei-millennium.com

Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal

performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several

heat sinks offered by Aavid Thermalloy, Advanced Thermal Solutions, Alpha Novatech, IERC, and

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

126

Freescale Semiconductor

Thermal

Millennium Electronics offer different heat sink-to-ambient thermal resistances, that will allow the

MPC8568E to function in various environments.

24.2.1 Recommended Thermal Model

For system thermal modeling, the MPC8568E thermal model without a lid is shown in Figure 70. The

substrate is modeled as a block 33x33x1.18 mm with an in-plane conductivity of 24 W/mK and a

through-plane conductivity of 0.92 W/mK. The solder balls and air are modeled as a single block

33x33x0.58 mm with an in-plane conductivity of 0.034 W/mK and a through plane conductivity of 12.2

W/mK. The die is modeled as 8.2x12.1 mm with a thickness of 0.75 mm. The bump/underfill layer is

modeled as a collapsed thermal resistance between the die and substrate assuming a conductivity of 5.3

W/m•K in the thickness dimension of 0.07 mm. The die is centered on the substrate. The thermal model

uses approximate dimensions to reduce grid. See the case outline for actual dimensions.

Conductivity

Value

Unit

Die

(8.2 × 12.1 × 0.75mm)

Bump/Underfill

die

substrate

Silicon Temperature

W/(m × K)

Z

solder/air

dependent

Side View of Model (Not to scale)

Bump/Underfill

(8.2 × 12.1 × 0.75 mm)

Collapsed Resistance

k

5.3

z

x

Substrate

(33 × 33× 1.18 mm)

Substrate

k

24

x

y

z

24

Heat Source

0.92

Soldera and Air

(33 × 33 × 0.58 mm)

y

k

0.034

x

y

z

Top View of Model (Not to Scale)

0.034

12.2

Figure 70. MPC8568E Thermal Model

24.2.2 Internal Package Conduction Resistance

For the packaging technology, shown in Table 87, the intrinsic internal conduction thermal resistance paths

are as follows:

•

The die junction-to-case thermal resistance

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

127

Thermal

•

The die junction-to-board thermal resistance

Figure 71 depicts the primary heat transfer path for a package with an attached heat sink mounted to a

printed-circuit board.

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Internal Resistance

Printed-Circuit Board

Radiation

Convection

External Resistance

(Note the internal versus external package resistance)

Figure 71. Package with Heat Sink Mounted to a Printed-Circuit Board

The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is

conducted through the silicon, then through the heat sink attach material (or thermal interface material),

and finally to the heat sink. The junction-to-case thermal resistance is low enough that the heat sink attach

material and heat sink thermal resistance are the dominant terms.

24.2.3 Thermal Interface Materials

A thermal interface material is required at the package-to-heat sink interface to minimize the thermal

contact resistance. For those applications where the heat sink is attached by spring clip mechanism,

Figure 72 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,

graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.

As shown, the performance of these thermal interface materials improves with increasing contact pressure.

The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a

thermal resistance approximately six times greater than the thermal grease joint.

Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see

Figure 69). Therefore, the synthetic grease offers the best thermal performance, especially at the low

interface pressure.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

128

Freescale Semiconductor

Thermal

Silicone Sheet (0.006 in.)

Bare Joint

2

Floroether Oil Sheet (0.007 in.)

Graphite/Oil Sheet (0.005 in.)

Synthetic Grease

1.5

1

0.5

0

10

20

30

Contact Pressure (psi)

Figure 72. Thermal Performance of Select Thermal Interface Materials

40

50

60

70

80

The system board designer can choose between several types of thermal interface. There are several

commercially-available thermal interfaces provided by the following vendors:

Chomerics, Inc.

781-935-4850

77 Dragon Ct.

Woburn, MA 01888-4014

Internet: www.chomerics.com

Dow-Corning Corporation

Dow-Corning Electronic Materials

2200 W. Salzburg Rd.

800-248-2481

Midland, MI 48686-0997

Internet: www.dow.com

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

Phoenix, AZ 85044

888-642-7674

800-347-4572

Internet: www.microsi.com

The Bergquist Company

th

18930 West 78 St.

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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129

System Design Information

Thermagon Inc.

888-246-9050

4707 Detroit Ave.

Cleveland, OH 44102

Internet: www.thermagon.com

25 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8568E.

25.1 System Clocking

This device includes six PLLs, as follows:

1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The

frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio

configuration bits as described in Section 23.2, “CCB/SYSCLK PLL Ratio.”

2. The e500 core PLL generates the core clock using the platform clock as the input. The frequency

ratio between the e500 core clock and the platform clock is selected using the e500 PLL ratio

configuration bits as described in Section 23.3, “e500 Core PLL Ratio.”

3. The PCI PLL generates the clocking for the PCI bus

4. The local bus PLL generates the clock for the local bus.

5. There is a PLL for the SerDes block.

6. QE PLL generates the QE clock from the externally supplied SYSCLK.

25.2 Power Supply Design and Sequencing

25.2.1 PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins

(AV

, AV

, and AV

, AV

respectively). The AV

DD_PLAT

DD_CORE

DD_PCI

DD_LBIU

DD_SRDS

DD_CE

DD

level should always be equivalent to V , and preferably these voltages will be derived directly from V

DD

through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits per PLL power supply as illustrated in Figure 73, one to each of the

AV type pins. By providing independent filters to each PLL the opportunity to cause noise injection

DD

from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

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System Design Information

Each circuit should be placed as close as possible to the specific AV type pin being supplied to minimize

DD

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV

type pin, which is on the periphery of 1023FC-PBGA the footprint, without the inductance of vias.

DD

Figure 73 shows the PLL power supply filter circuits for all PLLs except SerDes PLL.

10 Ω

V

AV

DD

2.2 μF

Low ESL Surface Mount Capacitors

GND

Figure 73. MPC8568E PLL Power Supply Filter Circuit

The AV

signal provides power for the analog portions of the SerDes PLL. To ensure stability of

DD_SRDS

the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in

following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the

AV

and AGND_SRDS ball to ensure it filters out as much noise as possible. The 0.003-µF

DD_SRDS

capacitor is closest to the ball, followed by the 2.2-µF capacitors, and finally the 1 ohm resistor to the board

supply plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces

should be kept short, wide and direct.

1.0 Ω

SCOEVDD

AV

DD_SRDS

1

0.003 μF

2.2 μF

AGND_SRDS

1. An 0805 sized capacitor is recommended for system initial bring-up.

Figure 74. SerDes PLL Power Supply Filter

Note the following:

•

AV

should be a filtered version of SCOREVDD.

DD_SRDS

The transmitter output signals on the SerDes interface are fed from the XV power plan.

DD

Power: XVDD consumes less than 300mW. SCOREVDD + AV

750mW.

consumes less than

DD_SRDS

25.3 Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

MPC8568E system, and the device itself requires a clean, tightly regulated source of power. Therefore, it

is recommended that the system designer place at least one decoupling capacitor at each V , TV

,

DD

BV , OV , GV , and LV pin of the device. These decoupling capacitors should receive their

DD

power from separate V TV , BV , OV , GV , and LV and GND power planes in the PCB,

DD,

DD

utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a

standard escape pattern. Others may surround the part.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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System Design Information

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the V , TV , BV , OV , GV , and LV planes, to enable quick recharging of the

DD

smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating

to ensure the quick response time necessary. They should also be connected to the power and ground

planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS

tantalum or Sanyo OSCON).

25.4 SerDes Block Power Supply Decoupling Recommendations

The SerDes block requires a clean, tightly regulated source of power (SCOREVDD and XV ) to ensure

DD

low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is

outlined below.

Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections

from all capacitors to power and ground should be done with multiple vias to further reduce inductance.

•

First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible

to the supply balls of the device. Where the board has blind vias, these capacitors should be placed

directly below the chip supply and ground connections. Where the board does not have blind vias,

these capacitors should be placed in a ring around the device as close to the supply and ground

connections as possible.

•

Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be

done for all SerDes supplies.

Third, between the device and any SerDes voltage regulator there should be a 10-µF, low

equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT

tantalum chip capacitor. This should be done for all SerDes supplies.

25.5 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. All unused active low inputs should be tied to V

TV , BV , OV , GV and LV as

DD,

DD DD DD DD DD

required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must

remain unconnected. Power and ground connections must be made to all external V TV

L

,

DD

DD, VDD,

BV , OV , GV and GND pins of the device.

DD

25.6 Pull-Up and Pull-Down Resistor Requirements

The MPC8568E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins

2

including I C pins and MPIC interrupt pins.

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 75. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions as most have asynchronous behavior and spurious assertion will

give unpredictable results.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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System Design Information

Refer to the PCI 2.2 specification for all pull-ups required for PCI.

The following pins must NOT be pulled down during power-on reset: HRESET_REQ,

TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP, PA[5].

Three test pins also require pull-up resistors (100 Ω–1 KΩ). These pins are L1_TSTCLK, L2_TSTCLK,

and LSSD_MODE. These signals are for factory use only and must be pulled up to OV for normal

DD

machine operation.

Refer to the PCI 2.2 specification for all pull-ups required for PCI.

25.7 Configuration Pin Muxing

The MPC8568E provides the user with power-on configuration options which can be set through the use

of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins. These pins are generally used

as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled

and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped

with an on-chip pull-up resistors of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to

pull the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET

(and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the

HRESET is negated, the pull-up resistor is also disabled, thus allowing functional operation of the pin as

an output with minimal signal quality or delay disruption. The default value for all configuration bits

treated this way has been encoded such that a high voltage level puts the device into the default state and

external resistors are needed only when non-default settings are required by the user.

Careful board layout with stubless connections to these pull-down resistors coupled with the large value

of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus

configured.

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up

devices.

25.8 JTAG Configuration Signals

Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 specification, but is provided on all processors that implement Power Architecture. The

device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not

interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using

only the TCK and TMS signals, generally systems will assert TRST during power-on reset. Because the

JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying

TRST to HRESET is not practical.

The COP function of these processors allows a remote computer system (typically, a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

interface connects primarily through the JTAG port of the processor, with some additional status

monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

133

System Design Information

to fully control the processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be

merged into these signals with logic.

The arrangement shown in Figure 75 allows the COP to independently assert HRESET or TRST, while

ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,

TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted.

The COP header shown in Figure 75 adds many benefits—breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features are possible through this interface—and

can be as inexpensive as an unpopulated footprint for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on the 0.025"

square-post, 0.100" centered header assembly (often called a Berg header).

There is no standardized way to number the COP header shown in Figure 75; consequently, many different

pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then

left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter

clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in

Figure 75 is common to all known emulators.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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System Design Information

3

SRESET0

SRESET

HRESET

From Target

Board Sources

(if any)

SRESET1

HRESET

10 kΩ

HRESET

OV

13

11

DD

SRESET

OV

DD

10 kΩ

OV

DD

TRST

4

2

1

3

10 Ω

4

VDD_SENSE

6

OV

DD

10 kΩ

5

7

6

8

1

5

CHKSTP_OUT

15

10 kΩ

9

10

12

OV

DD

11

10 kΩ

2

14

KEY

No pin

13

15

CHKSTP_IN

TMS

CHKSTP_IN

TMS

8

9

1

16

TDO

TDI

COP Connector

Physical Pin Out

TDO

3

TDI

TCK

7

2

TCK

NC

10

12

16

NC

Notes:

1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented.

Connect pin 5 of the COP header to OV with a 10-kΩ pull-up resistor.

DD

2. Key location; pin 14 is not physically present on the COP header.

3. Use a NOR gate with sufficient drive strength to drive two inputs.

Figure 75. JTAG Interface Connection

25.9 Guidelines for High-Speed Interface Termination

25.9.1 Unused output

Any of the outputs that are unused should be left unconnected. These signals are:

•

SD_TX[7:0]

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

135

Ordering Information

•

SD_TX[7:0]

25.9.2 Unused input

25.9.2.1 SerDes block power not supplied

If the high speed interface is not used at all, then SCOREVDD/XVDD/AV

all receiver inputs should be tied to the GND as well. This includes:

can be tied to GND,

DD_SRDS

•

SD_RX[7:0]

SD_REF_CLK

SD_RX_CLK

SD_RX_FRM_CTL

25.9.2.2 SerDes Interface Partly used

If the high-speed SerDes interface is partly unused, any of the unused receiver pins should be terminated

as follows:

•

SD_RX[7:0] = tied to SCOREGND

SD_REF_CLK = tied to SCOREGND

NOTE

Power down the unused lane through SERDESCR1[0:7] register

(offset = 0xE_0F08) (This prevents the oscillations and holds the receiver

output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly.

During HRESET/POR, the high-speed interface must be in Serial RapidIO mode and/or PCI Express mode

according to the state of the PE[8:10]. Software must disable this mode through DEVDISR[SRIO] or

DEVDISR[PCIE] accordingly during software initialization.

26 Ordering Information

Contact your local Freescale sales office or regional marketing team for order information.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

136

Freescale Semiconductor

Ordering Information

26.1 Part Marking

Parts are marked as the example shown in Figure 76.

MPC856Xxxxxxx

ATWLYYWW

MMMMM CCCCC

YWWLAZ

FC-PBGA

Notes:

MPC856Xxxxxxx is the orderable part number

ATWLYYWW is the freescale assembly, year and workweek code

MMMMM is the mask code

CCCC is the contry code for assembly.

YWWLAZ is the trace code for assembly.

Figure 76. Part Marking for FC-PBGA Device

26.2 Part Number Decoder

Figure 77 shows the MPC8568E/MPC8567E number decoder.

MPC 856x E C VT ANG J A

Product Code

PPC:

Prototype

Die revision

KMPC: Sample

MPC: Qualified

QE Speed

G: 400

J: 533

Device Number

8568, 8567

DDR speed

G: 400

J: 533

Security

Blank: No Security

E: With Security

CPU Speed

AN: 800

AQ: 1000

AU: 1333

Temperature

Blank: 0 - 105C

C:

-45(Ta) - 105C

Package

VT: Lead Free

Figure 77. MPC8568E Part Number Decoder

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

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137

Document Revision History

27 Document Revision History

Table 88 provides a revision history for the MPC8568E hardware specification.

Table 88. Document Revision History

Rev

Number

Date

Substantive Change(s)

1

10/2010 In Table 78, “MPC8568E Pinout Listing,” and Table 78, “MPC8568E Pinout Listing,” added footnote

49 to LGPL4.

0

05/2009 Initial public release.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

138

Freescale Semiconductor

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Document Number: MPC8568EEC

Rev. 1

10/2010


型号：	PPC8567ECVTAQGGA
厂家：	Freescale
描述：	MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications MPC8568E / MPC8567E的PowerQUICC III集成处理器硬件规格外围集成电路 PC 时钟
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