SCF5250VM120 [FREESCALE]
Integrated ColdFire Microprocessor Data Sheet;型号: | SCF5250VM120 |
厂家: | Freescale |
描述: | Integrated ColdFire Microprocessor Data Sheet 时钟 外围集成电路 |
文件: | 总56页 (文件大小:653K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: SCF5250EC
Freescale Semiconductor
Data Sheet: Technical Data
Rev. 1.3, 07/2006
SCF5250
Package Information
MAPBGA–196
LQFP-144
SCF5250
Ordering Information: See Table 1 on page 2
Integrated ColdFire®
Microprocessor
Data Sheet
Contents
1 Introduction
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 SCF5250 Block Diagram . . . . . . . . . . . . . . . . 8
3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . 8
4 Electrical Characteristics . . . . . . . . . . . . . . 21
5 Pin-Out and Package Information . . . . . . . . 36
6 Product Documentation . . . . . . . . . . . . . . . . 55
This document provides an overview of the SCF5250
ColdFire processor and general descriptions of
SCF5250 features and its various modules.
®
The SCF5250 was designed as a system
controller/decoder for compressed audio music players,
especially portable and automotive CD and hard disk
drive players. The 32-bit ColdFire core with Enhanced
Multiply Accumulate (EMAC) unit provides optimum
performance and code density for the combination of
control code and signal processing required for audio
decoding and post processing, file management, and
system control.
Low power features include a hardwired CD ROM
decoder, advanced 0.13um CMOS process technology,
1.2V core power supply, and on-chip 128KByte SRAM
that enables Windows Media Audio (WMA) decoding
without the need for external DRAM in CD applications.
The SCF5250 is also an excellent general purpose
system controller with over 110 Dhrystone 2.1 MIPS @
120MHz performance at a very competitive price. The
This document contains information on a product under development. Freescale reserves the right to change or discontinue this
product without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
integrated peripherals and enhanced MAC unit allow the SCF5250 to replace both the microcontroller and
the DSP in certain applications. Most peripheral pins can also be remapped as General Purpose I/O pins.
1.1
Orderable Part Numbers
Table 1 lists the orderable part numbers for the SCF5250 processor.
Table 1. Orderable Part Numbers
Orderable Part
Number
Maximum Clock
Frequency
Operating Temperature
Range
Package Type
Part Status
SCF5250LPV100
SCF5250LAG100
SCF5250PV120
SCF5250AG120
SCF5250DAG1201
SCF5250EAG1202
SCF5250CPV120
SCF5250CAG120
SCF5250VM120
100 MHz
100 MHz
120 MHz
120 MHz
120 MHz
120 MHz
120 MHz
120 MHz
120 MHz
144 pin QFP
144 pin QFP
144 pin QFP
144 pin QFP
144 pin QFP
144 pin QFP
144 pin QFP
144 pin QFP
196 ball MAPBGA
-20°C to 70°C
-20°C to 70°C
-20°C to 70°C
-20°C to 70°C
-20°C to 70°C
-20°C to 70°C
-40°C to 85°C
-40°C to 85°C
-20°C to 70°C
Leaded
Lead Free
Leaded
Lead Free
Lead Free
Lead Free
Leaded
Lead Free
Lead Free
1
SCF5250DAG120—This device has the same feature set, pin assignment and specification as SCF5250AG120 with the
addition of including the cost of the MP3 decoder royalty to be paid to Thomson Licensing S.A. for use of the MP3 patent rights
described at http://mp3licensing.com/patents/index.html.
2
SCF5250EAG120—This device has the same feature set, pin assignment and specification as SCF5250AG120 with the
addition of including the cost of the MP3 encoder and decoder royalty to be paid to Thomson Licensing S.A. for use of the MP3
patent rights described at http://mp3licensing.com/patents/index.html.
1.2
SCF5250 Features
This section provides brief descriptions of the features of the SCF5250 processor.
1.2.1
ColdFire V2 Core
The ColdFire processor Version 2 core consists of two independent, decoupled pipeline structures to
maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage
pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage
operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then
executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer
that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP,
which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline
featuring a traditional RISC data path with a dual-read-ported register file feeding an arithmetic/logic unit
(ALU).
SCF5250 Data Sheet: Technical Data, Rev. 1.3
2
Freescale Semiconductor
1.2.2
DMA Controller
The SCF5250 provides four fully programmable DMA channels for quick data transfer. Single and dual
address mode is supported with the ability to program bursting and cycle stealing. Data transfer is
selectable as 8, 16, 32, or 128-bits. Packing and unpacking is supported.
Two internal audio channels and the dual UART can be used with the DMA channels. All channels can
perform memory to memory transfers. The DMA controller has a user-selectable, 24- or 16-bit counter and
a programmable DMA exception handler.
External requests are not supported.
1.2.3
Enhanced Multiply and Accumulate Module (EMAC)
The integrated EMAC unit provides a common set of DSP operations and enhances the integer multiply
instructions in the ColdFire architecture. The EMAC provides functionality in three related areas:
1. Faster signed and unsigned integer multiplies
2. New multiply-accumulate operations supporting signed and unsigned operands
3. New miscellaneous register operations
Multiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensions
for signed and unsigned integers plus signed, fixed-point fractional input operands. The EMAC has a
single-clock issue for 32x32-bit multiplication instructions and implements a four-stage execution
pipeline.
1.2.4
Instruction Cache
The instruction cache improves system performance by providing cached instructions to the execution unit
in a single clock. The SCF5250 processor uses a 8K-byte, direct-mapped instruction cache to achieve 107
MIPS at 120 MHz. The cache is accessed by physical addresses, where each 16-byte line consists of an
address tag and a valid bit. The instruction cache also includes a bursting interface for 16-bit and 8-bit port
sizes to quickly fill cache lines.
1.2.5
Internal 128-KByte SRAM
The 128-KByte on-chip SRAM is available in two banks, SRAM0 (64K) and SRAM1 (64K). It provides
one clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code or
data segments to maximize performance. Memory in SRAM1 can be accessed under DMA.
1.2.6
SDRAM Controller
The SCF5250 SDRAM controller provides a glueless interface for one bank of SDRAM up to 32 MB
(256 Mbits). The controller supports a 16-bit data bus. A unique addressing scheme allows for increases
in system memory size without rerouting address lines and rewiring boards. The controller operates in
page mode, non-page mode, and burst-page mode and supports SDRAMS.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
3
1.2.7
System Interface
The SCF5250 provides a glueless interface to 16-bit port size SRAM, ROM, and peripheral devices with
independent programmable control of the assertion and negation of chip-select and write-enable signals.
The SCF5250 also supports bursting ROMs.
1.2.8
External Bus Interface
The bus interface controller transfers information between the ColdFire core or DMA and memory,
peripherals, or other devices on the external bus. The external bus interface provides 23 bits of address bus
space, a 16-bit data bus, Output Enable, and Read/Write signals. This interface implements an extended
synchronous protocol that supports bursting operations.
1.2.9
Serial Audio Interfaces
The SC5250 digital audio interface provides three serial Philips IIS/Sony EIAJ interfaces. One interface
is a 4-pin (1 bit clock, 1 word clock, 1 data in, 1 data out), the other two interfaces are 3-pin (1 bit clock,
1 word clock, 1 data in or out). The serial interfaces have no limit on minimum sampling frequency.
Maximum sampling frequency is determined by maximum frequency on bit clock input. This is 1/3 the
frequency of the internal system clock.
1.2.10 IEC958 Digital Audio Interfaces
The SCF5250 has one digital audio input interface, and one digital audio output interface. The single
output carries the consumer “c” channel.
1.2.11 Audio Bus
The audio interfaces connect to an internal bus that carries all audio data. Each receiver places its received
data on the audio bus and each transmitter takes data from the audio bus for transmission. Each transmitter
has a source select register.
In addition to the audio interfaces, there are six CPU accessible registers connected to the audio bus. Three
of these registers allow data reads from the audio bus and allow selection of the audio source. The other
three register provide a write path to the audio bus and can be selected by transmitters as the audio source.
Through these registers, the CPU has access to the audio samples for processing.
Audio can be routed from a receiver to a transmitter without the data being processed by the core so the
audio bus can be used as a digital audio data switch. The audio bus can also be used for audio format
conversion.
1.2.12 CD-ROM Encoder/Decoder
The SCF5250 is capable of processing CD-ROM sectors in hardware. Processing is compliant with
CD-ROM and CD-ROM XA standards.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
4
Freescale Semiconductor
The CD-ROM decoder performs following functions in hardware:
•
•
•
•
Sector sync recognition
Descrambling of sectors
Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors
Third-layer error correction is not performed
The CD-ROM encoder performs following functions in hardware:
•
•
•
•
Sector sync recognition
Scrambling of sectors
Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.
Third-layer error encoding needs to be done in software. This can use approximately 5–10 MHz of
performance for single-speed.
1.2.13 Dual UART Module
Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats
can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte
receive buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also
provides several error-detection and maskable-interrupt capabilities. Modem support includes
request-to-send (RTS) and clear-to-send (CTS) lines.
The system clock provides the clocking function from a programmable prescaler. You can select full
duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs
can interrupt the CPU on various normal or error-condition events.
1.2.14 Queued Serial Peripheral Interface QSPI
The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to
16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to
15 Mbits/second are possible at a CPU clock of 120 MHz. The QSPI supports master mode operation only.
1.2.15 Timer Module
The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer.
Timer0 has an external pin TOUT0, which can be used in Output Compare mode. This mode triggers an
external signal or interrupts the CPU when the timer reaches a set value, and can also generate waveforms
on TOUT0.
The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is
derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock (CPU clock
/ 2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
5
1.2.16 IDE and SmartMedia Interfaces
The SCF5250 system bus allows connection of an IDE hard disk drive or SmartMedia flash card with a
minimum of external hardware. The external hardware consists of bus buffers for address and data and are
intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the IDE
bus. The control signals for the buffers are generated in the SCF5250.
Low cost version SCF5250LPV100 and SCF5250LAG100 does not run production test for the
IDE/CF/SD/MMC interfaces. Freescale does not guarantee these interfaces will work on these two
devices.
1.2.17 Analog/Digital Converter (ADC)
The six channel ADC is a based on the Sigma-Delta concept with 12-bit resolution. Both the analogue
comparator and digital sections of the ADC are provided internally. An external integrator circuit
(resistor/capacitor) is required, which is driven by the ADC output. A software interrupt is provided when
the ADC measurement cycle is complete.
1.2.18 I2C Module
2
2
The two-wire I C bus interface, which is compliant with the Philips I C bus standard, is a bidirectional
2
serial bus that exchanges data between devices. The I C bus minimizes the interconnection between
devices in the end system and is best suited for applications that need occasional bursts of rapid
communication over short distances among several devices. Bus capacitance and the number of unique
addresses limit the maximum communication length and the number of devices that can be connected.
1.2.19 Chip-Selects
Up to four programmable chip-select outputs provide signals that enable glueless connection to external
memory and peripheral circuits. The base address, access permissions and automatic wait-state insertion
are programmable with configuration registers. These signals also interface to 16-bit ports.
CS0 is active after reset to provide boot-up from external FLASH/ROM.
1.2.20 GPIO Interface
A total of 60 General Purpose inputs and 57 General Purpose outputs are available. These are multiplexed
with various other signals. Seven of the GPIO inputs have edge sensitive interrupt capability.
1.2.21 Interrupt Controller
The interrupt controller provides user-programmable control of a total of 57 interrupts. There are 49
internal interrupt sources. In addition, there are 7 GPIOs where interrupts can be generated on the rising
or falling edge of the pin. All interrupts are autovectored and interrupt levels are programmable.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
6
Freescale Semiconductor
1.2.22 JTAG
To help with system diagnostics and manufacturing testing, the SCF5250 includes dedicated
user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability,
often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1A
standard. Freescale provides BSDL files for JTAG testing.
1.2.23 System Debug Interface
The ColdFire processor core debug interface supports real-time instruction trace and debug, plus
background-debug mode. A background-debug mode (BDM) interface provides system debug.
In real-time instruction trace, four status lines provide information on processor activity in real time (PST
pins). A four-bit wide debug data bus (DDATA) displays operand data and change-of-flow addresses,
which helps track the machine’s dynamic execution path.
1.2.24 Crystal and On-Chip PLL
Typically, an external 16.92 MHz or 33.86 MHz clock input is used for CD R/W applications, while an
11.2896 MHz clock is more practical for Portable CD player applications. However, the on-chip
programmable PLL, which generates the processor clock, allows the use of almost any low frequency
external clock (5-35 MHz).
Two clock outputs (MCLK1 and MCLK2) are provided for use as Audio Master Clock. The output
frequencies of both outputs are programmable to Fxtal, Fxtal/2, Fxtal/3, and Fxtal/4. The Fxtal/3 option is
only available when the 33.86 MHz crystal is connected.
The SCF5250 supports VCO operation of the oscillator by means of a 16-bit pulse density modulation
output. Using this mode, it is possible to lock the oscillator to the frequency of an incoming IEC958 or IIS
signal. The maximum trim depends on the type and design of the oscillator. Typically a trim of +/- 100 ppm
can be achieved with a crystal oscillator and over +/- 1000 ppm with an LC oscillator.
1.2.25 Boot ROM
The boot ROM on the SCF5250 serves to boot the CPU in designs which do not have external Flash
memory or ROM. Typically this occurs in systems which have a separate MCU to control the system,
and/or the SCF5250 is used as a stand-alone decoder.
The SCF5250 can be booted in one of three modes:
•
•
•
External ROM
Internal ROM Master mode – boots from I2C, SPI, or IDE
Internal ROM Slave mode – boots from I2C or UART
1.2.26 Voltage Regulator
The SCF5250 contains an on-chip linear regulator that generates 1.2V from a 3.3V input. The regulator is
self-contained and drives the 1.2V core voltage out on one pin that can be used to power the core supply
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
7
pins at the board level. In battery powered portable applications, it is recommended that an external dc-dc
converter be used to generate the 1.2V core voltage to minimize power consumption.
2 SCF5250 Block Diagram
Figure 1 illustrates the functional block diagram of the SCF5250 processor.
I2S Rx
x3
I2S Tx
x2
CD ROM
block encode
& decode
Flash
Media Int
IDE
Interface
12-bit
ADC
SPDIF
Tx
UART x2
DMAs /
Timers
SPDIF
Rx
QSPI
BDM
I2C x2
PLL
1.2V
Regulator
GPI/O
Boot
ROM
JTAG
128K
SRAM
8K
I-Cache
Oscillator
V2
ColdFire®
Core
System
Bus
Controller
SDRAM Ctr
&
Chip Selects
Figure 1. SCF5250 Block Diagram
3 Signal Descriptions
This section describes the SCF5250 processor’s input and output signals. The signal descriptions shown
in Table 2 are grouped according to relevant functionality.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
8
Freescale Semiconductor
Table 2. SCF5250 Signal Index
Mnemonic
Input/ Reset
Output State
Signal Name
Address
Function
A[24:1]
A[23]/GPO54
24 address lines, address line 23
multiplexed with GPO54 and address 24
is multiplexed with A20 (SDRAM access
only).
Out
X
Read-write control
Output enable
Data
R/W
Bus write enable - indicates if read or
write cycle in progress
Out
H
OE
Output enable for asynchronous
memories connected to chip selects
Out negated
In/Out Hi-Z
D[31:16]
Data bus used to transfer word data
Synchronous row address SDRAS/GPIO59
strobe
Row address strobe for external SDRAM. Out negated
Synchronous column
address strobe
SDCAS/GPIO39
Column address strobe for external
SDRAM
Out negated
SDRAM write enable
SDWE/GPIO38
Write enable for external SDRAM
Out negated
SDRAM upper byte
enable
SDUDQM/GPO53
Indicates during write cycle if high byte is
written
Out
Out
–
–
SDRAM lower byte enable SDLDQM/GPO52
Indicates during write cycle if low byte is
written
SDRAM chip selects
SDRAM clock enable
System clock
SD_CS0/GPIO60
BCLKE/GPIO63
BCLK/GPIO40
SDRAM chip select
SDRAM clock enable
SDRAM clock output
In/Out negated
Out
–
–
–
In/Out
ISA bus read strobe
IDE-DIOR/GPIO31
(CS2)
There is 1 ISA bus read strobe and 1 ISA In/Out
bus write strobe. They allow connection
of one independent ISA bus peripherals,
e.g. an IDE slave device.
ISA bus write strobe
ISA bus wait signal
Chip Selects[2:0]
IDE-DIOW/GPIO32
(CS2)
In/Out
–
–
IDE-IORDY/GPIO33
ISA bus wait line - available for both
busses
In/Out
CS0/CS4
CS1/QSPI_CS3/GPIO28
Enables peripherals at programmed
addresses.
Out negated
In/Out
CS[0] provides boot ROM selection
Buffer enable 1
Buffer enable 2
BUFENB1/GPIO29
BUFENB2/GPIO30
Two programmable buffer enables allow In/Out
–
–
seamless steering of external buffers to
In/Out
split data and address bus in sections.
Transfer acknowledge
Wake Up
TA/GPIO12
Transfer Acknowledge signal
Wake-up signal input
In/Out
In
–
–
–
WAKE_UP/GPIO21
Serial Clock Line
SCL0/SDATA1_BS1/GPIO41
SCL1/TXD1/GPIO10
Clock signal for Dual I2C module
operation
In/Out
Serial Data Line
Receive Data
SDA0/SDATA3/GPIO42
SDA1/RXD1/GPIO44
Serial data port for second I2C module
operation
In/Out
In
–
–
SDA1/RXD1/GPIO44
RXD0/GPIO46
Signal is receive serial data input for
DUART
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
9
Table 2. SCF5250 Signal Index (continued)
Mnemonic Function
SCL1/TXD1/GPIO10
Input/ Reset
Output State
Signal Name
Transmit Data
Signal is transmit serial data output for
DUART
Out
Out
In
–
–
–
–
–
TXD0/GPIO45
Request-To-Send
Clear-To-Send
Timer Output
DDATA3/RTS0/GPIO4
DDATA1/RTS1/SDATA2_BS2/GPIO2
DUART signals a ready to receive data
query
DDATA2/CTSO/GPIO3
Signals to DUART that data can be
DDATA0/CTS1/SDATA0_SDIO1/GPIO1 transmitted to peripheral
SDATAO1/TOUT0/GPIO18
Capable of output waveform or pulse
Out
In
generation
IEC958 inputs
EBUIN1/GPIO36
audio interfaces IEC958 inputs
EBUIN2/SCLK_OUT/GPIO13
EBUIN3/CMD_SDIO2/GPIO14
QSPI_CS0/EBUIN4/GPIO15
IEC958 outputs
Serial data in
Serial data out
Word clock
EBUOUT1/GPIO37
QSPI_CS1/EBUOUT2/GPIO16
audio interfaces IEC958 outputs
audio interfaces serial data inputs
audio interfaces serial data outputs
audio interfaces serial word clocks
Out
In
–
–
–
–
SDATAI1/GPIO17
SDATAI3/GPIO8
SDATAO1/TOUT0/GPIO18
SDATAO2/GPIO34
In/Out
Out
LRCK1/GPIO19
In/Out
LRCK2/GPIO23
LRCK3/GPIO43/AUDIO_CLOCK
Bit clock
SCLK1/GPIO20
SCLK2/GPIO22
SCLK3/GPIO35
audio interfaces serial bit clocks
In/Out
–
Serial input
Serial input
Subcode clock
EF/GPIO6
error flag serial in
In/Out
In/Out
In/Out
–
–
–
CFLG/GPIO5
C-flag serial in
RCK/QSPI_DIN/QSPI_DOUT/
GPIO26
audio interfaces subcode clock
Subcode sync
QSPI_DOUT/SFSY/GPIO27
QSPI_CLK/SUBR/GPIO25
XTRIM/GPIO0
audio interfaces subcode sync
audio interfaces subcode data
clock trim control
In/Out
In/Out
Out
–
–
–
–
Subcode data
Clock frequency trim
Audio clocks out
MCLK1/GPIO11
DAC output clocks
Out
QSPI_CS2/MCLK2/GPIO24
Audio clock in
LRCK3/GPIO43/AUDIO_CLOCK
Optional Audio clock Input
–
–
SCF5250 Data Sheet: Technical Data, Rev. 1.3
10
Freescale Semiconductor
Table 2. SCF5250 Signal Index (continued)
Input/ Reset
Output State
Signal Name
Memory Stick/
Mnemonic
Function
EBUIN3/CMD_SDIO2/GPIO14
Secure Digital command lane
Memory Stick interface 2 data I/O
In/Out
In/Out
In/Out
In/Out
In/Out
–
–
–
–
–
Secure Digital interface
EBUIN2/SCLK_OUT/GPIO13
Clock out for both Memory Stick
interfaces and for Secure Digital
DDATA0/CTS1/SDATA0_SDIO1/GPIO1 Secure Digital serial data bit 0
Memory Stick interface 1 data I/O
SCL0/SDATA1_BS1/GPIO41
Secure Digital serial data bit 1
Memory Stick interface 1 strobe
DDATA1/RTS1/SDATA2_BS2/GPIO2
Secure Digital serial data bit 2
Memory Stick interface 2 strobe
Reset output signal
SDA0/SDATA3/GPIO42
Secure Digital serial data bit 3
In/Out
In
–
–
ADC IN
ADIN0/GPI52
ADIN1/GPI53
ADIN2/GPI54
ADIN3/GPI55
ADIN4/GPI56
ADIN5/GPI57
Analog to Digital converter input signals
ADC OUT
ADREF
ADOUT/SCLK4/GPIO58
Analog to digital convertor output signal. In/Out
Connect to ADREF via integrator
network.
–
QSPI clock
QSPI_CLK/SUBR/GPIO25
QSPI clock signal
In/Out
In/Out
In/Out
–
–
–
QSPI data in
QSPI data out
RCK/QSPI_DIN/QSPI_DOUT/GPIO26 QSPI data input
RCK/QSPI_DIN/QSPI_DOUT/GPIO26 QSPI data out
QSPI_DOUT/SFSY/GPIO27
QSPI chip selects
QSPI_CS0/EBUIN4/GPIO15
QSPI_CS1/EBUOUT2/GPIO16
QSPI_CS2/MCLK2/GPIO24
CS1/QSPI_CS3/GPIO28
QSPI chip selects
In/Out
–
Crystal in
CRIN
Crystal input
In
Out
In
–
–
Crystal out
CROUT
RSTI
Crystal Out
Reset In
Processor Reset Input
TEST pins.
–
Freescale Test Mode
Linear regulator output
Linear regulator input
Linear regulator ground
High Impedance
Debug Data
TEST[2:0]
LINOUT
LININ
In
–
outputs 1.2 V to supply core
Input, typically I/O supply (3.3V)
–
Out
In
–
–
LINGND
HI-Z
–
–
Assertion Tri-states all output signal pins.
In
–
DDATA0/CTS1/SDATA0_SDIO1/GPIO1 Displays captured processor data and
In/Out
Hi-Z
DDATA1/RTS1/SDATA2_BS2/GPIO2
DDATA2/CTS0/GPIO3
break-point status.
DDATA3/RTS0/GPIO4
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
11
Table 2. SCF5250 Signal Index (continued)
Mnemonic Function
Input/ Reset
Output State
Signal Name
Processor Status
PST0/GPIO50
PST1/GPIO49
Indicates internal processor status.
In/Out
Hi-Z
PST2/INTMON2/GPIO48
PST3/INTMON1/GPIO47
Processor Clock
Test Clock
PSTCLK/GPIO51
TCK
processor clock output
Out
In
–
–
–
Clock signal for IEEE 1149.1A JTAG.
Test Reset/Development TRST/DSCLK
Serial Clock
Multiplexed signal that is asynchronous
reset for JTAG controller. Clock input for
debug module.
In
Test Mode Select/ Break TMS/BKPT
Point
Multiplexed signal that is test mode select
in JTAG mode and a hardware
break-point in debug mode.
In
–
Test Data Input /
Development Serial Input
TDI/DSI
Multiplexed serial input for the JTAG or
background debug module.
In
–
–
Test Data
Output/Development
Serial Output
TDO/DSO
Multiplexed serial output for the JTAG or
background debug module.
Out
3.1
GPIO
Many pins have an optional GPIO function.
•
•
General purpose input is always active, regardless of state of pin.
General purpose output or primary output is determined by the appropriate setting of the Pin
Multiplex Control Registers, GPIO-FUNCTION, GPIO1-FUNCTION and PIN-CONFIG.
•
At Power-on reset, all pins are set to their primary function.
3.2
SCF5250 Bus Signals
These signals provide the external bus interface to the SCF5250 processor.
3.2.1
Address Bus
•
The address bus provides the address of the byte or most significant byte of the word or longword
being transferred. The address lines also serve as the DRAM address pins, providing multiplexed
row and column address signals.
•
Bits 23 down to 1 and 24 of the address are available. A24 is intended to be used with 256 Mbit
DRAM’s. Signals are named:
— A[23:1]
— A20/24
SCF5250 Data Sheet: Technical Data, Rev. 1.3
12
Freescale Semiconductor
3.2.2
Read-Write Control
This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and
a high is a read cycle.
3.2.3
Output Enable
The OE signal is intended to be connected to the output enable of asynchronous memories connected to
chip selects. During bus read cycles, the ColdFire processor will drive OE low.
3.2.4
Data Bus
The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the SCF5250 on the
rising clock edge. The data bus uses a default configuration if none of the chip-selects or DRAM bank
match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or
operand size.
3.2.5
Transfer Acknowledge
The TA/GPIO12 pin is the transfer acknowledge signal.
3.3
SDRAM Controller Signals
The following SDRAM signals provide a glueless interface to external SDRAM. An SDRAM width of 16
bits is supported and can access as much as 32MB of memory. ADRAMs are not supported.
Table 3. SDRAM Controller Signals
SDRAM Signal
Description
Synchronous DRAM row address strobe The SDRAS/GPIO59 active low pin provides a seamless interface to the RAS input
on synchronous DRAM
Synchronous DRAM Column Address
Strobe
The SDCAS/GPIO39 active low pin provides a seamless interface to CAS input on
synchronous DRAM.
Synchronous DRAM Write
The SDWE/GPIO38 active-low pin is asserted to signify that a SDRAM write cycle
is underway. This pin outputs logic ‘1’ during read bus cycles.
Synchronous DRAM Chip Enable
The SD_CS0/GPIO60 active-low output signal is used during synchronous mode
to route directly to the chip select of a SDRAM device.
Synchronous DRAM UDQM and LQDM
signals
The DRAM byte enables UDMQ and LDQM are driven by the SDUDQM/GPO53
and SDLDQM/GPO52 byte enable outputs.
Synchronous DRAM clock
The DRAM clock is driven by the BCLK/GPIO40 signal
Synchronous DRAM Clock Enable
The BCLKE active high output signal is used during synchronous mode to route
directly to the SCKE signal of external SDRAMs. This signal provides the clock
enable to the SDRAM.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
13
3.4
Chip Selects
There are three chip select outputs on the SCF5250 device. CS0/CS4 and CS1/QSPI_CS3/GPIO28 and
CS2 which is associated with the IDE interface read and write strobes - IDE-DIOR and IDE-DIOW.
CS0 and CS4 are multiplexed. The SCF5250 has the option to boot from an internal Boot ROM.
The function of the CS0/CS4 pin is determined by the boot mode. When the device is booted from internal
ROM, the internal ROM is accessed with CS0 (required for boot) and the CS0/CS4 pin is driven by CS4.
When the device is booted from external ROM / Flash, the CS0/CS4 pin is driven by CS0 and the internal
ROM is disabled.
The active low chip selects can be used to access asynchronous memories. The interface is glueless.
3.5
ISA Bus
The SCF5250 supports an ISA bus. Using the ISA bus protocol, reads and writes for one ISA bus
peripheral is possible. IDE-DIOR/GPIO31 and IDE-DIOW/GPIO32 are the read and write strobe. The
peripheral can insert wait states by pulling IDE-IORDY/GPIO33.
CS2 is associated with the IDE-DIOR and IDE-DIOW.
3.6
Bus Buffer Signals
As the SCF5250 has a complicated slave bus, which allows SDRAM, asynchronous memories, and ISA
peripherals on the bus, it may become necessary to introduce a buffer on the bus in certain applications.
The SCF5250 has a glueless interface to steer these bus buffers with two bus buffer output signals
BUFENB1/GPIO29 and BUFENB2/GPIO30.
2
3.7
I C Module Signals
There are two I2C interfaces on this device as described in Table 4.
The I2C module acts as a two-wire, bidirectional serial interface between the SCF5250 processor and
peripherals with an I2C interface (e.g., LED controller, A-to-D converter, D-to-A converter). When
devices connected to the I2C bus drive the bus, they will either drive logic-0 or high-impedance. This can
be accomplished with an open-drain output.
2
Table 4. I C Module Signals
I2c Module Signal
Description
I2C Serial Clock The SCL0/SDATA1_BS1/GPIO41 and SCL1/TXD1/GPIO10 bidirectional signals are the clock signal for
first and second I2C module operation. The I2C module controls this signal when the bus is in master
mode; all I2C devices drive this signal to synchronize I2C timing.
Signals are multiplexed
I2C Serial Data The SDA0/SDATA3/GPIO42 and SDA1/RXD1/GPIO44 bidirectional signals are the data input/output for
the first and second serial I2C interface.
Signals are multiplexed
SCF5250 Data Sheet: Technical Data, Rev. 1.3
14
Freescale Semiconductor
3.8
Serial Module Signals
The signals described in Table 5 transfer serial data between the two UART modules and the external
peripherals.
Table 5. Serial Module Signals
Serial Module Signal
Description
Receive Data
The RXD0/GPIO46 and SDA1/RXD1/GPIO44 are the inputs on which serial data is received by the
DUART. Data is sampled on RxD[1:0] on the rising edge of the serial clock source, with the least
significant bit received first.
Transmit Data
The DUART transmits serial data on the TXD0/GPIO45 and SCL1/TXD1/GPIO10 output signals. Data
is transmitted on the falling edge of the serial clock source, with the least significant bit transmitted (LSB)
first. When no data is being transmitted or the transmitter is disabled, these two signals are held high.
TxD[1:0] are also held high in local loopback mode.
Request To Send
Clear To Send
The DDATA3/RTS0/GP104 and DDATA1/RTS1/SDATA2_BS2/GPIO2 request-to-send outputs indicate
to the peripheral device that the DUART is ready to send data and requires a clear-to-send signal to
initiate transfer.
Peripherals drive the DDATA2/CTS0/GPIO3 and DDATA0/CTS1/SDATA0_SDIO1/GPIO1 inputs to
indicate to the SCF5250 serial module that it can begin data transmission.
3.9
Timer Module Signals
Table 6 describes the Timer module signal which provides an external interface to Timer0.
Table 6. Timer Module Signals
Serial Module Signal
Description
Timer Output
The SDATAO1/TOUT0/GPIO18 programmable output pulse or toggle on various timer events.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
15
3.10 Serial Audio Interface Signals
Table 7 describes the signals that provide the external audio interface.
Table 7. Serial Audio Interface Signals
Serial Module Signal
Description
Serial Audio Bit Clock The SCLK1/GPIO20, SCLK2/GPIO22 and SCLK3/GPIO35,
multiplexed pins can serve as general purpose I/Os or serial audio bit clocks. As bit clocks, these
bidirectional pins can be programmed as outputs to drive their associated serial audio (IIS) bit clocks.
Alternately, these pins can be programmed as inputs when the serial audio bit clocks are driven
internally. The functionality is programmed within the Audio module. During reset, these pins are
configured as input serial audio bit clocks.
Serial Audio Word Clock The LRCK1/GPIO19, LRCK2/GPIO23 and LRCK3/GPIO43/AUDIO_CLOCK multiplexed pins can
serve as general purpose I/Os or serial audio word clocks. As word clocks, the bidirectional pins can
be programmed as inputs to drive their associated serial audio word clock. Alternately, these pins can
be programmed as outputs when the serial audio word clocks are derived internally. The functionality
is programmed within the Audio module. During reset, these pins are configured as input serial audio
word clocks.
LRCK3/GPIO43/AUDIO_CLOCK can be used as the external audio clock input. If the core clock
chosen to be non-audio specific.
Serial Audio Data In
The SDATAI1/GPIO17 and SDATAI3/GPIO8 multiplexed pins can serve as general purpose I/Os or
serial audio inputs. As serial audio inputs the data is sent to interfaces 1and 3 respectively. During
reset, the pins are configured as serial data inputs.
Serial Audio Data Out SDATO1/TOUT0/GPIO18 AND SDATAO2/GPIO34 multiplexed pins can serve as general purpose I/Os
or serial audio outputs. During reset, the pins are configured as serial data outputs.
Serial audio error flag The EF/GPIO6 multiplexed pin can serve as general purpose I/Os or error flag input. As error flag
input, this pin will input the error flag delivered by the CD-DSP. EF/GPIO6 is only relevant for serial
interface SDATAI1.
Serial audio CFLG
The CFLG/GPIO5 multiplexed pin can serve as general purpose I/O or CFLG input. As CFLG input,
the pin will input the CFLG flag delivered by the CD-DSP. CFLG/GPIO5 is only relevant for serial
interface SDATAI1.
3.11 Digital Audio Interface Signals
Table 8 describes the signals for the digital audio interface.
Table 8. Digital Audio Interface Signals
Serial Module Signal
Description
Digital Audio In
The EBUIN1/GPIO36, EBUIN2/SCLK_OUT/GPIO13, EBUIN3/CMD_SDIO2/GPIO14, and
QSPI_CS0/EBUIN4/GPIO15 multiplexed signals can serve as general purpose input or can be driven
by various digital audio (IEC958) input sources. Both functions are always active. Input chosen for
IEC958 receiver is programmed within the audio module. Input value on the 4 pins can always be read
from the appropriate GPIO register.
Digital Audio Out
The EBUOUT1/GPIO37 and QSPI_CS1/EBUOUT2/GPIO16 multiplexed pins can serve as general
purpose I/O or as digital audio (IEC958) output. EBUOUT1 is digital audio out for consumer mode,
EBUOUT2 is digital audio out for professional mode. During reset, the pin is configured as a digital audio
output.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
16
Freescale Semiconductor
3.12 Subcode Interface
There is a 3-line subcode interface on the SCF5250 processor. This 3-line subcode interface allows the
device to format and transmit subcode in EIAJ format to a CD channel encoder device. The three signals
are described in Table 9.
Table 9. Subcode Interface Signal
Signal name
Description
RCK/QSPI_DIN/QSPI_DOUT/GPIO26 Subcode clock input. When pin is used as subcode clock, this pin is driven by the CD
channel encoder.
QSPI_DOUT/SFSY/GPIO27
Subcode sync output
This signal is driven high if a subcode sync needs to be inserted in the EFM stream.
QSPI_CLK/SUBR/GPIO25
Subcode data output
This signal is a subcode data out pin.
3.13 Analog to Digital Converter (ADC)
The ADOUT signal on the ADOUT/SCLK4/GPIO58 pin provides the reference voltage in PWM format.
This output requires an external integrator circuit (resistor/capacitor) to convert it to a DC level to be input
to the ADREF pin.
The six AD inputs are each fed to their own comparator. The reference input to each (ADREF) is then
multiplexed as only one AD comparison can be made at any one time.
NOTE
To use the ADINx as General Purpose inputs (rather than there analogue function) it is
necessary to generate a fixed comparator voltage level of VDD/2. This can be
accomplished by a potential divider network connected to the ADREF pin. However in
portable applications where stand-by power consumption is important the current taken
by the divider network (in stand-by mode) could be excessive. Therefore it is possible to
generate a VDD/2 voltage by selecting SCLK4 output mode and feeding this clock signal
(which is 50% duty cycle) through an external integration circuit. This would generate a
voltage level equal to VDD/2 but would be disabled when stand-by mode was selected.
3.14 Secure Digital/Memory Stick Card Interface
The device has a versatile flash card interface that supports both Secure Digital and Memory Stick cards.
The interface can either support one Secure Digital or two Memory Stick cards. No mixing of card types
is possible. Table 10 gives the pin descriptions.
Table 10. Flash Memory Card Signals
Flash Memory Signal
Description
EBUIN2/SCLKOUT/GPIO13
Clock out for both Memory Stick interfaces and for Secure Digital
EBUIN3/CMD_SDIO2/GPIO14
Secure Digital command line
Memory Stick interface 2 data I/O
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
17
Table 10. Flash Memory Card Signals (continued)
Description
Flash Memory Signal
DDATAO/CTS1/SDATA0_SDIO1/GPIO1 Secure Digital serial data bit 0
Memory Stick interface 1 data I/O
SCL0/SDATA1_BS1/GPIO41
Secure Digital serial data bit 1
Memory Stick interface 1 strobe
DDATA1/RTS1/SDATA2_BS2/GPIO2 Secure Digital serial data bit 2
Memory Stick interface 2 strobe
Reset output signal
Selection between Reset function and SDATA2_BS2 is done by programming PLLCR
register.
SDA0/SDATA3/GPIO42
Secure Digital serial data bit 3
3.15 Queued Serial Peripheral Interface (QSPI)
The QSPI interface is a high-speed serial interface allowing transmit and receive of serial data. Pin
descriptions are given in Table 11.
Table 11. Queued Serial Peripheral Interface (QSPI) Signals
Serial Module Signal
Description
QSPICLK/SUBR/GPIO25
Multiplexed signal IIC interface clock or QSPI clock output Function select is done via
PLLCR register.
RCK/QSPIDIN/QSPI_DOUT/GPIO26 Multiplexed signal IIC interface data or QSPI data input. Function select is done via
PLLCR register.
RCK/QSPI_DIN/QSPI_DOUT/GPIO26
QSPI data output.
QSPI_DOUT/SFSY/GPIO27
QSPICS0/EBUIN4GPIO15
QSPICS1/EBUOUT2/GPIO16
4 different QSPI chip selects.
QSPICS2/MCLK2/GPIO24
CS1/QSPICS3/GPIO28
3.16 Crystal Trim
The XTRIM/GPIO0 output produces a pulse-density modulated phase/frequency difference signal to be
used after low-pass filtering to control varicap-voltage to control crystal oscillation frequency. This will
lock the crystal to the incoming digital audio signal.
3.17 Clock Out
The MCLK1/GPIO11 and QSPI_CS2/MCLK2/GPIO24 can serve as DAC clock outputs. When
programmed as DAC clock outputs, these signals are directly derived from the crystal oscillator or clock
Input (CRIN).
SCF5250 Data Sheet: Technical Data, Rev. 1.3
18
Freescale Semiconductor
3.18 Debug and Test Signals
These signals interface with external I/O to provide processor debug and status signals.
3.18.1 Test Mode
The TEST[2:0] inputs are used for various manufacturing and debug tests. For normal mode TEST [2:1]
should be ways be tied low. TEST0 should be set high for BDM debug mode and set low for JTAG mode.
3.18.2 High Impedance
The assertion of HI_Z will force all output drivers to a high-impedance state. The timing on HI_Z is
independent of the clock.
NOTE
JTAG operation will override the HI_Z pin.
3.18.3 Processor Clock Output
The internal PLL generates this PSTCLK/GPIO51 and output signal, and is the processor clock output that
is used as the timing reference for the Debug bus timing (DDATA[3:0] and PST[3:0]). The
PSTCLK/GPIO51 is at the same frequency as the core processor.
3.18.4 Debug Data
The debug data pins, DDATA0/CTS1/SDATA0_SDIO1/GPIO1, DDATA1/RTS1/SDATA2_BS2/GPIO2,
DDATA2/CTS0/GPIO3, and DDATA3/RTS0/GPIO4, are four bits wide. This nibble-wide bus displays
captured processor data and break-point status.
3.18.5 Processor Status
The processor status pins, PST0/GPIO50, PST1/GPIO49, PST2/INTMON/GPIO48, and
PST3/INTMON/GPIO47, indicate the SCF5250 processor status. During debug mode, the timing is
synchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer.
Table 12 shows the encodings of these signals.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
19
.
Table 12. Processor Status Signal Encodings
Definition
PST[3:0]
(HEX) (BINARY)
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
$F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Continue execution
Begin execution of an instruction
Reserved
Entry into user-mode
Begin execution of PULSE and WDDATA instructions
Begin execution of taken branch or Synch_PC1
Reserved
Begin execution of RTE instruction
Begin 1-byte data transfer on DDATA
Begin 2-byte data transfer on DDATA
Begin 3-byte data transfer on DDATA
Begin 4-byte data transfer on DDATA
Exception processing2
Emulator mode entry exception processing2
Processor is stopped, waiting for interrupt2
Processor is halted2
1
2
Rev. B enhancement.
These encodings are asserted for multiple cycles.
3.19 BDM/JTAG Signals
The SCF5250 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are multiplexed
with background debug pins.
3.20 Clock and Reset Signals
The clock and reset signals configure the SCF5250 processor and provide interface signals to the external
system.
3.20.1 Reset In
Asserting RSTI causes the SCF5250SCF5250 to enter reset exception processing. When RSTI is
recognized, the data bus is tri-stated.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
20
Freescale Semiconductor
3.20.2 Clock Input
SCF5250 includes an on-chip crystal oscillator. The crystal should be connected between CRIN and
CROUT. An externally generated clock signal can also be used and should be connected directly to the
CRIN pin.
3.21 Wake-Up Signal
To exit power down mode, apply a LOW level to the WAKE_UP/GPIO21 input pin.
3.22 On-Chip Linear Regulator
The SCF5250 includes an on-chip linear regulator. This regulator provides an 1.2 V output which is
intended to be used to power the SCF5250 core. Three pins are associated with this function.
LININ, LINOUT and LINGND. Typically LININ would be fed by the I/O (PAD) supply (3.3 V) with
separate filtering recommended to provide some isolation between the I/O and the core.
In portable solutions this linear regulator may not be efficient enough and in this case we would expect the
1.2 V supply to be generated externally, possibly by a highly efficient DC-DC convertor.
If not used leave pins not connected.
4 Electrical Characteristics
Table 14 through Table 19 provide the electrical characteristics for the SCF5250 processor. The remaining
figures and tables in this section provide the timing diagrams and the timing parameters for the SCF5250
processor.
Table 13. Quick Reference for Electrical Characteristics
For
See
Maximum Ratings
Table 14 on page 22
Operating Temperature Table 15 on page 22
Recommended
Operating Supply
Voltages
Table 16 on page 22
Linear Regulator
Operating Specification
Table 17 on page 23
Table 18 on page 23
Table 19 on page 24
DC Electrical
Specifications
Operating Parameters
for ADC DC Electrical
Characteristics
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
21
Table 14. Maximum Ratings
Symbol
Rating
Supply Core Voltage
Value
Units
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vin
-0.5 to +2.5
+1.32
V
V
Maximum Core Operating Voltage
Minimum Core Operating Voltage
Supply I/O Voltage
+1.08
V
-0.5 to +4.6
+3.6
V
Maximum I/O Operating Voltage
Minimum I/O Operating Voltage
Input Voltage
V
+3.0
V
-0.5 to +6.0
-65 to150
V
Storage Temperature Range
Tstg
oC
Table 15 provides the recommended operating temperatures for the SCF5250 processor.
Table 15. Operating Temperature
Characteristic
Symbol
Value
Units
Maximum Operating Ambient Temperature
Minimum Operating Ambient Temperature
TAmax
TAmin
851
-40
οC
oC
1
This published maximum operating ambient temperature should be used only as a system design guideline. All device operating
parameters are guaranteed only when the junction temperature does not exceed 105°C.
Table 16 provides the recommended operating supply voltages for the SCF5250 processor.
Table 16. Recommended Operating Supply Voltages
Pin Name
CORE-VDD
Min
Typ
Max
1.08V
–
1.2V
gnd
3.3v
gnd
3.3v
gnd
3.3v
gnd
1.2V
gnd
1.2v
gnd
3.3V
1.32V
–
CORE-VSS
PAD-VDD
3.0V
–
3.6V
–
PAD-VSS
ADVDD
3.0V
–
3.6V
–
ADGND
OSCPAD-VDD
OSCPAD-GND
PLLCORE1VDD
PLLCORE1GND
PLLCORE2VDD
PLLCORE2GND
LIN
3.0V
–
3.6V
–
1.08V
–
1.32V
–
1.08V
–
1.32V
–
3.0v
3.6V
SCF5250 Data Sheet: Technical Data, Rev. 1.3
22
Freescale Semiconductor
Table 17 provides the linear regulator operating specifications for the SCF5250 processor.
1
Table 17. Linear Regulator Operating Specification
Characteristic
Symbol
Min
Typ
Max
Input Voltage
Vin
Vout
Iout
Pd
3.0V
1.14V
–
3.3V
1.2V
100mA
–
3.6
1.26V
150mA
436uW
60mV
–
Output Voltage (LINOUT)
Output Current
Power Dissipation
–
Load Regulation (10% Iout ≥ 90% Iout)
Power Supply Rejection
–
40mV
–
50mV
40dB
PSRR
1
A pmos regulator is employed as a current source in this Linear regulator, so a 10µF capacitor (ESR 0 ... 5 Ohm) is needed on the output pin
(LINOUT) to integrate the current. Typically this will require the use of a Tantalum type capacitor.
Table 18 provides the DC electrical specifications.
Table 18. DC Electrical Specifications (I/O Vcc = 3.3 Vdc + 0.3 Vdc)
Characteristic
Symbol
Min
Max
Units
Operation Voltage Range for I/O
Input High Voltage
Vcc
VIH
VIL
Iin
3.0
2
3.6
5.5
0.8
±1
V
V
Input Low Voltage
-0.3
–
V
Input Leakage Current @ 0.0 V /3.3 V During Normal Operation
µµA
µµA
Hi-Impedance (Three-State) Leakage Current
@ 0.0 V/3.3 V During Normal Operation
ITSI
–
±1
Output High Voltage IOH = 8mA1, 4mA2, 2mA3
Output Low Voltage IOL = 8mA1, 4mA2, 2mA3
Schmitt Trigger Low to High Threshold Point6
Schmitt Trigger High to Low Threshold Point6
VOH
VOL
VT+
VT-
2.4
–
–
V
V
0.4
–
1.47
–
V
.95
50
V
Load Capacitance (DATA[31:16], SCLK[4:1], SCLKOUT, EBUOUT[2:1],
LRCK[3:1], SDATAO[2:1], CFLG, EF, DDATA[3:0], PST[3:0], PSTCLK,
IDE-DIOR, IDE-DIOW, IORDY)
CL
–
pF
Load Capacitance (ADDR[24:9], BCLK)
CL
CL
–
–
40
30
pF
pF
Load Capacitance (BCLKE, SDCAS, SDRAS, SDLDQM, SD_CS0, SDUDQM,
SDWE, BUFENB[2:1])
Load Capacitance (SDA0, SDA1, SCL0, SCL1, CMD_SDIO2, SDATA2_BS2,
SDATA1_BS1, SDATA0_SDIO1, CS0/CS4, CS1, OE, R/W, TA, TXD[1:0], XTRIM,
TDO/DSO, RCK, SFSY, SUBR, SDATA3, TOUT0, QSPID_OUT, QSPICS[3:0],
GP[6:5])
CL
–
20
pF
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
23
Table 18. DC Electrical Specifications (I/O Vcc = 3.3 Vdc + 0.3 Vdc) (continued)
Characteristic
Capacitance5, Vin = 0 V, f = 1 MHz
DATA[31:16], ADDR[24:9], PSTCLK, BCLK
Symbol
Min
Max
Units
CIN
–
6
pF
SCL, SDA, PST[3:0], DDATA[3:0], TDSO, SDRAS, SDCAS, SDWE, SD_CS0, SDLDQM, SDUDQM, R/W
TOUT0, RTS[1:0], TXD[1:0], SCLK[4:1]
BKPT/TMS, DSI/TDI, DSCLK/TRST
Capacitance C is periodically sampled rather than 100% tested.
IN
SCLK[4:1], SCL0, SCL1, SDA0, SDA1, CRIN, RSTI
Table 19 provides the operating parameters for the ADC DC electrical characteristics.
Table 19. Operating Parameters for ADC DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Units
Operation Voltage Range for ADC
Common Mode Rejection
ADVDD
CMR
3
0
–
–
3.6
ADVDD–1.1
ADVDD–1.1
–
V
v
Reference Voltage (external)
Input offset voltage
ADREF
Voffset
Vhyst
0
–
v
–
10
0.78
–
mV
mV
V
Input Hysteresis (ADINx = ADVDD/2)
ADC Input Linear Operating Range
0.73
0
0.85
ADINx
ADVDD–1.1
Figure 2 and Table 20 provide the clock timing diagram and timing parameters.
CRIN
C5
PSTCLK
C6
C6
C7
BCLK
C8
C8
Figure 2. Clock Timing Definition
SCF5250 Data Sheet: Technical Data, Rev. 1.3
24
Freescale Semiconductor
NOTE
The signals shown in Figure 2 are in relation to the clock. No relationship
between signals is implied or intended.
Table 20. Clock Timing Specification
Num
Characteristic
Min
Max
Units
–
CRIN Frequency1
5.00
7.1
40
33.86
–
MHz
ns
C5
C6
C7
C8
PSTCLK cycle time
PSTCLK duty cycle
BCLK cycle time
BCLK duty cycle
60
–
%
14.2
45
ns
55
%
1
There are only three choices for the valid Audio frequencies 11.29 MHz, 16.93 MHz, or 33.86 MHz; no other
values are allowed. The System Clock is derived from one of these crystals via an internal PLL.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
25
Figure 3 and Figure 4 provide the input and output AC timing definition diagrams and Table 21 and
Table 22 provide the input and output AC timing parameters.
Figure 3. Input/Output Timing Definition-I
SCF5250 Data Sheet: Technical Data, Rev. 1.3
26
Freescale Semiconductor
B3
B4
BCLK
INPUTS
B13
B14
BCLK
OUTPUTS
H1
H2
HIZ
OUTPUTS
Figure 4. Input/Output AC Timing Definition-III
Table 21. Input AC Timing Specification
Num
Characteristic
Min
Max
Units
B11,2
B21
Signal Valid to BCLK Rising (setup)
BCLK Rising to signal Invalid (hold)
BCLK to Input High Impedance
3
2
–
–
–
5
ns
ns
B31
BCLK cycle
1
2
Inputs (rising): DATA[31:16]
AC timing specs assume 40pF load capacitance on BCLK and 50pF load capacitance on output pins. If this value is different,
the input and output timing specifications would need to be adjusted to match the clock load.
Table 22. Output AC Timing Specification
Num
Characteristic1
BCLK (8mA) Rising to signal Valid
Min
Max
Units
B102
B112
B103
B113
B124
–
3.5
–
10
–
ns
ns
ns
ns
ns
BCLK (8mA) Rising to signal Invalid (hold)
BCLK (4mA) Rising to signal Valid
11
–
BCLK (4mA) Rising to signal Invalid (hold)
BCLK to High Impedance (Three-State)
4
–
14
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
27
Table 22. Output AC Timing Specification (continued)
Num
Characteristic1
Min
Max
Units
H1
H2
HIZ to High Impedance
HIZ to Low Impedance
–
–
tbd
tbd
ns
ns
1
AC timing specs assume 40pF load capacitance on BCLK and a 50pF load capacitance on output pins. If this value is different,
the input and output timing specifications would need to be adjusted to match the clock load.
2
3
4
Outputs (8mA): DATA[31:16], ADDR[25,23:9]
Outputs (4mA): SDRAS, SDCAS, SDWE, SD_CS0, SDUDQM, SDLDQM, BCLKE
High Impedance (Three-State): DATA[31:16]
Figure 5 and Table 23 provide the timing diagram and timing parameters for the Debug AC.
PSTCLK
D4
D3
DSCLK
D4
D3
D1
DSI
PST[3:0]
DDATA[3:0]
DSO
D2
Figure 5. Debug AC Timing Definition Diagram
1
Table 23. Debug AC Timing Specification
Num
Characteristic
Min
Max
Units
D1
D2
PSTCLK to signal Valid (Output valid)
PSTCLK to signal Invalid (Output hold)
Signal Valid to PSTCLK (Input setup)
PSTCLK to signal Invalid (Input hold)
–
1.8
3
6
–
–
–
ns
ns
ns
ns
D32
D4
5
1
2
AC timing specs assume 50pF load capacitance on PSTCLK and output pins. If this value is different, the input and
output timing specifications would need to be adjusted to match the clock load.
DSCLK and DSI are internally synchronized. This setup time must be met only if recognition on a particular clock is
required.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
28
Freescale Semiconductor
Figure 6 and Table 24 provide the timing diagram and timing parameters for the Timer module.
BCLK
T6
T2
T3
T1
TIN
TIN
T7
TOUT
T4
T5
Figure 6. Timer Module AC Timing Definition Diagram
Table 24. Timer Module AC Timing Specification
Num
Characteristic
Min
Max
Units
T1
T2
T3
T4
T5
T6
T7
TIN Cycle time
3T
6
–
–
bus clocks
TIN Valid to BCLK (input setup)
BCLK to TIN Invalid (input hold)
BCLK to TOUT Valid (output valid)
BCLK to TOUT Invalid (output hold)
TIN Pulse Width
ns
ns
0
–
–
10
–
ns
tbd
1T
1T
ns
–
bus clocks
bus clocks
TOUT Pulse Width
–
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
29
Figure 7 and Table 25 provide the timing diagram and timing parameters for the UART module.
BCLK
U1
RXD
U2
U3
CTS
U4
U5
TXD
U6
U7
RTS
U8
Figure 7. UART Module AC Timing Definition Diagram
Table 25. UART Module AC Timing Specifications
Num
Characteristic
Min
Max
Units
U1
U2
U3
U4
U5
U6
U7
U8
RXD Valid to BCLK (input setup)
BCLK to RXD Invalid (input hold)
CTS Valid to BCLK (input setup)
BCLK to CTS Invalid (input hold)
BCLK to TXD Valid (output valid)
BCLK to TXD Invalid (output hold)
BCLK to RTS Valid (output valid)
BCLK to RTS Invalid (output hold)
6
0
6
0
–
3
–
3
–
–
ns
ns
ns
ns
ns
ns
ns
ns
–
–
tbd
–
tbd
–
SCF5250 Data Sheet: Technical Data, Rev. 1.3
30
Freescale Semiconductor
Figure 8 provides the I2C-bus input and output timing diagram and Table 26 and Table 27 provide the
I2C-bus input and output timing parameters.
M2
M6
M5
SCL
SDA
M3
M1
M4
M7
M8
M9
Figure 8. I2C-Bus Input/Output Timing Definition Diagram
Table 26. I2C-Bus Input Timing Specifications Between SCL and SDA
Num
Characteristic
Min
Max
Units
M1
M2
M3
M4
M5
M6
M7
M8
M9
Start Condition Hold Time
Clock Low Period
2
8
–
0
–
4
0
2
2
–
–
1
–
1
–
–
–
–
bus clocks
bus clocks
mSec
SCL/SDA Rise Time (VIL= 0.5 V to VIH = 2.4 V)
Data Hold Time
ns
SCL/SDA Fall Time (VIH= 2.4 V to VIL = 0.5 V)
Clock High time
ms
bus clocks
ns
Data Setup Time
Start Condition Setup Time (for repeated start condition only)
Stop Condition Setup Time
bus clocks
bus clocks
Table 27. I2C-Bus Output Timing Specifications Between SCL and SDA
Num
Characteristic
Min
Max
Units
M11
M21
M32
Start Condition Hold Time
Clock Low Period
6
–
–
bus clocks
bus clocks
mSec
10
SCL/SDA Rise Time (VIL= 0.5 V to VIH = 2.4 V)
note 2
note 2
M41
M53
Data Hold Time
7
–
–
3
bus clocks
ns
SCL/SDA Fall Time (VIH= 2.4 V to VIL = 0.5 V)
M61
M71
M81
M91
Clock High time
10
2
–
–
–
–
bus clocks
bus clocks
bus clocks
bus clocks
Data Setup Time
Start Condition Setup Time (for repeated start condition only)
Stop Condition Setup Time
20
10
1
Output numbers are dependent on the value programmed into the MFDR; an MFDR programmed with the maximum frequency (MFDR =
0x20) will result in minimum output timings as shown. The MBUS interface is designed to scale the actual data transition time to move it to
the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the MFDR; however,
numbers given are the minimum values.
2
3
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time required for SCL or SDA to
reach a high level depends on external signal capacitance and pull-up resistor values.
Specified at a nominal 20 pF load.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
31
Figure 9 provides the I2C-bus and system clock timing diagram and Table 28 provides the I2C-bus output
timing parameters.
M10
BCLK
SCL, SDA IN
M11
M12
SCL, SDA OUT
SCL, SDA OUT
M13
Figure 9. I2C and System Clock Timing Relationship
Table 28. I2C Output Bus Timings
96 MHz
Num
Characteristic
Units
Min
Max
M101
M11
SCL, SDA Valid to BCLK (input setup)
BCLK to SCL, SDA Invalid (input hold)
BCLK to SCL, SDA Low (output valid)
BCLK to SCL, SDA Invalid (output hold)
2
4.5
–
–
–
ns
ns
ns
ns
M122
M133
10
–
3
1
2
SCL and SDA are internally synchronized. This setup time must be met only if recognition on a particular clock is required.
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL
or SDA are driven low by the processor. The time required for SCL or SDA to reach a high level depends on external signal capacitance and
pull-up resistor values.
3
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL
or SDA are actively being driven or held low by the processor.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
32
Freescale Semiconductor
Figure 10 provides the general-purpose parallel port timing diagram and Table 29 provides the timing
parameters.
BCLK
P1
GPIO IN
P2
P3
GPIO OUT
P4
Figure 10. General-Purpose I/O Port AC Timing Definition Diagram
Table 29. General-Purpose I/O Port AC Timing Specifications
Num
Characteristic
Min
Max
Units
P1
P2
P3
P4
GPIO Valid to BCLK (input setup)
BCLK to GPIO Invalid (input hold)
BCLK to GPIO Valid (output valid)
BCLK to GPIO Invalid (output hold)
6
0
–
1
–
–
ns
ns
ns
ns
tbd
–
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
33
Figure 11 provides the IEEE 1149.1 JTAG timing diagram and Table 30 provides the timing parameters.
J1
J3A
J2A
J2B
TCK
J3B
J4
TDI, TMS
J5
J6
BOUNDARY
SCAN DATA
INPUT
J7
TRST
TDO
J8
J9
J10
J11
BOUNDARY
SCAN DATA
OUTPUT
J12
Figure 11. JTAG AC Timing Diagram
Table 30. JTAG AC Timing Specifications
Characteristic
Num
Min
Max
Units
–
TCK Frequency of Operation
0
100
25
25
–
10
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
J1
TCK Cycle Time
J2a
J2b
J3a
J3b
J4
TCK Clock Pulse High Width
–
TCK Clock Pulse Low Width
–
TCK Fall Time (VIH=2.4 V to VIL=0.5 V)
TCK Rise Time (VIL=0.5 v to VIH=2.4 V)
TDI, TMS to TCK rising (Input Setup)
TCK rising to TDI, TMS Invalid (Hold)
Boundary Scan Data Valid to TCK (Setup)
TCK to Boundary Scan Data Invalid to rising edge (Hold)
TRST Pulse Width (asynchronous to clock edges)
TCK falling to TDO Valid (signal from driven or three-state)
TCK falling to TDO High Impedance
5
–
5
8
–
J5
10
tbd
tbd
12
–
–
J6
–
J7
–
J8
–
J9
15
15
J10
–
SCF5250 Data Sheet: Technical Data, Rev. 1.3
34
Freescale Semiconductor
Table 30. JTAG AC Timing Specifications (continued)
Characteristic
Num
Min
Max
Units
J11
J12
TCK falling to Boundary Scan Data Valid (signal from driven or three-state)
TCK falling to Boundary Scan. Data High Impedance
–
–
tbd
tbd
ns
ns
Figure 12 provides the SCLK input, SDATA output timing diagram for the IIS module and Table 31
provides the timing parameters.
SCLK (INPUT)
SDATAO1, 2 (OUTPUT)
TU
TD
Figure 12. SCLK Input, SDATA Output Timing Diagram
Table 31. SCLK Input, SDATA Output Timing Specifications
Num
Characteristic
Min
Max
Units
TU
TD
SCLK fall to SDATAO rise
SCLK fall to SDATAO fall
–
–
25
25
ns
ns
Figure 13 provides the SCLK output, SDATA output timing diagram for the IIS module and Table 32
provides the timing parameters.
SCLK (OUTPUT)
SDATAO1, 2 (OUTPUT)
TU
TD
Figure 13. SCLK Output, SDATA Output Timing Diagram
Table 32. SCLK Output, SDATA Output Timing Specifications
Num
Characteristic
Min
Max
Units
TU
TD
SCLK fall to SDATAO rise
SCLK fall to SDATAO fall
–
–
3
3
ns
ns
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
35
Figure 14 provides the SCLK input/output, SDATA input timing diagram and Table 33 provides the timing
parameters.
SCLK
(INPUT OR OUTPUT)
SDATA1, 3, 4 (INPUT)
TH
TSU
Figure 14. SCLK Input/Output, SDATA Input Timing Diagram
Table 33. SCLK Input/Output, SDATA Input Timing Specifications
Num
Characteristic
Min
Max
Units
TSU
TH
SDATAI IN to SCLKn
SCLK rise to SDATAI
-5
3
–
–
ns
ns
5 Pin-Out and Package Information
Visit the URL [http://www.freescale.com/coldfire] and choose the documentation library to obtain
information on the mechanical characteristics of the SCF5250 integrated microprocessor. Thermal
characteristics are not available at this time.
The SCF5250 is available in a 144 pin QFP and a 196 pin MAPBGA package. Use Table 34 to find the
information desired.
Table 34. Section Quick Reference
For Chip
Package
See
Pin assignments
Table 35 on page 37
Figure 15 on page 42
Figure 16 on page 43
Figure 17 on page 44
144 pin QFP
Package drawings
Pin assignments
Package drawings
Ball map
Table 36 on page 45
Figure 18 on page 52
Figure 19 on page 53
196 MAPBGA
Figure 20 on page 54
5.1
144 QFP Pin Assignments
The SCF5250 can be assembled in 144-pin QFP package. Table 35 provides the pin assignments for the
package.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
36
Freescale Semiconductor
Table 35. 144 QFP Pin Assignments
144 QFP
Pin Number
Pin State
After Reset
Name
Type
Description
01
02
DATA16
I/O
I/O
Data
X
A23/GPO54
SDRAM address / static adr
Out (requires pull up /down for
boot-up selection)
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PAD-VDD
A22
–
O
O
O
O
O
–
–
–
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
–
Out
Out
Out
Out
Out
–
A21
A20/A24
A19
A18
PAD-GND
A17
O
O
O
O
O
–
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
–
Out
Out
Out
Out
Out
–
A16
A15
A14
A13
PAD-VDD
A12
O
O
–
SDRAM address / static adr
SDRAM address / static adr
–
Out
Out
–
A11
CORE-VDD
CORE-GND
A10
–
–
–
O
O
O
O
O
O
–
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
PAD-GND
Out
Out
Out
Out
Out
Out
–
A9
A8
A7
A6
A5
PAD-GND
A4
O
O
O
O
O
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
Static chip select 0 / static chip select 4
Out
Out
Out
Out
Out
A3
A2
A1
CS0/CS4
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
37
Table 35. 144 QFP Pin Assignments (continued)
144 QFP
Pin Number
Pin State
After Reset
Name
Type
Description
Bus write enable
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
RW
O
–
Out
OSC PAD VDD
CRIN
–
Crystal / external clock input
Crystal clock output
OSC_PAD_GND
–
–
I
X
CROUT
O
X
OSC PAD GND
PLL CORE1 VDD
PLL CORE2 VDD
PLL CORE2 GND
PLL CORE1 GND
OE
–
–
–
–
–
–
–
–
–
–
–
–
–
O
Output Enable
IDE DIOW
Out
IDE-DIOW/GPIO32
IDE-IORDY/GPIO33
IDE-DIOR/GPIO31
BUFENB2/GPIO30
BUFENB1/GPIO29
TA/GPIO12
I/O
I/O
I/O
I/O
I/O
I/O
Out / HIGH
In / LOW
Out / HIGH
Out / HIGH
Out / HIGH
IDE interface IORDY
IDE interface DIOR
External buffer 2 enable
External buffer 1 enable
Transfer acknowledge
In (requires pull-up for normal
operation)
48
49
50
WAKE_UP/GPIO21
I/O
I/O
I/O
Wake-up input
In (requires pull-up for normal
operation)
EBUIN2/SCLK_OUT/
GPIO13
Audio interfaces EBU in 2 /
FlashMedia Clock
In / LOW
EBUIN3/CMD_SDIO2/
GPIO14
Audio interfaces EBU in 3 /
FlashMedia Command interface
In / LOW
51
52
53
54
55
56
PAD VDD
EBUIN1/GPIO36
–
–
–
I/O
I/O
I/O
I/O
I/O
Audio interfaces EBU in 1
Audio interfaces EBU out 1
Audio interfaces X-tal trim
Chip select 1/ QSPI Chip Select 3
In / LOW
EBUOUT1/GPIO37
XTRIM/GPIO0
Out / LOW
Out / clock out
Out / HIGH
Out / LOW
CS1/QSPI_CS3/GPIO28
RCK/
QSPI_DIN/QSPI_DOUT/
GPIO26
Subcode RCK interface /
QSPI Data In / Data Out
57
58
QSPI_CLK/SUBR/GPIO25
I/O
I/O
QSPI clock pin / subcode interface
Out / LOW
Out / LOW
QSPI_DOUT/SFSY/
GPIO27
QSPI Data Output / subcode
interface SFSY
SCF5250 Data Sheet: Technical Data, Rev. 1.3
38
Freescale Semiconductor
Table 35. 144 QFP Pin Assignments (continued)
144 QFP
Pin Number
Pin State
After Reset
Name
Type
Description
59
60
QSPI_CS1/EBUOUT2/
GPIO16
I/O
QSPI Chip select 1 output /
audio interface EBU output 2
Out / LOW
Out / LOW
QSPI_CS0/EBUIN4/
GPIO15
I/O
QSPI chip select 0 /
audio interface EBUIN 4
61
62
63
64
PAD GND
–
–
–
SCLK1/GPIO20
LRCK1/GPIO19
I/O
I/O
I/O
Audio interfaces serial clock 1
Audio interfaces word clock 1
In / LOW
In / LOW
Out / LOW
SDATAO1/TOUT0/
GPIO18
Audio interfaces serial data
output 1 / Timer output 0
65
66
67
68
SDATAI1/GPIO17
CFLG/GPIO5
EF/GPIO6
I
Audio interfaces serial data in 1
CFLG input
In / LOW
In / LOW
In / LOW
Out / LOW
I/O
I/O
I/O
Error flag input
QSPI_CS2/MCLK2/
GPIO24
QSPI Chip Select output 2 /
audio master clock output 2
69
70
71
72
73
74
75
76
77
78
79
SDATAI3/GPIO8
ADIN0/GPI52
ADIN1/GPI53
ADIN2/GPI54
ADVDD
I/O
A
Audio interfaces serial data input 3
In / LOW
AD input 0
AD input 1
AD input 2
–
In only
A
In only
A
In only
–
–
ADGND
–
–
–
In only
ADIN3/GPI55
ADIN4/GPI56
ADIN5/GPI57
ADREF
A
AD input 3
AD input 4
AD input 5
ADC reference input
A
In only
A
In only
A
In
ADOUT/SCLK4/
GPIO58
I/O
AD output / SCLK4 (for GPI function in
low power applications)
Out / clock output
80
LRCK3/GPIO43/
AUDIO_CLOCK
I/O
Audio interface LRCK3 /
Audio master clock input
In / LOW
81
82
SCLK3/GPIO35
I/O
I/O
Audio interface SCLK3
In / LOW
SCL0/SDATA1_BS1/
GPIO41
I2C0 clock line / FlashMedia
Data interface
Out / LOW
83
84
SDA0/SDATA3/GPIO42
I/O
I/O
I2C0 data / FlashMedia data interface
Hi-Z
DDATA0/CTS1/
SDATA0_SDIO1/GPIO1
Debug / UART1 CTS / FlashMedia data
interface
Out / HIGH
85
DDATA1/RTS1/
SDATA2_BS2/GPIO2
I/O
Debug / UART1 RTS / FlashMedia data
interface
Out / HIGH
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
39
Table 35. 144 QFP Pin Assignments (continued)
144 QFP
Pin Number
Pin State
After Reset
Name
Type
Description
Debug / UART0 CTS
86
87
88
DDATA2/CTS0/GPIO3
DDATA3/RTS0/GPIO4
SCL1/TXD1/GPIO10
I/O
I/O
I/O
Out / HIGH
Out / HIGH
Out / LOW
Debug / UART0 RTS
I2C1 clock line / second UART transmit
data output
89
90
91
CORE VDD
CORE GND
–
–
–
–
–
–
SDA1/RXD1/GPIO44
I/O
I2C1 data line / second UART receive
data input
Hi-Z
92
93
94
95
PAD VDD
–
–
–
TXD0/GPIO45
RXD0/GPIO46
I/O
I/O
I/O
First UART transmit data output
First UART receive data input
Debug / interrupt monitor output 1
Out / HIGH
In / LOW
Out / HIGH
PST3/INTMON1/
GPIO47
96
PST2/INTMON2/GPIO48
PAD GND
I/O
–
Debug / interrupt monitor output 2
Out / HIGH
97
–
–
98
PST1/GPIO49
PST0/GPIO50
PSTCLK/GPIO51
TDO/DSO
I/O
I/O
I/O
O
I
Debug
Out / HIGH
99
Debug
Out / HIGH
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
Debug
Out / clock output
JTAG/debug
BDM
TDI/DSI
JTAG/debug
BDM
TCK
I
JTAG
BDM
TMS/BKPT
TRST/DSCLK
RSTI
I
JTAG/debug
BDM
I
JTAG/Debug
BDM
I
Reset
X
SCLK2/GPIO22
LRCK2/GPIO23
LINOUT
I/O
I/O
A
Audio interfaces serial clock 2
Audio interfaces EBU out 1
Linear regulator output
Linear regulator input
Linear regulator ground
Audio interfaces serial data output 2
Audio master clock output 1
JTAG
In / LOW
In /LOW
X
LININ
A
X
LINGND
–
X
SDATAO2/GPIO34
MCLK1/GPIO11
HI-Z
I/O
I/O
I
Out / LOW
Out / clock output
X
X
TEST2
I
Test
SCF5250 Data Sheet: Technical Data, Rev. 1.3
40
Freescale Semiconductor
Table 35. 144 QFP Pin Assignments (continued)
144 QFP
Pin Number
Pin State
After Reset
Name
Type
Description
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TEST1
TEST0
I
Test
Test
X
I
X
SDWE/GPIO38
SDCAS/GPIO39
PAD VDD
SDRAS/GPIO59
SD_CS0/GPIO60
SDLDQM/GPO52
SDUDQM/GPO53
BCLKE/GPIO63
BCLK/GPIO40
DATA31
I/O
I/O
–
SDRAM write enable
Out / HIGH
SDRAM CAS
Out / HIGH
–
–
I/O
I/O
O
SDRAM RAS
Out / HIGH
SDRAM chip select out 0
Out / HIGH
SDRAM LDQM
Out / HIGH
O
SDRAM UDQM
Out / HIGH
I/O
I/O
I/O
I/O
–
SDRAM clock enable output
Out / HIGH
SDRAM clock output
Out / HIGH
Data
Data
–
X
X
–
DATA30
PAD GND
DATA29
I/O
I/O
I/O
I/O
I/O
–
Data
Data
Data
Data
Data
–
X
X
X
X
X
–
DATA28
DATA27
DATA26
DATA25
PAD-VDD
DATA24
I/O
I/O
I/O
I/O
I/O
–
Data
Data
Data
Data
Data
–
X
X
X
X
X
–
DATA23
DATA22
DATA21
DATA20
PAD GND
DATA19
I/O
I/O
I/O
Data
Data
Data
X
X
X
DATA18
DATA17
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
41
5.2
144 QFP Package
The SCF5250 is available in a 144-pin QFP package. For the 144 QFP package drawings, refer to Figure
15 on page 42, Figure 16 on page 43, and Figure 17 on page 44.
Figure 15. 144 QFP Package (1 of 3)
SCF5250 Data Sheet: Technical Data, Rev. 1.3
42
Freescale Semiconductor
Figure 16. 144 QFP Package (2 of 3)
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
43
Figure 17. 144 QFP Package (3 of 3)
SCF5250 Data Sheet: Technical Data, Rev. 1.3
44
Freescale Semiconductor
5.3
196 MAPBGA Pin Assignments
The SCF5250 can be assembled in a 196-pin MAPBGA package. Table 36 lists the 196 MAPBGA pin
assignments.
Table 36. 196 MAPBGA Pin Assignments
MAPBGA
Pin
Pin State
After Reset
Name
Type
Description
B1
D3
DATA16
I/O
I/O
Data
X
A23_GPO54
SDRAM address / static adr
Out (requires pull
up/down for
boot-up selection
P_VDD
C1
PST_VDD
A22
PST_VDD
O
O
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
Out
Out
D2
A21
E3
A20_A24
I/O
Out (requires pull
up/down for
boot-up selection
D1
E2
A19
A18
O
O
SDRAM address / static adr
SDRAM address / static adr
PST_GND
Out
Out
P_GND
F3
PST_GND
A17
O
O
O
O
O
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
PAD_VDD
Out
Out
Out
Out
Out
E1
A16
F2
A15
F1
A14
G3
A13
P_VDD
G2
PAD_VDD
A12
O
O
SDRAM address / static adr
SDRAM address / static adr
CORE_VDD
Out
Out
G1
A11
CORE_VDD
C_GND
H2
CORE_VDD
CORE_VSS
A10
CORE_VSS
Out
Out
Out
Out
Out
O
O
O
O
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
J1
A9
H3
A8
K1
A7
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
45
Table 36. 196 MAPBGA Pin Assignments (continued)
MAPBGA
Pin
Pin State
After Reset
Name
Type
Description
J2
L1
A6
A5
O
O
SDRAM address / static adr
SDRAM address / static adr
PAD_GND
Out
Out
P_GND
J3
PAD_GND
A4
O
O
O
O
O
O
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
SDRAM address / static adr
Static chip select 0
Bus write enable
Out
Out
Out
Out
Out
Out
K2
A3
L2
A2
M1
K3
A1
CS0
L3
RWB
J5
OSCPAD_VDD
CRIN
OSCPAD_VDD
M2
N1
J6
Crystal / external clock input
Crystal clock output
OSCPAD_GND
X
X
CROUT
OSCPAD_GND
PLLCORE_VDD
PLLCORE_VDD
PLLCORE_VDD
PLLCORE_GND
PLLCORE_GND
PLLCORE_GND
OE
K5
PLLCORE_VDD
K5
PLLCORE_VDD
K5
PLLCORE_VDD
K6
PLLCORE_GND
K6
PLLCORE_GND
K6
PLLCORE_GND
M3
M4
M5
N3
M6
P2
O
Output enable
Out
IDEDIOW_GP32
IDEIORDY_GP33
IDEDIOR_GP31
BUFENB2_GP30
BUFENB1_GP29
TA_GP12
I/O
I/O
I/O
I/O
I/O
I/O
IDE DIOW
Out / High
Out / Low
Out / High
Out / High
Out / High
IDE interface IORDY
IDE interface DIOR
External Buffer 2 enable
External Buffer 1 enable
Transfer acknowledge
N4
In (requires
pull-up for normal
operation)
SCF5250 Data Sheet: Technical Data, Rev. 1.3
46
Freescale Semiconductor
Table 36. 196 MAPBGA Pin Assignments (continued)
MAPBGA
Pin
Pin State
Name
Type
Description
Wake-up input
After Reset
N5
WAKEUP_GP21
I/O
In (requires
pull-up for normal
operation)
P3
P4
EBUIN2_SCLKOUT_GP1
3
I/O
I/O
Audio interfaces EBUIN2 /
FlashMedia Clock
In / Low
EBUIN3_CMDSDIO2_GP
14
Audio interfaces EBUIN3 /
FlashMedia Clock
In / Low
P_VDD
N6
PAD_VDD
EBUIN1_GP36
I/O
I/O
I/O
I/O
I/O
I/O
PAD_VDD
Audio interfaces EBUIN1
Audio interfaces EBUOUT1
Audio interfaces X-tal trim
QSPI Chip select 3
In / Low
P5
EBUOUT1_GP37
XTRIM_GP0
Out / Low
Out / clock out
Out / High
M7
P6
QSPICS3_CS1_GP28
N7
RCK_QSPIDIN_QSPIDO
UT_GP26
Subcode RCK interface / QSPI Data Out / Low
In / Data out
P7
P8
QSPICLK_SUBR_GP25
QSPIDOUT_SFSY_GP27
I/O
I/O
QSPI clockpin / subcode interface
Out / Low
Out / Low
QSPI Data Output / subcode
interface SFSY
M8
N8
QSPICS1_EBUOUT2_GP
16
I/O
I/O
QSPI Chip select 1 output / audio
interface EBU output 2
Out / Low
Out / Low
QSPICS0_EBUIN4_GP15
QSPI Chip select 0 output / audio
interface EBUIN4
P_GND
P9
PAD_GND
SCLK1_GP20
I/O
I/O
I/O
I/O
PAD_GND
Audio interfaces serial clock 1
Audio interfaces word clock 1
In / Low
In / Low
M9
LRCK1_GP19
N9
SDATAO1_TOUT1_GP18
Audio interfaces serial data output 1 Out / Low
/ Timer output 1
P10
N10
M10
P11
SDATAI1_GP17
CFLG_GP5
I/O
I/O
I/O
I/O
Audio interfaces serial data input 1 In / Low
CFLG input
In / Low
In / Low
Out / Low
EF_GP6
Error flag input
QSPICS2_MCLK2_GP24
QSPI Chip select output 2 / audio
master clock output 2
N11
SDATAI3_GP8
I/O
Audio interfaces serial data input 3 In / Low
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
47
Table 36. 196 MAPBGA Pin Assignments (continued)
MAPBGA
Pin
Pin State
After Reset
Name
Type
Description
M11
P12
P13
N12
M13
M12
L12
K12
N13
N14
ADIN0_GPI52
ADIN1_GPI53
ADIN2_GPI54
AD_VDD
A
A
A
AD input 0
AD input 1
AD input 2
AD_VDD
In only
In only
In only
AD_GND
AD_GND
AD input 3
AD input 4
AD input 5
ADIN3_GPI55
ADIN4_GPI56
ADIN5_GPI57
ADREF
A
A
In only
In only
In only
In
A
A
ADC reference input
ADOUT_SCLK4_GP58
I/O
AD output / SCLK4 (for GPI function Out / clock output
in low power applications
L13
M14
J12
LRCK3_GP43
SCLK3_GP35
I/O
I/O
I/O
Audio interface LRCK3
Audio interface SCLK3
In
In
SCL_SDATA1BS1_GP41
I2C clock line / FlashMedia data
interface
In / Low
L14
J13
K14
SDA_SDATA3_GP42
I/O
I/O
I/O
I2C data line / FlashMedia data
interface
Hi-Z
DDATA0_CTS2B_SDATA
0SDIO1_GP1
Debug / UART2 CTS / FlashMedia Out / High
data interface
DDATA1_RTS2B_SDATA
2BS2_GP2
Debug / UART2 RTS / FlashMedia Out / High
data interface
H12
J14
H13
DDATA2_CTS1B_GP3
DDATA3_RTS1B_GP4
SCL2_TXD2_GP10
I/O
I/O
I/O
Debug / UART1 CTS
Debug / UART1 RTS
Out / High
Out / High
Out / Low
I2C2 clock line / second UART
transmit data output
CORE_VDD
C_GND
H14
CORE_VDD
CORE_GND
I/O
I/O
I/O
CORE_VDD
CORE_GND
SDA2_RXD2_GP44
I2C2 data line / second UART2
receive data input
Hi-Z
P_VDD
G14
PAD_VDD
I/O
I/O
PAD_VDD
TXD1_GP45
UART1 transmit data output
Out / High
SCF5250 Data Sheet: Technical Data, Rev. 1.3
48
Freescale Semiconductor
Table 36. 196 MAPBGA Pin Assignments (continued)
MAPBGA
Pin
Pin State
After Reset
Name
Type
Description
G13
G12
F12
RXD1_GP46
PST3_INTMON1_GP47
PST2_INTMON2_GP48
PAD_GND
PST1_GP49
PST0_GP50
PSTCLK_GP51
TDO_DSO
TDI_DSI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
UART1 receive data input
Debug / interrupt monitor output 1
Debug / interrupt monitor output 2
PAD_GND
Out / Low
Out / High
Out / High
P_GND
F14
Debug
Out / High
F13
Debug
Out / High
E14
E13
D13
E12
C13
D12
D14
C14
B14
C11
C11
B12
B12
P_GND
C10
A12
---
Debug
Out / clock output
JTAG / Debug
BDM
BDM
BDM
BDM
BDM
X
I
JTAG / Debug
TCK
I
JTAG
TMS_BKPT
TRST_DSCLK
RSTI
I
JTAG / Debug
I
JTAG / Debug
I
Reset
SCLK2_GP22
LRCK2_GP23
LINOUT
I/O
I/O
A
Audio interfaces serial clock 2
Audio interfaces word clock 2
Linear regulator output
Linear regulator output
Linear regulator input
Linear regulator input
Linear regulator ground
In / Low
In / Low
X
LINOUT
A
X
LININ
A
X
LININ
A
X
LIN_GND
X
SDATAO2_GP34
MCLK1_GP11
VBGT
I/O
I/O
Audio interfaces serial data output 2 Out / Low
Audio master clock output 1
Out / clock output
B11
B10
C9
HIZ_B
I
I
I
I
JTAG
Test
Test
Test
X
X
X
X
TEST2
TEST1
A11
TEST0
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
49
Table 36. 196 MAPBGA Pin Assignments (continued)
MAPBGA
Pin
Pin State
Name
Type
Description
SDRAM write enable
After Reset
B9
A10
P_VDD
C8
SDWE_GP38
SDCAS_GP39
PAD_VDD
SDRAS_GP59
SDCS0_GP60
SDLDQM_GPO52
SDUDQM_GPO53
BCLKE_GPO63
BCLK_GP40
DATA31
I/O
I/O
Out / High
Out / High
Out / High
Out / High
Out / High
Out / High
Out / High
Out / High
Out / High
X
SDRA CAS
PAD_VDD
I/O
I/O
O
SDRAM RAS
A9
SDRAM chip select out 0
B8
SDRAM LDQM
A8
O
SDRAM UDQM
A7
O
SDRAM clock enable output
A6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SDRAM clock output
Data
B7
A5
DATA30
Data
X
P_GND
C7
PAD_GND
DATA29
PAD_GND
Data
X
X
X
X
X
B6
DATA28
Data
A4
DATA27
Data
B5
DATA26
Data
C6
DATA25
Data
P_VDD
B4
PAD_VDD
DATA24
PAD_VDD
Data
X
X
X
X
X
B3
DATA23
Data
C5
DATA22
Data
A2
DATA21
Data
B2
DATA20
Data
P_GND
C4
PAD_GND
DATA19
PAD_GND
Data
X
X
X
C3
DATA18
Data
C2
DATA17
Data
SCF5250 Data Sheet: Technical Data, Rev. 1.3
50
Freescale Semiconductor
Table 36. 196 MAPBGA Pin Assignments (continued)
MAPBGA
Pin
Pin State
After Reset
Name
Type
Description
A1
A14
P1
BGA1_NC_A1
BGA1_NC_A14
BGA1_NC_P1
BGA1_NC_P14
NC
NC
NC
NC
P14
5.4
196 MAPBGA Package and Ball Map
The SCF5250 is available in a 196-pin MAPBGA package. For the 196 MAPBGA package drawings,
refer to Figure 18 on page 52 and Figure 19 on page 53.
For the 196 MAPBGA ball map, refer to Figure 20 on page 54.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
51
Figure 18. 196 MAPBGA Package (1 of 2)
SCF5250 Data Sheet: Technical Data, Rev. 1.3
52
Freescale Semiconductor
Figure 19. 196 MAPBGA Package (2 of 2)
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
53
Figure 20. 196 MAPBGA Ball Map
SCF5250 Data Sheet: Technical Data, Rev. 1.3
54
Freescale Semiconductor
6 Product Documentation
This section contains this document’s revision history and the reference documents that are available to
provide more information about the SCF5250 processor.
6.1
Reference Documents
The following list contains the documents that provide a complete description of the SCF5250 and are
required to design properly with the part. The documents are available at: http://www.freescale.com.
ColdFire Family Programmer’s Reference Manual (order number CFPRM)
Version 2/2M ColdFire Core Processor User’s Manual (order number ColdFire2UM)
Version 2/2M ColdFire Core Processor User’s Manual Addendum (order number ColdFire2UMAD)
SCF5250 User’s Manual (order number SCF5250UM)
6.2
Revision History
Table 37 list the revision history for this data sheet.
Table 37. Revision History
Description
Added 144 LQFP package drawings.
Revision
1.3
Added 196 MAPBGA package drawings, pin assignments, and ball map.
1.2
Added SCF5250DAG120 and SCF5250EAG120 parts in Table 1.
Content has been reorganized, however there are no other content removal
or additions.
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
55
How to Reach Us:
Information in this document is provided solely to enable system and software implementers to use
Freescale Semiconductor products. There are no express or implied copyright licenses granted
hereunder to design or fabricate any integrated circuits or integrated circuits based on the information
in this document.
Home Page:
www.freescale.com
E-mail:
Freescale Semiconductor reserves the right to make changes without further notice to any products
herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters
that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating parameters,
including “Typicals”, must be validated for each customer application by customer’s technical experts.
Freescale Semiconductor does not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized for use as components
in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer purchase or use
Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was
negligent regarding the design or manufacture of the part.
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other
product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2006. All rights reserved.
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-521-6274 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Document Number: SCF5250EC
Rev. 1.3
07/2006
相关型号:
SCF5740
0.270” 4-Character, 5x7 Dot Matrix Serial Input Dot Addressable Intelligent Display
INFINEON
SCF5742
0.270” 4-Character, 5x7 Dot Matrix Serial Input Dot Addressable Intelligent Display
INFINEON
SCF5744
0.270” 4-Character, 5x7 Dot Matrix Serial Input Dot Addressable Intelligent Display
INFINEON
©2020 ICPDF网 联系我们和版权申明