SN54LS75 [FREESCALE]
4-BIT D LATCH LOW POWER SCHOTTKY; 4位D锁存器低功率肖特基
| 型号： | SN54LS75 |
| 厂家： | 
Freescale |
| 描述： | 4-BIT D LATCH LOW POWER SCHOTTKY |
| 文件： | 总4页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS75
SN54/74LS77
4-BIT D LATCH
The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem-
porary storage for binary information between processing units and input/out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH.
The SN54/74LS75 features complementary Q and Q output from a 4-bit
latch and is available in the 16-pin packages. For higher component density
applications the SN54/74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
4-BIT D LATCH
LOW POWER SCHOTTKY
CONNECTION DIAGRAMS DIP (TOP VIEW)
J SUFFIX
CERAMIC
CASE 620-09
Q
Q
Q
E
GND
12
Q
Q
Q
3
0
1
1
0–1
13
2
2
16
15
14
11
10
9
16
16
1
SN54/74LS75
N SUFFIX
PLASTIC
CASE 648-08
1
2
3
4
5
6
8
7
1
Q
D
D
E
V
D
D
Q
3
0
0
1
2–3
CC
2
3
Q
Q
E
GND
11
NC
10
Q
Q
3
0
1
0–1
12
2
D SUFFIX
SOIC
CASE 751B-03
14
13
9
8
16
1
SN54/74LS77
J SUFFIX
CERAMIC
CASE 632-08
1
2
3
4
5
6
7
NC
14
D
D
E
V
D
D
3
0
1
2–3
CC
2
1
PIN NAMES
LOADING (Note a)
HIGH
LOW
N SUFFIX
PLASTIC
CASE 646-06
D –D
Data Inputs
0.5 U.L.
2.0 U.L.
2.0 U.L.
10 U.L.
10 U.L.
0.25 U.L.
1.0 U.L.
1.0 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
1
4
E
E
Q –Q
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
0–1
2–3
1
14
1
4
4
Q –Q
Complimentary Latch Outputs (Note b)
1
NOTES:
a) 1 Unit Load (U.L.) = 40 µA HIGH.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
D SUFFIX
SOIC
CASE 751A-02
14
1
TRUTH TABLE
(Each latch)
ORDERING INFORMATION
NOTES:
= bit time before enable
t
n
t
n+1
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
t
n
negative-going transition
= bit time after enable
D
H
L
Q
H
L
t
n+1
negative-going transition
FAST AND LS TTL DATA
5-1
SN54/74LS75
LOGIC SYMBOLS
SN54/74LS75
SN54/74LS77
2
3
6
7
1
2
5
6
D
D
D
D
D
D
D
D
0
1
2
3
0
1
2
3
V
= PIN 4
E
E
E
E
CC
13
4
12
3
0–1
2–3
0–1
2–3
V
= PIN 5
CC
GND = PIN 12
GND = PIN 11
NC = PIN 7, 10
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
3
3
0
0
1
1
2
2
3
0
1
2
14
13
9
8
16
1
15 14 10 11
9
8
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
IH
2.0
V
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
= MAX, V = V
IN
CC
OH
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
= V or V
IL
MIN,
CC
54, 74
74
0.25
0.35
0.4
0.5
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
V
OL
Output LOW Voltage
IH
V
per Truth Table
OL
D Input
E Input
20
80
µA
V
= MAX, V = 2.7 V
IN
CC
CC
I
I
Input HIGH Current
Input LOW Current
IH
D Input
E Input
0.1
0.4
mA
mA
V
= MAX, V = 7.0 V
IN
D Input
E Input
–0.4
–1.6
V
CC
= MAX, V = 0.4 V
IN
IL
I
I
Short Circuit Current (Note 1)
Power Supply Current
–20
–100
12
mA
mA
V
V
= MAX
= MAX
OS
CC
CC
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V
= 5.0 V)
CC
A
Limits
Typ
Symbol
Parameter
Min
Max
Unit
Test Conditions
t
t
15
9.0
27
17
PLH
PHL
Propagation Delay, Data to Q
ns
t
t
12
7.0
20
15
PLH
PHL
Propagation Delay, Data to Q
ns
ns
ns
V
C
= 5.0 V
CC
= 15 pF
L
t
t
15
14
27
25
PLH
PHL
Propagation Delay, Enable to Q
Propagation Delay, Enable to Q
t
t
16
7.0
30
15
PLH
PHL
FAST AND LS TTL DATA
5-2
SN54/74LS77
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
IH
2.0
V
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
= MAX, V = V
IN
CC
OH
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
= V or V
IL
MIN,
CC
54, 74
74
0.25
0.35
0.4
0.5
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
V
OL
Output LOW Voltage
IH
V
per Truth Table
OL
D Input
E Input
20
80
µA
V
= MAX, V = 2.7 V
IN
CC
CC
I
I
Input HIGH Current
Input LOW Current
IH
D Input
E Input
0.1
0.4
mA
mA
V
= MAX, V = 7.0 V
IN
D Input
E Input
–0.4
–1.6
V
CC
= MAX, V = 0.4 V
IN
IL
I
I
Short Circuit Current (Note 1)
Power Supply Current
–20
–100
13
mA
mA
V
V
= MAX
= MAX
OS
CC
CC
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V
= 5.0 V)
CC
A
Limits
Typ
Min
Max
Symbol
Parameter
Unit
Test Conditions
t
t
11
9.0
19
17
PLH
PHL
Propagation Delay, Data to Q
ns
V
C
= 5.0 V
CC
= 15 pF
L
t
t
10
10
18
18
PLH
PHL
Propagation Delay, Enable to Q
ns
FAST AND LS TTL DATA
5-3
SN54/74LS75 SN54/74LS77
LOGIC DIAGRAM
DATA
Q (SN54/74LS75 ONLY)
Q
ENABLE
TO OTHER LATCH
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
AC SETUP REQUIREMENTS (T = 25°C, V
= 5.0 V)
CC
A
Limits
Typ
Min
Max
Symbol
Parameter
Enable Pulse Width High
Setup Time
Unit
Test Conditions
t
t
t
20
20
0
ns
ns
ns
W
V
CC
= 5.0 V
s
Hold Time
h
AC WAVEFORMS
1.3 V
1.3 V
D
E
t
t
s
h
1.3 V
PLH
1.3 V
1.3 V
t
t
t
1.3 V
1.3 V
t
PLH
1.3 V
1.3 V
PHL
Q
Q
t
t
PHL
t
PLH
PHL
t
PHL
PLH
DEFINITION OF TERMS
SETUP TIME (t ) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the
s
clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (t ) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be
h
maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may
be released prior to the clock transition from HIGH-to-LOW and still be recognized.
FAST AND LS TTL DATA
5-4
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