SPC5642AF2MVZ3 [FREESCALE]
Qorivva MPC5642A Microcontroller;
| 型号： | SPC5642AF2MVZ3 |
| 厂家： | 
Freescale |
| 描述： | Qorivva MPC5642A Microcontroller PC 微控制器 外围集成电路 |
| 文件： | 总120页 (文件大小：1167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5642A
Rev. 3.1, 06/2012
MPC5642A
Qorivva MPC5642A
Microcontroller Data Sheet
208 MAPBGA
(17 x 17 mm)
176 LQFP
(24 × 24 mm)
324 TEPBGA
(23 × 23 mm)
• 150 MHz e200z4 Power Architecture core
– Variable length instruction encoding (VLE)
– Superscalar architecture with 2 execution units
– Up to 2 integer or floating point instructions per cycle
– Up to 4 multiply and accumulate operations per cycle
• Memory organization
– 1 reaction module (6 channels with 3 outputs per
channel)
• 2 enhanced queued analog-to-digital converters (eQADCs)
– Forty 12-bit input channels (multiplexed on 2 ADCs);
expandable to 56 channels with external multiplexers
– 6 command queues
– 2 MB on-chip flash memory with ECC and
read-while-write (RWW)
– 128 KB on-chip SRAM with standby functionality (32
KB) and ECC
– Trigger and DMA support
– 688 ns minimum conversion time
• On-chip CAN/SCI Bootstrap loader with Boot Assist
Module (BAM)
– 8 KB instruction cache (with line locking), configurable
as 2- or 4-way
• Nexus: Class 3+ for core; Class 1 for eTPU
• JTAG (5-pin)
– 14 + 3 KB eTPU code and data RAM
– 4 4 crossbar switch (XBAR)
– 24-entry MMU
• Development Trigger Semaphore (DTS)
– EVTO pin for communication with external tool
• Clock generation
• Fail Safe Protection
– On-chip 4–40 MHz main oscillator
– On-chip FMPLL (frequency-modulated phase-locked
loop)
– 16-entry Memory Protection Unit (MPU)
– CRC unit with 3 submodules
– Junction temperature sensor
• Interrupt
• Up to 112 general purpose I/O lines
– Individually programmable as input, output or special
function
– Programmable threshold (hysteresis)
• Power reduction modes: slow, stop, and standby
• Flexible supply scheme
– Configurable interrupt controller (INTC) with
non-maskable interrupt (NMI)
– 64-channel eDMA
• Serial channels
– 3 eSCI modules
– 3 DSPI modules (2 of which support downstream Micro
Second Channel [MSC])
– 5 V single supply with external ballast
– Multiple external supply: 5 V, 3.3 V, and 1.2 V
– 3 FlexCAN modules with 64 message buffers each
– 1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or
single channel, 128 message objects, ECC
• 1 eMIOS
– 24 unified channels
• 1 eTPU2 (second generation eTPU)
—32 standard channels
© Freescale Semiconductor, Inc., 2009, 2010, 2012. All rights reserved.
Table of Contents
1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.5 Signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.5.1 e200z4 core. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . .10
1.5.3 Enhanced direct memory access (eDMA). . . . .10
1.5.4 Interrupt controller (INTC) . . . . . . . . . . . . . . . . .11
1.5.5 Memory protection unit (MPU). . . . . . . . . . . . . .11
1.5.6 Frequency-modulated phase-locked loop
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.1 Parameter classification. . . . . . . . . . . . . . . . . . . . . . . . 55
3.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.1 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4 EMI (electromagnetic interference) characteristics . . . 61
3.5 Electrostatic discharge (ESD) characteristics . . . . . . . 62
3.6 Power management control (PMC) and power on
reset (POR) electrical specifications . . . . . . . . . . . . . . 62
3.6.1 Regulator example . . . . . . . . . . . . . . . . . . . . . . 65
3.6.2 Recommended power transistors. . . . . . . . . . . 66
3.7 Power up/down sequencing. . . . . . . . . . . . . . . . . . . . . 66
3.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . 67
3.9 I/O pad current specifications . . . . . . . . . . . . . . . . . . . 72
3.9.1 I/O pad VRC33 current specifications . . . . . . . . 73
3.9.2 LVDS pad specifications. . . . . . . . . . . . . . . . . . 74
3.10 Oscillator and PLLMRFM electrical characteristics . . . 75
3.11 Temperature sensor electrical characteristics . . . . . . . 77
3.12 eQADC electrical characteristics. . . . . . . . . . . . . . . . . 77
3.13 Configuring SRAM wait states. . . . . . . . . . . . . . . . . . . 79
3.14 Platform flash controller electrical characteristics . . . . 80
3.15 Flash memory electrical characteristics . . . . . . . . . . . 80
3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.16.1 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 82
3.17 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.17.1 Reset and configuration pin timing. . . . . . . . . . 86
3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 86
3.17.3 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.17.4 Calibration bus interface timing . . . . . . . . . . . . 95
3.17.5 External interrupt timing (IRQ pin) . . . . . . . . . . 99
3.17.6 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.17.7 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.17.8 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.17.9 eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . 107
3.17.10FlexCAN system clock source. . . . . . . . . . . . 108
Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 109
4.1.1 176 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.1.2 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . 112
4.1.3 324 TEPBGA . . . . . . . . . . . . . . . . . . . . . . . . . 114
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 117
(FMPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5.7 System integration unit (SIU). . . . . . . . . . . . . . .12
1.5.8 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.9 Static random access memory (SRAM) . . . . . .14
1.5.10 Boot assist module (BAM). . . . . . . . . . . . . . . . .14
1.5.11 Enhanced modular input/output system
(eMIOS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.5.12 Second generation enhanced time processing
unit (eTPU2) . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.13 Reaction module (REACM) . . . . . . . . . . . . . . . .16
1.5.14 Enhanced queued analog-to-digital converter
(eQADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.5.15 Deserial serial peripheral interface (DSPI) . . . .18
1.5.16 Enhanced serial communications interface
(eSCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.5.17 Controller area network (FlexCAN) . . . . . . . . . .19
1.5.18 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.19 System timers . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.20 Software watchdog timer (SWT) . . . . . . . . . . . .21
1.5.21 Cyclic redundancy check (CRC) module. . . . . .21
1.5.22 Error correction status module (ECSM). . . . . . .22
1.5.23 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .22
1.5.24 Calibration bus interface . . . . . . . . . . . . . . . . . .22
1.5.25 Power management controller (PMC) . . . . . . . .22
1.5.26 Nexus port controller (NPC) . . . . . . . . . . . . . . .23
1.5.27 JTAG controller (JTAGC) . . . . . . . . . . . . . . . . . .23
1.5.28 Development trigger semaphore (DTS). . . . . . .23
Pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . .23
2.1 176 LQFP pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.2 208 MAP BGA ballmap. . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 324 TEPBGA ballmap. . . . . . . . . . . . . . . . . . . . . . . . . .26
2.4 Signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4
2
5
6
MPC5642A Microcontroller Data Sheet, Rev. 3.1
2
Freescale Semiconductor
Introduction
1
Introduction
1.1
Document overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5642A series of
microcontroller units (MCUs). It also describes the device features and highlights important electrical and physical
characteristics. For functional characteristics, refer to the device reference manual.
1.2
Description
This microcontroller is a 32-bit system-on-chip (SoC) device intended for use in mid-range engine control and automotive
transmission control applications.
It is compatible with devices in Freescale’s MPC5600 family and offers performance and capabilities beyond the MPC5632M
devices.
®
The microcontroller’s e200z4 host processor core is built on the Power Architecture technology and designed specifically for
embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal
processing (DSP).
The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM
and a 2 MB internal flash memory.
For development, the device includes a calibration bus that is accessible only when using the Freescale VertiCal Calibration
System.
1.3
Device feature summary
Table 1 summarizes the MPC5642A features and compares them to those of the MPC5644A.
Table 1. MPC5642A device feature summary
Feature
MPC5642A
MPC5644A
Process
Core
90 nm
e200z4
SIMD
Yes
VLE
Yes
Cache
8 KB instruction
Non-Maskable Interrupt (NMI)
NMI and Critical Interrupt
24-entry
MMU
MPU
16-entry
Crossbar switch
Core performance
Windowing software watchdog
Core Nexus
4 4
5 4
0–150 MHz
Yes
Class 3+
SRAM
128 KB
2 MB
192 KB
4 MB
Flash
Flash fetch accelerator
4 128-bit
4 256-bit
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
3
Introduction
Table 1. MPC5642A device feature summary (continued)
Feature
MPC5642A
MPC5644A
External bus
None
16-bit (incl. 32-bit muxed)
Calibration bus
DMA
16-bit (incl. 32-bit muxed)
64 channels
DMA Nexus
Serial
None
3
eSCI_A
eSCI_B
eSCI_C
CAN
Yes (MSC uplink)
Yes (MSC uplink)
Yes
3
CAN_A
CAN_B
CAN_C
SPI
64 message buffers
64 message buffers
64 message buffers
3
Micro Second Channel (MSC) bus downlink
Yes
DSPI_A
DSPI_B
DSPI_C
DSPI_D
No
Yes (with LVDS)
Yes (with LVDS)
Yes
FlexRay
Yes
System timers
5 PIT channels
4 STM channels
1 Software Watchdog
eMIOS
eTPU
24 channels
32-channel eTPU2
Code memory
14 KB
Data memory
Reaction module
Interrupt controller
ADC
3 KB
6 channels
485 channels1
40 channels
ADC_0
Yes
Yes
Yes
Yes
2
ADC_1
Temperature sensor
Variable gain amplifier
Decimation filter
Sensor diagnostics
Yes
MPC5642A Microcontroller Data Sheet, Rev. 3.1
4
Freescale Semiconductor
Introduction
Table 1. MPC5642A device feature summary (continued)
Feature
MPC5642A
MPC5644A
CRC
Yes
Yes
FMPLL
VRC
Yes
Supplies
Low-power modes
5 V, 3.3 V2
Stop mode
Slow mode
Packages
176 LQFP3
208 MAPBGA3,4
324 TEPBGA5
496-pin CSP6
176 LQFP3
208 MAPBGA3,4
324 TEPBGA5
496-pin CSP6
1
2
3
4
5
197 interrupt vectors are reserved.
5 V single supply only for 176 LQFP
Pinout compatible with Freescale’s MPC5634M devices
Pinout compatible with Freescale’s MPC5534
Ballmap upwardly compatible with the standardized package ballmap used for various Freescale MPC563xM family
members
6
For Freescale VertiCal Calibration System only
1.4
Block diagram
Figure 1 shows a top-level block diagram of the MPC5642A series.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
5
Introduction
Debug
JTAG
Power Architecture
Interrupt
Controller
e200z4
SPE
VLE
Nexus
IEEE-ISTO
5001-2010
MMU
64-channel
eDMA
8 KB I-cache
FlexRay
M4
M0
M1
M6
S1
Crossbar Switch
S0
MPU
S7
S2
Analog PLL
2 MB
Flash
128 KB
SRAM
Voltage Regulator
RCOSC
XOSC
Standby
Regulator
with Switch
ECSM
I/O Bridge
3 KB Data
ADCi
AMux
DEC
x2
eTPU2
eMIOS
24
Channel
RAM
14 KB Code
RAM
32
Channel
VGA
LEGEND
ADC
– Analog to Digital Converter
– ADC interface
– Analog Multiplexer
– Boot Assist Module
– Cyclic Redundancy Check unit
– Decimation Filter
– Development Trigger Semaphore
– Deserial/Serial Peripheral Interface
– Error Correction Status Module
– Enhanced Direct Memory Access
JTAG
– IEEE 1149.1 Test Controller
– Memory Management Unit
– Memory Protection Unit
– Power Management Controller
– Periodic Interrupt Timer
ADCi
AMux
BAM
CRC
DEC
DTS
DSPI
ECSM
eDMA
MMU
MPU
PMC
PIT
RCOSC – Low-speed RC Oscillator
REACM – Reaction Module
SIU
– System Integration Unit
– Signal Processing Extension
SPE
SRAM – Static RAM
eMIOS – Enhanced Modular Input Output System
eSCI – Enhanced Serial Communications Interface
STM
SWT
– System Timer Module
– Software Watchdog Timer
eTPU2 – Second gen. Enhanced Time Processing Unit VGA
– Variable Gain Amplifier
FlexCAN – Controller Area Network
VLE
– Variable Length (instruction) Encoding
FMPLL – Frequency-Modulated Phase-Locked Loop
XOSC – XTAL Oscillator
Figure 1. MPC5642A series block diagram
Table 2 summarizes the functions of the blocks present on the MPC5642A series microcontrollers.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
6
Freescale Semiconductor
Introduction
Table 2. MPC5642A series block summary
Function
Block
Boot assist module (BAM)
Block of read-only memory containing executable code that searches
for user-supplied boot code and, if none is found, executes the BAM
boot code resident in device ROM
Calibration bus interface
Transfers data across the crossbar switch to/from peripherals attached
to the calibration system connector
Controller area network (FlexCAN)
Crossbar switch (XBAR)
Supports the standard CAN communications protocol
Internal busmaster
Cyclic redundancy check (CRC)
Deserial serial peripheral interface (DSPI)
CRC checksum generator
Provides a synchronous serial interface for communication with
external devices
e200z4 core
Executes programs and interrupt handlers
Enhanced direct memory access (eDMA)
Performs complex data movements with minimal intervention from the
core.
Enhanced modular input-output system
(eMIOS)
Provides the functionality to generate or measure events
Enhanced queued analog-to-digital
converter (eQADC)
Provides accurate and fast conversions for a wide range of
applications
Enhanced serial communication interface
(eSCI)
Provides asynchronous serial communication capability with
peripheral devices and other microcontroller units
Enhanced time processor unit (eTPU2)
Second-generation co-processor processes real-time input events,
performs output waveform generation, and accesses shared data
without host intervention
Error Correction Status Module (ECSM)
The Error Correction Status Module supports a number of
miscellaneous control functions for the platform, and includes registers
for capturing information on platform memory errors if error-correcting
codes (ECC) are implemented
Flash memory
FlexRay
Provides storage for program code, constants, and variables
Provides high-speed distributed control for advanced automotive
applications
Frequency-modulated phase-locked loop
(FMPLL)
Generates high-speed system clocks and supports programmable
frequency modulation
Interrupt controller (INTC)
JTAG controller
Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode
Memory protection unit (MPU)
Nexus port controller (NPC)
Provides hardware access control for all memory references
generated
Provides real-time development support capabilities in compliance
with the IEEE-ISTO 5001-2010 standard
Periodic interrupt timer (PIT)
Reaction Module (REACM)
Produces periodic interrupts and triggers
Works in conjunction with the eQADC and eTPU2 to increase system
performance by removing the CPU from the current control loop.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
7
Introduction
Table 2. MPC5642A series block summary (continued)
Function
Block
System Integration Unit (SIU)
Controls MCU reset configuration, pad configuration, external
interrupt, general purpose I/O (GPIO), internal peripheral multiplexing,
and the system reset operation.
Static random-access memory (SRAM)
System timers
Provides storage for program code, constants, and variables
Includes periodic interrupt timer with real-time interrupt; output
compare timer and system watchdog timer
System watchdog timer (SWT)
Temperature sensor
Provides protection from runaway code
Provides the temperature of the device as an analog value
MPC5642A Microcontroller Data Sheet, Rev. 3.1
8
Freescale Semiconductor
Introduction
1.5
Feature details
e200z4 core
1.5.1
MPC5642A devices have a high performance e200z4 core processor:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
32-bit Power Architecture technology programmer’s model
Variable Length Encoding (VLE) enhancements
Dual issue, 32-bit Power Architecture technology compliant CPU
8 KB, 2/4-way set associative instruction cache
Thirty-two 64-bit general purpose registers (GPRs)
Memory Management Unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB)
Harvard Architecture: Separate instruction bus and load/store bus
Vectored interrupt support
Non-maskable interrupt input
Critical Interrupt input
New ‘Wait for Interrupt’ instruction, to be used with new low power modes
Reservation instructions for implementing read-modify-write accesses
Signal processing extension (SPE) APU
Single Precision Floating point (scalar and vector)
Nexus Class 3+ debug
Process ID manipulation for the MMU using an external tool
In-order execution and retirement
Precise exception handling
Branch processing unit
— Dedicated branch address calculation adder
— Branch target prefetching using 8-entry BTB
•
•
Supports independent instruction and data accesses to different memory subsystems, such as SRAM and flash memory
via independent Instruction and Data BIUs
Load/store unit
— 2-cycle load latency
— Fully pipelined
— Big and Little endian support
— Misaligned access support
•
•
•
Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the 64-bit General Purpose
Register file
Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single-precision floating-point operations,
using the 64-bit General Purpose Register file
Power management
— Low power design – extensive clock gating
— Power saving modes: wait
— Dynamic power management of execution units, cache and MMU
Testability
•
— Synthesizeable, MuxD scan design
— ABIST/MBIST for arrays
— Built-in Parallel Signature Unit
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
9
Introduction
•
Calibration support allowing an external tool to modify address mapping
1.5.2
Crossbar switch (XBAR)
The XBAR multiport crossbar switch supports simultaneous connections between four master ports and four slave ports. The
crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access
a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher
priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave
port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following
features:
•
4 master ports
— CPU instruction bus
— CPU data bus
— eDMA
— FlexRay
•
4 slave ports
— Flash
— Calibration bus interface
— SRAM
— Peripheral bridge
32-bit internal address, 64-bit internal data paths
•
1.5.3
Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 64 programmable channels, with minimal intervention from the host processor. The hardware
micro-architecture includes a DMA engine which performs source and destination address calculations, and the actual data
movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels.
This implementation minimizes overall block size. The eDMA module provides the following features:
•
•
•
•
•
•
All data movement via dual-address transfers: read from source, write to destination
Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes
Transfer control descriptor organized to support two-deep, nested transfer operations
An inner data transfer loop defined by a “minor” byte transfer count
An outer data transfer loop defined by a “major” iteration count
Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Peripheral-paced hardware requests (one per channel)
•
•
•
•
•
•
Support for fixed-priority and round-robin channel arbitration
Channel completion reported via optional interrupt requests
1 interrupt per channel, optionally asserted at completion of major iteration count
Error termination interrupts optionally enabled
Support for scatter/gather DMA processing
Ability to suspend channel transfers by a higher priority channel
MPC5642A Microcontroller Data Sheet, Rev. 3.1
10
Freescale Semiconductor
Introduction
1.5.4
Interrupt controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time
systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that
all tasks which share the resource cannot preempt each other.
The INTC provides the following features:
•
•
•
•
•
•
•
•
•
9-bit vector addresses
Unique vector for each interrupt request source
Hardware connection to processor or read from register
Each interrupt source can assigned a specific priority by software
Preemptive prioritized interrupt requests to processor
ISR at a higher priority preempts executing ISRs or tasks at lower priorities
Automatic pushing or popping of preempted priority to or from a LIFO
Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources
Low latency—3 clocks from receipt of interrupt request from peripheral to interrupt request to processor
This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.
1.5.5
Memory protection unit (MPU)
The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in a device. Using
preprogrammed region descriptors, which define memory spaces and their associated access rights, the MPU concurrently
monitors all system bus transactions and evaluates the appropriateness of each transfer. Memory references with sufficient
access control rights are allowed to complete; references that are not mapped to any region descriptor or have insufficient rights
are terminated with a protection error response.
The MPU has these major features:
•
Support for 16 memory region descriptors, each 128 bits in size
— Specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 GB
— MPU is invalid at reset, thus no access restrictions are enforced
— 2 types of access control definitions: processor core bus master supports the traditional {read, write, execute}
permissions with independent definitions for supervisor and user mode accesses; the remaining non-core bus
masters (eDMA, FlexRay) support {read, write} attributes
— Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a
coherent image of the descriptor
— Alternate memory view of the access control word for each descriptor provides an efficient mechanism to
dynamically alter the access rights of a descriptor only
— For overlapping region descriptors, priority is given to permission granting over access denying as this approach
provides more flexibility to system software
•
Support for two XBAR slave port connections (SRAM and PBRIDGE)
— For each connected XBAR slave port (SRAM and PBRIDGE), MPU hardware monitors every port access using
the preprogrammed memory region descriptors
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
11
Introduction
— An access protection error is detected if a memory reference does not hit in any memory region or the reference
is flagged as illegal in all memory regions where it does hit. In the event of an access error, the XBAR reference
is terminated with an error response and the MPU inhibits the bus cycle being sent to the targeted slave device
— 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes, and detail
information
1.5.6
Frequency-modulated phase-locked loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz crystal oscillator or external clock
generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication
factor, output clock divider ratio are all software configurable. The PLL has the following major features:
•
•
•
Input clock frequency from 4 MHz to 40 MHz
Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock
3 modes of operation
— Bypass mode with PLL off
— Bypass mode with PLL running (default mode out of reset)
— PLL normal mode
•
•
Each of the 3 modes may be run with a crystal oscillator or an external clock reference
Programmable frequency modulation
— Modulation enabled/disabled through software
— Triangle wave modulation up to 100 kHz modulation frequency
— Programmable modulation depth (0% to 2% modulation depth)
— Programmable modulation frequency dependent on reference frequency
•
•
Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to
report loss of lock conditions
Clock Quality Module
— Detects the quality of the crystal clock and causes interrupt request or system reset if error is detected
— Detects the quality of the PLL output clock; if error detected, causes system reset or switches system clock to
crystal clock and causes interrupt request
•
•
Programmable interrupt request or system reset on loss of lock
Self-clocked mode (SCM) operation
1.5.7
System integration unit (SIU)
The MPC5642A SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO),
internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot
configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block
provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring
of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z4 CPU core
is via the crossbar switch. The SIU provides the following features:
•
System configuration
— MCU reset configuration via external pins
— Pad configuration control for each pad
— Pad configuration control for virtual I/O via DSPI serialization
System reset monitoring and generation
•
— Power-on reset support
— Reset status register provides last reset source to software
MPC5642A Microcontroller Data Sheet, Rev. 3.1
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Freescale Semiconductor
Introduction
— Glitch detection on reset input
— Software controlled reset assertion
•
External interrupt
— Rising or falling edge event detection
— Programmable digital filter for glitch rejection
— Critical Interrupt request
— Non-Maskable Interrupt request
•
•
GPIO
— Centralized control of I/O and bus pins
— Virtual GPIO via DSPI serialization (requires external deserialization device)
— Dedicated input and output registers for setting each GPIO and Virtual GPIO pin
Internal multiplexing
— Allows serial and parallel chaining of DSPIs
— Allows flexible selection of eQADC trigger inputs
— Allows selection of interrupt requests between external pins and DSPI
— From a set of eTPU output channels, allows selection of source signals for decimation filter integrators
1.5.8
Flash memory
The MPC5642A provides 2 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used
to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the flash
array to match the CPU architecture. The flash module interfaces the system bus to a dedicated flash memory array controller.
For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and
128-bit read data interfaces to flash memory. The module contains a prefetch controller which prefetches sequential lines of
data from the flash array into the buffers. Prefetch buffer hits allow no-wait responses.
The flash memory provides the following features:
•
Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword
reads are supported. Only aligned word and doubleword writes are supported.
•
Fetch Accelerator
— Architected to optimize the performance of the flash
— Configurable read buffering and line prefetch support
— 4-entry 128-bit wide line read buffer
— Prefetch controller
•
•
Hardware and software configurable read and write access protections on a per-master basis
Interface to the flash array controller pipelined with a depth of one, allowing overlapped accesses to proceed in parallel
for pipelined flash array designs
•
•
Configurable access timing usable in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (0–31 additional cycles) usable for emulation of
other memory types
•
•
•
•
•
•
•
Software programmable block program/erase restriction control
Erase of selected block(s)
Read page size of 128 bits (4 words)
ECC with single-bit correction, double-bit detection
Program page size of 128 bits (4 words) to accelerate programming
ECC single-bit error corrections are visible to software
Minimum program size is 2 consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
13
Introduction
•
•
•
•
Embedded hardware program and erase algorithm
Erase suspend, program suspend and erase-suspended program
Shadow information stored in non-volatile shadow block
Independent program/erase of the shadow block
1.5.9
Static random access memory (SRAM)
The SRAM provides 128 KB of general purpose system SRAM. The first 32 KB block of the SRAM is powered by its own
power supply pin only during standby operation.
The SRAM controller includes these features:
•
•
•
•
•
•
128 KB data RAM implemented as eight 16 KB (2048 78 bits) blocks
Each 16 KB block has 2 rows repairable (RAMs with internal repair feature)
Supports read/write accesses mapped to the SRAM memory from any master
32 KB block powered by separate supply for standby operation
Byte, halfword, word and doubleword addressable
ECC performs single bit correction, double bit detection
1.5.10 Boot assist module (BAM)
The BAM is a block of read-only memory that is programmed once by Freescale and is identical for all MPC5642A MCUs.
The BAM program is executed every time the MCU is powered on or reset in normal mode. The BAM supports different modes
of booting. They are:
•
•
Booting from internal flash memory
Serial boot loading (boot code is downloaded into RAM via eSCI or the FlexCAN and then executed)
The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the MPC5642A
hardware accordingly. The BAM provides the following features:
•
Sets up MMU to cover all resources and mapping of all physical addresses to logical addresses with minimum address
translation
•
Sets up MMU to allow user boot code to execute as either Power Architecture technology code (default) or as Freescale
VLE code
•
•
•
•
•
•
•
•
•
•
Location and detection of user boot code
Automatic switch to serial boot mode if internal flash is blank or invalid
Supports user programmable 64-bit password protection for serial boot mode
Supports serial bootloading via FlexCAN bus and eSCI using Freescale protocol
Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing
Supports serial bootloading of either Power Architecture technology code (default) or Freescale VLE code
Supports booting from calibration bus interface
Supports censorship protection for internal flash memory
Provides an option to enable the core watchdog timer
Provides an option to disable the system watchdog timer
1.5.11 Enhanced modular input/output system (eMIOS)
The eMIOS timer module provides the capability to generate or measure events in hardware.
The eMIOS module features include:
•
Twenty-four 24-bit wide channels
MPC5642A Microcontroller Data Sheet, Rev. 3.1
14
Freescale Semiconductor
Introduction
•
•
•
•
•
3 channels’ internal timebases sharable between channels
1 timebase from eTPU2 can be imported and used by the channels
Global enable feature for all eMIOS and eTPU timebases
Dedicated pin for each channel (not available on all package types)
Each channel (0–23) supports the following functions:
— General Purpose Input/Output (GPIO)
— Single Action Input Capture (SAIC)
— Single Action Output Compare (SAOC)
— Output Pulse Width Modulation Buffered (OPWMB)
— Input Period Measurement (IPM)
— Input Pulse Width Measurement (IPWM)
— Double Action Output Compare (DOAC)
— Modulus Counter Buffered (MCB)
— Output Pulse Width & Frequency Modulation Buffered (OPWFMB)
Each channel has its own pin (not available on all package types)
•
1.5.12 Second generation enhanced time processing unit (eTPU2)
The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, the eTPU2
processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host
intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful
timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler
and documentation allows customers to develop their own functions on the eTPU2.
MPC5642A devices feature the second generation of the eTPU, called eTPU2. Enhancements of the eTPU2 over the standard
eTPU include:
•
•
•
•
The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input
[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.
Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this
enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.
A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture
characteristics of this channel mode can be programmed via microcode.
Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can
also be requested simultaneously at the same instruction.
•
•
Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.
Channel digital filters can be bypassed.
The eTPU2 includes these distinctive features:
•
32 channels; each channel associated with one input and one output signal
— Enhanced input digital filters on the input pins for improved noise immunity
— Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned
to more than one channel at a given time, so each signal can have any functionality.
— Each channel has an event mechanism which supports single and double action functionality in various
combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and
equal-only comparators.
— Input and output signal states visible from the host
•
2 independent 24-bit time bases for channel synchronization:
— First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by
output of second time base prescaler
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
15
Introduction
— Second time base counter can work as a continuous angle counter, enabling angle based applications to match
angle instead of time
— Both time bases can be exported to the eMIOS timer module
— Both time bases visible from the host
Event-triggered microengine:
•
— Fixed-length instruction execution in two-system-clock microcycle
— 14 KB of code memory (SCM)
— 3 KB of parameter (data) RAM (SPRAM)
— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected
combinations
— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value,
bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign
extension and conditional execution
— Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations,
and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands.
•
Resource sharing features support channel use of common channel registers, memory and microengine time:
— Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined,
host-configured priority
— Automatic channel context switch when a “task switch” occurs, that is, one function thread ends and another
begins to service a request from other channel: channel-specific registers, flags and parameter base address are
automatically loaded for the next serviced channel
— SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or
inter-channel
— Hardware implementation of 4 semaphores support coherent parameter sharing between both eTPU engines
— Dual-parameter coherency hardware support allows atomic access to 2 parameters by host
Test and development support features:
•
— Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware
breakpoints and watchpoints on several conditions
— Software breakpoints
— SCM continuous signature-check built-in self test MISC (multiple input signature calculator), runs concurrently
with eTPU2 normal operation
1.5.13 Reaction module (REACM)
The REACM provides the ability to modulate output signals to manage closed loop control without CPU assistance. It works
in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop.
The REACM has the following features:
•
•
•
6 reaction channels with peak and hold control blocks
Each channel output is a bus of 3 signals, providing ability to control 3 inputs.
Each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak
and hold control channels
Target applications include solenoid control for direct injection systems and valve control in automatic transmissions.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
16
Freescale Semiconductor
Introduction
1.5.14 Enhanced queued analog-to-digital converter (eQADC)
The eQADC block provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel
interface to two on-chip analog-to-digital converters (ADC), and a single master to single slave serial interface to an off-chip
external device. Both on-chip ADCs have access to all the analog channels.
The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the on-chip ADCs or to
the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six
result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having
the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort
a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a
deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger
occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands
from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result
queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system
memory, which is external to the eQADC.
The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used
in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for
increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics.
The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate,
passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate
results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band
noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully
process the digitized waveform.
The eQADC provides the following features:
•
Dual on-chip ADCs
— 2 12-bit ADC resolution
— Programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit)
–
–
–
12-bit conversion time – 938 ns (1M sample/s)
10-bit conversion time – 813 ns (1.2M sample/s)
8-bit conversion time – 688 ns (1.4M sample/s)
— Up to 10-bit accuracy at 500K sample/s and 8-bit accuracy at 1M sample/s
— Differential conversions
— Single-ended signal range from 0 to 5 V
— Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
— Provides time stamp information when requested
— Allows time stamp information relative to eTPU clock sources, such as an angle clock
— Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs (RFIFOs)
— Supports both right-justified unsigned and signed formats for conversion results
•
40 single-ended input channels, expandable to 56 channels with external multiplexers (supports 4 external 8-to-1
muxes)
•
•
•
8 channels can be used as 4 pairs of differential analog input channels
Differential channels include variable gain amplifier for improved dynamic range (1, 2, 4)
Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics
(200 k100 k5 k
•
Additional internal channels for monitoring voltages (such as core voltage, I/O voltage, LVI voltages, etc.) inside the
device
•
•
An internal bandgap reference to allow absolute voltage measurements
Silicon die temperature sensor
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
17
Introduction
— Provides temperature of silicon as an analog value
— Read using an internal ADC analog channel
— May be read with either ADC
•
2 decimation filters
— Programmable decimation factor (1 to 16)
— Selectable IIR or FIR filter
— Up to 4th order IIR or 8th order FIR
— Programmable coefficients
— Saturated or non-saturated modes
— Programmable Rounding (Convergent; Two’s Complement; Truncated)
— Prefill mode to precondition the filter before the sample window opens
— Supports Multiple Cascading Decimation Filters to implement more complex filter designs
— Optional Absolute Integrators on the output of Decimation Filters
Full duplex synchronous serial interface (SSI) to an external device
— Free-running clock for use by an external device
— Supports a 26-bit message length
•
•
Priority based queues
— Supports 6 queues with fixed priority. When commands of distinct queues are bound for the same ADC, the higher
priority queue is always served first
— Queue_0 can bypass all prioritization, buffering and abort current conversions to start a Queue_0 conversion a
deterministic time after the queue trigger
— Supports software and hardware trigger modes to arm a particular queue
— Generates interrupt when command coherency is not achieved
External hardware triggers
•
— Supports rising edge, falling edge, high level and low level triggers
— Supports configurable digital filter
1.5.15 Deserial serial peripheral interface (DSPI)
The DSPI block provides a synchronous serial interface for communication between the MPC5642A MCU and external
devices. The DSPI supports pin count reduction through serialization and deserialization of eTPU and eMIOS channels and
memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol. This SPI-like protocol
is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. Each bit in the frame may
be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be configured to serialize data
to an external device that implements the Microsecond Bus protocol. There are three identical DSPI blocks on the MPC5642A
MCU. The DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) to improve high speed operation.
DSPI module features include:
•
•
Selectable LVDS pads working at 40 MHz for SOUT and SCK pins for DSPI_B and DSPI_C
Support for downstream Micro Second Channel (MSC) with Timed Serial Bus (TSB) configuration on DSPI_B and
DSPI_C
•
•
3 sources of serialized data: eTPU_A, eMIOS output channels, and memory-mapped register in the DSPI
4 destinations for deserialized data: eTPU_A and eMIOS input channels, SIU external Interrupt input request,
memory-mapped register in the DSPI
•
•
32-bit DSI and TSB modes require 32 PCR registers, 32 GPO and GPI registers in the SIU to select either GPIO, eTPU
or eMIOS bits for serialization
The DSPI module can generate and check parity in a serial frame
MPC5642A Microcontroller Data Sheet, Rev. 3.1
18
Freescale Semiconductor
Introduction
1.5.16 Enhanced serial communications interface (eSCI)
Three eSCI modules provide asynchronous serial communications with peripheral devices and other MCUs, and include
support to interface to Local Interconnect Network (LIN) slave devices. Each eSCI block provides the following features:
•
•
•
•
•
Full-duplex operation
Standard mark/space non-return-to-zero (NRZ) format
13-bit baud rate selection
Programmable 8-bit or 9-bit data format
Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond bus
standard
•
•
Automatic parity generation
LIN support
— Compatible with LIN slaves from revisions 1.x and 2.0 of the LIN standard
— Autonomous transmission of entire frames
— Configurable to support all revisions of the LIN standard
— Automatic parity bit generation
— Double stop bit after bit error
— 10- or 13-bit break support
•
•
•
Separately enabled transmitter and receiver
Programmable transmitter output parity
2 receiver wake-up methods:
— Idle line wake-up
— Address mark wake-up
•
•
•
•
•
Interrupt-driven operation with flags
Receiver framing error detection
Hardware parity checking
1/16 bit-time noise detection
DMA support for both transmit and receive data
— Global error bit stored with receive data in system RAM to allow post processing of errors
1.5.17 Controller area network (FlexCAN)
The MPC5642A MCU includes three FlexCAN blocks. The FlexCAN module is a communication controller implementing the
CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle
serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment
of a vehicle, cost-effectiveness and required bandwidth. Each FlexCAN module contains 64 message buffers.
The FlexCAN modules provide the following features:
•
•
Based on and including all existing features of the Freescale TouCAN module
Full Implementation of the CAN protocol specification, Version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— Zero to eight bytes data length
— Programmable bit rate up to 1 Mbit/s
•
•
•
Content-related addressing
64 message buffers of 0 to 8 bytes data length
Individual Rx Mask Register per message buffer
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
19
Introduction
•
•
•
•
•
Each message buffer configurable as Rx or Tx, all supporting standard and extended messages
Includes 1088 bytes of embedded memory for message buffer storage
Includes 256-byte memory for storing individual Rx mask registers
Full-featured Rx FIFO with storage capacity for 6 frames and internal pointer handling
Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits)
IDs, with individual masking capability
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Selectable backwards compatibility with previous FlexCAN versions
Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock
Listen only mode capability
Programmable loop-back mode supporting self-test operation
3 programmable Mask Registers
Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority
Time Stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Warning interrupts when the Rx and Tx Error Counters reach 96
Independent of the transmission medium (an external transceiver is assumed)
Multi-master concept
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Low power mode, with programmable wakeup on bus activity
1.5.18 FlexRay
The MPC5642A includes one dual-channel FlexRay module that implements the FlexRay Communications System Protocol
Specification, Version 2.1 Rev A. Features include:
•
•
•
Single channel support
FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported
128 message buffers, each configurable as:
— Receive message buffer
— Single-buffered transmit message buffer
— Double-buffered transmit message buffer (combines two single-buffered message buffers)
2 independent receive FIFOs
•
•
— 1 receive FIFO per channel
— Up to 255 entries for each FIFO
ECC support
1.5.19 System timers
The system timers include two distinct types of system timer:
•
•
Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)
Operating system task monitors using the System Timer Module (STM)
1.5.19.1 Periodic interrupt timer (PIT)
The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has
no external input or output pins and is intended to provide system ‘tick’ signals to the operating system, as well as periodic
MPC5642A Microcontroller Data Sheet, Rev. 3.1
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Freescale Semiconductor
Introduction
triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock and one is clocked by the
crystal clock. This one channel is also referred to as Real-Time Interrupt (RTI) and is used to wake up the device from low power
stop mode.
The following features are implemented in the PIT:
•
•
•
•
•
5 independent timer channels
Each channel includes 32-bit wide down counter with automatic reload
4 channels clocked from system clock
1 channel clocked from crystal clock (wake-up timer)
Wake-up timer remains active when System STOP mode is entered; used to restart system clock after predefined
time-out period
•
Each channel optionally able to generate an interrupt request or a trigger event (to trigger eQADC queues) when timer
reaches zero
1.5.19.2 System timer module (STM)
1
The STM is designed to implement the software task monitor as defined by AUTOSAR . It consists of a single 32-bit counter,
clocked by the system clock, and four independent timer comparators. These comparators produce a CPU interrupt when the
timer exceeds the programmed value.
The following features are implemented in the STM:
•
•
•
•
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode
1.5.20 Software watchdog timer (SWT)
The SWT is a second watchdog module to complement the standard Power Architecture watchdog integrated in the CPU core.
The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or
interrupt request when the correct software key is not written within the required time window.
The following features are implemented:
•
•
•
•
•
•
•
32-bit modulus counter
Clocked by system clock or crystal clock
Optional programmable watchdog window mode
Can optionally cause system reset or interrupt request on timeout
Reset by writing a software key to memory mapped register
Enabled out of reset
Configuration is protected by a software key or a write-once register
1.5.21 Cyclic redundancy check (CRC) module
The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module features:
•
•
Support for CRC-16-CCITT (x25 protocol):
16
12
5
— x + x + x + 1
Support for CRC-32 (Ethernet protocol):
32
26
23
22
16
12
11
10
8
7
5
4
2
— x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1
1. AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
21
Introduction
•
Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency
1.5.22 Error correction status module (ECSM)
The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform
configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes,
and information on platform memory errors reported by error-correcting codes and/or generic access error information for
certain processor cores.
The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes
these features:
•
•
Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented
For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the
MPC5642A.
The sources of the ECC errors are:
•
•
•
Flash memory
SRAM
Peripheral RAM (FlexRay, CAN, eTPU2 parameter RAM)
1.5.23 Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
•
•
•
•
•
Duplicated periphery
Master access privilege level per peripheral (per master: read access enable; write access enable)
Write buffering for peripherals
Checker applied on PBRIDGE output toward periphery
Byte endianess swap capability
1.5.24 Calibration bus interface
The calibration bus interface controls data transfer across the crossbar switch to/from memories or peripherals attached to the
VertiCal connector in the calibration address space. The calibration bus interface is only available in the VertiCal Calibration
System.
Features include:
•
•
•
•
•
•
•
•
3.3 V ± 10% I/O (3.0 V to 3.6 V)
Memory controller supports various memory types
16-bit data bus, up to 22-bit address bus
Pin muxing supports 32-bit muxed bus
Selectable drive strength
Configurable bus speed modes
Bus monitor
Configurable wait states
1.5.25 Power management controller (PMC)
The PMC contains circuitry to generate the internal 3.3 V supply and to control the regulation of 1.2 V supply with an external
NPN ballast transistor. It also contains low voltage inhibit (LVI) and power-on reset (POR) circuits for the 1.2 V supply, the
3.3 V supply, the 3.3 V/5 V supply of the closest I/O segment (VDDEH1), and the 5 V supply of the regulators (VDDREG).
MPC5642A Microcontroller Data Sheet, Rev. 3.1
22
Freescale Semiconductor
Pinout and signal description
1.5.26 Nexus port controller (NPC)
The NPC block provides real-time Nexus Class3+ development support capabilities for the MPC5642A Power Architecture
technology-based MCU in compliance with the IEEE-ISTO 5001-2010 standard. MDO port widths of 4 pins and 12 pins are
available in all packages.
1.5.27 JTAG controller (JTAGC)
The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent
to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001
standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant
with the IEEE 1149.1-2001 standard and supports the following features:
•
•
IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP
A 5-bit instruction register that supports the additional following public instructions:
— ACCESS_AUX_TAP_NPC
•
•
— ACCESS_AUX_TAP_ONCE
— ACCESS_AUX_TAP_eTPU
— ACCESS_CENSOR
3 test data registers to support JTAG Boundary Scan mode
— Bypass register
— Boundary scan register
— Device identification register
•
•
A TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
Censorship Inhibit Register
— 64-bit Censorship password register
— If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash
shadow row, Censorship is disabled until the next system reset.
1.5.28 Development trigger semaphore (DTS)
MPC5642A devices include a system development feature, the Development Trigger Semaphore (DTS) module, that enables
user software to signal to an external tool—by driving a persistent (affected only by reset or an external tool) signal on an
external device pin—that data is available. The DTS includes a register of semaphores (32-bits) and an identification register.
There are a variety of ways this module can be used, including as a component of an external real-time data acquisition system.
2
Pinout and signal description
This section contains the pinouts for all production packages for the MPC5642A device. For pin signal descriptions, please refer
to Table 3
NOTE
Any pins labeled “NC” are to be left unconnected. Any connection to an external circuit or
voltage may cause unpredictable device behavior or damage.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
23
Pinout and signal description
2.1
176 LQFP pinout
AN[18]
AN[17]
VDD
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
TMS
2
AN[16]
TDI
3
AN[11] / ANZ
MDO5 / ETPUA4_O / GPIO[76]
4
AN[9] / ANX
TCK
VSS
5
VDDA
6
VSSA
MDO4 / ETPUA2_O / GPIO[75]
7
AN[39]
VDDEH7A
8
AN[8] / ANW
MDO11 / ETPUA29_O / GPIO[82]
9
VDDREG
TDO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VRCCTL
GPIO[219]
VSTBY
JCOMP
VRC33
EVTO
MCKO
NC
176-pin
LQFP
VSS
MSEO[0]
NC
MSEO[1]
MDO[0]
EVTI
MDO[1]
VSS
signal details:
MDO[2]
DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]
MDO[3]
DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]
pin 21: ETPUA31 / DSPI_C_PCS[4] / ETPUA13_O / GPIO[145]
pin 22: ETPUA30 / DSPI_C_PCS[3] / ETPUA11_O / GPIO[144]
pin 23: ETPUA29 / DSPI_C_PCS[2] / RCH5_C / GPIO[143]
pin 24: ETPUA28 / DSPI_C_PCS[1] / RCH5_B / GPIO[142]
pin 25: ETPUA27 / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT / GPIO[141]
pin 26: ETPUA26 / IRQ[14] / DSPI_C_SOUT_LVDS- / GPIO[140]
pin 27: ETPUA25 / IRQ[13] / DSPI_C_SCK_LVDS+ / GPIO[139]
pin 28: ETPUA24 / IRQ[12] / DSPI_C_SCK_LVDS- / GPIO[138]
pin 30: ETPUA23 / IRQ[11] / ETPUA21_O / FR_A_TX_EN / GPIO[137]
pin 32: ETPUA22 / IRQ[10] / ETPUA17_O / GPIO[136]
pin 34: ETPUA21 / IRQ[9] / RCH0_C / FR_A_RX / GPIO[135]
pin 35: ETPUA20 / IRQ[8] / RCH0_B / FR_A_TX / GPIO[134]
pin 36: ETPUA19 / DSPI_D_PCS[4] / RCH5_A / GPIO[133]
pin 37: ETPUA18 / DSPI_D_PCS[3] / RCH4_A / GPIO[132]
pin 38: ETPUA17 / DSPI_D_PCS[2] / RCH3_A / GPIO[131]
pin 39: ETPUA16 / DSPI_D_PCS[1] / RCH2_A / GPIO[130]
pin 40: ETPUA15 / DSPI_B_PCS[5] / RCH1_A / GPIO[129]
pin 42: ETPUA14 / DSPI_B_PCS[4] / ETPUA9_O / RCH0_A / GPIO[128]
(see signal details, pin 21)
(see signal details, pin 22)
(see signal details, pin 23)
(see signal details, pin 24)
(see signal details, pin 25)
(see signal details, pin 26)
(see signal details, pin 27)
(see signal details, pin 28)
VSS
DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]
DSPI_B_PCS[0] / DSPI_D_PCS[2] / GPIO[105]
VDDEH6B
DSPI_B_PCS[1] / DSPI_D_PCS[0] / GPIO[106]
VSS
DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]
DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]
DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]
DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]
(see signal details, pin 30)
VDDEH1A
(see signal details, pin 32)
VDD
VDDF
RSTOUT
CAN_C_TX / DSPI_D_PCS[3] / GPIO[87]
SCI_A_TX / EMIOS13 / GPIO[89]
(see signal details, pin 34)
(see signal details, pin 35)
(see signal details, pin 36)
(see signal details, pin 37)
(see signal details, pin 38)
(see signal details, pin 39)
(see signal details, pin 40)
VDDEH1B
SCI_A_RX / EMIOS15 / GPIO[90]
CAN_C_RX / DSPI_D_PCS[4] / GPIO[88]
98
RESET
97
VSS
96
VDDEH6A
95
VSS
94
XTAL
93
EXTAL
92
(see signal details, pin 42)
VSS
VDDPLL
91
VSS
90
NC
CAN_B_RX / DSPI_C_PCS[4] / SCI_C_RX / GPIO[86]
89
Note: Pin 96 (VSS) should be tied low.
Figure 2. 176-pin LQFP pinout (top view)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
24
Freescale Semiconductor
2.2
208 MAP BGA ballmap
1
2
3
AN11
4
VDDA1
AN21
AN17
VSS
5
6
7
AN5
8
9
10
11
12
13
MDO2
14
MDO0
MDO1
VSS
15
16
VSS
A
B
C
D
VSS
AN9
VSSA1
AN0
AN1
AN4
AN16
AN2
VRH
AN22
AN7
AN24
VRL
AN27
AN28
AN32
AN31
VSSA0
VDDA0
AN33
AN12-SDS
AN13-SDO
AN14-SDI
VDDEH7
VRC33
VSS
A
B
C
D
E
F
VDD
VSS
AN8
REFBYPC
AN3
AN25
AN23
AN30
MDO3
VDD
VSTBY
VRC33
VDD
VSS
AN34
AN18
AN15-FCK
VSS
MSEO0
EVTO
EVTI
TCK
AN39
VDD
AN6
AN35
TMS
TDI
NC
E
F
ETPUA30
ETPUA28
ETPUA24
ETPUA31
ETPUA29
ETPUA27
AN37
VDD
NC
MSEO1
JCOMP
ETPUA26
ETPUA25
AN36
ETPUA21
VDDEH6AB
TDO
MCKO
G
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DSPI_B_
SOUT
DSPI_B_ DSPI_B_SIN DSPI_B_
PCS[3]
G
PCS[0]
H
J
ETPUA23
ETPUA20
ETPUA22
ETPUA19
ETPUA17
ETPUA14
ETPUA18
ETPUA13
GPIO[99]
DSPI_B_
PCS[4]
DSPI_B_
PCS[2]
DSPI_B_
PCS[1]
H
J
DSPI_B_
PCS[5]
SCI_A_TX
GPIO[98]
DSPI_B_
SCK
K
L
ETPUA16
ETPUA12
ETPUA10
ETPUA8
ETPUA15
ETPUA11
ETPUA9
ETPUA4
ETPUA7
ETPUA6
ETPUA1
ETPUA0
VDDEH1AB
TCRCLKA
ETPUA5
VSS
CAN_C_TX SCI_A_RX
RSTOUT
VDDREG
RESET
VSS
K
L
SCI_B_TX CAN_C_RX WKPCFG
M
N
SCI_B_RX
VSS
PLLREF
VRCCTL
BOOTCFG1
NC
M
N
VDD
GPIO[207]
EMIOS4
EMIOS1
5
VRC33
NC
EMIOS2
EMIOS6
EMIOS9
EMIOS10 VDDEH4AB EMIOS12
MDO7_
ETPUA19_O
VRC33
EXTAL
P
R
T
ETPUA3
NC
ETPUA2
VSS
VDD
2
VSS
VDD
NC
3
VDD
GPIO[206]
EMIOS0
4
EMIOS8
EMIOS11
EMIOS13
8
MDO11_
MDO4_
MDO8_
CAN_A_TX
VDD
VSS
VDD
NC
VSS
VDD
15
XTAL
VDDPLL
VSS
P
R
T
ETPUA29_O ETPUA2_O ETPUA21_O
EMIOS3
GPIO[219]
6
EMIOS14
EMIOS15
9
MDO10_
ETPUA27_O
EMIOS23
CAN_A_RX CAN_B_RX
VSS
1
MDO9_
ETPUA25_O
MDO5_
ETPUA4_O ETPUA13_O
MDO6_
CAN_B_TX
VDDE12
ENGCLK
14
7
10 11
12
13
16
Figure 3. 208-pin MAPBGA package ballmap (viewed from above)
Pinout and signal description
2.3
324 TEPBGA ballmap
1
2
VDD
3
AN16
VDD
4
AN17
5
6
7
8
9
10
VRH
11
A
B
C
D
E
F
G
H
J
VSS
VRC33
AN11
AN10
AN8
AN37
AN36
AN20
VDD
VDDA1
AN21
AN0
VSSA1
AN4
AN23
AN5
AN6
AN3
AN25
AN24
AN7
VRL
VSS
AN18
REFBYPC
AN27
AN30
AN29
AN28
AN9
VSS
VDD
AN1
AN39
VSSA0
VRCCTL
MDO1
NC
AN38
VDDA0
MDO0
MDO2
NC
VSS
AN19
AN2
AN22
AN26
VSTBY
VDDREG
MDO3
NC
MCKO
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
L
ETPUA31
ETPUA27
NC
NC
VDDEH1AB
ETPUA30
ETPUA26
ETPUA29
Figure 4. 324-pin TEPBGA package ballmap (northwest, viewed from above)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
26
Freescale Semiconductor
Pinout and signal description
M
N
ETPUA23
NC
ETPUA24
NC
ETPUA25
ETPUA22
GPIO[12]
VDDE-EH
NC
ETPUA28
ETPUA21
GPIO[13]
GPIO[16]
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VDDE12
VRC33
P
NC
NC
R
GPIO[14]
GPIO[17]
NC
GPIO[15]
NC
T
U
NC
NC
NC
V
NC
VDDE-EH
ETPUA19
ETPUA16
ETPUA14
ETPUA13
2
NC
NC
W
Y
ETPUA20
ETPUA17
ETPUA15
VSS
ETPUA18
VSS
VSS
VDDE12
NC
NC
NC
NC
NC
6
NC
NC
NC
NC
7
VDDE12
NC
NC
NC
ENGCLK
ETPUA8
ETPUA7
ETPUA6
10
ETPUA4
ETPUA3
ETPUA2
ETPUA5
11
VDD
AA
AB
VDD
ETPUA10
ETPUA11
4
NC
NC
ETPUA9
CLKOUT
9
ETPUA12
3
NC
NC
1
5
8
Figure 5. 324-pin TEPBGA package ballmap (southwest, viewed from above)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
27
Pinout and signal description
12
13
14
15
16
17
18
19
20
21
VDD
22
VSS
DSPI_A_
PCS[5]
DSPI_A_
SOUT
MDO8_
ETPUA21_O ETPUA27_O
MDO10_
AN34
AN33
AN32
AN31
AN14-SDI
AN13-SDO
AN12-SDS
AN35
AN15-FCK
GPIO[207]
GPIO[206]
GPIO[204]
GPIO[203]
GPIO[99]
GPIO[98]
VDDEH7
VDD
A
B
C
DSPI_A_
PCS[4]
MDO7_ MDO4_
MDO5_
ETPUA4_O
DSPI_A_SIN
DSPI_A_SCK
VSS
VSS
VDDEH7
VDD
ETPUA19_O ETPUA2_O
MDO6_ MDO11_
DSPI_A_
PCS[1]
VSS
VDDEH7
ETPUA13_O ETPUA29_O
DSPI_A_
PCS[0]
MDO9_
VSS
VDDEH7
TMS
TCK
TDO
TDI
NC
D
E
F
G
H
J
ETPUA25_O
VDDEH7
VDDEH7
RDY
JCOMP
EVTO
EVTI
VSS
NC
MSEO0
VSS
MSEO1
DSPI_B_SIN
VDDEH7
DSPI_B_
SOUT
DSPI_B_
PCS[3]
DSPI_B_
PCS[0]
DSPI_B_
PCS[1]
VSS
VSS
VSS
VSS
VSS
VSS
VDDEH7
VSS
DSPI_B_
PCS[4]
DSPI_B_
PCS[2]
NC
DSPI_B_SCK
VSS
K
L
DSPI_B_
PCS[5]
VSS
NC
NC
Figure 6. 324-pin TEPBGA package ballmap (northeast, viewed from above)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
28
Freescale Semiconductor
Pinout and signal description
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VRC33
NC
NC
SCI_A_TX
SCI_A_RX
NC
NC
VSS
VDDEH6AB
NC
M
N
CAN_C_TX
NC
RSTOUT
NC
RSTCFG
RESET
VSS
P
R
VSS
BOOTCFG0
PLLCFG1
CAN_C_RX
VDD
VSS
T
VDDEH6AB
SCI_C_RX
SCI_C_TX
CAN_A_RX
VDDEH4AB
CAN_A_TX
19
BOOTCFG1
PLLREF
CAN_B_RX
VDD
EXTAL
XTAL
U
V
ETPUA1
ETPUA0
EMIOS0
TCRCLKA
12
EMIOS1
EMIOS2
EMIOS3
EMIOS4
13
VDDEH4AB
EMIOS5
EMIOS6
EMIOS7
14
EMIOS8
EMIOS9
EMIOS10
EMIOS11
15
EMIOS15
EMIOS14
EMIOS13
EMIOS12
16
EMIOS16
EMIOS17
EMIOS18
EMIOS19
17
EMIOS23
EMIOS22
EMIOS21
EMIOS20
18
VDDPLL
CAN_B_TX
VDD
W
Y
VSS
WKPCFG
SCI_B_RX
20
VSS
AA
AB
SCI_B_TX
21
VSS
22
Figure 7. 324-pin TEPBGA package ballmap (southeast, viewed from above)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
29
2.4
Signal summary
Table 3. MPC5642A signal properties
8
Status
Package pin No.
208
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
324
GPIO
FR_A_TX
GPIO[12]
FlexRay transmit data channel A
GPIO
A1
G
010
000
12
13
O
I/O
VDDE-EH /
Medium
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
—
—
—
—
—
—
R4
P5
T6
P3
P4
FR_A_TX_EN
GPIO[13]
FlexRay ch. A tx data enable
GPIO
A1
G
010
000
O
I/O
VDDE-EH /
Medium
FR_A_RX
GPIO[14]
FlexRay receive data ch. A
GPIO
A1
G
010
000
14
I
VDDE-EH /
Medium
—
R1
R2
R4
T1
I/O
FR_B_TX
GPIO[15]
FlexRay transmit data ch. B
GPIO
A1
G
010
000
15
O
I/O
VDDE-EH /
Medium
—
FR_B_TX_EN
GPIO[16]
FlexRay tx data enable for ch. B
GPIO
A1
G
010
000
16
O
I/O
VDDE-EH /
Medium
—
FR_B_RX
GPIO[17]
FlexRay receive data channel B
GPIO
A1
G
010
000
17
I
VDDE-EH /
Medium
—
I/O
9
GPIO[206] ETRIG0
GPIO[207] ETRIG1
GPIO[219]
GPIO / eQADC Trigger Input
GPIO / eQADC Trigger Input
GPIO
G
G
G
00
206
207
I/O
I/O
VDDEH7 /
143
144
122
C14
B14
—
10
Slow
9
00
VDDEH7 /
Slow
11
000 219
I/O
VDDEH7 /
MultV
Reset / Configuration
RESET
External Reset Input
External Reset Output
P
P
—
—
I
VDDEH6 /
Slow
RESET / Up
RESET / Up
RSTOUT / Down
PLLREF / Up
97
102
83
L16
K15
M14
R22
P21
V21
RSTOUT
01
230
208
O
VDDEH6 /
Slow
RSTOUT / Down
— / Up
PLLREF
IRQ[4]
ETRIG2
GPIO[208]
FMPLL Mode Selection
External Interrupt Request
eQADC Trigger Input
GPIO
P
A1
A2
G
001
010
100
000
I
I
I
VDDEH6 /
Slow
I/O
12
PLLCFG1
IRQ[5]
—
—
A1
A2
G
—
209
210
—
I
O
VDDEH6 /
Medium
— / Up
— / Up
—
—
—
—
U20
P22
External interrupt request
DSPI D data output
GPIO
010
100
000
DSPI_D_SOUT
GPIO[209]
I/O
RSTCFG
RSTCFG
GPIO
P
G
01
00
I
VDDEH6 /
Slow
— / Down
—
GPIO[210]
I/O
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
BOOTCFG[0]
IRQ[2]
GPIO[211]
Boot Config. Input
External Interrupt Request
GPIO
P
A1
G
01
10
00
211
I
I
VDDEH6 /
Slow
— / Down
BOOTCFG[0] /
Down
—
—
T20
I/O
BOOTCFG[1]
IRQ[3]
ETRIG3
Boot Config. Input
External Interrupt Request
eQADC Trigger Input
GPIO
P
A1
A2
G
001
010
100
000
212
213
I
I
I
VDDEH6 /
Slow
— / Down
— / Up
BOOTCFG[1] /
Down
85
86
M15
L15
U21
GPIO[212]
I/O
WKPCFG
NMI
DSPI_B_SOUT
Weak Pull Config. Input
Non-Maskable Interrupt
DSPI B data output
GPIO
P
A1
A2
G
001
010
100
000
I
I
O
VDDEH6 /
Medium
WKPCFG / Up
AA20
GPIO[213]
I/O
Calibration Bus
CAL_CS0
Calibration chip select
P
01
336
338
O
VDDE12 /
Fast
— / —
— / —
—
—
—
—
—
—
CAL_CS2
CAL_ADDR[10]
CAL_WE[2]/BE[2]
Calibration chip select
Calibration address bus
Calibration write/byte enable
P
A1
A2
001
010
100
O
I/O
O
VDDE12 /
Fast
CAL_CS3
CAL_ADDR[11]
CAL_WE[3]/BE[3]
Calibration chip select
Calibration address bus
Calibration write/byte enable
P
A1
A2
001
010
100
339
O
I/O
O
VDDE12 /
Fast
— / —
—
—
—
CAL_ADDR[12]
CAL_WE[2]/BE[2]
Calibration address bus
Calibration write/byte enable
P
A1
01
10
340
340
340
340
345
345
345
345
345
345
I/O
O
VDDE12 /
Fast
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CAL_ADDR[13]
CAL_WE[3]/BE[3]
Calibration address bus
Calibration write/byte enable
P
A1
01
10
I/O
O
VDDE12 /
Fast
CAL_ADDR[14]
CAL_DATA[31]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[15]
CAL_ALE
Calibration address bus
Calibration address latch enable
P
A1
01
10
I/O
O
VDDE12 /
Fast
CAL_ADDR[16]
CAL_DATA[16]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[17]
CAL_DATA[17]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[18]
CAL_DATA[18]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[19]
CAL_DATA[19]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[20]
CAL_DATA[20]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[21]
CAL_DATA[21]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
CAL_ADDR[22]
CAL_DATA[22]
Calibration address bus
Calibration data bus
P
A1
01
10
345
345
345
345
345
345
345
345
345
341
341
341
341
341
341
341
341
341
341
I/O
I/O
VDDE12 /
Fast
— / —
—
—
—
CAL_ADDR[23]
CAL_DATA[23]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / —
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CAL_ADDR[24]
CAL_DATA[24]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[25]
CAL_DATA[25]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[26]
CAL_DATA[26]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[27]
CAL_DATA[27]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[28]
CAL_DATA[28]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[29]
CAL_DATA[29]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_ADDR[30]
CAL_DATA[30]
Calibration address bus
Calibration data bus
P
A1
01
10
I/O
I/O
VDDE12 /
Fast
CAL_DATA[0]
CAL_DATA[1]
CAL_DATA[2]
CAL_DATA[3]
CAL_DATA[4]
CAL_DATA[5]
CAL_DATA[6]
CAL_DATA[7]
CAL_DATA[8]
CAL_DATA[9]
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
P
P
P
P
P
P
P
P
P
P
01
01
01
01
01
01
01
01
01
01
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDE12 /
Fast
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
VDDE12 /
Fast
VDDE12 /
Fast
VDDE12 /
Fast
VDDE12 /
Fast
VDDE12 /
Fast
VDDE12 /
Fast
VDDE12 /
Fast
VDDE12 /
Fast
VDDE12 /
Fast
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
CAL_DATA[10]
CAL_DATA[11]
CAL_DATA[12]
CAL_DATA[13]
CAL_DATA[14]
CAL_DATA[15]
CAL_RD_WR
CAL_WE[0]
Calibration data bus
P
P
P
P
P
P
P
P
P
P
01
341
341
341
341
341
341
342
342
342
342
343
—
I/O
I/O
I/O
I/O
I/O
I/O
O
VDDE12 /
Fast
— / Up
— / Up
—
—
—
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration data bus
Calibration write enable
Calibration write enable
01
01
01
01
01
01
01
01
01
VDDE12 /
Fast
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / —
— / —
— / —
— / —
— / —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDE12 /
Fast
VDDE12 /
Fast
VDDE12 /
Fast
VDDE12 /
Fast
VDDE12 /
Fast
O
VDDE12 /
Fast
CAL_WE[1]
O
VDDE12 /
Fast
CAL_OE
Calibration output enable
O
VDDE12 /
Fast
CAL_TS
CAL_ALE
Calibration transfer start
Address Latch Enable
P
A1
01
10
O
O
VDDE12 /
Fast
CAL_MDO[4]
CAL_MDO[5]
CAL_MDO[6]
CAL_MDO[7]
CAL_MDO[8]
CAL_MDO[9]
CAL_MDO[10]
CAL_MDO[11]
Calibration Nexus Message Data Out
Calibration Nexus Message Data Out
Calibration Nexus Message Data Out
Calibration Nexus Message Data Out
Calibration Nexus Message Data Out
Calibration Nexus Message Data Out
Calibration Nexus Message Data Out
Calibration Nexus Message Data Out
P
P
P
P
P
P
P
P
01
01
01
01
01
01
01
01
O
O
O
O
O
O
O
O
VDDE12 /
Fast
—
—
—
—
—
—
—
—
CAL_MDO[4] / —
CAL_MDO[5] / —
CAL_MDO[6] / —
CAL_MDO[7] / —
CAL_MDO[8] / —
CAL_MDO[9] / —
CAL_MDO[10] / —
CAL_MDO[11] / —
—
VDDE12 /
Fast
—
VDDE12 /
Fast
—
VDDE12 /
Fast
—
VDDE12 /
Fast
—
VDDE12 /
Fast
—
VDDE12 /
Fast
—
VDDE12 /
Fast
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
208
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
324
13
NEXUS
EVTI
Nexus event in
P
P
P
P
P
P
P
01
01
—
01
01
01
01
231
I
VDDEH7 /
MultiV
— / Up
EVTI / Up
EVTO / —
MCKO / —
116
120
14
E15
D15
F15
A14
B14
A13
B13
P10
H20
G20
F1
14
EVTO
Nexus event out
227
O
O
O
O
O
O
VDDEH7 /
MultiV
ABR/Up
11
MCKO
Nexus message clock out
Nexus message data out
Nexus message data out
Nexus message data out
Nexus message data out
219
VRC33 /
Fast
—
—
—
—
—
—
MDO[0]
MDO[1]
MDO[2]
MDO[3]
MDO[4]
220
221
222
223
75
VRC33 /
Fast
MDO[0] / —
MDO[1] / —
MDO[2] / —
MDO[3] / —
— / —
17
F3
VRC33 /
Fast
18
G2
VRC33 /
Fast
19
G3
VRC33 /
Fast
20
G4
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH7 /
MultiV
126
B19
ETPUA2_O
GPIO[75]
MDO[5]
ETPUA4_O
GPIO[76]
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
76
77
78
79
80
81
82
O
O
I/O
VDDEH7 /
MultiV
—
—
—
—
—
—
—
— / —
— / —
— / —
— / —
— / —
— / —
— / —
129
135
136
137
139
134
124
T10
T11
N11
P11
T7
B20
C18
B18
A18
D18
A19
C19
MDO[6]
ETPUA13_O
GPIO[77]
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH7 /
MultiV
MDO[7]
ETPUA19_O
GPIO[78]
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH7 /
MultiV
MDO[8]
ETPUA21_O
GPIO[79]
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH7 /
MultiV
MDO[9]
ETPUA25_O
PIO[80]
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH7 /
MultiV
MDO[10]
ETPUA27_O
GPIO[81]
Nexus message data out
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH7 /
MultiV
R10
P9
MDO[11]
ETPUA29_O
GPIO[82]
Nexus message data out
eTPU A channel (output only)
GPIO[82]
P
A1
G
01
10
00
O
O
I/O
VDDEH7 /
MultiV
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
MSEO[0]
MSEO[1]
RDY
Nexus message start/end out
Nexus message start/end out
Nexus ready output
P
P
P
01
224
225
226
O
O
O
VDDEH7 /
MultiV
—
MSEO[0] / —
MSEO[1] / —
—
118
C15
G21
01
01
VDDEH7 /
MultiV
—
—
117
—
E16
—
G22
G19
VDDEH7 /
MultiV
JTAG
TCK
JTAG test clock input
P
P
P
P
P
01
01
01
01
01
—
232
228
—
I
I
VDDEH7 /
MultiV
TCK / Down
TDI / Up
TCK / Down
TDI / Up
128
130
123
131
121
C16
E14
F14
D14
F16
D21
D22
E21
E20
F20
TDI
JTAG test data input
VDDEH7 /
MultiV
TDO
TMS
JCOMP
JTAG test data output
JTAG test mode select input
JTAG TAP controller enable
O
I
VDDEH7 /
MultiV
TDO / Up
TMS / Up
TDO / Up
VDDEH7 /
MultiV
TMS / Up
—
I
VDDEH7 /
MultiV
JCOMP / Down
JCOMP / Down
FlexCAN
CAN_A_TX
SCI_A_TX
GPIO[83]
FlexCAN A transmit
eSCI A transmit
GPIO
P
A1
G
01
10
00
83
84
85
O
O
I/O
VDDEH6 /
Slow
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
81
82
88
P12
R12
T12
AB19
Y19
CAN_A_RX
SCI_A_RX
GPIO[84]
FlexCAN A receive
eSCI A receive
GPIO
P
A1
G
01
10
00
I
I
VDDEH6 /
Slow
I/O
CAN_B_TX
DSPI_C_PCS[3]
SCI_C_TX
FlexCAN B transmit
DSPI C peripheral chip select
eSCI C transmit
P
A1
A2
G
001
010
100
000
O
O
O
VDDEH6 /
Slow
Y22
GPIO[85]
GPIO
I/O
CAN_B_RX
DSPI_C_PCS[4]
SCI_C_RX
FlexCAN B receive
DSPI C peripheral chip select
eSCI C receive
P
A1
A2
G
001
010
100
000
86
I
O
I
VDDEH6 /
Slow
— / Up
— / Up
89
R13
W21
GPIO[86]
GPIO
I/O
CAN_C_TX
DSPI_D_PCS[3]
GPIO[87]
FlexCAN C transmit
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
87
88
O
O
I/O
VDDEH6 /
Medium
— / Up
— / Up
— / Up
— / Up
101
98
K13
L14
P19
V20
CAN_C_RX
DSPI_D_PCS[4]
GPIO[88]
FlexCAN C receive
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
I
O
I/O
VDDEH6 /
Slow
eSCI
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
SCI_A_TX
EMIOS13
GPIO[89]
eSCI A transmit
eMIOS channel
GPIO
P
A1
G
01
10
00
89
O
O
I/O
VDDEH6 /
Medium
— / Up
— / Up
100
J14
N20
15
SCI_A_RX
EMIOS15
GPIO[90]
eSCI A receive
eMIOS channel
GPIO
P
A1
G
01
10
00
90
91
92
I
O
I/O
VDDEH6 /
Medium
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
99
87
84
K14
L13
M13
P20
15
SCI_B_TX
DSPI_D_PCS[1]
GPIO[91]
eSCI B transmit
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH6 /
Medium
AB21
SCI_B_RX
DSPI_D_PCS[5]
GPIO[92]
eSCI B receive
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
I
O
I/O
VDDEH6 /
Medium
AB20
SCI_C_TX
GPIO[244]
eSCI C transmit
GPIO
P
G
01
00
244
245
O
I/O
VDDEH6 /
Medium
— / Up
— / Up
— / Up
— / Up
—
—
—
—
W19
V19
SCI_C_RX
GPIO[245]
eSCI C receive
GPIO
P
G
01
00
I
VDDEH6 /
Medium
I/O
DSPI
16
DSPI_A_SCK
—
—
A1
G
—
10
00
93
94
95
96
97
98
99
100
—
O
I/O
VDDEH7 /
Medium
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
—
—
C17
B17
A17
D16
C16
C15
DSPI_C_PCS[1]
DSPI C peripheral chip select
GPIO
GPIO[93]
16
DSPI_A_SIN
—
—
A1
G
—
10
00
—
O
I/O
VDDEH7 /
Medium
DSPI_C_PCS[2]
GPIO[94]
DSPI C peripheral chip select
GPIO
16
DSPI_A_SOUT
DSPI_C_PCS[5]
GPIO[95]
—
—
A1
G
—
10
00
—
O
I/O
VDDEH7 /
Medium
—
—
DSPI C peripheral chip select
GPIO
16
DSPI_A_PCS[0]
DSPI_D_PCS[2]
GPIO[96]
—
—
A1
G
—
10
00
—
O
I/O
VDDEH7 /
Medium
—
—
DSPI C peripheral chip select
GPIO
16
DSPI_A_PCS[1]
DSPI_B_PCS[2]
GPIO[97]
—
—
A1
G
—
10
00
—
O
I/O
VDDEH7 /
Medium
—
—
DSPI C peripheral chip select
GPIO
16
16
16
DSPI_A_PCS[2]
DSPI_D_SCK
GPIO[98]
—
—
A1
G
—
10
00
—
I/O
I/O
VDDEH7 /
Medium
141
142
—
J15
H13
—
SPI clock pin for DSPI module
GPIO
DSPI_A_PCS[3]
DSPI_D_SIN
GPIO[99]
—
—
A1
G
—
10
00
—
I
I/O
VDDEH7 /
Medium
B15
DSPI D data input
GPIO
DSPI_A_PCS[4]
DSPI_D_SOUT
GPIO[100]
—
—
A1
G
—
10
00
—
O
I/O
VDDEH7 /
Medium
B16
DSPI D data output
GPIO
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
16
DSPI_A_PCS[5]
DSPI_B_PCS[3]
GPIO[101]
—
—
A1
G
—
10
00
101
—
O
I/O
VDDEH7 /
Medium
— / Up
— / Up
—
—
A16
DSPI B peripheral chip select
GPIO
DSPI_B_SCK
DSPI_C_PCS[1]
GPIO[102]
SPI clock pin for DSPI module
DSPI B peripheral chip select
GPIO
P
A1
G
01
10
00
102
103
104
105
106
107
108
109
110
I/O
O
I/O
VDDEH6 /
Medium
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
106
112
113
111
109
107
114
105
104
J16
G15
G13
G16
H16
H15
G14
H14
J13
K21
H22
J19
J21
J22
K22
J20
K20
L19
DSPI_B_SIN
DSPI_C_PCS[2]
GPIO[103]
DSPI B data input
DSPI C peripheral chip select
GPIO
P
A1
G
01
10
00
I
O
I/O
VDDEH6 /
Medium
DSPI_B_SOUT
DSPI_C_PCS[5]
GPIO[104]
DSPI B data output
DSPI C peripheral chip select
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH6 /
Medium
DSPI_B_PCS[0]
DSPI_D_PCS[2]
GPIO[105]
DSPI B peripheral chip select
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
I/O
O
I/O
VDDEH6 /
Medium
DSPI_B_PCS[1]
DSPI_D_PCS[0]
GPIO[106]
DSPI B peripheral chip select
DSPI D peripheral chip select
GPIO
P
A1
G
01
10
00
O
I/O
I/O
VDDEH6 /
Medium
DSPI_B_PCS[2]
DSPI_C_SOUT
GPIO[107]
DSPI B peripheral chip select
DSPI C data output
GPIO
P
A1
G
01
10
00
O
O
I/O
VDDEH6 /
Medium
DSPI_B_PCS[3]
DSPI_C_SIN
GPIO[108]
DSPI B peripheral chip select
DSPI C data input
GPIO
P
A1
G
01
10
00
O
I
I/O
VDDEH6 /
Medium
DSPI_B_PCS[4]
DSPI_C_SCK
GPIO[109]
DSPI B peripheral chip select
SPI clock pin for DSPI module
GPIO
P
A1
G
01
10
00
O
I/O
I/O
VDDEH6 /
Medium
DSPI_B_PCS[5]
DSPI_C_PCS[0]
GPIO[110]
DSPI B peripheral chip select
DSPI C peripheral chip select
GPIO
P
A1
G
01
10
00
O
I/O
I/O
VDDEH6 /
Medium
eQADC
AN0
DAN0+
Single Ended Analog Input
Positive Terminal Differential Input
P
P
P
—
—
—
—
—
—
I
VDDA /
Analog
Pull-up/down
I / —
I / —
I / —
AN[0] / —
AN[1] / —
AN[2] / —
172
171
170
B5
A6
D6
C6
C7
D7
AN1
DAN0
Single Ended Analog Input
Negative Terminal Differential Input
I
I
VDDA /
Analog
Pull-up/down
AN2
DAN1+
Single Ended Analog Input
Positive Terminal Differential Input
VDDA /
Analog
Pull-up/down
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
P
—
—
I
I
I
I
I
VDDA /
Analog
Pull-up/down
I / —
AN[3] / —
169
C7
D8
AN3
DAN1
Single Ended Analog Input
Negative Terminal Differential Input
P
P
P
P
—
—
—
—
—
—
—
—
VDDA /
Analog
Pull-up/down
I / —
I / —
I / —
I / —
AN[4] / —
AN[5] / —
AN[6] / —
AN[7] / —
168
167
166
165
B6
A7
D7
C8
B7
B8
C8
C9
AN4
DAN2+
Single Ended Analog Input
Positive Terminal Differential Input
VDDA /
Analog
Pull-up/down
AN5
DAN2
Single Ended Analog Input
Negative Terminal Differential Input
VDDA /
Analog
Pull-up/down
AN6
DAN3+
Single Ended Analog Input
Positive Terminal Differential Input
VDDA /
Analog
AN7
Single Ended Analog Input
DAN3
Negative Terminal Differential Input
Pull-up/down
AN8
ANW
Single-ended Analog Input
Multiplexed Analog Input
P
P
P
P
01
01
01
01
—
—
I
I
I
I
VDDA /
Analog
I / —
I / —
I / —
I / —
I / —
AN[8] / —
AN[9] / —
AN[10] / —
AN[11] / —
AN[12] / —
9
5
B3
A2
E1
C2
AN9
ANX
Single-ended Analog Input
External Multiplexed Analog Input
VDDA /
Analog
AN10
ANY
Single-ended Analog Input
Multiplexed Analog Input
—
VDDA /
Analog
—
4
—
D1
AN11
ANZ
Single-ended Analog Input
Multiplexed Analog Input
—
VDDA /
Analog
A3
C1
AN12 - SDS
MA0
ETPUA19_O
Single-ended Analog Input
MUX Address 0
eTPU A channel (output only)
P
A1
A2
G
001
010
100
000
215
I
O
O
I/O
VDDEH7 /
Medium
148
A12
C13
SDS
eQADC Serial Data Select
AN13 - SDO
MA1
ETPUA21_O
SDO
Single-ended Analog Input
MUX Address 1
eTPU A channel (output only)
eQADC Serial Data Out
P
A1
A2
G
001
010
100
000
216
217
218
I
VDDEH7 /
Medium
I / —
I / —
I / —
AN[13] / —
AN[14] / —
AN[15] / —
147
146
145
B12
C12
C13
B13
A13
A14
O
O
O
AN14 - SDI
MA2
ETPUA27_O
SDI
Single-ended Analog Input
MUX Address 2
eTPU A channel (output only)
eQADC Serial Data In
P
A1
A2
G
001
010
100
000
I
VDDEH7 /
Medium
O
O
I
AN15 - FCK
FCK
ETPUA29_O
Single-ended Analog Input
eQADC Free Running Clock
eTPU A channel (output only)
P
A1
A2
001
010
100
I
O
O
VDDEH7 /
Medium
AN16
Single-ended Analog Input
P
P
—
—
—
I
I
VDDA /
Analog
I / —
I / —
AN[16] / —
AN[17] / —
3
2
C6
C4
A3
A4
AN17
Single-ended Analog Input
—
VDDA /
Analog
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
VDDA /
Analog
I / —
AN[18] / —
1
D5
B4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDA /
Analog
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
AN[19] / —
AN[20] / —
AN[21] / —
AN[22] / —
AN[23] / —
AN[24] / —
AN[25] / —
AN[26] / —
AN[27] / —
AN[28] / —
AN[29] / —
AN[30] / —
AN[31] / —
AN[32] / —
AN[33] / —
AN[34] / —
AN[35] / —
AN[36] / —
—
—
—
D6
C5
VDDA /
Analog
—
VDDA /
Analog
173
161
160
159
158
—
B4
B6
VDDA /
Analog
B8
D9
VDDA /
Analog
C9
A8
VDDA /
Analog
D8
B9
VDDA /
Analog
B9
A9
VDDA /
Analog
—
D10
C10
D11
C11
B11
D12
C12
B12
A12
D13
B5
VDDA /
Analog
157
156
—
A10
B10
—
VDDA /
Analog
VDDA /
Analog
VDDA /
Analog
155
154
153
152
151
150
174
D9
VDDA /
Analog
D10
C10
C11
C5
VDDA /
Analog
VDDA /
Analog
VDDA /
Analog
VDDA /
Analog
D11
F4
VDDA /
Analog
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
AN37
AN38
AN39
VRH
VRL
Single-ended Analog Input
Single-ended Analog Input
Single-ended Analog Input
Voltage Reference High
Voltage Reference Low
P
P
P
P
P
P
—
—
—
—
—
—
—
I
I
I
I
I
I
VDDA /
Analog
I / —
AN[37] / —
175
E3
A5
—
—
—
—
—
VDDA /
Analog
I / —
I / —
I / —
I / —
I / —
AN[38] / —
—
8
—
D2
A8
A9
B7
D3
D2
VDDA /
Analog
AN[39] / —
VDDA /
—
—
—
—
163
162
164
A10
A11
B10
VDDA /
—
REFBYBC
Reference Bypass Capacitor
Input
VDDA /
Analog
eTPU2
TCRCLKA
IRQ[7]
GPIO[113]
eTPU A TCR clock
External interrupt request
GPIO
P
A1
G
01
10
00
113
114
I
I
VDDEH4 /
Slow
— / Up
— / Up
—
L4
AB12
Y12
I/O
ETPUA0
eTPU A channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
61
N3
ETPUA12_O
ETPUA19_O
GPIO[114]
eTPU A channel (output only)
eTPU A channel (output only)
GPIO
I/O
ETPUA1
ETPUA13_O
GPIO[115]
eTPU A channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
115
116
117
118
I/O
O
I/O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
60
59
58
56
M3
P2
P1
N2
W12
AA11
Y11
ETPUA2
ETPUA14_O
GPIO[116]
eTPU A channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
I/O
O
I/O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
ETPUA3
ETPUA15_O
GPIO[117]
eTPU A channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
I/O
O
I/O
VDDEH4 /
Slow
— / WKPCFG
GPIO / WKPCFG
ETPUA4
ETPUA16_O
—
FR_B_TX
GPIO[118]
eTPU A channel
eTPU A channel (output only)
—
FlexRay transmit data channel B
GPIO
P
0001
0010
—
1000
0000
I/O
O
—
O
I/O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
W11
A1
A2
A3
G
ETPUA5
ETPUA17_O
DSPI_B_SCK_LVDS
FR_B_TX_EN
GPIO[119]
eTPU A channel
P
0001
0010
0100
1000
0000
119
I/O
O
O
O
I/O
VDDEH4 /
Slow +
LVDS
— /
WKPCFG
— /
WKPCFG
54
M4
AB11
eTPU A channel (output only)
LVDS negative DSPI clock
FlexRay tx data enable for ch. B
GPIO
A1
A2
A3
G
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
ETPUA6
ETPUA18_O
DSPI_B_SCK_LVDS+
FR_B_RX
eTPU A channel
P
0001
0010
0100
1000
0000
120
I/O
O
O
VDDEH4 /
Medium +
LVDS
— /
WKPCFG
— /
WKPCFG
53
L3
AB10
eTPU A channel (output only)
LVDS positive DSPI clock
FlexRay receive data channel B
GPIO
A1
A2
A3
G
I
GPIO[120]
I/O
ETPUA7
ETPUA19_O
eTPU A channel
eTPU A channel (output only)
P
0001
0010
0100
1000
0000
121
I/O
O
O
O
I/O
VDDEH4 /
Slow +
LVDS
— /
WKPCFG
— /
WKPCFG
52
K3
AA10
A1
A2
A3
G
DSPI_B_SOUT_LVDS LVDS negative DSPI data out
ETPUA6_O
GPIO[121]
eTPU A channel (output only)
GPIO
ETPUA8
ETPUA20_O
eTPU A channel
eTPU A channel (output only)
P
A1
A2
G
001
010
100
000
122
123
124
125
126
I/O
O
O
VDDEH4 /
Slow +
LVDS
— /
WKPCFG
— /
WKPCFG
51
50
49
48
47
N1
M2
M1
L2
Y10
AA9
AA4
AB4
AB3
DSPI_B_SOUT_LVDS+ LVDS positive DSPI data out
GPIO[122]
GPIO
I/O
ETPUA9
ETPUA21_O
RCH1_B
eTPU A channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
eTPU A channel (output only)
Reaction channel 1B
GPIO
GPIO[123]
I/O
ETPUA10
ETPUA22_O
RCH1_C
eTPU A channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH1 /
Slow
— /
WKPCFG
— /
WKPCFG
eTPU A channel (output only)
Reaction channel 1C
GPIO
GPIO[124]
I/O
ETPUA11
ETPUA23_O
RCH4_B
eTPU A channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH1 /
Slow
— /
WKPCFG
— /
WKPCFG
eTPU A channel (output only)
Reaction channel 4B
GPIO
GPIO[125]
I/O
ETPUA12
DSPI_B_PCS[1]
RCH4_C
eTPU A channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH1 /
Medium
— /
WKPCFG
— /
WKPCFG
L1
DSPI B peripheral chip select
Reaction channel 4C
GPIO
GPIO[126]
I/O
ETPUA13
DSPI_B_PCS[3]
GPIO[127]
eTPU A channel
DSPI B peripheral chip select
GPIO
P
A1
G
01
10
00
127
128
I/O
O
I/O
VDDEH1 /
Medium
— /
WKPCFG
— /
WKPCFG
46
42
J4
J3
AB2
AA2
ETPUA14
eTPU A channel
P
0001
0010
0100
1000
0000
I/O
O
O
O
I/O
VDDEH1 /
Medium
— /
WKPCFG
— /
WKPCFG
DSPI_B_PCS[4]
ETPUA9_O
RCH0_A
DSPI B peripheral chip select
eTPU A channel (output only)
Reaction channel 0A
GPIO
A1
A2
A3
G
GPIO[128]
ETPUA15
DSPI_B_PCS[5]
RCH1_A
GPIO[129]
eTPU A channel
DSPI B peripheral chip select
Reaction channel 1A
GPIO
P
A1
A2
G
001
010
100
000
129
130
I/O
O
O
VDDEH1 /
Medium
— /
WKPCFG
— /
WKPCFG
40
39
K2
K1
AA1
Y2
I/O
ETPUA16
DSPI_D_PCS[1]
RCH2_A
GPIO[130]
eTPU A channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH1 /
Slow
— /
WKPCFG
— /
WKPCFG
DSPI D peripheral chip select
Reaction channel 2A
GPIO
I/O
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
ETPUA17
DSPI_D_PCS[2]
RCH3_A
GPIO[131]
eTPU A channel
P
A1
A2
G
001
010
100
000
131
I/O
O
O
VDDEH1 /
Slow
— /
WKPCFG
— /
WKPCFG
38
H3
Y1
DSPI D peripheral chip select
Reaction channel 3A
GPIO
I/O
ETPUA18
DSPI_D_PCS[3]
RCH4_A
GPIO[132]
eTPU A channel
P
A1
A2
G
001
010
100
000
132
133
134
I/O
O
O
VDDEH1 /
Slow
— /
WKPCFG
— /
WKPCFG
37
36
35
H4
J2
J1
W3
W2
W1
DSPI D peripheral chip select
Reaction channel 4A
GPIO
I/O
ETPUA19
DSPI_D_PCS[4]
RCH5_A
GPIO[133]
eTPU A channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH1 /
Slow
— /
WKPCFG
— /
WKPCFG
DSPI D peripheral chip select
Reaction channel 5A
GPIO
I/O
ETPUA20
IRQ[8]
RCH0_B
FR_A_TX
GPIO[134]
eTPU A channel
P
0001
0010
0100
1000
0000
I/O
I
O
O
I/O
VDDEH1 /
Slow
— /
WKPCFG
— /
WKPCFG
External interrupt request
Reaction channel 0B
FlexRay transmit data channel A
GPIO
A1
A2
A3
G
ETPUA21
IRQ[9]
RCH0_C
FR_A_RX
GPIO[135]
eTPU A channel
P
0001
0010
0100
1000
0000
135
I/O
I
O
I
VDDEH1 /
Slow
— /
WKPCFG
— /
WKPCFG
34
G4
N4
External interrupt request
Reaction channel 0C
FlexRay receive channel A
GPIO
A1
A2
A3
G
I/O
ETPUA22
IRQ[10]
ETPUA17_O
eTPU A channel
P
A1
A2
G
001
010
100
000
136
137
I/O
I
O
VDDEH1 /
Slow
— /
WKPCFG
— /
WKPCFG
32
30
H2
H1
N3
M1
External interrupt request
eTPU A channel (output only)
GPIO
GPIO[136]
I/O
ETPUA23
IRQ[11]
ETPUA21_O
FR_A_TX_EN
GPIO[137]
eTPU A channel
P
0001
0010
0100
1000
0000
I/O
I
O
O
I/O
VDDEH1 /
Slow
— /
WKPCFG
— /
WKPCFG
External interrupt request
eTPU A channel (output only)
FlexRay ch. A transmit enable
GPIO
A1
A2
A3
G
ETPUA24
IRQ[12]
DSPI_C_SCK_LVDS
GPIO[138]
eTPU A channel
P
A1
A2
G
001
010
100
000
138
139
140
I/O
I
O
VDDEH1 /
Slow +
LVDS
— /
WKPCFG
— /
WKPCFG
28
27
26
G1
G3
F3
M2
M3
L2
External interrupt request
LVDS negative DSPI clock
GPIO
I/O
ETPUA25
IRQ[13]
DSPI_C_SCK_LVDS+
GPIO[139]
eTPU A channel
P
A1
A2
G
001
010
100
000
I/O
I
O
VDDEH1 /
Medium +
LVDS
— /
WKPCFG
— /
WKPCFG
External interrupt request
LVDS positive DSPI clock
GPIO
I/O
ETPUA26
IRQ[14]
eTPU A channel
External interrupt request
P
A1
A2
G
001
010
100
000
I/O
I
O
VDDEH1 /
Slow +
LVDS
— /
WKPCFG
— /
WKPCFG
DSPI_C_SOUT_LVDS LVDS negative DSPI data out
GPIO[140] GPIO
I/O
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
ETPUA27
IRQ[15]
DSPI_C_SOUT_LVDS+ LVDS positive DSPI data out
eTPU A channel
External interrupt request
P
0001
0010
0100
1000
0000
141
I/O
I
O
O
I/O
VDDEH1 /
Slow +
LVDS
— /
WKPCFG
— /
WKPCFG
25
G2
L1
A1
A2
A3
G
DSPI_B_SOUT
GPIO[141]
DSPI B data output
GPIO
ETPUA28
DSPI_C_PCS[1]
RCH5_B
eTPU A channel
P
A1
A2
G
001
010
100
000
142
143
144
145
I/O
O
O
VDDEH1 /
Medium
— /
WKPCFG
— /
WKPCFG
24
23
22
21
F1
F2
E1
E2
M4
L3
L4
K1
DSPI C peripheral chip select
Reaction channel 5B
GPIO
GPIO[142]
I/O
ETPUA29
DSPI_C_PCS[2]
RCH5_C
eTPU A channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH1 /
Medium
— /
WKPCFG
— /
WKPCFG
DSPI C peripheral chip select
Reaction channel 5C
GPIO
GPIO[143]
I/O
ETPUA30
eTPU A channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH1 /
Medium
— /
WKPCFG
— /
WKPCFG
DSPI_C_PCS[3]
ETPUA11_O
GPIO[144]
DSPI C peripheral chip select
eTPU A channel (output only)
GPIO
I/O
ETPUA31
eTPU A channel
P
001
010
100
000
I/O
O
O
VDDEH1 /
Medium
— /
WKPCFG
— /
WKPCFG
DSPI_C_PCS[4]
ETPUA13_O
GPIO[145]
DSPI C peripheral chip select
eTPU A channel (output only)
GPIO
A1
A2
G
I/O
eMIOS
EMIOS0
eMIOS channel
P
A1
A2
G
001
010
100
000
179
I/O
O
O
VDDEH4 /
Slow
— / Up
— / Up
63
T4
AA12
ETPUA0_O
ETPUA25_O
GPIO[179]
eTPU A channel (output only)
eTPU A channel (output only)
GPIO
I/O
EMIOS1
ETPUA1_O
GPIO[180]
eMIOS channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
180
181
I/O
O
I/O
VDDEH4 /
Slow
— / Up
— / Up
— / Up
— / Up
64
65
T5
N7
W13
Y13
EMIOS2
ETPUA2_O
RCH2_B
GPIO[181]
eMIOS channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH4 /
Slow
eTPU A channel (output only)
Reaction channel 2B
GPIO
I/O
EMIOS3
ETPUA3_O
GPIO[182]
eMIOS channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
182
183
I/O
O
I/O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
66
67
R6
R5
AA13
AB13
EMIOS4
ETPUA4_O
RCH2_C
eMIOS channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
eTPU A channel (output only)
Reaction channel 2C
GPIO
GPIO[183]
I/O
EMIOS5
ETPUA5_O
GPIO[184]
eMIOS channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
184
I/O
O
I/O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
—
—
Y14
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
EMIOS6
ETPUA6_O
GPIO[185]
eMIOS channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
185
I/O
O
I/O
VDDEH4 /
Slow
— / Down
— / Down
68
P7
AA14
EMIOS7
ETPUA7_O
GPIO[186]
eMIOS channel
eTPU A channel (output only)
GPIO
P
A1
G
01
10
00
186
187
I/O
O
I/O
VDDEH4 /
Slow
— / Down
— / Up
— / Down
— / Up
69
70
—
AB14
W15
EMIOS8
eMIOS channel
eTPU A channel (output only)
eSCI B transmit
GPIO
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH4 /
Slow
P8
ETPUA8_O
SCI_B_TX
GPIO[187]
I/O
EMIOS9
eMIOS channel
eTPU A channel (output only)
eSCI B receive
GPIO
P
A1
A2
G
001
010
100
000
188
189
190
191
I/O
O
I
VDDEH4 /
Slow
— / Up
— / Up
71
73
75
76
R7
N8
Y15
ETPUA9_O
SCI_B_RX
GPIO[188]
I/O
EMIOS10
DSPI_D_PCS[3]
RCH3_B
eMIOS channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH4 /
Medium
— /
WKPCFG
— /
WKPCFG
AA15
AB15
AB16
DSPI D peripheral chip select
Reaction channel 3B
GPIO
GPIO[189]
I/O
EMIOS11
DSPI_D_PCS[4]
RCH3_C
eMIOS channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH4 /
Medium
— /
WKPCFG
— /
WKPCFG
R8
DSPI D peripheral chip select
Reaction channel 3C
GPIO
GPIO[190]
I/O
EMIOS12
eMIOS channel
P
A1
A2
G
001
010
100
000
I/O
O
O
VDDEH4 /
Medium
— /
WKPCFG
— /
WKPCFG
N10
DSPI_C_SOUT
ETPUA27_O
GPIO[191]
DSPI C data output
eTPU A channel (output only)
GPIO
I/O
EMIOS13
DSPI_D_SOUT
GPIO[192]
eMIOS channel
DSPI D data output
GPIO
P
A1
G
01
10
00
192
193
I/O
O
I/O
VDDEH4 /
Medium
— /
WKPCFG
— /
WKPCFG
77
78
T8
R9
AA16
Y16
EMIOS14
IRQ[0]
ETPUA29_O
GPIO[193]
eMIOS channel
P
A1
A2
G
001
010
100
000
I/O
I
O
VDDEH4 /
Slow
— / Down
— / Down
— / Down
— / Down
External interrupt request
eTPU A channel (output only)
GPIO
I/O
EMIOS15
IRQ[1]
GPIO[194]
eMIOS channel
External interrupt request
GPIO
P
A1
G
01
10
00
194
I/O
I
I/O
VDDEH4 /
Slow
79
T9
W16
EMIOS16
GPIO[195]
eMIOS channel
GPIO
P
G
01
00
195
196
197
198
I/O
I/O
VDDEH4 /
Slow
— / Up
— / Up
— / Up
— / Up
— / Up
— / Up
—
—
—
—
—
—
—
—
W17
Y17
EMIOS17
GPIO[196]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4 /
Slow
EMIOS18
GPIO[197]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4 /
Slow
AA17
AB17
EMIOS19
GPIO[198]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
208
324
EMIOS20
GPIO[199]
eMIOS channel
GPIO
P
G
01
00
199
200
201
202
203
204
I/O
I/O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
—
—
AB18
EMIOS21
GPIO[200]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4 /
Slow
— /
WKPCFG
— /
WKPCFG
—
—
80
—
—
—
—
AA18
Y18
EMIOS22
GPIO[201]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4 /
Slow
— / Down
— / Down
— / Down
— / Down
— / Down
— / Down
— / Down
— / Down
EMIOS23
GPIO[202]
eMIOS channel
GPIO
P
G
01
00
I/O
I/O
VDDEH4 /
Slow
R11
—
W18
A15
15
EMIOS14
GPIO[203]
eMIOS channel
GPIO
P
G
01
00
O
I/O
VDDEH7 /
Slow
15
EMIOS15
GPIO[204]
eMIOS channel
GPIO
P
G
01
00
O
I/O
VDDEH7 /
Slow
—
D14
Clock Synthesizer
XTAL
Crystal oscillator output
Crystal oscillator input
System clock output
P
P
P
P
01
01
01
01
—
—
O
I
VDDEH6 /
Analog
—
—
—
—
—
93
92
—
—
P16
N16
—
V22
U22
AB9
W10
EXTAL
VDDEH6 /
Analog
—
CLKOUT
ENGCLK
229
214
O
O
VDDE12 /
Fast
CLKOUT
ENGCLK
Engineering clock output
VDDE12 /
Fast
T14
Power / Ground
VDDREG
VRCCTL
Voltage regulator supply
—
—
—
—
I
5 V
—
I / —
VDDREG
VRCCTL
10
11
K16
N14
F4
F2
Voltage regulator control output
O
O / —
VRC3317
Internal regulator output
—
—
—
—
O
I
3.3 V
3.3 V
I/O / —
VRC33
13
A15,
D1, N6, M19,
N12 P11
B1,
Input for external 3.3 V supply
VDDA
eQADC high reference voltage
eQADC ground/low reference voltage
FMPLL supply voltage
—
—
—
—
—
—
—
—
I
I
I
I
5 V
—
I / —
I / —
I / —
I / —
VDDA
VSSA
6
7
A4, B11
E3, A6
VSSA
A5, A11
R16
A7, E2
W22
E4
VDDPLL
VSTBY
1.2 V
VDDPLL
VSTBY
91
12
Power supply for standby RAM
0.9 V – 6 V
C1
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
208 324
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
VDD
Core supply for input or decoupling
—
—
I
1.2 V
I / —
VDD
33, 45, 62, B1, B16, A2, A20,
103, 132,
C2, D3, A21, B3,
E4, N5, C4, C22,
P4, P13, D5, W20,
R3, R14, Y4, Y21,
T2, T15 AA3, AA22
149, 176
VDDE12
VDDE5
External supply input for calibration bus
interfaces
—
—
—
—
I
I
3.0 V – 3.6 V
3.0 V – 3.6 V
I / —
I / —
VDDE12
VDDE5
—
—
—
—
External supply input for ENGCLK and
CLKOUT
T13
N11, W5,
W8
VDDE-EH
VDDEH1A
VDDEH1B
External supply for EBI interfaces
I/O supply input
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
I
3.0 V – 5.0 V
3.3 V – 5.0 V
3.3 V – 5.0 V
3.3 V – 5.0 V
3.3 V – 5.0 V
3.3 V – 5.0 V
3.3 V – 5.0 V
3.3 V – 5.0 V
I / —
I / —
I / —
I / —
I / —
I / —
I / —
I / —
VDDE-EH
—
31
41
—
—
55
74
—
—
—
—
K4
—
—
—
N9
R3, V2
—
18
18
18
VDDEH1A
VDDEH1B
18
I/O supply input
—
18
18
VDDEH1AB
I/O supply input
VDDEH1AB
K4
—
19
19
VDDEH4
I/O supply input
VDDEH4
19
19
19
VDDEH4A
VDDEH4B
VDDEH4AB
I/O supply input
VDDEH4A
VDDEH4B
—
19
I/O supply input
—
19
19
I/O supply input
VDDEH4AB
W14,
AA19
20
20
VDDEH6
I/O supply input
I/O supply input
I/O supply input
I/O supply input
—
—
—
—
—
—
—
—
I
I
I
I
3.3 V – 5.0 V
3.3 V – 5.0 V
3.3 V – 5.0 V
3.3 V – 5.0 V
I / —
I / —
I / —
I / —
VDDEH6
—
95
—
—
—
—
20
20
20
VDDEH6A
VDDEH6B
VDDEH6AB
VDDEH6A
VDDEH6B
20
110
—
—
—
20
20
VDDEH6AB
F13
M22, U19
Table 3. MPC5642A signal properties (continued)
8
Status
Package pin No.
208 324
PCR
PA
field
6
I/O
type
Voltage /
1
2
3
5
Name
Function
P / A / G
PCR
7
Pad type
4
During reset
After reset
176
21
VDDEH7
I/O supply input
—
—
I
3.3 V – 5.0 V
I / —
VDDEH7
—
D12
B22, C21,
D15, D20,
E19, F19,
H19, J14
21
VDDEH7A
VDDEH7B
VSS
I/O supply input
I/O supply input
Ground
—
—
—
—
—
—
I
I
I
3.3 V – 5.0 V
3.3 V – 5.0 V
—
I / —
I / —
I / —
VDDEH7A
VDDEH7B
VSS
125
138
—
—
—
—
21
15, 29, 43, A1, A16, A1, A22,
57, 72, 90, B2, B15, B2, B21,
94, 96,
C3, C14, C3, C20,
108, 115, D4, D13, D4, D17,
127, 133,
140
G7, G8, D19, F21,
G9, G10, H21, J9,
H7, H8, J10, J11,
H9, H10, J12, J13,
J7, J8, J9, K9, K10,
J10, K7, K11, K12,
K8, K9, K13, K14,
K10, M16, L9, L10,
N4, N13, L11, L12,
P3, P14, L13, L14,
R2, R15, L21, M11,
T1, T16 M12, M13,
M14, N9,
N10, N12,
N13, N14,
N21, P9,
P10, P12,
P13, P14,
T19, T21,
T22, W4,
Y3, Y20,
AA21,
AB1, AB22
1
2
The suffix “_O” identifies an output-only eTPU channel
For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary
function or GPIO is done in the SIU except where explicitly noted. See the Signal details table for a description of each signal.
3
The P/A/G column indicates the position a signal occupies in the muxing order for a pin—Primary, Alternate 1, Alternate 2, Alternate 3, or GPIO. Signals are
selected by setting the PA field value in the appropriate PCR register in the SIU module. The PA field values are as follows: P - 0b0001, A1 - 0b0010, A2 -
0b0100, A3 - 0b1000, or G - 0b0000. Depending on the register, the PA field size can vary in length. For PA fields having fewer than four bits, remove the
appropriate number of leading zeroes from these values.
4
5
The Pad Configuration Register (PCR) PA field is used by software to select pin function.
Values in the PCR column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number. For
example, PCR[190] refers to the SIU register named SIU_PCR190.
6
The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V
range (10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/ 10%).
7
8
See Table 4 for details on pad types.
The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. Terminology is O (output),
I (input), Up (weak pull up enabled), Down (weak pull down enabled), Low (output driven low), High (output driven high). A dash for the function in this column
denotes that both the input and output buffer are turned off. The signal name to the left or right of the slash indicates the pin is enabled.
9
When used as ETRIG, this pin must be configured as an input. For GPIO it can be configured either as an input or output.
10 Maximum frequency is 50 kHz
11 PCR219 controls two different pins: MCKO and GPIO[219]. Please refer to Pad Configuration Register 219 section in SIU chapter of device reference manual
for details.
12 On 176 LQFP and 208 MAPBGA packages, this pin is tied low internally.
13 These pins are selected by asserting JCOMP and configuring the NPC. SIU values have no effect on the function of this pin once enabled.
14 The BAM uses this pin to select if auto baud rate is on or off.
15 Output only
16 This signal name is used to support legacy naming.
17 Do not use VRC33 to drive external circuits.
18 VDDEH1A, VDDEH1B and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy
naming, however they should be considered as the same signal in this document.
19 VDDEH4, VDDEH4A, VDDEH4B and VDDEH4AB are shorted together in all production packages. The separation of the signal names is present to support
legacy naming, however they should be considered as the same signal in this document.
20 VDDEH6, VDDEH6A, VDDEH6B and VDDEH6AB are shorted together in all production packages. The separation of the signal names is present to support
legacy naming, however they should be considered as the same signal in this document.
21 VDDEH7, VDDEH7A and VDDE7B are shorted together in all production packages. The separation of the signal names is present to support legacy naming,
however they should be considered as the same signal in this document.
Pinout and signal description
Table 4. Pad types
Name
Pad Type
I/O Voltage Range
Slow
Medium
Fast
pad_ssr_hv
pad_msr_hv
pad_fc
3.0V - 5.5 V
3.0 V - 5.5 V
3.0 V - 3.6 V
MultiV1,2
pad_multv_hv
3.0 V - 5.5 V (high swing mode)
3.0 V - 3.6 V (low swing mode)
Analog
LVDS
pad_ae_hv
pad_lo_lv
0.0 - 5.5 V
—
1
2
Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function
is selected, otherwise they are high swing.
VDDEH7 supply cannot be below 4.5 V when in low-swing mode.
2.5
Signal details
Table 5. Signal details
Module or function
Signal
Description
CLKOUT
ENGCLK
EXTAL
Clock Generation
Clock Generation
Clock Generation
MPC5642A clock output for the calibration bus interface
Clock for external ASIC devices
Input pin for an external crystal oscillator or an external clock
source based on the value driven on the PLLREF pin at reset
PLLREF
Clock Generation
Reset/Configuration
PLLREF is used to select whether the oscillator operates in
xtal mode or external reference mode from reset. PLLREF = 0
selects external reference mode. On the 324 TEPBGA
package, PLLREF is bonded to the ball used for PLLCFG[0]
for compatibility with MPC55xx devices.
For the 176-pin QFP and 208-ball BGA packages:
0: External reference clock is selected
1: XTAL oscillator mode is selected
For the 324-ball BGA package:
If RSTCFG is 0:
0: External reference clock is selected
1: XTAL oscillator mode is selected
If RSTCFG is 1, XTAL oscillator mode is selected.
Crystal oscillator input
XTAL
Clock Generation
DSPI
DSPI_B_SCK_LVDS
LVDS pair used for DSPI_B TSB mode transmission
DSPI_B_SCK_LVDS+
DSPI_B_SOUT_LVDS DSPI
LVDS pair used for DSPI_B TSB mode transmission
DSPI_B_SOUT_LVDS+
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
49
Pinout and signal description
Signal
Table 5. Signal details (continued)
Module or function
DSPI
Description
DSPI_C_SCK_LVDS
DSPI_C_SCK_LVDS+
LVDS pair used for DSPI_C TSB mode transmission
LVDS pair used for DSPI_C TSB mode transmission
DSPI_C_SOUT_LVDS DSPI
DSPI_C_SOUT_LVDS+
DSPI_B_PCS[0]
DSPI_C_PCS[0]
DSPI_D_PCS[0]
DSPI_B – DSPI_D
Peripheral chip select when device is in master mode—slave
select when used in slave mode
DSPI_B_PCS[1:5]
DSPI_C_PCS[1:5]
DSPI_D_PCS[1:5]
DSPI_B – DSPI_D
DSPI_B – DSPI_D
DSPI_B – DSPI_D
DSPI_B – DSPI_D
Peripheral chip select when device is in master mode—not
used in slave mode
DSPI_B_SCK
DSPI_C_SCK
DSPI_D_SCK
DSPI clock—output when device is in master mode; input
when in slave mode
DSPI_B_SIN
DSPI_C_SIN
DSPI_D_SIN
DSPI data in
DSPI_B_SOUT
DSPI_C_SOUT
DSPI_D_SOUT
DSPI data out
eMIOS[0:23]
AN[0:39]
eMIOS
eQADC
eQADC
eMIOS I/O channels
Single-ended analog inputs for analog-to-digital converter
AN[0:7]/DAN+
Differential analog input pair for analog-to-digital converter
with pull-up/pull-down functionality
AN[0:7]/DAN
eQADC
Differential analog input pair for analog-to-digital converter
with pull-up/pull-down functionality
FCK
eQADC
eQADC
eQADC free running clock for eQADC SSI
MA[0:2]
These three control bits are output to enable the selection for
an external Analog Mux for expansion channels.
REFBYPC
SDI
eQADC
Bypass capacitor input
Serial data in
eQADC
SDO
eQADC
Serial data out
SDS
eQADC
Serial data select
VRH
eQADC
Voltage reference high input
Voltage reference low input
eSCI receive
VRL
eQADC
SCI_A_RX
SCI_B_RX
SCI_C_RX
eSCI_A – eSCI_C
SCI_A_TX
SCI_B_TX
SCI_C_TX
eSCI_A – eSCI_C
eTPU
eSCI transmit
ETPU_A[0:31]
eTPU I/O channel
MPC5642A Microcontroller Data Sheet, Rev. 3.1
50
Freescale Semiconductor
Pinout and signal description
Table 5. Signal details (continued)
Module or function
eTPU2
Signal
RCH0_[A:C]
RCH1_[A:C]
RCH2_[A:C]
RCH3_[A:C]
RCH4_[A:C]
RCH5_[A:C]
Description
eTPU2 reaction channels. Used to control external actuators,
e.g., solenoid control for direct injection systems and valve
control in automatic transmissions
Reaction Module
TCRCLKA
eTPU2
Input clock for TCR time base
CAN_A_TX
CAN_B_TX
CAN_C_TX
FlexCAN_A – FlexCAN_C FlexCAN transmit
CAN_A_RX
CAN_B_RX
CAN_C_RX
FlexCAN_A – FlexCAN_C FlexCAN receive
FR_A_RX
FR_B_RX
FlexRay
FlexRay
FlexRay
FlexRay receive (Channels A, B)
FR_A_TX_EN
FR_B_TX_EN
FlexRay transmit enable (Channels A, B)
FlexRay transmit (Channels A, B)
FR_A_TX
FR_B_TX
JCOMP
TCK
JTAG
JTAG
JTAG
JTAG
JTAG
Nexus
Enables the JTAG TAP controller
Clock input for the on-chip test logic
TDI
Serial test instruction and data input for the on-chip test logic
Serial test data output for the on-chip test logic
Controls test mode operations for the on-chip test logic
TDO
TMS
EVTI
EVTI is an input that is read on the negation of RESET to
enable or disable the Nexus Debug port. After reset, the EVTI
pin is used to initiate program synchronization messages or
generate a breakpoint.
EVTO
Nexus
Nexus
Nexus
Output that provides timing to a development tool for a single
watchpoint or breakpoint occurrence
MCKO
MCKO is a free running clock output to the development tools
which is used for timing of the MDO and MSEO signals.
MDO[0:11]
Trace message output to development tools. This pin also
indicates the status of the crystal oscillator clock following a
power-on reset, when MDO[0] is driven high until the crystal
oscillator clock achieves stability and is then negated.
MSEO[0:1]
RDY
Nexus
Nexus
Output pin—Indicates the start or end of the variable length
message on the MDO pins
Nexus Ready Output (RDY)—Indicates to the development
tools that data is ready to be read from or written to the Nexus
read/write access registers.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
51
Pinout and signal description
Table 5. Signal details (continued)
Module or function
SIU – Configuration
Signal
Description
BOOTCFG[0:1]
Two BOOTCFG signals are implemented in MPC5642A
MCUs.
The BAM program uses the BOOTCFG0 bit to determine
where to read the reset configuration word, and whether to
initiate a FlexCAN or eSCI boot.
The BOOTCFG1 pin is sampled during the assertion of the
RSTOUT signal, and the value is used to update the RSR and
the BAM boot mode.
See reference manual section “Reset Configuration Half Word
(RCHW)” for details on the RCHW. The table “Boot Modes” in
reference manual section “BAM Program Operation” defines
the boot modes specified by the BOOTCFG1 pin.
The following values are for BOOTCFG[0:1}:
00: Boot from internal flash memory
01: FlexCAN/eSCI boot
10: Boot from external memory using calibration bus
11: Reserved
Note: For the 176-pin QFP and 208-ball BGA packages
BOOTCFG[0] is always 0 since the EBI interface is not
available.
WKPCFG
SIU – Configuration
The WKPCFG pin is applied at the assertion of the internal
reset signal (assertion of RSTOUT), and is sampled four clock
cycles before the negation of the RSTOUT pin.
The value is used to configure whether the eTPU and eMIOS
pins are connected to internal weak pull up or weak pull down
devices after reset. The value latched on the WKPCFG pin at
reset is stored in the Reset Status Register (RSR), and is
updated for all reset sources except the Debug Port Reset and
Software External Reset.
0: Weak pulldown applied to eTPU and eMIOS pins at reset
1: Weak pullup applied to eTPU and eMIOS pins at reset
ETRIG[2:3]
SIU – eQADC Triggers
SIU – eQADC Triggers
External signal eTRIGx triggers eQADC CFIFOx
External signal eTRIGx triggers eQADC CFIFOx
GPIO[206] ETRIG0
(Input)
GPIO[207] ETRIG1
(Input)
SIU – eQADC Triggers
External signal eTRIGx triggers eQADC CFIFOx
IRQ[0:5]
IRQ[7:15]
SIU – External Interrupts The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX
Select Register 1 is used to select the IRQ[0:15] pins as inputs
to the IRQs.
See reference manual section “External IRQ Input Select
Register (SIU_EIISR)” for more information.
NMI
SIU – External Interrupts Non-Maskable Interrupt
MPC5642A Microcontroller Data Sheet, Rev. 3.1
52
Freescale Semiconductor
Pinout and signal description
Table 5. Signal details (continued)
Signal
GPIO[12:17]
GPIO[75:110]
GPIO[113:145]
GPIO[179:204]
GPIO[206:213]
GPIO[219]
Module or function
Description
SIU – GPIO
Configurable general purpose I/O pins. Each GPIO input and
output is separately controlled by an 8-bit input (GPDI) or
output (GPDO) register. Additionally, each GPIO pin is
configured using a dedicated SIU_PCR register.
The GPIO pins are generally multiplexed with other I/O pin
functions.
GPIO[244:245]
See the following reference manual sections for more
information:
• “Pad Configuration Registers (SIU_PCR)”
• “GPIO Pin Data Output Registers (SIU_GPDO0_3 –
SIU_GPDO412_413)”
• “GPIO Pin Data Input Registers (SIU_GPDI0_3 –
SIU_GPDI_232)”
RESET
SIU – Reset
SIU – Reset
SIU – Reset
The RESET pin is an active low input. The RESET pin is
asserted by an external device during a power-on or external
reset. The internal reset signal asserts only if the RESET pin
asserts for 10 clock cycles. Assertion of the RESET pin while
the device is in reset causes the reset cycle to start over.
The RESET pin has a glitch detector which detects spikes
greater than two clock cycles in duration that fall below the
switch point of the input buffer logic of the VDDEH input pins.
The switch point lies between the maximum VIL and minimum
VIH specifications for the VDDEH input pins.
RSTCFG
Used to enable or disable the PLLREF and the
BOOTCFG[0:1] configuration signals.
0: Get configuration information from BOOTCFG[0:1] and
PLLREF
1: Use default configuration of booting from internal flash with
crystal clock source
Note: For the 176-pin QFP and 208-ball BGA packages
RSTCFG is always 0, so PLLREF and BOOTCFG
signals are used.
RSTOUT
The RSTOUT pin is an active low output that uses a push/pull
configuration. The RSTOUT pin is driven to the low state by
the MCU for all internal and external reset sources. There is a
delay between initiation of the reset and the assertion of the
RSTOUT pin. See reference manual section “RSTOUT” for
details.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
53
Pinout and signal description
Power segment
Table 6. Power/ground segmentation
I/O pins powered by segment
Voltage
VDDE5
3.0 V – 3.6 V DATA[0:15], CLKOUT, ENGCLK
VDDE12
3.0 V – 3.6 V CAL_CS0, CAL_CS2, CAL_CS3, CAL_ADDR[12:30], CAL_DATA[0:15],
CAL_RD_WR, CAL_WE0, CAL_WE1, CAL_OE, CAL_TS
VDDE-EH
VDDEH1
VDDEH4
VDDEH6
3.0 V – 5.5 V FR_A_TX, FR_A_TX_EN, FR_A_RX, FR_B_TX, FR_B_TX_EN, FR_B_RX
3.3 V – 5.5 V ETPUA[10:31]
3.3 V – 5.5 V EMIOS[0:23], TCRCLKA, ETPUA[0:9]
3.3 V – 5.5 V RESET, RSTOUT, PLLREF, PLLCFG1, RSTCFG, BOOTCFG0, BOOTCFG1,
WKPCFG, CAN_A_TX, CAN_A_RX, CAN_B_TX, CAN_B_RX, CAN_C_TX,
CAN_C_RX, SCI_A_TX, SCI_A_RX, SCI_B_TX, SCI_B_RX, SCI_C_TX,
SCI_C_RX, DSPI_B_SCK, DSPI_B_SIN, DSPI_B_SOUT, DSPI_B_PCS[0:5],
EXTAL, XTAL
VDDEH7
3.3 V – 5.5 V EMIOS14, EMIOS15, GPIO[98:99], GPIO[203:204], GPIO[206], GPIO[207],
GPIO[219], EVTI, EVTO, MDO[4:11], MSEO0, MSEO1, RDY, TCK, TDI, TDO,
TMS, JCOMP, DSPI_A_SCK, DSPI_A_SIN, DSPI_A_SOUT, DSPI_A_PCS[0:1],
DSPI_A_PCS[4:5], AN12-SDS, AN13-SDO, AN14-SDI, AN15-FCK
VDDA
5.0 V
3.3 V
AN[0:11], AN[16:39], VRH, VRL, REFBYBC
MCKO, MDO[0:3]
VRC33
Other power segments
VDDREG
VRCCTL
VDDPLL
VSTBY
VSS
5.0 V
—
—
—
—
—
—
1.2 V
0.9 V – 6.0 V
—
MPC5642A Microcontroller Data Sheet, Rev. 3.1
54
Freescale Semiconductor
Electrical characteristics
3
Electrical characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC5642A series of MCUs.
The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon
these specifications will be met. Finalized specifications will be published after complete characterization and device
qualifications have been completed.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
3.1
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 7 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 7. Parameter classifications
Classification tag
Tag description
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
55
Electrical characteristics
3.2
Maximum ratings
1
Table 8. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VDD
VFLASH
VSTBY
VDDPLL
VRC33
VDDA
SR 1.2 V core supply voltage2
SR Flash core voltage3,4
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
1.32
3.6
V
V
V
V
V
V
V
V
V
SR SRAM standby voltage5
SR Clock synthesizer voltage3
SR Voltage regulator control input voltage4
SR Analog supply voltage5
SR I/O supply voltage4,6
6.0
1.32
3.6
Reference to VSSA
5.5
VDDE
3.6
VDDEH
VIN
SR I/O supply voltage5,7
5.5
SR DC input voltage8
VDDEH powered I/O pads
–1.010
VDDEH +
0.3 V9
VDDE powered I/O pads
–1.014
VDDE +
0.3 V10
VDDA powered I/O pads
Reference to VRL
–1.0
–0.3
–0.3
–0.1
–0.3
–0.3
–0.1
–3
5.5
5.5
5.5
0.1
5.5
0.3
0.1
3
VDDREG
VRH
SR Voltage regulator supply voltage
SR Analog reference high voltage
V
V
V
SS – VSSA SR VSS differential voltage
VRH – VRL SR VREF differential voltage
VRL – VSSA SR VRL to VSSA differential voltage
SSPLL – VSS SR VSSPLL to VSS differential voltage
V
V
V
V
V
IMAXD
IMAXA
TJ
SR Maximum DC digital input current11
Per pin, applies to all digital
pins
mA
SR Maximum DC analog input current12 Per pin, applies to all analog
pins
—
513
mA
oC
SR Maximum operating temperature
range — die junction temperature
–40.0
150.0
TSTG
TSDR
MSL
SR Storage temperature range
SR Maximum solder temperature14
SR Moisture sensitivity level15
–55
—
150
260
3
°C
°C
—
—
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
2
3
Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V + 10%
The VFLASH supply is connected to VRC33 in the package substrate. This specification applies to calibration package
devices only.
4
5
Allowed 5.3 V for 10 hours cumulative time, remaining time at 3.3 V + 10%
Allowed 5.9 V for 10 hours cumulative time, remaining time at 5 V + 10%
MPC5642A Microcontroller Data Sheet, Rev. 3.1
56
Freescale Semiconductor
Electrical characteristics
6
7
8
All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH
.
Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met.
AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of
60 hours over the complete lifetime of the device (injection current not limited for this duration).
9
Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDEH supplies, if
the maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage
specifications.
10 Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if
the maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage
specifications.
11 Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
12 Total injection current for all analog input pins must not exceed 15 mA.
13 Lifetime operation at these specification limits is not guaranteed.
14 Solder profile per IPC/JEDEC J-STD-020D
15 Moisture sensitivity per JEDEC test method A112
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
57
Electrical characteristics
3.3
Thermal characteristics
1
Table 9. Thermal characteristics for 176-pin LQFP
Symbol
C
Parameter
Conditions
Value Unit
RJA CC D Junction-to-ambient, natural convection2
RJA CC D Junction-to-ambient, natural convection2
RJMA CC D Junction-to-moving-air, ambient2
CC D
Single-layer board – 1s
38 °C/W
31 °C/W
30 °C/W
25 °C/W
20 °C/W
Four-layer board – 2s2p
at 200 ft./min., single-layer board – 1s
at 200 ft./min., four-layer board – 2s2p
RJB CC D Junction-to-board3
RJCtop CC D Junction-to-case4
5
2
°C/W
°C/W
JT CC D Junction-to-package top, natural convection5
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3
4
5
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
1,
Table 10. Thermal characteristics for 208-pin MAPBGA
Symbol
C
Parameter
Conditions
Value Unit
RJA CC D Junction-to-ambient, natural convection2
CC D
Single layer board – 1s3
39 °C/W
24 °C/W
31 °C/W
20 °C/W
13 °C/W
Four layer board – 2s2p4
RJMA CC D Junction-to-moving-air, ambient2
CC D
at 200 ft./min., single-layer board – 1s4
at 200 ft./min., four-layer board – 2s2p
Four-layer board – 2s2p
RJB CC D Junction-to-board5
RJC CC D Junction-to-case6
6
2
°C/W
°C/W
JT CC D Junction-to-package top natural convection7
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
3
4
5
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal
Per JEDEC JESD51-6 with the board horizontal
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
6
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
58
Freescale Semiconductor
Electrical characteristics
7
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.
1
Table 11. Thermal characteristics for 324-pin TEPBGA
Symbol
C
Parameter
Conditions
Value Unit
RJA CC D Junction-to-ambient, natural convection2
Single-layer board – 1s
29 °C/W
19 °C/W
23 °C/W
16 °C/W
10 °C/W
CC D
Four-layer board – 2s2p
RJMA CC D Junction-to-moving-air, ambient2
CC D
at 200 ft./min., single-layer board – 1s
at 200 ft./min., four-layer board – 2s2p
RJB CC D Junction-to-board3
RJCtop CC D Junction-to-case4
7
2
°C/W
°C/W
JT CC D Junction-to-package top, natural convection5
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3
4
5
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
3.3.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, T , can be obtained from Equation 1:
J
T = T + (R
* P )
Eqn. 1
J
A
JA
D
where:
T = ambient temperature for the package (°C)
A
R
= junction-to-ambient thermal resistance (°C/W)
JA
P = power dissipation in the package (W)
D
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a
four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance
is not a constant. The thermal resistance depends on the:
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
59
Electrical characteristics
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit
board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components that are well separated
2
Overall power dissipation on the board is less than 0.02 W/cm
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the
ambient temperature varies widely within the application. For many natural convection and especially closed-box applications,
the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the
device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using Equation 2:
T = T + (R
* P )
Eqn. 2
J
B
JB
D
where:
T = board temperature for the package perimeter (°C)
B
R
= junction-to-board thermal resistance (°C/W) per JESD51-8S
JB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction
temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to
a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal
resistance:
R
= R
+ R
CA
Eqn. 3
JA
JC
where:
R
R
R
= junction-to-ambient thermal resistance (°C/W)
= junction-to-case thermal resistance (°C/W)
= case to ambient thermal resistance (°C/W)
JA
JC
CA
R
is device-related and is not affected by other factors. The thermal environment can be controlled to change the
JC
case-to-ambient thermal resistance, R
. For example, change the air flow around the device, add a heat sink, change the
CA
mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding
the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat
sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the
junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the
thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple
estimations and for computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization
parameter ( ) to determine the junction temperature by measuring the temperature at the top center of the package case using
JT
Equation 4:
T = T + ( x P )
Eqn. 4
J
T
JT
D
where:
T = thermocouple temperature on top of the package (°C)
T
MPC5642A Microcontroller Data Sheet, Rev. 3.1
60
Freescale Semiconductor
Electrical characteristics
= thermal characterization parameter (°C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests
on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from
the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling
effects of the thermocouple wire.
References:
•
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
USA
Phone (+1) 408-943-6900
•
MIL-SPEC and EIA/JESD (JEDEC) specifications available from Global Engineering Documents (phone (+1)
800-854-7179 or (+1) 303-397-7956)
•
•
JEDEC specifications available on the Web at http://www.jedec.org
C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
•
•
G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications”, Electronic
Packaging and Production, pp. 53-58, March 1998.
B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
3.4
EMI (electromagnetic interference) characteristics
1
Table 12. EMI testing specifications
Level
(max)
Symbol
Parameter
Conditions
VDD = 5.25 V;
f
OSC/fBUS
Frequency
Unit
VRE_TEM Radiated emissions,
electric field
16 MHz crystal
40 MHz bus
No PLL frequency
modulation
150 kHz–50 MHz
50–150 MHz
150–500 MHz
500–1000 MHz
IEC Level
20
20
26
26
K
dBµV
TA = +25 °C
150 kHz–30 MHz —
RBW 9 kHz, step size
5 kHz
30 MHz–1 GHz —
RBW 120 kHz, step
size 80 kHz
—
—
SAE Level
3
16 MHz crystal
40 MHz bus
2% PLL frequency
modulation
150 kHz–50 MHz
50–150 MHz
150–500 MHz
500–1000 MHz
IEC Level
13
13
11
13
L
dBµV
—
—
SAE Level
2
1
EMI testing and I/O port waveforms per standard IEC 61967-2.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
61
Electrical characteristics
3.5
Electrostatic discharge (ESD) characteristics
1,2
Table 13. ESD ratings
Symbol
SR ESD for Human Body Model (HBM)
R1 SR HBM circuit description
Parameter
Conditions
Value Unit
—
—
—
—
2000
1500
100
500
750
1
V
C
SR
pF
V
—
SR ESD for Field Induced Charge Model (FDCM)
All pins
Corner pins
—
SR Number of pulses per pin
Positive pulses (HBM)
Negative pulses (HBM)
—
—
—
—
1
—
SR Number of pulses
1
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot
temperature.”
3.6
Power management control (PMC) and power on reset (POR)
electrical specifications
Table 14. PMC operating conditions and external regulators supply voltage
Value
ID
Name
C
Parameter
Unit
Min Typ Max
1
TJ
SR — Junction temperature
–40
27
5
150 °C
2 VDDREG SR — PMC 5 V supply voltage VDDREG
4.75
5.25
V
V
3
VDD CC C Core supply voltage 1.2 V VDD when external regulator is used
without disabling the internal regulator (PMC unit turned on, LVI
monitor active)1
1.262 1.3 1.32
3a
—
CC C Core supply voltage 1.2 V VDD when external regulator is used with a 1.14 1.2 1.32
disabled internal regulator (PMC unit turned-off, LVI monitor disabled)
V
4
5
IVDD CC C Voltage regulator core supply maximum required DC output current
400
—
—
mA
V
VDD33 CC C Regulated 3.3 V supply voltage when external regulator is used
without disabling the internal regulator (PMC unit turned-on, internal
3.3V regulator enabled, LVI monitor active)3
3.3 3.45 3.6
5a
6
—
CC C Regulated 3.3 V supply voltage when external regulator is used with a
disabled internal regulator (PMC unit turned-off, LVI monitor disabled)
3
3.3
—
3.6
—
V
—
CC C Voltage regulator 3.3 V supply maximum required DC output current
80
mA
1
2
3
An internal regulator controller can be used to regulate the core supply.
The minimum supply required for the part to exit reset and enter in normal run mode is 1.28 V.
An internal regulator can be used to regulate the 3.3 V supply.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
62
Freescale Semiconductor
Electrical characteristics
Table 15. PMC electrical characteristics
Value
Typ
ID
Name
C
Parameter
Min
Unit
Max
1
VBG
CC C Nominal bandgap voltage reference
CC C Untrimmed bandgap reference voltage
—
1.219
VBG
—
V
V
V
1a
1b
—
—
VBG %
VBG + 6%
CC C Trimmed bandgap reference voltage (5 V,
27 °C)
VBG
10mV
VBG
VBG
+ 10mV
1c
1d
2
—
—
CC C Bandgap reference temperature variation
CC C Bandgap reference supply voltage variation
—
—
—
100
3000
1.28
—
—
—
ppm/°C
ppm/V
V
VDD
CC C Nominal VDD core supply internal regulator
target DC output voltage1
2a
2b
2c
—
—
—
CC C Nominal VDD core supply internal regulator VDD 6%
target DC output voltage variation at
power-on reset
VDD
VDD + 10%
VDD + 3%
V
V
CC C Nominal VDD core supply internal regulator VDD 10%2
target DC output voltage variation after
power-on reset
VDD
CC C Trimming step VDD
—
20
—
—
—
mV
mA
2d IVRCCTL CC C Voltage regulator controller for core supply
maximum DC output current
20
3
Lvi1p2
—
CC C Nominal LVI for rising core supply3
—
1.160
1.200
—
V
V
3a
CC C Variation of LVI for rising core supply at
power-on reset4
1.120
1.280
3b
—
CC C Variation of LVI for rising core supply after
power-on reset4
Lvi1p2
3%
Lvi1p2
Lvi1p2
+ 3%
V
3c
—
CC C Trimming step LVI core supply
—
—
—
20
40
—
—
—
mV
mV
V
3d Lvi1p2_h CC C LVI core supply hysteresis
4
Por1.2V_r CC C POR 1.2 V rising
CC C POR 1.2 V rising variation
0.709
4a
—
Por1.2V_r Por1.2V_r Por1.2V_r
V
35%
+ 35%
4b Por1.2V_f CC C POR 1.2 V falling
—
0.638
—
V
V
4c
—
VDD33
—
CC C POR 1.2 V falling variation
Por1.2V_f Por1.2V_f Por1.2V_f
35%
+ 35%
5
CC C Nominal 3.3 V supply internal regulator DC
output voltage
—
3.39
—
V
V
V
5a
5b
CC C Nominal 3.3 V supply internal regulator DC
output voltage variation at power-on reset
VDD33
8.5%
VDD33
VDD33
VDD33 + 7%
VDD33 + 7%
—
CC C Nominal 3.3 V supply internal regulator DC
output voltage variation after power-on
reset5
VDD33
7.5%
5c
—
CC C Voltage regulator 3.3 V output impedance at
maximum DC load
—
—
2
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
63
Electrical characteristics
Table 15. PMC electrical characteristics (continued)
Value
ID
Name
C
Parameter
Unit
Min
Typ
Max
5d
Idd3p3
CC C Voltage regulator 3.3 V maximum DC output
current
80
—
—
mA
5e Vdd33 ILim CC C Voltage regulator 3.3 V DC current limit
—
—
130
—
—
mA
V
6
Lvi3p3
—
CC C Nominal LVI for rising 3.3 V supply6
3.090
Lvi3p3
6a
CC C Variation of LVI for rising 3.3 V supply at
power-on reset7
Lvi3p3
6%
Lvi3p3
+ 6%
V
6b
—
CC C Variation of LVI for rising 3.3 V supply after
power-on reset7
Lvi3p3
3%
Lvi3p3
Lvi3p3
+ 3%
V
6c
—
CC C Trimming step LVI 3.3 V
—
—
—
20
60
—
—
—
mV
mV
V
6d Lvi3p3_h CC C LVI 3.3 V hysteresis
7
Por3.3V_r CC C Nominal POR for rising 3.3 V supply8
2.07
7a
—
CC C Variation of POR for rising 3.3 V supply
Por3.3V_r Por3.3V_r Por3.3V_r
V
35%
+ 35%
7b Por3.3V_f CC C Nominal POR for falling 3.3 V supply
—
1.95
—
V
V
7c
—
CC C Variation of POR for falling 3.3 V supply
Por3.3V_f Por3.3V_f Por3.3V_f
35%
+ 35%
8
Lvi5p0
—
CC C Nominal LVI for rising 5 V VDDREG supply
—
4.290
—
V
V
8a
CC C Variation of LVI for rising 5 V VDDREG
supply at power-on reset
Lvi5p0
6%
Lvi5p0
Lvi5p0
+ 6%
8b
8c
—
—
CC C Variation of LVI for rising 5 V VDDREG
supply power-on reset
Lvi5p0
3%
Lvi5p0
Lvi5p0
+ 3%
V
CC C Trimming step LVI 5 V
—
—
—
20
60
—
—
—
mV
mV
V
8d Lvi5p0_h CC C LVI 5 V hysteresis
9
Por5V_r CC C Nominal POR for rising 5 V VDDREG supply
2.67
9a
—
CC C Variation of POR for rising 5 V VDDREG
supply
Por5V_r
35%
Por5V_r
Por5V_r
+ 35%
V
9b Por5V_f CC C Nominal POR for falling 5 V VDDREG
supply
—
2.47
—
V
V
9c
—
CC C Variation of POR for falling 5 V VDDREG
supply
Por5V_f
35%
Por5V_f
Por5V_f
+ 35%
1
2
3
4
Using external ballast transistor.
Min range is extended to 10% since Lvi1p2 is reprogrammed from 1.2 V to 1.16 V after power-on reset.
LVI for falling supply is calculated as LVI rising – LVI hysteresis.
Lvi1p2 tracks DC target variation of internal VDD regulator. Minimum and maximum Lvi1p2 correspond to minimum
and maximum VDD DC target respectively.
5
6
7
With internal load up to Idd3p3
The Lvi3p3 specs are also valid for the VDDEH LVI
Lvi3p3 tracks DC target variation of internal VDD33 regulator. Minimum and maximum Lvi3p3 correspond to
minimum and maximum VDD33 DC target respectively.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
64
Freescale Semiconductor
Electrical characteristics
8
The 3.3V POR specs are also valid for the VDDEH POR
3.6.1
Regulator example
In designs where the MPC5642A microcontroller’s internal regulators are used, a ballast is required for generation of the 1.2 V
internal supply. No ballast is required when an external 1.2 V supply is used.
The resistor may or may not be
required. This depends on the
VDDREG
allowable power dissipation of
the npn bypass transistor
device. The resistor may be
Creg
Rc
used to limit the in-rush current
at power on.
The bypass transistor
MUST be operated out
of saturation region.
T1
Cc
VRCCTL
MCU
Rb
Keep parasitic inductance
under 20nH
Re
VDD
Mandatory decoupling
capacitor network
Cb
VSS
Ce
Cd
VRCCTL capacitor and resistor is required
Figure 8. Core voltage regulator controller external components preferred configuration
Table 16. MPC5642A External network specification
External Network
Min
Typ
Max
Comment
Parameter
T1
—
—
—
NJD2873 or BCP68
only
Cb
Ce
1.1 F
3*2.35F+5F
2.2F
3*4.7F+10F
—
2.97F
3*6.35F+13.5F
50m
X7R,-50%/+35%
X7R, -50%/+35%
—
Equivalent ESR of 5m
Ce capacitors
Cd
Rb
4*50nF
9
4*100nF
4*135nF
X7R, -50%/+35%
+/-10%
10
11
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
65
Electrical characteristics
Table 16. MPC5642A External network specification (continued)
External Network
Parameter
Min
Typ
Max
Comment
Re
0.252
0.280
10F
0.308
+/-10%
Creg
—
—
It depends on
external Vreg.
Cc
Rc
5F
10F
13.5F
5.6
X7R, -50%/+35%
1.1
—
May or may not be
required. It depends
on the allowable
power dissipation of
T1.
3.6.2
Recommended power transistors
The following NPN transistors are recommended for use with the on-chip voltage regulator controller: ON Semiconductor™
BCP68T1 or NJD2873 as well as Philips Semiconductor™ BCP68. The collector of the external transistor is preferably
connected to the same voltage supply source as the output stage of the regulator.
Table 17. Transistor recommended operating characteristics
Symbol
Parameter
DC current gain (Beta)
Absolute minimum power dissipation
Value
Unit
hFE ()
60–550
—
W
PD
>1.0
(1.5 preferred)
ICMaxDC Minimum peak collector current
1.0
A
mV
V
VCESAT Collector-to-emitter saturation voltage
200–6001
VBE
Base-to-emitter voltage
0.4–1.0
1
Adjust resistor at bipolar transistor collector for 3.3 V/5.0 V to avoid VCE < VCESAT
3.7
Power up/down sequencing
There is no power sequencing required among power sources during power up and power down, in order to operate within
specification.
Although there are no power up/down sequencing requirements to prevent issues such as latch-up or excessive current spikes,
the state of the I/O pins during power up/down varies according to Table 18 for all pins with pad type fast, and Table 19 for all
pins with pad type medium, slow, and multi-voltage.
Table 18. Power sequence pin states—Fast type pads
VDDE
VRC33
VDD
Pin state
Low
VDDE
VDDE
VDDE
X
X
Low
High
Low
X
VRC33
VRC33
Low
VDD
High impedance
Functional
MPC5642A Microcontroller Data Sheet, Rev. 3.1
66
Freescale Semiconductor
Electrical characteristics
Table 19. Power sequence pin states—Medium, slow and multi-voltage type pads
VDDEH
VDD
Pin state
Low
X
Low
VDDEH
VDDEH
Low
VDD
High impedance
Functional
3.8
DC electrical specifications
1
Table 20. DC electrical specifications
Value
Typ
Symbol
C
Parameter
Conditions
Unit
Min
Max
VDD
VDDE
SR
SR
SR
SR
SR
SR
SR
SR
SR
P
P
P
P
P
P
C
D
D
Core supply voltage
I/O supply voltage
—
—
—
—
—
—
—
—
—
1.14
3.0
—
—
—
—
—
—
—
—
—
1.32
3.6
V
V
VDDEH
VDDE-EH
VRC33
I/O supply voltage
3.0
5.25
V
I/O supply voltage
3.0
5.25
V
3.3 V regulated voltage2
Analog supply voltage
Analog input voltage
VSS differential voltage
3.0
3.6
V
VDDA
4.753
5.25
V
VINDC
VSSA
0.3
VDDA + 0.3
100
V
VSS – VSSA
VRL
–100
VSSA
mV
V
Analog reference low
voltage
VSSA + 0.1
V
RL – VSSA
SR
SR
D
D
VRL differential voltage
—
—
–100
—
—
100
mV
V
VRH
Analog reference high
voltage
VDDA
0.1
VDDA
V
RH – VRL
SR
SR
SR
SR
P
P
P
C
VREF differential voltage
Flash operating voltage4
Flash read voltage
—
4.75
1.14
3.0
—
—
—
—
—
—
5.25
1.32
3.6
V
V
V
V
VDDF
—
5
VFLASH
—
Unregulated mode
Regulated mode
—
VSTBY
SRAM standby voltage
0.95
2.0
1.2
5.5
VDDREG
SR
SR
P
P
D
Voltage regulator supply
voltage6
4.75
5.25
V
V
VDDPLL
Clock synthesizer
operating voltage
—
—
1.14
—
—
1.32
100
V
SSPLL – VSS SR
VSSPLL to VSS differential
voltage
–100
mV
V
VIL_S
SR
SR
P
P
P
P
Slow/medium I/O input low Hysteresis enabled
voltage
VSS
0.3
—
—
—
—
0.35 * VDDEH
0.40 * VDDEH
0.35 * VDDE
0.40 * VDDE
Hysteresis disabled
VSS
VSS
VSS
0.3
0.3
0.3
VIL_F
Fast I/O input low voltage Hysteresis enabled
Hysteresis disabled
V
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
67
Electrical characteristics
1
Table 20. DC electrical specifications (continued)
Value
Typ
Symbol
C
Parameter
Conditions
Unit
Min
Max
VIL_LS
SR
SR
P
P
Multi-voltage I/O pad input Hysteresis enabled
VSS
0.3
—
—
0.8
0.9
V
low voltage in
Hysteresis disabled
Low-swing-mode7,8,9,10
VSS
0.3
VIL_HS
P
P
Multi-voltage pad I/O input Hysteresis enabled
VSS
VSS
0.3
0.3
—
—
0.35 VDDEH
0.4 VDDEH
V
low voltage in
Hysteresis disabled
high-swing-mode
VIH_S
SR
SR
SR
P
P
P
P
P
P
Slow/medium pad I/O input Hysteresis enabled
0.65 VDDEH
0.55 VDDEH
0.65 VDDE
0.58 VDDE
2.5
—
—
—
—
—
—
VDDEH + 0.3
VDDEH + 0.3
VDDE + 0.3
VDDE + 0.3
VDDE + 0.3
VDDE + 0.3
V
V
V
high voltage
Hysteresis disabled
VIH_F
Fast I/O input high voltage Hysteresis enabled
Hysteresis disabled
VIH_LS
Multi-voltage pad I/O input Hysteresis enabled
high voltage in
Hysteresis disabled
low-swing-mode7,8,9,10
2.2
VIH_HS
SR
P
P
P
Multi-voltage I/O input high Hysteresis enabled
0.65 VDDEH
0.55 VDDEH
—
—
—
—
VDDEH + 0.3
VDDEH + 0.3
0.2 * VDDEH
V
voltage in high-swing-mode
Hysteresis disabled
VOL_S
VOL_F
VOL_LS
CC
CC
CC
Slow/medium pad I/O
output low voltage11
—
—
—
V
V
V
P
P
Fast I/O output low
voltage11
—
—
—
—
0.2 * VDDE
0.6
Multi-voltage pad I/O
output low voltage in
low-swing mode7,8,9,10,11
VOL_HS
CC
P
Multi-voltage pad I/O
output low voltage in
high-swing mode11
—
—
—
0.2 VDDEH
V
VOH_S
VOH_F
VOH_LS
CC
CC
CC
P
P
P
Slow/medium I/O output
high voltage11
—
—
—
0.8 VDDEH
0.8 VDDE
2.3
—
—
—
—
V
V
V
Fast pad I/O output high
voltage11
Multi-voltage pad I/O
output high voltage in
low-swing mode7,8,9,10,11
3.1
3.7
VOH_HS
CC
CC
P
P
Multi-voltage pad I/O
output high voltage in
high-swing mode11
—
—
0.8 VDDEH
—
—
—
—
V
V
VHYS_S
Slow/medium/multi-voltage
I/O input hysteresis
0.1 * VDDEH
VHYS_F
CC
CC
P
C
Fast I/O input hysteresis
—
0.1 * VDDE
0.25
—
—
—
—
V
v
VHYS_LS
Low-swing-mode
multi-voltage I/O input
hysteresis
Hysteresis enabled
MPC5642A Microcontroller Data Sheet, Rev. 3.1
68
Freescale Semiconductor
Electrical characteristics
1
Table 20. DC electrical specifications (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
IDD+IDDPLL CC
P
P
P
Operating current 1.2 V
supplies
VDD @1.32 V
@ 80 MHz
—
—
300
360
400
100
110
90
mA
mA
mA
A
A
A
VDD @ 1.32 V
—
—
—
—
—
—
—
@ 120 MHz
VDD @ 1.32 V
@ 150 MHz
IDDSTBY
CC T Operating current
0.95-1.2 V
VSTBY at 55 oC
35
45
25
T
Operating current
2–5.5 V
V
STBY at 55 oC
IDDSTBY27 CC P Operating current
0.95-1.2 V
VSTBY 27 oC
P
Operating current
2-5.5 V
V
STBY 27 oC
—
35
100
A
IDDSTBY150 CC P Operating current
0.95-1.2 V
VSTBY 150 oC
—
—
—
790
760
—
2000
2000
15
A
A
P
Operating current
2–5.5 V
VSTBY at 150 oC
IDDPLL
CC P Operating current 1.2 V VDDPLL, 80 MHz,
mA
mA
supplies
VDD=1.2 V
Slow mode12
Stop mode13
IDDSLOW
IDDSTOP
CC
C
C
P
VDD low-power mode
operating current @ 1.32 V
—
—
—
—
—
—
191
190
60
2
IDD33
CC
CC
Operating current 3.3 V
supplies
VRC33
mA
mA
IDDA
IREF
IDDREG
P
P
Operating current 5.0 V
supplies
VDDA
—
—
—
—
30.0
1.0
Analog reference
supply current
(transient)
P
P
P
P
P
P
P
P
VDDREG
VDDEH1
VDDEH4
VDDEH6
VDDEH7
VDDE7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7014
15
IDDH1
IDDH4
IDDH6
IDDH7
IDD7
CC
Operating current VDDE
supplies
See note 15
mA
IDDH9
IDD12
VDDEH9
VDDE12
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
69
Electrical characteristics
1
Table 20. DC electrical specifications (continued)
Value
Typ
Symbol
C
Parameter
Conditions
Unit
Min
Max
IACT_S
CC
CC
P
P
P
P
P
C
Slow/medium I/O weak
pull-up/down current16
3.0 V
–
3.6 V
15
35
36
34
42
10
—
—
—
—
—
—
95
µA
4.75 V
–
–
–
5.25 V
1.98 V
2.75 V
200
120
139
158
75
IACT_F
Fast I/O weak pull-up/down 1.62 V
µA
µA
current16
2.25 V
3.0 V–
3.6 V
IACT_MV_PU
CC
CC
Multi-voltage pad weak
pull-up current
VDDE = 3.0 – 3.6 V7,
multi-voltage,
high swing mode
only
C
C
4.75 V
–
5.25 V
25
10
—
—
175
60
IACT_MV_PD
Multi-voltage pad weak
pull-down current
VDDE = 3.0 – 3.6 V7,
multi-voltage,
µA
all process corners,
high swing mode
only
C
P
T
4.75 V
–
5.25 V
25
—
—
—
200
2.5
1.0
IINACT_D
IIC
CC
SR
I/O input leakage current17
—
–2.5
–1.0
µA
DC injection current (per
pin)
—
mA
IINACT_A
SR P Analog input current,
channel off, AN[0:7]18
—
—
–250
–150
—
—
250
150
nA
P Analog input current,
channel off, all other
analog pins18
CL
CC
D
D
D
D
D
D
D
C
Load capacitance (fast
I/O)19
DSC(PCR[8:9]) =
0b00
—
—
—
—
—
—
—
—
—
—
10
20
30
50
7
pF
DSC(PCR[8:9]) =
0b01
DSC(PCR[8:9]) =
0b10
—
DSC(PCR[8:9]) =
0b11
—
CIN
CC
CC
CC
SR
Input capacitance (digital
pins)
—
—
—
—
—
pF
pF
pF
CIN_A
Input capacitance (analog
pins)
—
10
12
280
CIN_M
Input capacitance (digital
—
and analog pins20
)
RPUPD200K
Weak pull-up/down
resistance21, 200 k
option
130
k
MPC5642A Microcontroller Data Sheet, Rev. 3.1
70
Freescale Semiconductor
Electrical characteristics
1
Table 20. DC electrical specifications (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
RPUPD100K
SR
SR
C
Weak pull-up/down
resistance21, 100 k
option
—
65
—
140
k
RPUPD5K
C
C
Weak pull-up/down
5 V 10% supply
3.3 V 10% supply
5 V 5% supply
1.4
1.7
1.4
—
—
—
5.2
7.7
7.5
k
resistance21, 5 k
option
RPUPD5K
SR C Weak Pull-Up/Down
k
Resistance21
,
5 k Option
RPUPDMTCH
CC
C
Pull-up/Down
Pull-up and
–2.5
—
2.5
%
Resistance matching
ratios (100K/200K)
pull-down
resistances both
enabled and
settings are equal.
TA (TL to TH) SR
P
D
Operating temperature
range - ambient
(packaged)
—
–40.0
—
—
—
125.0
25
°C
—
SR
Slew rate on power supply
pins
—
V/ms
1
2
3
These specifications are design targets and subject to change per device characterization.
These specifications apply when VRC33 is supplied externally, after disabling the internal regulator (VDDREG = 0).
ADC is functional with 4 V VDDA 4.75 V but with derated accuracy. This means the ADC will continue to function
at full speed with no undesirable behavior, but the accuracy will be degraded.
4
The VDDF supply is connected to VDD in the package substrate. This specification applies to calibration package
devices only.
5
6
7
8
9
VFLASH is available in the calibration package only.
Regulator is functional, with derated performance, with supply voltage down to 4.0 V
Multi-voltage power supply cannot be below 4.5 V when in low-swing mode
The slew rate (SRC) setting must be 0b11 when in low-swing mode.
While in low-swing mode there are no restrictions in transitioning to high-swing mode.
10 Pin in low-swing mode can accept a 5 V input
11 All VOL/VOH values 100% tested with 2 mA load except where otherwise noted
12 Bypass mode, system clock @ 1 MHz (using system clock divider), PLL shut down, CPU running simple executive
code, 4 x ADC conversion every 10 ms, 2 x PWM channels @ 1 kHz, all other modules stopped.
13 Bypass mode, system clock @ 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules
stopped
14 If 1.2V and 3.3V internal regulators are on,then iddreg=70mA
If supply is external that is 3.3V internal regulator is off, then iddreg=15mA
15 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on
a particular I/O segment, and the voltage of the I/O segment. See Table 21 for values to calculate power dissipation
for specific operation. The total power consumption of an I/O segment is the sum of the individual power
consumptions for each pin on the segment.
16 Absolute value of current, measured at VIL and VIH
17 Weak pull-up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to all digital pad types.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
71
Electrical characteristics
18 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately
one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to analog pads.
19 Applies to CLKOUT, external bus pins, and Nexus pins
20 Applies to the FCK, SDI, SDO, and SDS pins
21 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor
diagnostics.
3.9
I/O pad current specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption
is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 21 based on
the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load
parameters that fall outside the values given in Table 21.
1
Table 21. I/O pad average I
specifications
DDE
Period
(ns)
Load2
(pF)
VDDE Drive/Slew IDDE Avg IDDE RMS
Pad type
Symbol
C
(V)
rate select
(mA)3
(mA)
Slow
IDRV_SSR_HV CC D
37
130
650
840
24
50
50
50
200
50
50
50
200
50
30
20
10
50
30
20
10
50
50
50
200
30
5.25
5.25
5.25
5.25
5.25
5.25
5.25
5.25
3.6
11
01
00
00
11
01
00
00
11
10
01
00
11
10
01
00
11
01
00
00
11
9
—
—
CC D
2.5
0.5
1.5
14
CC D
CC D
—
—
Medium
Fast
IDRV_MSR_HV CC D
CC D
—
62
5.3
1.1
3
—
CC D
317
425
10
—
CC D
—
IDRV_FC
CC D
CC D
CC D
CC D
CC D
CC D
CC D
CC D
22.7
12.1
8.3
4.44
12.5
7.3
5.42
2.84
9
68.3
41.1
27.7
14.3
31
10
3.6
10
3.6
10
3.6
10
1.98
1.98
1.98
1.98
5.25
5.25
5.25
5.25
5.25
10
18.6
12.6
6.4
—
10
10
MultiV
(High swing mode)
IDRV_MULTV_HV CC D
CC D
20
30
6.1
2.3
5.8
3.4
—
CC D
117
212
30
—
CC D
—
MultiV
IDRV_MULTV_HV CC D
—
(Low swing mode)
1
2
3
Numbers from simulations at best case process, 150 °C
All loads are lumped.
Average current is for pad configured as output only
MPC5642A Microcontroller Data Sheet, Rev. 3.1
72
Freescale Semiconductor
Electrical characteristics
3.9.1
I/O pad VRC33 current specifications
The power consumption of the V
supply is dependent on the usage of the pins on all I/O segments. The power consumption
RC33
is the sum of all input and output pin V
currents for all I/O segments. The output pin V
current can be calculated from
RC33
RC33
Table 22 based on the voltage, frequency, and load on all fast pins. The input pin V
current can be calculated from Table 22
RC33
based on the voltage, frequency, and load on all medium pins. Use linear scaling to calculate pin currents for voltage, frequency,
and load parameters that fall outside the values given in Table 22.
1
Table 22. I/O pad V
average I
specifications
RC33
DDE
Period
(ns)
Load2
(pF)
Drive
select
IDD33 Avg
(µA)
IDD33 RMS
(µA)
Pad type
Symbol
C
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
D
D
D
D
D
D
D
100
200
800
800
40
50
50
11
01
00
00
11
01
00
00
11
01
00
00
11
0.8
0.04
0.06
0.009
2.75
0.11
0.02
0.01
33.4
33.4
33.4
33.4
33.4
235.7
87.4
47.4
47
Slow
IDRV_SSR_HV
50
200
50
258
100
500
500
20
50
76.5
56.2
56.2
35.4
34.8
33.8
33.7
33.7
Medium
IDRV_MSR_HV
50
200
50
MultiV3
(High swing mode)
30
50
IDRV_MULTV_HV
117
212
30
50
200
30
MultiV4
(Low swing mode)
IDRV_MULTV_HV
1
2
3
4
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
All loads are lumped.
Average current is for pad configured as output only
In low swing mode, multi-voltage pads must operate in highest slew rate setting, ipp_sre0 = 1, ipp_sre1 = 1.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
73
Electrical characteristics
1
Table 23. V
pad average DC current
RC33
Period
(ns)
Load2
(pF)
VRC33
(V)
VDDE
(V)
Drive
select
IDD33 Avg IDD33 RMS
Pad type
Symbol
C
(µA)
(µA)
CC
CC
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
D
D
10
10
10
10
10
10
10
10
50
30
20
10
50
30
20
10
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
11
10
01
00
11
10
01
00
2.35
1.75
1.41
1.06
1.75
1.32
1.14
0.95
6.12
4.3
3.6
3.43
2.9
3.6
Fast
IDRV_FC
1.98
1.98
1.98
1.98
4.56
3.44
2.95
2.62
1
2
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
All loads are lumped.
3.9.2
LVDS pad specifications
LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is an enhanced feature of the DSPI
module. The LVDS pads are compliant with LVDS specifications and support data rates up to 50 MHz.
Table 24. DSPI LVDS pad specification
Value
Symbol
C
Parameter
Condition
Unit
Min
Typ
Max
Data rate
fLVDSCLK
CC D Data frequency
—
—
50
—
—
MHz
mV
Driver specifications
SRC = 0b00 or
VOD
CC P Differential output voltage
150
400
0b11
CC P
SRC = 0b01
90
160
1.06
—
—
—
1.2
2
320
480
1.39
—
CC P
SRC = 0b10
VOC
CC P Common mode voltage (LVDS), VOS
CC D Rise/Fall time
—
—
—
—
—
—
V
TR/TF
TPLH
TPHL
tPDSYNC
TDZ
ns
ns
ns
ns
ns
CC D Propagation delay (Low to High)
CC D Propagation delay (High to Low)
CC D Delay (H/L), sync mode
CC D Delay, Z to Normal (High/Low)
—
4
—
—
4
—
—
4
—
—
500
—
MPC5642A Microcontroller Data Sheet, Rev. 3.1
74
Freescale Semiconductor
Electrical characteristics
Table 24. DSPI LVDS pad specification (continued)
Value
Symbol
C
Parameter
Condition
Unit
Max
Min
Typ
TSKEW
CC D Differential skew Itphla-tplhbI or
Itplhb-tphlaI
—
—
—
0.5
ns
Termination
CC D Transmission line (differential Zo)
CC D Temperature
—
—
95
100
—
105
150
W
–40
C
3.10 Oscillator and PLLMRFM electrical characteristics
1
Table 25. PLLMRFM electrical specifications
(VDDPLL = 1.08 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
fref_crystal CC P PLL reference frequency range2
Crystal reference
External reference
—
4
4
4
40
80
16
MHz
fref_ext
P
fpll_in
CC D Phase detector input frequency range
(after pre-divider)
MHz
fvco
fsys
fsys
CC D VCO frequency range
CC T On-chip PLL frequency2
CC T System frequency in bypass mode3
T
—
—
256
16
4
512
150
40
MHz
MHz
MHz
Crystal reference
External reference
—
0
80
tCYC
CC D System clock period
—
1.6
24
1.2
–5
1 / fsys
3.7
ns
fLORL CC D Loss of reference frequency window4
Lower limit
Upper limit
—
MHz
fLORH
D
CC P Self-clocked mode frequency5,6
CJITTER CC C CLKOUT period Peak-to-peak (clock
56
fSCM
72.25
5
MHz
fSYS maximum
% fCLKOUT
jitter7,8,9,10
edge to clock edge)
C
Long-term jitter (avg.
over 2 ms interval)
–6
—
6
ns
tcst
CC T Crystal start-up time11,12
—
10
—
ms
V
VIHEXT CC D EXTAL input high voltage
Crystal mode13
Vxtal
+ 0.4
T
External
VRC33/2 VRC33
+ 0.4
reference13,14
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
75
Electrical characteristics
1
Table 25. PLLMRFM electrical specifications
(VDDPLL = 1.08 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
VILEXT CC D EXTAL input low voltage
T
Crystal mode13
—
Vxtal
– 0.4
V
External
0
VRC33/2
– 0.4
reference13,14
—
—
CC T XTAL load capacitance
CC C XTAL load capacitance11
—
4 MHz
8 MHz
12 MHz
16 MHz
20 MHz
40 MHz
—
5
5
30
30
26
23
19
16
8
pF
pF
5
5
5
5
5
tlpll
tdc
fLCK
fUL
fCS
CC P PLL lock time11,15
CC D Duty cycle of reference
CC D Frequency LOCK range
CC D Frequency un-LOCK range
CC D Modulation depth
D
—
40
–6
–18
0.25
–0.5
—
200
60
6
µs
—
%
—
% fsys
% fsys
% fsys
—
18
4.0
–8.0
100
Center spread
Down spread
—
fDS
fMOD
CC D Modulation frequency16
kHz
1
2
3
4
All values given are initial design targets and subject to change.
Considering operation with PLL not bypassed
All internal registers retain data at 0 Hz.
“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked
mode.
5
6
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside
the fLOR window.
fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
7
8
This value is determined by the crystal manufacturer and board design.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
9
Proper PC board layout procedures must be followed to achieve specifications.
10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
11 This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals specified for
this PLL, load capacitors should not exceed these limits.
12 Proper PC board layout procedures must be followed to achieve specifications.
13 This parameter is guaranteed by design rather than 100% tested.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
76
Freescale Semiconductor
Electrical characteristics
14
V
cannot exceed VRC33 in external reference mode.
IHEXT
15 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
16 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
3.11 Temperature sensor electrical characteristics
Table 26. Temperature sensor electrical characteristics
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
—
CC C Temperature
monitoring range
–40
—
150
°C
—
—
CC C Sensitivity
CC C Accuracy
—
6.3
—
—
mV/°C
°C
TJ = –40 to 150 °C
–10
10
3.12 eQADC electrical characteristics
Table 27. eQADC conversion specifications (operating)
Value
Unit
Symbol
C
Parameter
min
max
fADCLK
SR
CC
CC
SR
—
D
ADC clock (ADCLK) frequency
Conversion cycles
2
2+13
—
16
128+14
10
MHz
CC
TSR
ADCLK cycles
C
Stop mode recovery time1
s
fADCLK
—
ADC clock (ADCLK) frequency
2
16
mV
1
Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to
the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.
Table 28. eQADC single ended conversion specifications (operating)
Value
Symbol
C
Parameter
Unit
min
max
OFFNC
CC
CC
CC
C
C
C
C
T
Offset error without calibration
0
–4
160
4
Counts
Counts
Counts
Counts
mA
OFFWC
GAINNC
Offset error with calibration
Full scale gain error without calibration
Full scale gain error with calibration
Disruptive input injection current 1, 2, 3, 4
Incremental error due to injection current5,6
Total unadjusted error (TUE) at 8 MHz
Total unadjusted error at 16 MHz
–160
–4
0
GAINWC CC
4
IINJ
EINJ
CC
CC
CC
CC
–3
3
T
–4
4
Counts
Counts
Counts
TUE8
TUE16
C
C
–4
46
–8
8
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
77
Electrical characteristics
1
Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog
inputs greater then VRH and 0x0 for values less then VRL. Other channels are not affected by non-disruptive
conditions.
2
3
Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions
within the limit do not affect device reliability or cause permanent damage.
Input must be current limited to the value specified. To determine the value of the required current-limiting
resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use
the larger of the calculated values.
4
5
6
Condition applies to two adjacent pins at injection limits.
Performance expected with production silicon.
All channels have same 10 k < Rs < 100 k; Channel under test has Rs=10 k; IINJ=IINJMAX INJMIN
,I
Table 29. eQADC differential ended conversion specifications (operating)
Value
Symbol
C
Parameter
Unit
min
max
GAINVGA11
GAINVGA21
GAINVGA41
CC
CC
–
Variable gain amplifier accuracy (gain=1)2
C
INL
8 MHz
ADC
–4
–8
4
8
Counts
3
CC
CC
CC
C
C
C
16 MHz
ADC
Counts
Counts
Counts
DNL
8 MHz
ADC
–34
–34
34
34
16 MHz
ADC
CC
CC
–
Variable gain amplifier accuracy (gain=2)2
D
INL
8 MHz
ADC
–5
–8
–3
–3
5
8
3
3
Counts
Counts
Counts
Counts
CC
CC
CC
D
D
D
16 MHz
ADC
DNL
8 MHz
ADC
16 MHz
ADC
CC
CC
–
Variable gain amplifier accuracy (gain=4)2
D
INL
8 MHz
ADC
–7
–8
–4
–4
7
8
4
4
Counts
Counts
Counts
Counts
CC
CC
CC
D
D
D
16 MHz
ADC
DNL
8 MHz
ADC
16 MHz
ADC
MPC5642A Microcontroller Data Sheet, Rev. 3.1
78
Freescale Semiconductor
Electrical characteristics
Table 29. eQADC differential ended conversion specifications (operating) (continued)
Value
Symbol
C
Parameter
Unit
min
max
DIFFmax
CC
CC
CC
CC
C
Maximum
differential voltage set to 1X
(DANx+ - DANx-) or
(DANx- - DANx+)5
PREGAIN
—
(VRH - VRL)/2
V
setting
DIFFmax2
DIFFmax4
DIFFcmv
C
C
C
PREGAIN
set to 2X
setting
—
—
(VRH - VRL)/4
(VRH - VRL)/8
V
V
V
PREGAIN
set to 4X
setting
Differential input
Common mode
voltage (DANx- +
DANx+)/25
—
(VRH + VRL)/2 - 5% (VRH + VRL)/2 + 5%
1
2
Applies only to differential channels.
Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1, 2, or 4.
Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated.
3
4
5
At VRH – VRL = 5.12 V, one LSB = 1.25 mV.
Guaranteed 10-bit mono tonicity.
Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the
differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode
voltage of the differential signal violates the Differential Input common mode voltage specification.
3.13 Configuring SRAM wait states
Use the SWSC field in the ECSM_MUDCR register to specify an additional wait state for the device SRAM. By default, no
wait state is added.
Table 30. Cutoff frequency for additional SRAM wait state
1
SWSC Value
98
0
1
153
1
Max frequencies including 2% PLL FM.
Please see the device reference manual for details.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
79
Electrical characteristics
3.14 Platform flash controller electrical characteristics
Table 31. APC, RWSC, WWSC settings vs. frequency of operation
Max. Flash Operating
1
APC3
RWSC3
WWSC
Frequency (MHz)2
20 MHz
61 MHz
90 MHz
123 MHz
153 MHz
0b000
0b001
0b010
0b011
0b100
0b000
0b001
0b010
0b011
0b100
0b01
0b01
0b01
0b01
0b01
1
APC, RWSC and WWSC are fields in the flash memory BIUCR register used to
specify wait states for address pipelining and read/write accesses. Illegal
combinations exist—all entries must be taken from the same row.
2
3
Max frequencies including 2% PLL FM.
APC must be equal to RWSC.
3.15 Flash memory electrical characteristics
1
Table 32. Flash program and erase specifications
Value
#
Symbol
C
Parameter
Unit
Initial
Min
Typ
Max3
max2
1
2
3
5
Tdwprogram CC C Double Word (64 bits) Program Time
Tpprogram CC C Page Program Time4
—
—
30
40
—
500
500
µs
µs
160
T16kpperase CC C 16 KB Block Pre-program and Erase Time
T64kpperase CC C 64 KB Block Pre-program and Erase Time
—
250
450
800
1,400
—
1,000
1,800
2,600
5,000 ms
5,000 ms
7,500 ms
—
6 T128kpperase CC C 128 KB Block Pre-program and Erase Time
7 T256kpperase CC C 256 KB Block Pre-program and Erase Time
—
—
5,200 15,000 ms
8
9
Tpsrt
Tesrt
SR —
SR —
Program suspend request rate5
Erase suspend request rate 6
100
10
—
—
s
ms
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
3
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage, 80 MHz minimum system
frequency.
The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is
characterized but not guaranteed.
4
5
6
Page size is 128 bits (4 words)
Time between program suspend resume and the next program suspend request.
Time between erase suspend resume and the next erase suspend request.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
80
Freescale Semiconductor
Electrical characteristics
Table 33. Flash EEPROM module life
Value
Symbol
C
Parameter
Conditions
Unit
Typ
Min
P/E
CC
CC
D
Number of program/erase
cycles per block for 16 KB,
48 KB, and 64 KB blocks over
the operating temperature
range (TJ)
—
100,000
—
cycles
P/E
D
Number of program/erase
cycles per block for 128 KB and
256 KB blocks over the
operating temperature range
(TJ)
—
1,000
100,000 cycles
Retention CC
D
D
D
Minimum data retention at
85 °C
Blocks with 0 – 1,000
P/E cycles
20
10
5
—
—
—
years
Blocks with 10,000 P/E
cycles
Blocks with 100,000 P/E
cycles
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
81
Electrical characteristics
3.16 AC specifications
3.16.1 Pad AC specifications
1
Table 34. Pad AC specifications (V
= 4.75 V)
DDE
Output delay (ns)2,3
Low-to-High /
Rise/Fall edge (ns)3,4
SRC/DSC
MSB, LSB
Drive load
(pF)
Name
C
High-to-Low
Min
Max
Min
Max
Medium5,6,7
CC D
4.6/3.7
12/12
2.2/2.2
12/12
50
118
109
01
—
CC D
CC D
CC D
12/13
69/71
28/34
152/165
19/18
5.6/6
34/35
4.4/4.3
15/15
74/74
20/20
50
50
50
00
Slow7,10
7.3/5.7
118
109
01
—
CC D
CC D
CC D
26/27
137/142
4.1/3.6
61/69
13/13
72/74
34/34
164/164
8/8
50
50
50
320/330
10.3/8.9
00
MultiV11
(High Swing Mode)
3.28/2.98
—
118
109
01
CC D 8.38/6.11
CC D 61.7/10.4
CC D 2.31/2.34
16/12.9
92.2/24.3
7.62/6.33
5.48/4.81
42.0/12.2
1.26/1.67
11/11
63/63
50
50
30
00
MultiV
6.5/4.4
118
(Low Swing Mode)
Fast12
—
Standalone input CC D
buffer13
0.5/0.5
1.9/1.9
0.3/0.3
1.5/1.5
0.5
—
1
These are worst case values that are estimated from simulation and not tested. The values in the table are
simulated at VDD = 1.14 V to 1.32 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH.
2
3
4
5
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
In high swing mode, high/low swing pad VOL and VOH values are the same as those of the slew controlled output
pads.
6
7
Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down.
Output delay is shown in Figure 9 and Figure 10. Add a maximum of one system clock to the output delay for delay
with respect to system clock.
8
9
Can be used on the tester
This drive select value is not supported. If selected, it will be approximately equal to 11.
10 Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down.
11 Selectable high/low swing I/O pad with selectable slew in high swing mode only
12 Fast pads are 3.3 V pads.
13 Also has weak pull-up/pull-down.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
82
Freescale Semiconductor
Electrical characteristics
1
Table 35. Pad AC specifications (V
Output delay (ns)2,3
= 3.0 V)
DDE
Low-to-High /
High-to-Low
Rise/Fall edge (ns)3,4
SRC/DSC
Drive load
Pad type
C
(pF)
Min
Max
Min
Max
MSB,LSB
Medium5,6,7
CC
CC
D
D
5.8/4.4
16/13
18/17
46/49
2.7/2.1
10/10
34/34
50
118
11.2/8.6
200
—
109
01
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
14/16
27/27
37/45
69/82
6.5/6.7
15/13
38/38
53/46
5.5/4.1
21/16
19/19
43/43
50
200
50
83/86
200/210
270/285
27/28
86/86
00
11
113/109
9.2/6.9
30/23
120/120
20/20
200
50
Slow7,10
81/87
63/63
200
—
109
01
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
31/31
58/52
162/168
216/205
—
80/90
144/155
415/415
533/540
3.7/3.1
46/49
15.4/15.4
32/26
80/82
106/95
—
42/42
82/85
50
200
50
190/190
250/250
10/10
00
200
30
MultiV7,11
(High Swing Mode)
118
—
—
42/42
200
—
109
01
CC
CC
CC
CC
D
D
D
D
—
—
—
—
32
72
—
—
—
—
15/15
46/46
50
200
50
210
295
100/100
134/134
00
200
MultiV
Not a valid operational mode
(Low Swing Mode)
Fast
CC
CC
CC
CC
CC
D
D
D
D
D
—
—
2.5/2.5
2.5/2.5
2.5/2.5
2.5/2.5
3/3
—
—
1.2/1.2
1.2/1.2
1.2/1.2
1.2/1.2
1.5/1.5
10
20
30
50
0.5
00
01
—
—
10
—
—
118
Standalone input
buffer12
0.5/0.5
0.4/0.4
—
1
These are worst case values that are estimated from simulation and not tested. The values in the table are
simulated at VDD = 1.14 V to 1.32 V, VDDE = 3 V to 3.6 V, VDDEH = 3 V to 3.6 V, TA = TL to TH.
2
3
4
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
83
Electrical characteristics
5
In high swing mode, high/low swing pad VOL and VOH values are the same as those of the slew controlled output
pads.
6
7
Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down.
Output delay is shown in Figure 9 and Figure 10. Add a maximum of one system clock to the output delay for delay
with respect to system clock.
8
9
Can be used on the tester.
This drive select value is not supported. If selected, it will be approximately equal to 11.
10 Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down.
11 Selectable high/low swing I/O pad with selectable slew in high swing mode only.
12 Also has weak pull-up/pull-down.
VDDE/2
Pad
Data Input
Rising
Edge
Falling
Edge
Output
Delay
Output
Delay
VOH
Pad
Output
VOL
Figure 9. Pad output delay—Fast pads
MPC5642A Microcontroller Data Sheet, Rev. 3.1
84
Freescale Semiconductor
Electrical characteristics
VDDE/2
Pad
Data Input
Rising
Edge
Falling
Edge
Output
Delay
Output
Delay
VOH
Pad
Output
VOL
Figure 10. Pad output delay—Slew rate controlled fast, medium, and slow pads
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
85
Electrical characteristics
3.17 AC timing
3.17.1 Reset and configuration pin timing
1
Table 36. Reset and configuration pin timing
Value
#
Symbol
Characteristic
Unit
Min
Max
1
2
3
4
tRPW
tGPW
tRCSU
tRCH
RESET Pulse Width
10
2
—
—
—
—
tCYC
tCYC
tCYC
tCYC
RESET Glitch Detect Pulse Width
PLLREF, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid
PLLREF, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid
10
0
1
Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.14 V to 1.32 V, TA = TL to TH.
2
RESET
1
RSTOUT
3
BOOTCFG
WKPCFG
4
Figure 11. Reset and configuration pin timing
3.17.2 IEEE 1149.1 interface timing
1
Table 37. JTAG pin AC electrical characteristics
Value
#
Symbol
C
Characteristic
Unit
Min
Max
1
2
3
tJCYC
tJDC
CC D TCK Cycle Time
100
40
—
60
3
ns
ns
ns
CC D TCK Clock Pulse Width
tTCKRISE
CC D TCK Rise and Fall Times (40%–70%)
—
MPC5642A Microcontroller Data Sheet, Rev. 3.1
86
Freescale Semiconductor
Electrical characteristics
1
Table 37. JTAG pin AC electrical characteristics (continued)
Value
#
Symbol
C
Characteristic
Unit
Min
Max
4
5
tTMSS, TDIS
t
CC D TMS, TDI Data Setup Time
10
25
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tTMSH, tTDIH CC D TMS, TDI Data Hold Time
6
tTDOV
tTDOI
CC D TCK Low to TDO Data Valid
222
7
CC D TCK Low to TDO Data Invalid
0
—
8
tTDOHZ
tJCMPPW
tJCMPS
tBSDV
CC D TCK Low to TDO High Impedance
CC D JCOMP Assertion Time
—
22
—
9
100
40
—
10
11
12
13
14
15
CC D JCOMP Setup Time to TCK Low
—
CC D TCK Falling Edge to Output Valid
50
50
50
—
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
CC D TCK Falling Edge to Output Valid out of High Impedance
CC D TCK Falling Edge to Output High Impedance
CC D Boundary Scan Input Valid to TCK Rising Edge
CC D TCK Rising Edge to Boundary Scan Input Invalid
—
—
253
253
—
1
JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.75 V to 5.25 V with multi-voltage pads programmed to
Low-Swing mode, TA = TL to TH, CL = 30 pF, SRC = 0b11. These specifications apply to JTAG boundary scan only.
See Table 38 for functional specifications.
2
3
Pad delay is 8–10 ns. Remainder includes TCK pad delay, clock tree delay logic delay and TDO output pad delay.
For 20 MHz TCK.
NOTE
The Nexus/JTAG Read/Write Access Control/Status Register (RWCS) write (to begin a
read access) or the write to the Read/Write Access Data Register (RWD) (to begin a write
access) does not actually begin its action until 1 JTAG clock (TCK) after leaving the JTAG
Update-DR state. This prevents the access from being performed and therefore will not
signal its completion via the READY (RDY) output unless the JTAG controller receives an
additional TCK. In addition, EVTI is not latched into the device unless there are clock
transitions on TCK.
The tool/debugger must provide at least one TCK clock for the EVTI signal to be
recognized by the MCU. When using the RDY signal to indicate the end of a Nexus
read/write access, ensure that TCK continues to run for at least one TCK after leaving the
Update-DR state. This can be just a TCK with TMS low while in the Run-Test/Idle state or
by continuing with the next Nexus/JTAG command. Expect the effect of EVTI and RDY
to be delayed by edges of TCK.
RDY is not available in all device packages.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
87
Electrical characteristics
TCK
2
3
3
2
1
Figure 12. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 13. JTAG test access port timing
MPC5642A Microcontroller Data Sheet, Rev. 3.1
88
Freescale Semiconductor
Electrical characteristics
TCK
10
JCOMP
9
Figure 14. JTAG JCOMP timing
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
89
Electrical characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 15. JTAG boundary scan timing
3.17.3 Nexus timing
1
Table 38. Nexus debug port timing
Value
Min Max
#
Symbol
C
Characteristic
Unit
1
tMCYC CC D MCKO Cycle Time
22,3
254
40
8
tCYC
ns
1a tMCYC CC D Absolute Minimum MCKO Cycle Time
—
60
2
3
4
6
7
tMDC
CC D MCKO Duty Cycle
%
tMDOV CC D MCKO Low to MDO Data Valid5
tMSEOV CC D MCKO Low to MSEO Data Valid5
tEVTOV CC D MCKO Low to EVTO Data Valid5
tEVTIPW CC D EVTI Pulse Width
0.1 0.35 tMCYC
0.1 0.35 tMCYC
0.1 0.35 tMCYC
4.0
—
tTCYC
MPC5642A Microcontroller Data Sheet, Rev. 3.1
90
Freescale Semiconductor
Electrical characteristics
1
Table 38. Nexus debug port timing (continued)
Value
Unit
#
Symbol
C
Characteristic
Min Max
8
9
tEVTOPW CC D EVTO Pulse Width
tTCYC CC D TCK Cycle Time
1
46,7
1008
40
—
—
tMCYC
tCYC
ns
9a tTCYC CC D Absolute Minimum TCK Cycle Time
10 tTDC CC D TCK Duty Cycle
—
60
—
%
11 tNTDIS CC D TDI Data Setup Time
12 tNTDIH CC D TDI Data Hold Time
13 tNTMSS CC D TMS Data Setup Time
14 tNTMSH CC D TMS Data Hold Time
10
ns
25
—
ns
10
—
ns
25
—
ns
15
16
—
—
CC D TDO propagation delay from falling edge of TCK
—
19.5
—
ns
CC D TDO hold time wrt TCK falling edge (minimum TDO propagation delay) 5.25
ns
1
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing
specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.75 V to 5.25 V with multi-voltage pads programmed to Low-Swing
mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10.
2
3
4
Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum
setting (NPC_PCR[MCKO_DIV] depending on the actual system frequency being used.
This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the
Absolute minimum MCKO period specification.
This may require setting the MCO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending on
the actual system frequency being used.
5
6
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that
is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system
frequency being used.
7
8
This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the
Absolute minimum TCK period specification.
This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability
of the design (system frequency / 4) depending on the actual system frequency being used.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
91
Electrical characteristics
1
2
MCKO
3
4
6
MDO
MSEO
EVTO
Output Data Valid
Figure 16. Nexus output timing
TCK
EVTI
EVTO
7
7
8
9
8
Figure 17. Nexus event trigger and test clock timings
MPC5642A Microcontroller Data Sheet, Rev. 3.1
92
Freescale Semiconductor
Electrical characteristics
TCK
11
13
12
14
TMS, TDI
15
16
TDO
Figure 18. Nexus TDI, TMS, TDO timing
N
Table 39. Nexus debug port operating frequency
Nexus Pin Usage
Max. Operating
Frequency
Package Nexus Width Nexus Routing
CAL_MDO[4:1
1]
MDO[0:3]
MDO[4:11]
176 LQFP Reducedport Route to MDO2 Nexus Data Out
GPIO
GPIO
GPIO
GPIO
GPIO
40 MHz3
40 MHz5,6
40 MHz3
40 MHz5,6
40 MHz3
208 BGA mode1
[0:3]
324 BGA
Full port
Route to MDO2 Nexus Data Out Nexus Data Out
mode4
[0:3]
[4:11]
GPIO
496 CSP Reducedport Route to MDO2 Nexus Data Out
mode1
[0:3]
Full port
mode4
Route to MDO2 Nexus Data Out Nexus Data Out
[0:3]
[4:11]
GPIO
Route to
Cal Nexus Data
Out [0:3]
Cal Nexus Data
Out [4:11]
CAL_MDO7
1
2
NPC_PCR[FPM] = 0
NPC_PCR[NEXCFG] = 0
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
93
Electrical characteristics
3
The Nexus AUX port runs up to 40 MHz. Set NPC_PCR[MCKO_DIV] to divide-by-two if the system frequency is
greater than 40 MHz.
4
5
NPC_PCR[FPM] = 1
Set the NPC_PCR[MCKO_DIV] to divide by two if the system frequency is between 40 MHz and 80 MHz inclusive.
Set the NPC_PCR[MCKO_DIV] to divide by four if the system frequency is greater than 80 MHz.
6
7
Pad restrictions limit the Maximum Operation Frequency in these configurations
NPC_PCR[NEXCFG] = 1
MPC5642A Microcontroller Data Sheet, Rev. 3.1
94
Freescale Semiconductor
Electrical characteristics
3.17.4 Calibration bus interface timing
Table 40. Calibration bus interface maximum operating frequency
Pin usage
Multiplexed
mode
Max. operating
frequency
Port width
CAL_ADDR[12:15] CAL_ADDR[16:30]
CAL_DATA[0:15]
16-bit
Yes
GPIO
GPIO
CAL_ADDR[12:30]
CAL_DATA[0:15]
66 MHz1
16-bit
32-bit
No
CAL_ADDR[12:15] CAL_ADDR[16:30]
CAL_DATA[0:15]
66 MHz1
66 MHz1
Yes
CAL_WE/BE[2:3]
CAL_DATA[31]
CAL_ADDR[16:30]
CAL_DATA[16:30]
CAL_ADDR[0:15]
CAL_DATA[0:15]
1
Set SIU_ECCR[EBDF] to either divide by two or divide by four if the system frequency is greater than 66 MHz.
1
Table 41. Calibration bus operation timing
66 MHz2
#
Symbol
C
Characteristic
Unit
Min
Max
1
2
3
4
5
TC CC P CLKOUT period3
tCDC CC T CLKOUT duty cycle
tCRT CC T CLKOUT rise time
tCFT CC T CLKOUT fall time
15.2
45%
—
—
ns
TC
ns
ns
ns
55%
4
4
—
tCOH CC P CLKOUT Posedge to Output Signal Invalid or High Z (Hold Time)
1.3
—
CAL_ADDR[12:30]
CAL_CS[0], CAL_CS[2:3]
CAL_DATA[0:15]
CAL_OE
CAL_RD_WR
CAL_TS
CAL_WE[0:3]/BE[0:3]
6
tCOV CC P CLKOUT Posedge to Output Signal Valid (Output Delay)
—
9
ns
CAL_ADDR[12:30]
CAL_CS[0], CAL_CS[2:3]
CAL_DATA[0:15]
CAL_OE
CAL_RD_WR
CAL_TS
CAL_WE[0:3]/BE[0:3]
7
8
9
tCIS CC P Input Signal Valid to CLKOUT Posedge (Setup Time)
6.0
1.0
—
—
ns
ns
DATA[0:31]
tCIH CC P CLKOUT Posedge to Input Signal Invalid (Hold Time)
DATA[0:31]
tAPW CC P ALE Pulse Width5
6.5
—
—
ns
ns
10 tAAI CC P ALE Negated to Address Invalid5
1.56
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
95
Electrical characteristics
1
Calibration bus timing specified at fSYS = 150 MHz and 100 MHz, VDD = 1.14 V to 1.32 V, VDDE = 3 V to 3.6 V
(unless stated otherwise), TA = TL to TH, and CL = 30 pF with DSC = 0b10.
2
The calibration bus is limited to half the speed of the internal bus. The maximum calibration bus frequency is
66 MHz. The bus division factor should be set accordingly based on the internal frequency being used.
3
4
5
6
Signals are measured at 50% VDDE
Refer to fast pad timing in Table 34 and Table 35 (different values for 1.8 V vs. 3.3 V).
Measured at 50% of ALE
When CAL_TS pad is used for CAL_ALE function the hold time is 1 ns instead of 1.5 ns.
VOH_F
VDDE/2
VOL_F
CLKOUT
2
3
2
4
1
Figure 19. CLKOUT timing
MPC5642A Microcontroller Data Sheet, Rev. 3.1
96
Freescale Semiconductor
Electrical characteristics
VDDE/2
CLKOUT
6
5
VDDE/2
5
OUTPUT
BUS
VDDE/2
6
5
5
OUTPUT
SIGNAL
VDDE/2
6
OUTPUT
SIGNAL
VDDE/2
Figure 20. Synchronous output timing
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
97
Electrical characteristics
CLKOUT
VDDE/2
7
8
INPUT
BUS
VDDE/2
7
8
INPUT
SIGNAL
VDDE/2
Figure 21. Synchronous input timing
System clock
CLKOUT
ALE
TS
A/D
DATA
ADDR
9
10
Figure 22. ALE signal timing
MPC5642A Microcontroller Data Sheet, Rev. 3.1
98
Freescale Semiconductor
Electrical characteristics
3.17.5 External interrupt timing (IRQ pin)
1
Table 42. External interrupt timing
Value
#
Symbol
Characteristic
Unit
Min
Max
1
2
3
tIPWL
tIPWH
tICYC
IRQ Pulse Width Low
3
3
6
—
—
—
tCYC
tCYC
tCYC
IRQ Pulse Width High
IRQ Edge to Edge Time2
1
2
IRQ timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 3.0 V to 5.25 V, VDD33 and VDDSYN = 3.0 V to 3.6 V,
TA = TL to TH.
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
IRQ
2
1
3
Figure 23. External interrupt timing
3.17.6 eTPU timing
1
Table 43. eTPU timing
Value
#
Symbol
Characteristic
Unit
Min
Max
1
2
tICPW
eTPU Input Channel Pulse Width
4
2
—
—
tCYC
tCYC
tOCPW eTPU Output Channel Pulse Width2
1
2
eTPU timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 3.0 V to 5.25 V, VDD33 and VDDSYN = 3.0 V to 3.6 V,
TA = TL to TH, and CL = 50 pF with SRC = 0b00.
This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include
the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
99
Electrical characteristics
3.17.7 eMIOS timing
1
Table 44. eMIOS timing
Value
#
Symbol
C
Characteristic
Unit
Min
Max
1
2
tMIPW
CC
CC
D
D
eMIOS Input Pulse Width
eMIOS Output Pulse Width
4
1
—
—
tCYC
tCYC
tMOPW
1
eMIOS timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH, and CL = 50 pF with
SRC = 0b00.
3.17.8 DSPI timing
DSPI channel frequency support for the MPC5642A MCU is shown in Table 45. Timing specifications are in Table 46.
Table 45. DSPI channel frequency support
System clock
(MHz)
Maximum usable
frequency (MHz)
DSPI Use Mode
Notes
150
LVDS
Non-LVDS
LVDS
37.5
18.75
40
Use sysclock /4 divide ratio
Use sysclock /8 divide ratio
120
Use sysclock /3 divide ratio. Gives 33/66 duty cycle. Use DSPI
configuration DBR = 0b1 (double baud rate), BR = 0b0000
(scaler value 2) and PBR = 0b01 (prescaler value 3).
Non-LVDS
LVDS
20
40
20
Use sysclock /6 divide ratio
Use sysclock /2 divide ratio
Use sysclock /4 divide ratio
80
Non-LVDS
1,2
Table 46. DSPI timing
#
Symbol
C
Characteristic
SCK Cycle Time3,4,5
PCS to SCK Delay6
Condition
Min.
Max.
Unit
1
2
3
4
5
tSCK
tCSC
tASC
tSDC
tA
CC
CC
CC
CC
CC
D
D
D
D
D
24.4 ns
227
2.9 ms
—
—
ns
ns
ns
ns
After SCK Delay8
219
—
SCK Duty Cycle
(½tSC) 2 (½tSC) + 2
Slave Access Time (SS active to
SOUT driven)
—
25
6
tDIS
CC
D
Slave SOUT Disable Time (SS inactive
to SOUT High-Z or invalid)
—
25
ns
7
8
tPCSC CC
tPASC CC
D
D
PCSx to PCSS time
PCSS to PCSx time
410
511
—
—
ns
ns
MPC5642A Microcontroller Data Sheet, Rev. 3.1
100
Freescale Semiconductor
Electrical characteristics
1,2
Table 46. DSPI timing (continued)
#
Symbol
tSUI CC
C
Characteristic
Condition
Min.
Max.
Unit
9
Data Setup Time for Inputs
VDDEH=4.75–5.25 V
VDDEH=3–3.6 V
D
D
D
D
D
D
Master (MTFE = 0)
20
22
2
—
—
—
—
—
—
ns
Slave
Master (MTFE = 1, CPHA = 0)12
8
Master (MTFE = 1, CPHA = 1)
VDDEH=4.75–5.25 V
VDDEH=3–3.6 V
20
22
10
11
tHI
CC
CC
Data Hold Time for Inputs
D
D
D
D
Master (MTFE = 0)
4
7
—
—
—
—
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)12
21
4
Master (MTFE = 1, CPHA = 1)
tSUO
Data Valid (after SCK edge)
VDDEH=4.75–5.25 V
VDDEH=3–3.6 V
D
D
D
D
D
D
D
Master (MTFE = 0)
Slave
—
—
—
—
—
—
—
5
6.3
25
VDDEH=4.75–5.25 V
VDDEH=3–3.6 V
25.7
21
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
VDDEH=4.75–5.25 V
VDDEH=3–3.6 V
5
6.3
12
tHO
CC
Data Hold Time for Outputs
VDDEH=4.75–5.25 V
VDDEH=3–3.6 V
D
D
D
D
D
D
Master (MTFE = 0)
5
6.3
5.5
3
—
—
—
—
—
—
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
VDDEH=4.75–5.25 V
VDDEH=3–3.6 V
5
6.3
1
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type pad_msr. DSPI signals using pad type of
pad_ssr have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0 to 3.6 V, TA = TL to TH,
and CL = 50 pF with SRC = 0b11.
2
3
Data is verified at fSYS = 102 MHz and 153 MHz (100 MHz and 150 MHz + 2% frequency modulation).
The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two MPC5642A devices communicating over a DSPI link.
4
5
The actual minimum SCK cycle time is limited by pad performance.
For DSPI channels using LVDS output operation, up to 40 MHz SCK cycle time is supported. For non-LVDS output,
maximum SCK frequency is 20 MHz. Appropriate clock division must be applied.
6
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
101
Electrical characteristics
7
Timing met when PCSSCK = 3 (01), and CSSCK = 2 (0000)
8
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
9
Timing met when ASC = 2 (0000), and PASC = 3 (01)
10 Timing met when PCSSCK = 3
11 Timing met when ASC = 3
12 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Figure 24. DSPI classic SPI timing (master, CPHA = 0)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
102
Freescale Semiconductor
Electrical characteristics
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Figure 25. DSPI classic SPI timing (master, CPHA = 1)
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Figure 26. DSPI classic SPI timing (slave, CPHA = 0)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
103
Electrical characteristics
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Figure 27. DSPI classic SPI timing (slave, CPHA = 1)
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
10
SIN
First Data
Last Data
Last Data
Data
12
11
SOUT
First Data
Data
Figure 28. DSPI modified transfer format timing (master, CPHA = 0)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
104
Freescale Semiconductor
Electrical characteristics
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Figure 29. DSPI modified transfer format timing (master, CPHA = 1)
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Figure 30. DSPI modified transfer format timing (slave, CPHA = 0)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
105
Electrical characteristics
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Figure 31. DSPI modified transfer format timing (slave, CPHA = 1)
8
7
PCSS
PCSx
Figure 32. DSPI PCS strobe (PCSS) timing
MPC5642A Microcontroller Data Sheet, Rev. 3.1
106
Freescale Semiconductor
Electrical characteristics
3.17.9 eQADC SSI timing
1
Table 47. eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)
CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.
Value
#
Symbol
C
Rating
Unit
Min
Typ
Max
1
1
2
3
fFCK CC D FCK Frequency 2,3
1/17
12
fSYS_CLK
tSYS_CLK
ns
tFCK CC D FCK Period (tFCK = 1/ fFCK
tFCKHT CC D Clock (FCK) High Time
tFCKLT CC D Clock (FCK) Low Time
)
2
tSYS_CLK 6.5
tSYS_CLK 6.5
7.5
17
9 * tSYS_CLK + 6.5
8 * tSYS_CLK + 6.5
7.5
ns
4 tSDS_LL CC D SDS Lead/Lag Time
5 tSDO_LL CC D SDO Lead/Lag Time
ns
7.5
7.5
ns
6
tDVFE CC D Data Valid from FCK Falling Edge
(tFCKLT + tSDO_LL
1
ns
)
7
8
tEQ SU CC D eQADC Data Setup Time (Inputs)
22
1
ns
ns
_
tEQ_HO CC D eQADC Data Hold Time (Inputs)
1
SSI timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH, and CL =
50 pF with SRC = 0b00.
2
3
Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.
FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
1
2
3
FCK
SDS
4
5
4
5
25th
6
1st (MSB)
2nd
26th
SDO
External Device Data Sample at
FCK Falling Edge
8
7
1st (MSB)
2nd
25th
26th
SDI
eQADC Data Sample at
FCK Rising Edge
Figure 33. eQADC SSI timing
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
107
Electrical characteristics
3.17.10 FlexCAN system clock source
Table 48. FlexCAN engine system clock divider threshold
#
Symbol
Characteristic
Value
Unit
1
fCAN_TH
FlexCAN engine system clock threshold
100
MHz
Table 49. FlexCAN engine system clock divider
System frequency
Required SIU_SYSDIV[CAN_SRC] value
fCAN_TH
01,2
12,3
> fCAN_TH
1
2
3
Divides system clock source for FlexCAN engine by 1
System clock is only selected for FlexCAN when CAN_CR[CLK_SRC] = 1
Divides system clock source for FlexCAN engine by 2
MPC5642A Microcontroller Data Sheet, Rev. 3.1
108
Freescale Semiconductor
Packages
4
Packages
4.1
4.1.1
Package mechanical data
176 LQFP
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
109
Packages
Figure 34. 176 LQFP package mechanical drawing (part 1)
Figure 35. 176 LQFP package mechanical drawing (part 2)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
110
Freescale Semiconductor
Packages
Figure 36. 176 LQFP package mechanical drawing (part 3)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
111
Packages
4.1.2
208 MAPBGA
Figure 37. 208 MAPBGA package mechanical drawing (part 1)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
112
Freescale Semiconductor
Packages
Figure 38. 208 MAPBGA package mechanical drawing (part 2)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
113
Packages
4.1.3
324 TEPBGA
Figure 39. 324 BGA package mechanical drawing (part 1)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
114
Freescale Semiconductor
Packages
Figure 40. 324 BGA package mechanical drawing (part 2)
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
115
Ordering information
5
Ordering information
Table 50 shows the orderable part numbers for the MPC5642A series.
Table 50. Orderable part number summary
Part number
Flash/SRAM
Package
Speed (MHz)
SPC5642AF2MLU1
SC667201MMG1
SPC5642AF2MVZ1
SPC5642AF2MLU2
SC667201MMG2
SPC5642AF2MVZ2
SPC5642AF2MLU3
SC667201MMG3
SPC5642AF2MVZ3
2 MB/128 KB
2 MB/128 KB
2 MB/128 KB
2 MB/128 KB
2 MB/128 KB
2 MB/128 KB
2 MB/128 KB
2 MB/128 KB
2 MB/128 KB
176 LQFP (Pb free)
208 MAPBGA (Pb free)
324 TEPBGA
150
176 LQFP (Pb free)
208 MAPBGA (Pb free)
324 TEPBGA
120
80
176 LQFP (Pb free)
208 MAPBGA (Pb free)
324 TEPBGA
Figure 41. Product code structure
Example code:
MPC
5642A
F0
M
VZ
1
Qualification Status
Product Family
ATMC Fab and Mask Revision
Temperature Range
Package
Maximum Frequency
Qualification Status
MPC = Industrial qualified
SPC = Automotive qualified
PC = Prototype
Fab and Mask Revision
F = ATMC
0 = Revision
Package Code
LU = 176 LQFP
MG = 208 MAPBGA
VZ = 324 TEPBGA
Temperature spec.
Product
5642A = MPC5642A family
M = –40 °C to 125 °C
Maximum Frequency
1 = 150 MHz
2 = 120 MHz
3 = 80 MHz
MPC5642A Microcontroller Data Sheet, Rev. 3.1
116
Freescale Semiconductor
Document revision history
6
Document revision history
Table 51 summarizes customer facing revisions to this document.
Table 51. Revision history
Substantive changes
Date
Revision
05 Oct 2010
26 Mar 2012
1
2
Initial release
Figure 1 (MPC5642A series block diagram), added ECSM block and its definition in the
elegend.
Table 2 (MPC5642A series block summary), added the following blocks: REACN, SIU,
ECSM, FMPLL, PIT and SWT.
Updated Table 8 (Absolute maximum ratings)
In 3, Electrical characteristics, deleted the “Recommended operating conditions”
subsection.
Table 14 (PMC operating conditions and external regulators supply voltage), removed
minimum value of VDDREG and its footnote.
Updated Table 15 (PMC electrical characteristics)
Updated Section 3.6.1, Regulator example
Updated Table 20 (DC electrical specifications)
Figure 8 (Core voltage regulator controller external components preferred
configuration), added “T1” label to indicate the transistor.
Table 20 (DC electrical specifications), changed maximum value of VIL_LS to 0.9, was
1.1
Table 21 (I/O pad average IDDE specifications), in the VDDE column changed all 5.5 to
5.25
Table 24 (DSPI LVDS pad specification):
Renamed VOC, was VOD
Updated minimum and maximum value of VOC
deleted all footnote
Table 26 (Temperature sensor electrical characteristics), updated minimum and
maximum value of accuracy
Updated Section 3.12, eQADC electrical characteristics
Added Section 3.13, Configuring SRAM wait states
Updated Table 31 (APC, RWSC, WWSC settings vs. frequency of operation)
Updated Table 32 (Flash program and erase specifications)
Table 31 (APC, RWSC, WWSC settings vs. frequency of operation), changed all values
in the WWSC column to 0b01.
Updated Table 32 (Flash program and erase specifications)
Table 33 (Flash EEPROM module life):
updated temperature value in the Retention description (was 150 C, is 85 C)
added values for Retention
Table 34 (Pad AC specifications (VDDE = 4.75 V)):
changed maximum value of Medium to 12/12
changed maximum value of Slow to 20/20
Updated Table 35 (Pad AC specifications (VDDE = 3.0 V))
Table 37 (JTAG pin AC electrical characteristics):
changed all parameter classification to D
changed minumum value of tTMSS, tTDIS to 10
Updated Table 38 (Nexus debug port timing)
Added Table 39 (Nexus debug port operating frequency)
Table 39 (Nexus debug port operating frequency), added a footnote near the value of
tAAI
Table 44 (eMIOS timing):
changed minumum value of tMOPW to 1
removed the footnote of tMOPW
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
117
Document revision history
Table 51. Revision history (continued)
Substantive changes
Date
Revision
26 Mar 2012
2
Merged “DSPI timing (VDDEH = 3.0 to 3.6 V)” and “DSPI timing (VDDEH = 4.5 to 5.5V)”
tables into Table 46 (DSPI timing,) and changed all parameter classification to D
Table 47 (eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)) changed all
parameter classification to D
(cont’d)
04 May 2012
3
Minor editorial changes and improvements throughout.
In Section 2.4, Signal summary, Table 3 (MPC5642A signal properties), updated the
following properties for the Nexus pins:
• Added a footnote to the “Nexus” title for this pin group.
• Added a footnote to the “Name” entry for EVTO.
• Updated the “Status During reset” entry for EVTO.
In Section 3.2, Maximum ratings, Table 8 (Absolute maximum ratings), removed the
“TBD - To be defined” footnote.
In Section 3.6, Power management control (PMC) and power on reset (POR) electrical
specifications, removed the “Voltage regulator controller (VRC) electrical
specifications” subsection.
In Section 3.8, DC electrical specifications, Table 20 (DC electrical specifications),
removed the “TBD - To be defined” footnote.
In Section 3.9, I/O pad current specifications, Table 21 (I/O pad average IDDE
specifications):
• Updated values and replaced TBDs with numerical data.
• Removed the “TBD - To be defined” footnote.
In Section 3.9.1, I/O pad VRC33 current specifications, Table 22 (I/O pad VRC33 average
IDDE specifications):
• Updated values and replaced TBDs with numerical data.
• Removed the “TBD - To be defined” footnote.
In Section 3.14, Platform flash controller electrical characteristics, Table 31 (APC,
RWSC, WWSC settings vs. frequency of operation), removed the “TBD - To be
defined” footnote.
In Section 5, Ordering information, Table 50 (Orderable part number summary):
• Changed all part numbers from “MPC5642AF0...“ to “SPC5642AF2...“.
• Changed “MPC5642AF0MMG1“ to “SC667201MMG1“.
• Changed “MPC5642AF0MMG2“ to “SC667201MMG2“.
• Changed “MPC5642AF0MMG3“ to “SC667201MMG3“.
In Table 51 (Revision history), removed several erroneous items from the Revision 2
entry.
29 Jun 2012
3.1
No content changes, technical or editorial, were made in this revision.
Removed the “preliminary” footers throughout.
Changed “Data Sheet: Advance Information” to “Data Sheet: Technical Data” on page 1.
Removed the “product under development” disclaimer on page 1.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
118
Freescale Semiconductor
Document revision history
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
119
Document revision history
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