SPXD1010VLQ64R [FREESCALE]
PXD10 Microcontroller; PXD10微控制器
| 型号： | SPXD1010VLQ64R |
| 厂家： | 
Freescale |
| 描述： | PXD10 Microcontroller |
| 文件： | 总130页 (文件大小：717K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: PXD10
Rev. 1, 09/2011
PXD10
208 LQFP
416 TEPBGA
28 mm x 28 mm
27 mm x 27 mm
PXD10 Microcontroller Data
Sheet
176 LQFP
24 mm x 24 mm
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Device comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 PXD10 series blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 PXD10 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pinout and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 144 LQFP package pinouts . . . . . . . . . . . . . . . . . . . . . 27
2.2 176 LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . 29
2.3 Pad configuration during reset phases. . . . . . . . . . . . . 30
2.4 Voltage supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.6 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.7 Debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.8 Port pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 57
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62
3.6 Electromagnetic compatibility (EMC) characteristics . . 65
3.7 Power management electrical characteristics . . . . . . . 67
3.8 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . 75
3.9 SSD specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.10 RESET electrical characteristics . . . . . . . . . . . . . . . . . 84
3.11 Fast external crystal oscillator (4–16 MHz) electrical characteristics87
3.12 Slow external crystal oscillator (32 KHz) electrical characteristics89
3.13 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . 91
3.14 Fast internal RC oscillator (16 MHz) electrical characteristics 92
3.15 Slow internal RC oscillator (128 kHz) electrical characteristics92
3.16 Flash memory electrical characteristics . . . . . . . . . . . . 93
3.17 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 94
3.18 LCD driver electrical characteristics. . . . . . . . . . . . . . 101
3.19 Pad AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . 102
3.20 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.1 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.2 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
The PXD10 family represents a new generation of
32-bit microcontrollers based on the Power
Architecture . These devices provide a
®
cost-effective, single chip display solution for the
industrial market. An integrated TFT driver with
digital video input ability from an external video
source, significant on-chip memory, and low power
design methodologies provide flexibility and
reliability in meeting display demands in rugged
environments. The advanced processor core offers
high performance processing optimized for low
power consumption, operating at speeds as high as
64 MHz. The family itself is fully scalable from
512 KB to 1 MB internal flash memory. The
memory capacity can be further expanded via the
on-chip QuadSPI serial flash controller module.
3
The PXD10 family platform has a single level of
memory hierarchy supporting on-chip SRAM and
flash memories. The 1 MB flash version features
160 KB of on-chip graphics SRAM to buffer cost
effective color TFT displays driven via the on-chip
Display Control Unit (DCU). See Table 1 for
specific memory size and feature sets of the product
family members.
The PXD10 family benefits from the extensive
development infrastructure for Power Architecture
devices, which is already well established. This
includes full support from available software
drivers, operating systems, and configuration code
to assist with users’ implementations. See
Section 3, Developer support, for more
information.
4
5
6
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Overview
1
Overview
1.1
Document overview
This document describes the device features and highlights important electrical and physical
characteristics. For functional characteristics, see the PXD10 Microcontroller Reference Manual.
1.2
Description
The PXD10 family of chips is designed to enable the development of industrial HMI applications by
providing a single-chip solution capable of hosting real-time applications and driving a TFT display
directly using an on-chip color TFT display controller.
®
PXD10 chips incorporate a cost-efficient host processor core compliant with the Power Architecture
embedded category. The processor is 100% user-mode compatible with the Power Architecture and
capitalizes on the available development infrastructure of current Power Architecture devices with full
support from available software drivers, operating systems and configuration code to assist with users'
implementations.
Offering high performance processing at speeds up to 64 MHz, the PXD10 family is optimized for low
power consumption and supports a range of on-chip SRAM and internal flash memory sizes. The version
with 1 MB of flash memory (PXD1010) features 160 KB of on-chip graphics SRAM.
See Table 1 for specific memory and feature sets of the product family members.
1.3
Device comparison
Table 1. PXD10 family feature set
Feature
PXD1005
PXD1010
CPU
e200z0h
Execution speed
Flash (ECC)
Static – 64 MHz
512 KB
No
1 MB
EEPROM Emulation Block (ECC)
RAM (ECC)
4 × 16 KB
48 KB
Graphics RAM
160 KB
MPU
12 entry
eDMA
16 channels
Display Control Unit (DCU)
Parallel Data Interface
Stepper Motor Controller (SMC)
Stepper Stall Detect (SSD)
Sound Generation Logic (SGL)
No
No
Yes
Yes
6 motors
Yes
Yes
PXD10 Microcontroller Data Sheet, Rev. 1
2
Freescale Semiconductor
Overview
Table 1. PXD10 family feature set (continued)
Feature
PXD1005
PXD1010
LCD driver
64 × 6
40 × 4, 38 × 6
32 kHz slow external crystal oscillator
Yes
Yes
Real-Time Counter and Autonomous Periodic
Interrupt
Periodic Interrupt Timer (PIT)
Software Watchdog Timer (SWT)
System Timer Module (STM)
Timed I/O (eMIOS)
4 ch, 32-bit
Yes
4 ch, 32-bit
8 ch, 16-bit IC/OC
16 ch, 16-bit PWM/IC/OC
16 channels, 10-bit
2 × CAN
ADC
CAN (64 Mailboxes)
CAN Sampler
Yes
SCI
2 × UART
SPI
2 × SPI
3 × SPI
Yes
QuadSPI Serial Flash Interface
No
2
I2C
4
GPIO
105
105 (144-pin package)
133 (176-pin package)
Debug
Nexus 1
Nexus 2+
Package
144 LQFP
144 LQFP
176 LQFP
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
3
Overview
1.4
PXD10 series blocks
Block diagram
1.4.1
Figure 1 shows a high-level block diagram of the PXD10 series.
PXD10 Block Diagram
e200z0 Core
Oscillators
BAM
PLL
PIT
Aux PLL
VREG
STM
Integer
Execution
Unit
General
Purpose
Registers
(32 x 32-bit)
INTC
RTC
SWT
Multiply
Unit
Branch
Unit
JTAG
Display
Control
Unit
Instruction
Unit
Nexus2+
Load/Store
Unit
eDMA
VLE
(TFTs)
Instruction Bus
Data Bus
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
RAM
Controller
RAM
Controller
Flash Controller
Peripheral I/O Bridge (PBRIDGE)
QuadSPI
UART/LIN
ADC
SPI
I2C
CAN
SIU
Flash
(ECC)
Flash
(ECC)
EEPROM
(Emulation)
Graphics
SRAM
SRAM
(ECC)
LCD Seg
eMIOS
SMD SSD
ADC
BAM
CAN
ECC
eDMA
eMIOS
I2C
INTC
JTAG
LCD
PIT
– Analog-to-digital converter
– Boot assist module
– Controller area network controller
– Error correction code
– Enhanced direct memory access controller
– Timed input/output
– Inter-integrated circuit controller
– Interrupt controller
RTC
SIU
SMD SSD – Stepper motor driver/stepper stall detect
– Real time clock
– System integration unit
SPI
– Serial peripheral interface controller
– Static random-access memory
– System timer module
SRAM
STM
SWT
– Software watchdog timer
UART/LIN – Universal asynchronous receiver/transmitter/
– Joint Test Action Group interface
– Liquid crystal display
– Periodic interrupt timer
local interconnect network
VLE
VREG
– Variable-length execution set
– Voltage regulator
PLL
– Phase-locked loop
Figure 1. PXD10 series block diagram
PXD10 Microcontroller Data Sheet, Rev. 1
4
Freescale Semiconductor
Overview
1.5
1.5.1
•
PXD10 features
Summary
Single issue, 32-bit Power Architecture technology compliant CPU core complex (e200z0h)
— Compatible with Power Architecture instruction set
— Includes variable length encoding (VLE) instruction set for smaller code size footprint; with
the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code
size footprint reduction over conventional Book E compliant code
•
On-chip ECC flash memory with flash controller
— As much as 1 MB primary flash—two 512 KB modules with prefetch buffer and 128-bit data
access port
— 64 KB data flash—separate 416 KB flash block for EEPROM emulation with prefetch buffer
and 128-bit data access port
•
•
•
As much as 48 KB on-chip ECC SRAM with SRAM controller
As much as 160 KB on-chip non-ECC graphics SRAM with SRAM controller
Memory Protection Unit (MPU) with as many as 12 region descriptors and 32-byte region
granularity to provide basic memory access permission
•
•
Interrupt Controller (INTC) with as many as 127 peripheral interrupt sources and eight software
interrupts
Two Frequency-Modulated Phase-Locked Loops (FMPLLs)
— Primary FMPLL provides a 64 MHz system clock
— Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock
source to eMIOS modules and as alternate clock to the DCU for pixel clock generation
•
•
•
•
Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from
multiple bus masters (AMBA 2.0 v6 AHB)
16-channel Enhanced Direct Memory Access controller (eDMA) with multiple transfer request
sources using a DMA channel multiplexer
Boot Assist Module (BAM) supports internal flash programming via a serial link (FlexCAN or
LINFlex)
Display Control Unit to drive TFT LCD displays
— Includes processing of as many as four planes that can be blended together
— Offers a direct unbuffered hardware bit-blitter of as many as 16 software-configurable dynamic
layers in order to drastically minimize graphic memory requirements and provide fast
animations
— Programmable display resolutions are available up to WVGA
Parallel Data Interface (PDI) for digital video input
•
•
LCD segment driver module with two software programmable configurations:
— As many as 40 frontplane drivers and four backplane drivers
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
5
Overview
— As many as 38 frontplane drivers and six backplane drivers
•
Stepper Motor Controller (SMC) module with high-current drivers for as many as six stepper
motors driven in full dual H-Bridge configuration including full diagnostics for short circuit
detection
•
•
Stepper motor return-to-zero and stall detection module
Sound generation and playback utilizing PWM channels and eDMA; supports monotonic and
polyphonic sound
•
•
24 eMIOS channels providing as many as 16 PWM and 24 input capture / output compare channels
10-bit Analog-to-Digital Converter (ADC)
— Maximum conversion time of 1 µs
— As many as 16 internal channels, expandable to 23 via external multiplexing
•
•
•
As many as two Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous,
communications with external devices (extendable to include up to 8 multiplexed external
channels)
QuadSPI serial flash memory controller supporting single, dual and quad modes of operation to
interface to external serial flash memory. QuadSPI can be configured to function as another DSPI
module.
Two Local Interconnect Network Flexible (LINFlex) controller modules capable of autonomous
message handling (master), autonomous header handling (slave mode), and UART support.
Compliant with LIN protocol rev 2.1
•
•
Two full CAN 2.0B controllers with 64 configurable buffers each; bit rate programmable as fast as
1 Mbit/s
2
As many as four inter-integrated circuit (I C) internal bus controllers with master/slave bus
interface
•
•
As many as 133 configurable general purpose pins supporting input and output operations
Real Time Counter (RTC) with multiple clock sources:
— 128 kHz slow internal RC oscillator or 16 MHz fast internal RC oscillator supporting
autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds
— 32 KHz slow external crystal oscillator, supporting wakeup with 1 s resolution and maximum
timeout of one hour
— 4–16 MHz fast external crystal oscillator
•
System timers:
— Four-channel 32-bit System Timer Module (STM)—included in processor platform
— Four-channel 32-bit Periodic Interrupt Timer (PIT) module
— Software Watchdog Timer (SWT)
•
•
System Integration Unit (SIU) module to manage resets, external interrupts, GPIO and pad control
System Status and Configuration Module (SSCM) to provide information for identification of the
device, last boot mode, or debug status and provides an entry point for the censorship password
mechanism
PXD10 Microcontroller Data Sheet, Rev. 1
6
Freescale Semiconductor
Overview
•
•
Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified
register interface, enabling access to all clock sources
Clock Monitor Unit (CMU) to monitor the integrity of the main crystal oscillator and the PLL and
act as a frequency meter, measuring the frequency of one clock source and comparing it to a
reference clock
•
•
Mode Entry Module (MC_ME) to control the device power mode, i.e., RUN, HALT, STOP, or
STANDBY, control mode transition sequences, and manage the power control, voltage regulator,
clock generation and clock management modules
Reset Generation Module (MC_RGM) to manage reset assertion and release to the device at initial
power-up
•
•
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard
Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
•
•
On-chip voltage regulator controller for regulating the 3.3 or 5 V supply voltage down to 1.2 V for
core logic (requires external ballast transistor)
1
The PXD10 microcontrollers are offered in the following packages:
— 144 LQFP, 0.5 mm pitch, 20 mm 20 mm outline
— 176 LQFP, 0.5 mm pitch, 24 mm 24 mm outline
1.6
Details
1.6.1
Low-power operation
PXD10 devices are designed for optimized low-power operation and dynamic power management of the
core processor and peripherals. Power management features include software-controlled clock gating of
peripherals and multiple power domains to minimize leakage in low-power modes.
There are two static low-power modes, STANDBY and STOP, and two dynamic power modes—RUN and
HALT. Both low power modes use clock gating to halt the clock for all or part of the device. The
STANDBY mode also uses power gating to automatically turn off the power supply to parts of the device
to minimize leakage.
STANDBY mode turns off the power to the majority of the chip to offer the lowest power consumption
mode. The contents of the cores, on-chip peripheral registers and potentially some of the volatile memory
are lost. STANDBY mode is configurable to make certain features available with the disadvantage that
these consume additional current:
•
•
It is possible to retain the contents of the full RAM or only 8 KB.
It is possible to enable the internal 16 MHz or 128 kHz RC oscillator, the external 4–16 MHz
oscillator, or the external 32 KHz oscillator.
•
It is possible to keep the LCD module active.
1. See the device comparison table or orderable parts summary for package offerings for each device in the family.
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
7
Overview
The device can be awakened from STANDBY mode via from any of as many as 19 I/O pins, a reset or
from a periodic wake-up using a low power oscillator.
STOP mode maintains power to the entire device allowing the retention of all on-chip registers and
memory, and providing a faster recovery low power mode than the lowest STANDBY mode. There is no
need to reconfigure the device before executing code. The clocks to the core and peripherals are halted and
can be optionally stopped to the oscillator or PLL at the expense of a slower start-up time.
STOP is entered from RUN mode only. Wake-up from STOP mode is triggered by an external event or by
the internal periodic wake-up, if enabled.
RUN modes are the main operating mode where the entire device can be powered and clocked and from
which most processing activity is done. Four dynamic RUN modes are supported—RUN0 - RUN3. The
ability to configure and select different RUN modes enables different clocks and power configurations to
be supported with respect to each other and to allow switching between different operating conditions. The
necessary peripherals, clock sources, clock speed and system clock prescalers can be independently
configured for each of the four RUN modes of the device.
HALT mode is a reduced activity, low power mode intended for moderate periods of lower processing
activity. In this mode the core system clocks are stopped but user-selected peripheral tasks can continue to
run. It can be configured to provide more efficient power management features (switch-off PLL, flash
memory, main regulator, etc.) at the cost of longer wake up latency. The system returns to RUN mode as
soon as an event or interrupt is pending.
PXD10 Microcontroller Data Sheet, Rev. 1
8
Freescale Semiconductor
Table 1 summarizes the operating modes of PXD10 devices.
1
Table 1. Operating mode summary
SOC features
Clock sources
Wake-up time2
Operating
modes
RUN
On
CG OP OP
CG CG CG On
Off Off3 Off CG4 Off
Off Off
Off 8K5 Off
OP OP
On
On
OP OP
OP OP
On
On
OP
OP
On
On
On
On
On
OP
—
—
FP
FP
—
—
—
—
—
—
—
—
—
—
—
—
—
HALT
On
On
OP OP OP
OP OP OP
OP OP OP
OP OP OP
—
TBD
24 µs
STOP
On CG CG OP OP
LP 50 µs 4 µs 20 µs 1ms 200 µs
STANDBY
Off
Off
Off
Off
OP OP
OP OP
LP 50 µs 8 µs 100 µs 1ms 200 µs Var 28 µs
LP 50 µs 8 µs 100 µs 1ms 200 µs Var 28 µs
POR
500 µs 8 µs 100 µs 1ms 200 µs
BAM
NOTES:
1
Table Key:
On—Powered and clocked
OP—Optionally configurable to be enabled or disabled (clock gated)
CG—Clock Gated, Powered but clock stopped
Off—Powered off and clock gated
FP—VREG Full Performance mode
LP—VREG Low Power mode, reduced output capability of VREG but lower power consumption
Var—Variable duration, based on the required reconfiguration and execution clock speed
BAM—Boot Assist Module Software and Hardware used for device start-up and configuration
2
A high level summary of some key durations that need to be considered when recovering from low power modes. This does not account for all durations
at wake up. Other delays will be necessary to consider including, but not limited to the external supply start-up time.
IRC Wake-up time must not be added to the overall wake-up time as it starts in parallel with the VREG.
All other wake-up times must be added to determine the total start-up time
3
4
5
The LCD can optionally be kept running while the device is in STANDBY mode.
All of the RAM contents is retained, but not accessible in STANDBY mode.
8 KB of the RAM contents is retained, but not accessible in STANDBY mode.
Overview
Additional notes on low power operation:
•
Fast wake-up using the on-chip 16 MHz internal RC oscillator allows rapid execution from RAM
on exit from low power modes
•
The 16 MHz internal RC oscillator supports low speed code execution and clocking of peripherals
when it is selected as the system clock and can also be used as the PLL input clock source to
provide fast start-up without the external oscillator delay
•
PXD10 devices include an internal voltage regulator that includes the following features:
— Regulates input to generate all internal supplies
— Manages power gating
— Low power regulators support operation when in STOP and STANDBY modes to minimize
power consumption
— Startup on-chip regulators in <50 µs for rapid exit of STOP and STANDBY modes
— Low voltage detection on main supply and 1.2 V regulated supplies
1.6.2
e200z0h core processor
The e200z0h processor is similar to other processors in the e200zx series but supports only the VLE
instruction set and does not include the signal processing extension for DSP applications or a floating point
unit.
The e200z0h has all the features of the e200z0 plus:
•
•
Branch acceleration using Branch Target Buffer (BTB)
Supports independent instruction and data accesses to different memory subsystems, such as
SRAM and Flash memory via independent Instruction and Data BIUs
The e200z0h processor uses a four stage in-order pipeline for instruction execution. The Instruction Fetch
(stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory
Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single
clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel
shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a
Count-Leading-Zeros unit (CLZ), an 8 × 32 Hardware Multiplier array, result feed-forward hardware, and
a hardware divider.
Most arithmetic and logical operations are executed in a single cycle with the exception of the divide and
multiply instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit
contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of
flow operations. Branch target prefetching from the BTB is performed to accelerate certain taken branches.
Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch
target prefetching is performed to accelerate taken branches. Prefetched instructions are placed into an
instruction buffer capable of holding four instructions.
Conditional branches not taken execute in a single clock. Branches with successful target prefetching have
an effective execution time of one clock on e200z0h. All other taken branches have an execution time of
two clocks.
PXD10 Microcontroller Data Sheet, Rev. 1
10
Freescale Semiconductor
Overview
Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic
zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These
instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word
instructions allow low overhead context save and restore operations. The load/store unit contains a
dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use
dependency does not incur any pipeline bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register operations defined
by the Power Architecture. The condition register consists of eight 4-bit fields that reflect the results of
certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions,
and provide a mechanism for testing and branching.
Vectored and autovectored interrupts are supported. Hardware vectored interrupt support is provided to
allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This allows the
classic PowerPC instruction set to be represented by a modified instruction set made up from a mixture of
16-bit and 32-bit instructions. This results in a significantly smaller code size footprint without affecting
performance noticeably.
The CPU core is enhanced by an additional interrupt source—Non Maskable Interrupt. This interrupt
source is routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing the
Interrupt Controller completely. Once the edge detection logic is programmed, it can not be disabled,
except by reset. The Non Maskable Interrupt is, as the name suggests, completely un-maskable and when
asserted will always result in the immediate execution of the respective interrupt service routine. The Non
maskable interrupt is not guaranteed to be recoverable.
The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power
STOP mode. When Low Power Stop mode is selected, this instruction is executed to allow the system
clock to be stopped. An external interrupt source or the system wake-up timer is used to restart the system
clock and allow the CPU to service the interrupt.
Additional features include:
•
Load/store unit
— 1-cycle load latency
— Misaligned access support
— No load-to-use pipeline bubbles
•
•
•
•
Thirty-two 32-bit general purpose registers (GPRs)
Separate instruction bus and load/store bus Harvard architecture
Reservation instructions for implementing read-modify-write constructs
Multi-cycle divide (divw) and load multiple (lmw) store multiple (smw) multiple class
instructions, can be interrupted to prevent increases in interrupt latency
•
Extensive system development support through Nexus debug port
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
11
Overview
1.6.3
Display Control Unit (DCU)
The DCU is a display controller designed to drive TFT LCD displays capable of driving up to WQVGA
resolution screens with 16 layers and 4 planes with real time alpha-blending.
The DCU generates all the necessary signals required to drive the display: up to 24-bit RGB data bus, Pixel
Clock, Data Enable, Horizontal-Sync and Vertical-Sync.
Internal memory resource of the PXD10 allows to easily handle complex graphics contents (pictures,
icons, languages, fonts) on a color TFT panel in up to Wide Quarter Video Graphics Array (WQVGA)
sizes. All the data fetches from internal and/or external memory are performed by the internal four-channel
DMA of the DCU providing a high speed/low latency access to the system backbone.
Control Descriptors (CDs) associated with each layer enable effective merging of different resolutions into
one plane to optimize use of internal memory buffers. A layer may be constructed from graphic content of
various resolutions including 1bpp, 2bpp, 4bpp, 8bpp, 16bpp, 24bpp and 24bpp+alpha. The ability of the
DCU to handle input data in resolutions as low as 1bpp, 2bpp and 4bpp enables a highly efficient use of
internal memory resources of the PXD10. A special tiled mode can be enabled on any of the 16 layers to
repeat a pattern optimizing graphic memory usage.
A hardware cursor can be managed independently of the layers at blending level increasing the efficient
use of the internal DCU resources.
To secure the content of all critical information to be displayed, a safety mode can be activated to check
the integrity of critical data along the whole system data path from the memory to the TFT pads.
The DCU features the following:
•
•
•
•
•
•
•
•
•
•
•
•
Display color depth: up to 24 bpp
Generation of all RGB and control signals for TFT
Four-plane blending
Maximum number of Input Layers: 16 (fixed priority)
Dynamic look-up table (color and gamma look-up)
blending range: as many as 256 levels
Transparency Mode
Gamma Correction
Tiled mode on all the layers
Hardware cursor
Critical display content integrity monitoring for functional safety support
Internal Direct Memory Access (DMA) module to transfer data from internal and/or external
memory.
PXD10 Microcontroller Data Sheet, Rev. 1
12
Freescale Semiconductor
Overview
1.6.4
Parallel Data Interface (PDI)
The PDI is a digital interface used to receive external digital video or graphic content into the DCU.
The PDI input is directly injected into the DCU background plane FIFO. When the PDI is activated, all
the DCU synchronization is extracted from the external video stream to guarantee the synchronization of
the two video sources.
The PDI can be used to:
•
•
•
•
Connect a video camera output directly to the PDI
Connect a secondary display driver as slave with a minimum of extra cost
Connect a device gathering various Video sources
Provide flexibility to allow the DCU to be used in slave mode (external synchronization)
The PDI features the following:
•
Supported color modes:
— 8-bit mono
— 8-bit color multiplexed
— RGB565
— 16-bit/18-bit RAW color
Supported synchronization modes:
— Embedded ITU-R BT.656-4 (RGB565 mode 2)
— HSYNC, VSYNC
•
— Data Enable
•
•
Direct interface with DCU background plane FIFO
Synchronization generation for the DCU
1.6.5
Liquid Crystal Display (LCD) driver
The LCD driver module has two configurations allowing a maximum of 160 or 228 LCD segments:
•
•
As many as 40 frontplane drivers and four backplane drivers
As many as 38 frontplane drivers and six backplane drivers
Each segment is controlled and can be masked by a corresponding bit in the LCD RAM.
Four to six multiplex modes (1/1, 1/2, 1/3, 1/4, 1/5, 1/6 duty), and three bias (1/1, 1/2, 1/3) methods are
available. All frontplane and backplane pins can be multiplexed with other port functions.
The LCD driver module features the following:
•
Programmable frame clock generator from different clock sources:
— System clock
— Internal RC oscillator
•
•
Programmable bias voltage level selector
On-chip generation of all output voltage levels
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
13
Overview
— LCD voltage reference taken from main 5V supply
•
•
LCD RAM
— Contains the data to be displayed on the LCD
— Data can be read from or written to the display RAM at any time
End of Frame interrupt
— Optimizes the refresh of the data without visual artefact
— Provides selectable number of frames between each interrupt
Contrast adjustment using programmable internal voltage reference
Remapping capability of four or six backplanes with frontplanes
— Increase pin selection flexibility
•
•
•
In low power modes, the LCD operation can be suspended under software control. The LCD can
also operate in low power modes, clocked by the internal 128 kHz IRC or external 32 KHz crystal
oscillator
•
Selectable output current boost during transitions
1.6.6
Stepper Motor Controller (SMC)
The SMC module is a PWM motor controller suitable to drive loads requiring a PWM signal. The motor
controller has twelve PWM channels associated with two pins each (24 pins in total).
The SMC module includes the following features:
•
•
•
•
•
10/11-bit PWM counter
11-bit resolution with selectable PWM dithering function
Left, right, or center aligned PWM
Output slew rate control
Output Short Circuit Detection
This module is suited for, but not limited to, driving small stepper and air core motors used in
instrumentation applications. This module can be used for other motor control or PWM applications that
match the frequency, resolution, and output drive capabilities of the module.
1.6.7
Stepper Stall Detector (SSD)
The stepper stall detector (SSD) module provides a circuit to measure and integrate the induced voltage
on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (RTZ).
The SSD module features the following:
•
•
•
•
•
Programmable full step state
Programmable integration polarity
Blanking (recirculation) state
16-bit integration accumulator register
16-bit modulus down counter with interrupt
PXD10 Microcontroller Data Sheet, Rev. 1
14
Freescale Semiconductor
Overview
1.6.8
Flash memory
The PXD10 microcontroller has the following flash memory features:
• As much as 1 MB of burst flash memory
— Typical flash memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer miss
at 64 MHz
— Two 4 × 128-bit page buffers with programmable prefetch control
– One set of page buffers can be allocated for code-only, fixed partitions of code and data, all
available for any access
– One set of page buffers allocated to Display Controller Unit and the eDMA
— 64-bit ECC with single-bit correction, double-bit detection for data integrity
— 64 KB data flash memory — separate 4 16 KB flash block for EEPROM emulation with
prefetch buffer and 128-bit data access port
•
Small block flash memory arrangement to support features such as boot block, operating system
block
•
•
•
Hardware managed flash memory writes, erase and verify sequence
Censorship protection scheme to prevent flash memory content visibility
Separate dedicated 64 KB data flash memory for EEPROM emulation
— Four erase sectors each containing 16 KB of memory
— Offers Read-While-Write functionality from main program space
— Same data retention and program erase specification as main program flash memory array
1.6.9
Static random-access memory (SRAM)
The PXD10 microcontrollers have as much as 48 KB general-purpose on-chip SRAM with the following
features:
•
Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit
writes if back to back with a read to same memory block
•
•
•
•
32-bit ECC with single-bit correction, double bit detection for data integrity
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
User transparent ECC encoding and decoding for byte, half word, and word accesses
Separate internal power domain applied to full SRAM block, 8 KB SRAM block during
STANDBY modes to retain contents during low power mode.
1.6.10 On-chip graphics SRAM
The PXD10 microcontroller has 160 KB on-chip graphics SRAM with the following features:
•
•
•
Usable as general purpose SRAM
Typical SRAM access time: 0 wait-state for reads and 32-bit writes
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
15
Overview
1.6.11 QuadSPI serial flash controller
The QuadSPI module enables use of external serial flash memories supporting single, dual and quad
modes of operation. It features the following:
•
•
•
•
•
Memory mapping of external serial flash
Automatic serial flash read command generation by CPU, DMA or DCU read access on AHB bus
Supports single, dual and quad serial flash read commands
Flexible buffering scheme to maximize read bandwidth of serial flash
‘Legacy’ mode allowing QuadSPI to be used as a standard SPI (no DSI or CSI mode)
1.6.12 Analog-to-digital converter (ADC)
The ADC features the following:
•
•
•
•
•
10-bit A/D resolution
0 to 5 V common mode conversion range
Supports conversions speeds of as fast as 1 µs
16 internal and 8 external channels support
As many as 16 single-ended inputs channels
— All channels configured to have alternate function as general purpose input/output pins
– 10-bit ±3 counts accuracy (TUE)
•
External multiplexer support to increase as many as 23 channels
— Automatic 1 × 8 multiplexer control
— External multiplexer connected to a dedicated input channel
— Shared register between the 8 external channels
Result register available for every non-multiplexed channel
Configurable left- or right-aligned result format
Supports for one-shot, scan and injection conversion modes
Injection mode status bit implemented on adjacent 16-bit register for each result
— Supports access to result and injection status with single 32-bit read
Independently enabling of function for channels:
— Pre-sampling
•
•
•
•
•
— Offset error cancellation
— Offset refresh
•
•
Conversion Triggering support
— Internal conversion triggering from periodic interrupt timer (PIT)
Four configurable analog comparator channels offering range comparison with triggered alarm
— Greater than
— Less than
— Out of range
PXD10 Microcontroller Data Sheet, Rev. 1
16
Freescale Semiconductor
Overview
•
•
•
All unused analog inputs can be used as general purpose input and output pins
Power down mode
Optional support for DMA transfer of results
1.6.13 Sound generation logic (SGL) module
The SGL module has two modes of operation:
•
Amplitude modulated PWM mode for low cost buzzers using any two eMIOS channels
— Monophonic signal with amplitude control
— 8-bit amplitude resolution
— Ability to mix any two eMIOS channels.
— Requires simple external RC lowpass filter
Digital sample mode for higher quality sound using one eMIOS channel and eDMA
— Up to 10-bit audio amplitude resolution
— Polyphonic sound synthesis
•
— Playback of sample based waveforms
— Text-to-speech possibility
— Requires external lowpass filter
1.6.14 Serial communication interface module (UART)
The PXD10 devices include as many as two UART modules and support UART Master mode, UART
Slave mode and UART mode. The modules are UART state machine compliant to the UART 1.3 and 2.0
and 2.1 Specifications and handle UART frame transmission and reception without CPU intervention.
The serial communication interface module offers the following:
•
UART features:
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
– Parity, noise and framing errors
— Interrupt driven operation with four interrupts sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— Two receiver wake-up methods
•
LIN features:
— Autonomous LIN frame handling
— Message buffer to store identifier and as many as 8 data bytes
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
17
Overview
— Supports message length of as long as 64 bytes
— Detection and flagging of LIN errors
— Sync field; Delimiter; ID parity; Bit, Framing; Checksum and Timeout errors
— Classic or extended checksum calculation
— Configurable Break duration of up to 36-bit times
— Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features
– Loop back
– Self Test
– LIN bus stuck dominant detection
— Interrupt driven operation with 16 interrupt sources
— LIN slave mode features
– Autonomous LIN header handling
– Autonomous LIN response handling
– Discarding of irrelevant LIN responses using as many as 16 ID filters
1.6.15 Serial Peripheral Interface (SPI) module
The SPI modules provide a synchronous serial interface for communication between the PXD10 MCU and
external devices.
The SPI features the following:
•
•
•
•
•
•
•
•
•
As many as two SPI modules
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
Programmable data frames from four to 16 bits
As many as six chip select lines available, depending on package and pin multiplexing, enable 64
external devices to be selected using external muxing from a single SPI
•
•
•
•
•
Eight clock and transfer attributes registers
Chip select strobe available as alternate function on one of the chip select pins for deglitching
FIFOs for buffering as many as four transfers on the transmit and receive side
General purpose I/O functionality on pins when not used for SPI
Queueing operation possible through use of eDMA
PXD10 Microcontroller Data Sheet, Rev. 1
18
Freescale Semiconductor
Overview
1.6.16 Controller Area Network (CAN) module
The PXD10 contains two CAN modules that offer the following features:
•
•
Compliant with CAN protocol specification, Version 2.0B active
64 mailboxes, each configurable as transmit or receive
— Mailboxes configurable while module remains synchronized to CAN bus
Transmit features
•
— Supports configuration of multiple mailboxes to form message queues of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
Receive features
•
•
— Individual programmable filters for each mailbox
— 8 mailboxes configurable as a 6-entry receive FIFO
— 8 programmable acceptance filters for receive FIFO
Programmable clock source
— System clock
— Direct oscillator clock to avoid PLL jitter
Listen only mode capabilities
•
•
CAN Sampler
— Can catch the first message sent on the CAN network while the PXD10 is stopped. This
guarantees a clean startup of the system without missing messages on the CAN network.
— The CAN sampler is connected to one of the CAN RX pins.
1.6.17 Inter-IC Communications (I2C) module
2
The I C module features the following:
2
•
•
•
•
•
•
•
•
•
•
•
•
•
As many as four I C modules supported
Two-wire bi-directional serial bus for on-board communications
2
Compatibility with I C bus standard
Multimaster operation
Software-programmable for one of 256 different serial clock frequencies
Software-selectable acknowledge bit
Interrupt-driven, byte-by-byte data transfer
Arbitration-lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
19
Overview
1.6.18 Real Time Counter (RTC)
The Real Timer Counter supports wake-up from Low Power modes or Real Time Clock generation
•
Configurable resolution for different timeout periods
— 1 s resolution for >1 hour period
— 1 ms resolution for 2 second period
•
Selectable clock sources from external 32 KHz crystal, external 4–16 MHz crystal, internal
128 kHz RC oscillator or divided internal 16 MHz RC oscillator
1.6.19 Enhanced Modular Input/Output System (Timers, PWM)
PXD10 microcontrollers have two eMIOS modules—one with 16 channels and one with 8—with
input/output channels supporting a range of 16-bit input capture, output compare, and Pulse Width
Modulation functions.
The modules are configurable and can implement 8-channel, 16-bit input capture/output compare or
16-channel, 16-bit output pulse width modulation/input compare/output compare. As many as five
additional channels are configurable as modulus counters.
eMIOS features include:
•
Selectable clock source from main FMPLL, auxiliary FMPLL, external 4–16 MHz oscillator or
16 MHz Internal RC oscillator
•
•
•
•
Timed I/O channels with 16-bit counter resolution
Buffered updates
Support for shifted PWM outputs to minimize occurrence of concurrent edges
Edge aligned output pulse width modulation
— Programmable pulse period and duty cycle
— Supports 0% and 100% duty cycle
— Shared or independent time bases
•
•
•
•
Programmable phase shift between channels
Selectable combination of pairs of eMIOS outputs to support sound generation
DMA transfer support
Selectable clock source from the primary FMPLL, auxiliary FMPLL, external 4–16 MHz
oscillator or the 16 MHz internal RC oscillator.
The channel configuration options for the 16-channel eMIOS module are summarized in Table 2.
PXD10 Microcontroller Data Sheet, Rev. 1
20
Freescale Semiconductor
Overview
Table 2. 16-channel eMIOS module channel configuration
Channel number
8
9–15
16
17–22
PWM
23
Channel mode
IC/OC
IC/OC
PWM
PWM
Counter
Counter
Counter
General Purpose Input/Output
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Single Action Input Capture
Single Action Output Compare
Modulus Counter Buffered1
Output Pulse Width and Frequency Modulation Buffered
Output Pulse Width Modulation Buffered
X
X
NOTES:
1
Modulus up and down counters to support driving local and global counter busses
The channel configuration options for the 8-channel eMIOS module are summarized in Table 3.
Table 3. 8-Channel eMIOS module channel configuration
Channel number
Channel mode
16
17–22
PWM
23
PWM Counter
PWM Counter
General Purpose Input/Output
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Single Action Input Capture
Single Action Output Compare
Modulus Counter Buffered1
Output Pulse Width and Frequency Modulation Buffered
Output Pulse Width Modulation Buffered
X
X
NOTES:
1
Modulus up and down counters to support driving local and global counter busses
1.6.20 Periodic interrupt timer (PIT) module
The PIT features the following:
•
•
•
•
•
Four general purpose interrupt timers
As many as two dedicated interrupt timers for triggering ADC conversions
32-bit counter resolution
Clocked by system clock frequency
32-bit counter for Real Time Interrupt, clocked from main external oscillator
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
21
Overview
1.6.21 System Timer Module (STM)
The STM is a 32-bit timer that supports commonly required system and application software timing
functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate
interrupt source for each channel. The counter is driven by the system clock divided by an 8-bit prescale
value (1 to 256).
•
•
•
•
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode
1.6.22 Software Watchdog Timer (SWT)
The SWT features the following:
•
•
•
•
•
•
Watchdog supporting software activation or enabled out of reset
Supports normal or windowed mode
Watchdog timer value writable once after reset
Watchdog supports optional halting during low power modes
Configurable response on timeout: reset, interrupt, or interrupt followed by reset
Selectable clock source for main system clock or internal 16 MHz RC oscillator clock
1.6.23 Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral
to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC
provides a unique vector for each interrupt request source for quick determination of which ISR needs to
be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the
execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request,
the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority can be raised temporarily so that all tasks which share the resource can not preempt each other.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests.
These same software settable interrupt requests also can be used to break the work involved in servicing an
interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by
a peripheral interrupt request, but then the ISR asserts a software settable interrupt request to finish the servicing
in a lower priority ISR. Therefore these software settable interrupt requests can be used instead of the peripheral
ISR scheduling a task through the RTOS. The INTC provides the following features:
•
•
Unique 9-bit vector for each of the possible 128 separate interrupt sources
Eight software-triggerable interrupt sources
PXD10 Microcontroller Data Sheet, Rev. 1
22
Freescale Semiconductor
Overview
•
•
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Ability to modify the ISR or task priority.
— Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing
shared resources.
•
•
External non-maskable interrupt directly accessing the main core critical interrupt mechanism
32 external interrupts
1.6.24 System Integration Unit (SIU)
The SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O
(GPIO), internal peripheral multiplexing, and the system reset operation.
The GPIO features the following:
•
As many as four levels of internal pin multiplexing, allowing exceptional flexibility in the
allocation of device functions for each package
•
Centralized general purpose input output (GPIO) control of as many as 132 input/output pins
(package dependent)
•
•
•
All GPIO pins can be independently configured to support pull-up, pull down, or no pull
Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
All peripheral pins can be alternatively configured as both general purpose input or output pins
except ADC channels which support alternative configuration as general purpose inputs
•
•
Direct readback of the pin value supported on all digital output pins through the SIU
Configurable digital input filter that can be applied to as many as 14 general purpose input pins for
noise elimination on external interrupts
•
Register configuration protected against change with soft lock for temporary guard or hard lock to
prevent modification until next reset.
1.6.25 System Clocks and Clock Generation Modules
The system clock on the PXD10 can be derived from an external oscillator, an on-chip FMPLL, or the
internal 16 MHz oscillator.
•
The source system clock frequency can be changed via an on-chip programmable clock divider (1
to 2).
•
•
Additional programmable peripheral bus clock divider ratio (1 to 16)
The PXD10 has two on-chip FMPLLs—the primary module and an auxiliary module.
— Each features the following:
– Input clock frequency from 4 MHz to 16 MHz
– Lock detect circuitry continuously monitors lock status
– Loss Of Clock (LOC) detection for reference and feedback clocks
– On-chip loop filter (for improved electromagnetic interference performance and reduction
of number of external components required)
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
23
Overview
– Support for frequency ramping from PLL
— The primary FMPLL module is for use as a system clock source. The auxiliary FMPLL is
available for use as an alternate, modulated or non-modulated clock source to eMIOS modules
and as alternate clock to the DCU for pixel clock generation.
•
The main oscillator provides the following features:
— Input frequency range 4–16 MHz
— Square-wave input mode
— Oscillator input mode 3.3 V (5.0 V)
— Automatic level control
— PLL reference
•
•
PXD10 includes a 32 KHz low power external oscillator for slow execution, low power, and Real
Time Clock
Dedicated internal 128 kHz RC oscillator for low power mode operation and self wake-up
— ±10% accuracy across voltage and temperature (after factory trimming)
— Trimming registers to support improved accuracy with in-application calibration
Dedicated 16 MHz internal RC oscillator
•
— Used as default clock source out of reset
— Provides a clock for rapid start-up from low power modes
— Provides a back-up clock in the event of PLL or External Oscillator clock failure
— Offers an independent clock source for the Watchdog timer
— ±5% accuracy across voltage and temperature (after factory trimming)
— Trimming registers to support frequency adjustment with in-application calibration
1.6.26 Crossbar Switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and
four slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave port but one
of those transfers must be an instruction fetch from internal flash. If a slave port is simultaneously
requested by more than one master port, arbitration logic selects the higher priority master and grants it
ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority
master completes its transactions. Requesting masters having equal priority are granted access to a slave
port in round-robin fashion, based upon the ID of the last master to be granted access.
The crossbar provides the following features:
•
Four master ports
— e200z0h core instruction port
— e200z0h core complex load/store data port
— eDMA controller
— Display control unit
PXD10 Microcontroller Data Sheet, Rev. 1
24
Freescale Semiconductor
Overview
•
Four slave ports
— One flash port dedicated to the CPU
— Platform SRAM
— QuadSPI serial flash controller
— One slave port combining:
– Flash port dedicated to the Display Control Unit and eDMA module
– Graphics SRAM
– Peripheral bridge
•
32-bit internal address bus, 32-bit internal data bus
1.6.27 Enhanced Direct Memory Access (eDMA)
The eDMA module is a controller capable of performing complex data movements via 16 programmable
channels, with minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual data movement
operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the
channels. This implementation is utilized to minimize the overall block size. The eDMA module provides
the following features:
•
•
•
16 channels support independent 8-, 16- or 32-bit single value or block transfers
Supports variable sized queues and circular queues
Source and destination address registers are independently configured to post-increment or remain
constant
•
•
Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request
Each DMA channel can optionally send an interrupt request to the CPU on completion of a single
value or block transfer
2
•
•
DMA transfers possible between system memories, QuadSPI, SPIs, I C, ADC, eMIOS and
General Purpose I/Os (GPIOs)
Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA
channel with a total of as many as 64 potential request sources.
1.6.28
Memory Protection Unit (MPU)
The MPU features the following:
•
•
•
•
•
•
•
12 region descriptors for per-master protection
Start and end address defined with 32-byte granularity
Overlapping regions supported
Protection attributes can optionally include process ID
Protection offered for 3 concurrent read ports
Read and write attributes for all masters
Execute and supervisor/user mode attributes for processor masters
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
25
Overview
1.6.29 Boot Assist Module (BAM)
The BAM is a block of read-only memory that is programmed once by Freescale. The BAM program is
executed every time the MCU is powered-on or reset in normal mode. The BAM supports different modes
of booting. They are:
•
•
•
Booting from internal flash memory
Serial boot loading (A program is downloaded into RAM via CAN or UART and then executed)
Booting from external memory
Additionally, the BAM:
•
•
•
Enables and manages the transition of the MCU from reset to user code execution
Configures device for serial bootload
Enables multiple bootcode starting locations out of reset through implementation of search for
valid Reset Configuration Halfword
•
Enables or disables software watchdog timer out of reset through BAM read of the Reset
Configuration Halfword option bit
1.6.30 IEEE 1149.1 JTAG Controller (JTAGC)
JTAGC features the following:
•
•
Backward compatible to standard JTAG IEEE 1149.1-2001 test access port (TAP) interface
Support for boundary scan testing
1.6.31 Nexus Development Interface (NDI)
Nexus features the following:
•
•
Per IEEE-ISTO 5001-2003
Nexus 2 Plus features supported
— Static debug
— Watchpoint messaging
— Ownership trace messaging
— Program trace messaging
— Real time read/write of any internally memory mapped resources through JTAG pins
— Overrun control, which selects whether to stall before Nexus overruns or keep executing and
allow overwrite of information
— Watchpoint triggering, watchpoint triggers program tracing
•
•
Configured via the IEEE 1149.1 (JTAG) port
Nexus Auxiliary port supported on the 176 LQFP package FOR DEVELOPMENT ONLY
— Narrow Auxiliary Nexus port supporting support trace, with two MDO pins
— Wide Auxiliary Nexus port supporting higher bandwidth trace, with four MDO pins
PXD10 Microcontroller Data Sheet, Rev. 1
26
Freescale Semiconductor
Pinout and signal descriptions
2
Pinout and signal descriptions
2.1
144 LQFP package pinouts
This section shows the pinouts for the 144-pin LQFP packages.
CAUTION
Any pins labeled “NC” must not be connected to any external circuit.
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
(see detail inset) PA10
(see detail inset) PA11
(see detail inset) PA12
(see detail inset) PA13
(see detail inset) PA14
(see detail inset) PA15
VDDE_A
PB11/GPIO[27]/CANTX_1/PDI3/eMIOSA16
PB10GPIO[26]//CANRX_1/PDI2/eMIOSA23
PB0/GPIO[16]/CANTX_0/PDI1
PB1/GPIO[17]/CANRX_0/PDI0
VSS12
VDD12
PE7/GPIO[69]/M5C1P/SSD5_3/eMIOSA8
PE6/GPIO[68]/M5C1M/SSD5_2/eMIOSA9
PE5/GPIO[67]/M5C0P/SSD5_1/eMIOSA10
PE4/GPIO[66]/M5C0M/SSD5_0/eMIOSA11
VSSMC
VSSE_A
9
(see detail inset) PG0
FP6/SDA_3/DCU_B1/GPIO[87]/PG1
(see detail inset) PG2
(see detail inset) PG3
(see detail inset) PG4
FP2/eMIOSA8/DCU_B5/GPIO[91]/PG5
FP1/DCU_B6/GPIO[92]/PG6
FP0/DCU_B7/GPIO[93]/PG7
BP0/DCU_VSYNC/GPIO[94]/PG8
BP1/DCU_HSYNC/GPIO[95]/PG9
BP2/DCU_DE/GPIO[96]/PG10
BP3/DCU_PCLK/GPIO[97]/PG11
VLCD/GPIO[104]/PH5
VDDR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VDDMC
PE3/GPIO[65]/M4C1P/SSD4_3/eMIOSA12
PE2/GPIO[64]/M4C1M/SSD4_2/eMIOSA13
PE1/GPIO[63]/M4C0P/SSD4_1/eMIOSA14
PE0/GPIO[62]/M4C0M/SSD4_0/eMIOSA15
PD15/GPIO[61]/M3C1P/SSD3_3
PD14/GPIO[60]/M3C1M/SSD3_2
PD13/GPIO[59]/M3C0P/SSD3_1
PD12/GPIO[58/M3C0M/SSD3_0
VSSMB
144-Pin
LQFP
PXD1010
VDDMB
VSSR
RESET
VRC_CTRL
VPP
XTAL
VSSOSC
EXTAL
PD11/GPIO[57]/M2C1P/SSD2_3
PD10/GPIO[56]/M2C1M/SSD2_2
PD9/GPIO[55]/M2C0P/SSD2_1
PD8/GPIO[54]/M2C0M/SSD2_0
PD7/GPIO[53]/M1C1P/SSD1_3/eMIOSB16
PD6/GPIO[52]/M1C1M/SSD1_2/eMIOSB17
PD5/GPIO[51]/M1C0P/SSD1_1/eMIOSB18
PD4/GPIO[50]/M1C0M/SSD1_0/eMIOSB19
VSSMA
Detail:
FP13/eMIOSB20/DCU_G2/GPIO[10]/PA10 –
FP12/eMIOSA13/DCU_G3/GPIO[11]/PA11 –
FP11/eMIOSA12/DCU_G4/GPIO[12]/PA12 –
FP10/eMIOSA11/DCU_G5/GPIO[13]/PA13 –
FP9/eMIOSA10/DCU_G6/GPIO[14]/PA14 –
FP8/eMIOSA9/DCU_G7/GPIO[15]/PA15 –
FP7/SOUND/SCL_3/DCU_B0/GPIO[86]/PG0 –
FP5/eMIOSB19/DCU_B2/GPIO[88]/PG2 –
FP4/eMIOSB21/DCU_B3/GPIO[89]/PG3 –
FP3/eMIOSB17/DCU_B4/GPIO[90]/PG4 –
VSSPLL
VDDPLL
VREG_BYPASS
VDDMA
TDI/GPIO[100]/PH1
TDO/GPIO[101]/PH2
TMS/GPIO[102]/PH3
TCK/GPIO[99]/PH0
PD3/GPIO[49]/M0C1P/SSD0_3/eMIOSB20
PD2/GPIO[48]/M0C1M/SSD0_2/eMIOSB21
PD1/GPIO[47]/M0C0P/SSD0_1/eMIOSB22
PD0/GPIO[46]/M0C0M/SSD0_0/eMIOSB23
74
73
Figure 2. 144-pin LQFP pinout for PXD1010
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
27
Pinout and signal descriptions
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
(see detail inset) PA10
(see detail inset) PA11
(see detail inset) PA12
(see detail inset) PA13
(see detail inset) PA14
(see detail inset) PA15
VDDE_A
PB11/GPIO[27]/CANTX_1/eMIOSA16
PB10GPIO[26]//CANRX_1/eMIOSA23
PB0/GPIO[16]/CANTX_0
PB1/GPIO[17]/CANRX_0
VSS12
VDD12
PE7/GPIO[69]/M5C1P/SSD5_3/eMIOSA8
PE6/GPIO[68]/M5C1M/SSD5_2/eMIOSA9
PE5/GPIO[67]/M5C0P/SSD5_1/eMIOSA10
PE4/GPIO[66]/M5C0M/SSD5_0/eMIOSA11
VSSMC
VSSE_A
9
(see detail inset) PG0
FP6/GPIO[87]/PG1
(see detail inset) PG2
(see detail inset) PG3
(see detail inset) PG4
FP2/eMIOSA8/GPIO[91]/PG5
FP1/GPIO[92]/PG6
FP0/GPIO[93]/PG7
BP0/GPIO[94]/PG8
BP1/GPIO[95]/PG9
BP2/GPIO[96]/PG10
BP3/GPIO[97]/PG11
VLCD/GPIO[104]/PH5
VDDR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VDDMC
PE3/GPIO[65]/M4C1P/SSD4_3/eMIOSA12
PE2/GPIO[64]/M4C1M/SSD4_2/eMIOSA13
PE1/GPIO[63]/M4C0P/SSD4_1/eMIOSA14
PE0/GPIO[62]/M4C0M/SSD4_0/eMIOSA15
PD15/GPIO[61]/M3C1P/SSD3_3
PD14/GPIO[60]/M3C1M/SSD3_2
PD13/GPIO[59]/M3C0P/SSD3_1
PD12/GPIO[58/M3C0M/SSD3_0
VSSMB
144-pin
LQFP
PXD1005
VDDMB
VSSR
RESET
VRC_CTRL
VPP
XTAL
VSSOSC
EXTAL
PD11/GPIO[57]/M2C1P/SSD2_3
PD10/GPIO[56]/M2C1M/SSD2_2
PD9/GPIO[55]/M2C0P/SSD2_1
PD8/GPIO[54]/M2C0M/SSD2_0
PD7/GPIO[53]/M1C1P/SSD1_3/eMIOSB16
PD6/GPIO[52]/M1C1M/SSD1_2/eMIOSB17
PD5/GPIO[51]/M1C0P/SSD1_1/eMIOSB18
PD4/GPIO[50]/M1C0M/SSD1_0/eMIOSB19
VSSMA
Detail:
FP13/eMIOSB20/GPIO[10]/PA10 –
FP12/eMIOSA13/GPIO[11]/PA11 –
FP11/eMIOSA12/GPIO[12]/PA12 –
FP10/eMIOSA11/GPIO[13]/PA13 –
FP9/eMIOSA10/GPIO[14]/PA14 –
FP8/eMIOSA9/GPIO[15]/PA15 –
FP7/SOUND/GPIO[86]/PG0 –
FP5/eMIOSB19/GPIO[88]/PG2 –
FP4/eMIOSB21/GPIO[89]/PG3 –
FP3/eMIOSB17/GPIO[90]/PG4 –
VSSPLL
VDDPLL
VREG_BYPASS
TDI/GPIO[100]/PH1
TDO/GPIO[101]/PH2
TMS/GPIO[102]/PH3
TCK/GPIO[99]/PH0
VDDMA
PD3/GPIO[49]/M0C1P/SSD0_3/eMIOSB20
PD2/GPIO[48]/M0C1M/SSD0_2/eMIOSB21
PD1/GPIO[47]/M0C0P/SSD0_1/eMIOSB22
PD0/GPIO[46]/M0C0M/SSD0_0/eMIOSB23
74
73
Figure 3. 144-pin LQFP pinout for PXD1005
PXD10 Microcontroller Data Sheet, Rev. 1
28
Freescale Semiconductor
Pinout and signal descriptions
2.2
176 LQFP package pinout
Figure 4 shows the pinout for the 176-pin LQFP package.
CAUTION
Any pins labeled “NC” must not be connected to any external circuit.
(see detail inset) PA10
(see detail inset) PA11
(see detail inset) PA12
(see detail inset) PA13
(see detail inset) PA14
(see detail inset) PA15
VDDE_A
PB11/GPIO[27]/CANTX_1/PDI3/eMIOSA16
PB10/GPIO[26]/CANRX_1/PDI2/eMIOSA23
PB0/GPIO[16]/CANTX_0/PDI1
PB1/GPIO[17]/CANRX_0/PDI0
PJ11/GPIO[116]/PDI7
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
2
3
4
5
PJ10/GPIO[115]/PDI6
6
PJ9/GPIO[114]/PDI5
PJ8/GPIO[113]/PDI4
VSS12
VDD12
PJ3/GPIO[108]/PDI_PCLK
PJ2/GPIO[107]/PDI_VSYNC
PJ1/GPIO[106]/PDI_HSYNC
PJ0/GPIO[105]/PDI_DE
7
VSSE_A
8
(see detail inset) PG0
(see detail inset) PG1
(see detail inset) PG2
(see detail inset) PG3
(see detail inset) PG4
(see detail inset) PG5
FP1/DCU_B6/GPIO[92]/PG6
FP0/DCU_B7/GPIO[93]/PG7
(see detail inset) PG8
(see detail inset) PG9
BP2/DCU_DE/GPIO[96]/PG10
(see detail inset) PG11
VLCD/GPIO[104]/PH5
VDDR
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PE7/GPIO[69]/M5C1P/SSD5_3/eMIOSA8
PE6/GPIO[68]/M5C1M/SSD5_2/eMIOSA9
PE5/GPIO[67]/M5C0P/SSD5_1/eMIOSA10
PE4/GPIO[66]/M5C0M/SSD5_0/eMIOSA11
VSSMC
VDDMC
PE3/GPIO[65]/M4C1P/SSD4_3/eMIOSA12
PE2/GPIO[64]/M4C1M/SSD4_2/eMIOSA13
PE1/GPIO[63]/M4C0P/SSD4_1/eMIOSA14
PE0/GPIO[62]/M4C0M/SSD4_0/eMIOSA15
PD15/GPIO[61]/M3C1P/SSD3_3
PD14/GPIO[60]/M3C1M/SSD3_2
PD13/GPIO[59]/M3C0P/SSD3_1
PD12/GPIO[58]/M3C0M/SSD3_0
VSSMB
176-Pin
LQFP
VSSR
RESET
VRC_CTRL
VPP
Detail:
XTAL
FP13/eMIOSB20/DCU_G2/GPIO[10]/PA10 –
VSSOSC
FP12/eMIOSA13/DCU_G3/GPIO[11]/PA11 –
FP11/eMIOSA12/DCU_G4/GPIO[12]/PA12 –
FP10/eMIOSA11/DCU_G5/GPIO[13]/PA13 –
FP9/eMIOSA10/DCU_G6/GPIO[14]/PA14 –
FP8/eMIOSA9/DCU_G7/GPIO[15]/PA15 –
FP7/SOUND/SCL_3/DCU_B0/GPIO[86]/PG0 –
FP6/SDA_3/DCU_B1/GPIO[87]/PG1 –
FP5/eMIOSB19/DCU_B2/GPIO[88]/PG2 –
FP4/eMIOSB21/DCU_B3/GPIO[89]/PG3 –
FP3/eMIOSB17/DCU_B4/GPIO[90]/PG4 –
FP2/eMIOSA8/DCU_B5/GPIO[91]/PG5 –
BP0/DCU_VSYNC/GPIO[94]/PG8 –
EXTAL
VSSPLL
VDDMB
VDDPLL
PD11/GPIO[57]/M2C1P/SSD2_3
PD10/GPIO[56]/M2C1M/SSD2_2
PD9/GPIO[55]/M2C0P/SSD2_1
PD8/GPIO[54]/M2C0M/SSD2_0
PD7/GPIO[53]/M1C1P/SSD1_3/eMIOSB16
PD6/GPIO[52]/M1C1M/SSD1_2/eMIOSB17
PD5/GPIO[51]/M1C0P/SSD1_1/eMIOSB18
PD4/GPIO[50]/M1C0M/SSD1_0/eMIOSB19
VSSMA
VREG_BYPASS
PDI10/MCKO/GPIO[123]/PK2
PDI11/MSEO/GPIO[124]/PK3
PDI12/EVTO/GPIO[125]/PK4
TDI/GPIO[100]/PH1
PDI13/EVTI/GPIO[126]/PK5
PDI14/MDO0/GPIO[127]/PK6
TDO/GPIO[101]/PH2
PDI15/MDO1/GPIO[128]/PK7
TMS/GPIO[102]/PH3
PDI16/MDO2/GPIO[129]/PK8
TCK/GPIO[99]/PH0
PDI17/MDO3/GPIO[130]/PK9
98
97
96
95
94
VDDMA
93
BP1/DCU_HSYNC/GPIO[95]/PG9 –
BP3/DCU_PCLK/GPIO[97]/PG11 –
PD3/GPIO[49]/M0C1P/SSD0_3/eMIOSB20
PD2/GPIO[48]/M0C1M/SSD0_2/eMIOSB21
PD1/GPIO[47]/M0C0P/SSD0_1/eMIOSB22
PD0/GPIO[46]/M0C0M/SSD0_0/eMIOSB23
92
91
90
89
Figure 4. 176-pin LQFP pinout
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
29
Pinout and signal descriptions
2.3
Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are floating with the following exceptions:
•
•
•
•
•
PB[5] (FAB) is pull-down. Without external strong pullup the device starts fetching from flash.
RESET pad is driven low. This is released only after PHASE2 reset completion.
Main oscillator pads (EXTAL, XTAL) are tristate.
Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.
The following pads are pullup:
— PB[6]
— PH[0]
— PH[1]
— PH[3]
— EVTI
2.4
Voltage supply pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V
regulator stabilization.
There is a preferred power-up sequence for devices in the PXD10 family. That sequence is described in
the following paragraphs.
Broadly, the supply voltages can be grouped as follows:
•
•
VREG HV supply (V
Generic I/O supply
)
DDR
— V
— V
— V
— V
— V
— V
— V
— V
— V
DDA
DDE_A
DDE_B
DDE_C
DDE_E
DDMA
DDMB
DDMC
DDPLL
•
LV supply (V
)
DD12
The preferred order of ramp up is as follows:
1. Generic I/O supply
PXD10 Microcontroller Data Sheet, Rev. 1
30
Freescale Semiconductor
Pinout and signal descriptions
2. VREG HV supply (V
- Should be the last HV supply to ramp up. It is also OK if all HV and
DDR
generic I/O supplies including V
ramp up together)
DDR
3. LV supply
The reason for following this sequence is to ensure that when VREG releases its LVDs, the I/O and other
HV segments are powered properly. This is important because the PXD10 does not monitor LVDs on I/O
HV supplies.
Table 2. Voltage supply pin descriptions
Pin number
Supply Pin
Function
144 LQFP
176 LQFP
VDD121
VDDA
1.2 V core supply
42, 51, 103, 118, 133
50, 67, 123, 148, 163
3.3 V/5 V ADC supply source
3.3 V/5 V I/O supply
3.3 V/5 V I/O supply
3.3 V/5 V I/O supply
3.3 V/5 V I/O supply
Motor pads 5 V supply
Motor pads 5 V supply
Motor pads 5 V supply
1.2 V PLL supply
53
7, 124
38
69
7, 154, 170
46, 64
79
VDDE_A
VDDE_B
VDDE_C
VDDE_E
VDDMA2
VDDMB2
VDDMC2
VDDPLL
VDDR
63
109
77
133
93
87
103
97
113
31
31
VREG reg supply
22
22
VPP3
9 V - 12 V flash test analog write signal
Digital ground
26
26
VSS
8, 23, 39, 43, 52, 64, 104,
110, 119, 125, 134
8, 23, 47, 51, 68, 80, 124,
134, 149, 155, 164, 65, 171
VSSA
VSSMA
VSSMB
VSSMC
VSSOSC
VSSPLL
ADC ground
54
78
88
98
28
30
70
94
Stepper motor ground
Stepper motor ground
Stepper motor ground
MHz oscillator ground
PLL ground
104
114
28
30
NOTES:
1
2
3
Decoupling capacitors must be connected between these pins and the nearest VSS12 pin.
All stepper motor supplies need to be at same level (3.3 V or 5 V).
This signal needs to be connected to ground during normal operation.
2.5
Pad types
The pads available for system pins and functional port pins are described in:
•
•
The port pin summary table
The pad type descriptions
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
31
Pinout and signal descriptions
•
•
The description of the pad configuration registers in Chapter 37, System Integration Unit Lite
(SIUL)
The device data sheet
2.6
System pins
The system pins are listed in Table 3.
Table 3. System pin descriptions
Pin No.
I/O
Pad
RESET
config
System pin
Function
208 MAPBG
A
direction type
144 LQFP 176 LQFP
RESET
Bidirectional reset with
Schmitt-Trigger
characteristics and noise
filter.
I/O
M
X
X
Input, weak
pull up
24
29
27
24
29
27
J1
M1
K1
EXTAL
XTAL
Analog output of the
oscillator amplifier circuit.
Input for the clock generator
in bypass mode.
—
—
Analog input of the
oscillator amplifier circuit.
Needs to be grounded if
oscillator bypass mode is
used.
I
VRC_CTRL VREG ballast control gain
—
I
—
X
—
—
25
32
25
32
P1
VREG_
Pin used for factory testing
M4
BYPASS1
NOTES:
1
VREG_BYPASS should be pulled down externally.
2.7
Debug pins
The debug pins are listed in Table 4 and Table 5.
Table 4. Debug pin descriptions
Pin number
Pad
type
I/O
direction
Reset
Configuration
Debug pin
Function
176 LQFP 208 MAPB
144 LQFP
1
GA
EVTI
EVTO
MCKO
Nexus event input
Nexus event output
M
M
F
I/O
I/O
I/O
None
None
None
—
—
—
37
35
33
A11
D12
B12
Nexus message clock
output
MDO0
Nexus message clock
output
M
I/O
None
—
38
B11
PXD10 Microcontroller Data Sheet, Rev. 1
32
Freescale Semiconductor
Pinout and signal descriptions
Table 4. Debug pin descriptions (continued)
Pin number
Pad
type
I/O
direction
Reset
Configuration
Debug pin
Function
176 LQFP 208 MAPB
144 LQFP
1
GA
MDO1
MDO2
MDO3
MSEO
Nexus message clock
output
M
M
M
M
I/O
I/O
I/O
I/O
None
None
None
None
—
—
—
—
40
C11
Nexus message clock
output
42
44
34
D11
A10
C12
Nexus message clock
output
Nexus message clock
output
NOTES:
1
On the 176 LQFP package options the Nexus pins are multiplexed with other GPIO. On the 208 TEPBGA package,
there are additional dedicated Nexus pins.
Table 5. Debug pin descriptions
Pin number
Pad
type
I/O
direction
Reset
Configuration
Debug pin
Function
TEPBGA2
08 1
144 LQFP 176 LQFP
EVTI
EVTO
MCKO
Nexus event input
Nexus event output
M
M
F
I/O
I/O
I/O
Input, Pull Up
Input, Pull Up
Input, Pull Up
—
—
—
—
—
—
T3
R3
T1
Nexus message clock
output
MDO0
MDO1
MDO2
MDO3
MSEO
Nexus message clock
output
M
M
M
M
M
I/O
I/O
I/O
I/O
I/O
Input, Pull Up
Input, Pull Up
Input, Pull Up
Input, Pull Up
Input, Pull Up
—
—
—
—
—
—
—
—
—
—
T5
P5
P4
L4
T2
Nexus message clock
output
Nexus message clock
output
Nexus message clock
output
Nexus message clock
output
NOTES:
1
The dedicated (208 pin package only) Nexus output pins (Message Data outputs 0:3 [MDO] and Message Start/End
outputs 0:1 [MSEO]) may drive an unknown value (high or low) immediately after power up but before-the 1st clock
edge propagates through the device (instead of being weakly pulled low). This may cause high currents if the pins
are tied directly to a supply/ground or any low resistance-driver (when used as a general purpose input [GPI] in the
application).
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
33
2.8
Port pin summary
The functional port pins are listed in Table 6.
Table 6. Port pin summary
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
PA[6]
PA[7]
PCR[0] Option 0
Option 1
GPIO[0]
FP23
FP22
FP21
FP20
FP19
FP18
FP17
FP16
SIUL
DCU
PWM/Timer
Sound
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1
M1
M1
M1
M1
M1
M1
M1
None,
None
135
165
DCU_R0
eMIOSA[22]
SOUND
Option 2
Option 3
PCR[1] Option 0
Option 1
GPIO[1]
DCU_R1
eMIOSA[21]
—
SIUL
DCU
PWM/Timer
—
None,
None
136
137
138
139
140
141
142
166
167
168
169
172
173
174
Option 2
Option 3
PCR[2] Option 0
Option 1
GPIO[2]
DCU_R2
eMIOSA[20]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
PCR[3] Option 0
Option 1
GPIO[3]
DCU_R3
eMIOSA[19]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
PCR[4] Option 0
Option 1
GPIO[4]
DCU_R4
eMIOSA[18]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
PCR[5] Option 0
Option 1
GPIO[5]
DCU_R5
eMIOSA[17]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
PCR[6] Option 0
Option 1
GPIO[6]
DCU_R6
eMIOSA[15]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
PCR[7] Option 0
Option 1
GPIO[7]
DCU_R7
eMIOSA[16]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PA[8]
PCR[8] Option 0
Option 1
GPIO[8]
FP15
FP14
FP13
FP12
FP11
FP10
FP9
SIUL
DCU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1
M1
M1
M1
M1
M1
M2
M1
None,
None
143
175
DCU_G0
eMIOSB[23]
SCL_2
Option 2
Option 3
PWM/Timer
I2C_2
PA[9]
PCR[9] Option 0
Option 1
GPIO[9]
SIUL
DCU
None,
None
144
1
176
1
DCU_G1
eMIOSB[18]
SDA_2
Option 2
Option 3
PWM/Timer
I2C_2
PA[10]
PA[11]
PA[12]
PA[13]
PA[14]
PA[15]
PCR[10] Option 0
Option 1
GPIO[10]
DCU_G2
eMIOSB[20]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
PCR[11] Option 0
Option 1
GPIO[11]
DCU_G3
eMIOSA[13]
—
SIUL
DCU
PWM/Timer
—
None,
None
2
2
Option 2
Option 3
PCR[12] Option 0
Option 1
GPIO[12]
DCU_G4
eMIOSA[12]
—
SIUL
DCU
PWM/Timer
—
None,
None
3
3
Option 2
Option 3
PCR[13] Option 0
Option 1
GPIO[13]
DCU_G5
eMIOSA[11]
—
SIUL
DCU
PWM/Timer
—
None,
None
4
4
Option 2
Option 3
PCR[14] Option 0
Option 1
GPIO[14]
DCU_G6
eMIOSA[10]
—
SIUL
DCU
PWM/Timer
—
None,
None
5
5
Option 2
Option 3
PCR[15] Option 0
Option 1
GPIO[15]
DCU_G7
eMIOSA[9]
—
FP8
SIUL
DCU
PWM/Timer
—
None,
None
6
6
Option 2
Option 3
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PB[0]
PB[1]
PB[2]
PB[3]
PB[4]
PB[5]
PB[6]
PB[7]
PCR[16] Option 0
Option 1
GPIO[16]
CANTX_0
PDI1
—
—
—
—
—
—
—
—
SIUL
FlexCAN_0
PDI
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1
S
None,
None
106
130
Option 2
Option 3
—
PCR[17] Option 0
Option 1
GPIO[17]
CANRX_0
PDI0
SIUL
FlexCAN_0
PDI
None,
None
105
112
111
48
129
140
139
62
Option 2
Option3
—
—
PCR[18] Option 0
Option 1
GPIO[18]
TXD_0
—
SIUL
LINFlex_0
—
—
S
None,
None
Option 2
Option3
—
PCR[19] Option 0
Option 1
GPIO[19]
RXD_0
—
SIUL
LINFlex_0
—
—
S
None,
None
Option 2
Option3
—
PCR[20] Option 0
Option 1
GPIO[20]
SCK_1
MA0
SIUL
DSPI_1
ADC
—
M1
M1
S
None,
None
Option 2
Option 3
—
PCR[21] Option 0
Option 1
GPIO[21]
SOUT_1
MA1
SIUL
DSPI_1
ADC
Input,
Pulldown
49
63
Option 2
Option 3
FABM
Control
PCR[22] Option 0
Option 1
GPIO[22]
SIN_1
MA2
SIUL
DSPI_1
ADC
Input,
Pullup
50
66
Option 2
Option 3
ABS[0]
Control
PCR[23] Option 0
Option 1
GPIO[23]
SIN_0
eMIOSB[22]
—
SIUL
S
None,
None
46
56
DSPI_0
PWM/Timer
—
Option 2
Option 3
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PB[8]
PCR[24] Option 0
Option 1
GPIO[24]
—
—
—
—
—
—
SIUL
I/O
I/O
I/O
I/O
I/O
I/O
M1
M1
S
None,
None
45
55
SOUT_0
eMIOSB[21]
—
DSPI_0
PWM/Timer
—
Option 2
Option 3
PB[9]
PCR[25] Option 0
Option 1
GPIO[25]
SCK_0
eMIOSB[20]
—
SIUL
None,
None
44
107
108
40
54
131
132
48
DSPI_0
PWM/Timer
—
Option 2
Option 3
PB[10] PCR[26] Option 0
GPIO[26]
CANRX_1
PDI2
SIUL
FlexCAN_1
PDI
None,
None
Option 1
Option 2
Option 3
eMIOSA[23]
PWM/Timer
PB[11] PCR[27] Option 0
GPIO[27]
CANTX_1
PDI3
SIUL
FlexCAN_1
PDI
M1
S
None,
None
Option 1
Option 2
Option 3
eMIOSA[16]
PWM/Timer
PB[12] PCR[28] Option 0
GPIO[28]
RXD_1
eMIOSB[19]
PCS2_0
SIUL
None,
None
Option 1
Option 2
Option 3
LINFlex_1
PWM/Timer
DSPI_0
PB[13] PCR[29] Option 0
GPIO[29]
TXD_1
eMIOSB[18]
PCS1_0
SIUL
S
None,
None
41
49
Option 1
Option 2
Option 3
LINFlex_1
PWM/Timer
DSPI_0
PB[14]
PB[15]
PC[0]
—
—
—
—
Reserved
Reserved
—
—
—
—
—
—
—
—
J
—
—
—
—
72
—
—
88
PCR[30] Option 0
Option 1
GPIO[30]
ANS[0]
SIUL
—
—
I/O
None,
None
—
—
—
Option 2
Option 3
—
PC[1]
PCR[31] Option 0
Option 1
GPIO[31]
ANS[1]
SIUL
—
—
I/O
J
None,
None
71
87
—
—
—
Option 2
Option 3
—
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PC[2]
PC[3]
PC[4]
PC[5]
PC[6]
PC[7]
PC[8]
PC[9]
PCR[32] Option 0
Option 1
GPIO[32]
ANS[2]
ANS[3]
ANS[4]
ANS[5]
ANS[6]
ANS[7]
ANS[8]
ANS[9]
SIUL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J
J
J
J
J
J
J
J
None,
None
70
86
—
—
—
—
—
—
Option 2
Option 3
PCR[33] Option 0
Option 1
GPIO[33]
SIUL
—
—
None,
None
69
68
67
66
65
62
61
85
84
83
82
81
78
77
—
—
—
Option 2
Option 3
—
PCR[34] Option 0
Option 1
GPIO[34]
SIUL
—
—
None,
None
—
—
—
Option 2
Option 3
—
PCR[35] Option 0
Option 1
GPIO[35]
SIUL
—
—
None,
None
—
—
—
Option 2
Option 3
—
PCR[36] Option 0
Option 1
GPIO[36]
SIUL
—
—
None,
None
—
—
—
Option 2
Option 3
—
PCR[37] Option 0
Option 1
GPIO[37]
SIUL
—
—
None,
None
—
—
—
Option 2
Option 3
—
PCR[38] Option 0
Option 1
GPIO[38]
SIUL
—
—
None,
None
—
—
—
Option 2
Option 3
—
PCR[39] Option 0
Option 1
GPIO[39]
SIUL
—
—
None,
None
—
—
—
Option 2
Option 3
—
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PC[10] PCR[40] Option 0
GPIO[40]
—
SOUND
—
ANS[10]
ANS[11]
ANS[12]
ANS[13]
SIUL
—
SGL
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J
None,
None
60
76
Option 1
Option 2
Option 3
PC[11] PCR[41] Option 0
GPIO[41]
—
MA0
SIUL
—
ADC
DSPI_1
J
None,
None
59
58
57
56
55
73
74
75
74
73
72
71
89
90
Option 1
Option 2
Option 3
PCS2_1
PC[12] PCR[42] Option 0
GPIO[42]
—
MA1
SIUL
—
ADC
DSPI_1
J
J
None,
None
Option 1
Option 2
Option 3
PCS1_1
PC[13] PCR[43] Option 0
GPIO[43]
—
MA2
SIUL
—
ADC
DSPI_1
None,
None
Option 1
Option 2
Option 3
PCS0_1
PC[14] PCR[44] Option 0
GPIO[44]
ANS[14]
EXTAL32
SIUL
—
—
J
None,
None
Option 1
Option 2
Option 3
—
—
—
—
PC[15] PCR[45] Option 0
GPIO[45]
ANS[15]
XTAL32
SIUL
—
—
J
None,
None
Option 1
Option 2
Option 3
—
—
—
—
PD[0]
PD[1]
PCR[46] Option 0
Option 1
GPIO[46]
M0C0M
SSD0_0
—
—
SIUL
SMC
SSD
PWM/Timer
SMD
SMD
None,
None
Option 2
Option 3
eMIOSB[23]
PCR[47] Option 0
Option 1
GPIO[47]
M0C0P
SIUL
SMC
None,
None
Option 2
SSD0_1
SSD
Option 3
eMIOSB[22]
PWM/Timer
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PD[9]
PCR[48] Option 0
Option 1
GPIO[48]
M0C1M
SSD0_2
eMIOSB[21]
—
—
—
—
—
—
—
—
SIUL
SMC
SSD
PWM/Timer
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SMD
SMD
SMD
SMD
SMD
SMD
SMD
SMD
None,
None
75
91
Option 2
Option 3
PCR[49] Option 0
Option 1
GPIO[49]
M0C1P
SSD0_3
SIUL
SMC
SSD
PWM/Timer
None,
None
76
79
80
81
82
83
84
92
95
Option 2
Option 3
eMIOSB[20]
PCR[50] Option 0
Option 1
GPIO[50]
M1C0M
SSD1_0
SIUL
SMC
SSD
PWM/Timer
None,
None
Option 2
Option 3
eMIOSB[19]
PCR[51] Option 0
Option 1
GPIO[51]
M1C0P
SSD1_1
SIUL
SMC
SSD
PWM/Timer
None,
None
96
Option 2
Option 3
eMIOSB[18]
PCR[52] Option 0
Option 1
GPIO[52]
M1C1M
SSD1_2
SIUL
SMC
SSD
PWM/Timer
None,
None
97
Option 2
Option 3
eMIOSB[17]
PCR[53] Option 0
Option 1
GPIO[53]
M1C1P
SSD1_3
SIUL
SMC
SSD
PWM/Timer
None,
None
98
Option 2
Option 3
eMIOSB[16]
PCR[54] Option 0
Option 1
GPIO[54]
M2C0M
SSD2_0
—
SIUL
SMC
SSD
—
None,
None
99
Option 2
Option 3
PCR[55] Option 0
Option 1
GPIO[55]
M2C0P
SSD2_1
—
SIUL
SMC
SSD
—
None,
None
100
Option 2
Option 3
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PD[10] PCR[56] Option 0
GPIO[56]
—
—
—
—
—
—
—
—
SIUL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SMD
SMD
SMD
SMD
SMD
SMD
SMD
SMD
None,
None
85
101
Option 1
Option 2
Option 3
M2C1M
SSD2_2
—
SMC
SSD
—
PD[11] PCR[57] Option 0
GPIO[57]
M2C1P
SSD2_3
—
SIUL
SMC
SSD
—
None,
None
86
89
90
91
92
93
94
102
105
106
107
108
109
110
Option 1
Option 2
Option 3
PD[12] PCR[58] Option 0
GPIO[58]
M3C0M
SSD3_0
—
SIUL
SMC
SSD
—
None,
None
Option 1
Option 2
Option 3
PD[13] PCR[59] Option 0
GPIO[59]
M3C0P
SSD3_1
—
SIUL
SMC
SSD
—
None,
None
Option 1
Option 2
Option 3
PD[14] PCR[60] Option 0
GPIO[60]
M3C1M
SSD3_2
—
SIUL
SMC
SSD
—
None,
None
Option 1
Option 2
Option 3
PD[15] PCR[61] Option 0
GPIO[61]
M3C1P
SSD3_3
—
SIUL
SMC
SSD
—
None,
None
Option 1
Option 2
Option 3
PE[0]
PE[1]
PCR[62] Option 0
Option 1
GPIO[62]
M4C0M
SSD4_0
SIUL
SMC
SSD
PWM/Timer
None,
None
Option 2
Option 3
eMIOSA[15]
PCR[63] Option 0
Option 1
GPIO[63]
M4C0P
SIUL
SMC
None,
None
Option 2
SSD4_1
SSD
Option 3
eMIOSA[14]
PWM/Timer
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PE[2]
PE[3]
PE[4]
PE[5]
PE[6]
PE[7]
PCR[64] Option 0
Option 1
GPIO[64]
M4C1M
SSD4_2
eMIOSA[13]
—
—
—
—
—
—
SIUL
SMC
SSD
PWM/Timer
I/O
I/O
I/O
I/O
I/O
I/O
SMD
SMD
SMD
SMD
SMD
SMD
None,
None
95
111
Option 2
Option 3
PCR[65] Option 0
Option 1
GPIO[65]
M4C1P
SSD4_3
SIUL
SMC
SSD
PWM/Timer
None,
None
96
99
112
115
116
117
118
Option 2
Option 3
eMIOSA[12]
PCR[66] Option 0
Option 1
GPIO[66]
M5C0M
SSD5_0
SIUL
SMC
SSD
PWM/Timer
None,
None
Option 2
Option 3
eMIOSA[11]
PCR[67] Option 0
Option 1
GPIO[67]
M5C0P
SSD5_1
SIUL
SMC
SSD
PWM/Timer
None,
None
100
101
102
Option 2
Option 3
eMIOSA[10]
PCR[68] Option 0
Option 1
GPIO[68]
M5C1M
SSD5_2
eMIOSA[9]
SIUL
SMC
SSD
PWM/Timer
None,
None
Option 2
Option 3
PCR[69] Option 0
Option 1
GPIO[69]
M5C1P
SIUL
SMC
None,
None
Option 2
Option 3
SSD5_3
eMIOSA[8]
SSD
PWM/Timer
PE[8]
PE[9]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PE[10]
PE[11]
PE[12]
PE[13]
PE[14]
PE[15]
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PCR[70] Option 0
Option 1
GPIO[70]
eMIOSA[13]
PDI4
FP39
FP38
—
SIUL
PWM/Timer
PDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
S
None,
None
113
143
Option 2
Option 3
eMIOSA[22]
PWM/Timer
PCR[71] Option 0
Option 1
GPIO[71]
eMIOSA[12]
PDI5
SIUL
PWM/Timer
PDI
None,
None
114
37
144
45
Option 2
Option 3
eMIOSA[21]
PWM/Timer
PCR[72] Option 0
Option 1
GPIO[72]
NMI
—
SIUL
NMI
—
S
None,
None
Option 2
Option 3
—
—
PCR[73] Option 0
Option 1
GPIO[73]
eMIOSA[11]
PDI6
FP37
FP36
FP35
FP34
FP33
SIUL
PWM/Timer
PDI
M1
M1
M1
S
None,
None
115
116
117
120
121
145
146
147
150
151
Option 2
Option 3
—
—
PCR[74] Option 0
Option 1
GPIO[74]
eMIOSA[10]
PDI7
SIUL
PWM/Timer
PDI
None,
None
Option 2
Option 3
—
—
PCR[75] Option 0
Option 1
GPIO[75]
eMIOSA[9]
DCU_TAG
—
SIUL
PWM/Timer
DCU
None,
None
Option 2
Option 3
—
PCR[76] Option 0
Option 1
GPIO[76]
SDA_0
—
SIUL
I2C_0
—
None,
None
Option 2
Option 3
—
—
PCR[77] Option 0
Option 1
GPIO[77]
SCL_0
PCS2_1
—
SIUL
I2C_0
DSPI_1
—
S
None,
None
Option 2
Option 3
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PF[8]
PCR[78] Option 0
Option 1
GPIO[78]
FP32
FP31
FP29
FP28
FP27
FP26
FP25
FP24
SIUL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
None,
None
122
152
SDA_1
PCS1_1
RXD_1
I2C_1
Option 2
Option 3
DSPI_1
LINFlex_1
PF[9]
PCR[79] Option 0
Option 1
GPIO[79]
SCL_1
PCS0_1
TXD_1
SIUL
S
None,
None
123
127
128
129
130
131
132
153
157
158
159
160
161
162
I2C_1
Option 2
Option 3
DSPI_1
LINFlex_1
PF[10]
PF[11]
PF[12]
PF[13]
PF[14]
PF[15]
PCR[80] Option 0
Option 1
GPIO[80]
eMIOSA[16]
PCS0_2
—
SIUL
M1
M1
M1
M1
M1
F
None,
None
PWM/Timer
QuadSPI
—
Option 2
Option 3
PCR[81] Option 0
Option 1
GPIO[81]
eMIOSB[23]
IO2/PCS1_26
—
SIUL
None,
None
PWM/Timer
QuadSPI
—
Option 2
Option 3
PCR[82] Option 0
Option 1
GPIO[82]
eMIOSB[16]
IO3/PCS2_26
—
SIUL
None,
None
PWM/Timer
QuadSPI
—
Option 2
Option 3
PCR[83] Option 0
Option 1
GPIO[83]
IO0/SIN_26
CANRX_1
—
SIUL
None,
None
QuadSPI
FlexCAN_1
—
Option 2
Option 3
PCR[84] Option 0
Option 1
GPIO[84]
IO1/SOUT_26
CANTX_1
—
SIUL
None,
None
QuadSPI
FlexCAN_1
—
Option 2
Option 3
PCR[85] Option 0
Option 1
GPIO[85]
SCK_2
—
SIUL
QuadSPI
—
None,
None
Option 2
Option 3
—
—
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PG[0]
PG[1]
PG[2]
PG[3]
PG[4]
PG[5]
PG[6]
PG[7]
PCR[86] Option 0
Option 1
GPIO[86]
DCU_B0
SCL_3
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
SIUL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M2
M1
M2
M1
M2
M1
M2
M1
None,
None
9
9
DCU
I2C_3
SGL
Option 2
Option 3
SOUND
PCR[87] Option 0
Option 1
GPIO[87]
DCU_B1
SDA_3
—
SIUL
DCU
I2C_3
—
None,
None
10
11
12
13
14
15
16
10
11
12
13
14
15
16
Option 2
Option 3
PCR[88] Option 0
Option 1
GPIO[88]
DCU_B2
eMIOSB[19]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
PCR[89] Option 0
Option 1
GPIO[89]
DCU_B3
eMIOSB[21]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
PCR[90] Option 0
Option 1
GPIO[90]
DCU_B4
eMIOSB[17]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
PCR[91] Option 0
Option 1
GPIO[91]
DCU_B5
eMIOSA[8]
—
SIUL
DCU
PWM/Timer
—
None,
None
Option 2
Option 3
PCR[92] Option 0
Option 1
GPIO[92]
DCU_B6
—
SIUL
DCU
—
None,
None
Option 2
Option 3
—
—
PCR[93] Option 0
Option 1
GPIO[93]
DCU_B7
—
SIUL
DCU
—
None,
None
Option 2
Option 3
—
—
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PG[8]
PCR[94] Option 0
Option 1
GPIO[94]
DCU_VSYNC
—
—
BP0
BP1
BP2
BP3
FP30
SIUL
DCU
—
I/O
I/O
I/O
I/O
I/O
M2
M1
M2
M1
S
Input,
None
17
17
Option 2
Option 3
—
PG[9]
PCR[95] Option 0
Option 1
GPIO[95]
DCU_HSYNC
—
—
SIUL
DCU
—
Input,
None
18
19
18
19
Option 2
Option 3
—
PG[10] PCR[96] Option 0
GPIO[96]
DCU_DE
—
SIUL
DCU
—
None,
None
Option 1
Option 2
Option 3
—
—
PG[11] PCR[97] Option 0
GPIO[97]
DCU_PCLK
—
—
SIUL
DCU
—
None,
None
20
20
Option 1
Option 2
Option 3
—
PG[12] PCR[98] Option 0
GPIO[98]
eMIOSA[23]
SOUND
SIUL
PWM/Timer
SGL
None,
None
126
156
Option 1
Option 2
Option 3
eMIOSA[8]
PWM/Timer
PG[13]
PG[14]
PG[15]
PH[0]7
—
—
—
—
—
—
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
S
—
—
—
—
—
—
36
—
—
—
43
—
PCR[99] Option 0
Option 1
GPIO[99]
TCK
—
SIUL
JTAG
—
I/O
Input,
Pullup
Option 2
Option 3
—
—
PH[1]7 PCR[100] Option 0
GPIO[100]
TDI
—
—
SIUL
JTAG
—
I/O
S
Input,
Pullup
33
36
Option 1
Option 2
Option 3
—
—
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PH[2]7 PCR[101] Option 0
GPIO[101]
TDO
—
—
—
—
—
SIUL
JTAG
—
I/O
I/O
I/O
I/O
M1
S
Output,
None
34
39
Option 1
Option 2
Option 3
—
—
PH[3]7 PCR[102] Option 0
GPIO[102]
TMS
—
SIUL
JTAG
—
Input,
Pullup
35
47
21
41
61
21
Option 1
Option 2
Option 3
—
—
PH[4] PCR[103] Option 0
GPIO[103]
PCS0_0
eMIOSB[16]
CLKOUT
SIUL
F
None,
None
Option 1
Option 2
Option 3
DSPI_0
PWM/Timer
Control
PH[5] PCR[104] Option 0
GPIO[104]
VLCD8
—
SIUL
LCD
—
S
None,
None
Option 1
Option 2
Option 3
—
—
PH[6]
PH[7]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I/O
—
—
—
—
—
—
—
—
—
—
S
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
119
PH[8]
PH[9]
PH[10]
PH[11]
PH[12]
PH[13]
PH[14]
PH[15]
PJ[0]
PCR[105] Option 0
Option 1
GPIO[105]
PDI_DE
—
SIUL
PDI
—
None,
None
Option 2
Option 3
—
—
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PJ[1]
PJ[2]
PJ[3]
PJ[4]
PJ[5]
PJ[6]
PJ[7]
PJ[8]
PCR[106] Option 0
Option 1
GPIO[106]
PDI_HSYNC
—
—
—
—
—
—
—
—
—
—
SIUL
PDI
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
S
None,
None
—
120
Option 2
Option 3
—
PCR[107] Option 0
Option 1
GPIO[107]
PDI_VSYNC
—
—
SIUL
PDI
—
None,
None
—
—
—
—
—
—
—
121
122
57
Option 2
Option 3
—
PCR[108] Option 0
Option 1
GPIO[108]
PDI_PCLK
—
—
SIUL
PDI
—
M1
S
None,
None
Option 2
Option 3
—
PCR[109] Option 0
Option 1
GPIO[109]
PDI[0]
CANRX_0
—
SIUL
PDI
FlexCAN_0
—
None,
None
Option 2
Option 3
PCR[110] Option 0
Option 1
GPIO[110]
PDI[1]
CANTX_0
—
SIUL
PDI
FlexCAN_0
—
M1
S
None,
None
58
Option 2
Option 3
PCR[111] Option 0
Option 1
GPIO[111]
PDI[2]
CANRX_1
eMIOSA[22]
SIUL
PDI
FlexCAN_1
PWM/Timer
None,
None
59
Option 2
Option 3
PCR[112] Option 0
Option 1
GPIO[112]
PDI[3]
CANTX_1
eMIOSA[21]
SIUL
PDI
FlexCAN_1
PWM/Timer
M1
S
None,
None
60
Option 2
Option 3
PCR[113] Option 0
Option 1
GPIO[113]
PDI[4]
—
SIUL
PDI
—
None,
None
125
Option 2
Option 3
—
—
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PJ[9]
PCR[114] Option 0
Option 1
GPIO[114]
PDI[5]
—
—
—
—
—
—
—
—
—
SIUL
PDI
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
None,
None
—
126
Option 2
Option 3
—
—
PJ[10] PCR[115] Option 0
GPIO[115]
PDI[6]
—
SIUL
PDI
—
S
None,
None
—
—
—
—
—
—
—
127
128
135
136
137
138
141
Option 1
Option 2
Option 3
—
—
PJ[11] PCR[116] Option 0
GPIO[116]
PDI[7]
—
SIUL
PDI
—
S
None,
None
Option 1
Option 2
Option 3
—
—
PJ[12] PCR[117] Option 0
GPIO[117]
PDI[8]
eMIOSB[17]
—
SIUL
PDI
PWM/Timer
—
M1
M1
M1
M1
M1
None,
None
Option 1
Option 2
Option 3
PJ[13] PCR[118] Option 0
GPIO[118]
PDI[9]
eMIOSB[20]
—
SIUL
PDI
PWM/Timer
—
None,
None
Option 1
Option 2
Option 3
PJ[14] PCR[119] Option 0
GPIO[119]
PDI[10]
eMIOSA[20]
—
SIUL
PDI
PWM/Timer
—
None,
None
Option 1
Option 2
Option 3
PJ[15] PCR[120] Option 0
GPIO[120]
PDI[11]
eMIOSA[19]
—
SIUL
PDI
PWM/Timer
—
None,
None
Option 1
Option 2
Option 3
PK[0]
PCR[121] Option 0
Option 1
GPIO[121]
PDI[12]
SIUL
PDI
None,
None
Option 2
Option 3
eMIOSA[18]
DCU_TAG
PWM/Timer
DCU
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PK[1]
PK[2]
PK[3]
PK[4]
PK[5]
PK[6]
PK[7]
PK[8]
PCR[122] Option 0
Option 1
GPIO[122]
—
—
—
—
—
—
—
—
SIUL
PDI
PWM/Timer
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1
F
None,
None
—
142
PDI[13]
eMIOSA[17]
—
Option 2
Option 3
PCR[123] Option 0
Option 1
GPIO[123]
MCKO
PDI[10]
—
SIUL
Nexus
PDI
None,
None
—
—
—
—
—
—
—
33
34
35
37
38
40
42
Option 2
Option 3
—
PCR[124] Option 0
Option 1
GPIO[124]
MSEO
PDI[11]
—
SIUL
Nexus
PDI
M1
M1
M1
M1
M1
M1
None,
None
Option 2
Option 3
—
PCR[125] Option 0
Option 1
GPIO[125]
EVTO
PDI[12]
—
SIUL
Nexus
PDI
None,
None
Option 2
Option 3
—
PCR[126] Option 0
Option 1
GPIO[126]
EVTI
PDI[13]
—
SIUL
Nexus
PDI
None,
None
Option 2
Option 3
—
PCR[127] Option 0
Option 1
GPIO[127]
MDO0
PDI[14]
—
SIUL
Nexus
PDI
None,
None
Option 2
Option 3
—
PCR[128] Option 0
Option 1
GPIO[128]
MDO1
PDI[15]
—
SIUL
Nexus
PDI
None,
None
Option 2
Option 3
—
PCR[129] Option 0
Option 1
GPIO[129]
MDO2
PDI[16]
—
SIUL
Nexus
PDI
None,
None
Option 2
Option 3
—
Table 6. Port pin summary (continued)
Pin number
Port
pin
PCR
register
Alternate
function1
Special
I/O
Pad
RESET
Function
Peripheral3
function2
direction type4 config.5
144 LQFP
176 LQFP
PK[9]
PCR[130] Option 0
Option 1
GPIO[130]
—
—
—
SIUL
I/O
I/O
I/O
M1
S
None,
None
—
44
MDO3
PDI[17]
—
Nexus
PDI
—
Option 2
Option 3
PK[10] PCR[131] Option 0
GPIO[131]
SDA_1
eMIOSA[15]
—
SIUL
None,
None
—
—
52
53
Option 1
Option 2
Option 3
I2C_1
PWM/Timer
—
PK[11] PCR[132] Option 0
GPIO[132]
SCL_1
eMIOSA[14]
—
SIUL
S
None,
None
Option 1
Option 2
Option 3
I2C_1
PWM/Timer
—
PK[12]
PK[13]
PK[14]
PK[15]
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NOTES:
1
Alternate functions are chosen by setting the values of the PCR[n].PA bitfields inside the SIUL module. PCR[n].PA = 00 Option 0; PCR[nn.PA = 01
Option 1; PCR[n].PA = 10 Option 2; PCR[n].PA = 11 Option 3. This is intended to select the output functions; to use one of the input functions, the
PCR[n].IBE bit must be written to ‘1’, regardless of the values selected in the PCR[n].PA bitfields. For this reason, the value corresponding to an input only
function is reported as “—”.
2
3
Special functions are enabled independently from the standard digital pin functions. Enabling standard I/O functions in the PCR registers may interfere with
their functionality. ADC functions are enabled using the PCR[APC] bit; other functions are enabled by enabling the respective module.
Using the PSMI registers in the System Integration Unit Lite (SIUL), different pads can be multiplexed to the same peripheral input. Please see the SIUL chapter
of the PXD10 Microcontroller Reference Manual for details.
4
5
6
7
8
See Table 7.
Reset configuration is given as I/O direction and pull, e.g., “Input, Pullup”.
This option on this pin has alternate functions that depend on whether the QuadSPI is in SPI mode or in serial flash mode (SFM).
Out of reset pins PH[0:3] are available as JTAG pins (TCK, TDI, TDO and TMS respectively). It is up to the user to configure pins PH[0:3] when needed.
This pin can be used for LCD supply pin VLCD. Refer to the voltage supply pin descriptions in the PXD10 data sheet for details.
Pinout and signal descriptions
Abbreviation1
Table 7. Pad type descriptions
Description
F
J
Fast (with GPIO and digital alternate function)
Slow pads with analog muxing (built for ADC channels)
Medium (with GPIO and digital alternate function)
M1
M2
Programmable medium/slow pad (programmed via the slew rate control in the PCR):
Slew rate disabled: Slow driver configuration (AC/DC parameters same as for a slow pad)
Slew rate enabled: Medium driver configuration (AC/DC parameters same as for a medium pad)
S
SMD
X
Slow (with GPIO and digital alternate function)
Stepper motor driver (with slew rate control)
Oscillator
NOTES:
1
The pad descriptions refer to the different Pad Configuration Register (PCR) types. Refer to the SIUL chapter in the
device reference manual for the features available for each pad type.
2.8.1
Signal details
Table 8. Signal details
Signal
Peripheral
Description
ABS[0]
BAM
ADC
ADC
Alternate Boot Select. Gives an option to boot by downloading code
via CAN or LIN.
ANS[0:15]
MA[0:2]
Inputs used to bring into the device sensor-based signals for A/D
conversion. ANS[0:15] connect to ATD channels [32:47].
These three control bits are output to enable the selection for an
external Analog Mux for expansion channels. The available 8
multiplexed channels connect to ATD channels [64:71].
FABM
Force Alternate Boot mode. Forces the device to boot from the
external bus (Can or LIN). If not asserted, the device boots up from
the lowest flash sector containing a valid boot signature.
DCU
Indicates that valid pixels are present.
DCU_DE
DCU_HSYNC
DCU
DCU
Horizontal sync pulse for TFT-LCD display
Output pixel clock for TFT-LCD display
DCU_PCLK
DCU_R[0:7],
DCU_G[0:7],
DCU_B[0:7]
DCU
Red, green and blue color 8-bit Pixel values for TFT-LCD displays
DCU_TAG
DCU
DCU
DSPI
Indicates when a tagged pixel is present in safety mode
Vertical sync pulse for TFT-LCD display
DCU_VSYNC
PCS[0..2]_0,
PCS[0..2]_1
Peripheral chip selects when device is in Master mode; not used in
slave modes.
SCK_0,
SCK_1
DSPI
SPI clock signal—bidirectional
PXD10 Microcontroller Data Sheet, Rev. 1
52
Freescale Semiconductor
Pinout and signal descriptions
Table 8. Signal details (continued)
Peripheral Description
Signal
SIN_0,
SIN_1
DSPI
SPI data input signal
SOUT_0,
SOUT_1
DSPI
SPI data output signal
PCS0_2
QuadSPI
QuadSPI
QuadSPI
QuadSPI
QuadSPI
QuadSPI
eMIOS
Peripheral chip select for serial flash mode or chip select 0 for SPI
master mode
IO2/PCS1_2
IO3/PCS2_2
IO0/SIN_2
IO1/SOUT_2
SCK_2
Chip select 1 for SPI master mode and bidirectional IO2 for serial
flash mode
Chip select 2 for SPI master mode and bidirectional IO3 for serial
flash mode
Data input signal for SPI master and slave modes and bidirectional
IO0 for serial flash mode
Data output signal for SPI master and slave modes and bidirectional
IO1 for serial flash mode
Clock output signal for SPI master and serial flash modes and clock
input signal for SPI slave mode
eMIOSA[8:23],
eMIOSB[16:23]
Enhanced Modular Input Output System. 16+8 channel eMIOS for
timed input or output functions.
CANRX_0,
CANRX_1
FlexCAN
Receive (RX) pins for the CAN bus transceiver
CANTX_0, CANTX_1 FlexCAN
Transmit (TX) pins for the CAN bus transceiver
SCL_0,
SCL_1,
SCL_2,
SCL_3
I2C
Bidirectional serial clock compatible with I2C specifications
SDA_0,
SDA_1,
SDA_2,
SDA_3
I2C
Bidirectional serial data compatible with I2C specifications
Debug port serial clock as per JTAG specifications
TCK
TDI
JTAG
JTAG
Debug port serial data input port as per JTAG standards
specifications
TDO
TMS
JTAG
JTAG
Debug port serial data output port as per JTAG standards
specifications
Debug port Test Mode Select signal for the JTAG TAP controller state
machine and indicates various state transitions for the TAP controller
in the device
BP[0:3]
LCD
Backplane signals from the LCD controlling the backplane reference
voltage for the LCD display
FP[0:39]
EVTI
LCD
Frontplane signals for LCD segments
Nexus2+ event input trigger
Nexus
Nexus
EVTO
Nexus2+ event output trigger
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
53
Pinout and signal descriptions
Signal
Table 8. Signal details (continued)
Peripheral
Nexus
Description
MCKO
Output clock for the development tool
MDO[0:3]
Nexus
Message output port pins that send information bits to the
development tools for messages such as Branch Trace Message
(BTM), Ownership Trace Message (OTM), Data Trace Message
(DTM). Only available in reduced port mode.
MSEO
Nexus
Output pin—Indicates the start or end of the variable length message
on the MDO pins
PDI[0:17]
PDI_DE
DCU (PDI)
DCU (PDI)
Video/graphic data in various RGB modes input to the DCU
Input signal indicates the validity of pixel data on the Input PDI data
bus.
PDI_HSYNC
DCU (PDI)
Input indicates the timing reference for the start of each frame line for
the PDI Input data.
PDI_PCLK
DCU (PDI)
DCU (PDI)
Input pixel clock from PDI
PDI_VSYNC
Input indicates the timing reference for the start of a frame for the PDI
input data.
RXD_0
RXD_1
TXD_0
TXD_1
SOUND
LINFlex
LINFlex
LINFlex
LINFlex
SCI/LIN Receive data signal—This port is used to download the code
for the BAM boot sequence.
SCI/LIN Receive data signal. Input pad for the LIN SCI module.
Connects to the internal LIN second port.
SCI/LIN Transmit data signal. This port is used to download the code
for the BAM boot sequence.
SCI/LIN Transmit data signal—Transmit (output) port for the second
LIN module in the chip
SGL
SSD
Sound signal to the speaker/buzzer
SSD[0:5]_0
SSD[0:5]_1
SSD[0:5]_2
SSD[0:5]_3
Bidirectional control of stepper motors using stall detection module
M[0:5]C0M
M[0:5]C0P
M[0:5]C1M
M[0:5]C1P
SMC
Controls stepper motors in various configuration
CLKOUT
MC_CGM
Output clock—It can be selected from several internal clocks of the
device from the clock generation module.
PXD10 Microcontroller Data Sheet, Rev. 1
54
Freescale Semiconductor
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains electrical characteristics of the device as well as temperature and power
considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However,
it is advisable to take precautions to avoid application of any voltage higher than the specified maximum
rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This
DD
SS
could be done by internal pull up and pull down, which is provided by the product for most general purpose
pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on
the system.
In the tables where the device logic provides signals with their respective timing characteristics, the
symbol “CC” for Controller Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to
the device, the symbol “SR” for System Requirement is included in the Symbol column.
3.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the classifications listed in Table 9 are used and the parameters are tagged
accordingly in the tables where appropriate.
Table 9. Parameter Classifications
Classification tag
Tag description
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
55
Electrical characteristics
3.3
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog
enable/disable after reset are controlled via bit values in the Nonvolatile User Options (NVUSRO) register.
For a detailed description of the NVUSRO register, please see the chip reference manual.
3.3.1
NVUSRO[PAD3V5V] field description
Table 10 shows how NVUSRO[PAD3V5V] controls the device configuration.
1
Table 10. PAD3V5V field description
Value2
Description
0
1
High voltage supply is 5.0 V
High voltage supply is 3.3 V
NOTES:
1
2
See the device reference manual for more information on the NVUSRO register.
Default manufacturing value before Flash initialization is ‘1’ (3.3 V)
The DC electrical characteristics are dependent on the PAD3V5V bit value.
3.3.2
NVUSRO[OSCILLATOR_MARGIN] field description
Table 10 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
1
Table 11. OSCILLATOR_MARGIN field description
Value2
Description
0
1
Low consumption configuration (4 MHz/8 MHz)
High margin configuration (4 MHz/16 MHz)
NOTES:
1
2
See the device reference manual for more information on the NVUSRO register.
Default manufacturing value before Flash initialization is ‘1’
The 4–16 MHz fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN
bit value.
PXD10 Microcontroller Data Sheet, Rev. 1
56
Freescale Semiconductor
Electrical characteristics
3.4
Absolute maximum ratings
Table 12. Absolute maximum ratings
Value
Unit
Symbol
C
Parameter
Conditions
Min
Max
VDDA
VSSA
SR C Voltage on VDDA pin (ADC reference) with
respect to ground (VSSA
—
—
—
0.3
6.0
VSS + 0.1
1.4
V
V
V
)
SR C Voltage on VSSA (ADC reference) pin with
respect to VSS
VSS 0.1
VDDPLL CC C Voltage on VDDPLL (1.2 V PLL supply) pin with
respect to ground (VSSPLL
-0.1
)
VSSPLL SR C Voltage on VSSPLL pin with respect to VSS12
—
—
VSS12 0.1 VSS12 + 0.1
V
V
VDDR
VSSR
VDD12
SR C Voltage on VDDR pin (regulator supply) with
respect to ground (VSSR
0.3
VSS 0.1
-0.1
6.0
VSS + 0.1
1.4
)
SR C Voltage on VSSR (regulator ground) pin with
respect to VSS
—
—
V
V
CC C Voltage on VDD12 pin with respect to ground
(VSS12
)
VSS12
CC C Voltage on VSS12 pin with respect to VSS
SR C Voltage on VDDE_A (I/O supply) pin with
—
—
VSS 0.1
0.3
VSS + 0.1
6.0
V
V
1
1
1
VDDE_A
respect to ground (VSSE_A
)
VDDE_B
SR C Voltage on VDDE_B (I/O supply) pin with
—
—
—
—
—
0.3
0.3
0.3
0.3
0.3
6.0
6.0
6.0
6.0
6.0
V
V
V
V
V
respect to ground (VSSE_B
)
VDDE_C SR C Voltage on VDDE_C (I/O supply) pin with
respect to ground (VSSE_C
)
1
VDDE_E
SR C Voltage on VDDE_E (I/O supply) pin with
respect to ground (VSSE_E
)
1
VDDMA
SR C Voltage on VDDMA (stepper motor supply) pin
with respect to ground (VSSMA
)
1
VDDMB
VDDMC
SR C Voltage on VDDMB/C (stepper motor supply)
1
pin with respect to ground (VSSMB
)
2
VSS
SR C I/O supply ground
—
—
0
0
V
V
VSSOSC SR C Voltage on VSSOSC (oscillator ground) pin with
respect to VSS
VSS 0.1
VSS + 0.1
VLCD
SR C Voltage on VLCD (LCD supply) pin with respect
to VSS
—
0
VDDE_A + 0.3
V
V
VIN
SR C Voltage on any GPIO pin with respect to ground
—
0.3
0.3
6.0
(VSS
)
C
Relative to VDD
VDD + 0.33
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
57
Electrical characteristics
Table 12. Absolute maximum ratings (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
IINJPAD SR C Injected input current on any pin during
overload condition
—
—
10
10
mA
IINJSUM SR C Absolute sum of all injected input currents
during overload condition
50
50
IMAX
CC D Absolute maximum current drive rating
—
—
—
45
TSTORAGE SR C Storage temperature
55
150
°C
NOTES:
1
Throughout the remainder of this document VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B
,
V
DDE_C, VDDE_E, VDDMA, VDDMB and VDDMC, unless otherwise noted.
2
3
Throughout the remainder of this document VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B
,
VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC, unless otherwise noted.
As long as the current injection specification is adhered to, then a higher potential is allowed.
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of this specification are not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability. During overload conditions (V > V or
IN
DD
V
< V ), the voltage on pins with respect to ground (V ) must not
IN
SS SS
exceed the recommended values.
PXD10 Microcontroller Data Sheet, Rev. 1
58
Freescale Semiconductor
Electrical characteristics
3.4.1
Recommended operating conditions
NOTE
Maximum slew time for the supplies to ramp up should be 1 second, which
is slowest ramp-up time.
CAUTION
V
V
and V
must be the same voltage.
DDA
DDE_C
and V
must be the same voltage.
DDMB
DDMC
Table 13. Recommended operating conditions (3.3 V)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
1
VDDA
SR C Voltage on VDDA pin (ADC reference) with
respect to ground (VSS
—
3.0
3.6
V
)
C
Relative to
VDDE_C
VDD 0.1
VDD + 0.1
VSSA SR C Voltage on VSSA (ADC reference) pin with
respect to VSS
—
VSS 0.1
VSS + 0.1
V
VSSPLL SR C Voltage on VSSPLL pin with respect to VSS12
—
—
0
0
V
V
2
VDDR
SR C Voltage on VDDR pin (regulator supply) with
respect to ground (VSSR
3.0
3.6
)
VSSR SR C Voltage on VSSR (regulator ground) pin with
respect to VSS12
—
0
0
V
4
VSS12 CC C Voltage on VSS12 pin with respect to VSS
—
—
VSS 0.1
VSS + 0.1
3.6
V
V
3,4,5
VDD
SR C Voltage on VDD pins (VDDE_A, VDDE_B,
VDDE_C, VDDE_E, VDDMA, VDDMB,
3.0
VDDMC) with respect to ground (VSS
SR C I/O supply ground
VDDE_A SR C Voltage on VDDE_A (I/O supply) pin with
)
6
VSS
—
—
0
0
V
V
3.0
3.6
respect to ground (VSSE_A
)
VDDE_B SR C Voltage on VDDE_B (I/O supply) pin with
—
—
—
—
—
—
3.0
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.6
3.6
V
V
V
V
V
V
respect to ground (VSSE_B
)
VDDE_C SR C Voltage on VDDE_C (I/O supply) pin with
respect to ground (VSSE_C
)
VDDE_E SR C Voltage on VDDE_E (I/O supply) pin with
respect to ground (VSSE_E
)
VDDMA SR C Voltage on VDDMA (stepper motor supply)
pin with respect to ground (VSSMA
)
VDDMB SR C Voltage on VDDMB (stepper motor supply)
pin with respect to ground (VSSMB
)
VDDMC SR C Voltage on VDDMC (stepper motor supply)
pin with respect to ground (VSSMC
)
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
59
Electrical characteristics
Table 13. Recommended operating conditions (3.3 V) (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
VSSOSC SR C Voltage on VSSOSC (oscillator ground) pin
with respect to VSS
—
—
0
0
V
V
VLCD SR C Voltage on VLCD (LCD supply) pin with
respect to VSS
0
VDDE_A + 0.3
TVDD SR C VDD slope to ensure correct power up
—
—
510–6
40
0.25
105
150
V/µs
°C
TA
TJ
SR C Ambient temperature under bias
SR C Junction temperature under bias
40
NOTES:
1
100 nF capacitance needs to be provided between VDDA/VSSA pair.
2
At least 10 µF capacitance must be connected between VDDR and VSS. This is required because of sharp surge
due to external ballast.
3
4
5
VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC
.
100 nF capacitance needs to be provided between each VDD/VSS pair
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/O’s DC electrical specification may not be guaranteed.
When voltage drops below VLVDHVL device is reset.
6
VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and
VSSMC) unless otherwise noted.
Table 14. Recommended operating conditions (5.0 V)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
1
VDDA
SR C Voltage on VDDA pin (ADC reference) with
—
4.5
3.0
5.5
5.5
V
respect to ground (VSS
)
C
C
Voltage drop2
Relative to
VDDE_C
VDD 0.1
VDD + 0.1
VSSA SR C Voltage on VSSA (ADC reference) pin with
respect VSS
—
VSS 0.1
VSS + 0.1
0
V
V
V
VSSPLL SR C Voltage on VSSPLL pin with respect to
VSS12
—
0
3
VDDR
SR C Voltage on VDDR pin (regulator supply) with
—
Voltage drop2
Relative to VDD
—
4.5
3.0
5.5
5.5
respect to ground (VSSR
)
C
C
VDD 0.1
0
VDD + 0.1
0
VSSR SR C Voltage on VSSR (regulator ground) pin with
respect to VSS12
V
VSS12 CC C Voltage on VSS12 pin with respect to VSS
—
VSS 0.1
VSS + 0.1
5.5
V
V
VDD
SR C Voltage on VDD pins (VDDE_A, VDDE_B, Voltage drop2
VDDE_C, VDDE_E, VDDMA, VDDMB,
4.5
4,5
VDDMC) with respect to ground (VSS
)
PXD10 Microcontroller Data Sheet, Rev. 1
60
Freescale Semiconductor
Electrical characteristics
Table 14. Recommended operating conditions (5.0 V) (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
6
VSS
SR C I/O supply ground
—
—
0
0
V
V
VDDE_A SR C Voltage on VDDE_A (I/O supply) pin with
respect to ground (VSSE_A
4.5
5.5
)
VDDE_B SR C Voltage on VDDE_B (I/O supply) pin with
respect to ground (VSSE_B
—
—
—
—
—
—
—
—
4.5
4.5
4.5
4.5
4.5
4.5
0
5.5
V
V
V
V
V
V
V
V
)
7
VDDE_C SR C Voltage on VDDE_C (I/O supply) pin with
respect to ground (VSSE_C
5.5
)
VDDE_E SR C Voltage on VDDE_E (I/O supply) pin with
respect to ground (VSSE_E
5.5
)
VDDMA SR C Voltage on VDDMA (stepper motor supply)
pin with respect to ground (VSSMA
5.5
)
VDDMB SR C Voltage on VDDMB (stepper motor supply)
pin with respect to ground (VSSMB
5.5
)
VDDMC SR C Voltage on VDDMC (stepper motor supply)
pin with respect to ground (VSSMC
5.5
0
)
VSSOSC SR C Voltage on VSSOSC (oscillator ground) pin
with respect to VSS
VLCD SR C Voltage on VLCD (LCD supply) pin with
respect to VSS
0
VDDE_A + 0.3
TVDD SR C VDD slope to ensure correct power up
—
—
—
310–6
40
0.25
105
150
V/µs
°C
TA
TJ
SR C Ambient temperature under bias
SR C Junction temperature under bias
40
°C
NOTES:
1
100 nF capacitance needs to be provided between VDDA/VSSA pair.
2
Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical
characteristics may not be guaranteed below 4.5 V during the voltage drop sequence.
3
10 µF capacitance must be connected between VDDR and VSS12. This is required because of sharp surge due to
external ballast.
4
5
6
VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC
.
100 nF capacitance needs to be provided between each VDD/VSS pair
VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and
VSSMC) unless otherwise noted.
7
VDDE_C should be the same as VDDA with a 100 mV variation, i.e., VDDE_C = VDDA 100 mV.
NOTE
RAM data retention is guaranteed with VDD12 not below 1.08 V.
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
61
Electrical characteristics
3.4.2
Connecting power supply pins: What to do and what not to do
•
Do:
— Have all power/ground supplies connected on the board from a strong supply source rather than
weak voltage divider sources unless there is “NO IO activity” in the section
— Meet the supply specifications for max / typical operating conditions to guarantee correct
operation
— Place the decoupling near the supply/ground pin pair for EMI emissions reduction
— Route high-noise supply/ground away from sensitive signals (for example, ADC channels must
be away from SMD supply/motor pads)
— Use star routing for the ballast supply from the VDDR supply to avoid ballast startup noise
injected to VDDR supply of the device
— Use LC inductive filtering for ADC, OSC, and PLL supplies if these are generated from
common board regulators
•
Do not:
— Violate injection current limit per IO/All IO pins as per specifications
— Connect sensitive supplies/ground on noisy supplies/ground (that is, ADC, PLL, and OSC)
— Use SMD supply for generation of noise free supply as these are most noisy lines in the system
— Connect different VDD pins (connected together inside the device) to different potentials.
3.5
Thermal characteristics
Table 15. LQFP thermal characteristics
Value
Symbol
C
Parameter
Conditions
Unit
144-pin 176-pin
RJA CC D Thermal resistance, junction-to-ambient Single layer board—1s
natural convection1
50
41
41
43
35
35
°C/W
°C/W
°C/W
CC
Four layer board—2s2p
RJMA CC D Thermalresistance, junction-to-moving-air @ 200 ft./min., single layer
ambient2
board—1s
CC
@ 200 ft./min., four layer
board—2s2p
35
30
°C/W
RJB CC D Thermal resistance, junction-to-board2
—
—
29
10
24
9
°C/W
°C/W
RJCtop CC D Thermal resistance, junction-to-case
(top)3
JT
CC D Junction-to-package top thermal
characterization parameter, natural
convection4
—
2
2
°C/W
NOTES:
1
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
2
Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
PXD10 Microcontroller Data Sheet, Rev. 1
62
Freescale Semiconductor
Electrical characteristics
Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
3
4
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
3.5.1
General notes for specifications at maximum junction temperature
An estimate of the chip junction temperature, T , can be obtained from Equation 1:
J
T = T + (R
P )
Eqn. 1
J
A
JA
D
where:
T
= ambient temperature for the package (°C)
= junction to ambient thermal resistance (°C/W)
= power dissipation in the package (W)
A
R
JA
P
D
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide
consistent values for estimations and comparisons. The difference between the values determined for the
single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground
plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance
depends on the:
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to
connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal
performance. When the clearance between the vias leave the planes virtually disconnected, the thermal
performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly
packed printed circuit board. The value obtained on a board with the internal planes is usually within the
normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components are well separated
2
Overall power dissipation on the board is less than 0.02 W/cm
The thermal performance of any component depends on the power dissipation of the surrounding
components. In addition, the ambient temperature varies widely within the application. For many natural
convection and especially closed box applications, the board temperature at the perimeter (edge) of the
package is approximately the same as the local air temperature near the device. Specifying the local
ambient conditions explicitly as the board temperature provides a more precise description of the local
ambient conditions that determine the temperature of the device.
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
63
Electrical characteristics
At a known board temperature, the junction temperature is estimated using Equation 2:
T = T + (R
P )
Eqn. 2
J
B
JB
D
where:
T
= board temperature for the package perimeter (°C)
= junction-to-board thermal resistance (°C/W) per JESD51-8S
= power dissipation in the package (W)
B
R
JB
P
D
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value
for the junction temperature is predictable. Ensure the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a
case-to-ambient thermal resistance:
R
= R
+ R
CA
Eqn. 3
JA
JC
where:
R
R
R
= junction to ambient thermal resistance (°C/W)
= junction to case thermal resistance (°C/W)
= case to ambient thermal resistance (°C/W)
JA
JC
CA
R
s device related and is not affected by other factors. The thermal environment can be controlled to
JC
change the case-to-ambient thermal resistance, R
. For example, change the air flow around the device,
CA
add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device. This description is most useful for
packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most
packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal
resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes
when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The
junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. This model can be used to generate simple estimations and for
computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the
thermal characterization parameter ( ) to determine the junction temperature by measuring the
JT
temperature at the top center of the package case using Equation 4:
T = T + ( x P )
Eqn. 4
J
T
JT
D
where:
T
= thermocouple temperature on top of the package (°C)
= thermal characterization parameter (°C/W)
= power dissipation in the package (W)
T
JT
P
D
PXD10 Microcontroller Data Sheet, Rev. 1
64
Freescale Semiconductor
Electrical characteristics
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using
a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple
so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple
junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat
against the package case to avoid measurement errors caused by the cooling effects of the thermocouple
wire.
References:
Semiconductor Equipment and Materials International
805 East Middlefield Rd.
Mountain View, CA 94043 USA
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
3.6
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
3.6.1
EMC requirements on board
The following practices help minimize noise in applications.
•
Place a 100 nF capacitor between each of the V
/V
supply pairs and also between the
DD12 SS12
V
/V
pair. The voltage regulator also requires stability capacitors for these supply pairs.
DDPLL SSPLL
•
•
•
Place a 10 F capacitor on VDDR.
Isolate VDDR with ballast emitter to avoid voltage droop during STANDBY mode exit.
Enable pad slew rate only as necessary to eliminate I/O noise:
— Enabling slew rate for SMD pads will reduce noise on motors.
— Disabling slew rate for non-SMD pads will reduce noise on non-SMD IOs.
Enable PLL modulation (± 2%) for system clock.
•
•
Place decoupling capacitors for all HV supplies close to the pins.
3.6.2
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application
environment and simplified MCU software. It should be noted that good EMC performance is highly
dependent on the user application and the software in particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in
relation with the EMC level requested for his application.
•
Software recommendations The software flowchart must include the management of runaway
conditions such as:
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
65
Electrical characteristics
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers...)
•
Prequalification trials Most of the common failures (unexpected reset and program counter
corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins
for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected
behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.
3.6.3
Electromagnetic interference (EMI)
1
Table 16. EMI testing specifications
Value
Symbol
C
Parameter
Conditions
Unit
Min Typ Max
—
SR T Scan range
150 kHz – 30 MHz: RBW 9 kHz, step size 5 kHz
30 MHz – 1 GHz: RBW 120 kHz, step size 80 kHz
0.15
—
1000 MHz
—
—
SR T Operating frequency Crystal frequency 8 MHz
—
—
64
—
—
MHz
V
SR T VDD12, VDDPLL
operating voltages
—
1.28
—
—
SR T VDD, VDDA
operating voltages
—
—
5
—
V
SR T Maximum amplitude No PLL frequency modulation
±2% PLL frequency modulation
—
—
—
33
30
25
—
—
—
dBµV
—
SR T Operating
temperature
—
°C
NOTES:
1
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03.
3.6.4
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed
in order to determine its performance in terms of electrical sensitivity.
3.6.4.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of
each sample according to each pin combination. The sample size depends on the number of supply pins in
the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard.
PXD10 Microcontroller Data Sheet, Rev. 1
66
Freescale Semiconductor
Electrical characteristics
1 2
Table 17. ESD absolute maximum ratings
Symbol
C
Ratings
Conditions
TA = 25 °C
Class Max value
Unit
VESD(HBM) CC T Electrostatic discharge voltage
(Human Body Model)
H1C
2000
V
conforming to AEC-Q100-002
VESD(MM) CC T Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) CC T Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
750 (corners)
NOTES:
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
3.6.4.2
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 18. Latch-up results
Symbol
LU CC
C
Parameter
Conditions
Class
T Static latch-up class
TA = 105 °C
conforming to JESD 78
II level A
3.7
Power management electrical characteristics
Voltage regulator electrical characteristics
3.7.1
The internal high power or main regulator (HPREG) requires an external NPN ballast transistor (see
Table 19 and Table 20) to be connected as shown in Figure 5 as well as an external capacitance (C
be connected to the device in order to provide a stable low voltage digital supply to the device.
) to
REG
Capacitances should be placed on the board as near as possible to the associated pins. Care should also be
taken to limit the serial inductance of the board to less than 15 nH.
For the PXD10 microcontroller, 100 nF should be placed between each of the V
/V
supply pairs
DD12 SS12
and also between the V
/V
pair. These decoupling capacitors are in addition to the required
DDPLL SSPLL
stability capacitance. Additionally, 10 F should be placed between the V
pin.
pin and the adjacent V
SS
DDR
V
= 3.0 V to 3.6 V / 4.5 V to 5.5 V, T = 40 to 105 °C, unless otherwise specified.
DDR
A
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
67
Electrical characteristics
V
DDR
VRC_CTRL
20 k
V
DD12
Figure 5. External NPN ballast connections
Table 19. Allowed ballast components
Part
Manufacturer
Recommended derivative
BCP68
BCX68
ON, IFX, NXP, Fairchild, ST, etc.
IFX
BCP68
BCX68-10
BCX68-16
BC817
BCP56
ON, IFX, NXP, Fairchild, etc.
BC817Su
BC817-25
ON, IFX, NXP, Fairchild, ST, etc.
BCP68-10
BCP68-16
Table 20. Ballast component parameters
Specification
Parameter
Capacitance on VDDR
10 F (minimum)
Place close to NPN collector
Stability capacitance on VDD12
40 F (minimum)
Place close to NPN emitter
Decoupling capacitance on VDD12
100 nF number of pins (minimum)
Place on each VDD12/VSS12 pair and on the PLL
supply/ground pair
Base resistor
20 k
The capacitor values listed in Table 20 include a de-rating factor of 40%, covering tolerance, temperature,
and aging effects. These factors are taken into account to assure proper operation under worst-case
conditions. X7R type materials are recommended for all capacitors, based on ESR characteristics.
Large capacitors are for regulator stability and should be located near the external ballast transistor. The
number of capacitors is not important — only the overall capacitance value and the overall ESR value are
important.
Small capacitors are for power supply decoupling, although they do contribute to the overall capacitance
values. They should be located close to the device pin.
PXD10 Microcontroller Data Sheet, Rev. 1
68
Freescale Semiconductor
Electrical characteristics
Table 21. Voltage regulator electrical characteristics
Value
Unit
Symbol
C
Parameter
Conditions
Min
Typ
Max
TJ
SR C Junction temperature
40
—
150
°C
—
IREG CC C Current consumption
Reference included,
@ 55 °C No load
@ Full load
—
—
mA
2
11
IL
CC C Output current capacity
DC load current
—
—
—
200
—
mA
V
VDD12 CC C Output voltage
Pre-trimming sigma <
7 mV
1.330
P
SR C External decoupling/stability capacitor
Post-trimming
1.145
—
1.28
—
1.32
V
4 capacitances of
10 µF each
10 4
µF
C
C
ESR of external cap
0.05
0.2
—
0.2
1
1 bond wire R + 1 pad
R
LBOND CC D Bonding Inductance for Bipolar Base Control pad
CC D Power supply rejection @ DC @ no load
0
—
—
15
nH
dB
—
CL = 10 µF 4
—
30
100
30
D
@ 200 kHz @ no load
@ DC @ 200 mA
D
D
@ 200 kHz @ 200 mA
30
CC D Load current transient
CL = 10 µF 4
CL = 10 µF 4
—
—
—
—
10% to 90% of
IL (max) in
100 ns
tSU CC C Start-up time after input supply stabilizes1
NOTES:
100
µs
1
Time after the input supply to the voltage regulator has ramped up (VDDR).
Table 22. Low-power voltage regulator electrical characteristics
Value
Typ
Unit
Symbol
C
Parameter
Conditions
Min
Max
TJ
SR C Junction temperature
40
150
°C
—
IREG CC C Current consumption
Reference included,
@ 55 °C No load
@ Full load
—
—
A
5
600
IL
VDD12 CC C Output voltage
CC C Output current capacity1
DC load current
—
—
—
15
mA
V
Pre-trimming sigma <
7 mV
1.33
P
Post-trimming
1.14
1.24
1.32
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
69
Electrical characteristics
Table 22. Low-power voltage regulator electrical characteristics (continued)
Value
Unit
Symbol
C
Parameter
Conditions
Min
Typ
Max
SR C External decoupling/stability capacitor
4 capacitances of
10 µF each
10 4
—
10 4
µF
C
C
ESR of external cap
0.1
0.2
—
—
0.6
1
ohm
ohm
1 bond wire R + 1 pad
R
LBOND CC D Bonding Inductance for Bipolar Base Control pad
CC D Power supply rejection @ DC @ no load
0
—
—
15
nH
dB
—
CL = 10 µF 4
—
55
32
24
12
D
D
D
any frequency @ no load
@ DC @ max load
any frequency @ max
load
CC D Load current transient
CL = 10 µF 4
CL = 10 µF 4
—
—
—
—
10% to 90% of
IL in 10 s
tSU CC C Start-up time after input supply stabilizes2
700
µs
NOTES:
1
On this device, the ultra-low-power regulator is always enabled when the low-power regulator is enabled. Therefore, the total
low-power current capacity is the sum of IL values for the two regulators.
2
Time after the input supply to the voltage regulator has ramped up (VDDR) and the voltage regulator has asserted the Power
OK signal.
Table 23. Ultra-low-power voltage regulator electrical characteristics
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
TJ
SR C Junction temperature
40
—
150
°C
—
IREG CC C Current consumption
Reference included,
@ 55 °C No load
@ Full load
—
—
A
2
100
IL
CC C Output current capacity
DC load current
—
—
—
5
mA
V
VDD12 CC C Output voltage (value @ IL = 0 @ 27 °C)
Pre-trimming sigma <
7 mV
1.33
—
Post-trimming
1.14
1.24
1.32
PXD10 Microcontroller Data Sheet, Rev. 1
70
Freescale Semiconductor
Electrical characteristics
Table 23. Ultra-low-power voltage regulator electrical characteristics (continued)
Value
Typ
Symbol
C
Parameter
Conditions
Unit
Min
Max
CC D Power supply rejection @ DC @ no load
—
—
25
7
dB
D
D
D
any frequency @ no load
@ DC @ max load
25
8
any frequency @ max
load
CC D Load current transient
—
—
10 to 90 A in
70 s
3.7.2
Voltage monitor electrical characteristics
The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well
as four low voltage detectors (LVDs) to monitor the V and the V voltage while device is supplied:
DD
DD12
•
•
•
•
•
POR monitors V during the power-up phase to ensure device is maintained in a safe reset state
DD
LVDHV3 monitors V to ensure device reset below minimum functional supply
DD
LVDHV5 monitors V when application uses device in the 5.0 V ± 10% range
DD
LVDLVCOR monitors power domain No. 1
LVDLVBKP monitors power domain No. 0
Table 24. Low voltage monitor electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ Max
VPORH
CC
P
P
P
P
P
P
P
Power-on reset threshold
—
—
—
—
—
1.5
—
—
—
—
—
—
—
—
2.6
2.9
4.4
—
V
VLVDHV3H CC
VLVDHV5H CC
VLVDHV3L CC
VLVDHV5L CC
VLVDLVCORH CC
VLVDLVCORL CC
LVDHV3 low voltage detector high threshold
LVDHV5 low voltage detector high threshold
LVDHV3 low voltage detector low threshold
LVDHV5 low voltage detector low threshold
LVDLVCOR low voltage detector high threshold
LVDLVCOR low voltage detector low threshold
—
2.6
3.8
—
—
TA = 25 °C,
after trimming
1.14
—
1.08
NOTES:
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 105 °C, unless otherwise specified
3.7.3
Low voltage domain power consumption
Table 25 provides DC electrical characteristics for significant application modes. These values are
indicative values; actual consumption depends on the application.
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
71
Electrical characteristics
Table 25. DC electrical characteristics
Conditions1
Value
Symbol
C
Parameter
TA
Unit
Min Typ Max
2
IDDRUN
CC P RUN mode current
—
—
—
—
—
—
—
—
130 180 mA
25 mA
250 1800 A
IDDHALT CC P HALT mode current
IDDSTOP CC P STOP mode current
4
16 MHz fast internal RC oscillator
off, HPVREG off
25°C
105°C
25°C
5
2.5
7
20
6.5 mA
25 mA
mA
16 MHz fast internal RC oscillator
off, HPVREG on
105°C
IDDSTDBY CC C STANDBY mode current See Table 26
3
IDDSTDBY1 CC P STANDBY1 mode current
25°C
105°C
—
—
—
—
—
—
—
20
100 A
A
180
—
TJ = 150°C
350 1500 A
4
IDDSTDBY2 CC P STANDBY2 mode current
25°C
105°C
—
30
100 A
A
350
—
TJ = 150°C
600 2500 A
NOTES:
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 105 °C
Value is for maximum peripherals turned on. May vary significantly based on different configurations, active
peripherals, operating frequency, etc.
2
3
4
ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules
switched off.
ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum consumption, all possible modules
switched off.
1
Table 26. IDDSTDBY specification
FIRC off,
8 KB RAM on
FIRC on,
8 KB RAM on
32 kHz SXOSC on,
8 KB RAM on
32 kHz SXOSC on,
all RAM on
Temperature
(TA,°C)
3.3 V
5.5 V
3.3 V
5.5 V
3.3 V
5.5 V
3.3 V
5.5 V
–40
0
16 A
18 A
23 A
41 A
93 A
173 A
320 A
681 A
25 A
29 A
326 A
334 A
342 A
363 A
421 A
502 A
648 A
1005 A
340 A
347 A
355 A
377 A
435 A
517 A
667 A
1028 A
16 A
19 A
26 A
29 A
22 A
26 A
32 A
37 A
25
33 A
24 A
34 A
34 A
45 A
55
51 A
42 A
53 A
69 A
80 A
85
104 A
185 A
334 A
698 A
100 A
181 A
321 A
654 A
110 A
194 A
335 A
677 A
182 A
344 A
620 A
1270 A
195 A
358 A
638 A
1300 A
105
1252
1502
NOTES:
1
All current values are typical values.
PXD10 Microcontroller Data Sheet, Rev. 1
72
Freescale Semiconductor
Electrical characteristics
Values provided for reference only. The permitted temperature range of the chip is specified separately.
2
3.7.4
Recommended power-up and power-down order
Figure 6 shows the recommended order for powering up the power supplies on this device.
The 1.2 V regulator output starts after the device’s internal POR (VDDREG HV) is deasserted at
approximately 2.7 V on VDDREG.
2.7 V
VDDREG HV supply
VDDREG HV POR (internal)
V
A
1.2 V regulator output
Soft startup (approx. 200 s)
V
B
VDD IO HV supply (3–5.5 V)
>= 200 s
Figure 6. Recommended order for powering up the power supplies
CAUTION
The voltages V and V in Figure 6 must always obey the relation
A
B
V V – 0.7 V. Otherwise, currents from the 1.2 V supply to the 3.3 V
B
A
supply may result.
Figure 7 shows the recommended order for powering down the power supplies on this device.
It is acceptable for the VDD IO HV supply to ramp down faster than the 1.2 V regulator output, even if
the latter takes time to discharge the high 40 F capacitance. (The capacitor will ultimately discharge.)
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
73
Electrical characteristics
2.7 V
> 1.5 V
VDDREG HV supply
VDDREG HV POR (internal)
1.2 V regulator output
Soft startup (approx. 200 s)
Time to discharge 40 F
Capacitance depends on load
VDD IO HV supply (3–5.5 V)
Figure 7. Recommended order for powering down the power supplies
CAUTION
The VDD IO HV supply must be disabled after the VDDREG HV supply
voltage drops below 1.5 V. This is to ensure that the 1.2 V regulator shuts
down before the 3.3 V regulator shuts down.
3.7.5
Power-up inrush current profile
Figure 8 shows the power up inrush current profile of the ballast transistor under the worst possible startup
condition (fastest PVT and fastest power ramp time).
1.2 V supply
Base control
Current profile
3–5.5 V
Figure 8. Power-up inrush current profile
PXD10 Microcontroller Data Sheet, Rev. 1
74
Freescale Semiconductor
Electrical characteristics
The HPREG has a “soft startup” profile which increases the supply in steps of approximately 50 mV in a
series of approximately 25 steps. Therefore, the peak current is within 750 mA of the maximum current
during startup. This eliminates any noise on the VDDR supply during startup and charging of NPN emitter
stability capacitance of 40 F (minimum).
Soft startup also occurs when waking up from standby mode to limit noise on the VDDR supply.
In case VDDR is shared between the device and the ballast, it must be star routed on the board or isolated
as much as possible to avoid any noise injected by the ballast. Soft startup will help to limit this noise but
a VDDR capacitor close to the ballast pin is critical here. A minimum capacitance of 10 F is needed.
Table 27 shows the typical and maximum startup currents.
Table 27. Startup current
Value
Symbol
C
Parameter
Unit
Typ
Max
ISTART
CC T Startup current
300
800
mA
3.7.6
HPREG load regulation characteristics
The HPREG exhibits a very strong load-regulation behavior (the transition from low- to high-current state
is regulated quickly). This is illustrated in Figure 10, which shows a 10–150 mA jump over 10 ns. Under
any case of load transition, the HPREG responds within 100 ns and stabilizes within 5 s. This helps
improve the stability of the 1.2 V supply and settling time.
1.2 V supply
Base control
3 V input supply
Load
Figure 9. HPREG load regulation
3.8
I/O pad electrical characteristics
I/O pad types
3.8.1
The device provides five main I/O pad types:
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
75
Electrical characteristics
•
•
•
Slow pads — These are the most common pads, providing a good compromise between transition
time and low electromagnetic emission.
Medium pads — These are provided in two types (M1 and M2) and provide transitions fast enough
for the serial communication channels. M2 pads include slew rate control.
Fast pads — These provide maximum speed. There are used for improved NEXUS debugging
capability.
•
•
SMD pads — These provide additional current capability to drive stepper motor loads.
Digital I/O with analog (J) pad — These provide input and output digital features and analog input
for ADC.
M2 and Fast pads can disable slew rate to reduce electromagnetic emission, at the cost of reducing AC
performance.
3.8.2
I/O input DC characteristics
Table 28 provides input DC electrical characteristics as described in Figure 10.
VIN
VDD
VIH
VHYS
VIL
PDI = ‘1’
(GPDI register of SIU)
PDI = ‘0’
Figure 10. I/O input DC electrical characteristics definition
Table 28. I/O input DC electrical characteristics
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
VIH SR P Input high level CMOS Schmitt trigger
VIL SR P Input low level CMOS Schmitt trigger
VHYS CC D Input hysteresis CMOS Schmitt trigger
—
—
—
0.65VDD
0.3
—
—
—
VDD + 0.3
0.35VDD
—
V
0.1VDD
PXD10 Microcontroller Data Sheet, Rev. 1
76
Freescale Semiconductor
Electrical characteristics
Table 28. I/O input DC electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
ILKG CC P Input leakage current
—
–1
—
—
—
—
—
—
2
1
—
A
nA
nA
nA
nA
k
TA = -40°C
TA = 25°C
TA = 105°C
TJ = 150°C
2
—
C
P
12
70
—
500
1000
1
RON CC D Resistance of the analog switch inside the J Supply range
pad type2
3.3–5 V
NOTES:
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 °C.
Applies to the J pad type only.
2
3.8.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
•
•
•
Table 29 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 30 provides output driver characteristics for I/O pads when in SLOW configuration.
Table 31 provides output driver characteristics for I/O pads when in MEDIUM configuration
(applies to both M1 and M2 type pads).
•
•
Table 32 provides output driver characteristics for I/O pads when in FAST configuration.
Table 33 provides SMD pad characteristics.
1
Table 29. I/O pull-up/pull-down DC electrical characteristics
Value
Symbol
C
Parameter
Conditions2
Unit
Min Typ Max
|IWPU| CC P Weak pull-up current absolute VIN = VIL, VDD = 5.0V 10% PAD3V5V = 0 10
—
—
—
—
—
—
150 µA
250
value
C
P
PAD3V5V = 13 10
VIN = VIL, VDD = 3.3V 10% PAD3V5V = 1 10
150
|IWPD| CC P Weak pull-down current abso- VIN = VIL, VDD = 5.0V 10% PAD3V5V = 0 10
150 µA
250
lute value
C
P
PAD3V5V = 1 10
V
IN = VIL, VDD = 3.3V 10% PAD3V5V = 1 10
150
NOTES:
1
2
3
The pull currents are dependent on the HVE settings.
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
77
Electrical characteristics
Table 30. SLOW configuration output buffer electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC P Output high level
SLOW configuration
Push Pull, IOH = 2 mA,
VDD = 5.0 V ±10%, PAD3V5V = 0
(recommended)
0.8VDD
—
—
V
D
C
Push Pull, IOH = 2 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V ±10%, PAD3V5V = 12
Push Pull, IOH = 1 mA,
VDD = 3.3 V ±10%, PAD3V5V = 1
(recommended)
VDD 0.8
VOL CC P Output low level
SLOW configuration
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
D
C
Push Pull, IOL = 2 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V ± 10%, PAD3V5V = 12
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
Ttr CC T Output transition time output CL = 25 pF,
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
100
125
40
ns
pin3
VDD = 5.0 V ±10%, PAD3V5V = 0
SLOW configuration
T
T
T
T
T
CL = 50 pF,
VDD = 5.0 V ±10%, PAD3V5V = 0
CL = 100 pF,
VDD = 5.0 V ±10%, PAD3V5V = 0
CL = 25 pF,
VDD = 3.3 V ±10%, PAD3V5V = 1
CL = 50 pF,
VDD = 3.3 V ±10%, PAD3V5V = 1
50
CL = 100 pF,
75
VDD = 3.3 V ±10%, PAD3V5V = 1
Itr50 CC D Current slew at CL = 50 pF recommended configuration at
2
mA/ns
SLOW configuration
VDD = 5.0 V ±10%, PAD3V5V = 0
VDD = 3.3 V ±10%, PAD3V5V = 1
D
VDD = 5.0 V ±10%, PAD3V5V = 1
—
—
7
NOTES:
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 °C, unless otherwise specified
This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are
configured in input or in high impedance state.
2
3
CL calculation should include device and package capacitances (CPKG < 5 pF).
PXD10 Microcontroller Data Sheet, Rev. 1
78
Freescale Semiconductor
Electrical characteristics
Table 31. MEDIUM configuration output buffer electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC P Output high level
MEDIUM configuration
Push Pull, IOH = 2 mA,
VDD = 5.0 V ±10%, PAD3V5V = 0
(recommended)
0.8VDD
—
—
V
D
C
Push Pull, IOH = 1 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V ±10%, PAD3V5V = 12
Push Pull, IOH = 1 mA,
VDD = 3.3 V ±10%, PAD3V5V = 1
(recommended)
VDD 0.8
VOL CC P Output low level
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
MEDIUM configuration
D
C
Push Pull, IOL = 1 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V ± 10%, PAD3V5V = 12
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
Ttr CC T Output transition time out- CL = 25 pF,
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
20
40
12
25
40
7
ns
put pin3
VDD = 5.0 V ±10%, PAD3V5V = 0
MEDIUM configuration
T
T
T
T
T
CL = 50 pF,
VDD = 5.0 V ±10%, PAD3V5V = 0
CL = 100 pF,
VDD = 5.0 V ±10%, PAD3V5V = 0
CL = 25 pF,
VDD = 3.3 V ±10%, PAD3V5V = 1
CL = 50 pF,
VDD = 3.3 V ±10%, PAD3V5V = 1
CL = 100 pF,
VDD = 3.3 V ±10%, PAD3V5V = 1
Itr50 CC D Current slew at CL = 50 pF recommended configuration at
mA/ns
MEDIUM configuration
VDD = 5.0 V ±10%, PAD3V5V = 0
VDD = 3.3 V ±10%, PAD3V5V = 1
D
VDD = 5.0 V ±10%, PAD3V5V = 1
—
—
16
NOTES:
1
VDD = 3.3 V ± 10% / 5.0 V 10%, TA = 40 to 105 °C, unless otherwise specified
This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are
configured in input or in high impedance state.
2
3
CL includes device and package capacitance (CPKG < 5 pF).
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
79
Electrical characteristics
Table 32. FAST configuration output buffer electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC P Output high level
FAST configuration
Push Pull, IOH = 14 mA,
VDD = 5.0 V ±10%, PAD3V5V = 0
(recommended)
0.8VDD
—
—
V
D
C
Push Pull, IOH = 7 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V ±10%, PAD3V5V = 12
Push Pull, IOH = 11 mA,
VDD = 3.3 V ±10%, PAD3V5V = 1
(recommended)
VDD 0.8
VOL CC P Output low level
FAST configuration
Push Pull, IOL = 14 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
V
D
C
Push Pull, IOL = 7 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V ± 10%, PAD3V5V = 12
Push Pull, IOL = 11 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
Ttr CC T Output transition time output CL = 25 pF,
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
6
ns
pin3
VDD = 5.0 V ±10%, PAD3V5V = 0
FAST configuration
T
T
T
T
T
CL = 50 pF,
VDD = 5.0 V ±10%, PAD3V5V = 0
CL = 100 pF,
VDD = 5.0 V ±10%, PAD3V5V = 0
12
4
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 50 pF,
VDD = 3.3 V ±10%, PAD3V5V = 1
7
CL = 100 pF,
12
55
40
100
VDD = 3.3 V ±10%, PAD3V5V = 1
Itr50 CC D Current slew at CL = 50 pF VDD = 5.0 V ±10%, PAD3V5V = 0
FAST configuration (recommended configuration)
mA/ns
D
VDD = 3.3 V ±10%, PAD3V5V = 1
(recommended configuration)
D
VDD = 5.0 V ±10%, PAD3V5V = 1
NOTES:
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 °C, unless otherwise specified
This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are
configured in input or in high impedance state.
2
3
CL includes device and package capacitance (CPKG < 5 pF).
PXD10 Microcontroller Data Sheet, Rev. 1
80
Freescale Semiconductor
Electrical characteristics
Table 33. SMD pad electrical characteristics
Value
Typ
Symbol
C
Parameter
Conditions
Unit
Max
Min
VIL
VIH
CC P Low level input voltage
CC P High level input voltage
—
—
—
–0.4
0.65VDDM
0.1VDDM
—
—
—
—
—
—
—
—
—
—
—
0.35VDDM
V
VDDM+0.4
—
VHYST CC C Schmitt trigger hysteresis
VOL
VOH
IPU
CC P Low level output voltage
IOL = 20 mA1
IOL = 30 mA2
IOH = –20 mA1
0.32
0.48
—
—
CC P High level output voltage
VDDM–0.32
VDDM–0.48
–130
I
OH = –30 mA2
—
CC P Internal pull-up device current Vin=VIL
Vin=VIH
—
A
—
–10
—
IPD
CC P Internal pull-down device
current
Vin=VIL
10
Vin=VIH
—
-1
—
—
—
—
130
1
IIN
CC P Input leakage current
—
RDSONH CC C SMD pad driver active high
impedance
IOH –30 mA2
16
RDSONL CC C SMD pad driver active low
impedance
IOL 30 mA2
—
—
—
—
16
90
VOMATCH CC P Output driver matching
VOH / VOL
IOH / IOL 30 mA2
mV
NOTES:
1
VDD = 5.0 V ±10%, Tj = -40 to 150 °C.
2
VDD = 5.0 V ±10%, Tj = -40 to 130 °C.
3.8.4
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a
/V supply pair as described in Table 34.
V
DD SS
Table 35 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below
the I
maximum value.
AVGSEG
In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single
segment should remain below the I
maximum value.
DYNSEG
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
81
Electrical characteristics
Table 34. I/O supply segment
Supply segment
Package
A1
B2
C3,4
D5
E6
144 LQFP
176 LQFP
pins 1–21
pins 113–144
pins 22– 52
pins 53–72
pins 73–102
pins 103–112
pins 1–21
pins 22–68
pins 69–88
pins 89–118
pins 119–142
pins 143–176
NOTES:
1
2
3
4
5
6
LCD pad segment containing pad supplies VDDE_A
Miscellaneous pad segment containing pad supplies VDDE_B
ADC pad segment containing pad supplies VDDE_C
VDDE_C should be the same as VDDA with a 100 mV variation, i.e., VDDE_C = VDDA 100 mV.
Stepper Motor pad segment containing I/O supplies VDDMA, VDDMB, VDDMC
Miscellaneous pad segment containing pad supplies VDDE_E
Table 35. I/O consumption
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
ISWTSLW CC D Dynamic I/O current for SLOW
configuration
CL = 25 pF,
VDD = 5.0 V ±10%, PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20
16
29
17
mA
D
CL = 25 pF,
VDD = 3.3 V ±10%, PAD3V5V = 1
ISWTMED CC D Dynamic I/O current for MEDIUM CL = 25 pF,
configuration VDD = 5.0 V ±10%, PAD3V5V = 0
mA
D
CL = 25 pF,
VDD = 3.3 V ±10%, PAD3V5V = 1
ISWTFST CC D Dynamic I/O current for FAST
configuration
CL = 25 pF,
VDD = 5.0 V ±10%, PAD3V5V = 0
110 mA
50
D
CL = 25 pF,
VDD = 3.3 V ±10%, PAD3V5V = 1
IRMSSLW CC D Root mean square I/O current for CL = 25 pF, 2 MHz
2.3 mA
3.2
SLOW configuration VDD = 5.0 V ±10%, PAD3V5V = 0
D
D
D
D
D
CL = 25 pF, 4 MHz
VDD = 5.0 V ±10%, PAD3V5V = 0
CL = 100 pF, 2 MHz
6.6
VDD = 5.0 V ±10%, PAD3V5V = 0
CL = 25 pF, 2 MHz
VDD = 3.3 V ±10%, PAD3V5V = 1
1.6
CL = 25 pF, 4 MHz
VDD = 3.3 V ±10%, PAD3V5V = 1
2.3
CL = 100 pF, 2 MHz
4.7
VDD = 3.3 V ±10%, PAD3V5V = 1
PXD10 Microcontroller Data Sheet, Rev. 1
82
Freescale Semiconductor
Electrical characteristics
Table 35. I/O consumption (continued)
Parameter
Conditions1
Value
Unit
Symbol
C
Min Typ Max
IRMSMED CC D Root mean square I/O current for CL = 25 pF, 2 MHz
MEDIUM configuration VDD = 5.0 V ±10%, PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6.6 mA
D
D
D
D
D
CL = 25 pF, 4 MHz
DD = 5.0 V ±10%, PAD3V5V = 0
13.4
V
CL = 100 pF, 2 MHz
VDD = 5.0 V ±10%, PAD3V5V = 0
18.3
CL = 25 pF, 2 MHz
VDD = 3.3 V ± 10%, PAD3V5V = 1
5.0
CL = 25 pF, 4 MHz
8.5
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 100 pF, 2 MHz
11.0
VDD = 3.3 V ± 10%, PAD3V5V = 1
IRMSFST CC D Root mean square I/O current for CL = 25 pF, 2 MHz
FAST configuration VDD = 5.0 V ± 10%, PAD3V5V = 0
22.0 mA
33.0
D
D
D
D
D
CL = 25 pF, 4 MHz
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 100 pF, 2 MHz
VDD = 5.0 V ± 10%, PAD3V5V = 0
56.0
CL = 25 pF, 2 MHz
VDD = 3.3 V ± 10%, PAD3V5V = 1
14.0
CL = 25 pF, 4 MHz
VDD = 3.3 V ± 10%, PAD3V5V = 1
20.0
CL = 100 pF, 2 MHz
25.0
VDD = 3.3 V ± 10%, PAD3V5V = 1
IDYNSEG SR D Sum of all the dynamic and static VDD = 5.0 V ± 10%, PAD3V5V = 0
I/O current within a supply seg-
—
—
—
—
110 mA
65
D
VDD = 3.3 V ± 10%, PAD3V5V = 1
ment
IAVGSEG SR D Sum of all the static I/O current
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
—
—
—
—
70
65
90
mA
within a supply segment
D
VDD = 3.3 V ± 10%, PAD3V5V = 1
IDDMxAVG SR D Sum of currents of two motors
VDD = 5.0 V ± 10%, PAD3V5V = 0
assigned to segment VDDMx
VSSMx pair
,
TJ = 130 C
DD = 5.0 V ± 10%, PAD3V5V = 0
V
—
—
120
TJ = –40 C
NOTES:
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 °C, unless otherwise specified
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
83
Electrical characteristics
3.9
SSD specifications
3.9.1
Electrical characteristics
Table 36. SSD electrical characteristics
Value1
Symbol
C
Parameter
Unit
Min
Typ
Max
VVREF
IVREF
RIN
CC P Reference voltage (IVREF = 0)
CC P Reference voltage output current
CC D Input resistance (against VDDM/2)
CC C Input common mode range
VDDM/2 - 0.02
1.85
VDDM/2
—
VDDM/2 + 0.02
V
mA
M
V
—
1.2
0.8
1.0
VIN
VSSM
0.549
–9
—
VDDM
0.597
9
SSDCONST CC C SSD constant
0.572
—
—
SSDOFFSET CC C SSD offset (unipolar, Nsample
256)
=
counts
SSD offset (bipolar, Nsample = 256)
–8
–5
—
—
8
5
SSD offset (bipolar with offset
cancellation, Nsample = 256)
fSSDSMP
CC D SSD cmpout sample rate
0.5
—
2.0
MHz
NOTES:
1
Vdd = 5.0V +/- 10%, Tj = -40C to +150C.
3.9.2
Accumulator values
Equation 5 describes the accumulator value in unipolar configuration. The voltage V is applied between
in
the integrator input and V
. The internal generated reference voltage is not connected. The accumulator
DDM
value is a function of V
, the number of samples (Nsample) taken and the SSD constant (SSDconst).
DDM
The SSD constant and offset (SSDconst, SSDoffset) vary with temperature and process.
V – VDDM 2
in
-----------------------------------------------
ACCval =
Nsample + SSDoffset
VDDM SSDconst
Eqn. 5
Equation 6 describes the accumulator value in bipolar configuration. The voltage V is applied between
in
the integrator input and the reference output. The accumulator value depends on the same parameters as
in the unipolar case but the inaccuracy of the voltage reference (Vvref) is compensated.
V
in
-----------------------------------------------
ACCval =
Nsample + SSDoffset
VDDM SSDconst
Eqn. 6
3.10 RESET electrical characteristics
PXD10 Microcontroller Data Sheet, Rev. 1
84
Freescale Semiconductor
Electrical characteristics
The device implements a dedicated bidirectional RESET pin.
Figure 11. Start-up reset requirements
V
DD
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
device start-up phase
Figure 12. Noise filtering on reset signal
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
85
Electrical characteristics
Table 37. Reset electrical characteristics
Conditions1
Value
Symbol
C
Parameter
Unit
Min
Typ
Max
VIH
VIL
SR P Input high level CMOS
Schmitt Trigger
—
0.65VDD
—
VDD + 0.4
V
V
V
V
SR P Input low level CMOS Schmitt —
Trigger
0.4
0.1VDD
—
—
—
—
0.35VDD
—
VHYS CC D Input hysteresis CMOS
Schmitt Trigger
—
VOL CC P Output low level
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.1VDD
D
C
Push Pull, IOL = 1 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V ± 10%, PAD3V5V = 12
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
Ttr
CC T Output transition time output CL = 25 pF,
—
—
—
—
—
—
—
—
—
—
—
—
10
20
40
12
25
40
ns
pin3
VDD = 5.0 V ± 10%, PAD3V5V = 0
MEDIUM configuration
T
T
T
T
T
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
WFRST SR P RESET input filtered pulse
—
—
1000
10
—
—
—
40
—
ns
ns
µA
WNFRST SR P RESET input not filtered pulse —
IWPU CC P Weak pull-up current absolute —
value
150
D RUN Current during RESET Before Flash is ready
After Flash is ready
—
—
10
20
—
—
mA
mA
NOTES:
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 105 °C, unless otherwise specified
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to reset generation module
(RGM) section of the device reference manual).
2
3
CL includes device and package capacitance (CPKG < 5 pF).
PXD10 Microcontroller Data Sheet, Rev. 1
86
Freescale Semiconductor
Electrical characteristics
3.11 Fast external crystal oscillator (4–16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 13 describes a simple model of the internal
oscillator driver and provides an example of a connection for an oscillator or a resonator.
XTAL
C
L
XTAL
EXTAL
C
L
DEVICE
V
DD
I
R
XTAL
EXTAL
DEVICE
EXTAL
DEVICE
Figure 13. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
Table 38. Crystal description
Shunt
capacitance
between
xtalout
Crystal
equivalent
series
resistance
ESR
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
Nominal
frequency
(MHz)
NDK crystal
reference
(pF)1
and xtalin
C02 (pF)
4
NX8045GB
NX5032GA
300
300
150
120
120
2.68
2.46
2.93
3.11
3.90
591.0
160.7
86.6
21
17
15
15
10
2.93
3.01
2.91
2.93
3.00
8
10
12
16
56.5
25.3
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
87
Electrical characteristics
NOTES:
1
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2
The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
Table 39. Resonator description
CSTCR4M00G53-R0
CSTCR4M00G55-R0
Vibration
Fundamental
Fr (kHz)
3929.50
4163.25
233.75
372.41
12.78
3898.00
4123.00
225.00
465.03
11.38
Fa (kHz)
Fa–Fr (dF) (kHz)
Ra (k)
R1 ()
L1 (mH)
0.84443
1.94268
15.85730
1630.93
15
0.88244
1.88917
15.90537
1899.77
39
C1 (pF)
Co (pF)
Qm
CL1 (nominal) (pF)
CL2 (nominal) (pF)
15
39
S_MTRANS bit (ME_GS register)
‘1’
‘0’
V
XTAL
1/f
FXOSC
V
FXOSC
90%
10%
V
FXOSCOP
t
valid internal clock
FXOSCSU
Figure 14. Fast external crystal oscillator (4–16 MHz) electrical characteristics
PXD10 Microcontroller Data Sheet, Rev. 1
88
Freescale Semiconductor
Electrical characteristics
Table 40. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fFXOSC
SR — Fast external crystal
oscillator frequency
—
4.0
—
16.0
MHz
gmFXOSC CC C Fast external crystal
oscillator
V
DD = 3.3 V ± 10%,
2.2
2.0
2.7
2.5
—
—
—
—
8.2
7.4
9.7
9.2
mA/V
PAD3V5V = 1
OSCILLATOR_MARGIN = 0
transconductance
CC P
CC C
CC C
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
VFXOSC
CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
1.3
—
—
—
—
V
f
OSC = 16 MHz,
OSCILLATOR_MARGIN = 1
VFXOSCOP CC C Oscillation operating point
—
—
—
—
0.95
2
—
3
V
,2
IFXOSC
CC T Fast external crystal
oscillator consumption
mA
TFXOSCSU CC T Fast external crystal
oscillator start-up time
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
—
—
—
—
6
ms
f
OSC = 16 MHz,
1.8
OSCILLATOR_MARGIN = 1
VIH
VIL
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.65VDD
0.4
VDD+0.4
0.35VDD
V
V
SR P Input low level CMOS
(Schmitt Trigger)
Oscillator bypass mode
NOTES:
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 105 °C, unless otherwise specified
Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals)
2
3.12 Slow external crystal oscillator (32 KHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
89
Electrical characteristics
PC[15]
PC[15]
PC[14]
C
X
PC[14]
C
Y
DEVICE
DEVICE
Figure 15. Crystal oscillator and resonator connection scheme
NOTE
PC[14]/PC[15] must not be directly used to drive external circuits.
OSCON bit (OSC_CTL register)
‘1’
‘0’
V
SXOSC_XTAL
1/f
SXOSC
V
SXOSC
90%
10%
T
valid internal clock
SXOSCSU
Figure 16. Slow external crystal oscillator (32 KHz) timing
PXD10 Microcontroller Data Sheet, Rev. 1
90
Freescale Semiconductor
Electrical characteristics
Table 41. Slow external crystal oscillator (32 KHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fSXOSC SR T Slow external crystal oscillator —
frequency
32
—
40
kHz
V
VSXOSC CC T Oscillation amplitude
T
VDD = 3.3 V ± 10%
DD = 5.0 V ± 10%
1.12
1.12
—
1.33
1.37
—
1.74
1.74
5
V
ISXOSC CC D Slow external crystal oscillator —
consumption
µA
s
TSXOSCSU CC T Slow external crystal oscillator —
start-up time
—
—
—
—
22
VIH
SR D Input high level CMOS Schmitt Oscillator bypass mode 0.65VDD
Trigger
VDD + 0.4
0.35VDD
V
VIL
SR D Input low level CMOS Schmitt Oscillator bypass mode
Trigger
0.4
V
NOTES:
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 105 °C, unless otherwise specified
The quoted figure is based on a board that is properly laid out and has no stray capacitances.
2
3.13 FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system
clock from the main oscillator driver.
Table 42. FMPLL electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ Max
fPLLIN SR T FMPLL reference clock2
PLLIN SR T FMPLL reference clock duty cycle2
fPLLOUT CC T FMPLL output clock frequency
fCPU CC T System clock frequency
tLOCK CC T FMPLL lock time
—
—
—
—
4
—
—
—
—
—
—
—
—
64 MHz
60
40
16
—
—
—
—
—
%
64 MHz
643 MHz
Stable oscillator (fPLLIN = 16 MHz)
fPLLIN = 16 MHz (resonator)
fPLLIN = 16 MHz (resonator)
TA = 25 °C
200
220
1.5
4
µs
ps
tPKJIT CC T FMPLL jitter (peak to peak)
tLTJIT CC T FMPLL long term jitter
ns
IPLL
CC D FMPLL consumption
mA
NOTES:
1
VDDPLL = 1.2 V ± 10%, TA = 40 to 105 °C, unless otherwise specified.
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN
2
.
3
fCPU 64 MHz can be achieved only at temperatures up to TA = 105 °C with a maximum FM depth of 2%.
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
91
Electrical characteristics
3.14 Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up
of the device.
Table 43. Fast internal RC oscillator (16 MHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
fFIRC
CC P Fast internal RC oscillator high TA = 25 °C, trimmed
frequency
16
MHz
SR —
—
12
20
+5
FIRCVAR CC C Fast internal RC oscillator
variation across temperature
(TA = -40°C to 105°C) and
supply with respect to fFIRC at
TA = 25 °C in high-frequency
configuration
Trimmed
—
5
—
%
IFIRCRUN CC D Fast internal RC oscillator high TA = 25 °C, trimmed —
—
—
—
—
200 µA
frequency current in running
mode
IFIRCPWD CC D Fast internal RC oscillator high TA = 25 °C
frequency current in power
—
1
µA
down mode
IFIRCSTOP CC D Fast internal RC oscillator high TA = 25 °C
sysclk = off
—
—
—
—
—
—
0.3
2
—
—
—
—
—
2
mA
frequency and system clock
current in stop mode
D
sysclk = 2 MHz
sysclk = 4 MHz
sysclk = 8 MHz
sysclk = 16 MHz
VDD = 5.0 V ± 10%
D
D
D
2.5
3.3
5.2
1
tFIRCSU CC P Fast internal RC oscillator
start-up time
µs
NOTES:
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 105 °C, unless otherwise specified.
3.15 Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the
RTC module.
PXD10 Microcontroller Data Sheet, Rev. 1
92
Freescale Semiconductor
Electrical characteristics
Table 44. Slow internal RC oscillator (128 kHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
fSIRC
CC P Slow internal RC oscillator low
TA = 25 °C, trimmed
—
128
—
kHz
frequency
SR —
—
100
150
SIRCVAR CC C Slow internal RC oscillator variation
across temperature (TA = -40°C to
105°C) and supply with respect to fSIRC
at TA = 25 °C in high frequency
Trimmed
-10%
+10% kHz
configuration
ISIRC
CC D Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
—
—
—
8
5
µA
µs
tSIRCSU CC C Slow internal RC oscillator start-up time TA = 25 °C, VDD = 5.0 V ± 10%
NOTES:
12
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 105 °C, unless otherwise specified.
3.16 Flash memory electrical characteristics
Table 45. Program and erase specifications
Value
Symbol
C
Parameter
Unit
Initial
max2
Typ1
Max3
Tdwprogram
T16kpperase
T32kpperase
CC C Double word (64 bits) program time4
CC C 16 KB block pre-program and erase time
CC C 32 KB block pre-program and erase time
22
300
400
800
—
50
500
600
1300
30
500
5000
5000
7500
30
µs
ms
ms
ms
µs
T128kpperase CC C 128 KB block pre-program and erase time
Teslat CC D Erase suspend latency
NOTES:
1
2
3
Typical program and erase times assume nominal supply values and operation at 25 °C.
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
93
Electrical characteristics
Table 46. Flash module life
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
P/E
CC C Number of program/erase cycles per
block for 16 KB blocks over the operating
temperature range (TJ)
—
—
—
100000
10000
1000
—
cycles
P/E
P/E
CC C Number of program/erase cycles per
block for 32 KB blocks over the operating
temperature range (TJ)
100000 cycles
100000 cycles
CC C Number of program/erase cycles per
block for 128 KB blocks over the
operating temperature range (TJ)
Retention CC C Minimum data retention at 85 °C
average ambient temperature1
Blocks with 0–1,000 P/E
cycles
20
10
5
—
—
—
years
years
years
Blocks with 10,000 P/E
cycles
Blocks with 100,000 P/E
cycles
NOTES:
1
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
Table 47. Flash memory read access timing
Symbol
C
Parameter
Condition1
Max value Unit
fREAD
CC P Maximum frequency for flash memory reading
2 wait states
1 wait state
0 wait states
64
40
20
MHz
C
C
NOTES:
1
VDD = 3.3 V ±10% / 5.0 V ±10%, TA = –40 to 105 C, unless otherwise specified
3.17 ADC electrical characteristics
The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter.
PXD10 Microcontroller Data Sheet, Rev. 1
94
Freescale Semiconductor
Electrical characteristics
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = V
/ 1024
DDA
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
(LSB
V
)
ideal
in(A)
Offset Error OSE
Figure 17. ADC Characteristics and Error Definitions
3.17.1 Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC
impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can
be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to
attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase,
when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple
RC filter). The RC filtering may be limited according to the value of source impedance of the transducer
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
95
Electrical characteristics
or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking
into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input
impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling
capacitance: C being substantially a switched capacitance, with a frequency equal to the conversion rate
S
of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz,
with C equal to 3 pF, a resistance of 330 k is obtained (R = 1 / (f C ), where f represents the
S
EQ
c
S
c
conversion rate at the considered channel). To minimize the error induced by the voltage partitioning
between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external
S
S
F
L
SW
AD
circuit must be designed to respect the Equation 7:
Eqn. 7
R + R + R + R
+ R
S
F
L
SW
AD
1
2
--------------------------------------------------------------------------
V
-- LSB
A
R
EQ
Equation 7 generates a constraint for external network design, in particular on resistive path. Internal
switch resistances (R and R ) can be neglected with respect to external resistances.
SW
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
C
S
A
F
P1
P2
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 18. Input equivalent circuit (precise channels)
PXD10 Microcontroller Data Sheet, Rev. 1
96
Freescale Semiconductor
Electrical characteristics
EXTERNAL CIRCUIT
Filter
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Selection
Extended
Switch
Sampling
Source
R
Current Limiter
R
R
R
F
R
L
R
AD
SW2
S
SW1
C
S
C
V
C
F
C
C
P2
A
P1
P3
R
R
C
R
R
R
C
C
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions R
Sampling Switch Impedance
S
F
F
L
and R
)
SW2
SW
AD
P
SW1
Pin Capacitance (three contributions, C , C and C )
Sampling Capacitance
P1
P2
P3
S
Figure 19. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances
C , C and C are initially charged at the source voltage V (refer to the equivalent circuit reported in
F
P1
P2
A
Figure 18): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch
close).
Voltage transient on CS
V
CS
V
A
V <0.5 LSB
V
A2
1
2
1 < (RSW + RAD) CS << TS
V
A1
2 = RL (CS + CP1 + CP2)
T
t
S
Figure 20. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
•
A first and quick charge transfer from the internal capacitance C and C to the sampling
P1 P2
capacitance C occurs (C is supposed initially completely discharged): considering a worst case
S
S
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
97
Electrical characteristics
(since the time constant in reality would be faster) in which C is reported in parallel to C (call
P2
P1
C = C + C ), the two capacitances C and C are in series, and the time constant is
P
P1
P2
P
S
Eqn. 8
C C
P
S
--------------------
= R
+ R
1
SW
AD
C + C
P
S
Equation 8 can again be simplified considering only C as an additional worst condition. In reality,
S
the transient is faster, but the A/D converter circuitry has been designed to be robust also in the
very worst case: the sampling time T is always much longer than the internal time constant:
S
Eqn. 9
R
+ R
C « T
1
SW
AD
S
S
The charge of C and C is redistributed also on C , determining a new value of the voltage V
P1
P2
S
A1
on the capacitance according to Equation 10:
Eqn. 10
V
C + C + C = V C + C
P1 P2 P1 P2
A1
S
A
•
A second charge transfer involves also C (that is typically bigger than the on-chip capacitance)
F
through the resistance R : again considering the worst case in which C and C were in parallel
L
P2
S
to C (since the time constant in reality would be faster), the time constant is:
P1
Eqn. 11
R C + C + C
P1 P2
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the
transient is completed well before the end of sampling time T , a constraints on R sizing is
S
L
obtained:
Eqn. 12
10 = 10 R C + C + C T
2
L
S
P1
P2
S
Of course, R shall be sized also according to the current limitation constraints, in combination
L
with R (source impedance) and R (filter resistance). Being C definitively bigger than C , C
S
F
F
P1 P2
and C , then the final voltage V (at the end of the charge transfer transient) will be much higher
S
A2
than V . Equation 13 must be respected (charge balance assuming now C already charged at
A1
S
V ):
A1
Eqn. 13
V
C + C + C + C = V C + V C + C + C
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C
F F
filter, is not able to provide the extra charge to compensate the voltage drop on C with respect to the ideal
S
PXD10 Microcontroller Data Sheet, Rev. 1
98
Freescale Semiconductor
Electrical characteristics
source V ; the time constant R C of the filter is very high with respect to the sampling time (T ). The
A
F F
S
filter is typically designed to act as anti-aliasing.
Analog source bandwidth (V )
A
T
f
2 R C (conversion rate vs. filter pole)
F F
C
Noise
f (anti-aliasing filtering condition)
F
0
2 f f (Nyquist)
0
C
f
0
f
Anti-aliasing filter (f = RC filter pole)
Sampled signal spectrum (f = conversion rate)
C
F
f
f
f
C
F
0
f
f
Figure 21. Spectral representation of input signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the
0
anti-aliasing filter, f ), according to the Nyquist theorem the conversion rate f must be at least 2f ; it
F
C
0
means that the constant time of the filter is greater than or at least equal to twice the conversion period
(T ). Again the conversion period T is longer than the sampling time T , which is just a portion of it,
C
C
S
even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific
channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher
F F
than the sampling time T , so the charge level on C cannot be modified by the analog signal source during
S
S
the time in which the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy
error due to the voltage drop on C ; from the two charge balance equations above, it is simple to derive
S
Equation 14 between the ideal and real sampled voltage on C :
S
Eqn. 14
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A
P1
F
V
C
+ C + C + C
A2
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5V), assuming to accept a
A
maximum error of half a count, a constraint is evident on C value:
F
Eqn. 15
C
2048 C
F
S
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
99
Electrical characteristics
3.17.2 ADC conversion characteristics
NOTE
For input leakage current specification, see Table 28.
Table 48. ADC conversion characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VSSA
SR D Voltage on VSSA (ADC
reference) pin with
—
—
0.1
—
0.1
V
2
respect to ground (VSS
)
VDDA
SR D Voltage on VDDA pin
(ADC reference) with
VDD 0.1
—
VDD + 0.1
V
respect to ground (VSS
)
VAINx
fADC
SR D Analog input voltage3
—
—
—
VSSA 0.1
—
—
—
—
VDDA + 0.1
V
MHz
µs
SR D ADC analog frequency
6
32
1.5
—
tADC_PU SR D ADC power up delay
tADC_S CC T Sample time4,5
—
fADC = 32 MHz,
0.5
µs
ADC_conf_sample_input = 17
T
fADC = 6 MHz,
ADC_conf_sample_input = 127
—
0.625
—
—
—
—
—
—
—
—
—
—
—
21
—
3
tADC_C CC T Conversion time6
fADC = 32 MHz,
ADC_conf_comp = 2
µs
pF
pF
pF
pF
k
k
k
mA
CS
CC D ADC input sampling
capacitance
—
—
—
—
—
—
—
CP1
CP2
CP3
CC D ADC input pin
capacitance 1
—
3
CC D ADC input pin
capacitance 2
—
1
CC D ADC input pin
capacitance 3
—
1
RSW1 CC D Internal resistance of
analog source
—
1
RSW2 CC D Internal resistance of
analog source
—
1
RAD
CC D Internal resistance of
analog source
—
0.1
5
IINJ
SR T Input current Injection
Current injection on one ADC
input, different from the
converted one
5
INL
CC P Integral Non Linearity
No overload
.5
—
—
2.5
1.0
LSB
LSB
DNL
CC P Differential Non Linearity No overload
1.0
PXD10 Microcontroller Data Sheet, Rev. 1
100
Freescale Semiconductor
Electrical characteristics
Table 48. ADC conversion characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
OFS
GNE
CC T Offset error
CC T Gain error
After offset cancellation
—
—
–3
–4
0.5
0.6
—
—
—
3
LSB
LSB
LSB
TUEx CC P Total unadjusted error for Without current injection
extended channel
T
With current injection
—
4
NOTES:
1
VDDA = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 105 °C, unless otherwise specified.
Analog and digital VSS must be common (to be tied together externally).
2
3
VAINx may exceed VSSA and VDDA limits, remaining on absolute maximum ratings, but the results of the conversion
will be clamped respectively to 0x000 or 0x3FF
4
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
5
The maximum sample rate is 1 million samples per second, provided the source impedance and current
limiter(>1 k) are calculated adequately.
- Filter capacitor at analog source output must meet the criteria Cf (filter capacitor) > 2048*Cs (sampling capacitor
which is 3 pF)
6
This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
3.18 LCD driver electrical characteristics
Table 49. LCD driver specifications
Value1
Symbol
C
Parameter
Unit
Min
Typ
Max
VLCD
ZBP/FP
SR C Voltage on VLCD (LCD supply) pin with
respect to VSS
0
—
VDDE + 0.3
V
CC T LCD output impedance
(BP[n-1:0],FP[m-1:0]) for output levels
VLCD, VSS2
—
—
—
5.0
—
k
IBP/FP
CC T LCD output current
25
A
(BP[n-1:0],FP[m-1:0]) for outputs
charge/discharge voltage levels
VLCD2/3, VLCD1/2, VLCD1/3)2,3
NOTES:
1
2
3
VDD = 5.0 V ± 10%, TA = –40–105 °C, unless otherwise specified
Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
With PWR=10, BSTEN=0, and BSTAO=0
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
101
Electrical characteristics
3.19 Pad AC specifications
1
Table 50. Pad AC specifications (5.0 V, PAD3V5V = 0)
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew
(mA/ns)
Load drive
(pF)
No.
Pad
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
1
Slow
1.5
1.5
1.5
1.5
1
—
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
30
15
15
15
15
6
6
9
—
—
—
—
—
—
—
—
—
—
—
—
—
50
100
125
150
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
2
0.04
0.04
0.04
0.04
2.5
2.5
2.5
2.5
18
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
25
50
12
16
3
2
2
100
200
25
2
2
2
3
4
Medium
40
20
13
7
7
1
5
20
7
50
1
9
40
8
100
200
25
1
12
1
70
8
Fast
1
4
100
80
40
25
—
55
55
55
55
—
1
6
1.5
3
6
18
50
1
6
12
18
100
200
50
1
6
5
16
18
Pull Up/Down
(5.5 V max)
—
—
—
5000
—
Parameter
Classification
D
C
C
C
n/a
NOTES:
1
2
Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition
Slope at rising/falling edge
1
Table 51. Pad AC specifications (3.3 V, PAD3V5V = 1)
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew
(mA/ns)
Load drive
(pF)
No.
Pad
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
1
Slow
3
3
3
3
1
1
1
1
—
—
—
—
—
—
—
—
40
40
40
40
15
15
15
15
4
6
—
—
—
—
—
—
—
—
40
50
75
100
12
25
40
70
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
2
0.01
0.01
0.01
0.01
2.5
—
—
—
—
—
—
—
—
2
2
2
2
7
7
7
7
25
50
10
14
2
2
100
200
25
2
2
Medium
40
20
13
7
4
2.5
50
8
2.5
100
200
14
2.5
PXD10 Microcontroller Data Sheet, Rev. 1
102
Freescale Semiconductor
Electrical characteristics
Table 51. Pad AC specifications (3.3 V, PAD3V5V = 1) (continued)
1
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew
(mA/ns)
Load drive
(pF)
No.
Pad
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
3
Fast
1
1
—
—
—
—
—
6
6
1
1.5
3
—
—
—
—
—
4
7
—
—
—
—
—
—
—
—
—
—
72
55
40
25
—
3
3
—
—
—
—
—
40
40
40
40
—
25
50
1
6
12
3
100
200
50
1
6
5
18
3
4
Pull Up/Down
(3.6 V max)
—
—
—
7500
—
Parameter
Classification
D
C
C
C
n/a
NOTES:
1
2
Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition
Slope at rising/falling edge
VDD/2
Pad
Data Input
Rising
Edge
Falling
Edge
Output
Delay
Output
Delay
VOH
VOL
Pad
Output
Figure 22. Pad output delay
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
103
Electrical characteristics
Table 52. SMD pad delays
Conditions
Value
Symbol
C
Parameter
Unit
Min
Typ
Max
—
CC D SMD pad delay
CL=50pf
—
—
165
ns
VDD=5V±10%
SRE=1
CL=50pf
—
—
—
—
—
—
35
350
50
VDD=5V±10%
SRE=0
—
CC D SMD pad delay
CL=50pf
VDD=3.3V±10%
SRE=1
CL=50pf
VDD=3.3V±10%
SRE=0
3.20 AC timing
3.20.1 IEEE 1149.1 interface timing
1
Table 53. JTAG interface timing
Value
No.
Symbol
tJCYC
C
Parameter
Unit
ns
Min
Max
1
2
3
4
5
6
7
8
CC D TCK Cycle Time
100
40
—
5
—
60
3
tJDC
CC D TCK Clock Pulse Width (measured at VDD/2)
CC D TCK Rise and Fall Times (40%–70%)
CC D TMS, TDI Data Setup Time
tTCKRISE
tTMSS, TDIS
t
—
—
40
—
30
t
TMSH, tTDIH CC D TMS, TDI Data Hold Time
10
—
0
tTDOV
tTDOI
CC D TCK Low to TDO Data Valid
CC D TCK Low to TDO Data Invalid
CC D TCK Low to TDO High Impedance
tTDOHZ
—
NOTES:
1
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 3.0 V to 5.5 V, TA = 40 to
105 °C, and CL = 50 pF with SRC = 0b11.
PXD10 Microcontroller Data Sheet, Rev. 1
104
Freescale Semiconductor
Electrical characteristics
TCK
2
3
3
2
1
Figure 23. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 24. JTAG test access port timing
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
105
Electrical characteristics
TCK
9
11
Output
Signals
10
Output
Signals
12
13
Input
Signals
Figure 25. JTAG boundary scan timing
3.20.2 Nexus debug interface
1
Table 54. Nexus debug port timing
Value
No.
Symbol
C
Parameter
Unit
Min
Max
1
2
3
4
5
6
tMCYC
MDC
tMDOV
CC D MCKO Cycle Time
22
40
–2
–2
–2
4
—
60
14
14
14
—
ns
%
CC D MCKO Duty Cycle
CC D MCKO Low to MDO Data Valid2
CC D MCKO Low to MSEO Data Valid2
CC D MCKO Low to EVTO Data Valid2
CC D EVTI Pulse Width
ns
tMSEOV
tEVTOV
tEVTIPW
ns
ns
tTCYC
PXD10 Microcontroller Data Sheet, Rev. 1
106
Freescale Semiconductor
Electrical characteristics
1
Table 54. Nexus debug port timing (continued)
Value
No.
Symbol
tEVTOPW
C
Parameter
Unit
Min
Max
7
8
CC D EVTO Pulse Width
1
100
40
10
5
—
—
60
—
—
40
tMCYC
ns
tTCYC
CC D TCK Cycle Time3
9
TDC
CC D TCK Duty Cycle
%
10
11
12
tNTDIS, NTMSS
tNTDIH, NTMSH
tJOV
t
CC D TDI, TMS Data Setup Time
CC D TDI, TMS Data Hold Time
CC D TCK Low to TDO Data Valid
ns
t
ns
0
ns
NOTES:
1
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is
measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 3.0 V to 5.5V,
TA = 40 to 105 °C, and CL = 50 pF (CL = 30 pF on MCKO), with SRC = 0b11.
2
3
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
The system clock frequency needs to be three times faster than the TCK frequency.
1
2
MCKO
3
4
5
MDO
MSEO
EVTO
Output Data Valid
Figure 26. Nexus output timing
TCK
9
8
9
Figure 27. Nexus TCK timing
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
107
Electrical characteristics
TCK
10
11
TMS, TDI
12
TDO
Figure 28. Nexus TDI, TMS, TDO timing
3.20.3 Interface to TFT LCD panels
Figure 29 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure
signals are shown with positive polarity. The sequence of events for active matrix interface timing is:
1. DCU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In
active mode, DCU_CLK runs continuously.
2. DCU_HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.
3. DCU_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC
pulse.
4. DCU_DE acts like an output enable signal to the LCD panel. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
PXD10 Microcontroller Data Sheet, Rev. 1
108
Freescale Semiconductor
Electrical characteristics
DCU_VSYNC
DCU_HSYNC
LINE 1 LINE 2
LINE 3
LINE 4
LINE n-1 LINE n
DCU_HSYNC
DCU_DE
1
2
3
m-1
m
DCU_CLK
DCU_LD[23:0]
1
Figure 29. TFT LCD interface timing overview
3.20.3.1 Interface to TFT LCD panels—pixel level timings
Figure 30 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive
polarity of the DCU_CLK signal (meaning the data and sync signals change on the rising edge) and
active-high polarity of the DCU_HSYNC, DCU_VSYNC and DCU_DE signals. The user can select the
polarity of the DCU_HSYNC and DCU_VSYNC signals via the SYN_POL register, whether active-high
or active-low. The default is active-high. The DCU_DE signal is always active-high.
Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are
programmed via the DCU Clock Confide Register (DCCR) in the system clock module.
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H,
BP_H and FP_H parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V
parameters are programmed via the VSYN_PARA register.
Table 55. LCD interface timing parameters—horizontal and vertical
Symbol
C
Parameter
Value
Unit
tPCP
tPWH
tBPH
tFPH
tSW
CC D Display pixel clock period
CC D HSYNC pulse width
CC D HSYNC back porch width
CC D HSYNC front porch width
CC D Screen width
—
PW_H tPCP
ns
ns
ns
ns
ns
ns
ns
BP_H tPCP
FP_H tPCP
DELTA_X tPCP
tHSP
tPWV
CC D HSYNC (line) period
CC D VSYNC pulse width
(PW_H + BP_H + FP_H + DELTA_X ) tPCP
PWVtHSP
1. In Figure 29, the “DCU_LD[23:0]” signal is an aggregation of the DCU’s RGB signals—DCU_R[0:7], DCU_G[0:7] and
DCU_B[0:7].
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
109
Electrical characteristics
Table 55. LCD interface timing parameters—horizontal and vertical (continued)
Symbol
C
Parameter
Value
Unit
tBPV
tFPV
tSH
CC D VSYNC back porch width
CC D VSYNC front porch width
CC D Screen height
BP_V tHSP
FP_V tHSP
ns
ns
ns
ns
DELTA_Y tHSP
tVSP
CC D VSYNC (frame) period
(PW_V + BP_V + FP_V + DELTA_Y ) tHSP
t
HSP
t
t
t
t
SW
FPH
PWH
BPH
Start of line
t
PCP
DCU_CLK
Invalid Data
1
2
3
DELTA_X
Invalid Data
DCU_LD[23:0]
DCU_HSYNC
DCU_DE
Figure 30. Horizontal sync timing
t
VSP
t
t
t
t
SH
FPV
BPV
PWV
Start of Frame
DCU_HSYNC
t
HCP
DCU_LD[23:0]
(Line Data)
2
DELTA_Y
1
Invalid Data
3
Invalid Data
DCU_HSYNC
DCU_DE
Figure 31. Vertical sync pulse
3.20.3.2 Interface to TFT LCD panels
PXD10 Microcontroller Data Sheet, Rev. 1
110
Freescale Semiconductor
Electrical characteristics
1,2,3,4
Table 56. TFT LCD interface timing parameters
Parameter
Value
Symbol
C
Unit
Min
Typ
Max
tCKP CC D PDI clock period
CK CC D PDI clock duty cycle
15.25
40
—
—
—
—
—
—
—
—
—
—
—
—
60
—
—
—
—
6
ns
%
tDSU CC D PDI data setup time
9.5
4.5
9.5
4.5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDHD CC D PDI data access hold time
tCSU CC D PDI control signal setup time
tCHD CC D PDI control signal hold time
CC D TFT interface data valid after pixel clock
CC D TFT interface VSYNC valid after pixel clock
CC D TFT interface DE valid after pixel clock
CC D TFT interface hold time for data and control bits
CC D Relative skew between the data bits
—
5.5
5.6
—
3.7
—
2
—
NOTES:
1
The characteristics in this table are based on the assumption that data is output at positive edge and displays latch
data on negative edge
2
3
4
Intra bit skew is less than 2 ns
Load CL = 50 pF for panel frequency up to 20 MHz
Load CL = 25 pF for panel frequency from 20 to 32 MHz
tCHD tCSU
DCU_HSYNC
DCU_VSYNC
DCU_DE
DCU_CLK
tCKH
tCKL
tDSU tDHD
DCU_LD[23:0]
Figure 32. TFT LCD interface timing parameters
3.20.4 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) timing
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
111
Electrical characteristics
Table 57. IRQ and NMI timing
Parameter
Value
No.
Symbol
C
Unit
Min
Max
1
2
3
tIPWL
tIPWH
tICYC
CC
CC
CC
T
T
T
IRQ/NMI Pulse Width Low
IRQ/NMI Pulse Width High
IRQ/NMI Edge to Edge Time1
200
200
400
—
—
—
ns
ns
ns
NOTES:
1
Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
1,2
1,2
3
Figure 33. IRQ and NMI timing
3.20.5 eMIOS timing
1
Table 58. eMIOS timing
Value
No.
Symbol
C
Parameter
Unit
Min2
Max
1
2
tMIPW
tMOPW
CC
CC
D
D
eMIOS input pulse width
eMIOS output pulse width
4
1
—
—
tCYC
tCYC
NOTES:
1
eMIOS timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = 40 to 105 °C,
and CL = 50 pF with SRC = 0b00
2
There is no limitation on the peripheral for setting the minimum pulse width, the actual width is restricted by the pad
delays. Refer to the pad specification section for the details.
PXD10 Microcontroller Data Sheet, Rev. 1
112
Freescale Semiconductor
Electrical characteristics
3.20.6 FlexCAN timing
The CAN functions are available as TX pins at normal IO pads and as RX pins at the always on domain.
There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup if configured.
1
Table 59. FlexCAN timing
Value
No.
Symbol
C
Parameter
Unit
Min
Max
1
2
tCANOV CC D CTNX Output Valid after CLKOUT Rising Edge (Output Delay)
tCANSU CC D CNRX Input Valid to CLKOUT Rising Edge (Setup Time)
—
—
22.48
12.46
ns
ns
NOTES:
1
FlexCAN timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = 40 to 105 °C,
and CL = 50 pF with SRC = 0b00.
3.20.7 Deserial Serial Peripheral Interface (DSPI)
1
Table 60. DSPI timing
Value
No. Symbol
C
Parameter
Conditions
Master (MTFE = 0)
Slave (MTFE = 0)
Slave Receive Only Mode
Unit
Min
Max
1
tSCK CC D DSPI Cycle TIme2,3
62
62
62
—
—
—
ns
ns
ns
2
3
4
5
tCSC CC D PCS to SCK Delay4
tASC CC D After SCK Delay5
tSDC CC D SCK Duty Cycle
tA CC D Slave Access Time
—
20
20
—
—
ns
ns
—
—
0.4 x tSCK 0.6 x tSCK ns
SS active to SOUT valid
—
40
ns
(PCSx active to SOUT driven)
6
tDIS CC D Slave SOUT Disable Time
SS inactive to SOUT High-Z or
—
10
ns
(PCSx inactive to SOUT High-Z or invalid
invalid)
7
8
9
tPCSC
tPASC
PCSx to PCSS time
PCSS to PCSx time
—
—
20
20
—
—
ns
ns
tSUI CC D Data Setup Time for Inputs
Master (MTFE = 0)
35
2
20
35
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
10 tHI CC D Data Hold Time for Inputs
Master (MTFE = 0)
–5
5
10
–5
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
113
Electrical characteristics
1
Table 60. DSPI timing (continued)
Value
No. Symbol
C
Parameter
Conditions
Unit
Min
Max
11 tSUO CC D Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
—
—
—
—
14
39
24
15
ns
ns
ns
ns
12 tHO CC D Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–3
6
12
–3
—
—
—
—
ns
ns
ns
ns
NOTES:
1
DSPI timing specified at VDDE_x = 3.0 V to 5.5 V, TA = 40 to 105 °C, and CL = 50 pF with SRC = 0b11.
The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate.
The actual minimum SCK Cycle Time is limited by pad performance.
2
3
4
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK = 2
and CSSCK = 2
5
6
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
This delay value is corresponding to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
8
7
Last Data
SIN
First Data
Data
Data
10
9
First Data
Last Data
SOUT
Note: Numbers in circles refer to values in Table 60.
Figure 34. DSPI classic SPI timing — master, CPHA = 0
PXD10 Microcontroller Data Sheet, Rev. 1
114
Freescale Semiconductor
Electrical characteristics
PCSx
SCK Output
(CPOL = 0)
8
SCK Output
(CPOL = 1)
7
Data
Data
First Data
Last Data
SIN
10
9
SOUT
Last Data
First Data
Note: Numbers in circles refer to values in Table 60.
Figure 35. DSPI classic SPI timing — master, CPHA = 1
3
2
PCSx
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
9
10
Data
6
First Data
Last Data
SOUT
SIN
7
8
Data
Last Data
First Data
Note: Numbers in circles refer to values in Table 60.
Figure 36. DSPI classic SPI timing — slave, CPHA = 0
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
115
Electrical characteristics
PCSx
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
9
5
6
10
Last Data
Data
Data
SOUT
SIN
First Data
8
7
Last Data
First Data
Note: Numbers in circles refer to values in Table 60.
Figure 37. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
7
8
SIN
First Data
Last Data
Last Data
Data
10
9
SOUT
First Data
Data
Note: Numbers in circles refer to values in Table 60.
Figure 38. DSPI modified transfer format timing — master, CPHA = 0
PXD10 Microcontroller Data Sheet, Rev. 1
116
Freescale Semiconductor
Electrical characteristics
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
8
7
SIN
Last Data
First Data
Data
10
Data
9
First Data
Last Data
SOUT
Note: Numbers in circles refer to values in Table 60.
Figure 39. DSPI modified transfer format timing — master, CPHA = 1
3
2
PCSx
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
10
9
6
5
First Data
7
Data
Data
Last Data
8
SOUT
SIN
Last Data
First Data
Note: Numbers in circles refer to values in Table 60.
Figure 40. DSPI modified transfer format timing — slave, CPHA = 0
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
117
Electrical characteristics
PCSx
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
9
5
6
10
Last Data
First Data
8
Data
Data
SOUT
SIN
7
First Data
Last Data
Note: Numbers in circles refer to values in Table 60.
Figure 41. DSPI modified transfer format timing — slave, CPHA = 1
3.20.8 I2C timing
2
Table 61. I C Input Timing Specifications — SCL and SDA
Value
Min Max
No. Symbol C
Parameter
Unit
1
2
4
6
7
8
9
—
—
—
—
—
—
—
CC D Start condition hold time
CC D Clock low time
2
8
—
—
—
—
—
—
—
IP-Bus Cycle1
IP-Bus Cycle1
ns
CC D Data hold time
0.0
4
CC D Clock high time
CC D Data setup time
IP-Bus Cycle1
0.0
2
ns
CC D Start condition setup time (for repeated start condition only)
CC D Stop condition setup time
IP-Bus Cycle1
IP-Bus Cycle1
2
NOTES:
1
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
PXD10 Microcontroller Data Sheet, Rev. 1
118
Freescale Semiconductor
Electrical characteristics
2
Table 62. I C Output Timing Specifications — SCL and SDA
Value
Min Max
No. Symbol C
Parameter
Unit
11
21
33
41
51
61
71
81
91
—
—
—
—
—
—
—
—
—
CC D Start condition hold time
CC D Clock low time
6
—
—
IP-Bus Cycle2
IP-Bus Cycle1
ns
10
—
7
CC D SCL/SDA rise time
99.6
—
CC D Data hold time
IP-Bus Cycle1
CC D SCL/SDA fall time
—
10
2
99.5
—
ns
CC D Clock high time
IP-Bus Cycle1
IP-Bus Cycle1
IP-Bus Cycle1
IP-Bus Cycle1
CC D Data setup time
—
CC D Start condition setup time (for repeated start condition only)
CC D Stop condition setup time
20
10
—
—
NOTES:
1
Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings
listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the prescale and division values programmed in IFDR.
2
3
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
2
6
5
SCL
SDA
3
1
4
8
9
7
2
Figure 42. I C input/output timing
3.20.9 QuadSPI timing
The following notes apply to Table 63:
•
All data are based on a negative edge data launch from PXD10 and a positive edge data capture as
shown in the timing diagrams.
•
Typical values are provided from center-split material at 25 C and 3.3 V. Minimum and maximum
values are from a temperature variation of –45 C to 105 C and the following supply conditions:
— IO voltage: 3.2 V, core supply: 1.2 V
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
119
Electrical characteristics
— IO voltage: 3.6 V, core supply: 1.2 V
•
•
•
•
All measurements are taken at 70% of VDDE levels for clock pin and 50% of VDDE level for data
pins.
Timings correspond to QSPI_SMPR = 0x0000_000x. See the PXD10 Microcontroller Reference
Manual for details.
A negative value of hold is an indication of pad delay on the clock pad (delay between the edge
capturing data inside the device and the edge appearing at the pin).
Values are with a load of 15pF on the output pins.
Table 63. QuadSPI timing
Value
Symbol
C
Parameter
Unit
Min
Typ
Max
tCQ
tS
CC T Clock to Q delay
1.60
6.1
2.4
9.4
5.33
12.1
–7.5
1.0
ns
ns
ns
ns
ns
CC T Setup time for incoming data
CC T Hold time requirement for incoming data
CC T Clock pad rise time
tH
–12.5
0.4
–8.5
0.6
tR
tF
CC T Clock pad fall time
0.3
0.5
0.9
1
tCQ
SCK
DO
1. Last address out
Figure 43. QuadSPI output timing diagram
PXD10 Microcontroller Data Sheet, Rev. 1
120
Freescale Semiconductor
Electrical characteristics
1
tCQ
2
3
4
5
6
7
8
SCK
DO
DI
tS
tH
1. Last address out
2. Address captured at flash
3. Data out from flash
4. Ideal data capture edge
5. Delayed data capture edge with QSPI_SMPR=0x0000_000x
6. Delayed data capture edge with QSPI_SMPR=0x0000_002x
7. Delayed data capture edge with QSPI_SMPR=0x0000_004x
8. Delayed data capture edge with QSPI_SMPR=0x0000_006x
Figure 44. QuadSPI input timing diagram
The clock profile in Figure 45 is measured at 30% to 70% levels of VDDE.
tR
tF
70%
VDDE
30%
SCK
Figure 45. QuadSPI clock profile
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
121
Package mechanical data
4
Package mechanical data
4.1
144 LQFP
PXD10 Microcontroller Data Sheet, Rev. 1
122
Freescale Semiconductor
Package mechanical data
Figure 46. LQFP144 mechanical drawing (Part 1 of 3)
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
123
Package mechanical data
Figure 47. LQFP144 mechanical drawing (Part 2 of 3)
PXD10 Microcontroller Data Sheet, Rev. 1
124
Freescale Semiconductor
Package mechanical data
Figure 48. LQFP144 mechanical drawing (Part 3 of 3)
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
125
Package mechanical data
4.2
176 LQFP
Figure 49. LQFP176 mechanical drawing (Part 1 of 3)
PXD10 Microcontroller Data Sheet, Rev. 1
126
Freescale Semiconductor
Package mechanical data
Figure 50. LQFP176 mechanical drawing (Part 2 of 3)
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
127
Package mechanical data
Figure 51. LQFP176 mechanical drawing (Part 3 of 3)
PXD10 Microcontroller Data Sheet, Rev. 1
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Freescale Semiconductor
Ordering information
5
Ordering information
M PX
D 10 10 V LU 64 R
Qualification status
Brand
Family
Class
Flash memory size
Temperature range
Package identifier
Operating frequency
Tape and reel indicator
Qualification status
Family
Flash Memory Size
D = Display Graphics
N = Connectivity/Network
R = Performance/Real Time Control
S = Safety
05 = 512 KB
10 = 1 MB
P = Pre-qualification (engineering samples)
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Temperature range
Package identifier
Operating frequency
Tape and reel status
V = –40 °C to 105 °C
(ambient)
LQ = 144 LQFP
LU = 176 LQFP
64 = 64 MHz
120 = 120 MHz
R = Tape and reel
(blank) = Trays
Note: Not all options are available on all devices. See Table 64 for more information.
Figure 52. PXD10 orderable part number description
Table 64. PXD10 orderable part number summary
Speed
(MHz)
Part number
Flash/SRAM
Package
MPXD1005VLQ64
MPXD1010VLQ64
MPXD1010VLU64
512 KB / 48 KB
1 MB / 48 KB
1 MB / 48 KB
144 LQFP (20 mm x 20 mm)
144 LQFP (20 mm x 20 mm)
176 LQFP (24 mm x 24 mm)
64
64
64
PXD10 Microcontroller Data Sheet, Rev. 1
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6
Revision history
Table 65. Document revision history
Revision
Date
Substantive changes
1
30 Sep 2011 Initial release.
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Document Number: PXD10
Rev. 1
09/2011
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