SPXS2010VLT120R [FREESCALE]
PXD20 Microcontroller;型号: | SPXS2010VLT120R |
厂家: | Freescale |
描述: | PXD20 Microcontroller 微控制器 |
文件: | 总130页 (文件大小:778K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: PXD20
Rev. 2, 04/2012
PXD20
208 LQFP
416 TEPBGA
28 mm x 28 mm
27 mm x 27 mm
PXD20 Microcontroller Data
Sheet
176 LQFP
24 mm x 24 mm
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Device comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pinout and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1 176 LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . 24
2.2 208 LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . 25
2.3 416 TEPBGA package pinout–40 to 105°C . . . . . . . . . 26
2.4 Signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
System design information. . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.1 Power-up sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . 60
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 63
4.4 Recommended operating conditions . . . . . . . . . . . . . . 64
4.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66
4.6 EMI (electromagnetic interference) characteristics . . . 70
4.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . 75
4.9 RESET electrical characteristics . . . . . . . . . . . . . . . . . 84
4.10 Fast external crystal oscillator (4–16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.11 Slow external crystal oscillator (32 KHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.12 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 88
4.13 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.14 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.15 Flash memory electrical characteristics . . . . . . . . . . . . 90
4.16 ADC parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.17 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.18 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
The PXD20 represents a new generation of 32-bit
microcontrollers targeting single-chip industrial HMI
applications. PXD20 devices are part of the PX family of
Power Architecture -based devices. This family has been
designed with an emphasis on providing cost-effective and
high quality graphics capabilities.
®
PXD20 devices contain 2 MB internal flash memory. Serial
flash memory and DRAM interfaces are provided to allow
even greater system flexibility.
3
4
The PXD20:
•
•
•
Includes 2 MB internal flash memory, 1 MB internal
graphics SRAM, and 64 KB system SRAM
Offers high processing performance operating at
speeds up to 125 MHz
Is optimized for low power consumption
The PXD20 is designed to reduce development and
production costs of TFT-based displays by providing a
single-chip solution with the processing and storage capacity
to host and execute real-time application software and drive
TFT displays directly.
The PXD20 features a 2D OpenVG 1.1 graphics accelerator,
Video Input Unit (VIU2) and two on-chip display control
units (DCU3 and DCULite) designed to drive two color TFT
displays simultaneously. The PXD20 includes a enhanced
QuadSPI serial flash controller and an optional DRAM
controller allowing graphics RAM expansion externally.
The PXD20 is compatible with the existing development
infrastructure of current Power Architecture devices and are
supported with software drivers, operating systems and
configuration code to assist with application development.
5
6
7
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2011–2012. All rights reserved.
Preliminary—Subject to Change Without Notice
Overview
1
Overview
1.1
Device comparison
Table 1. PXD20 Family Feature Set
Feature
PXD20
Package
CPU
208 LQFP
416 MAPBGA
176 LQFP
e200z4d
4 KB Instruction-Cache
16-entry Memory Management Unit (MMU)
Floating Point Unit (FPU)
Signal Processing Extension (SPE)
Execution speed
Flash memory (ECC)
RAM (ECC)
Static–125 MHz
2 MB
64 KB
On-chip graphics RAM (no ECC)
MPU
1 MB
16 entry
eDMA
16 channels
No
DRAM controller
Yes
OpenVG Graphics Accelerator
(GFX2D)
Yes (OpenVG 1.1)
Display Control Unit (DCU3)
Yes
Yes
Yes
Display Control Unit Lite (DCULite)
No
No
Timing Controller (TCON) and RSDS
interface
Video Input Unit (VIU2)
Yes
QuadSPI serial flash interface
Stepper Motor Controller (SMC)
Stepper Stall Detect (SSD)
Sound Generator Module (SGM)
32 kHz external crystal oscillator
Yes
4 motors
6 motors
Yes
Yes
Yes
Real Time Counter and Autonomous
Periodic Interrupt (RTC/API)
Yes
Periodic interrupt timer (PIT)
Software Watchdog Timer (SWT)
System Timer Module (STM)
Timed I/O
8 ch, 32-bit
Yes
4 ch, 32-bit
20 ch, 16-bit: IC / OC / OPWM
8 ch, 16-bit: IC / OC
4 ch, 16-bit: IC / OC / OPWM / QDEC
PXD20 Microcontroller Data Sheet, Rev. 2
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
Table 1. PXD20 Family Feature Set (continued)
PXD20
Feature
Package
208 LQFP
416 MAPBGA
176 LQFP
Analog-to-Digital Converter (ADC)
16 channels, 10-bit
20 channels, 10-bit
CAN (64 mailboxes)
3 × CAN
Yes
CAN sampler
Serial communication interface
3 × LIN
2 × SPI
4 × LIN
3 × SPI
SPI
I2C
4
GPIO
Debug
128
150
177
Nexus Class 3 (12MDO)
Nexus Class 3 (4MDO)
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Overview
1.2
Block diagram
PXD20 Block Diagram
System
VREG
Debug
JTAG
Crossbar Masters
Z160
2D
GFX
e200z4d Core
(4 KB I-Cache)
DCU
Lite
Oscillator
Nexus
Class 3+
VIU2
DCU
TCON RSDS
FMPLL x 2
RTC/32 kHz
Oscillator
MMU
Interrupt
Controller
16-ch DMA
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
PIT
SWT
STM
2 MB
Flash
1 MB
Graphics PBRIDGE
SRAM
64 KB
SRAM
RLE
Decode
Quad
SPI V02
DRAM
Interface
Boot
Assist
Module
(BAM)
ECC
Crossbar Slaves
Communications I/O System
SSD
20-ch
ADC
10-bit
eMIOS A eMIOS B
16-ch 16-ch
3x
CAN
4x
UART/LIN
3x
SPI
4x
I2C
SGM
6x
SMD
ADC
– Analog-to-digital converter
RTC
– Real time clock
CAN
DCU
– Controller area network controller
– Display control unit
RSDS
SGM
– Reduced-swing differential sgnal interface
– Sound generator module
DMA
DRAM
ECC
– Direct memory access controller
– Dynamic random-access memory
– Error correction code
SMD SSD – Stepper motor driver/stepper stall detect
SPI
SRAM
STM
– Serial peripheral interface controller
– Sraric random-access memory
– System timer module
eMIOS
FMPLL
GFX
– Timed input/output
– Frequency-modulated phase-locked loop
– OpenVG graphics accelerator
– Inter-integrated circuit controller
– Joint Test Action Group interface
– Memory management unit
SWT
TCON
– Software watchdog timer
– Timing controller
I2C
UART/LIN – Universal asynchronous receiver/transmitter/
JTAG
MMU
local interconnect network
VIU2
VLE
VREG
– Video input unit
– Variable-length execution set
– Voltage regulator
PBRIDGE – Peripheral I/O bridge
PIT
RLE
– Periodic interrupt timer
– Run length encoding
Figure 1. PXD20 block diagram
PXD20 Microcontroller Data Sheet, Rev. 2
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
1.3
Feature list
•
Dual-issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z4d)
— Memory Management Unit (MMU)
— 4 KB, 2/4-way instruction cache
•
2 MB on-chip ECC flash memory with:
— Flash memory controller
— Prefetch buffers
•
•
•
64 KB on-chip ECC SRAM
1 MB on-chip non-ECC graphics SRAM with two-port graphics SRAM controller
Memory Protection Unit (MPU) with up to 16 region descriptors and 32-byte region granularity to provide basic
memory access permission and ensure separation between different codes and data
•
•
Interrupt Controller (INTC) with 181 peripheral interrupt sources and eight software interrupts
Two Frequency-Modulated Phase-Locked Loops (FMPLLs)
— Primary FMPLL (FMPLL0) provides a system clock up to 125 MHz
— Auxiliary FMPLL (FMPLL1) is available for use as an alternate, modulated or non-modulated clock source to
eMIOS modules, QuadSPI and as alternate clock to the DCU and DCU-Lite for pixel clock generation
•
•
•
•
Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus
masters
16-channel Enhanced Direct Memory Access controller (eDMA) with multiple transfer request sources using a DMA
channel multiplexer
Boot Assist Module (BAM) with 8 KB dedicated ROM for embedded boot code supports boot options including
download of boot code via a serial link (CAN or SCI)
Two Display Control Units (DCU3 and DCULite) for direct drive of up to two TFT LCD displays up to XGA
resolution
•
•
•
Timing Controller (TCON) and RSDS interface for the DCU3 module
2D OpenVG 1.1 and raster graphics accelerator (GFX2D)
Video Input Unit (VIU2) supporting 8/10-bit ITU656 video input, YUV to RGB conversion, video down-scaling,
de-interlacing, contrast adjustment and brightness adjustment.
•
•
DRAM controller supporting DDR1, DDR2, LPDDR1 and SDR DRAMs
Stepper Motor Controller (SMC)
— High-current drivers for as many as six stepper motors driven in full dual H-bridge configuration
— Stepper motor return-to-zero and stall detection module
— Stepper motor short circuit detection
•
Sound Generator Module (SGM)
— 4-channel mixer
— Supports PCM wave playback and synthesized tones
2
— Optional PWM or I S outputs
•
•
Two 16-channel Enhanced Modular Input Output System (eMIOS) modules
— Support a range of 16-bit Input Capture, Output Compare, Pulse Width Modulation and Quadrature Decode
functions
10-bit Analog-to-Digital Converter (ADC) with a maximum conversion time of 1 s
— Up to 20 internal channels
— Up to 8 external channels
•
•
Three Deserial Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous, communications with
external devices
QuadSPI serial flash memory controller
— Supports single, dual and quad IO serial flash memory
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
Overview
— Interfaces to external, memory-mapped serial flash memories
— Supports simultaneous addressing of 2 external serial flashes to achieve up 80 MB/s read bandwidth
RLE decoder supporting memory to memory decoding of RLE data in conjunction with eDMA
Four local interconnect network (LINFlex) controller modules
•
•
— Capable of autonomous message handling (master), autonomous header handling (slave mode), and UART
support
— Compliant with LIN protocol rev 2.1
Three controller-area network (FlexCAN) modules
— Compliant with the CAN protocol version 2.0 C
— 64 configurable buffers
•
— Programmable bit rate of up to 1 Mb/s
2
•
•
•
Four Inter-Integrated Circuit (I C) internal bus controllers with master/slave bus interface
Low-power loop controlled pierce crystal oscillator supporting 4–16MHz external crystal or resonator
Real Time Counter (RTC) with clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous
wake-up with 1 ms resolution with maximum timeout of 2 seconds
— Support for real time counter (RTC) with clock source from external 32 KHz crystal oscillator, supporting
wake-up with 1 s resolution and maximum timeout of one hour
— RTC optionally clocked by fast 4–16 MHz external oscillator
System timers:
•
— Four-channel 32-bit System Timer Module (STM)
— Eight-channel 32-bit Periodic Interrupt Timer (PIT) module (including ADC trigger)
— Software Watchdog Timer (SWT)
•
•
System Integration Unit Lite (SIUL) module to manage external interrupts, GPIO and pad control
System Status and Configuration Module (SSCM)
— Provides information for identification of the device, last boot mode, or debug status
— Provides an entry point for the censorship password mechanism
•
•
Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified register interface,
enabling access to all clock sources
Clock Monitor Unit (CMU)
— Monitors the integrity of the fast (4–16 MHz) external crystal oscillator and the primary FMPLL (FMPLL0)
— Acts as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock
Mode Entry Module (MC_ME)
•
— Controls the device power mode, i.e., RUN, HALT, STOP, or STANDBY
— Controls mode transition sequences
— Manages the power control, voltage regulator, clock generation and clock management modules
Power Control Unit (MC_PCU) to implement standby mode entry/exit and control connections to power domains
Reset Generation Module (MC_RGM) to manage reset assertion and release to the device at initial power-up
Nexus Development Interface (NDI) per IEEE-ISTO 5001-2008 Class 3 standard with additional Class 4 features:
— Watchpoint Triggering
•
•
•
— Processor Overrun Control
•
•
Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator controller for regulating the 3.3–5 V supply voltage down to 1.2 V for core logic (requires
external ballast transistor)
1
•
Package:
— 176 LQFP, 0.5 mm pitch, 24 mm 24 mm outline
1. See the device comparison table for package offerings for each device in the family.
PXD20 Microcontroller Data Sheet, Rev. 2
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
— 208 LQFP, 0.5 mm pitch, 28 mm 28 mm outline
— 416 TEPBGA, 1mm ball pitch, 27 mm 27 mm outline
1.4
Feature details
1.4.1
Low-power operation
The PXD20 is designed for optimized low-power operation and dynamic power management of the CPU and peripherals.
Power management features include software-controlled clock gating of peripherals and multiple power domains to minimize
leakage in low-power modes.
There are three low-power modes:
•
•
•
STANDBY
STOP
HALT
and five dynamic power modes — RUN[0..3] and DRUN. All low-power modes use clock gating to halt the clock for all or part
of the device.
STANDBY mode turns off the power to the majority of the chip to offer the lowest power consumption mode.
The device can be awakened from STANDBY mode via from any of up to 23 I/O pins, a reset or from a periodic wake-up using
a low power oscillator. If required, it is possible to enable the internal 16 MHz oscillator, the external 4–16 MHz oscillator and
the external 32 KHz oscillator.
In STANDBY mode the contents of the CPU, on-chip peripheral registers and potentially some of the volatile memory are lost.
The two possible configurations in STANDBY mode are:
•
•
The device retains 64 KB of the on-chip SRAM, but the content of the graphics SRAM is lost.
The device retains 8 KB of the on-chip SRAM, but the content of the graphics SRAM is lost.
STOP mode maintains power to the entire device allowing the retention of all on-chip registers and memory, and providing a
faster recovery low power mode than the lowest-power STANDBY mode. There is no need to reconfigure the device before
executing code. The clocks to the CPU and peripherals are halted and can be optionally stopped to the oscillator or PLL at the
expense of a slower start-up time.
STOP is entered from RUN mode only. Wake-up from STOP mode is triggered by an external event or by the internal periodic
wake-up, if enabled.
RUN modes are the main operating modes where the entire device can be powered and clocked and from which most processing
activity is done. Four dynamic RUN modes are supported—RUN0 - RUN3. The ability to configure and select different RUN
modes enables different clocks and power configurations to be supported with respect to each other and to allow switching
between different operating conditions. The necessary peripherals, clock sources, clock speed and system clock prescalers can
be independently configured for each of the four RUN modes of the device.
HALT mode is a reduced activity, low power mode intended for moderate periods of lower processing activity. In this mode the
CPU system clocks are stopped but user-selected peripheral tasks can continue to run. It can be configured to provide more
efficient power management features (switch-off PLL, flash memory, main regulator, etc.) at the cost of longer wake up latency.
The system returns to RUN mode as soon as an event or interrupt is pending.
Table 2 summarizes the operating modes of the PXD20.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
Overview
1
Table 2. Operating mode summary
Clock sources
SoC features
Wake-up time2
RUN
On
CG
CG
Off
Off
OP OP OP On OP OP On OP On OP
3
—
—
FP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
HALT
OP OP OP On OP OP On OP On OP OP OP FP
3
TBD
24 µs
STOP
CG CG OP On CG CG OP OP On OP OP OP LP 350 µs 4 µs 20 µs 1 ms 200 µs
3
STANDBY
Off Off 64 Off Off Off OP OP OP OP OP OP LP 350 µs 8 µs 100 µs 1 ms 200 µs Var 28 µs
4
KB
Off Off
8
Off Off Off OP OP OP OP OP OP LP 200 µs 8 µs 100 µs 1 ms 200 µs Var 28 µs
5
KB
POR
500 µs 8 µs 100 µs 1 ms 200 µs
BAM
6
1
Table Key:
On—Powered and clocked
OP—Optionally configurable to be enabled or disabled (clock gated)
CG—Clock Gated, Powered but clock stopped
Off-—Powered off and clock gated
FP—VREG Full Performance mode
LP—VREG Low Power mode, reduced output capability of VREG but lower power consumption
Var—Variable duration, based on the required reconfiguration and execution clock speed
BAM—Boot Assist Module Software and Hardware used for device start-up and configuration
2
A high level summary of some key durations that need to be considered when recovering from low power modes. This
does not account for all durations at wake up. Other delays will be necessary to consider including, but not limited to the
external supply start-up time.
IRC Wake-up time must not be added to the overall wake-up time as it starts in parallel with the VREG.
All other wake-up times must be added to determine the total start-up time.
3
4
5
6
Either 64 KB or 8 KB available.
64 KB of the RAM contents is retained, but not accessible in STANDBY mode.
8 KB of the RAM contents is retained, but not accessible in STANDBY mode.
Dependent on boot option after reset.
Additional notes on low power operation:
•
Fast wake-up using the on-chip 16 MHz internal RC oscillator allows rapid execution from RAM on exit from low
power modes
•
The 16 MHz internal RC oscillator supports low speed code execution and clocking of peripherals when it is selected
as the system clock and can also be used as the PLL input clock source to provide fast start-up without the external
oscillator delay
•
The device includes an internal voltage regulator that includes the following features:
PXD20 Microcontroller Data Sheet, Rev. 2
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
— Regulates input to generate all internal supplies
— Manages power gating
— External ballast transistor for high power regulator
— Low-Power and Ultra-Low-Power regulators support operation when in STOP and STANDBY modes,
respectively, to minimize power consumption
— Startup on-chip regulators in <350 µs for rapid exit of STOP and STANDBY modes
— Low voltage detection on main supply and 1.2 V regulated supplies.
1.4.2
e200z4d core
The e200z4d Power Architecture core provides the following features:
•
•
•
•
•
Dual issue, 32-bit Power Architecture Book E compliant CPU
Implements the VLE APU for reduced code footprint
In-order execution and retirement
Precise exception handling
Branch processing unit
— Dedicated branch address calculation adder
— Branch target prefetching using 8-entry BTB
•
•
Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory
via independent Instruction and Data BIUs.
Load/store unit
— 2 cycle load latency
— Fully pipelined
— Big and Little endian support
— Misaligned access support
•
•
•
•
•
64-bit General Purpose Register file
Dual AHB 2.v6 64-bit System buses
Memory Management Unit (MMU) with 16-entry fully-associative TLB and multiple page size support
4 KB, 2/4-Way Set Associative Instruction Cache
Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the 64-bit General Purpose
Register file.
•
Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single-precision floating-point operations,
using the 64-bit General Purpose Register file.
•
•
Nexus Class 3 real-time Development Unit
Dynamic power management of execution units, cache and MMU
1.4.3
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between seven master ports and eight slave ports.
The crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows concurrent transactions to occur from any master port to any slave port but one of those transfers must be
an instruction fetch from internal flash. If a slave port is simultaneously requested by more than one master port, arbitration
logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions. Requesting masters having equal priority are granted access
to a slave port in round-robin fashion, based upon the ID of the last master to be granted access.
The crossbar provides the following features:
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
Overview
• Seven master ports:
— e200z4d core instruction port
— e200z4d core complex load/store data port
— eDMA controller
— DCU
— DCU-Lite
— VIU
— 2D Graphics Accelerator (GFX2D)
Seven slave ports:
•
— Platform Flash Controller (2 Ports)
— Platform SRAM Controller
— Graphics SRAM Controller (2 Ports)
— QuadSPI serial flash Controller and RLE Decoder
— Peripheral Bridge
•
•
32-bit internal address bus, 64-bit internal data bus
Programmable Arbitration Priority
— Requesting masters can be treated with equal priority and will be granted access to a slave port in round-robin
fashion, based upon the ID of the last master to be granted access or a priority order can be assigned by software
at application run time
•
Temporary dynamic priority elevation of masters
1.4.4
Enhanced Direct Memory Access (eDMA)
The eDMA module is a controller capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source
and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing
the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The
eDMA module provides the following features:
•
•
•
•
•
16 channels support independent 8-, 16- or 32-bit single value or block transfers
Supports variable sized queues and circular queues
Source and destination address registers are independently configured to post-increment or remain constant
Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request
Each DMA channel can optionally send an interrupt request to the CPU on completion of a single value or block
transfer
2
•
•
DMA transfers possible between system memories, QuadSPI, RLE Decoder, SPIs, I C, ADC, eMIOS and General
Purpose I/Os (GPIOs)
Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA channel with up to
a total of 64 potential request sources.
1.4.5
Interrupt Controller (INTC)
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
PXD20 Microcontroller Data Sheet, Rev. 2
10
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that
all tasks which share the resource can not preempt each other.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests. These same software
settable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority
portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts
a software settable interrupt request to finish the servicing in a lower priority ISR. Therefore these software settable interrupt
requests can be used instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following
features:
•
•
•
•
Unique 9-bit vector for each of the possible 128 separate interrupt sources
Eight software triggerable interrupt sources
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Ability to modify the ISR or task priority.
— Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources.
External non maskable interrupt directly accessing the main CPU critical interrupt mechanism
32 external interrupts
•
•
1.4.6
QuadSPI serial flash memory controller
The QuadSPI module enables use of external serial flash memories supporting single, dual and quad modes of operation. It
features the following:
•
•
•
•
•
Maximum serial clock frequency 80 MHz
Memory mapped read access for AHB crossbar switch masters
Automatic serial flash read command generation by CPU, eDMA, DCU, or DCU-Lite read access on AHB bus
Supports single, dual and quad serial flash read commands
Simultaneous mode:
— Supports concurrent read of two external serial flashes
— The quad data streams from the two flashes can be recombined in the QuadSPI to achieve up to 80 MB/s read
bandwidth with 80 MHz serial flash
•
•
•
1664-bit buffer with speculative fetch and buffer flush mechanisms to maximize read bandwidth of serial flash
DMA support
All Serial Flash program, erase, read and configuration commands available via IP bus interface.
1.4.7
System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal
peripheral multiplexing, and the system reset operation.
The GPIO features the following:
•
Up to four levels of internal pin multiplexing, allowing exceptional flexibility in the allocation of device functions for
each package
•
•
•
•
Centralized general purpose input output (GPIO) control
All GPIO pins can be independently configured to support pull-up, pull down, or no pull
Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
All peripheral pins can be alternatively configured as both general purpose input or output pins except ADC channels
which support alternative configuration as general purpose inputs
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
11
Overview
•
•
Direct readback of the pin value supported on all digital output pins through the SIU
Configurable digital input filter that can be applied to up to 24 general purpose input pins for noise elimination on
external interrupts
•
Register configuration protected against change with soft lock for temporary guard or hard lock to prevent
modification until next reset.
1.4.8
On-chip flash memory with ECC
The PXD20 microcontroller has the following flash memory features:
•
2 MB of flash memory
— Typical flash memory access time: 0 wait-state for buffer hits, 3 wait-states for page buffer miss at 125 MHz
— Two 4 × 128-bit page buffers with programmable prefetch control
–
One set of page buffers can be allocated for code-only, fixed partitions of code and data, all available for any
access
–
One set of page buffers allocated to Display Controller Units, Graphics Accelerator and the eDMA
— 64-bit ECC with single-bit correction, double-bit detection for data integrity
•
Small block flash arrangement to support features such as boot block, EEPROM Emulation, operating system block.
— 816 KB
— 264 KB
— 2128 KB
— 6256 KB
•
•
Hardware managed Flash writes, erase and verify sequence
Censorship protection scheme to prevent Flash content visibility
1.4.9
Static random-access memory (SRAM)
The PXD20 microcontroller has 64 KB general-purpose on-chip SRAM with the following features:
•
•
•
•
•
Typical SRAM access time: 1 wait-state for reads and 32-bit writes
32-bit ECC with single-bit correction, double bit detection for data integrity
Supports byte (8-bit), half word (16-bit), word (32-bit) and double-word (64-bit) writes for optimal use of memory
User transparent ECC encoding and decoding for byte, half word, and word accesses
Separate internal power domains applied to 56 KB and 8 KB SRAM blocks during STANDBY modes to retain
contents during low power mode.
1.4.10 On-chip graphics SRAM
The PXD20 microcontroller has 1 MB on-chip graphics SRAM with the following features:
•
Two crossbar slave ports:
— One dedicated to the 2D Graphics Accelerator (GFX2D) access
— One dedicated to all other crossbar masters
•
•
•
•
Usable as general purpose SRAM
Supports byte (8-bit), half word (16-bit), word (32-bit) and double-word (64-bit) writes for optimal use of memory
RAM controller with hardware RAM fill function supporting all-zeroes or all-ones SRAM initialization
Independent data buffers (one per AHB port) for maximum system performance
— Optimized for burst transfers (read + write)
— Programmable read prefetch capabilities
PXD20 Microcontroller Data Sheet, Rev. 2
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
1.4.11 Memory Protection Unit (MPU)
The MPU features the following:
•
•
•
•
•
•
•
Sixteen region descriptors for per master protection
Start and end address defined with 32-byte granularity
Overlapping regions supported
Protection attributes can optionally include process ID
Protection offered for 4 concurrent read ports
Read and write attributes for all masters
Execute and supervisor/user mode attributes for processor masters
1.4.12 2D graphics accelerator (GFX2D)
•
Native vector graphics rendering
— Compatible with OpenVG1.1
— Complete hardware OpenVG 1.1 rendering pipeline
— Both geometry and pixel processing
— Adaptive processing of Bezier curves and strokes
16-sample edge anti-aliasing
•
— High image quality, font scalability, etc.
— 4 Rotated Grid Supersampling (RGSS) AA for Flash
3D perspective texturing, reflections, and shadowing
Shading (linear or radial gradient)
•
•
•
•
Separate 2D engine for BitBlt, fill and ROP operations
Significant performance improvement when compared to software or 3D GPU-based OpenVG implementations
1.4.13 Display Control Unit (DCU3)
The DCU3 is a display controller designed to drive TFT LCD displays up to WVGA resolution using direct blit graphics and
video.
The DCU3 generates all the necessary signals required to drive the TFT LCD displays: up to 24-bit RGB data bus, Pixel Clock,
Data Enable, Horizontal-Sync and Vertical-Sync.
The flexible architecture of the DCU3 enables the display of OpenVG-rendered frame buffer content and direct blit rendered
graphics simultaneously.
An optional Timing Controller (TCON) and RSDS interface is available to directly drive the row and column drivers of a
display panel.
Internal memory resource of the device allows to easily handle complex graphics contents (pictures, icons, languages, fonts).
The DCU3 supports 4-plane blending and 16 graphics layers. Control Descriptors (CDs) associated with each of the 16 layers
enable effective merging of different resolutions into one plane to optimize use of internal memory buffers. A layer may be
constructed from graphic content of various resolutions including indexed colors of 1, 2, 4 and 8 bpp, direct colors of 16, 24
and 32 bpp, and a YUV 4:2:2 color space. The ability of the DCU3 to handle input data in resolutions as low as 1bpp, 2bpp and
4bpp enables a highly efficient use of internal memory resources of the PXD20. A special tiled mode can be enabled on any of
the 16 layers to repeat a pattern optimizing graphic memory usage.
A hardware cursor can be managed independently of the layers at blending level increasing the efficient use of the internal
DCU3 resources.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
Overview
To secure the content of all critical information to be displayed, a safety mode can be activated to check the integrity of critical
data along the whole system data path from the memory to the TFT pads.
The DCU3 features the following:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Display color depth: up to 24 bpp
Generation of all RGB and control signals for TFT
Four-plane blending
Maximum number of Input Layers: 16 (fixed priority)
Dynamic Look-Up-Table (Color and Gamma Look-Up)
blending range: up to 256 levels
Transparency Mode
Gamma Correction
Tiled mode on all the layers
Hardware Cursor
Supports YCrCb 4:2:2 input data format
RLE decode inline supporting direct read of RLE compressed images from system memory
Critical display content integrity monitoring for Functional Safety support
Internal Direct Memory Access (DMA) module to transfer data from internal and / or external memory.
The DCU3 also features a Parallel Data Interface (PDI) to receive external digital video or graphic content into the DCU3. The
PDI input is directly injected into the DCU3 background plane FIFO. When the PDI is activated, all the DCU3 synchronization
is extracted from the external video stream to guarantee the synchronization of the two video sources.
The PDI can be used to:
•
•
•
•
Connect a video camera output directly to the PDI
Connect a secondary display driver as slave with a minimum of extra cost
Connect a device gathering various Video sources
Provide flexibility to allow the DCU to be used in slave mode (external synchronization)
The PDI features the following:
•
Supported color modes:
— 8-bit mono
— 8-bit color multiplexed
— RGB565
— 16-bit/18-bit RAW color
Supported synchronization modes:
— embedded ITU-R BT.656-4 (RGB565 mode 2)
— HSYNC, VSYNC
•
— Data Enable
•
•
Direct interface with DCU3 background plane FIFO
Synchronization generation for the DCU3
1.4.14 Display Control Unit Lite (DCULite)
The DCULite is a display controller designed to enable the PXD20 to drive a second TFT LCD display up to XGA resolution
using direct blit graphics and video. The DCULite includes all features of the DCU3, including the PDI with the following
exceptions:
•
•
•
Reduced from 4-plane to 2-plane blending
Reduced from 16 layers to 4 layers
Reduced CLUT size
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
14
Freescale Semiconductor
Overview
1.4.15 Timing controller (TCON) and RSDS interface
The TCON enables direct drive of the row and column drivers of display panels enabling emulation of TCON ICs used in
display panels.
•
Programmable Timing Generation unit featuring 12 waveform generators allowing high degree of flexibility in panel
waveform generation
•
•
Reduced Swing Differential Signaling (RSDS) interface for RGB data and pixel clock
Conforms to “RSDS ‘Intra Panel’ Interface Specification” Rev. 1.0 (National Semiconductor)
1.4.16 RLE decoder
The RLE decoder is a crossbar slave sharing a slave port with the QuadSPI module. The platform eDMA is used to stream
compressed image data into and extract decompressed data out of the RLE Decoder.
•
•
•
•
•
Lossless decompression
Pixel formats supported: 8bpp, 16bpp, 24bpp and 32bpp
AHB mapped read and write registers in RLE_DEC to achieve higher throughput
Programmable fill levels of read and write buffers for initiating burst transfers
Crop feature: Support for selectively reading out a part of decompressed image data taking complete compressed data
for the full image as input.
1.4.17 DRAM controller
The DRAM controller is a multi-port DRAM controller supporting SDR, LPDDR1, DDR-1, and DDR-2 memories. The DRAM
controller listens to the incoming requests to the seven buses in parallel and then sends commands to the DRAM from the
highest priority bus at the current time
The seven incoming 64-bit buses are:
•
•
•
•
•
•
•
DCU3
DCULite
e200z4d core - instruction bus
e200z4d core - data bus
VIU2
GFX2D
eDMA
The DRAM controller features the following:
•
•
Supports CAS latency of 2, 3, and 4 clock cycles.
Master buses
— 7 incoming master buses
— Supports 16-byte and 32-byte bursts
— Supports byte enables
— Supports 4-bit priority signal for each bus
Write buffer contains five 32-byte entries
•
•
•
•
•
Supports 16-wide and 32-wide SDR, DDR1, DDR2 and LPDDR1 DRAM devices
Controller supports one chip select, 8-bank DRAM system
Supports dynamic on-die termination in the host device and in the DRAM.
Supports memory sizes as small as 64Mbit
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Overview
1.4.18 Video Input Unit (VIU2)
The VIU2 is a crossbar master module accepting an ITU656 compatible video input stream on a parallel interface, converting
the pixel data to RGB or YUV format and transferring the video image to internal frame buffer memory or external DRAM if
available.
•
•
Supports 8-bit/10-bit ITU656 video input
Output formats:
— RGB888
— RGB565
— 8-bit monochrome
— YCrCb 4:2:2
•
•
•
•
Video downscaling
Contrast and Brightness adjustment
De-interlace for interlaced video image
Internal DMA engine for data transfer to memory
1.4.19 Boot assist module (BAM)
The BAM is a block of read-only memory that is programmed once by Freescale. The BAM program is executed every time
the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are:
•
•
•
Booting from internal flash memory
Serial boot loading (A program is downloaded into RAM via CAN or LIN and then executed)
Booting from external memory
Additionally the BAM:
•
•
•
Enables and manages the transition of the MCU from reset to user code execution
Configures device for serial bootload
Enables multiple bootcode starting locations out of reset through implementation of search for valid Reset
Configuration Halfword
•
Enables or disables software watchdog timer out of reset through BAM read of Reset Configuration Halfword option
bit
1.4.20 Enhanced Modular Input/Output System (eMIOS)
This device has two eMIOS modules, each with 16 channels supporting a range of 16-bit Input Capture, Output Compare, Pulse
Width Modulation, and Quadrature Decode functions.
•
Selectable clock source from primary FMPLL, secondary FMPLL, external 4–16 MHz oscillator or 16 MHz Internal
RC oscillator on a per module basis
•
•
•
•
Timed I/O channels with 16-bit counter resolution
Buffered updates
Support for shifted PWM outputs to minimize occurrence of concurrent edges
Edge aligned output pulse width modulation
— Programmable pulse period and duty cycle
— Supports 0% and 100% duty cycle
— Shared or independent time bases
Programmable phase shift between channels
4 channels of Quadrature Decode
•
•
•
DMA transfer support
PXD20 Microcontroller Data Sheet, Rev. 2
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
1.4.21 Analog-to-digital converter (ADC)
The ADC features the following:
•
•
•
•
•
10-bit A/D resolution
0–5 V or 0–3.3 V common mode conversion range
Supports conversions speeds of up to 1s
20 internal and 8 external channels support
Up to 20 single-ended inputs channels
— 10 channels configured as input only pins
–
10-bit ± 2 counts accuracy (TUE)
— 10 channels configured to have alternate function as general purpose input/output pins
10-bit ± 3 counts accuracy (TUE)
–
•
External multiplexer support to increase up to 27 channels
— Automatic 1 × 8 multiplexer control
— External multiplexer connected to a dedicated input channel
— Shared register between the 8 external channels
Result register available for every non-multiplexed channel
Configurable Left or Right aligned result format
Supports for one-shot, scan and injection conversion modes
Injection mode status bit implemented on adjacent 16-bit register for each result
— Supports Access to Result and injection status with single 32-bit read
Independently enabling of function for channels:
— Pre-sampling
•
•
•
•
•
— Offset error cancellation
— Offset Refresh
•
•
Conversion Triggering support
— Internal conversion triggering from periodic interrupt timer (PIT)
Four configurable analog comparator channels offering range comparison with triggered alarm
— Greater than
— Less than
— Out of range
•
•
•
•
All unused analog pins available as general purpose input pins
Selected unused analog pins available as general purpose pins
Power Down mode
Optional support for DMA transfer of results
1.4.22 Serial Peripheral Interface (SPI)
The SPI modules provide a synchronous serial interface for communication between the MCU and external devices.
The SPI features:
•
•
•
•
•
•
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Overview
•
•
Programmable data frames from 4 to 16 bits
Up to 3 chip select lines available, depending on package and pin multiplexing, enable 8 external devices to be selected
using external muxing from a single SPI
•
•
•
•
•
Eight clock and transfer attributes registers
Chip select strobe available as alternate function on one of the chip select pins for de-glitching
FIFOs for buffering up to 4 transfers on the transmit and receive side
General purpose I/O functionality on pins when not used for SPI
Queueing operation possible through use of eDMA
1.4.23 Controller Area Network (CAN) module
The PXD20 includes up to three controller area network (CAN) modules. The CAN module is a communication controller
implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in
the EMI environment of a vehicle, cost-effectiveness and required bandwidth.
Each CAN module offers the following:
•
•
Compliant with CAN protocol specification, Version 2.0B active
64 mailboxes, each configurable as transmit or receive
— Mailboxes configurable while module remains synchronized to CAN bus
Transmit features
•
— Supports configuration of multiple mailboxes to form message queues of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
Receive features
•
•
— Individual programmable filters for each mailbox
— 8 mailboxes configurable as a 6-entry receive FIFO
— 8 programmable acceptance filters for receive FIFO
Programmable clock source
— System clock
— Direct oscillator clock to avoid PLL jitter
Listen only mode capabilities
•
•
CAN Sampler
— Can catch the 1st message sent on the CAN network while the MCU is stopped. This guarantees a clean startup
of the system without missing messages on the CAN network.
— The CAN sampler is connected to one of the CAN RX pins.
1.4.24 Serial communication interface module (UART)
The PXD20 devices include up to four UART modules and support for UART Master mode, UART Slave mode and UART
mode. The modules are UART state machine compliant to the LIN 1.3 and 2.0 and 2.1 Specifications and handle UART frame
transmission and reception without CPU intervention.
The serial communication interface module offers the following:
•
UART features:
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
18
Freescale Semiconductor
Overview
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
–
Parity, noise and framing errors
— Interrupt driven operation with 4 interrupts sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— 2 receiver wake-up methods
•
LIN features:
— Autonomous LIN frame handling
— Message buffer to store identifier and up to eight data bytes
— Supports message length of up to 64 bytes
— Detection and flagging of LIN errors
— Sync field; Delimiter; ID parity; Bit, Framing; Checksum and Timeout errors
— Classic or extended checksum calculation
— Configurable Break duration of up to 36-bit times
— Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features
–
–
–
Loop back
Self Test
LIN bus stuck dominant detection
— Interrupt driven operation with 16 interrupt sources
— LIN slave mode features
–
–
–
Autonomous LIN header handling
Autonomous LIN response handling
Discarding of irrelevant LIN responses using up to 16 ID filters
1.4.25 Inter-Integrated Circuit (I2C) controller modules
2
The PXD20 includes four I C modules. Each module features the following:
•
•
•
•
•
•
•
•
•
•
•
•
Two-wire bi-directional serial bus for on-board communications
2
Compatibility with I C bus standard
Multi-master operation
Software-programmable for one of 256 different serial clock frequencies
Software-selectable acknowledge bit
Interrupt-driven, byte-by-byte data transfer
Arbitration-lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
19
Overview
1.4.26 System clocks and clock generation modules
The system clock on the PXD20 can be derived from an external oscillator, an on-chip FMPLL, or the internal 16 MHz
oscillator.
The source system clock frequency can be changed via an on-chip programmable clock divider (1 to 2). An additional
programmable peripheral bus clock divider (ratios 1 to ) is also available.
The PXD20 has two on-chip FMPLLs (primary and secondary). Each features the following:
•
•
•
•
Input clock frequency from 4 MHz to 16 MHz
Lock detect circuitry continuously monitors lock status
Loss Of Clock (LOC) detection for reference and feedback clocks
On-chip loop filter (for improved electromagnetic interference performance and reduction of number of external
components required)
•
Support for frequency ramping from PLL
The primary FMPLL module is for use as a system clock source. The secondary FMPLL is available for use as an alternate,
modulated or non-modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation.
The main oscillator provides the following features:
•
•
•
•
•
•
Input frequency range 4–16 MHz
Square-wave input mode
Oscillator input mode 3.3 V (5.0 V)
Automatic level control
Low power consumption
PLL reference
The PXD20 also includes the following oscillators:
•
•
32 KHz low power external oscillator for slow execution, low power, and RTC
Dedicated internal 128 kHz RC oscillator for low power mode operation and self wake-up
— ±10% accuracy across voltage and temperature (after factory trimming)
— Trimming registers to support improved accuracy with in-application calibration
Dedicated 16 MHz internal RC oscillator
•
— Used as default clock source out of reset
— Provides a clock for rapid start-up from low power modes
— Provides a back-up clock in the event of PLL or External Oscillator clock failure
— Offers an independent clock source for the SWT
— ±5% accuracy across voltage and temperature (after factory trimming)
— Trimming registers to support frequency adjustment with in-application calibration
1.4.27 Periodic interrupt timer (PIT)
The PIT features the following:
•
•
•
•
Eight general purpose interrupt timers
Two dedicated interrupt timers for triggering ADC conversions
32-bit counter resolution
Clocked by system clock frequency
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
20
Freescale Semiconductor
Overview
1.4.28 Real time counter (RTC)
The Real Timer Counter supports wake-up from Low Power modes or Real Time Clock generation
•
Configurable resolution for different timeout periods
— 1 s resolution for >1 hour period
— 1 ms resolution for 2 second period
•
Selectable clock sources from external 32 KHz crystal, external 4–16 MHz crystal, internal 128 kHz RC oscillator or
divided internal 16 MHz RC oscillator
1.4.29 System timer module (STM)
The STM is a 32-bit timer designed to support commonly required system and application software timing functions. The STM
includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is
driven by the system clock divided by an 8-bit prescale value (1 to 256).
•
•
•
•
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode
1.4.30 Software watchdog timer (SWT)
The SWT features the following:
•
•
•
•
•
•
Watchdog supporting software activation or enabled out of Reset
Supports normal or windowed mode
Watchdog timer value writable once after reset
Watchdog supports optional halting during low power modes
Configurable response on timeout: reset, interrupt, or interrupt followed by reset
Clock source: 128 kHz RC oscillator
1.4.31 Stepper motor controller (SMC)
The SMC module is a PWM motor controller suitable to drive instruments in a cluster configuration or any other loads requiring
a PWM signal. The motor controller has twelve PWM channels associated with two pins each (24 pins in total) driving up to 6
stepper motors.
The SMC module includes the following features:
•
•
•
•
•
10/11-bit PWM counter
11-bit resolution with selectable PWM dithering function
Left, right, or center aligned PWM
Output slew rate control
Output Short Circuit Detection
This module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. This
module can be used for other motor control or PWM applications that match the frequency, resolution, and output drive
capabilities of the module.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
21
Overview
1.4.32 Stepper stall detect (SSD) module
The SSD module provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using
full steps when the gauge pointer is returning to zero (RTZ).
The SSD module features the following:
•
•
•
•
•
Programmable full step state
Programmable integration polarity
Blanking (recirculation) state
16-bit integration accumulator register
16-bit modulus down counter with interrupt
1.4.33 Sound generator module (SGM)
The SGM features the following:
•
•
•
•
4-channel audio mixer
Each channel capable of independent Tone generation or Wave playback
Individual channel volume control (8-bit resolution)
Tone Mode:
—
—
—
Programmable Tone frequency
Programmable amplitude envelope: attack, duration and decay
Programmable number of tone pulses and inter-tone duration
•
Wave Mode:
—
—
One FIFO per channel working in conjunction with eDMA
Supports standard audio sampling rates (4 kHz, 8 kHz, 11.025 kHz, 16 kHz, 22.050 kHz, 32 kHz, 44.100 kHz,
48 kHz)
—
—
—
—
Same sample rate applies to all channels
8-bit, 12-bit, 16-bit input data formats
Programmable wave duration and inter-wave duration
Repeat mode with programmable number of wave playbacks
•
SGM Output:
—
—
16-bit PWM channel
2
Integrated I S master interface for connection to external audio DAC
1.4.34 IEEE 1149.1 JTAG controller (JTAGC)
JTAGC features the following:
•
•
Backward compatible to standard JTAG IEEE 1149.1-2001 test access port (TAP) interface
Support for boundary scan testing
1.4.35 Nexus Development Interface (NDI)
The Nexus 3 module is compliant with Class 3 of the IEEE-ISTO 5001-2008 standard, with additional Class 4 features
available. The following features are implemented:
•
Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program flow discontinuities
(direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between
the discontinuities. Thus static code may be traced.
PXD20 Microcontroller Data Sheet, Rev. 2
22
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
•
•
Data Trace via Data Write Messaging (DWM) and Data Read Messaging (DRM). This provides the capability for the
development tool to trace reads and/or writes to selected internal memory resources.
Ownership Trace via Ownership Trace Messaging (OTM). OTM facilitates ownership trace by providing visibility of
which process ID or operating system task is activated. An Ownership Trace Message is transmitted when a new
process/task is activated, allowing the development tool to trace ownership flow.
•
Run-time access to embedded processor memory map via the JTAG port. This allows for enhanced download/upload
capabilities.
•
•
•
Watchpoint Messaging via the auxiliary pins
Watchpoint Trigger enable of Program and/or Data Trace Messaging
Data Acquisition Messaging (DQM) allows code to be instrumented to export customized information to the Nexus
Auxiliary Output Port.
•
Address Translation Messaging via program correlation messages displays updates to the TLB for use by the debugger
in correlating virtual and physical address information
•
•
•
Auxiliary interface for higher data input/output
Registers for Program Trace, Data Trace, Ownership Trace and Watchpoint Trigger.
All features controllable and configurable via the JTAG port
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Pinout and signal descriptions
2
Pinout and signal descriptions
2.1
176 LQFP package pinout
Figure 2 shows the pinout for the 176-pin LQFP package.
DCU_VSYNC / PG8
1
VDDE_B
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
DCU_HSYNC / PG9
2
PA13 / DCU_G5
DCU_DE / PG10
3
PA12 / DCU_G4
eMIOS0[8] / eMIOS1[9] / PDI_HSYNC_VIU1 / PJ1
4
PA11 / DCU_G3
eMIOS0[9] / eMIOS1[14] / PDI_VSYNC_VIU0 / PJ2
5
PA10 / DCU_G2
VDDE_B
6
PA9 / DCU_G1 / SDA_2 / eMIOS0[19]
PA8 / DCU_G0 / SCL_2 / eMIOS0[20]
PA7 / DCU_R7
VSS
7
eMIOS0[13] / eMIOS0[17] / PDI4_VIU6 / PJ8
8
eMIOS0[12] / eMIOS1[22] / PDI5_VIU7 / PJ9
9
PA6 / DCU_R6
eMIOS0[11] / eMIOS1[17] / PDI6_VIU8 / PJ10
10
VSS
eMIOS0[10] / eMIOS1[15] / PDI7_VIU9 / PJ11
11
VDDE_B
RXD_0 / CNRX_0 / PB1
12
PA5 / DCU_R5
TXD_0 / CNTX_0 / PB0
13
PA4 / DCU_R4
I2S_DO / CNRX_1 / PB10
14
PA3 / DCU_R3
SGM_MCLK / CNTX_1 / PB11
15
PA2 / DCU_R2
DCU_TAG / eMIOS1[22] / PDI13_VIU5 / PM5
PA1 / DCU_R1 / SCL_1 / eMIOS0[17]
PA0 / DCU_R0 / SDA_1 / eMIOS0[18]
PM11 / TXD_2 / CNTX_2 / eMIOS0[23]
PM10 / RXD_2 / CNRX_2 / eMIOS0[16]
PM9/ PDI_PCLK/ SGM_MCLK/ eMIOS0[8]
VDDE_B
16
eMIOS1[23] / PDI14_VIU6 / PM6
17
VSS
18
VDDE_B
19
VDDR
20
VSSR
21
PXD20
176 LQFP
Top view
VSUP_TEST
VSS
VDD12
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VDD12
VSS
PD15 / M3C1P / SSD3_3 / eMIOS0[15]
PD14 / M3C1M / SSD3_2 / eMIOS0[14]
PD13 / M3C0P / SSD3_1 / eMIOS0[13]
PD12 / M3C0M / SSD3_0 / eMIOS0[12]
VSSM
VDDPLL
VREG_BYPASS
EXTAL
XTAL
VRC_CTRL
VDDM
RESET
PD11 / M2C1P / SSD2_3 / eMIOS0[11]
PD10 / M2C1M / SSD2_3 / eMIOS0[10]
PD9 / M2C0P / SSD2_1 / eMIOS0[9]
PD8 / M2C0M / SSD2_0
PD7 / M1C1P / SSD1_3
PD6 / M1C1M / SSD1_2 / eMIOS0[23]
PD5 / M1C0P / SSD1_1 / eMIOS0[16]
PD4 / M1C0M / SSD1_0 / eMIOS0[8]
VSSM
eMIOS1[10] / PDI8_VIU0 / PK2
eMIOS1[11] / PDI9_VIU1 / PK3
eMIOS1[12] / PDI10_VIU2 / PK4
eMIOS1[13] / PDI11_VIU3 / PK5
eMIOS1[9] / PDI12_VIU4 / PK6
VSS
98
97
VDDE_B
96
eMIOS1[8] / I2S_FS / PDI15_VIU7 / PH5
eMIOS1[16] / I2S_DO / PDI16_VIU8 / PM7
eMIOS1[23] / I2S_SCK / PDI17_VIU9 / PM8
TCK / PH0
95
VDDM
94
PD3 / M0C1P / SSD0_3 / eMIOS0[9]
PD2 / M0C1M / SSD0_2 / eMIOS1[23]
PD1 / M0C0P / SSD0_1 / eMIOS1[16]
PD0 / M0C0M / SSD0_0 / eMIOS1[8]
VDDE_B
93
92
TDI / PH1
91
TDO / PH2
90
TMS / PH3
89
Note: Functions in bold are
available only on this package.
Figure 2. 176-pin LQFP pinout
PXD20 Microcontroller Data Sheet, Rev. 2
24
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Pinout and signal descriptions
2.2
208 LQFP package pinout
Figure 3 shows the pinout for the 208-pin LQFP package.
DCU_VSYNC_TCON2 / PG8
DCU_HSYNC_TCON1 / PG9
1
2
3
4
5
6
7
8
9
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VDDE_B
PA13 / DCU_G5 / RSDS6M
PA12 / DCU_G4 / RSDS6P
PA11 / DCU_G3 / RSDS5M
PA10 / DCU_G2 / RSDS5P
PA9 / DCU_G1 / SDA_2 / eMIOS0[19] / RSDS4M
PA8 / DCU_G0 / SCL_2 / eMIOS0[20] / RSDS4P
PA7 / DCU_R7 / RSDS3M
PA6 / DCU_R6 / RSDS3P
VSS
DCU_DE_TCON3 / PG10
eMIOS0[8] / eMIOS1[9] / PDI_HSYNC_VIU1 / PJ1
eMIOS0[9] / eMIOS1[14] / PDI_VSYNC_VIU0 / PJ2
VDDE_B
VSS
eMIOS0[13] / eMIOS0[17] / PDI4_VIU6 / PJ8
eMIOS0[12] / eMIOS1[22] / PDI5_VIU7 / PJ9
eMIOS0[11] / eMIOS1[17] / PDI6_VIU8 / PJ10 10
eMIOS0[10] / eMIOS1[15] / PDI7_VIU9 / PJ11 11
RXD_0 / CNRX_0 / PB1 12
TXD_0 / CNTX_0 / PB0 13
I2S_DO / CNRX_1 / PB10 14
SGM_MCLK / CNTX_1 / PB11 15
TCON4 / RXD_3 / CNRX_2 / PM3 16
TCON5 / TXD_3 / CNTX_2 / PM4 17
VSS 18
VDDE_B
VREF_RSDS
PA5 / DCU_R5 / RSDS2M
PA4 / DCU_R4 / RSDS2P
PA3 / DCU_R3 / RSRS1M
PA2 / DCU_R2 / RSDS1P
PA1 / DCU_R1 / SCL_1 / eMIOS0[17] / RSDS0M
PA0 / DCU_R0 / SDA_1 / eMIOS0[18] / RSDS0P
VDDE_B
VDDE_B 19
PXD20
208 LQFP
Top view
VDDR 20
VSS
VDD12
VSSR 21
VSUP_TEST 22
PE7 / M5C1P / SSD5_3
PE6 / M5C1M / SSD5_2
PE5 / M5C0P / SSD5_1
PE4 / M5C0M / SSD5_0
VSSM
VDD12 23
VSS 24
VDDPLL 25
VREG_BYPASS 26
EXTAL 27
VDDM
XTAL 28
PE3 / M4C1P / SSD4_3
PE2 / M4C1M / SSD4_2
PE1 / M4C0P / SSD4_1
PE0 / M4C0M / SSD4_0
PD15 / M3C1P / SSD3_3 / eMIOS0[15]
PD14 / M3C1M / SSD3_2 / eMIOS0[14]
PD13 / M3C0P / SSD3_1 / eMIOS0[13]
PD12 / M3C0M / SSD3_0 / eMIOS0[12]
VSSM
VRC_CTRL 29
RESET 30
TCON6 / PDI13_VIU5 / CS2_2 / PL4 31
TCON7 / PDI14_VIU6 / CS1_2 / PL5 32
eMIOS1[18] / PDI15_VIU7 / CS0_2 / PL6 33
eMIOS1[19] / PDI16_VIU8 / SIN_2 / PL7 34
eMIOS1[20] / PDI17_VIU9 / SOUT_2 / PL8 35
eMIOS1[21] / PDI_PCLK / SCK_2 / PL9 36
VDDE_B 37
VDDM
VSS 38
PD11 / M2C1P / SSD2_3 / eMIOS0[11]
PD10 / M2C1M / SSD2_2 / eMIOS0[10]
PD9 / M2C0P / SSD2_1 / eMIOS0[9]
PD8 / M2C0M / SSD2_0
PD7 / M1C1P / SSD1_3
PD6 / M1C1M / SSD1_2 / eMIOS0[23]
PD5 / M1C0P / SSD1_1 / eMIOS0[16]
PD4 / M1C0M / SSD1_0 / eMIOS0[8]
VSSM
DCULITE_TAG / eMIOS1[10] / PDI8_VIU0 / PK2 39
DCULITE_DE / eMIOS1[11] / PDI9_VIU1 / PK3 40
DCULITE_HSYNC / eMIOS1[12] / PDI10_VIU2 / PK4 41
DCULITE_VSYNC / eMIOS1[13] / PDI11_VIU3 / PK5 42
DCULITE_PCLK / eMIOS1[9] / PDI12_VIU4 / PK6 43
TCON8 / DCULITE_R2 / RXD_2 / PK7 44
TCON9 / DCULITE_R3 / TXD_2 / PK8 45
TCON10 / DCULITE_R4 / I2S_DO / PK9 46
VSS 47
VDDM
VDDE_B 48
PD3 / M0C1P / SSD0_3 / eMIOS0[9]
PD2 / M0C1M / SSD0_2 / eMIOS1[23]
PD1 / M0C0P / SSD0_1 / eMIOS1[16]
PD0 / M0C0M / SSD0_0 / eMIOS1[8]
VDDE_B
TCK / PH0 49
TDI / PH1 50
TDO / PH2 51
TMS / PH3 52
Figure 3. 208-pin LQFP pinout
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
2.3
416 TEPBGA package pinout–40 to 105°C
Figure 4 shows the pinout for the 416 TEPBGA package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ddr_dq[2 ddr_dq[2 ddr_dq[2 ddr_dq[2
ddr_addr ddr_addr ddr_addr ddr_addr ddr_addr
A
B
A
B
30]
31] ddr_ba[0]ddr_ba[1]ddr_ba[2]
PG12
PF14
PF10
PF8
PF5
PF3
PK0
PB3
PJ12
PL11
PG7
PG6
6]
7]
8]
9]
ess[0]
ess[4]
ess[6]
ess[8]
ess[12]
ddr_dq[2
5]
ddr_dqs[ ddr_dm[3
ddr_addr
ess[1]
ddr_addr ddr_addr
ddr_addr
ess[15]
VSS
VSS
ddr_cas ddr_ras
VSS
ddr_web
VSS
VSS
VSS
PF13
PF12
PF11
VDDE
VSS
PF15
PF7
VSS
VDDE
PF4
PF1
PF0
PK1
VDDE
VSS
PJ15
PJ14
PJ13
PL13
PL12
PM2
PG11
PA15
PA11
PA10
PA3
VDDE
PL10
VSS
PG3
PG5
PG4
PG1
PG0
PA12
PA7
3]
]
ess[7]
VSS
ess[9]
ddr_dq[2 VDDE_DD
3]]
ddr_dq[2 VDDE_DD
4]
ddr_dramVDDE_DD
_clk DR
ddr_addr VDDE_DD
ess[2]
ddr_addr VDDE_DD
ess[10]
C
C
VSS
VSS
VSS
R
R
R
R
ddr_dq[1 ddr_dq[2 ddr_dq[2 ddr_dq[2
VDD33_D ddr_dram
ddr_addr ddr_addr VDD33_D ddr_addr ddr_addr ddr_addr
VREF_RS
DS2
D
D
ddr_cke ddr_cs
PF9
PF6
PB2
PG2
ddr_odt
9]
0]
1]
2]
DR
_clkb
ess[3]
ess[5]
DR
ess[11] ess[13] ess[14]
ddr_dq[1
7]
VDDE_DD ddr_dq[1
E
E
VSS
VSS
PA14
PA9
VDDE
PA13
PA8
R
8]
ddr_dq[1
6]
VDD33_D
DR
F
F
MVTT3
VSS
ddr_dq[1 ddr_dqs[ ddr_dm[2 ddr_dq[1
G
H
G
H
5]
2]
]
4]
ddr_dq[1
3]
VDDE_DD ddr_dq[1
VSS
VDDE
VSS
VA6
PA4
R
2]
ddr_dq[1
1]
VREF_RS
DS1
J
J
MVTT2
VSS
MVREF
PA5
ddr_dqs[ ddr_dm[1 ddr_dq[1
K
K
ddr_dq[9]
VDD12
VSS
VSS
VDD12
VSS
VDD12
VSS
VSS
VDD12
VSS
VDD12
VSS
VSS
VDD12
VSS
VDD12
VSS
VSS
VDD12
VSS
PA2
VSS
PM12
PO6
PA1
PA0
1]
]
0]
VDDE_DD
R
L
L
ddr_dq[8] VSS
ddr_dq[7]
PM13
PO7
PO3
PO0
PE7
VDDE
PO5
PO2
VSS
PJ0
M
N
M
N
ddr_dq[5] MVTT1
VSS ddr_dq[6]
VDD12
VSS
VSS
VSS
VDD12
VSS
PO4
PO1
PN14
PN12
PE2
ddr_dqs[ VDDE_DD
ddr_dq[3]
ddr_dq[4]
VDD12
VSS
VSS
VSS
VSS
VSS
VDD12
VSS
VDDE
PN15
PE6
0]
R
ddr_dm[0
P
P
ddr_dq[1] VSS
ddr_dq[2]
VDD12
VSS
VSS
VSS
VSS
VSS
VDD12
VSS
]
VDD33_D
DR
R
R
ddr_dq[0] MVTT0
VSS
VDD12
VSS
VSS
VSS
VSS
VSS
VDD12
VSS
PN13
PE3
VDDE_DD
R
T
T
PG10
PJ9
PG9
PJ8
PG8
PJ1
VDD12
VSS
VDD12
VSS
VSS
VDD12
VSS
VSS
VDD12
VSS
PE5
PE4
U
U
PJ2
PJ11
VDDE
PM3
VDD12
VDD12
VDD12
VDD12
PE1
VSSM
PD14
VDDM
PD8
VDDM
PD13
VSSM
PD7
PE0
V
V
PB1
VSS
PJ10
PD15
PD11
PD9
PD12
PD10
PD6
PD4
PD0
PC2
PC5
PC8
W
Y
W
Y
RESET
VSS
PB10
PM4
PB0
PB11
VDDREG
VDDPLL
PK4
VREG_BY VRC_CTR
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
XTAL
EXTAL
PD5
VSSM
PD2
VDDM
PD1
PASS
L
PL4
VSS
PD3
VSUP_TE
ST
VSSEH_A
DC
PL5
VDDE
VSS
PN0
PN1
PK2
PK6
PK7
PK8
PH0
PH1
PH2
PF2
VDDE
VSS
PB13
EVTI
PK11
MSEO
PM0
PN2
VSS
PN4
PN5
PN6
PN8
PN9
PB9
VDDE
VSS
PB7
PJ4
PJ5
PJ7
PJ3
PB5
VSS
MCKO
MDO6 MDO10 MVO0
PC0
PC6
PL1
VDDA
VSSA
PL0
PC3
PC1
VDDEH_A
DC
PL6
PL7
VSS
MSEO2 MDO7
VDDE
VSS
MDO1
MDO2
PC4
PC7
VDDE
EVTO
VDDE
PN10
PH4
VDDE
MDO4
MDO8
PC10
PC11
PC9
PL8
PL9
PK3
PK5
PK9
PH3
PB12
PK10
PM1
PN3
PN7
PN11
PB8
PJ6
PB4
PB6
MDO5
MDO9 MDO11 MDO3
18 20
PL3
PL2
PC15
PC14
PC13
PC12
4
5
6
7
8
9
10
11
14
16
17
21
22
25
1
2
3
12
13
15
19
23
24
26
Figure 4. 416 TEPBGA pinout
Pinout and signal descriptions
2.4
Signal description
The following sections provide signal descriptions and related information about the signals’ functionality and configuration.
2.4.1
Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are floating with the following exceptions:
•
•
•
•
PB[5] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash memory.
RESET pad is driven low. This is released only after PHASE2 reset completion.
Fast (4-16 MHz) external oscillator pads (EXTAL, XTAL) are tristate.
The following pads are pull-up:
— PB[6]
— PH[0]
— PH[1]
— PH[3]
2.4.2
Voltage supply pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.
Table 3. Voltage supply pin descriptions
Pin number
Supply pin
Function
176 LQFP
208 LQFP
416 TEPBGA
1
VDD12
1.2 V core supply (1.08 V - 1.32 V)
23, 50, 67, 110, 138, 23, 58, 79, 136, 162, K10,K12,K14,K16,L
175
186, 207
11,L13,L15,L17,M1
0,M16,N11,N17,P1
0,P16,R11,R17,T10
,T12,T14,T16,U11,
U13,U15,U17
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Pinout and signal descriptions
Table 3. Voltage supply pin descriptions (continued)
Pin number
208 LQFP
Supply pin
Function
176 LQFP
416 TEPBGA
VSS
1.2 V ground
7, 18, 36, 49, 66, 68, 7, 18, 38, 47, 57, 64, AB3,AD10,AD16,A
111, 123, 133, 139, 78, 80, 137, 147, D4,AE13,AE19,AE2
154, 167, 176
157, 163, 185, 199, ,AE7,B11,B14,B19,
208
B2,B25,B5,B8,C12,
C15,C17,C21,C3,C
6,C9,E2,E24,F3,H2
,H25,J3,K11,K13,K
15,K17,K24,L10,L1
2,L14,L16,L2,M11,
M12,M13,M14,M15,
M17,M3,N10,N12,N
13,N14,N15,N16,P
11,P12,P13,P14,P1
5,P17,P2,P25,R10,
R12,R13,R14,R15,
R16,R3,T11,T13,T1
5,T17,U10,U12,U14
,U16,V2,Y1
VDD12 ground and VDDPLL ground
(VSSPLL)
24
24
—
VDDE_B
3.3 V I/O supply. This supply is shared with 6, 19, 37, 48, 65, 89, 6, 19, 37, 48, 56, 63, AD13,AD19,AD2,A
internal flash, 16 MHz IRC oscillator and
4–16MHz crystal oscillator.
112, 122, 132, 140, 77, 105, 138, 146, D7,AE10,AE16,AE4
166
156, 164, 184, 198 ,B17,B21,B24,C19,
E25,H24,L25,N24,
W3
2
VDDA
3.3 V/5 V reference voltage and analog
supply for A/D converter. This supply is
shared with the SXOSC.
79
95
96
AC22
AD22
VSSA
Reference ground and analog ground for A/D
converter
80
VDDR
VSSR
Voltage regulator VREG supply
Voltage regulator ground
20
21
77
20
21
93
AA4
—
2
VDDE_A
3.3 V/5 V I/O supply. This supply is shared
with the SXOSC.
AD23
VSSE_A
VDDM
3.3 V/5 V I/O supply ground
78
94
AC23
Stepper motor 3.3 V/5 V pad supply. SSD
shares this supply.
94, 104
110, 120, 130
U25,W24,AA25
VSSM
VDDPLL
Stepper motor ground
95, 105
25
111, 121, 131
U24,W24,AA24
1.2 V PLL supply
25
22
—
AB4
AC1
3
VSUP_TEST
VDD_DR
9 V - 12 V flash test analog write signal
1.8V, 2.5V, and 3.3V DDR SDRAM supply
22
—
C2,C5,C8,C11,C14,
E3,H3,L3,N3,T3
VDD33_DR
Functional supply for SDRAM pads (where
available must be >= VDD_DR)
—
—
D6, D12, F4, R4
PXD20 Microcontroller Data Sheet, Rev. 2
28
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Pinout and signal descriptions
1
2
3
Decoupling capacitors must be connected between these pins and the nearest VSS pin.
VDDA must be at the same voltage as VDDE_A.
This signal needs to be connected to ground during normal operation.
2.4.3
Pad types
The pads available for system pins and functional port pins are described in:
•
•
•
The port pin summary in Table 1;
The pad type descriptions in Table 3-6;
Section 43.5.3.8, “Pad Configuration Registers (PCR0–PCR184) and Section 43.5.3.9, “Pad Configuration Registers
(PCR185–PCR281);
•
The device data sheet.
2.4.4
System pins
The system pins are listed in Table 4.
Table 4. System pin descriptions
Pin number
176 LQFP 208 LQFP
I/O
Pad
RESET
System pin
Function
direction type configuration1
416 TEPBGA
RESET
Bidirectional reset with
Schmitt-Trigger
characteristics and noise
filter.
I/O
I
M
X
X
Input, weak pull
up
30
27
28
30
27
28
W1
EXTAL
XTAL
Analog input to the oscillator
amplifier circuit. Input for the
clock generator in bypass
mode.
—
—
AB1
AA1
Analog output of the
oscillator amplifier circuit.
Needs to be grounded if
oscillator bypass mode is
used.
O
EXTAL32 Analog input of the 32KHz
oscillator amplifier circuit.
O
I
S
S
—
—
70
69
86
85
AF24
AF23
XTAL32
Analog output of the 32 KHz
oscillator amplifier circuit.
Input for the clock generator
in bypass mode.
NMI
Non-Maskable Interrupt
I/O
S
Input, none
—
45
29
53
29
AC7
AA3
VRC_CTRL Voltage Regulator external
Analo
g
NPN Ballast base control
pin
VREF_
RSDS2
RSDS interface reference
voltage
Analo
g
—
—
—
145, 165
26
J24,D24
AA2
VREG_
Pin used for factory testing
I
—
26
BYPASS3
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
29
Pinout and signal descriptions
1
Reset configuration is given as I/O direction and pull direction (for example, “Input, pullup”).
2
Although this signal is not a supply for RSDS pads, it needs to be terminated in an external capacitor with a value of 47 pF.
3
VREG_BYPASS should be pulled down externally.
2.4.5
Nexus pins
On the 176 LQFP and the 208 LQFP package options a reduced set of Nexus pins are optionally available, multiplexed with
GPIO pins.
On the 416 TEPBGA package option all Nexus pins are dedicated to Nexus only.
Table 5. Nexus pins
Pin number1
Pad
type
System pin
Function
PCR
176 LQFP
208 LQFP
416 TEPBGA
EVTI
Nexus Event In
M
M
F
PCR[80]
PCR[70]
PCR[85]
PCR[71]
PCR[73]
PCR[81]
PCR[82]
PCR[83]
PCR[84]
PCR[197]
PCR[198]
PCR[200]
PCR[199]
PCR[201]
PCR[185]
PCR[186]
PCR[187]
PCR[188]
PCR[189]
PCR[190]
PCR[191]
PCR[192]
169
157
174
158
159
170
171
172
173
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
201
189
206
190
191
202
203
204
205
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
A17
C20
EVTO
Nexus Event Out
MCKO
Nexus Msg Clock Out
Nexus Msg Start/End Out
Nexus Msg Start/End Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Event In
B18
MSEO[0]
MSEO[2]
MDO[0]
MDO[1]
MDO[2]
MDO[3]
EVTI
M
M
M
M
M
M
M
M
F
B20
A20
D16
C16
B16
A16
AD8
AE8
EVTO
Nexus Event Out
MCKO
Nexus Msg Clock Out
Nexus Msg Start/End Out
Nexus Msg Start/End Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
AC17
AD9
AD17
AC20
AD20
AE20
AF20
AE17
AF17
AC18
AD18
MSEO[0]
MSEO[2]
MDO[0]
MDO[1]
MDO[2]
MDO[3]
MDO[4]
MDO[5]
MDO[6]
MDO[7]
M
M
M
M
M
M
M
M
M
M
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
30
Freescale Semiconductor
Pinout and signal descriptions
Pin number1
Table 5. Nexus pins (continued)
Pad
type
System pin
Function
PCR
176 LQFP
208 LQFP
416 TEPBGA
MDO[8]
MDO[9]
MDO[10]
MDO[11]
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
Nexus Msg Data Out
M
M
M
M
PCR[193]
PCR[194]
PCR[195]
PCR[196]
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
AE18
AF18
AC19
AF19
1
On the 176 LQFP and 208 LQFP package options the Nexus pins are multiplexed with other GPIO. On the 416 TEPBGA
package, there are additional dedicated Nexus pins.
2.4.6
DRAM interface
The DRAM interface pins are listed in Table 6.
Table 6. DRAM interface pin summary
Pin number
I/O
direction
Pad
type
RESET
config2
Port pin1
Function
PCR
416 TEPBGA
DRAM Data Bus
DDR_DQ[31]
DDR_DQ[30]
DDR_DQ[29]
DDR_DQ[28]
DDR_DQ[27]
DDR_DQ[26]
DDR_DQ[25]
DDR_DQ[24]
DDR_DQ[23]
DDR_DQ[22]
DDR_DQ[21]
DDR_DQ[20]
DDR_DQ[19]
DDR_DQ[18]
DDR_DQ[17]
DDR_DQ[16]
DDR_DQ[15]
DDR_DQ[14]
DDR_DQ[13]
DDR_DQ[12]
DRAM Data Bus [31]
DRAM Data Bus [30]
DRAM Data Bus [29]
DRAM Data Bus [28]
DRAM Data Bus [27]
DRAM Data Bus [26]
DRAM Data Bus [25]
DRAM Data Bus [24]
DRAM Data Bus [23]
DRAM Data Bus [22]
DRAM Data Bus [21]
DRAM Data Bus [20]
DRAM Data Bus [19]
DRAM Data Bus [18]
DRAM Data Bus [17]
DRAM Data Bus [16]
DRAM Data Bus [15]
DRAM Data Bus [14]
DRAM Data Bus [13]
DRAM Data Bus [12]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
PCR[237] None, None
PCR[238] None, None
PCR[239] None, None
PCR[240] None, None
PCR[241] None, None
PCR[242] None, None
PCR[243] None, None
PCR[244] None, None
PCR[245] None, None
PCR[246] None, None
PCR[247] None, None
PCR[248] None, None
PCR[249] None, None
PCR[250] None, None
PCR[251] None, None
PCR[252] None, None
PCR[253] None, None
PCR[254] None, None
PCR[255] None, None
PCR[256] None, None
A6
A5
A4
A3
A2
A1
B1
C4
C1
D4
D3
D2
D1
E4
E1
F1
G1
G4
H1
H4
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
31
Pinout and signal descriptions
Table 6. DRAM interface pin summary (continued)
Pin number
I/O
direction
Pad
type
RESET
config2
Port pin1
Function
PCR
416 TEPBGA
DDR_DQ[11]
DDR_DQ[10]
DDR_DQ[9]
DDR_DQ[8]
DDR_DQ[7]
DDR_DQ[6]
DDR_DQ[5]
DDR_DQ[4]
DDR_DQ[3]
DDR_DQ[2]
DDR_DQ[1]
DDR_DQ[0]
DRAM Data Bus [11]
DRAM Data Bus [10]
DRAM Data Bus [9]
DRAM Data Bus [8]
DRAM Data Bus [7]
DRAM Data Bus [6]
DRAM Data Bus [5]
DRAM Data Bus [4]
DRAM Data Bus [3]
DRAM Data Bus [2]
DRAM Data Bus [1]
DRAM Data Bus [0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
PCR[257] None, None
PCR[258] None, None
PCR[259] None, None
PCR[260] None, None
PCR[261] None, None
PCR[262] None, None
PCR[263] None, None
PCR[264] None, None
PCR[265] None, None
PCR[266] None, None
PCR[267] None, None
PCR[268] None, None
J1
K4
K1
L1
L4
M4
M1
N4
N1
P4
P1
R1
DRAM Data Strobes
DDR_DQS[3]
DDR_DQS[2]
DDR_DQS[1]
DDR_DQS[0]
DRAM Data Strobe [3]
I/O
I/O
I/O
I/O
DDR
DDR
DDR
DDR
PCR[232] None, None
PCR[231] None, None
PCR[230] None, None
PCR[229] None, None
B3
G2
K2
N2
DRAM Data Strobe [2]
DRAM Data Strobe [1]
DRAM Data Strobe [0]
DRAM Data Enables
DDR_DM[3]
DDR_DM[2]
DDR_DM[1]
DDR_DM[0]
DRAM Data Enable [3]
Output
Output
Output
Output
DDR
DDR
DDR
DDR
PCR[236]
PCR[235]
PCR[234]
PCR[233]
Output,
None
B4
G3
K3
P3
DRAM Data Enable [2]
DRAM Data Enable [1]
DRAM Data Enable [0]
Output,
None
Output,
None
Output,
None
DRAM Address
DDR_A[15]
DRAM address [15]
DRAM address [14]
DRAM address [13]
DRAM address [12]
DRAM address [11]
Output
Output
Output
Output
Output
DDR
DDR
DDR
DDR
DDR
PCR[217]
PCR[216]
PCR[215]
PCR[214]
PCR[213]
Output,
None
B15
D15
D14
A14
D13
DDR_A[14]
DDR_A[13]
DDR_A[12]
DDR_A[11]
Output,
None
Output,
None
Output,
None
Output,
None
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
32
Freescale Semiconductor
Pinout and signal descriptions
Table 6. DRAM interface pin summary (continued)
Pin number
RESET
I/O
direction
Pad
type
Port pin1
Function
PCR
config2
416 TEPBGA
DDR_A[10]
DDR_A[9]
DDR_A[8]
DDR_A[7]
DDR_A[6]
DDR_A[5]
DDR_A[4]
DDR_A[3]
DDR_A[2]
DDR_A[1]
DDR_A[0]
DRAM address [10]
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
PCR[212]
PCR[211]
PCR[210]
PCR[209]
PCR[208]
PCR[207]
PCR[206]
PCR[205]
PCR[204]
PCR[203]
PCR[202]
Output,
None
C13
B13
A13
B12
A12
D11
A11
D10
C10
B10
A10
DRAM address [9]
DRAM address [8]
DRAM address [7]
DRAM address [6]
DRAM address [5]
DRAM address [4]
DRAM address [3]
DRAM address [2]
DRAM address [1]
DRAM address [0]
Output,
None
Output,
None
Output,
None
Output,
None
Output,
None
Output,
None
Output,
None
Output,
None
Output,
None
Output,
None
DRAM Bank Address
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
DRAM Bank Address[2]
Output
Output
Output
DDR
DDR
DDR
PCR[220]
PCR[219]
PCR[218]
Output,
None
A9
A8
A7
DRAM Bank Address[1]
DRAM Bank Address[0]
Output,
None
Output,
None
DRAM Control
DDR_CAS
Column Address Strobe
Row Address Strobe
Write Enable
Output
Output
Output
Output
Output
DDR
DDR
DDR
DDR
DDR
PCR[221]
PCR[227]
PCR[228]
PCR[226]
PCR[225]
Output,
None
B6
B7
B9
D5
C7
DDR_RAS
DDR_WEB
DDR_ODT
DDR_CLK
Output,
None
Output,
None
DRAM On-die termination
DRAM Clock
Output,
Pull Down
Output,
None
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
33
Pinout and signal descriptions
Table 6. DRAM interface pin summary (continued)
Pin number
I/O
direction
Pad
type
RESET
config2
Port pin1
Function
PCR
416 TEPBGA
DDR_CLKB
DDR_CK
DDR_CS
DRAM Clock bar
Output
Output
Output
DDR
DDR
DDR
NA
Output,
None
D7
DRAM Clock Enable
DRAM Chip Select
PCR[222]
PCR[223]
Output,
Pull Down
D8
D9
Output,
None
MVREF
MVTT
DDR Reference Voltage
Input
Input
—
—
NA
NA
—
—
J4
DRAM Termination Voltage
F2,J2,M2,R2
1
2
These port pins are disabled and unpowered on packages where the DRAM interface is not bonded out.
Reset configuration is given as I/O direction and pull direction (for example, “Input, pullup”).
2.4.7
VIU muxing
The DCU3, DCULite and VIU2 modules share the same pins for input video. It is, however, possibile to feed independent video
streams to VIU2 and DCU3 (operating in narrow mode). Figure 5 explains the pin sharing arrangement.
DE
PDI_PCLK
Direct feed of PDI interface
to DCU3 or DCULite
VSYNC
HSYNC
DATA[17:0]
VIU_PCLK
VIU[9:0]
VIU2
DCU3
PDI
DCULite
PDI
RGB565
RGB888
8-bit mono
YUV422
XBAR
Figure 5. VIU2, DCU3, and DCULite pin sharing
VIU input data selection is done based on select bit (bit 0) of Miscellaneous control register (0xC3FE0340).
•
•
•
VIU pix data: VIU[9:0]
Select bit 1’b0: PDI[7:0],HSYNC,VSYNC
Select bit 1’b1: PDI[17:8]
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
34
Freescale Semiconductor
Pinout and signal descriptions
2.4.8
SGM muxing
The SGM shares pins between the PWM output signals and the I2S bus signals as shown in the “Port pin summary” table. When
the PWM function is enabled in the SGM (SGMCTL[PWME]) the PWM (PWMO, PWMOA) signals are available. When the
PWM function is disabled the I2S bus signals (I2S_DO, I2S_SCK) are available.
2.4.9
RSDS special function muxing
Ports PA[0:15], PG[0:7], PG[11] and PM[2] have the RSDS signalling option as a special function. The SIUL allocates pad
control registers to these functions (PCR[270:282]), but because these pads share a common pin with the normal GPIO pins
they do not operate in the same way as the normal GPIO ports. PG[11] in particular has a special configuration separate from
the other pads.
The special-function pads are output-only, and the associated PCR[OBE] bit is controlled by the TCON_CTRL1 register
(TCON_BYPASS and RSDS_MODE bits). However, the alternate function selection is taken from the associated normal GPIO
pad. This allows selection of the DCU3 function as the alternate function of the pad and then the TCON module to select if the
output style is TCON/RSDS or digital RGB format.
Therefore, when the TCON bypass is active (bypass disabled with or without RSDS active), it is important not to configure the
normal GPIO ports for output operation with a non-DCU3 alternate function on ports PA[0:15] and PG[0:7].
For PG[11], the PCR[282] OBE bit is fully controlled by the TCON module and will become an output whenever the DCU3
alternate option is selected. Therefore, only select the DCU3 function on this pin when ready to configure it as a clock for a TFT
panel.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
35
2.4.10 Functional ports
The functional port pins are listed in Table 7. The following pad types are available for system pins and functional port pins:
•
•
•
•
•
•
•
•
S — Slow (pad_ssr, pad_ssr_hv)
M — Medium (pad_msr, pad_msr_hv)
F — Fast (pad_fc)
J — Input/output with analog features (pad_tgate, pad_tgate_hv)
Analog — Input only with analog features (pad_ae, pad_ae_hv)
SMD — Stepper Motor Detector
DDR — DDR pads
RSDS — RSDS pads
Table 7. Port pin summary
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PORT A
PA[0]
PCR[0]
Option 0 GPIO[0]
Option 1 DCU_R0
Option 2 SDA_1
RSDS0P
SIUL
I/O
I/O
I/O
I/O
I/O
M /
None,
116
117
118
119
120
139
140
141
142
143
K26
K25
K23
J23
J26
DCU3
RSDS none
I2C_1
Option 3 eMIOS0[18]
PWM/Timer
PA[1]
PA[2]
PA[3]
PA[4]
PCR[1]
PCR[2]
PCR[3]
PCR[4]
Option 0 GPIO[1]
Option 1 DCU_R1
Option 2 SCL_1
RSDS0M
RSDS1P
RSDS1M
RSDS2P
SIUL
M /
None,
DCU3
RSDS none
I2C_1
Option 3 eMIOS0[17]
PWM/Timer
Option 0 GPIO[2]
Option 1 DCU_R2
SIUL
DCU3
—
M /
None,
RSDS none
Option 2
Option 3
—
—
—
Option 0 GPIO[3]
Option 1 DCU_R3
SIUL
DCU3
—
M /
None,
RSDS none
Option 2
Option 3
—
—
—
Option 0 GPIO[4]
Option 1 DCU_R4
SIUL
DCU3
—
M /
None,
RSDS none
Option 2
Option 3
—
—
—
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PA[5]
PA[6]
PA[7]
PA[8]
PA[9]
PCR[5]
Option 0 GPIO[5]
Option 1 DCU_R5
RSDS2M
RSDS3P
RSDS3M
RSDS4P
RSDS4M
RSDS5P
RSDS5M
RSDS6P
RSDS6M
SIUL
DCU3
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M /
None,
121
124
125
126
127
128
129
130
131
144
148
149
150
151
152
153
154
155
J25
H26
G26
G25
G24
H23
G23
F26
F25
RSDS none
Option 2
Option 3
—
—
—
PCR[6]
PCR[7]
PCR[8]
PCR[9]
Option 0 GPIO[6]
Option 1 DCU_R6
SIUL
DCU3
—
M /
None,
RSDS none
Option 2
Option 3
—
—
—
Option 0 GPIO[7]
Option 1 DCU_R7
SIUL
DCU3
—
M /
None,
RSDS none
Option 2
Option 3
—
—
—
Option 0 GPIO[8]
Option 1 DCU_G0
Option 2 SCL_2
SIUL
M /
None,
DCU3
RSDS none
I2C_2
Option 3 eMIOS0[20]
PWM/Timer
Option 0 GPIO[9]
Option 1 DCU_G1
Option 2 SDA_2
SIUL
M /
None,
DCU3
RSDS none
I2C_2
Option 3 eMIOS0[19]
PWM/Timer
PA[10] PCR[10] Option 0 GPIO[10]
Option 1 DCU_G2
SIUL
DCU3
—
M /
None,
RSDS none
Option 2
Option 3
—
—
—
PA[11] PCR[11] Option 0 GPIO[11]
Option 1 DCU_G3
SIUL
DCU3
—
M /
None,
RSDS none
Option 2
Option 3
—
—
—
PA[12] PCR[12] Option 0 GPIO[12]
Option 1 DCU_G4
SIUL
DCU3
—
M /
None,
RSDS none
Option 2
Option 3
—
—
—
PA[13] PCR[13] Option 0 GPIO[13]
Option 1 DCU_G5
SIUL
DCU3
—
M /
None,
RSDS none
Option 2
Option 3
—
—
—
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PA[14] PCR[14] Option 0 GPIO[14]
Option 1 DCU_G6
RSDS7P
SIUL
DCU3
—
I/O
I/O
M /
None,
134
158
F24
RSDS none
Option 2
Option 3
—
—
—
PA[15] PCR[15] Option 0 GPIO[15]
Option 1 DCU_G7
RSDS7M
SIUL
DCU3
—
M /
None,
135
159
F23
RSDS none
Option 2
Option 3
—
—
—
PORT B
PB[0] PCR[16] Option 0 GPIO[16]
Option 1 CANTX_0
—
—
—
—
—
—
SIUL
I/O
I/O
I/O
I/O
I/O
I/O
S
S
S
S
S
S
None,
none
13
12
13
12
W4
V1
FlexCAN_0
LINFlex_0
—
Option 2 TXD_0
Option 3
—
PB[1] PCR[17] Option 0 GPIO[17]
Option 1 CANRX_0
SIUL
None,
none
FlexCAN_0
LINFlex_0
—
Option 2 RXD_0
Option 3
—
PB[2] PCR[18] Option 0 GPIO[18]
Option 1 TXD_0
SIUL
LINFlex_0
—
—
None,
none
153
152
62
183
182
74
D21
A22
AF15
AC16
Option 2
Option 3
—
—
PB[3] PCR[19] Option 0 GPIO[19]
Option 1 RXD_0
SIUL
LINFlex_0
—
—
None,
none
Option 2
Option 3
—
—
PB[4] PCR[20] Option 0 GPIO[20]
Option 1 SCK_1
SIUL
DSPI_1
ADC
—
None,
none
Option 2 MA0
Option 3
—
PB[5] PCR[21] Option 0 GPIO[21]
Option 1 SOUT_1
SIUL
DSPI_1
ADC
Input,
pull-
down
63
75
Option 2 MA1
Option 3 FABM
Control
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PB[6] PCR[22] Option 0 GPIO[22]
Option 1 SIN_1
—
—
—
—
—
—
—
—
SIUL
DSPI_1
ADC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
S
S
M
S
S
S
S
Input,
pull-
up
64
55
54
53
14
15
46
47
76
67
66
65
14
15
54
55
AF16
AC14
AF13
AC13
W2
Option 2 MA2
Option 3 ABS[0]
Control
PB[7] PCR[23] Option 0 GPIO[23]
Option 1 SIN_0
SIUL
None,
none
DSPI_0
PWM/Timer
SGM
Option 2 eMIOS1[20]
Option 3 I2S_SCK/PWMOA
PB[8] PCR[24] Option 0 GPIO[24]
Option 1 SOUT_0
SIUL
None,
none
DSPI_0
PWM/Timer
SGM
Option 2 eMIOS1[19]
Option 3 I2S_DO/PWMO
PB[9] PCR[25] Option 0 GPIO[25]
Option 1 SCK_0
SIUL
None,
none
DSPI_0
PWM/Timer
SGM
Option 2 eMIOS1[18]
Option 3 I2S_FS
PB[10] PCR[26] Option 0 GPIO[26]
Option 1 CANRX_1
SIUL
FlexCAN_1
SGM
None,
none
Option 2 I2S_DO/PWMO
Option 3
—
—
PB[11] PCR[27] Option 0 GPIO[27]
Option 1 CANTX_1
SIUL
FlexCAN_1
SGM
None,
none
Y4
Option 2 SGM_MCLK
Option 3
—
—
PB[12] PCR[28] Option 0 GPIO[28]
Option 1 RXD_1
SIUL
None,
none
AF7
LINFlex_1
PWM/Timer
DSPI_0
Option 2 eMIOS1[10]
Option 3 CS2_0
PB[13] PCR[29] Option 0 GPIO[29]
Option 1 TXD_1
SIUL
None,
none
AC8
LINFlex_1
PWM/Timer
DSPI_0
Option 2 eMIOS1[11]
Option 3 CS1_0
PB[14]
PB[15]
—
—
—
—
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PORT C
PC[0] PCR[30] Option 0 GPIO[30]
ANS[0]
ANS[1]
ANS[2]
ANS[3]
ANS[4]
ANS[5]
ANS[6]
ANS[7]
ANS[8]
SIUL
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J
J
J
J
J
J
J
J
J
None,
none
88
87
86
85
84
83
82
81
76
104
103
102
101
100
99
AC21
AC25
AC26
AC24
AD24
AD26
AD21
AD25
AE26
Option 1
Option 2
Option 3
—
—
—
—
PC[1] PCR[31] Option 0 GPIO[31]
SIUL
—
—
None,
none
Option 1
Option 2
Option 3
—
—
—
—
PC[2] PCR[32] Option 0 GPIO[32]
SIUL
—
—
None,
none
Option 1
Option 2
Option 3
—
—
—
—
PC[3] PCR[33] Option 0 GPIO[33]
SIUL
—
—
None,
none
Option 1
Option 2
Option 3
—
—
—
—
PC[4] PCR[34] Option 0 GPIO[34]
SIUL
—
—
None,
none
Option 1
Option 2
Option 3
—
—
—
—
PC[5] PCR[35] Option 0 GPIO[35]
SIUL
—
—
None,
none
Option 1
Option 2
Option 3
—
—
—
—
PC[6] PCR[36] Option 0 GPIO[36]
SIUL
—
—
None,
none
98
Option 1
Option 2
Option 3
—
—
—
—
PC[7] PCR[37] Option 0 GPIO[37]
SIUL
—
—
None,
none
97
Option 1
Option 2
Option 3
—
—
—
—
PC[8] PCR[38] Option 0 GPIO[38]
SIUL
—
—
None,
none
92
Option 1
Option 2
Option 3
—
—
—
—
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PC[9] PCR[39] Option 0 GPIO[39]
ANS[9]
ANS[10]
ANS[11]
ANS[12]
ANS[13]
SIUL
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J
J
J
J
J
J
J
None,
none
75
74
73
72
71
70
69
91
90
89
88
87
86
85
AE25
AE23
AE24
AF26
AF25
AF24
AF23
Option 1
Option 2
Option 3
—
—
—
—
PC[10] PCR[40] Option 0 GPIO[40]
Option 1
Option 2 I2S_DO/PWMO
Option 3
SIUL
—
SGM
—
None,
none
—
—
PC[11] PCR[41] Option 0 GPIO[41]
Option 1
SIUL
—
ADC
DSPI_1
None,
None
—
Option 2 MA0
Option 3 CS2_1
PC[12] PCR[42] Option 0 GPIO[42]
SIUL
—
ADC
DSPI_1
None,
None
Option 1
—
Option 2 MA1
Option 3 CS1_1
PC[13] PCR[43] Option 0 GPIO[43]
SIUL
—
ADC
DSPI_1
None,
None
Option 1
—
Option 2 MA2
Option 3 CS0_1
PC[14] PCR[44] Option 0 GPIO[44]
ANS[14]
EXTAL32
SIUL
—
—
None,
None
Option 1
Option 2
Option 3
—
—
—
—
PC[15] PCR[45] Option 0 GPIO[45]
ANS[15]
XTAL32
SIUL
—
—
None,
None
Option 1
Option 2
Option 3
—
—
—
—
PORT D
PD[0] PCR[46] Option 0 GPIO[46]
Option 1 M0C0M
—
—
SIUL
SMD
SSD
PWM/Timer
I/O
I/O
SMD
SMD
None,
None
90
91
106
107
AB26
AB25
Option 2 SSD0_0
Option 3 eMIOS1[8]
PD[1] PCR[47] Option 0 GPIO[47]
Option 1 M0C0P
SIUL
SMD
None,
None
Option 2 SSD0_1
SSD
Option 3 eMIOS1[16]
PWM/Timer
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PD[2] PCR[48] Option 0 GPIO[48]
Option 1 M0C1M
—
—
—
—
—
—
—
—
—
SIUL
SMD
SSD
PWM/Timer
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SMD
SMD
SMD
SMD
SMD
SMD
SMD
SMD
SMD
None,
None
92
108
109
112
113
114
115
116
117
118
AB24
AB23
AA26
AA23
Y26
Option 2 SSD0_2
Option 3 eMIOS1[23]
PD[3] PCR[49] Option 0 GPIO[49]
Option 1 M0C1P
SIUL
SMD
SSD
PWM/Timer
None,
None
93
Option 2 SSD0_3
Option 3 eMIOS0[9]
PD[4] PCR[50] Option 0 GPIO[50]
Option 1 M1C0M
SIUL
SMD
SSD
PWM/Timer
None,
None
96
Option 2 SSD1_0
Option 3 eMIOS0[8]
PD[5] PCR[51] Option 0 GPIO[51]
Option 1 M1C0P
SIUL
SMD
SSD
PWM/Timer
None,
None
97
Option 2 SSD1_1
Option 3 eMIOS0[16]
PD[6] PCR[52] Option 0 GPIO[52]
Option 1 M1C1M
SIUL
SMD
SSD
PWM/Timer
None,
None
98
Option 2 SSD1_2
Option 3 eMIOS0[23]
PD[7] PCR[53] Option 0 GPIO[53]
Option 1 M1C1P
SIUL
SMD
SSD
—
None,
None
99
Y25
Option 2 SSD1_3
Option 3
—
PD[8] PCR[54] Option 0 GPIO[54]
Option 1 M2C0M
SIUL
SMD
SSD
—
None,
None
100
101
102
Y24
Option 2 SSD2_0
Option 3
—
PD[9] PCR[55] Option 0 GPIO[55]
Option 1 M2C0P
SIUL
SMD
SSD
PWM/Timer
None,
None
Y23
Option 2 SSD2_1
Option 3 eMIOS0[9]
PD[10] PCR[56] Option 0 GPIO[56]
Option 1 M2C1M
SIUL
SMD
None,
None
W26
Option 2 SSD2_2
SSD
Option 3 eMIOS0[10]
PWM/Timer
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PD[11] PCR[57] Option 0 GPIO[57]
Option 1 M2C1P
—
—
—
—
—
SIUL
SMD
SSD
PWM/Timer
I/O
I/O
I/O
I/O
I/O
SMD
SMD
SMD
SMD
SMD
None,
None
103
106
107
108
109
119
122
123
124
125
W23
V26
V25
V24
V23
Option 2 SSD2_3
Option 3 eMIOS0[11]
PD[12] PCR[58] Option 0 GPIO[58]
Option 1 M3C0M
SIUL
SMD
SSD
PWM/Timer
None,
None
Option 2 SSD3_0
Option 3 eMIOS0[12]
PD[13] PCR[59] Option 0 GPIO[59]
Option 1 M3C0P
SIUL
SMD
SSD
PWM/Timer
None,
None
Option 2 SSD3_1
Option 3 eMIOS0[13]
PD[14] PCR[60] Option 0 GPIO[60]
Option 1 M3C1M
SIUL
SMD
SSD
PWM/Timer
None,
None
Option 2 SSD3_2
Option 3 eMIOS0[14]
PD[15] PCR[61] Option 0 GPIO[61]
Option 1 M3C1P
SIUL
SMD
None,
None
Option 2 SSD3_3
SSD
Option 3 eMIOS0[15]
PWM/Timer
PORT E
PE[0] PCR[62] Option 0 GPIO[62]
Option 1 M4C0M
—
—
—
SIUL
SMD
SSD
—
I/O
I/O
I/O
SMD
SMD
SMD
None,
None
—
—
—
126
127
128
U26
U23
T26
Option 2 SSD4_0
Option 3
—
PE[1] PCR[63] Option 0 GPIO[63]
Option 1 M4C0P
SIUL
SMD
SSD
—
None,
None
Option 2 SSD4_1
Option 3
—
PE[2] PCR[64] Option 0 GPIO[64]
Option 1 M4C1M
SIUL
SMD
SSD
—
None,
None
Option 2 SSD4_2
Option 3
—
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PE[3] PCR[65] Option 0 GPIO[65]
Option 1 M4C1P
—
—
—
—
—
SIUL
SMD
SSD
—
I/O
I/O
I/O
I/O
I/O
SMD
SMD
SMD
SMD
SMD
None,
None
—
—
—
—
—
129
132
133
134
135
T25
T24
T23
R24
R23
Option 2 SSD4_3
Option 3
—
PE[4] PCR[66] Option 0 GPIO[66]
Option 1 M5C0M
SIUL
SMD
SSD
—
None,
None
Option 2 SSD5_0
Option 3
—
PE[5] PCR[67] Option 0 GPIO[67]
Option 1 M5C0P
SIUL
SMD
SSD
—
None,
None
Option 2 SSD5_1
Option 3
—
PE[6] PCR[68] Option 0 GPIO[68]
Option 1 M5C1M
SIUL
SMD
SSD
—
None,
None
Option 2 SSD5_2
Option 3
—
PE[7] PCR[69] Option 0 GPIO[69]
Option 1 M5C1P
SIUL
SMD
SSD
—
None,
None
Option 2 SSD5_3
Option 3
—
PORT F
PF[0]
PCR[70] Option 0 GPIO[70]
Option 1 eMIOS1[19]
Option 2 EVTO
—
—
—
SIUL
I/O
I/O
I/O
M
M
S
None,
None
157
158
45
189
190
53
C20
B20
AC7
PWM/Timer
NEXUS
DCULite
Option 3 DCULITE_B2
PF[1]
PF[2]
PCR[71] Option 0 GPIO[71]
Option 1 eMIOS1[20]
Option 2 MSEO
SIUL
None,
None
PWM/Timer
NEXUS
DCULite
Option 3 DCULITE_B3
PCR[72] Option 0 GPIO[72]
Option 1 NMI
SIUL
NMI
—
None,
None
Option 2
Option 3
—
—
—
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PF[8]
PF[9]
PCR[73] Option 0 GPIO[73]
Option 1 eMIOS1[21]
Option 2 MSEO
—
—
—
—
—
—
—
—
—
SIUL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
S
None,
None
159
160
161
162
163
164
165
169
170
191
192
193
194
195
196
197
201
202
A20
D19
A19
D18
C18
A18
D17
A17
D16
PWM/Timer
NEXUS
DCULite
Option 3 DCULITE_B4
PCR[74] Option 0 GPIO[74]
Option 1 eMIOS1[14]
Option 2 SDA_1
SIUL
None,
None
PWM/Timer
I2C_1
Option 3 DCULITE_B5
DCULite
PCR[75] Option 0 GPIO[75]
Option 1 QUADSPI_IO1_B
Option 2 eMIOS1[15]
SIUL
None,
None
QuadSPI
PWM/Timer
VIU2/PDI
Option 3 VIU8_PDI16
PCR[76] Option 0 GPIO[76]
Option 1 QUADSPI_IO0_B
Option 2 eMIOS1[16]
SIUL
None,
None
QuadSPI
PWM/Timer
VIU2/PDI
Option 3 VIU9_PDI17
PCR[77] Option 0 GPIO[77]
Option 1 eMIOS1[15]
Option 2 SCL_1
SIUL
None,
None
PWM/Timer
I2C_1
Option 3 DCULITE_B6
DCULite
PCR[78] Option 0 GPIO[78]
Option 1 SDA_0
SIUL
None,
None
I2C_0
Option 2 CS2_1
Option 3 RXD_1
DSPI_1
LINFlex_1
PCR[79] Option 0 GPIO[79]
Option 1 SCL_0
SIUL
S
None,
None
I2C_0
Option 2 CS1_1
Option 3 TXD_1
DSPI_1
LINFlex_1
PF[10] PCR[80] Option 0 GPIO[80]
Option 1 QUADSPI_PCS_A
Option 2
SIUL
QuadSPI
—
M
M
None,
None
—
Option 3 EVTI
NEXUS
PF[11] PCR[81] Option 0 GPIO[81]
SIUL
QuadSPI
—
None,
None
Option 1 QUADSPI_IO2_A
Option 2
Option 3 MDO0
—
NEXUS
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PF[12] PCR[82] Option 0 GPIO[82]
Option 1 QUADSPI_IO3_A
Option 2
—
—
—
—
SIUL
QuadSPI
—
I/O
I/O
I/O
I/O
M
M
M
F
None,
None
171
172
173
174
203
204
205
206
C16
B16
A16
B18
—
Option 3 MDO1
NEXUS
PF[13] PCR[83] Option 0 GPIO[83]
SIUL
QuadSPI
—
None,
None
Option 1 QUADSPI_IO0_A
Option 2
—
Option 3 MDO2
NEXUS
PF[14] PCR[84] Option 0 GPIO[84]
SIUL
QuadSPI
—
None,
None
Option 1 QUADSPI_IO1_A
Option 2
—
Option 3 MDO3
NEXUS
PF[15] PCR[85] Option 0 GPIO[85]
SIUL
None,
None
Option 1 QUADSPI_CLK_A
Option 2 CLKOUT
Option 3 MCKO
QuadSPI
Control
NEXUS
PORT G
PG[0] PCR[86] Option 0 GPIO[86]
Option 1 DCU_B0
RSDS8P SIUL
DCU3
I/O
I/O
I/O
I/O
M
M
M
M
None,
None
136
137
141
142
160
161
166
167
E26
D26
D25
C25
Option 2 SCL_3
Option 3 eMIOS0[21]
I2C_3
PWM/Timer
PG[1] PCR[87] Option 0 GPIO[87]
Option 1 DCU_B1
RSDS8M SIUL
DCU3
None,
None
Option 2 SDA_3
Option 3 eMIOS0[22]
I2C_3
PWM/Timer
PG[2] PCR[88] Option 0 GPIO[88]
Option 1 DCU_B2
RSDS9P SIUL
None,
None
DCU3
—
—
Option 2
Option 3
—
—
PG[3] PCR[89] Option 0 GPIO[89]
Option 1 DCU_B3
RSDS9M SIUL
None,
None
DCU3
—
—
Option 2
Option 3
—
—
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PG[4] PCR[90] Option 0 GPIO[90]
Option 1 DCU_B4
RSDS10P SIUL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
F
None,
None
143
144
145
146
1
168
169
170
171
1
C26
B26
A26
A25
T4
DCU3
—
—
Option 2
Option 3
—
—
PG[5] PCR[91] Option 0 GPIO[91]
Option 1 DCU_B5
RSDS10M SIUL
None,
None
DCU3
—
—
Option 2
Option 3
—
—
PG[6] PCR[92] Option 0 GPIO[92]
Option 1 DCU_B6
RSDS11P SIUL
None,
None
DCU3
—
—
Option 2
Option 3
—
—
PG[7] PCR[93] Option 0 GPIO[93]
Option 1 DCU_B7
RSDS11M SIUL
None,
None
DCU3
—
—
Option 2
Option 3
—
—
PG[8] PCR[94] Option 0 GPIO[94]
Option 1 DCU_VSYNC
—
—
—
SIUL
DCU3
—
None,
None
Option 2
Option 3
—
—
—
PG[9] PCR[95] Option 0 GPIO[95]
Option 1 DCU_HSYNC
SIUL
DCU3
—
None,
None
2
2
T2
Option 2
Option 3
—
—
—
PG[10] PCR[96] Option 0 GPIO[96]
Option 1 DCU_DE
SIUL
DCU3
—
None,
None
3
3
T1
Option 2
Option 3
—
—
—
PG[11] PCR[97] Option 0 GPIO[97]
Option 1 DCU_PCLK
RSDSCLKP SIUL
None,
None
147
168
172
200
E23
A15
DCU3
—
—
Option 2
Option 3
—
—
PG[12] PCR[98] Option 0 GPIO[98]
Option 1 CS0_1
—
SIUL
M
None,
None
DSPI_1
PDI
Option 2 PDI_DE
Option 3 DCULITE_B7
DCULite
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PG[13]
PG[14]
PG[15]
PORT H
—
—
—
—
—
—
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
Reserved
PH[0]6 PCR[99] Option 0 GPIO[99]
Option 1 TCK
—
—
—
—
—
—
SIUL
JTAG
—
I/O
I/O
I/O
I/O
I/O
I/O
S
S
Input,
Pull Up
41
42
43
44
61
38
49
50
51
52
73
—
AC6
AD6
AE6
AF6
AE15
—
Option 2
Option 3
—
—
—
PH[1]6 PCR[100] Option 0 GPIO[100]
Option 1 TDI
SIUL
JTAG
—
Input,
Pull Up
Option 2
Option 3
—
—
—
PH[2]6 PCR[101] Option 0 GPIO[101]
Option 1 TDO
SIUL
JTAG
—
M
S
Output,
None
Option 2
Option 3
—
—
—
PH[3]6 PCR[102] Option 0 GPIO[102]
Option 1 TMS
SIUL
JTAG
—
Input,
Pull Up
Option 2
Option 3
—
—
—
PH[4] PCR[103] Option 0 GPIO[103]
Option 1 CS0_0
SIUL
M
S
None,
None
DSPI_0
PWM/Timer
DCULite
Option 2 eMIOS1[21]
Option 3 DCULITE_G6
PH[5] PCR[104] Option 0 GPIO[104]
Option 1 VIU7_PDI15
SIUL
VIU2/PDI
SGM
None,
None
Option 2 I2S_FS
Option 3 eMIOS1[8]
PWM/Timer
PH[6]
PH[7]
PH[8]
PH[9]
PH[10]
—
—
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PH[11]
PH[12]
PH[13]
PH[14]
PH[15]
PORT J
PJ[0]
—
—
—
—
—
—
—
—
—
—
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
PCR[105] Option 0 GPIO[105]
Option 1 DCULITE_B6
—
—
—
—
—
—
—
SIUL
DCULite
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
S
S
S
S
M
S
None,
None
—
4
—
4
L26
U4
Option 2
Option 3 I2S_DO / PWMO
—
SGM
PJ[1]
PJ[2]
PJ[3]
PJ[4]
PJ[5]
PJ[6]
PCR[106] Option 0 GPIO[106]
Option 1 VIU1_PDI_HSYNC
Option 2 eMIOS1[9]
SIUL
None,
None
VIU2/PDI
PWM/Timer
PWM/Timer
Option 3 eMIOS0[8]
PCR[107] Option 0 GPIO[107]
Option 1 VIU0_PDI_VSYNC
Option 2 eMIOS1[14]
SIUL
None,
None
5
5
U3
VIU2/PDI
PWM/Timer
PWM/Timer
Option 3 eMIOS0[9]
PCR[108] Option 0 GPIO[108]
Option 1 VIU_PCLK
SIUL
VIU2
None,
None
60
56
57
58
72
68
69
70
AD15
AD14
AE14
AF14
Option 2 eMIOS0[22]
Option 3 PDI_DE
PWM/Timer
PDI
PCR[109] Option 0 GPIO[109]
Option 1 VIU2_PDI0
SIUL
None,
None
VIU2/PDI
PWM/Timer
PWM/Timer
Option 2 eMIOS0[21]
Option 3 eMIOS0[23]
PCR[110] Option 0 GPIO[110]
Option 1 VIU3_PDI1
SIUL
None,
None
VIU2/PDI
PWM/Timer
PWM/Timer
Option 2 eMIOS0[20]
Option 3 eMIOS0[16]
PCR[111] Option 0 GPIO[111]
Option 1 VIU4_PDI2
SIUL
None,
None
VIU2/PDI
PWM/Timer
PWM/Timer
Option 2 eMIOS0[19]
Option 3 eMIOS0[15]
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PJ[7]
PJ[8]
PJ[9]
PCR[112] Option 0 GPIO[112]
Option 1 VIU5_PDI3
—
—
—
—
—
—
—
—
—
SIUL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
S
S
S
S
M
M
F
None,
None
59
71
AC15
VIU2/PDI
PWM/Timer
PWM/Timer
Option 2 eMIOS0[18]
Option 3 eMIOS0[14]
PCR[113] Option 0 GPIO[113]
Option 1 VIU6_PDI4
SIUL
None,
None
8
8
U2
VIU2/PDI
PWM/Timer
PWM/Timer
Option 2 eMIOS0[17]
Option 3 eMIOS0[13]
PCR[114] Option 0 GPIO[114]
Option 1 VIU7_PDI5
SIUL
None,
None
9
9
U1
VIU2/PDI
PWM/Timer
PWM/Timer
Option 2 eMIOS1[22]
Option 3 eMIOS0[12]
PJ[10] PCR[115] Option 0 GPIO[115]
Option 1 VIU8_PDI6
SIUL
None,
None
10
10
V4
VIU2/PDI
PWM/Timer
PWM/Timer
Option 2 eMIOS1[17]
Option 3 eMIOS0[11]
PJ[11] PCR[116] Option 0 GPIO[116]
Option 1 VIU9_PDI7
SIUL
None,
None
11
11
V3
VIU2/PDI
PWM/Timer
PWM/Timer
Option 2 eMIOS1[15]
Option 3 eMIOS0[10]
PJ[12] PCR[117] Option 0 GPIO[117]
Option 1 DCU_TAG
SIUL
DCU3
—
None,
None
148
149
150
151
178
179
180
181
A23
D22
C22
B22
Option 2
—
Option 3 DCULITE_G6
DCULite
PJ[13] PCR[118] Option 0 GPIO[118]
Option 1 QUADSPI_PCS_B
Option 2 eMIOS1[8]
SIUL
None,
None
QuadSPI
PWM/Timer
VIU2/PDI
Option 3 VIU5_PDI13
PJ[14] PCR[119] Option 0 GPIO[119]
Option 1 QUADSPI_CLK_B
Option 2 eMIOS1[17]
SIUL
None,
None
QuadSPI
PWM/Timer
PDI
Option 3 PDI_PCLK
PJ[15] PCR[120] Option 0 GPIO[120]
Option 1 QUADSPI_IO3_B
Option 2 eMIOS1[9]
SIUL
M
None,
None
QuadSPI
PWM/Timer
VIU2/PDI
Option 3 VIU6_PDI14
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PORT K
PK[0]
PCR[121] Option 0 GPIO[121]
Option 1 eMIOS1[18]]
—
—
—
—
—
—
—
—
SIUL
PWM/Timer
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
F
None,
None
155
156
31
187
188
39
A21
D20
AE3
AF3
AC4
AF4
AC5
AD5
Option 2
Option 3
—
—
PK[1]
PK[2]
PK[3]
PK[4]
PK[5]
PK[6]
PK[7]
PCR[122] Option 0 GPIO[122]
Option 1 QUADSPI_IO2_B
Option 2 eMIOS1[14]
SIUL
None,
None
QuadSPI
PWM/Timer
VIU2/PDI
Option 3 VIU7_PDI15
PCR[123] Option 0 GPIO[123]
Option 1 VIU0_PDI8
SIUL
None,
None
VIU2/PDI
PWM/Timer
DCULite
Option 2 eMIOS1[10]
Option 3 DCULITE_TAG
PCR[124] Option 0 GPIO[124]
Option 1 VIU1_PDI9
SIUL
None,
None
32
40
VIU2/PDI
PWM/Timer
DCULite
Option 2 eMIOS1[11]
Option 3 DCULITE_DE
PCR[125] Option 0 GPIO[125]
Option 1 VIU2_PDI10
SIUL
None,
None
33
41
VIU2/PDI
PWM/Timer
DCULite
Option 2 eMIOS1[12]
Option 3 DCULITE_HSYNC
PCR[126] Option 0 GPIO[126]
Option 1 VIU3_PDI11
SIUL
None,
None
34
42
VIU2/PDI
PWM/Timer
DCULite
Option 2 eMIOS1[13]
Option 3 DCULITE_VSYNC
PCR[127] Option 0 GPIO[127]
Option 1 VIU4_PDI12
SIUL
None,
None
35
43
VIU2/PDI
PWM/Timer
DCULite
Option 2 eMIOS1[9]
Option 3 DCULITE_PCLK
PCR[128] Option 0 GPIO[128]
Option 1 RXD_2
SIUL
M
None,
None
—
44
LINFlex_2
DCULite
TCON
Option 2 DCULITE_R2
Option 3 TCON[8]
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PK[8]
PCR[129] Option 0 GPIO[129]
Option 1 TXD_2
—
—
—
—
SIUL
I/O
I/O
I/O
I/O
M
M
S
None,
None
—
—
51
52
45
46
59
60
AE5
AF5
AF8
AC9
LINFlex_2
DCULite
TCON
Option 2 DCULITE_R3
Option 3 TCON[9]
PK[9]
PCR[130] Option 0 GPIO[130]
Option 1 I2S_DO / PWMO
Option 2 DCULITE_R4
Option 3 TCON[10]
SIUL
SGM
DCULite
TCON
None,
None
PK[10] PCR[131] Option 0 GPIO[131]
Option 1 SDA_1
SIUL
None,
None
I2C_1
Option 2 eMIOS1[12]
Option 3 DCULITE_TAG
PWM/Timer
DCULite
PK[11] PCR[132] Option 0 GPIO[132]
Option 1 SCL_1
SIUL
S
None,
None
I2C_1
Option 2 eMIOS1[13]
Option 3 DCU_TAG / TCON[3]
PWM/Timer
DCU3 / TCON
PK[12]
PK[13]
PK[14]
PK[15]
PORT L
PL[0]
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCR[133] Option 0 GPIO[133]
Option 1
Option 2 CANRX_1
Option 3
ANS[19]
ANS[18]
ANS[17]
SIUL
—
I/O
I/O
I/O
M /
None,
—
—
—
81
82
83
AE22
AE21
AF22
—
ANALO None
G
FlexCAN_1
—
—
PL[1]
PL[2]
PCR[134] Option 0 GPIO[134]
Option 1
Option 2 CANTX_1
Option 3
SIUL
—
M /
None,
—
ANALO None
G
FlexCAN_1
—
—
PCR[135] Option 0 GPIO[135]
Option 1
SIUL
—
S /
None,
—
ANALO None
G
Option 2 CANRX_0
Option 3 eMIOS1[22]
FlexCAN_0
PWM/Timer
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PL[3]
PL[4]
PL[5]
PL[6]
PL[7]
PL[8]
PL[9]
PCR[136] Option 0 GPIO[136]
Option 1
ANS[16]
SIUL
—
FlexCAN_0
PWM/Timer
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S /
None,
—
—
—
—
—
—
—
—
—
84
AF21
AB2
AC2
AD1
AE1
AF1
AF2
C24
A24
—
ANALO None
G
Option 2 CANTX_0
Option 3 eMIOS1[23]
PCR[137] Option 0 GPIO[137]
Option 1 CS2_2
—
—
—
—
—
—
—
—
SIUL
M
M
S
None,
None
31
DSPI_2
VIU2/PDI
TCON
Option 2 VIU5_PDI13
Option 3 TCON[6]
PCR[138] Option 0 GPIO[138]
Option 1 CS1_2
SIUL
None,
None
32
DSPI_2
VIU2/PDI
TCON
Option 2 VIU6_PDI14
Option 3 TCON[7]
PCR[139] Option 0 GPIO[139]
Option 1 CS0_2
SIUL
None,
None
33
DSPI_2
VIU2/PDI
PWM/Timer
Option 2 VIU7_PDI15
Option 3 eMIOS1[18]
PCR[140] Option 0 GPIO[140]
Option 1 SIN_2
SIUL
S
None,
None
34
DSPI_2
VIU2/PDI
PWM/Timer
Option 2 VIU8_PDI16
Option 3 eMIOS1[19]
PCR[141] Option 0 GPIO[141]
Option 1 SOUT_2
SIUL
S
None,
None
35
DSPI_2
VIU2/PDI
PWM/Timer
Option 2 VIU9_PDI17
Option 3 eMIOS1[20]
PCR[142] Option 0 GPIO[142]
Option 1 SCK_2
SIUL
DSPI_2
PDI
S
None,
None
36
Option 2 PDI_PCLK
Option 3 eMIOS1[21]
PWM/Timer
PL[10] PCR[143] Option 0 GPIO[143]
Option 1 eMIOS1[10]
SIUL
M
M
None,
None
174
175
PWM/Timer
DCULite
—
Option 2 DCULITE_G2
Option 3
—
PL[11] PCR[144] Option 0 GPIO[144]
Option 1 eMIOS1[11]
SIUL
None,
None
PWM/Timer
DCULite
—
Option 2 DCULITE_G3
Option 3
—
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PL[12] PCR[145] Option 0 GPIO[145]
Option 1 eMIOS1[12]
—
SIUL
I/O
I/O
M
M
None,
None
—
176
C23
PWM/Timer
DCULite
—
Option 2 DCULITE_G4
Option 3
—
PL[13] PCR[146] Option 0 GPIO[146]
Option 1 eMIOS1[13]
—
SIUL
None,
None
—
177
B23
PWM/Timer
DCULite
—
Option 2 DCULITE_G5
Option 3
—
PL[14]
—
—
—
—
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PL[15]
PORT M
PM[0] PCR[147] Option 0 GPIO[147]
Option 1 I2S_SCK / PWMOA
—
—
SIUL
SGM
DCULite
TCON
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
None,
None
—
—
—
—
—
16
61
62
AE9
AF9
D23
Y3
Option 2 DCULITE_R5
Option 3 TCON[11]
PM[1] PCR[148] Option 0 GPIO[148]
Option 1 I2S_FS
SIUL
SGM
DCULite
—
None,
None
Option 2 DCULITE_R6
Option 3
—
PM[2] PCR[149] Option 0 GPIO[149]
Option 1 eMIOS1[17]
RSDSCLKM SIUL
PWM/Timer
None,
None
173
16
Option 2 DCULITE_R7
Option 3 DCULITE_DE
DCULite
DCULite
PM[3] PCR[150] Option 0 GPIO[150]
Option 1 CANRX_2
—
—
—
SIUL
None,
None
FlexCAN_2
LINFlex_3
TCON
Option 2 RXD_3
Option 3 TCON[4]
PM[4] PCR[151] Option 0 GPIO[151]
Option 1 CANTX_2
SIUL
None,
None
17
Y2
FlexCAN_2
LINFlex_3
TCON
Option 2 TXD_3
Option 3 TCON[5]
PM[5] PCR[152] Option 0 GPIO[152]
Option 1 VIU5_PDI13
SIUL
None,
None
—
—
VIU2/PDI
PWM/Timer
DCU3
Option 2 eMIOS1[22]
Option 3 DCU_TAG
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PM[6] PCR[153] Option 0 GPIO[153]
Option 1 VIU6_PDI14
—
—
—
—
—
—
—
—
SIUL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
S
S
M
S
S
M
F
None,
None
17
—
—
—
—
—
—
—
—
—
VIU2/PDI
PWM/Timer
DCULite
Option 2 eMIOS1[23]
Option 3 DCULITE_TAG
PM[7] PCR[154] Option 0 GPIO[154]
Option 1 VIU8_PDI16
SIUL
VIU2/PDI
SGM
None,
None
39
—
Option 2 I2S_DO / PWMO
Option 3 eMIOS1[16]
PWM/Timer
PM[8] PCR[155] Option 0 GPIO[155]
Option 1 VIU9_PDI17
SIUL
VIU2/PDI
SGM
None,
None
40
—
Option 2 I2S_SCK / PWMOA
Option 3 eMIOS1[23]
PWM/Timer
PM[9] PCR[156] Option 0 GPIO[156]
Option 1 PDI_PCLK
SIUL
PDI
SGM
PWM/Timer
None,
None
113
114
115
—
—
Option 2 SGM_MCLK
Option 3 eMIOS0[8]
PM[10] PCR[157] Option 0 GPIO[157]
Option 1 RXD_2
SIUL
None,
None
—
LINFlex_2
FlexCAN_2
PWM/Timer
Option 2 CANRX_2
Option 3 eMIOS0[16]
PM[11] PCR[158] Option 0 GPIO[158]
Option 1 TXD_2
SIUL
None,
None
—
LINFlex_2
FlexCAN_2
PWM/Timer
Option 2 CANTX_2
Option 3 eMIOS0[23]
PM[12] PCR[159] Option 0 GPIO[159]
Option 1 DCULITE_B7
SIUL
DCULite
—
None,
None
L24
L23
Option 2
—
Option 3 I2S_SCK / PWMOA
SGM
PM[13] PCR[160] Option 0 GPIO[160]
Option 1 DCULITE_PCLK
Option 2
Option 3 SGM_MCLK
SIUL
DCULite
—
None,
None
—
—
SGM
PM[14]
PM[15]
—
—
—
—
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PORT N
PN[0]
PCR[161] Option 0 GPIO[161]
Option 1 DCULITE_HSYNC
Option 2
—
—
—
—
—
—
—
—
SIUL
DCULite
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
M
None,
None
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AC3
AD3
—
Option 3 TCON[4]
TCON
PN[1]
PN[2]
PN[3]
PN[4]
PN[5]
PN[6]
PN[7]
PCR[162] Option 0 GPIO[162]
SIUL
DCULite
—
None,
None
Option 1 DCULITE_VSYNC
Option 2
—
Option 3 TCON[5]
TCON
PCR[163] Option 0 GPIO[163]
Option 1 DCULITE_R0
Option 2 RXD_2
SIUL
None,
None
AC10
AF10
AC11
AD11
AE11
AF11
DCULite
LINFlex_2
VIU2/PDI
Option 3 VIU0_PDI8
PCR[164] Option 0 GPIO[164]
Option 1 DCULITE_R1
Option 2 TXD_2
SIUL
None,
None
DCULite
LINFlex_2
VIU2/PDI
Option 3 VIU1_PDI9
PCR[165] Option 0 GPIO[165]
Option 1 DCULITE_R2
SIUL
DCULite
—
None,
None
Option 2
—
Option 3 TCON[6]
TCON
PCR[166] Option 0 GPIO[166]
Option 1 DCULITE_R3
SIUL
DCULite
—
None,
None
Option 2
—
Option 3 TCON[7]
TCON
PCR[167] Option 0 GPIO[167]
Option 1 DCULITE_R4
SIUL
DCULite
—
None,
None
Option 2
—
Option 3 TCON[8]
TCON
PCR[168] Option 0 GPIO[168]
Option 1 DCU_LITE_R5
SIUL
DCULite
—
None,
None
Option 2
—
Option 3 TCON[9]
TCON
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PN[8]
PCR[169] Option 0 GPIO[169]
Option 1 DCULITE_R6
—
—
—
—
—
—
—
—
SIUL
DCULite
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
M
None,
None
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AC12
AD12
AE12
AF12
R26
Option 2
—
Option 3 TCON[10]
TCON
PN[9]
PCR[170] Option 0 GPIO[170]
Option 1 DCULITE_R7
SIUL
DCULite
—
None,
None
Option 2
—
Option 3 TCON[11]
TCON
PN[10] PCR[171] Option 0 GPIO[171]
Option 1 DCULITE_G0
Option 2 RXD_3
SIUL
None,
None
DCULite
LINFlex_3
VIU2/PDI
Option 3 VIU2_PDI10
PN[11] PCR[172] Option 0 GPIO[172]
Option 1 DCULITE_G1
Option 2 TXD_3
SIUL
None,
None
DCULite
LINFlex_3
VIU2/PDI
Option 3 VIU3_PDI11
PN[12] PCR[173] Option 0 GPIO[173]
Option 1 DCULITE_G2
SIUL
DCULite
—
None,
None
Option 2
—
Option 3 eMIOS0[17]
PWM/Timer
PN[13] PCR[174] Option 0 GPIO[174]
Option 1 DCULITE_G3
SIUL
DCULite
—
None,
None
R25
Option 2
—
Option 3 eMIOS0[18]
PWM/Timer
PN[14] PCR[175] Option 0 GPIO[175]
Option 1 DCULITE_G4
SIUL
DCULite
—
None,
None
P26
Option 2
—
Option 3 eMIOS0[19]
PWM/Timer
PN[15] PCR[176] Option 0 GPIO[176]
Option 1 DCULITE_G5
SIUL
DCULite
—
None,
None
P24
Option 2
—
Option 3 eMIOS0[20]
PWM/Timer
PORT P
PP[0]
PCR[177] Option 0 GPIO[177]
Option 1 DCULITE_G6
—
SIUL
DCULite
—
I/O
M
None,
None
—
—
P23
Option 2
—
Option 3 eMIOS0[21]
PWM/Timer
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PP[1]
PP[2]
PP[3]
PP[4]
PP[5]
PP[6]
PP[7]
PCR[178] Option 0 GPIO[178]
Option 1 DCULITE_G7
—
—
—
—
—
—
—
SIUL
DCULite
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
None,
None
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N26
N25
N23
M26
M25
M24
M23
Option 2
—
Option 3 eMIOS0[22]
PWM/Timer
PCR[179] Option 0 GPIO[179]
Option 1 DCULITE_B0
Option 2 CANRX_2
SIUL
None,
None
DCULite
FlexCAN_2
VIU2/PDI
Option 3 VIU4_PDI12
PCR[180] Option 0 GPIO[180]
Option 1 DCULITE_B1
Option 2 CANTX_2
SIUL
None,
None
DCULite
FlexCAN_2
PDI
Option 3 PDI_DE
PCR[181] Option 0 GPIO[181]
Option 1 DCULITE_B2
SIUL
DCULite
—
None,
None
Option 2
—
Option 3 eMIOS0[11]
PWM/Timer
PCR[182] Option 0 GPIO[182]
Option 1 DCULITE_B3
SIUL
DCULite
—
None,
None
Option 2
—
Option 3 eMIOS0[13]
PWM/Timer
PCR[183] Option 0 GPIO[183]
Option 1 DCULITE_B4
SIUL
DCULite
—
None,
None
Option 2
—
Option 3 eMIOS0[15]
PWM/Timer
PCR[184] Option 0 GPIO[184]
Option 1 DCULITE_B5
SIUL
DCULite
—
None,
None
Option 2
—
Option 3 I2S_FS
SGM
PP[8]
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PP[9]
PP[10]
PP[11]
Table 7. Port pin summary (continued)
Pin number
Port
pin
Alternate
function1
Special
I/O
Pad RESET
PCR
Function
Peripheral3
function2
direction Type4 config5
176 LQFP 208 LQFP 416 TEPBGA
PP[12]
PP[13]
PP[14]
PP[15]
—
—
—
—
—
—
—
—
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
Reserved
Reserved
1
Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIUL module.
PCR[PA] = 00 selects Option 0
PCR[PA] = 01 selects Option 1
PCR[PA] = 10 selects Option 2
PCR[PA] = 11 selects Option 3
This is intended to select the output functions. To use one of the input functions, the PCR[IBE] bit must be written to ‘1’, regardless of the values selected in
the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is reported as “—”.
2
3
Special functions are enabled independently from the standard digital pin functions. Enabling standard I/O functions in the PCR registers may interfere with
their functionality. ADC functions are enabled using the PCR[APC] bit; other functions are enabled by enabling the respective module.
Using the PSMI registers in the System Integration Unit Lite (SIUL), different pads can be multiplexed to the same peripheral input. Please see the SIUL chapter
of the PXD20 Microcontroller Reference Manual for details.
4
5
6
See the “Pad types” section for an explanation of the letters in this column.
Reset configuration is given as I/O direction and pull, e.g., “Input, pullup”.
Out of reset pins PH[0:3] are available as JTAG pins (TCK, TDI, TDO and TMS respectively). It is up to the user to configure pins PH[0:3] when needed.
System design information
3
System design information
3.1
Power-up sequencing
The preferred power-up sequence for PXD20 is as follows:
1. Generic IO supplies or noise-free supplies, consisting of:
— VDDA
— VDDE_A
— VDDE_B
— VDDM
— VDD_DR
— VDD33_DR
— VDDPLL
Figure 6. Power-up sequencing
PXD20 Microcontroller Data Sheet, Rev. 2
60
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
System design information
Figure 7. Power-down sequencing
2. All 3.3V supplies (VDDE_B and VDD33_DR) should be ramped up first, and then the rest of the I/O supplies should
be ramped up (VDDA, VDDE_A, VDDM, and VDD_DR).
3. VDDR, the regulator input supply, should be the last supply to ramp up; all supplies can be ramped up together as long
as VDDR is included. So all 5V supplies should be ramped up after the 3.3 V supplies, and if all the supplies are of
the same level, they can be ramped up together as well.
4. LV supply (VDD12). If Vreg is in bypass mode and the core supply (1.2 V) is supplied externally, then this should be
the last supply given.
NOTE
For DDR, the 3.3 V supply (VDD33_DR) should come before VDD_DR.
This sequence ensures that when VREG releases its LVDs, the IO and other HV segments
are powered properly. This is important because PXD20 doesn't monitor LVDs on IO HV
supplies.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
61
Electrical characteristics
4
Electrical characteristics
4.1
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This could be done by
DD
SS
internal pull up and pull down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
4.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the classifications listed in Table 8 are used and the parameters are tagged
accordingly in the tables where appropriate.
Table 8. Parameter classifications
Classification tag
Tag description
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
PXD20 Microcontroller Data Sheet, Rev. 2
62
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
4.3
Absolute maximum ratings
Table 9. Absolute maximum ratings
Value
Symbol
C
Parameter
Conditions
Unit SpecID
Min
Max
VDDA
SR D Voltage on VDDA pin (ADC reference) with
respect to ground (VSSA
–0.3
+5.5
V
D1.1
)
Relative to VDD VDD – 0.3 VDD + 0.3
VSSA
SR D Voltage on VSSA (ADC reference) pin with
respect VSS
VSS – 0.1
VSS+0.1
V
V
D1.2
D1.3
VDDPLL
CC D Voltage on VDDPLL (1.2 V PLL supply) pin with
1.08
1.32
respect to ground (VSSPLL
)
Relative to VDD VDD – 0.3 VDD + 0.3
–0.3 +5.5
VDDR
SR D Voltage on VDDR pin (regulator supply) with
respect to ground (VSSR
V
D1.4
)
Relative to VDD VDD – 0.3 VDD + 0.3
VSS – 0.1 VSS + 0.1
VSSR
VDD12
VSS12
SR D Voltage on VSSR (regulator ground) pin with
respect to VSS
V
V
D1.5
D1.6
CC D Voltage on VDD12 pin with respect to ground
1.08
1.4
(VSS12
)
CC D Voltage on VSS12 pin with respect to VSS
VSS – 0.1 VSS + 0.1
V
V
D1.7
D1.8
1
VDDE_A
SR D Voltage on VDDE_A (I/O supply) pin with
–0.3
–0.3
–0.3
+5.5
+3.6
+5.5
respect to ground (VSSE_A
)
1
VDDE_B
SR D Voltage on VDDE_B (I/O supply) pin with
V
V
D1.9
respect to ground (VSS
)
1
VDDM
SR D Voltage on VDDM (stepper motor supply) pin
D1.10
with respect to ground (VSSM
)
2
VSS
SR D I/O supply ground
0
0
V
V
V
V
D1.11
D1.12
D1.13
VDD_DR
VRSDS
VIN
D Voltage on VDDDDR with respect to VSS
D Voltage on VDDRSDS with respect to VSS
–0.3
–0.3
–0.3
3.6
3.6
SR D Voltage on any GPIO pin with respect to ground
VDDmax
(VDDE maxof
that
(VSS
)
segment)
IINJPAD
IINJSUM
SR D Injected input current on any pin during
overload condition
–10
–50
–55
10
50
mA
D1.15
D1.16
SR D Absolute sum of all injected input currents
during overload condition
TSTORAGE SR T Storage temperature
150
°C
V
D1.17
D1.18
ESDHBM SR T ESD Susceptibility (Human Body Model)
2000
1
2
Throughout the remainder of this document VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, and VDDM
unless otherwise noted.
,
Throughout the remainder of this document VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSPLL, and
VSSM, unless otherwise noted.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
63
Electrical characteristics
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (V > V or
IN
DD
V
< V ), the voltage on pins with respect to ground (V ) must not exceed the
IN
SS SS
recommended values.
4.4
Recommended operating conditions
Table 10. Recommended operating conditions (3.3 V)
Value
Symbol
C
Parameter
Conditions
Unit SpecID
Min
Max
+3.6
1
VDDA
SR P Voltage on VDDA pin (ADC reference) with re-
+3.0
V
D2.1
spect to ground (VSS
)
D
Relative to VDD VDD – 0.1 VDD + 0.1
VSS – 0.1 VSS + 0.1
VSSA
SR P Voltage on VSSA (ADC reference) pin with
respect VSS
V
V
V
D2.2
D2.3
D2.4
VDDPLL CC P Voltage on VDDPLL (1.2 V PLL supply) pin
with respect to ground (VSSPLL
1.08
1.32
)
2
VDDR
SR P Voltage on VDDR pin (regulator supply) with
respect to ground (VSSR
+3.0
+3.6
)
D
Relative to VDD VDD – 0.1 VDD + 0.1
VSS – 0.1 VSS + 0.1
VSSR
SR D Voltage on VSSR (regulator ground) pin with
respect to VSS
V
V
D2.5
D2.6
3,4
VDD12
CC P Voltage on VDD12 pin with respect to ground
1.08
1.4
(VSS12
)
VSS12 CC D Voltage on VSS12 pin with respect to VSS
VSS – 0.1 VSS + 0.1
V
V
D2.7
D2.8
5,6,7
5
5
VDD
SR P Voltage on VDD pins (VDDE_A, VDDE_B
,
VDDmin
VDDmax
VDD_DR, VDDM) with respect to ground (VSS
)
8
VSS
SR D I/O supply ground
0
0
V
V
D2.9
9
VDDE_A SR P Voltage on VDDE_A (I/O supply) pin with
respect to ground (VSSE_A
+3.0
+3.6
D2.10
)
VDDE_B SR P Voltage on VDDE_B (I/O supply) pin with
respect to ground (VSSE_B
+3.0
+3.0
+3.6
+3.6
V
V
D2.11
D2.12
)
VDDM
SR P Voltage on VDDM (stepper motor supply) pin
with respect to ground (VSSM
)
VDD_DR
VSS_DR
VRSDS
TVDD
TA
P Voltage on VDDDDR with respect to VSS
D Voltage on VSSRSDS with respect to VSS
P Voltage on VDDDDR with respect to VSS
SR D VDD slope to ensure correct power up10
SR P Ambient temperature under bias
SR D Junction temperature under bias
+1.62
+1.62
+3.0
+3.6
+3.6
+3.6
12
V
V
D2.13
D2.14
D2.15
D2.16
D2.17
D2.18
V
V/ms
°C
–40
–40
105
140
TJ
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
64
Freescale Semiconductor
Electrical characteristics
1
2
3
4
100 nF capacitance needs to be provided between VDDA/VSSA pair.
10 F capacitance must be connected between VDDR and VSS12 because of a sharp surge due to external ballast.
VDD12 cannot be used to drive any external component.
Each VDD12/VSS12 supply pair should have a 10 F capacitor. Absolute combined maximum capacitance is 40 F. Preferably,
all the VDD12 supply pads should be shorted and then connected to a 4 10 F capacitance. This is to ensure the ESR of
external capacitance does not exceed 0.2 . A 100 nF capacitor must be placed close to the pin.
5
6
VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDD_DR, and VDDM
.
100 nF capacitance needs to be provided between each VDD/VSS pair. VDDmin value for is 3 V for VDDE_A & VDDM as well
as for VDDE_B, while it is 1.62 V for VDD_DR. VDD max value is 3.6 V for VDDE_A & VDDM as well as for VDDE_B &
VDD_DR.
7
Full electrical specification cannot be guaranteed when voltage drops below 3.0V. In particular, ADC electrical characteristics
and I/O’s DC electrical specification may not be guaranteed.
When voltage drops below VLVDHVL device is reset.
8
9
VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSS, and VSSM unless otherwise noted.
VDDE_A should not be less than VDDA
.
10 Guaranteed by device validation.
Table 11. Recommended operating conditions (5.0 V)
Value
Symbol
C
Parameter
Conditions
Unit SpecID
Min
Max
1
VDDA
SR P Voltage on VDDA pin (ADC reference) with re-
+4.5
+3.0
+5.5
+5.5
V
D2.19
spect to ground (VSS
)
D
D
Voltage drop2
Relative to VDD VDD – 0.1 VDD + 0.1
VSSA
SR D Voltage on VSSA (ADC reference) pin with
respect VSS
VSS – 0.1
VSS + 0.1
V
V
V
D2.20
D2.21
D2.22
VDDPLL CC P Voltage on VDDPLL (1.2 V PLL supply) pin
with respect to ground (VSSPLL
1.08
1.32
)
3
VDDR
SR P Voltage on VDDR pin (regulator supply) with
+3.0
+3.0
+3.6
+3.6
respect to ground (VSSR
)
D
D
Voltage drop2
Relative to VDD VDD – 0.1 VDD + 0.1
VSSR
SR D Voltage on VSSR (regulator ground) pin with
respect to VSS
VSS – 0.1
VSS + 0.1
V
V
D2.23
D2.24
4,5
VDD12
CC P Voltage on VDD12 pin with respect to ground
1.08
1.4
(VSS12
)
VSS12
CC D Voltage on VSS12 pin with respect to VSS
VSS – 0.1
VSS + 0.1
V
V
D2.25
D2.26
6,7
6
6
VDD
SR P Voltage on VDD pins (VDDE_A, VDDE_B,
VDD_DR, VDDMA, VDDMB, VDDMC) with
Voltage drop2
VDDmin
VDDmax
respect to ground (VSS
)
8
VSS
SR D I/O supply ground
0
0
V
V
D2.27
D2.28
9
VDDE_A SR P Voltage on VDDE_A (I/O supply) pin with
respect to ground (VSSE_A
+4.5
+5.5
)
10
VDDE_B
SR P Voltage on VDDE_B (I/O supply) pin with
respect to ground (VSSE_B
+3.0
+3.6
V
D2.29
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
65
Electrical characteristics
Table 11. Recommended operating conditions (5.0 V) (continued)
Value
Symbol
C
Parameter
Conditions
Unit SpecID
Min
Max
VDDM
SR P Voltage on VDDMA (stepper motor supply)
pin with respect to ground (VSSMA
+4.5
+5.5
V
D2.30
)
11
VDD_DR
P Voltage on VDD_DR with respect to VSS
D Voltage on VSSRSDS with respect to VSS
P Voltage on VDD_DR with respect to VSS
SR D VDD slope to ensure correct power up12
SR P Ambient temperature under bias
+1.62
+1.62
+3.0
+3.6
+3.6
+3.6
12
V
V
V
D2.31
D2.32
D2.33
VSS_DR
VRSDS
TVDD
TA
V/ms D2.34
–40
–40
–40
105
105
140
°C
D2.35
D2.36
TJ
SR D Junction temperature under bias
1
2
100 nF capacitance needs to be provided between VDDA/VSSA pair.
Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical characteristics
may not be guaranteed below 4.5 V during the voltage drop sequence.
3
10 F capacitance must be connected between VDDR and VSS12. It is recommended that this cap should be placed, as close
as possible to the DUT pin on board.
4
5
VDD12 cannot be used to drive any external component.
Each VDD12/VSS12 supply pair should have a 10 F capacitor. Absolute combined maximum capacitance is 40 F. Preferably,
all the VDD12 supply pads should be shorted and then connected to a 410 F capacitance. This is to ensure the ESR of
external capacitance does not exceed 0.2 . A 100 nF capacitor must be placed close to the pin.
VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_DR, VDDMA, VDDMB and VDDMC. VDDmin value for
is 4.5 V for VDDE_A & VDDM, 3 V VDDE_B, while it is 1.62 V for VDD_DR. VDD max value is 5.5 V for VDDE_A & VDDM
and 3.6 V for VDDE_B & VDD_DR.
6
7
8
100 nF capacitance needs to be provided between each VDD/VSS pair.
VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_A, VSSE_E, VSSMA, VSSMB and VSSMC) unless
otherwise noted.
9
VDDE_A should not be less than VDDA
.
10 VDDE_B cannot go beyond 3.6V under any operating condition.
11 VDD_DR can be 1.8, 2.5 and 3.3V (typical) based on type of SDR memory.
12 Guaranteed by device validation
4.5
Thermal characteristics
1
Table 12. Thermal characteristics for 176-pin LQFP
Parameter Conditions
CC D Junction to Ambient Natural Convection2 Single layer board –1s
CC D Junction to Ambient Natural Convection2 Four layer board –2s2p
Symbol
RJA
RJA
RJMA
C
Value
Unit
SpecID
36
29
28
°C/W
°C/W
°C/W
D3.1
D3.2
D3.3
CC D Junction to Ambient2
@200 ft./min., single layer
board –1s
RJMA
CC D Junction to Ambient2
@200 ft./min., Four layer
board –2s2p
23
°C/W
D3.4
RJB
CC D Junction to Board3
CC D Junction to Case (Top)4
18
5
°C/W
°C/W
D3.5
D3.6
RJCtop
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
66
Freescale Semiconductor
Electrical characteristics
Table 12. Thermal characteristics for 176-pin LQFP (continued)
1
Symbol
JT
C
Parameter
Conditions
Value
Unit
SpecID
CC D Junction to Package Top Natural Convec-
tion5
2
°C/W
D3.7
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3
4
5
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used
for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
1
Table 13. Thermal characteristics for 208-pin LQFP
Symbol
RJA
C
Parameter
Conditions
Value
Unit
SpecID
CC D Junction to Ambient Natural Convection2
CC D Junction to Ambient Natural Convection2
CC D Junction to Ambient2
Single layer board –1s
Four layer board –2s2p
34
27
27
°C/W
°C/W
°C/W
D3.8
D3.9
RJA
RJMA
@200 ft./min., single layer
board –1s
D3.10
RJMA
CC D Junction to Ambient2
@200 ft./min., Four layer
board –2s2p
22
°C/W
D3.11
RJB
RJCtop
JT
CC D Junction to Board3
CC D Junction to Case (Top)4
—
—
—
18
5
°C/W
°C/W
°C/W
D3.12
D3.13
D3.14
CC D Junction to Package Top Natural Convec-
tion5
2
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC
specification for this package.
3
4
5
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used
for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as
Psi-JT.
1
Table 14. Thermal characteristics for 416-pin TEPBGA
Symbol
RJA
C
Parameter
Conditions
Value
Unit
SpecID
CC D Junction to Ambient Natural Convection2 Single layer board –1s
CC D Junction to Ambient Natural Convection2 Four layer board –2s2p
CC D Junction to Ambient2
26
18
20
°C/W
°C/W
°C/W
D3.15
D3.16
D3.17
RJA
RJMA
@200 ft./min., single layer
board –1s
RJMA
CC D Junction to Ambient2
@200 ft./min., Four layer
board –2s2p
15
°C/W
D3.18
RJB
CC D Junction to Board3
CC D Junction to Case (Top)4
—
—
10
6
°C/W
°C/W
D3.19
D3.20
RJCtop
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
67
Electrical characteristics
Table 14. Thermal characteristics for 416-pin TEPBGA (continued)
1
Symbol
JT
C
Parameter
Conditions
Value
Unit
SpecID
CC D Junction to Package Top Natural Convec-
tion5
—
2
°C/W
D3.21
1
2
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3
4
5
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used
for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
4.5.1
General notes for specifications at maximum junction temperature
An estimate of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
* P )
Eqn. 1
J
A
JA
D
where:
T = ambient temperature for the package ( C)
o
A
o
R
= junction to ambient thermal resistance ( C/W)
JA
P = power dissipation in the package (W)
D
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a
four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance
is not a constant. The thermal resistance depends on the:
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit
board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components are well separated
Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the
ambient temperature varies widely within the application. For many natural convection and especially closed box applications,
the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the
device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
PXD20 Microcontroller Data Sheet, Rev. 2
68
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R * P )
Eqn. 2
J
B
JB
D
where:
o
T = board temperature for the package perimeter ( C)
B
o
R
= junction-to-board thermal resistance ( C/W) per JESD51-8S
JB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction
temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to
a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal
resistance:
R
= R
+ R
CA
Eqn. 3
JA
JC
where:
o
R
R
R
R
= junction to ambient thermal resistance ( C/W)
JA
JC
CA
JC
o
= junction to case thermal resistance ( C/W)
o
= case to ambient thermal resistance ( C/W)
s device related and is not affected by other factors. The thermal environment can be controlled to change the
. For example, change the air flow around the device, add a heat sink, change the
case-to-ambient thermal resistance, R
CA
mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding
the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat
sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the
junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the
thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple
estimations and for computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization
parameter ( ) to determine the junction temperature by measuring the temperature at the top center of the package case using
JT
the following equation:
T = T + ( x P )
Eqn. 4
J
T
JT
D
where:
o
T = thermocouple temperature on top of the package ( C)
T
o
= thermal characterization parameter ( C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests
on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from
the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling
effects of the thermocouple wire.
References:
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
69
Electrical characteristics
Semiconductor Equipment and Materials International
805 East Middlefield Rd.
Mountain View, CA 94043
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
4.6
EMI (electromagnetic interference) characteristics
1 2
Table 15. EMI testing specifications
Frequency
Range
Level
(Typ)
Symbol
Parameter
Conditions
Clocks
Unit
Radiated
Emissions
VEME
Device Configuration,
test conditions and EM
testing per standard
IEC61967-2
FOSC — 8 MHz, External
Crystal
150 kHz –
50 MHz
19
30
25
19
dBµV
FCPU —124 MHz
FBUS —124 MHz
50 MHz –
150 MHz
No PLL Frequency
Modulation
150 MHz –
500 MHz
500 MHz –
1000 MHz
IEC Level
K
FOSC — 8 MHz, External
Crystal
150 kHz –
50 MHz
15
dBµV
FCPU —124 MHz
FBUS —124 MHz
50 MHz –
150 MHz
24
17
14
L
2% PLL Frequency
Modulation
150 MHz –
500 MHz
500 MHz –
1000 MHz
IEC Level
1
2
The reported emission level is the value of the maximum emission, rounded up to the next whole number.
IEC Level Maximum:, L is less than or equal to 24 dBµV, K is less than or equal to 30 dBµV.
4.7
Power management
4.7.1
Voltage regulator electrical characteristics
The internal voltage regulator requires an external NPN (BCP68 or NJD2873) ballast to be connected as shown in Figure 8 s
well as an external capacitance (C ) to be connected to the device in order to provide a stable low voltage digital supply to
REG
the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to
limit the serial inductance of the board to less than 15 nH.
PXD20 Microcontroller Data Sheet, Rev. 2
70
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
supply pair and also between the
For the PXD20 microcontroller, 100 nF should be placed between each V
/V
DD12 SS12
V
/V
pair. Additionally, 10 F should be placed between the V
pin and the adjacent V pin.
DDPLL SSPLL
DDR SS
V
= 3.0 V to 3.6 V / 4.5 V to 5.5 V, T = –40 to 105 °C, unless otherwise specified.
DDR
A
V
DDR
VRC_CTRL
V
DD12
Figure 8. External NPN ballast connections
Table 16. Voltage regulator electrical characteristics
Symbol
C
Parameter
Conditions
Min
Max Unit SpecID
VDDR SR P Power supply
3.0
5.5
V
D5.1
D5.2
D5.3
—
—
TJ
SR D Junction temperature
–40
—
140
°C
IREG
CC
T
Current consumption
Reference included,
@ 55 °C No load
@ Full load
mA
2
11
IL
CC
T
Output current capacity
DC load current
—
—
450
mA
V
D5.4
D5.5
VDD12 CC D Output voltage (value @ IL = 0 @ 27°C)
Pre-trimming sigma
< 7 mV
1.330
P
Post-trimming
Post-trimming
1.26
1.145
10 × 4
1.29
—
T
Output voltage (value @ IL = Imax)
SR D External decoupling/stability capacitor
4 capacitances of
10 µF each
—
µF
D5.6
D
D
ESR of external cap
0.05
0.2
0.2
1
ohm
ohm
1 bond wire R + 1
pad R
LBOND CC
CC
D
Bonding Inductance for Bipolar Base Control pad
0
15
nH
dB
D5.7
D5.8
D
D
D
D
D
Power supply rejection
@ DC @ no load
@ 200 kHz @ no load
@ DC @ 400 mA
Cload = 10 µF × 4
—
–30
–100
–30
@ 200 kHz @ 400 mA
–30
CC
Load current transient
Cload = 10 µF × 4
Cload = 10 µF × 4
—
—
10% to 90%
of IL (max) in
100 ns
D5.9
tSU
CC
T
Start-up time after input supply stabilizes1
500
µs
D5.10
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
71
Electrical characteristics
1
Time after the input supply to the voltage regulator has ramped up (VDDR) and the voltage regulator has asserted the Power
OK signal.
Table 17. Low-power voltage regulator electrical characteristics
Symbol
C
Parameter
Conditions
Min
Max Unit SpecID
TJ
SR D Junction temperature
–40
140
°C
µA
D5.2
D5.3
—
IREG
CC
CC
T
T
Current consumption
Reference included,
@ 55 °C No load
@ Full load
—
5
600
IL
Output current capacity
DC load current
—
—
15
mA
V
D5.4
D5.5
VDD12 CC D Output voltage
Pre-trimming sigma
< 7 mV
1.33
P
Post-trimming
1.14
1.32
Table 18. Ultra low-power voltage regulator electrical characteristics
Symbol
C
Parameter
Conditions
Min
Max Unit SpecID
TJ
SR D Junction temperature
–40
140
°C
µA
D5.2
D5.3
—
IREG
CC
CC
T
T
Current consumption
Reference included,
@ 55 °C No load
@ Full load
—
2
100
IL
Output current capacity
DC load current
—
—
5
mA
V
D5.4
D5.5
VDD12 CC D Output voltage (value @ IL = 0 @ 27°C)
Pre-trimming sigma
< 7 mV
1.33
P
Post-trimming
1.14
1.32
4.7.2
Voltage monitor electrical characteristics
The device implements a Power On Reset module to ensure correct power-up initialization, as well as four low voltage detectors
to monitor the V and the V voltage while device is supplied:
DD
DD12
•
•
•
•
•
POR monitors V during the power-up phase to ensure device is maintained in a safe reset state
DD
LVDHV3 monitors V to ensure device reset below minimum functional supply
DD
LVDHV5 monitors V when application uses device in the 5.0V ±10% range
DD
LVDLVCOR monitors power domain No. 1
LVDLVBKP monitors power domain No. 0
PXD20 Microcontroller Data Sheet, Rev. 2
72
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Table 19. Low voltage monitor electrical characteristics
Value2
Min Typ Max
Symbol
C
Parameter
Conditions1
Unit SpecID
VPORH
CC C Power-on reset threshold
TA = 25°C,
after trimming
1.5
—
—
—
—
—
—
—
—
2.7
2.8
V
D5.11
D5.12
D5.13
D5.14
D5.15
D5.16
D5.17
VLVDHV3H CC C LVDHV3 low voltage detector high threshold
VLVDHV3L CC C LVDHV3 low voltage detector low threshold
VLVDHV5H CC C LVDHV5 low voltage detector high threshold
VLVDHV5L CC C LVDHV5 low voltage detector low threshold
VLVDLVCORH CC C LVDLVCOR low voltage detector high threshold
VLVDLVCORL CC C LVDLVCOR low voltage detector low threshold
2.7
—
—
4.37
—
4.2
—
1.185
—
1.095
1
2
VDD = 3.3V ±10% / 5.0V ± 10%, TA = –40 to 105°C, unless otherwise specified.
All values need to be confirmed during device validation.
4.7.3
Low voltage domain power consumption
Table 20 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 20. DC electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit
Min Typ
Max
2
IDDMAX
CC D RUN mode maximum
average current
—
—
—
—
250 276.633 mA
4
IDDRUN
CC P RUN mode typical
average current5
fCPU = 125 MHz, Dual Display Drive
with external DRAM, 416 TEPBGA
package option only
—
275
240
—
—
mA
f
CPU = 125 MHz, Single Display Drive,
—
—
no external DRAM, 176 LQFP / 208
LQFP package options
IDDHALT CC C HALT mode current6
Slow internal RC oscillator (128 kHz) TA = 25 oC
—
—
—
—
—
—
—
—
17.5 21.5 mA
running
P
TB = 105 oC
35
43.5
—
IDDSTOP CC D STOP mode current7
Slow internal RC oscillator (128 kHz) TA = –40oC
645
A
running
D
P
D
D
P
TA = 0oC
1100
—
TA = 25oC
TA = 55oC
TA = 85oC
TA = 105oC
1531 1615
3.8
9.7
—
—
mA
17.67 18.46
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
73
Electrical characteristics
Table 20. DC electrical characteristics (continued)
Value2
Min Typ
Symbol
C
Parameter
Conditions1
Unit
Max
IDDSTDBY2 CC D STANDBY2 mode
SXOSC (32 KHz9) ON and RTC
running
TA = –40oC
TA = 0oC
—
—
—
—
—
—
470
480
481
525
650
870
63
—
—
A
current8
D
(64K SRAM on)
P
D
D
P
TA = 25oC
TA = 55oC
TA = 85oC
TA = 105oC
TA = –40oC
TA = 0oC
490
—
—
910
—
CC
D
D
P
D
D
P
SXOSC (32 KHz) and RTC OFF
A
A
A
85
—
TA = 25oC
TA = 55oC
TA = 85oC
TA = 105oC
TA = –40oC
TA = 0oC
93
100
—
95
190
390
415
422
426
575
680
810
20
—
430
—
IDDSTDBY1 CC D STANDBY1 mode
SXOSC (32KHz) ON and RTC
running
—
—
—
—
—
—
current
D
—
(8K SRAM on)10
P
D
D
P
TA = 25oC
TA = 55oC
TA = 85oC
TA = 105oC
TA = –40oC
TA = 0oC
430
—
—
915
—
CC
D
D
P
D
D
P
SXOSC (32 KHz) and RTC OFF
22
—
TA = 25oC
TA = 55oC
TA = 85oC
TA = 105oC
29
45
—
47
118
236
—
310
1
2
VDD = 3.0 V to 5.5 V, TA = –40 to 105 °C, unless otherwise specified.
IDDMAX is composed of the current consumption on all supplies (VDD12, VDDE_A, VDDE_B, VDDA, VDDR, VDDM, VDDPLL, and
VDD_DR). It does not include current consumption linked to I/Os toggling which is highly dependent on the application. The
given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify
operation on-going on data flash. It is to be noticed that this value can be significantly reduced by application; switch-off not
used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use
low power mode when possible.
3
4
5
HIgher current may be sinked by device during power-up and standby exit. Please refer to inrush current in Table 21.
RUN current measured with typical application and accesses on both flash and RAM.
Data and Code Flash in Normal Power. Code fetched from RAM: DCUs running with 20MHz pixel clock, QuadSPI fetching data
at 80MHz, GPU accessing internal SRAM and external DRAM, DMA, RLE, and VIU active, Serial IPs CAN and LIN in loop
back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/ADC/SMD/SSD/SGM) and running
at max frequency, periodic SW/WDG timer reset enabled.
PXD20 Microcontroller Data Sheet, Rev. 2
74
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
6
7
Flash in Low Power. RCOSC 128 kHz and RCOSC 16 MHz ON. 10 MHz XTAL clock. FlexCAN: instances: 0, 1ON (clocked
but no reception or transmission), LINFLEX: instances 0, 1, 2 ON (clocked but no reception or transmission). eMIOS: instance:
0, 1 ON - 16 channels on with PWM20K Hz. DSPI: instance: 0 (clocked but no communication). DCUs, TCON, VIU, GPU clock
gated, RTC/API ON.PIT ON. STM ON. ADC ON but not converting.
No clock, RC 16MHz off, RCI 128 kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock
gated. Flash in power down mode.
8
9
ULPreg ON, HP/LPVreg off, 64 KB RAM on, device configured for minimum consumption, all possible modules switched off.
32 KHz oscillator operates at 32,768 Hz.
10 ULPreg ON, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules switched off.
4.8
DC electrical specifications
4.8.1
DC specification for CMOS090LP2 library @ VDDE = 3.3 V
NOTE
These pad specifications are applicable for pads in the Digital segment Only. See the
“GPIO power bank supplies and functionality” table in the “Voltage Regulators and Power
Supplies” chapter of the reference manual for details.
Table 21. DC electrical specifications
Value
Symbol
C
Parameter
Condition
Unit SpecID
Min
Max
Vdd
Vdde
Vdd33
Vih_c
SR P Core supply voltage
SR P I/O supply voltage
—
—
—
1.08
3.0
1.47
3.6
V
V
V
V
D9.1
D9.2
D9.3
D9.4
SR P I/O pre-driver supply voltage
3.0
3.6
SR P CMOS input buffer high
voltage
With hysteresis enabled 0.65 Vdde Vdde + 0.3
With hysteresis disabled 0.55 Vdde Vdde + 0.3
Vil_c
SR P CMOS input buffer low
voltage
With hysteresis enabled
With hysteresis disabled
—
Vss – 0.3
Vss – 0.3
0.1 Vdde
0.35 Vdde
0.40 Vdde
—
V
D9.5
Vhys_c
SR T CMOS input buffer hysteresis
V
V
D9.6
D9.7
Vih_fod_h SR P 5 V tolerant CMOS input
buffer high voltage
With hysteresis enabled 0.65 Vdd33 Vdd33 + 0.3
Vil_fod_h SR P 5 V tolerant CMOS input
buffer low voltage
With hysteresis enabled
Vss – 0.3
25
0.35 Vdd33
V
D9.8
D9.9
Iact_s
Iinact_d
Iinact_a
Voh
SR T Selectable weak
pullup/pulldown current
—
Weak pull inactive
Weak pull inactive
—
150
2.5
150
—
A
A
A
V
SR P Digital pad input leakage
current
–2.5
D9.10
D9.11
D9.12
SR P Analog pad input leakage
current
–150
SR P Output high voltage
0.8 Vdde
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
75
Electrical characteristics
Table 21. DC electrical specifications (continued)
Value
Symbol
C
Parameter
Condition
Unit SpecID
Min
Max
Vol
SR P Output low voltage
—
—
—
—
0.9 Vdde
—
0.2 Vdde
—
V
V
V
D9.13
D9.14
D9.15
D9.16
Voh_pci
Vol_pci
SR P PCI output high voltage
SR P PCI output low voltage
0.1 Vdde
0.2 Vdd33
Vol_fod_h SR P Fast open-drain output low Iol_fod_h = 10 mA
voltage
—
Table 22. Drive current, VDDE=3.3 V (±10%)
Pad
C
Drive mode
Minimum Ioh (mA)1
Minimum Iol (mA)2
pad_fc
C
00
01
10
11
All
All
16.1
31.8
47.2
77
24
47.9
70.6
114.5
83.6
83.6
pad_msr
pad_ssr
P
P
61.9
61.9
1
2
Ioh is defined as the current sourced by the pad to drive the output to Voh.
Iol is defined as the current sunk by the pad to drive the output to Vol.
Table 23. Supply leakage
VDDE
VDD33
(Typ/Max)
Pad
C
VDD
(Typ/Max)
pad_fc
pad_msr
pad_ssr
D
90 A
—
3 nA / 4 A
1 nA / 30 A
—
—
—
—
—
PXD20 Microcontroller Data Sheet, Rev. 2
76
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
4.8.2
DC specification for CMOS090LP2fg library @ VDDE = 5.0 V
NOTE
These pad specifications are applicable for pads in the Analog segment Only. See the
“GPIO power bank supplies and functionality” table in the “Voltage Regulators and Power
Supplies” chapter of the reference manual for details.
Table 24. DC electrical specifications
Value
Symbol
C
Parameter
Condition
Unit SpecID
Min
Max
Vdd
Vdde
SR P Core supply voltage
SR P I/O supply voltage
—
—
—
1.08
4.5
1.32
5.5
V
V
V
V
D9.17
D9.18
D9.19
D9.20
Vdd33
Vih_hys
SR P I/O pre-driver supply voltage
3.0
3.6
SR P CMOS input buffer high
voltage
With hysteresis enabled 0.65 Vdde Vdde + 0.3
With hysteresis enabled Vss – 0.3 0.35 Vdde
With hysteresis disabled 0.55 Vdde Vdde + 0.3
Vil_hys
Vih
SR P CMOS input buffer low
voltage
V
V
V
D9.21
D9.22
D9.23
SR P CMOS input buffer high
voltage
Vil
SR P CMOS input buffer low
voltage
With hysteresis disabled
Vss – 0.3
0.40 Vdde
Vhys
SR T CMOS input buffer hysteresis
SR P Weak pullup current
—
0.1 Vdde
—
V
D9.24
D9.25
D9.26
D9.27
Pull_Ioh
Pull_Iol
Iinact_d
—
—
35
35
135
200
2.5
A
A
A
SR P Weak pulldown current
SR P Digital pad input leakage
current
Weak pull inactive
–2.5
Iinact_a
Voh
SR P Analog pad input leakage
current
Weak pull inactive
–150
0.8 Vdde
—
150
—
A
V
D9.28
D9.29
D9.30
D9.31
SR P Slew rate controlled output
high voltage
—
—
—
Vol
SR P Slew rate controlled output
low voltage
0.2 Vdde
—
V
Voh_ls
SR P Low swing output pad output
high voltage
2.64
V
Ioh_msr
Iol_msr
Ioh_ssr
Iol_ssr
SR C pad_msr_hv Ioh
SR C pad_msr_hv Iol
SR C pad_ssr_hv Ioh
SR C pad_ssr_hv Iol
—
11.6
17.7
6.0
40.7
68.2
21.3
36.3
40
mA
mA
mA
mA
mA
D9.32
D9.33
D9.34
D9.35
D9.36
—
—
—
9.2
Ioh_multv_h SR C pad_multv_hv Ioh
s
High swing mode
10
Ioh_multv_l SR C pad_multv_hv Ioh
s
Low swing mode
TBD
12
TBD
56
mA
mA
D9.37
D9.38
Iol_multv SR C pad_multv_hv Iol
High/low swing mode
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
77
Electrical characteristics
Table 24. DC electrical specifications (continued)
Value
Symbol
C
Parameter
Condition
Unit SpecID
Min
Max
Rtgate
SR D Pad_tgate_hv input
resistance
—
—
—
—
—
—
250
800
D9.39
D9.40
D9.41
D9.42
D9.43
D9.44
pupd_rm SR D pad_pupd_hv resistance
mismatch
—
0.1
130
65
5
75000
280
%
pupd_leak SR D pad_pupd_hv leakage
current
pA
k
k
k
pupd200k SR D pad_pupd_hv 200 k
resistance
pupd100k SR D pad_pupd_hv 100 k
140
resistance
pupd5k
SR D pad_pupd_hv 5 k
1.4
5.2
resistance
Table 25. DC electrical specifications
Condition
Value
Symbol
Parameter
Unit SpecID
Min
Max
Vdd
Vdde
SR Core supply voltage
SR I/O supply voltage
—
1.08
3.0
1.32
3.6
V
V
V
V
D9.45
D9.46
D9.47
D9.48
—
Vdd33
Vih_hys
SR I/O pre-driver supply voltage
—
3.0
3.6
SR CMOS input buffer high
voltage
With hysteresis enabled
0.65 Vdde Vdde + 0.3
Vss – 0.3 0.35 Vdde
0.55 Vdde Vdde + 0.3
Vil_hys
Vih
SR CMOS input buffer low
voltage
With hysteresis enabled
With hysteresis disabled
With hysteresis disabled
V
V
V
D9.49
D9.50
D9.51
SR CMOS input buffer high
voltage
Vil
SR CMOS input buffer low
voltage
Vss – 0.3
0.40 Vdde
Vhys
SR CMOS input buffer hysteresis
SR Weak pullup current
—
0.1 Vdde
—
70
95
2.5
V
D9.52
D9.53
D9.54
D9.55
Pull_Ioh
Pull_Iol
Iinact_d
—
—
15
15
A
A
A
SR Weak pulldown current
SR Digital pad input leakage
current
Weak pull inactive
–2.5
Iinact_a
Voh
SR Analog pad input leakage
current
Weak pull inactive
–150
0.8 Vdde
—
150
—
A
V
D9.56
D9.57
D9.58
SR Slew rate controlled output
high voltage
—
—
Vol
SR Slew rate controlled output
low voltage
0.2 Vdde
V
PXD20 Microcontroller Data Sheet, Rev. 2
78
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Unit SpecID
Table 25. DC electrical specifications (continued)
Value
Symbol
Parameter
Condition
Min
Max
Ioh_msr
SR pad_msr_hv Ioh
—
5.4
8.1
2.8
4.2
—
21
mA
mA
mA
mA
mA
D9.59
D9.60
D9.61
D9.62
D9.63
Iol_msr
Ioh_ssr
Iol_ssr
SR pad_msr_hv Iol
SR pad_ssr_hv Ioh
SR pad_ssr_hv Iol
—
38.6
11.2
20.6
TBD
—
—
Ioh_multv_h SR pad_multv_hv Ioh
s
High swing mode
Iol_multv SR pad_multv_hv Iol
High/low swing mode
—
—
TBD
mA
D9.64
D9.65
Rtgate
SR Pad_tgate_hv input
resistance
325
1250
pupd_rm SR pad_pupd_hv resistance
mismatch
—
—
—
—
—
—
0.1
130
65
5
75000
280
140
7.7
%
D9.66
D9.67
D9.68
D9.69
D9.70
pupd_leak SR pad_pupd_hv leakage
current
pA
k
k
k
pupd200k SR pad_pupd_hv 200 k
resistance
pupd100k SR pad_pupd_hv 100 k
resistance
pupd5k
SR pad_pupd_hv 5 k
1.7
resistance
Table 26. Supply leakage
VDD
VDDE
VDD33
Pad
Typ
Max
Typ
Max
Typ
Max
pad_msr_hv
pad ssr_hv
pad_i_hv
0.818 nA
83.7 nA
0.81 nA
118 nA
88.7 nA
30 nA
—
—
—
—
—
0
—
—
—
—
0
0.818 nA
83.7 nA
0.858 nA
0.307 nA
48.4 nA
88.2 pA
—
biasref_hv
—
0
—
0
core_v_det_hv
core_v_det_lp_hv
—
—
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
corner_esdpadcell_hv
corner_esdpadcell_id00_hv
corner_esdpadcell_id11_hv
corner_esdpadcell_lp_hv
esd_term_35_84_hv
pad_9v_hv
—
—
—
—
—
0
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
pad_ae_hv
—
—
—
—
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
79
Electrical characteristics
Table 26. Supply leakage (continued)
VDD VDDE
VDD33
Pad
Typ
Max
Typ
Max
Typ
Max
pad_esdspacer_hv
pad_tgate_hv
—
—
—
0
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
0
pad_vdd33_hv
pad_vdde_hv
pad_vddint3v_hv
pad_vddint_hv
pad_vss_hv
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
pad_vsse_hv
0
0
pad_vssint3v_hv
pad_vssint_hv
spcr_17_82_hv
spcr_35_84_hv
spcr_71_88_hv
spcr_143_38_hv
spcr_vdde_lvl_hv
0
0
0
0
—
—
—
—
—
—
—
—
—
—
Table 27. AVG IDDE specifications
Cell
Period (ns)
Load (pF)1
VDDE (V)
Drive/slew select
IDDE (mA)
pad_msr_hv2
24
62
50
50
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
11
01
00
00
11
01
00
00
14
5.3
1.1
3
317
425
37
50
200
50
pad_ssr_hv2
9
130
650
840
50
2.5
0.5
1.5
50
200
1
2
All loads are lumped loads.
Average current is for pad configured as output only. Use pad_i current for input.
PXD20 Microcontroller Data Sheet, Rev. 2
80
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
4.8.3
DC specification for CMOS090_ddr library @ VDDE = 3.3 V
Table 28. DC electrical specifications at 3.3 V VDDE
Value
Symbol
Parameter
Unit
SpecID
Min
Max
Vdd
SR Core supply voltage
1.08
1.08
1.32
1.47
V
D9.71
Vdde
Vdd33
Vref
Vtt
SR I/O supply voltage
SR I/O pre-driver supply voltage
SR Input reference voltage
SR Termination voltage
SR Input high voltage
3.0
3.6
V
V
V
V
V
V
V
V
D9.72
D9.73
D9.74
D9.75
D9.76
D9.77
D9.78
D9.79
3.0
3.6
1.3
1.7
Vref – 0.05
Vref + 0.20
—
Vref + 0.05
—
Vih
Vil
SR Input low voltage
Vref – 0.2
—
Voh
Vol
SR Output high voltage
SR Output low voltage
Vtt + 0.8
—
Vtt – 0.8
Table 29. Output drive current @ VDDE = 3.3 V (±10%)
Pad
C
Drive mode
Minimum Ioh (mA)
Minimum Iol (mA)
pad_st_acc
pad_st_dq
pad_st_clk
pad_st
P
P
P
P
P
P
111
111
111
111
111
111
–16
–16
–16
–16
–16
–16
16
16
16
16
16
16
pad_st_odt
pad_st_ck
4.8.4
DC specification for CMOS090_ddr library @ VDDE = 2.5 V
Table 30. DC electrical specifications at 2.5 V VDDE
Value
Symbol
C
Parameter
Unit SpecID
Min
Max
Vdd
SR
P
Core supply voltage
1.08
1.08
2.3
1.32
1.47
2.7
V
D9.80
Vdde
Vdd33
Vref
SR
SR
SR
SR
P
P
P
P
I/O supply voltage
V
V
V
V
D9.81
D9.82
D9.83
D9.84
I/O pre-driver supply voltage
Input reference voltage
Termination voltage
3.0
3.6
0.49 Vdde 0.51 Vdde
Vref – 0.04 Vref + 0.04
Vtt
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
81
Electrical characteristics
Table 30. DC electrical specifications at 2.5 V VDDE (continued)
Value
Symbol
C
Parameter
Unit SpecID
Min
Max
Vih
Vil
SR
SR
SR
SR
P
P
P
P
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Vref + 0.15
—
—
V
V
V
V
D9.85
D9.86
D9.87
D9.88
Vref – 0.15
—
Voh
Vol
Vtt + 0.81
—
Vtt – 0.81
Table 31. Output drive current @ VDDE = 2.5 V (±200mV)
Pad
C
Drive mode
Minimum Ioh (mA)
Minimum Iol (mA)
Libraries
pad_st_acc
pad_st_dq
pad_st_ck
P
P
P
011
011
011
–16.2
–16.2
–16.2
16.2
16.2
16.2
6MDDR
6MDDR
6MDDR
4.8.5
DC specification for CMOS090_ddr library @ VDDE = 1.8 V
Table 32. DC electrical specifications for 1.8 V VDDE
Value
Symbol
C
Parameter
Unit
SpecID
Min
Max
Vdd
SR
P
Core supply voltage
1.08
1.08
1.7
1.32
1.47
1.9
V
D9.89
Vdde
Vdd33
Vref
Vtt
SR
SR
SR
SR
SR
SR
SR
SR
P
P
P
P
P
P
P
P
I/O supply voltage
V
V
V
V
V
V
V
V
D9.90
D9.91
D9.92
D9.93
D9.94
D9.95
D9.96
D9.97
I/O pre-driver supply voltage
Input reference voltage
Termination voltage
Input high voltage
3.0
3.6
0.49 Vdde 0.51 Vdde
Vref – 0.04
Vref + 0.125
—
Vref + 0.04
—
Vih
Vil
Input low voltage
Vref – 0.125
—
Voh
Vol
Output high voltage
Output low voltage
Vtt + 0.81
—
Vtt – 0.81
Table 33. Output drive current @ VDDE = 1.8 V (±100mV)
Pad
pad_st_acc
Drive mode
Minimum Ioh (mA)
Minimum Iol (mA)
Libraries
P
000
001
010
110
–3.57
–7.84
–5.36
–13.4
3.57
7.84
5.36
13.4
6MDDR
PXD20 Microcontroller Data Sheet, Rev. 2
82
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Table 33. Output drive current @ VDDE = 1.8 V (±100mV) (continued)
Pad
Drive mode
Minimum Ioh (mA)
Minimum Iol (mA)
Libraries
pad_st_dq
P
000
001
010
110
000
001
010
110
–3.57
–7.84
–5.36
–13.4
–3.57
–7.84
–5.36
–13.4
3.57
7.84
5.36
13.4
3.57
7.84
5.36
13.4
6MDDR
pad_st_clk
P
6MDDR
Table 34. ODT DC electrical characteristics
Condition
Value
Symbol
C
Parameter
Unit SpecID
Min Typ Max
Rtt
SR
C
Effective impedance PXD20 supports only 150 ohm termination and 120 150 180
D9.98
value
that can be enabled by enabling any bit of the
termination control register (all of them are
OR’ed).
Table 35. core_v_det_odt and core_v_det33_odt specifications
VDDE
C
VDD
Vtrip max (V)
Vtrip min
Hysteresis min (V)
3.5
C
C
C
C
C
Rising
Falling
Rising
Falling
0.0
0.79
0.56
0.65
0.33
1.40
0.44
0
0.07
1.62
0.3
0
0.16
—
Rising
0.3
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
83
Electrical characteristics
4.9
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
Figure 9. Start-up reset requirements
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
Figure 10. Noise filtering on reset signal
PXD20 Microcontroller Data Sheet, Rev. 2
84
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Table 36. Reset electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit SpecID
Min
Typ
Max
VIH
VIL
SR P Input High Level CMOS
Schmitt Trigger
—
—
—
0.65 VDD
—
VDD + 0.4
V
V
V
V
D8.1
D8.2
D8.3
D8.4
SR P Input low Level CMOS
Schmitt Trigger
–0.4
0.1 VDD
—
—
—
—
0.35 VDD
—
VHYS CC3 D Input hysteresis CMOS
Schmitt Trigger
VOL CC4 P Output low level
Push Pull, IOL = 2mA,
VDD = 5.0V ± 10%, ipp_hve = 0
(recommended)
0.1 VDD
D
C
Push Pull, IOL = 1mA,
—
—
—
—
0.1 VDD
0.5
VDD = 5.0V ± 10%, ipp_hve = 15
Push Pull, IOL = 1mA,
VDD = 3.3V ± 10%, ipp_hve = 1
(recommended)
Ttr
CC4 T Output transition time output pin6 CL = 25pF,
—
—
—
—
—
—
—
—
—
—
—
—
10
20
40
12
25
40
ns
D8.5
MEDIUM configuration
VDD = 5.0V ± 10%, ipp_hve = 0
CL = 50pF,
VDD = 5.0V ± 10%, ipp_hve = 0
CL = 100pF,
VDD = 5.0V ± 10%, ipp_hve = 0
CL = 25pF,
VDD = 3.3V ± 10%, ipp_hve = 1
CL = 50pF,
VDD = 3.3V ± 10%, ipp_hve = 1
CL = 100pF,
VDD = 3.3V ± 10%, ipp_hve = 1
WFRST SR P RESET Input Filtered Pulse
—
—
—
—
400
10
—
—
—
70
—
—
ns
ns
µA
D8.6
D8.7
D8.8
WNFRST SR P RESET Input Not Filtered Pulse
|IWPU
|
CC4 P Weak pullup current absolute val-
ue
1
2
3
4
5
VDD = 3.3V ±10% / 5.0V ±10%, TA = –40 to +105oC, unless otherwise specified
All values need to be confirmed during device validation.
Data based on characterization results, not tested in production
Guaranteed by design simulation.
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the reference
manual).
6
CL calculation should include device and package capacitance (CPKG < 5pF).
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
85
Electrical characteristics
4.10 Fast external crystal oscillator (4–16 MHz) electrical
characteristics
This device implements the fast external oscillator (FXOSC) using a low power Loop Controlled Pierce Oscillator (LCP)
configuration.
Table 37. Fast external crystal oscillator electrical characteristics
Value
Symbol
Parameter
Conditions
Unit SpecID
Min
Typ
Max
fOSC
C
P
C
D
D
Crystal oscillator range
Startup current
Loop controlled Pierce
4.0
—
—
16
—
MHz
µA
O9.1
O9.2
O9.3
O9.4
O9.5
iOSC
—
100
tUPOSC
tCQOUT
fCMFA
Oscillator start-up time
Clock quality check time-out
Loop controlled Pierce
41
502
2.5
800
ms
s
—
—
0.45
200
—
Clock monitor failure assert
frequency
400
kHz
fEXT
tEXTL
tEXTH
D
D
D
External square wave input
frequency2
—
—
—
2.0
9.5
9.5
—
—
—
50
—
—
MHz
ns
O9.6
O9.7
O9.8
External square wave pulse
width low
External square wave pulse
width high
ns
tEXTR
tEXTF
D
D
D
P
External square wave rise time
External square wave fall time
Input capacitance
—
—
—
—
—
—
7
1
1
ns
ns
pF
V
O9.9
O9.10
O9.11
O9.12
—
CIN
EXTAL and XTAL pins
—
—
—
VIH,EXTAL
EXTAL pin input high voltage2
0.75
—
VDDPLL
T
P
T
—
—
—
—
—
VDDPLL
+ 0.3
VIL,EXTAL
EXTAL pin input low voltage2
EXTAL pin input hysteresis2
—
0.25
VDDPLL
V
O9.13
VSSPLL
– 0.3
—
VHYS,EXTAL
VPP,EXTAL
C
C
—
—
180
1.0
—
—
mV
V
O9.14
O9.15
EXTAL pin oscillation amplitude Loop controlled Pierce
1
2
fOSC = 4 MHz, C = 22 pF
Maximum value is for extreme cases using high Q, low frequency crystals
PXD20 Microcontroller Data Sheet, Rev. 2
86
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
4.11 Slow external crystal oscillator (32 KHz) electrical characteristics
The device provides a slow external oscillator/resonator driver (SXOSC). The 32 KHz oscillator operates at 32,768 Hz.
PC[15]
PC[15]
C
X
R
F
PC[14]
PC[14]
C
Y
DEVICE
DEVICE
Figure 11. Crystal oscillator and resonator connection scheme
NOTE
PC[14]/PC[15] must not be directly used to drive external circuits.
V
DD
V
DDMIN
V
XTAL
1/f
XOSCLP
V
XOSCLP
90%
10%
T
valid internal clock
XOSCLPSU
Figure 12. Slow external crystal oscillator electrical characteristics
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
87
Electrical characteristics
Table 38. Slow external crystal oscillator electrical characteristics
Value2
Typ
Symbol
C
Parameter
Conditions1
Unit SpecID
Min
Max
fXOSCLP SR C Oscillator frequency
VXOSCLP CC3 C Oscillation amplitude
32
—
40
kHz O10.1
VDDA=3.3V10%,
1.12
1.33
1.74
V
O10.2
VDDE_A=3.3V10%
VDDA=5.0V10%,
1.12
1.37
1.74
VDDE_A=5.0V10%
IXOSCLP CC3 D Oscillator consumption
—
—
—
—
—
—
5
2
µA
s
O10.3
O10.4
TXOSCLPS CC3 D Oscillator start-up time
U
VIH
SR C Input high level CMOS Oscillator bypass mode 0.65VDDA
—
—
VDDA+0.4
VDDE_A+0.4
V
V
O10.5
O10.6
Schmitt Trigger
0.65VDDE_A
VIL
SR C Input low level CMOS Oscillator bypass mode
Schmitt Trigger
VSS–0.4
0.35VDDA
0.35VDDE_A
1
2
3
VDD = 3.3 V ±10% / 5.0 V ±10%, TA = –40 to +105 °C, unless otherwise specified
All values need to be confirmed during device validation.
Granted by device validation
4.12 FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the fast
external oscillator driver.
Table 39. FMPLL electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit SpecID
Min
Typ
Max
120 MHz O11.1
52.5 O11.2
fPLLIN
SR T PLL reference clock3
—
4
47.5
15
—
—
—
—
—
—
PLLIN
SR T PLL reference clock duty cycle3
—
%
fPLLOUT CC4 T PLL output clock frequency
fCPU
CC4 T System clock frequency
—
2505 MHz O11.3
1256 MHz O11.4
—
—
TLOCK CC4 T PLL lock time
Stable oscillator (fPLLIN = 10 MHz)
—
100
509
µs O11.5
ps O11.6
TPKJIT CC4 T PLL jitter
fPLLOUT (PHI i.e. FMPLL O/P) =
15.625 MHz @ 10 MHz resonator
–509
TLTJIT CC4 T PLL long term jitter
fPLLIN = 10 MHz (resonator)
–2.4
—
—
—
2.4
ns O11.7
µA O11.8
IPLL
CC7 D Current Consumption (Normal TA = 25°C
Mode for Analog Supply)
500
1
2
3
VDDPLL = 1.2 V ±10%, TA = –40 to 105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
PLLIN clock retrieved directly from XOSCHS clock. Input characteristics are granted when oscillator is used in functional
mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN
.
PXD20 Microcontroller Data Sheet, Rev. 2
88
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
4
5
6
7
Data based on device simulation.
2x sys clock required for generation of DDR timing.
fCPU of 125 MHz can be achieved only at temperatures up to 105 °C with a maximum FM depth of 2%.
Data based on characterization results, not tested in production
4.13 Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a fast internal RC oscillator (FIRC). This is used as the default clock at the power-up of the device.
Table 40. Fast internal oscillator electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit SpecID
Min
Typ Max
fRCM
CC3 P RC oscillator high frequency
TA = 25 °C, trimmed
—
—
16
—
—
MHz O12.1
IRCMRUN CC3 D RC oscillator high frequency current in run- TA = 25 °C, trimmed
ning mode
200 µA O12.2
IRCMPWD CC3 D RC oscillator high frequency current in power
down mode
TA = 25 °C
—
—
—
10
+5
µA O12.3
O12.5
RCMVAR CC4 C RC oscillator variation in temperature and
supply with respect to fRC at TA = 55 °C in
high-frequency configuration
—
–5
%
1
2
3
4
VDD = 3.3 V ±10% / 5.0 V ±10%, TA = –40 to 105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
Guaranteed by device simulation, not tested in production
Guaranteed by device characterization, not tested in production
4.14 Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a slow internal RC oscillator (SIRC). This can be used as the reference clock for the RTC module.
Table 41. Slow internal RC oscillator electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit SpecID
Min
Typ Max
fRCL
IRCL
CC3 P RC oscillator low frequency
TA = 25 °C, trimmed
TA = 25 °C, trimmed
—
—
–2
128
—
—
5
kHz O13.1
CC3 D RC oscillator low frequency current
µA
%
O13.2
O13.3
RCLTRI CC3 C RC oscillator precision after trimming of TA = 25 °C
fRCL
—
+2
M
RCLVAR CC3 C RC oscillator variation in temperature and High frequency config- –10
—
+10
%
O13.4
3
supply with respect to fRC at TA = 55 °C in uration
high frequency configuration
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to +105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
2
3
Guaranteed by device simulation, not tested in production
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
89
Electrical characteristics
4.15 Flash memory electrical characteristics
Table 42. Program and erase specifications
Min
Value
Typical
Value1
Initial
Max2
Symbol
C
Parameter
Max3 Unit
SpecID
Tdwprogram
T16kpperase
T32kpperase
C Double Word (64 bits) Program Time4
C 16 KB Block Pre-program and Erase Time
C 32 KB Block Pre-program and Erase Time
—
—
—
—
22
500
600
1300
500
s
ms
ms
ms
D14.1
D14.2
D14.3
D14.4
5000
5000
7500
T128kpperase C 128 KB Block Pre-program and Erase Time
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2
3
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program & erase times occur after the specified number of program/erase cycles. These maximum values are
characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
Table 43. Flash module life
Value
Symbol
C
Parameter
Conditions
Unit SpecID
Min
Typ
P/E
C Number of program/erase cycles per block
for 16 KB, 48KB and 64KB blocks, across
full operating temperature range (Tj)
—
100,000
—
P/E
cycles
D14.5
D14.6
D14.8
P/E
C Number of program/erase cycles per block
for 128KB and 256KB blocks, across full
operating temperature range (Tj)
—
1, 000
100,000
P/E
cycles
Data
retention
C Minimum data retention at 85 °C average Blocks with 0 – 1,000 P/E
20
10
5
—
—
—
Years
Years
Years
ambient temperature1
cycles
Blocks with 1,001 –
10,000 P/E cycles
Blocks with 10,001 –
100,000 P/E cycles
1
Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.
PXD20 Microcontroller Data Sheet, Rev. 2
90
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
4.16 ADC parameters
The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter.
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = V
/ 1024
DDA
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
(LSB
V
)
ideal
in(A)
Offset Error OSE
Figure 13. ADC characteristics and error definitions
4.16.1 Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
91
Electrical characteristics
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being
S
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330 k is obtained (R
S
EQ
= 1 / (fc × C ), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
S
partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external circuit
S
S
F
L
SW
AD
must be designed to respect the Equation 5:
Eqn. 5
R + R + R + R
+ R
S
F
L
SW
AD
1
2
--------------------------------------------------------------------------
V
-- LSB
A
R
EQ
Equation 5 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (R
SW
and R ) can be neglected with respect to external resistances.
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
C
S
A
F
P1
P2
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 14. Input equivalent circuit (precise channels)
PXD20 Microcontroller Data Sheet, Rev. 2
92
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
EXTERNAL CIRCUIT
Filter
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Selection
Extended
Switch
Sampling
Source
R
Current Limiter
R
R
R
F
R
L
R
AD
SW2
S
SW1
C
S
C
V
C
F
C
C
P2
A
P1
P3
R
R
C
R
R
R
C
C
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions R
Sampling Switch Impedance
S
F
F
L
and R
)
SW2
SW
AD
P
SW1
Pin Capacitance (three contributions, C , C and C )
Sampling Capacitance
P1
P2
P3
S
Figure 15. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are
F
P1
P2
initially charged at the source voltage V (refer to the equivalent circuit reported in Figure 14): A charge sharing phenomenon
A
is installed when the sampling phase is started (A/D switch close).
Voltage Transient on CS
V
CS
V
A
V <0.5 LSB
V
A2
1
2
1 < (RSW + RAD) CS << TS
V
A1
2 = RL (CS + CP1 + CP2)
T
t
S
Figure 16. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C
S
•
P1
P2
S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,
P2
P1
P
P1
P2
P
S
and the time constant is
Eqn. 6
C C
P
S
--------------------
= R
+ R
1
SW
AD
C + C
P
S
Equation 6 can again be simplified considering only C as an additional worst condition. In reality, the transient is
S
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T
is always much longer than the internal time constant:
S
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
93
Electrical characteristics
Eqn. 7
R
+ R
C « T
1
SW
AD
S
S
The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance
P1
P2
S
A1
according to Equation 8:
Eqn. 8
V
C + C + C = V C + C
A1
S
P1
P2
A
P1
P2
•
A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance
F
R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality
L
P2
S
P1
would be faster), the time constant is:
Eqn. 9
R C + C + C
P1 P2
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time T , a constraints on R sizing is obtained:
S
L
Eqn. 10
10 = 10 R C + C + C T
P1 P2 S
2
L
S
Of course, R shall be sized also according to the current limitation constraints, in combination with R (source
L
S
impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V
F
F
P1 P2
S
A2
(at the end of the charge transfer transient) will be much higher than V . Equation 11 must be respected (charge
A1
balance assuming now C already charged at V ):
S
A1
Eqn. 11
V
C + C + C + C = V C + V C + C + C
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to
F
F
provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of
S
A
F F
the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.
S
Analog Source Bandwidth (V )
A
T
f
2 R C (Conversion Rate vs. Filter Pole)
F F
C
Noise
f (Anti-aliasing Filtering Condition)
F
0
2 f f (Nyquist)
0
C
f
0
f
Anti-Aliasing Filter (f = RC Filter pole)
Sampled Signal Spectrum (f = conversion Rate)
C
F
f
f
f
C
F
0
f
f
Figure 17. Spectral representation of input signal
PXD20 Microcontroller Data Sheet, Rev. 2
94
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),
0
F
according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater
C
0
than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T ,
C
C
S
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the
F
F
sampling time T , so the charge level on C cannot be modified by the analog signal source during the time in which the
S
S
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on C ; from the two charge balance equations above, it is simple to derive Equation 12 between the ideal and real sampled
S
voltage on C :
S
Eqn. 12
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A
P1
F
V
C
+ C + C + C
A2
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5V), assuming to accept a maximum error of
A
half a count, a constraint is evident on C value:
F
Eqn. 13
C
2048 C
F
S
4.16.2 ADC electrical characteristics
Table 44. ADC electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Min
Unit SpecID
Typ
Max
VSSA
SR D Voltage on VSSA (ADC
—
–0.1
—
0.1
V
V
V
D15.1
D15.2
D15.3
reference) pin with re-
3
spect to ground (VSS
)
VDDA
SR D Voltage on VDDA pin
(ADC reference) with re-
—
V
DDE_A – 0.
—
VDDE_A + 0.1
1
spect to ground (VSS
)
VAINx
fADC
SR D Analog input voltage4
—
—
—
VSSA – 0.1
6
—
—
—
—
VDDA + 0.1
SR D ADC analog frequency
32
MHz D15.4
tADC_PU SR D ADC power up delay
tADC_S CC5 T Sample time6
1.5
µs
µs
D15.5
D15.6
fADC = 32 MHz,
0.5
ADC_conf_sample_input=
17
f
ADC = 6 MHz,
—
—
21
—
ADC_conf_sample_input=
127
tADC_C CC5 T Conversion time7
fADC = 32 MHz,
0.625
µs
D15.7
ADC_conf_comp = 2
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
95
Electrical characteristics
Table 44. ADC electrical characteristics (continued)
Value2
Symbol
C
Parameter
Conditions1
Unit SpecID
Min
Typ
Max
CS
CC5 D ADC input sampling
capacitance
—
—
—
—
—
—
—
—
—
3
pF
pF
pF
pF
D15.8
D15.9
CP1
CP2
CP3
CC5 D ADC input pin
capacitance 1
—
—
—
—
—
—
—
—
—
3
1
CC5 D ADC input pin
capacitance 2
D15.10
D15.11
CC5 D ADC input pin
capacitance 3
—
1
RSW1 CC5 D Internal resistance of
analog source
—
3
k D15.12
k D15.13
k D15.14
mA D15.15
RSW2 CC5 D Internal resistance of
analog source
—
2
RAD
CC5 D Internal resistance of
analog source
—
0.1
10
IINJ
SR T Input current Injection
Current injection on one
ADC input, different from
the converted one
–10
INL
CC5 P Integral Non Linearity
No overload
–1.5
–1.0
—
—
—
1.5
1.0
—
—
3
LSB D15.16
LSB D15.17
LSB D15.18
LSB D15.19
LSB D15.21
DNL CC5 P Differential Non Linearity No overload
OFS CC5 T Offset error
GNE CC5 T Gain error
After offset cancellation
0.5
0.6
—
—
—
TUEX CC T Total Unadjusted Error for No overload
extended channel
–3
TUEP CC5 T Total Unadjusted Error for No overload
precise channels, input
–2
—
—
—
2
LSB D15.22
LSB
overload conditions on
adjacent channel
only pins
TUEX CC5 T Total Unadjusted Error for No overload
extended channel,
–3
—
—
—
3
LSB D15.23
LSB
overload conditions on
adjacent channel
—
1
2
3
4
VDDA = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to +105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSSA and VDDA limits, remaining on absolute maximum ratings, but the results of the conversion will be
clamped respectively to 0x000 or 0x3FF
5
6
Guaranteed by design
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance
of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time
tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend
on programming.
7
This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to
load the result’s register with the conversion result.
PXD20 Microcontroller Data Sheet, Rev. 2
96
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
4.17 AC specifications
4.17.1 AC specification for CMOS090LP2 library @ VDDE = 3.3 V
Table 45. Functional pad type AC specifications
Prop. delay (ns)
Drive/slew
rate select
Rise/fall edge (ns)
L>H / H>L1
Drive load
Name
C
(pF)
Min
Max
Min
Max
MSB, LSB
pad_ssr
C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4.5 / 4.5
8 / 8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.2 / 2.2
6 / 6
50
200
50
112
45 / 45
22 / 22
10
01
00
60 / 60
28 / 28
200
50
90 / 90
42 / 42
110 / 110
430 / 430
480 / 480
2.5 / 2.5
2.5 / 2.5
2.5 / 2.5
2.5 / 2.5
4.0 / 4.5
7.3 / 8.3
24 / 22
50 / 50
200
50
210 / 210
220 / 220
1.2 / 1.2
1.2 / 1.2
1.2 / 1.2
1.2 / 1.2
1.02 / 1.4
3.5 / 4.2
9.1 / 10.3
14 / 15
200
10
pad_fc
C
C
00
01
20
30
10
50
112
112
pad_msr
50
200
50
10
01
00
33 / 31
200
50
49 / 44
18 / 21
60 / 53
24 / 25
200
50
332 / 302
362 / 325
126 / 151
136 / 158
200
1
2
L>H signifies low-to-high propagation delay and H>L signifies high-to-low propagation delay.
Can be used on the tester.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
97
Electrical characteristics
4.17.2 AC specification for CMOS090LP2fg library @ VDDE = 5.0 V
Table 46. Functional pad type AC specifications
Prop. delay (ns)
L>H / H>L1
Drive/slew
rate select
Rise/fall edge (ns)
Drive load
(pF)
Name
C
Min
Max
Min
Max
MSB, LSB
pad_msr_hv2
C
4.6 / 3.7
13 / 10
12 / 12
32 / 32
2.2 / 2.2
9 / 9
5.3 / 5.9
22 / 22
50
113
200
N/A
104
01
12 / 13
23 / 23
69 / 71
95 / 90
7.3 / 5.7
24 / 19
28 / 34
52 / 59
5.6 / 6
11 / 14
34 / 35
44 / 51
4.4 / 4.3
17 / 15
N/A
12 / 15
28 / 31
70 / 74
96 / 96
10 / 11
40 / 42
50
200
50
152 / 165
205 / 220
19 / 18
00
200
50
pad_ssr_hv2
C
113
58 / 58
200
104
01
26 / 27
49 / 45
61 / 69
115 / 115
320 / 330
420 / 420
1.9 / 1.9
13 / 13
27 / 23
72 / 74
90 / 85
0.3 / 0.3
30 / 34
61 / 61
50
200
50
137 / 142
182 / 172
0.5 / 0.5
156 / 164
200 / 200
1.5 / 1.5
00
200
0.5
pad_i_hv
C
N/A
1
2
3
4
L>H signifies low-to-high propagation delay and H>L signifies high-to-low propagation delay.
For input buffer timing, look at pad_i_hv.
Can be used on the tester.
This drive select value is not supported. If selected, it will be approximately equal to 11.
4.17.3 AC specification for CMOS090LP2fg library @ VDDE = 3.3 V
Table 47. Functional pad AC type specifications
Prop. delay (ns)
L>H / H>L
Drive/slew
rate select
Rise/fall edge (ns)
Drive load
(pF)
Name
Min
Max
Min
Max
MSB, LSB
pad_msr_hv
5.8 / 4.4
16 / 13
18 / 17
46 / 49
2.7 / 2.1
11.2 / 8.6
N/A
7.6 / 8.5
30 / 34
50
11
200
10
01
14 / 16
27 / 27
37 / 45
69 / 82
6.5 / 6.7
15 / 13
38 / 38
53 / 46
15.5 / 19
38 / 43
50
200
50
83 / 86
200 / 210
270 / 285
86 / 86
00
113 / 109
120 / 120
200
PXD20 Microcontroller Data Sheet, Rev. 2
98
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Drive/slew
Table 47. Functional pad AC type specifications (continued)
Prop. delay (ns)
Rise/fall edge (ns)
Drive load
L>H / H>L
rate select
Name
(pF)
Min
Max
Min
Max
MSB, LSB
pad_ssr_hv
9.2 / 6.9
30 / 23
27 / 28
81 / 87
5.5 / 4.1
21 / 16
15 / 17
57 / 63
50
11
200
N/A
10
01
31 / 31
58 / 52
80 / 90
144 / 155
415 / 415
533 / 540
3 / 3
15.4 / 15.4
32 / 26
38 / 42
82 / 85
50
200
50
162 / 168
216 / 205
0.5 / 0.5
80 / 82
190 / 190
250 / 250
1.5 / 1.5
00
106 / 95
0.4 / 0.4
200
0.5
pad_i_hv
N/A
4.17.4 Pad AC specifications (3.3 V, PAD3V5V = 1)
1
Table 48. Pad AC specifications (3.3 V, PAD3V5V = 1)
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew
(mA/ns)
Load drive
(pF)
No.
Pad
Min
Typ Max Min
Typ Max Min
Typ Max Min
Typ Max
1
Slow
3
3
3
3
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40
40
40
40
15
15
15
15
6
4
6
—
—
—
—
—
—
—
—
—
—
—
—
—
40
50
75
100
12
25
40
70
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
2
0.01
0.01
0.01
0.01
2.5
2.5
2.5
2.5
3
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
25
50
10
14
2
2
2
100
200
25
2
2
2
3
4
Medium
40
20
13
7
7
4
7
50
8
7
100
200
25
14
1
7
Fast
72
55
40
25
—
40
40
40
40
—
6
1.5
3
7
3
50
6
12
18
7500
3
100
200
50
6
5
3
Pull Up/Down
(3.6 V max)
—
—
—
Parameter
Classification
D
C
C
C
n/a
1
2
Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition
Slope at rising/falling edge
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
99
Electrical characteristics
4.17.5 AC specification for CMOS090_ddr library @ VDDE = 3.3 V
Table 49. AC specifications at 3.3 V VDDE
Prop. delay (ns)
L>H / H>L
Drive/slew
rate select
Rise/fall edge (ns)
Drive load
(pF)
Name
C
C
C
C
Libraries
6MDDR
6MDDR
6MDDR
Min
Max
Min
Max
MSB, LSB
pad_st_acc
pad_st_dq
pad_st_clk
1.4/1.4
1.7/1.7
1.4/1.4
1.7/1.7
1.4/1.4
1.6/1.6
2.4/2.4
2.7/2.7
2.4/2.4
2.7/2.7
2.4/2.4
2.6/2.6
3.1/2.5
0.9/1.1
3.1/2.5
0.9/1.1
3.1/2.5
1.1/1.3
5.6/5.4
1.7/2.0
5.6/5.4
1.7/2.0
5.7/5.7
2.3/2.3
5
20
5
111
111
111
20
5
20
4.17.6 AC specification for CMOS090_ddr library @ VDDE = 2.5 V
Table 50. AC specifications at 2.5 V VDDE
Prop. delay (ns)
L>H / H>L
Drive/slew
rate select
Rise/fall edge (ns)
Drive load
(pF)
Name
C
C
C
C
Libraries
6MDDR
6MDDR
6MDDR
Min
Max
Min
Max
MSB, LSB
pad_st_acc
pad_st_dq
pad_st_clk
1.4/1.5
1.7/1.7
1.4/1.5
1.7/1.7
1.4/1.4
1.1/1.6
2.5/2.4
2.8/2.7
2.5/2.4
2.8/2.7
2.4/2.4
2.7/2.7
2.1/2.1
0.6/0.7
2.1/2.1
0.6/0.7
2.1/2.1
0.6/0.7
4.3/4.1
1.1/1.3
4.3/4.1
1.1/1.3
4.4/4.1
1.6/1.8
5
20
5
011
011
011
20
5
20
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
100
Freescale Semiconductor
Electrical characteristics
4.17.7 AC specification for CMOS090_ddr library @ VDDE = 1.8 V
Table 51. AC electrical specifications at 1.8 V VDD
Prop. delay (ns)
L>H / H>L
Drive/slew
rate select
Rise/fall edge (ns)
Drive load
(pF)
Name
C
Libraries
Min
Max
Min
Max
MSB, LSB
pad_st_acc
C
1.4/1.4
1.7/1.7
1.4/1.5
1.7/1.7
1.4/1.5
1.7/1.7
1.4/1.5
1.7/1.8
1.4/1.4
1.7/1.7
1.4/1.5
1.7/1.7
1.4/1.5
1.7/1.7
1.4/1.5
1.7/1.8
1.4/1.4
1.6/1.6
1.4/1.4
1.7/1.7
1.4/1.4
1.6/1.6
1.4/1.5
1.7/1.8
2.4/2.4
2.8/2.7
2.4/2.5
2.8/2.8
2.4/2.4
2.8/2.7
2.5/2.5
2.8/2.8
2.4/2.4
2.8/2.7
2.4/2.5
2.8/2.8
2.4/2.4
2.8/2.7
2.5/2.5
2.8/2.8
2.4/2.4
2.7/2.7
2.4/2.4
2.7/2.7
2.4/2.4
2.7/2.7
2.5/2.5
2.7/2.7
0.6/1.0
0.2/0.4
1.1/1.1
0.4/0.4
1.0/1.1
0.3/0.4
1.5/1.1
0.4/0.4
0.6/1.0
0.2/0.4
1.1/1.1
0.4/0.4
1.0/1.1
0.3/0.4
1.5/1.1
0.4/0.4
0.4/0.6
0.7/0.9
1.1/1.1
0.3/0.4
0.9/1.1
0.3/0.4
1.5/1.2
0.4/0.4
2.7/2.6
0.5/0.6
3.0/2.7
0.7/0.7
2.9/2.7
0.6/0.7
3.1/2.6
0.7/0.6
2.7/2.6
0.5/0.6
3.0/2.7
0.7/0.7
2.9/2.7
0.6/0.7
3.1/2.6
0.7/0.6
2.7/2.7
1.8/3.4
3.0/2.8
1.0/1.1
3.0/2.8
0.9/1.0
3.2/2.6
1.1/1.2
5
20
5
000
6MDDR
001
010
110
000
001
010
110
000
001
010
110
20
5
20
5
20
5
pad_st_dq
C
6MDDR
20
5
20
5
20
5
20
5
pad_st_clk
C
6MDDR
20
5
20
5
20
5
20
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
101
Electrical characteristics
4.18 AC timing
4.18.1 IEEE 1149.1 interface timing
1
Table 52. JTAG interface timing
Num
Symbol
tJCYC
C
Characteristic
Min
Max
Unit
SpecID
1
2
CC2 D TCK Cycle Time
100
40
—
5
—
60
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A1.1
A1.2
A1.3
A1.4
A1.5
A1.6
A1.7
A1.8
A1.9
A1.10
tJDC
CC2 D TCK Clock Pulse Width (Measured at VDD/2)
CC2 D TCK Rise and Fall Times (40% – 70%)
3
tTCKRISE
4
t
TMSS, tTDIS CC2 D TMS, TDI Data Setup Time
—
—
35
—
30
35
50
5
tTMSH, TDIH
tTDOV
tTDOI
tTDOHZ
tBSDV
t
CC2 D TMS, TDI Data Hold Time
25
—
0
6
CC2 D TCK Low to TDO Data Valid
CC2 D TCK Low to TDO Data Invalid
CC2 D TCK Low to TDO High Impedance
CC2 D TCK Falling Edge to Output Valid
7
8
—
—
—
9
10
tBSDVZ
CC2 D TCK Falling Edge to Output Valid out of High
Impedance
11
12
13
tBSDHZ
tBSDST
tBSDHT
CC2 D TCK Falling Edge to Output High Impedance
—
50
50
50
—
—
ns
ns
ns
A1.11
A1.12
A1.13
CC2 D Boundary Scan Input Valid to TCK Rising Edge
CC2 D TCK Rising Edge to Boundary Scan Input Invalid
1
2
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 3.0 V to 3.6 V, TA = –40 to 105 °C,
and CL = 50 pF with SRC = 0b01.
Parameter values guaranteed by design.
TCK
2
3
2
1
3
Figure 18. JTAG test clock input timing
PXD20 Microcontroller Data Sheet, Rev. 2
102
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 19. JTAG test access port timing
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
103
Electrical characteristics
TCK
9
11
Output
Signals
10
Output
Signals
12
13
Input
Signals
Figure 20. JTAG boundary scan timing
PXD20 Microcontroller Data Sheet, Rev. 2
104
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
4.18.2 Nexus debug interface
1
Table 53. Nexus debug port timing
Num
Symbol
tMCYC
C
Characteristic
Min
Max
Unit
SpecID
1
2
3
4
5
6
7
8
9
CC2 D MCKO Cycle Time
15
40
0.1
0.1
0.1
4
—
60
0.2
0.2
0.2
—
ns
%
A2.1
A2.2
A2.3
A2.4
A2.5
A2.6
A2.7
A2.8
A2.9
A2.10
A2.11
tMDC
tMDOV
tMSEOV
tEVTOV
tEVTIPW
tEVTOPW
tTCYC
CC2 D MCKO Duty Cycle
CC2 D MCKO Low to MDO Data Valid3
CC2 D MCKO Low to MSEO Data Valid3
CC2 D MCKO Low to EVTO Data Valid3
CC2 D EVTI Pulse Width
tMCYC
tMCYC
tMCYC
tTCYC
tMCYC
ns
CC2 D EVTO Pulse Width
1
—
CC2 D TCK Cycle Time4
100
40
25
5
—
tTDC
CC2 D TCK Duty Cycle
60
—
%
10 tNTDIS, NTMSS
t
CC2 D TDI, TMS Data Setup Time
CC2 D TDI, TMS Data Hold Time
ns
11
tNTDIH,
tNTMSH
—
ns
12
tJOV
CC2 D TCK Low to TDO Data Valid
0
35
ns
A2.12
1
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from
50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 3.0 V to 3.6 V, TA = –40 to 105 °C, and
CL = 50 pF (Cl = 30 pF on MCKO), with SRC = 0b10 for MCKO and 0b11 for others.
2
3
4
Parameter values guaranteed by design.
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
The system clock frequency needs to be three times faster that the TCK frequency.
Nexus Dual Data Rate is not supported. The timings are mentioned for dedicated pins on 416TEPBGA package. The max value
for #2, 3, and 4 above, are 0.3 of tMCYC for shared Nexus ports.
1
2
MCKO
3
4
5
MDO
MSEO
EVTO
Output Data Valid
Figure 21. Nexus output timing
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
105
Electrical characteristics
TCK
9
8
9
Figure 22. Nexus TCK timing
TCK
10
11
TMS, TDI
12
TDO
Figure 23. Nexus TDI, TMS, TDO timing
4.18.3 Interface to TFT LCD panels (DCU3 and DCULite)
Figure 24 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure
signals are shown with positive polarity. The sequence of events for active matrix interface timing is:
PXD20 Microcontroller Data Sheet, Rev. 2
106
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
•
PCLK latches data into the panel on its positive edge (when positive polarity is selected). In active
mode, PCLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on
the panel type.
•
•
•
HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.
VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted
onto the display. When disabled, the data is invalid and the trace is off.
VSYNC
LINE 1 LINE 2
LINE 3
LINE 4
LINE n-1 LINE n
HSYNC
HSYNC
DE
1
2
3
m-1
m
PCLK
LD[23:0]
1
Figure 24. TFT LCD interface timing overview
4.18.3.1 Interface to TFT LCD panels—pixel level timings
Figure 25 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive
polarity of the PCLK signal (meaning the data and sync signals change on the rising edge) and active-high
polarity of the HSYNC, VSYNC and DE signals. The user can select the polarity of the HSYNC and
VSYNC signals via the SYN_POL register, whether active-high or active-low. The default is active-high.
The DE signal is always active-high.
Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are
programmed via the DCU Clock Confide Register (DCCR) in the system clock module.
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H,
BP_H and FP_H parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V
parameters are programmed via the VSYN_PARA register.
1. In Figure 24, the “LD[23:0]” signal is “line data,” an aggregation of the DCU’s RGB signals—R[0:7], G[0:7] and B[0:7].
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
107
Electrical characteristics
Table 54. LCD interface timing parameters—horizontal and vertical
Num
Symbol
C
Characteristic
Value
Unit
SpecID
1
2
3
4
5
6
tPCP
CC1
CC1
CC1
CC1
CC1
CC1
D
D
D
D
D
D
Display pixel clock period
HSYNC pulse width
HSYNC back porch width
HSYNC front porch width
Screen width
31.25
ns
ns
ns
ns
ns
ns
A3.1
A3.2
A3.3
A3.4
A3.5
A3.6
tPWH
tBPH
tFPH
tSW
PW_H × tPCP
BP_H × tPCP
FP_H × tPCP
DELTA_X × tPCP
tHSP
HSYNC (line) period
(PW_H + BP_H + FP_H + DELTA_X )
× tPCP
7
tPWV
tBPV
tFPV
tSH
CC1
CC1
CC1
CC1
CC1
D
D
D
D
D
VSYNC pulse width
VSYNC back porch width
VSYNC front porch width
Screen height
PWV × tHSP
BP_V × tHSP
ns
ns
ns
ns
ns
A3.7
A3.8
8
—
—
—
FP_V × tHSP
A3.9
DELTA_Y × tHSP
A3.10
A3.11
tVSP
VSYNC (frame) period
(PW_V + BP_V + FP_V + DELTA_Y )
× tHSP
1
Parameter values guaranteed by design.
tHSP
tFPH
tPWH
tBPH
tSW
Start of line
PCLK
tPCP
Invalid Data
Invalid Data
2
3
1
DELTA_X
LD[23:0]
HSYNC
DE
Figure 25. Horizontal sync timing
PXD20 Microcontroller Data Sheet, Rev. 2
108
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
t
VSP
t
t
t
t
SH
FPV
BPV
PWV
Start of Frame
HSYNC
t
HCP
LD[23:0]
(Line Data)
2
DELTA_Y
1
Invalid Data
3
Invalid Data
HSYNC
DE
Figure 26. Vertical sync pulse
4.18.3.2 Interface to TFT LCD panels—access level
1,2,3,4
Table 55. LCD interface timing parameters
—Access Level
Min.
Value
Typical
Value
Max.
Value
Num
Symbol
C
Characteristic
PDI Clock Period
Unit
SpecID
1
2
tCKP CC5
tCHD CC5
tDSU CC5
tDHD CC5
tCSU CC5
tCHD CC5
D
D
D
D
D
D
D
D
D
D
D
31.25
40
6
—
—
—
—
—
—
—
—
—
—
—
—
60
—
—
—
—
6
ns
%
A3.12
A3.13
A3.14
A3.15
A3.16
A3.17
A3.18
A3.19
A3.20
A3.21
A3.22
Duty cycle
3
interface data setup time
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
PDI interface data access hold time
PDI interface control signal setup time
PDI interface control signal hold time
TFT interface data valid after pixel clock
TFT interface HSYNC valid after pixel clock
TFT interface VSYNC valid after pixel clock
TFT interface DE valid after pixel clock
1
5
3
6
1
7
—
—
—
—
—
CC5
CC5
CC5
CC5
CC5
—
—
—
—
2
8
5
9
5.5
5.6
—
10
11
TFT interface hold time for data and control
bits
12
—
CC5
D
Relative skew between the data bits
—
—
3.7
ns
A3.23
1
The characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data on –ve
edge.
2
3
4
5
Intrabit skew is less than 2 ns.
Load CL = 50 pf for frequency up to 20 MHz.
Load CL = 25 pf for display freq from 20 to 32 MHz.
Parameter values guaranteed by design.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
109
Electrical characteristics
tCHD tCSU
HSYNC
VSYNC
DDE
PCLK
tCKH
tCKL
tDSU tDHD
LD[23:0]
Figure 27. LCD Interface timing parameters—access level
4.18.4 RSDS interface to TFT LCD panels
Table 56. RSDS electrical characteristics
Value2
Symbol
C
Parameter
Conditions1
Unit SpecID
Min Typ Max
AVDD SR P Voltage on VSSE_A pin with respect
to ground (VSS
—
—
3.0
3.3
3.6
V
A4.1
A4.2
)
IDDTX SR P Current Consumption: RSDS Trans-
mitter — Single Cell
—
2.7
—
mA
IDDPD SR P Power Down Current
—
—
—
—
10
—
—
µA
µA
A4.3
A4.4
IDDBG SR P Current Consumption of Bandgap
and buffer
100
Fmax SR P Data Frequency
VOD SR P Differential Output Voltage
VOFF SR P Offset Voltage
—
—
—
0.5
—
—
—
—
—
60
200
1.2
500
3
85
400
1.5
—
MHz A4.5
RL = 100 Ohms
mV
V
A4.6
A4.7
A4.8
A4.9
VCM ±5%
tR / tF SR P Output Rise / Fall times
tXdelay SR P Tx Delay
20% to 80%, VOD=200mV, CL = 5pF
—
ps
ns
—
SR P Termination Resistance (external)
SR P Transmitter Settling time
SR D Transmitter Delay
5% variation
100
10
—
Ohms A4.10
After power down, high to low
Data in to Tx out
—
µs
ns
A4.11
A4.12
8
—
1
VDDA = 3.3 V ± 10% TA = –40 to 105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
2
PXD20 Microcontroller Data Sheet, Rev. 2
110
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Figure 28. TCON/RSDS timing diagram
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
111
Electrical characteristics
4.18.5 DRAM interface
DDR Interface specification from ‘MCD — 32 Bit Automotive MCU — CMOS090LP2’ I/O Pad
Specification Revision 1.5 — May14th 2008.
This device supports SDR, DDR1, DDR2 half and full strengths, as well as LPDDR half and full speeds.
Table 57 shows the SRE settings for the different modes.
Table 57. Pad mode configurations
ipp_sre[2:0]
Mode
000
001
010
011
100
101
110
111
1.8V LPDDR Half Speed
1.8V LPDDR Full Speed
1.8V DDR2 Half Strength
2.5V DDR1
Not supported
Not supported
1.8V DDR2 Full Strength
SDR
NOTE:
The specifications given in Table 58 are preliminary.
1 2 3
Table 58. LPDDR, DDR, and DDR2 (DDR2-250) SDRAM timing specifications
No.
Symbol
Parameter
Min
Max
Unit
1
1.1
2
F
CC Frequency of Operation (Clock Period)
CC Clock period
N/A
N/A
125
8
MHz
ns
tCK
VIX-AC CC MCK AC differential crosspoint voltage4
VDDE_DR × 0.5 – 0.1 VDDE_DR × 0.5 + 0.1
V
3
tCH
CC CK HIGH pulse width 4, 5
CC CK LOW pulse width 4, 5
0.47
0.47
0.53
0.53
150
N/A
TCK
tCK
ps
4
tCL
5
tDQSS CC Skew between MCK and DQS transitions5, 6
150
6
tOS(base) CC Address and control output setup time relative to MCK
rising edge5, 6
(tCK/2) – 1000
ps
7
tOH(base) CC Address and control output hold time relative to MCK
rising edge5, 6
(tCK/2) + 1000
N/A
ps
8
9
tDS1(base) CC DQ and DM output setup time relative to DQS5, 6
tDH1(base) CC DQ and DM output hold time relative to DQS5, 6
tDQSQ CC DQS-DQ skew for DQS and associated DQ inputs5
(tCK/4) – 750
(tCK/4) + 750
–(tCK/4) – 600
TBD
N/A
N/A
ps
ps
ps
ps
10
(tCK/4) – 600
TBD
11 tDQSEN CC DQS window start position related to CAS read
command4, 5, 6, 7, 8
1
2
3
At recommended operating conditions with VDDE_DR of ±5%.
VDDE_DR value is 1.8 for DDR2 mode, 2.5 V for DDR1 mode, and 1.8 V for LPDDR mode.
CZ at –40, 140, 25 oC.
PXD20 Microcontroller Data Sheet, Rev. 2
112
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
4
5
6
7
8
Measured with clock pin loaded with differential 100 ohm termination resistor.
All transitions measured at mid-supply (VDDE_DR/2).
Measured with all outputs except the clock loaded with 50 ohm termination resistor to VDDE_DR/2.
In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.
Window position is given for tDQSEN = 2.0 tCK. For other values of tDQSEN, window position is shifted accordingly.
4.18.5.1 2.5V DDR1
Table 59. SSTL_2 Class II 2.5V DDR DC specifications
Symbol
C
Parameter
Condition
Min
Nom
Max
Units
Notes
SpecID
Vddet
Vdd
P
P
P
I/O Supply Voltage
—
—
—
2.30
1.08
1.13
2.50
1.20
1.25
2.70
1.32
1.38
V
V
V
JESD8-9B
—
A5.1
A5.2
A5.3
Core Supply Voltage
Vref(dc)
Input Reference
Voltage
JESD8-9B
Vtt
P
C
C
C
C
P
Termination Voltage
DC Input Logic High
DC Input Logic Low
AC Input Logic High
AC Input Logic Low
—
—
—
—
—
—
Vref – 0.04
Vref + 0.15
–0.3
vref
—
Vref + 0.04
vddet + 0.3
Vref – 0.15
—
V
V
JESD8-9B
JESD8-9B
JESD8-9B
JESD8-9B
JESD8-9B
—
A5.4
A5.5
A5.6
A5.7
A5.8
A5.9
Vih(dc)
Vil(dc)
Vih(ac)
Vil(ac)
Iin
—
V
Vref + 0.31
—
—
V
—
Vref – 0.31
±10
V
Pad input Leakage
Current
—
—
µA
Voh
Vol
C
C
C
C
Output High Voltage
Level
—
—
vddet – 0.35
—
—
—
—
—
—
0.35
—
V
V
—
—
A5.10
A5.11
Output Low Voltage
Level
Ioh(dc)
Iol(dc)
Output min source dc Vout = Voh
current
–16.2
16.2
mA vddet = 2.3 V A5.12
Voh = 1.95 V
Output min sink dc
current
Vout = Vol
—
mA vddet = 2.3 V A5.13
Vol = 0.35 V
The SSTL_2 differential input switch point is at Vref = 0.50 × Vddet.
Note that the JEDEC SSTL_2 specifications (JESD8-9B) for an SSTL interface for class II operation supersedes any
specification in this document.
The SSTL_2 Class II output with ipp_sre[2:0] set to enabling SSTL_2 2.5V DDR1 mode, at the destination, have a rise/fall time
(10–90%) between 1 ns and 2 ns over process, voltage, and temperature driving a 70 ohm transmission line with 0.167 ns td
terminated at the destination with 70 ohms to Vtt (0.5 × vddet) with 4.0 pf, representing the DDR input capacitance.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
113
Electrical characteristics
Vtt
70 ohms
4pF
Z =70 td= 0.167ns
0
ipp_do
pad_st/pad_st_odt
PAD
Figure 29. SSTL_2 Class II test load
4.18.5.2 1.8V DDR2
Table 60. SSTL_18 Class II 1.8V DDR2 DC specifications
Symbol
C
Parameter
Condition
Min
Nom
Max
Units
Notes
SpecID
Vddet
Vdd
P
P
P
I/O Supply Voltage
—
—
—
1.7
1.08
0.833
1.8
1.2
0.9
1.9
1.32
V
V
V
JESD8-15A
—
A5.14
A5.15
A5.16
Core Supply Voltage
Vref(dc)
Input Reference
Voltage
1.0869
JESD8-15A
Vtt
P
C
C
C
C
P
Termination Voltage
DC Input Logic High
DC Input Logic Low
AC Input Logic High
AC Input Logic Low
—
—
—
—
—
—
Vref – 0.04
Vref + 0.125
–0.3
Vref
—
Vref + 0.04
vddet + 0.3
Vref – 0.125
—
V
V
JESD8-15A
JESD8-15A
JESD8-15A
JESD8-15A
JESD8-15A
—
A5.17
A5.18
A5.19
A5.20
A5.21
A5.22
Vih(dc)
Vil(dc)
Vih(ac)
Vil(ac)
Iin
—
V
Vref + 0.25
—
—
V
—
Vref – 0.25
±10
V
Pad input Leakage
Current
—
—
µA
Voh
Vol
C
C
Output High Voltage
Level
—
—
vddet – 0.28
—
—
—
—
—
0.28
—
V
V
—
—
A5.23
A5.24
A5.25
Output Low Voltage
Level
Ioh(dc) C Output min source dc Vout = Voh
current
–13.4
mA
JESD8-15A
vddet = 1.7 V
Voh = 1.42 V
Iol(dc)
C
Output min sink dc Vout = Vol
current
13.4
—
—
mA
JESD8-15A
vddet = 1.7 V
Vol = 0.28 V
A5.26
The SSTL_18 differential input switch point is at Vref = 0.50 × Vddet.
Note that the Jedec SSTL_18 specifications (JESD8-15a) for an SSTL interface for class II operation supersedes any
specification in this document.
The SSTL_18 Class II output with ipp_sre[2:0] set to enabling sstl_2 1.8V DDR2 mode, at the destination, have a rise/fall time
(10–90%) between 0.4 ns and 1.0 ns over process, voltage, and temperature driving a 70 ohm transmission line with 0.167 ns
PXD20 Microcontroller Data Sheet, Rev. 2
114
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
td terminated at the destination with 70 ohms to Vtt (0.5 × Vddet) with 4.0 pf, representing the DDR2 input capacitance. See
Figure 30 (SSTL_18 Class II test load).
Vtt
70
Z =70 td= 0.167ns
0
ipp_do
pad_st/pad_st_odt
4pF
PAD
Figure 30. SSTL_18 Class II test load
Table 61. 1.8V LPDDR DC specifications
4.18.5.3 1.8V LPDDR
Symbol
C
Parameter
Condition
Min
Nom
Max
Units
Notes
SpecID
vddet
vdd
P I/O Supply Voltage
P Core Supply Voltage
—
—
1.7
1.8
1.2
1.9
V
V
JESD79-4
—
A5.27
A5.28
A5.29
A5.30
A5.31
A5.32
A5.33
A5.34
A5.35
1.08
1.32
Data Inputs (DQ, DM, DQS)
Vih(dc) C DC Input Logic High
—
—
—
—
vddet × 0.7
–0.3
—
—
—
—
vddet+0.3
vddet × 0.3
vddet + 0.3
vddet × 0.2
V
V
V
V
JESD79-4
JESD79-4
JESD79-4
JESD79-4
Vil(dc)
Vih(ac) C AC Input Logic High
Vil(ac) C AC Input Logic low
Data Outputs (DQ, DQS)
C DC Input Logic Low
vddet × 0.8
–0.3
Voh
C Output High Voltage Ioh = –0.1mA vddet × 0.9
Level
—
—
—
V
V
JESD79-4
JESD79-4
Vol
C Output Low Voltage
Level
Iol = 0.1mA
—
vddet × 0.1
A5.36
Note that the final JEDEC LPDDR SDRAM specifications (JESD79-4) for LPDDR operation supersedes any specification in
this document.
The SSTL_18 output with ipp_sre[2:0] set to enabling 1.8V LPDDR mode, at the destination, have a rise/fall time (10–90%)
between 0.4 ns and 1.0 ns over process, voltage, and temperature driving a 70 ohm transmission line with 0.167 ns td terminated
at the destination with 70 ohms to Vtt (0.5 × vddet) with 4.0 pf, representing the DDR input capacitance. See Figure 30
(SSTL_18 Class II test load).
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
115
Electrical characteristics
4.18.6 Video Input Unit timing
Clock
fPIX_CLK
tDHD
tDSU
Data
Figure 31. VIU2 timing diagram
Table 62. VIU2 timing parameters
Parameter C
fPIX_CK
tDSU
Description
Min
Typ
Max
Unit
SpecID
D VIU2 pixel clock frequency
D VIU2 data setup time
D VIU2 data hold time
—
4
—
—
—
64
—
—
MHz
ns
A6.1
A6.2
A6.3
tDHD
1
ns
4.18.7 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Timing
Table 63. IRQ and NMI timing
Min.
Value
Max.
Value
Num
Symbol
C
Characteristic
Unit
SpecID
1
2
3
tIPWL
tIPWH
tICYC
CC1 D IRQ/NMI Pulse Width Low
CC1 D IRQ/NMI Pulse Width High
CC1 D IRQ/NMI Edge to Edge Time2
200
200
400
—
—
—
ns
ns
ns
A7.1
A7.2
A7.3
1
2
Parameter values guaranteed by design.
Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
1,2
1,2
3
Figure 32. IRQ and NMI timing
PXD20 Microcontroller Data Sheet, Rev. 2
116
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
4.18.8 eMIOS timing
1
Table 64. eMIOS timing
Min.
Max.
value
Num
Symbol
C
Characteristic
Unit
SpecID
value2
1
2
tMIPW
tMOPW
CC3 D eMIOS Input Pulse Width
CC3 D eMIOS Output Pulse Width
4
1
—
—
tCYC
tCYC
A8.1
A8.2
1
2
3
eMIOS timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = –40 to 105 °C, and
CL = 50 pF with SRC = 0b00.
There is no limitation on the peripheral for setting the minimum pulse width, the actual width is restricted by the pad delays.
Refer to the pad specification section for the details.
Parameter values guaranteed by design.
4.18.9 FlexCAN timing
The CAN functions are available as TX pins at normal I/O pads and as RX pins at the always on domain.
There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup if configured.
1
Table 65. FlexCAN timing
Max.
value
Num
Symbol
tCANOV
tCANSU
C
Characteristic
Min. value
Unit SpecID
1
CC2 D CTNX Output Valid after CLKOUT Rising Edge (Output
Delay)
CC2 D CNRX Input Valid to CLKOUT Rising Edge (Setup
—
22.48
ns
ns
A10.1
A10.2
2
—
12.46
Time)
1
2
FlexCAN timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = –40 to 105 °C, and CL
= 50 pF with SRC = 0b00.
Parameter values guaranteed by design.
4.18.10 Deserial Serial Peripheral Interface (DSPI)
1
Table 66. DSPI timing
Num
Symbol
C
Characteristic
Min
Max
Unit
SpecID
1
2
3
4
5
tSCK
tCSC
tASC
tSDC
tA
CC2 D SCK Cycle TIme3,4
CC2 D PCS to SCK Delay6
CC2 D After SCK Delay7
CC2 D SCK Duty Cycle
CC2 D Slave Access Time
605
—
ns
ns
ns
ns
ns
A11.1
A11.2
A11.3
A11.4
A11.5
—
—
20
tSCK/2 – 2ns
—
—
tSCK/2 + 2ns
25
(PCSx active to SOUT driven)
6
tDIS
CC2 D Slave SOUT Disable Time
—
25
ns
A11.6
(PCSx inactive to SOUT High-Z or invalid)
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
117
Electrical characteristics
1
Table 66. DSPI timing (continued)
Num
Symbol
tSUI
C
Characteristic
Min
Max
Unit
SpecID
7
CC2 D Data Setup Time for Inputs
Master (MTFE = 0)
A11.7
20
10
5
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)8
Master (MTFE = 1, CPHA = 1)
35
8
9
tHI
CC2 D Data Hold Time for Inputs
Master (MTFE = 0)
A11.8
A11.9
–4
10
26
–4
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)8
Master (MTFE = 1, CPHA = 1)
tSUO
CC2 D Data Valid (after SCK edge)
Master (MTFE = 0)
—
—
—
—
15
20
30
15
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
10
tHO
CC2 D Data Hold Time for Outputs
Master (MTFE = 0)
A11.10
–15
5.5
0
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–15
1
2
3
4
5
6
7
8
DSPI timing specified at VDDE_x = 3.0 V to 3.6 V, TA = –40 to 105 °C, and CL = 50 pF with SRC = 0b10.
Parameter values guaranteed by design.
The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate.
The actual minimum SCK Cycle Time is limited by pad performance.
Maximum clock possible is System clock/2.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK=2 & CSSCK = 2
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
This delay value is corresponding to SMPL_PT=00b which is bit field 9 and 8 of DSPI_MCR register.
PXD20 Microcontroller Data Sheet, Rev. 2
118
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
8
7
Last Data
SIN
First Data
Data
Data
10
9
First Data
Last Data
SOUT
Figure 33. DSPI classic SPI timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
8
SCK Output
(CPOL=1)
7
Data
Data
First Data
Last Data
SIN
10
9
SOUT
Last Data
First Data
Figure 34. DSPI classic SPI timing — Master, CPHA = 1
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
119
Electrical characteristics
3
2
PCSx
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
9
10
Data
6
First Data
Last Data
SOUT
7
8
Data
Last Data
First Data
SIN
Figure 35. DSPI classic SPI timing — Slave, CPHA = 0
PCSx
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
9
5
6
10
Last Data
Data
Data
SOUT
SIN
First Data
8
7
Last Data
First Data
Figure 36. DSPI classic SPI timing — Slave, CPHA = 1
PXD20 Microcontroller Data Sheet, Rev. 2
120
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
7
8
SIN
First Data
Last Data
Last Data
Data
10
9
SOUT
First Data
Data
Figure 37. DSPI modified transfer format timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
8
7
SIN
Last Data
First Data
Data
10
Data
9
First Data
Last Data
SOUT
Figure 38. DSPI modified transfer format timing — Master, CPHA = 1
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
121
Electrical characteristics
3
2
PCSx
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
10
9
6
5
First Data
7
Data
Data
Last Data
8
SOUT
Last Data
First Data
SIN
Figure 39. DSPI modified transfer format timing — Slave, CPHA = 0
PCSx
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
9
5
6
10
Last Data
First Data
8
Data
Data
SOUT
SIN
7
First Data
Last Data
Figure 40. DSPI modified transfer format timing — Slave, CPHA = 1
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
122
Freescale Semiconductor
Electrical characteristics
4.18.11 I2C timing
2
Table 67. I C input timing specifications—SCL and SDA
Num
Symbol
C
Characteristic Min. Value Max. Value
Unit
SpecID
1
2
4
6
7
8
—
—
—
—
—
—
CC1 D Start condition hold time
CC1 D Clock low time
CC1 D Data hold time
CC1 D Clock high time
CC1 D Data setup time
2
8
—
—
—
—
—
—
IP-Bus Cycle2
IP-Bus Cycle2
ns
A12.1
A12.2
A12.3
A12.4
A12.5
A12.6
0.0
4
IP-Bus Cycle2
0.0
2
ns
CC1 D Start condition setup time (for repeated
start condition only)
IP-Bus Cycle2
9
—
CC1 D Stop condition setup time
2
—
IP-Bus Cycle2
A12.7
1
2
Parameter values guaranteed by design.
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
2
Table 68. I C Output timing specifications—SCL and SDA
Num
Symbol
C
Characteristic
Min. Value
Max. Value
Unit
SpecID
11
21
34
41
51
61
71
81
—
—
—
—
—
—
—
—
CC2 D Start condition hold time
CC2 D Clock low time
6
10
—
7
—
—
IP-Bus Cycle3
IP-Bus Cycle2
ns
A12.8
A12.9
CC2 D SCL/SDA rise time
CC2 D Data hold time
99.6
—
A12.10
A12.11
A12.12
A12.13
A12.14
A12.15
IP-Bus Cycle2
CC2 D SCL/SDA fall time
CC2 D Clock high time
CC2 D Data setup time
—
10
2
99.5
—
ns
IP-Bus Cycle2
IP-Bus Cycle2
IP-Bus Cycle2
—
CC2 D Start condition setup time (for repeated
start condition only)
20
—
91
—
CC2 D Stop condition setup time
10
—
IP-Bus Cycle2
A12.16
1
Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed. The
I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is
affected by the prescale and division values programmed in IFDR.
2
3
4
Parameter values guaranteed by design.
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA
takes to reach a high level depends on external signal capacitance and pullup resistor values.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
123
Electrical characteristics
6
2
5
SCL
3
8
4
7
9
1
SDA
2
Figure 41. I C input/output timing
4.18.12 QuadSPI timing
The following notes apply to Table 69 and Table 70:
•
All data is based on a negative edge data launch from PXD20 and a positive edge data capture, as shown in the timing
diagrams in this section.
•
The supply conditions, over a temperature range of –45 C to 125 C/150 C, are as follows:
— I/O voltage: 3.0 V, Core supply: 1.2 V
— I/O voltage: 3.3 V, Core supply: 1.2 V
— I/O voltage: 3.6 V, Core supply: 1.2 V
•
•
•
•
The actual frequency at which the device can work will be a combination of this data and the clock pad profile.
All measurements are considering 70% of VDDE levels for clock pin and 50% of VDDE level for data pins.
Timings assume a setting of 0x0000_000x for QSPI_SMPR register (see the reference manual for details).
A negative value of hold is an indication of pad delay on the clock pad (delay b/w actual edge capturing data in the
device vs. edge appearing at the pin).
•
•
Measurements are with a load of 50 pF on output pins
The clock profile is measured at 30% to 70% levels of VDDE.
Table 69. QuadSPI timing specifications, maximum temperature 125 C
Value
Symbol
C
Parameter
Unit SpecID
Min
Typ
Max
Tcq
Ts
Th
tr
CC T Clock to Q delay
3.8
7.6
–13
0.5
0.8
5.3
9
12.1
13.2
–7.5
1.0
ns
ns
ns
ns
ns
A13.1
A13.2
A13.3
A13.4
A13.5
CC T Setup time for incoming data
CC T Hold time requirement for incoming data
CC T Clock pad rise time
–8.5
0.7
0.8
tf
CC T Clock pad fall time
1.2
The numbers in Figure 42 and Figure 43 correspond to events as described in Table 70.
PXD20 Microcontroller Data Sheet, Rev. 2
124
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Table 70. QuadSPI timing events
Event
Number
1
2
3
4
5
6
7
8
Last address out
Address captured at flash memory
Data out from flash memory
Ideal data capture edge
Delayed data capture edge with QSPI_SMPR=0x0000_000X
Delayed data capture edge with QSPI_SMPR=0x0000_002X
Delayed data capture edge with QSPI_SMPR=0x0000_004X
Delayed data capture edge with QSPI_SMPR=0x0000_006X
1
tCQ
SCK
DO
1. Last address out
Figure 42. QuadSPI output timing
1
tCQ
2
3
4
5
6
7
8
SCK
DO
DI
tS
tH
1. Last address out
2. Address captured at flash
3. Data out from flash
4. Ideal data capture edge
5. Delayed data capture edge with QSPI_SMPR=0x0000_000x
6. Delayed data capture edge with QSPI_SMPR=0x0000_002x
7. Delayed data capture edge with QSPI_SMPR=0x0000_004x
8. Delayed data capture edge with QSPI_SMPR=0x0000_006x
Figure 43. QuadSPI input timing
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
125
Electrical characteristics
tR
tF
70%
VDDE
30%
SCK
Figure 44. QuadSPI clock profile
4.18.13 TCON/RSDS timing
The following notes apply to Table 71:
•
•
•
Measurement condition: Vdde/Vdd33 = 3.3 V ± 10%, Vdd = 1.2 V ± 10%, Vss/Vsse = 0 V, T = –40 to 105°C
Termination: 100 ± 5%
VREFH_RSDS terminations of 47 F
Table 71. TCON/RSDS timing
Value
Symbol
C
Parameter
Condition
Unit SpecID
Min
Typ
Max
VOD
VOS
CC C Differential output voltage RSDS mode
391
—
—
471
1.4
mV
V
A14.1
A14.2
CC C Common mode voltage
100 termination between
1.17
Pad_p and Pad_n
Transition from 20% to 80%
Transition from 20% to 80%
—
tr
tf
CC C Rise time
CC C Fall time
606
607
—
—
—
844
842
—
ps
ps
ns
A14.3
A14.4
A14.5
tplh
CC D Propagation delay, low to
high
2.65
tphl
CC D Propagation delay, high to
low
—
—
2.47
—
ns
A14.6
tdz
CC D Start-up time
—
—
—
200
—
—
—
s
A14.7
A14.8
tskew1 2 3 CC C Skew between different
RSDS lines
Max and min skew between
clock and data pads
ps
1
2
3
There are eight programmable bits to provide 256 different skew numbers with various combinations of these bits.
Default value of all the eight skew options are all “1”.
All “0” combination of eight bits is not valid.
PXD20 Microcontroller Data Sheet, Rev. 2
126
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical characteristics
Figure 45. Rise/fall transition, part 1
Figure 46. Rise/fall transition, part 2
TR
TF
80%
20%
+VOD
pad_p - pad_n
0V Differential
–VOD
Figure 47. Illustration of tr, tf, and V
OD
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
127
Package mechanical data
5
6
Package mechanical data
Ordering information
M PX
D 20 20 V LT 125 R
Qualification status
Brand
Family
Class
Flash memory size
Temperature range
Package identifier
Operating frequency
Tape and reel indicator
Qualification status
Family
Flash Memory Size
D = Display Graphics
N = Connectivity/Network
R = Performance/Real Time Control
S = Safety
05 = 512 KB
10 = 1 MB
P = Pre-qualification (engineering samples)
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Temperature range
Package identifier
Operating frequency
Tape and reel status
V = –40 °C to 105 °C
(ambient)
LU = 176 LQFP
LT = 208 LQFP
VU = 416 PBGA
80 = 80 MHz
120 = 120 MHz
R = Tape and reel
(blank) = Trays
Note: Not all options are available on all devices. See Table 72 for more information.
Figure 48. PXD20 orderable part number description
Table 72. PXD20 orderable part number summary
Speed
(MHz)
Part number
Flash/SRAM
Package
MPXD2020VLU125
MPXD2020VVU125
MPXD2020VLT125
2 MB / 64 KB
2 MB / 64 KB
2 MB / 64 KB
176 LQFP (24 mm x 24 mm)
416 PBGA (27 mm x 27 mm)
208 LQFP (28 mm x 28 mm)
125
125
125
PXD20 Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
128
Freescale Semiconductor
Revision history
7
Revision history
Table 73. Revision history
Description
Revision
Date
1
2
30 Sep 2011
27 Apr 2012
Initial release.
Editorial updates and improvements throughout the document.
In Figure 4 (416 TEPBGA pinout), corrected pin P25 to VSS.
In Section 3, System design information, added Figure 6 (Power-up sequencing) and
Figure 7 (Power-down sequencing).
In Table 10 (Recommended operating conditions (3.3 V)), changed maximum Tj from
150 oC to 140 oC.
In Table 11 (Recommended operating conditions (5.0 V)), changed maximum Tj from
150 oC to 140 oC.
In Table 16 (Voltage regulator electrical characteristics):
— Changed maximum Tj from 150 oC to 140 oC.
— Changed VDD12 post-trimming minimum value from 1.270 V to 1.26 V and
maximum value from 1.280 V to 1.29 V.
— Removed footnote: “All values in this table are PRELIMINARY.”
In Section 4.7.1, Voltage regulator electrical characteristics. added Table 17
(Low-power voltage regulator electrical characteristics) and Table 18 (Ultra
low-power voltage regulator electrical characteristics).
In Table 19 (Low voltage monitor electrical characteristics), updated the following
values:
— VLVDHV3H maximum from 2.8 V to 2.9 V
— VLVDHV3L minimum from 2.7 V to 2.5 V
— VLVDHV5H maximum from 4.37 V to 4.4 V
— VLVDHV5L minimum from 4.2 V to 3.9 V
In Table 20 (DC electrical characteristics):
— Updated IDDRUN typical values for Dual Display Drive from 235 to 275 mA; for
Single Display Drive from 306 to 240 mA.
— Updated typical IDDHALT current at 25 oC from 12.67 mA to 17.5 mA.
— Updated typical IDDHALT current at 105 oC from 33.1 mA to 35 mA.
— Updated maximum IDDHALT current at 25 oC from 18.26 mA to 21.5 mA.
— Updated maximum IDDHALT current at 105 oC from 36.41 mA to 43.5 mA.
— In IDDHALT specification, changed TB = 105 oC to TA = 105 oC.
In Table 40 (Fast internal oscillator electrical characteristics), removed RCMTRIM
specification.
In Table 41 (Slow internal RC oscillator electrical characteristics), removed
RCMTRIM specification.
In Table 44 (ADC electrical characteristics), added offset error value of 0.5 typical, and
gain error value of 0.6 typical. Removed minimum and maximum values for both
specifications.
In Section 4.18.5, DRAM interface:
— Added Table 58 (LPDDR, DDR, and DDR2 (DDR2-250) SDRAM timing
specifications).
— Removed Table 56 (AC Specs for SDR mode (VDDE_DR = 3.3 V)), Table 57 (AC
Specs for DDR2 mode (VDDE_DR = 1.8 V)), Table 58 (AC Specs for DDR1 mode
(VDDE_DR = 2.5 V)), and Table 59 (AC Specs for LPMDDR mode (VDDE_DR = 1.8
V)).
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
129
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Document Number: PXD20
Rev. 2
04/2012
Preliminary—Subject to Change Without Notice
相关型号:
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32-bit Power Architecture® Dual Core Microcontrollers for Industrial Networking
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