TBD_技术文档

Freescale Semiconductor

Data Sheet: Product Preview

Document Number: MSC8144E

Rev. 6, 12/2007

MSC8144E

FC-PBGA–783

29 mm × 29 mm

Quad Core Digital Signal

Processor

•

Four StarCore™ SC3400 DSP subsystems, each with an SC3400

DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,

memory management unit (MMU), extended programmable

interrupt controller (EPIC), two general-purpose 32-bit timers,

debug and profiling support, and low-power Wait and Stop

processing modes.

Chip-level arbitration and system (CLASS) that provides full

fabric non-blocking arbitration between the processing elements

and other initiators and the M2 memory, DDR SRAM controller,

device configuration control and status registers, and other

targets.

128 Kbyte L2 shared instruction cache.

512 Kbyte M2 memory for critical data and temporary data

buffering.

10 Mbyte 128-b8t wide M3 memory.

96 Kbyte boot ROM.

Three input clocks (shared, global, and differential).

Four PLLs (system, core, global, and serial RapidIO).

Security Engine (SEC0 optimized to process all the algorithms

associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP

using 4 crypto-channels with multi-command chains, integrated

controller for assignment of the six execution units (PKEU, DEU,

AESU, AFEU, MDEU, and KEU0) and the random number

generator (RNG), and XOR engine to accelerate parity checking

for RAID storage applications.

DDR controller with up to a 200 MHz clock (400 MHz data rate),

16/32 bit data bus, supporting up to 1 Gbyte in up to two banks

and support for DDR1 and DDR2.

DMA controller with 16 bidirectional channels with up to 1024

buffer descriptors, and programmable priority, buffer, and

multiplexing configuration.

– The two Ethernet controllers support 10/100/1000 Mbps

operations via MII/RMII/SMII/RGMII/SGMII and the SGMII

protocol using a 4-pin SerDes interface at 1000 Mbps data rate

only.

– The ATM controller supports UTOPIA level II 8/16 bits at

25/50 MHz in UTOPIA/POS mode with adaptation layer

support AAL0, AAL2, and AAL5.

PCI designed to comply with the PCI specification revision 2.2 at

33 MHz or 66 MHz with access to all PCI address spaces.

Serial RapidIO® 1x/4x endpoint corresponds to Specification 1.2

of the RapidIO trade association, and supports read, write,

messages, doorbells, and maintenance accesses in inbound mode,

and messages and doorbells in outbound mode.

I/O interrupt concentrator consolidates all chip maskable interrupt

and non-maskable interrupt sources and routes them to

INT_OUT, NMI_OUT, and the cores.

UART that permits full-duplex operation with a bit rate of up to

6.25 Mbps.

Serial peripheral interface (SPI).

Four timer modules, each with four configurable16-bit timers.

Four software watchdog timer (SWT) modules.

Up to 32 general-purpose input/output (GPIO) ports, 16 of which

can be configured as maskable interrupt inputs.

I²C interface that allows booting from EEPROM devices.

Eight programmable hardware semaphores.

•

Thirty two virtual maskable interrupts and one virtual NMI that

can be generated by a simple write access.

•

Optional booting via serial RapidIO port, PCI, I²C, SPI, or

Ethernet interfaces.

Note: This document supports mask set M31H.

Up to eight independent TDM modules with programmable word

size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,

up to 128 Mbps data rate for all channels, with glueless interface

to E1 or T1 framers, and can interface with H-MVIP/H.110

devices, TSI, and codecs such as AC-97.

•

QUICC Engine™ technology subsystem with dual RISC

processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction

RAM, supporting three communication controllers with one ATM

and two Gigabit Ethernet interfaces, to offload scheduling tasks

from the DSP cores.

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

Table of Contents

1

2

Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4

1.1 FC-PBGA Ball Layout Diagrams. . . . . . . . . . . . . . . . . . .4

1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.2 Recommended Operating Conditions. . . . . . . . . . . . . .27

2.3 Default Output Driver Characteristics . . . . . . . . . . . . . .27

2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28

2.5 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .29

2.7 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .64

3.1 Start-up Sequencing Recommendations . . . . . . . . . . .64

3.2 Power Supply Design Considerations. . . . . . . . . . . . . .65

3.3 Clock and Timing Signal Board Layout Considerations 65

3.4 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .66

3.5 External DDR SDRAM Selection . . . . . . . . . . . . . . . . .74

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Figure 12.Differential V of Transmitter or Receiver . . . . . . . . . . 42

Figure 13.Transmitter Output Compliance Mask . . . . . . . . . . . . . . 45

PP

Figure 14.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 47

Figure 15.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . . 48

Figure 16.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 17.PCI Input AC Timing Measurement Conditions. . . . . . . 50

Figure 18.PCI Output AC Timing Measurement Condition . . . . . . 50

Figure 19.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 21.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 22.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 23.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 24.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 25.MII Management Interface Timing. . . . . . . . . . . . . . . . . 54

Figure 26.MII Transmit AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 27.AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 28.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 29.RMII Transmit and Receive AC Timing . . . . . . . . . . . . . 56

Figure 30.AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 31.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 32.RGMII AC Timing and Multiplexing s. . . . . . . . . . . . . . . 58

Figure 33.ATM/UTOPIA/POS AC Test Load . . . . . . . . . . . . . . . . . 59

Figure 34.ATM/UTOPIAPOS AC Timing (External Clock). . . . . . . 59

Figure 35.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 36.SPI AC Timing in Slave Mode (External Clock). . . . . . . 60

Figure 37.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 61

Figure 38.Asynchronous Signal Timing . . . . . . . . . . . . . . . . . . . . . 61

Figure 39.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 40.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 62

Figure 41.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 42.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3

4

5

6

7

List of Figures

Figure 1. MSC8144E Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram 3

Figure 3. MSC8144E FC-PBGA Package, Top View . . . . . . . . . . . 4

Figure 4. MSC8144E FC-PBGA Package, Bottom View . . . . . . . . 5

Figure 5. SerDes Reference Clocks Input Stage . . . . . . . . . . . . . 31

Figure 6. Overshoot/Undershoot Voltage for V and V . . . . . . . 34

Figure 7. Start-Up Sequence with V Raised Before V

IH

IL

with

DD

DDIO

CLKIN Started with V

. . . . . . . . . . . . . . . . . . . . . . . 35

DDIO

Figure 43.V

, V

and V

Power-on Sequence . . . . . 64

DDM3

DDM3IO

25M3

Figure 8. Timing for a Reset Configuration Write. . . . . . . . . . . . . 38

Figure 9. Timing for t . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 45.MSC8144E Mechanical Information, 783-ball FC-PBGA

Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DDKHMH

Figure 10.DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41

Figure 11.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

2

Freescale Semiconductor

DDR Interface 16/32-bit at 400 MHz data rate

I/O-Interrupt

10 Mbytes

M3

Memory

512 Kbytes

M2

Memory

Concentrator

DDR

Controller

UART

128-bit at

400 MHz

Clocks

Timers

CLASS

Reset

QUICC Engine™

Subsystem

Semaphores

Ser. RapidIO

Subsystem

Dual RISC

Processors

Virtual

Four DSP

Subsystems

128 Kbyte

Interrupts

L2

RMU SRIO

Boot ROM

I²C

ICache

Ether-

net

Ether-

net

ATM SPI

Other

Modules

JTAG

Eight TDMs

256-Channels each

PCI 32-bit

33/66 MHz

SPI

10/100/1000 Mbps

16-bit/8-bit

UTOPIA

1x/4x

Note: The arrow direction indicates master or slave.

Figure 1. MSC8144E Block Diagram

Two Internal Buses

(128 bits wide each)

Interrupts

EPIC

Timer

Bus Interface

IQBus

DQBus

TWB

Task

Protection

Write-

Through

Buffer

Write-

Back

Buffer

Debug Support

OCE30 DPU

Instruction

Cache

Data

Cache

Address

Translation

(WBB)

(WTB)

MMU

P-bus

Xa-bus

Xb-bus

SC3400

Core

Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

3

Pin Assignments and Reset States

1

Pin Assignments and Reset States

This section includes diagrams of the MSC8144E package ball grid array layouts and tables showing how the pinouts are

allocated for the package.

1.1

FC-PBGA Ball Layout Diagrams

Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers.

Top View

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

A

B

C

D

E

F

G

H

J

K

L

M

N

P

MSC8144E

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

Figure 3. MSC8144E FC-PBGA Package, Top View

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

4

Freescale Semiconductor

Bottom View

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

M S C 8 1 4

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

28

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Figure 4. MSC8144E FC-PBGA Package, Bottom View

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

5

1.2

Signal List By Ball Location

Table 1 presents the signal list sorted by ball number. The functionality of multi-functional (multiplexed) pins is separated for

each mode. When designing a board, make sure that the reference supply for each signal is appropriately considered. The

specified reference supply must be tied to the voltage level specified in this document if any of the related signal functions are

used (active).

Table 1. Signal List by Ball Number

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

A2

A3

GND

GE2_RX_ER/PCI_AD31

GND

Ethernet 2

PCI

Ethernet 2

V

DDGE2

A4

V

DDGE2

A5

GE2_RX_DV/PCI_AD30

GE2_TD0/PCI_CBE0

SRIO_IMP_CAL_RX

Ethernet 2

PCI

Ethernet 2

A6

A7

DDSXC

1

A8

Reserved

—

1

A9

Reserved

—

1

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

Reserved

1

Reserved

SRIO_RXD0

V

DDSXC

V

DDSXC

SRIO_RXD1

V

DDSXC

SRIO_REF_CLK

V

GND

RIOPLL

DDRIOPLL

GND

SXC

SRIO_RXD2/

GE1_SGMII_RX

SGMII support on SERDES is enabled by Reset Configuration Word

V

DDSXC

A20

A21

V

DDSXC

SRIO_RXD3/

GE2_SGMII_RX

A22

A23

A24

A25

A26

A27

A28

B1

V

DDSXC

DDSXP

DDDDR

SRIO_IMP_CAL_TX

MDQ28

V

MDQ29

MDQ30

MDQ31

MDQS3

DDDDR

1

Reserved

—

B2

GE2_TD1/PCI_CBE1

GE2_TX_EN/PCI_CBE2

GE_MDIO

Ethernet 2

PCI

Ethernet 2

V

DDGE2

B3

B4

Ethernet

B5

GND

B6

GE_MDC

Ethernet

V

DDGE2

B7

GND

SXC

1

B8

Reserved

—

B9

—

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

6

Freescale Semiconductor

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

1

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

Reserved

—

1

Reserved

SRIO_RXD0

GND

V

DDSXC

GND

SXC

SRIO_RXD1

GND

V

DDSXC

GND

SXC

SRIO_REF_CLK

V

DDSXC

1

Reserved

—

V

DDSXC

SRIO_RXD2/

GE1_SGMII_RX

SGMII support on SERDES is enabled by Reset Configuration Word

B20

B21

GND

SXC

SRIO_RXD3/

V

DDSXC

GE2_SGMII_RX

B22

B23

B24

B25

B26

B27

B28

C1

GND

SXC

SXP

SXC

SXP

MDQ27

V

DDDDR

V

DDDDR

GND

V

DDDDR

MDQS3

DDDDR

1

Reserved

—

C2

GE2_RX_CLK/PCI_AD29

Ethernet 2

PCI

Ethernet 2

V

DDGE2

C3

V

DDGE2

C4

TDM7RSYN/GE2_TD2/

PCI_AD2/UTP_TER

TDM

PCI

Ethernet 2

UTOPIA

C5

TDM7RCLK/GE2_RD2/

PCI_AD0/UTP_RVL

V

DDGE2

C6

V

DDGE2

C7

GE2_RD0/PCI_AD27

Ethernet 2

PCI

Ethernet 2

DDGE2

1

C8

Reserved

—

1

C9

Reserved

—

1

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

Reserved

1

Reserved

V

DDSXP

SRIO_TXD0

V

DDSXP

SRIO_TXD1

GND

SXC

GND

RIOPLL

1

RIOPLL

Reserved

—

V

DDSXP

SRIO_TXD2/GE1_SGMII_T

X

SGMII support on SERDES is enabled by Reset Configuration Word

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

7

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

C21

C22

V

DDSXP

SRIO_TXD3/GE2_SGMII_T

X

SGMII support on SERDES is enabled by Reset Configuration Word

DDSXP

C23

C24

C25

C26

C27

C28

D1

V

DDSXP

DDDDR

MDQ26

MDQ25

MDM3

V

DDDDR

GND

MDQ24

Reserved

V

DDDDR

1

—

D2

GE2_RD1/PCI_AD28

GND

Ethernet 2

PCI

Ethernet 2

V

DDGE2

D3

GND

D4

TDM7TDAT/GE2_TD3/

PCI_AD3/UTP_TMD

TDM

PCI

Ethernet 2

UTOPIA

V

DDGE2

DDGE1

DDGE2

D5

D6

D7

TDM7RDAT/GE2_RD3/

PCI_AD1/UTP_STA

V

GE1_RD0/UTP_RD2/

PCI_CBE2

UTOPIA

TDM

Ethernet 1

UTOPIA

Ethernet 1 UTOPIA

Ethernet 2 UTOPIA

TDM7TCLK/GE2_TCK/

PCI_IDS/UTP_RER

1

D8

Reserved

—

1

D9

Reserved

1

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

Reserved

1

Reserved

GND

SXP

SRIO_TXD0

GND

V

DDSXP

GND

SXP

SRIO_TXD1

V

DDSXP

V

DDSXC

1

Reserved

—

GND

SXP

SRIO_TXD2/GE1_SGMII_T

X

SGMII support on SERDES is enabled by Reset Configuration Word

V

DDSXP

D21

D22

GND

SXP

SRIO_TXD3/GE2_SGMII_T

X

V

DDSXP

D23

D24

D25

D26

D27

D28

E1

GND

SXP

DDDDR

MDQ23

V

DDDDR

MDQ22

MDQ21

MDQS2

Reserved

DDDDR

1

—

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

8

Freescale Semiconductor

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

E2

E3

E4

E5

GE1_RX_CLK/UTP_RD6/

PCI_PAR

UTOPIA

Ethernet 1

PCI

UTOPIA

Ethernet 1 UTOPIA

V

DDGE1

GE1_RD2/UTP_RD4/

PCI_FRAME

GE1_RD1/UTP_RD3/

PCI_CBE3

GE1_RD3/UTP_RD5/

PCI_IRDY

E6

E7

V

DDGE1

GE1_TX_EN/UTP_TD6/

PCI_CBE0

UTOPIA

Ethernet 1

PCI

UTOPIA

Ethernet 1 UTOPIA

DDGE1

1

E8

Reserved

—

1

E9

Reserved

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

F1

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DDDDR

MDQ20

GND

DDDDR

GND

V

DDDDR

GND

MDQS2

Reserved

DDDDR

1

—

F2

GE1_TX_CLK/UTP_RD0/

PCI_AD31

UTOPIA

Ethernet 1

PCI

UTOPIA

Ethernet 1 UTOPIA

V

DDGE1

F3

F4

V

DDGE1

GE1_TD3/UTP_TD5/

PCI_AD30

UTOPIA

Ethernet 1

PCI

UTOPIA

Ethernet 1 UTOPIA

DDGE1

F5

GE1_TD1/UTP_TD3/

PCI_AD28

V

DDGE1

F6

F7

GND

GE1_TD0/UTP_TD2/

PCI_AD27

UTOPIA

Ethernet 1

PCI

UTOPIA

Ethernet 1 UTOPIA

V

DDGE1

F8

F9

V

DDGE1

GND

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

9

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

G1

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

1

Reserved

—

V

DDDDR

GND

MDQ19

MDQ18

MDM2

V

DDDDR

MDQ17

MDQ16

Reserved

DDDDR

1

—

4

G2

SRESET

GND

V

DDIO

G3

GND

4

G4

PORESET

V

DDIO

G5

GE1_COL/UTP_RD1

UTOPIA

Ethernet 1

UTOPIA

Ethernet 1 UTOPIA

V

G6

GE1_TD2/UTP_TD4/

PCI_AD29

PCI

V

DDGE1

G7

G8

GE1_RX_DV/UTP_RD7

UTOPIA

Ethernet 1

UTOPIA

Ethernet 1 UTOPIA

V

DDGE1

GE1_TX_ER/UTP_TD7/

PCI_CBE1

G9

V

DD

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

—

1

Reserved

GND

—

GND

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

10

Freescale Semiconductor

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

G23

G24

G25

G26

G27

G28

H1

MBA1

MA3

V

DDDDR

MA8

V

DDDDR

GND

MCK0

V

DDDDR

1

Reserved

—

H2

CLKIN

V

DDIO

H3

HRESET

V

H4

PCI_CLK_IN

NMI

V

H5

H6

URXD/GPIO14/IRQ8/

RC_LDF

UART/GPIO/IRQ

3, 6

H7

H8

GE1_RX_ER/PCI_AD6/

GPIO25/IRQ15

GPIO/ Ethernet

PCI

GPIO/

IRQ

Ethernet 1

V

DDIO

3, 6

IRQ

1

GE1_CRS/PCI_AD5

PCI

Ethernet

1

PCI

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

J1

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

V

DDDDR

MBA0

MA15

V

DDDDR

MA9

MA7

MCK0

Reserved

GND

DDDDR

1

—

J2

GND

J3

V

DDIO

J4

STOP_BS

V

4

J5

NMI_OUT

V

4

J6

INT_OUT

3, 4, 6

J7

SDA/GPIO27

I2C/GPIO

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

11

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

J8

V

DDIO

DD

J9

V

DD

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

K1

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DDDDR

GND

V

DDDDR

GND

V

DDDDR

1

Reserved

—

K2

—

K3

K4

K5

V

DDPLL2A

K6

GND

K7

V

DDPLL0A

DDPLL1A

DD

DDPLL0A

DDPLL1A

K8

K9

V

DD

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

V

DDDDR

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

12

Freescale Semiconductor

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

K23

K24

K25

K26

K27

K28

L1

MBA2

MA10

MA12

MA14

MA4

V

DDDDR

MV

REF

DDDDR

1

Reserved

—

L2

CLKOUT

V

DDIO

L3

TMR1/UTP_IR/PCI_CBE3/

UTOPIA

TMR/ UTOPIA

GPIO

PCI

UTOPIA

V

3, 6

GPIO17

3,

L4

TMR4/PCI_PAR/GPIO20

TIMER/GPIO

V

DDIO

6

/ UTP_REOP

L5

L6

GND

TMR2/PCI_FRAME/

GPIO18

TIMER/GPIO

PCI

TIMER/GPIO

UTOPIA

V

DDIO

3, 6

3, 4, 6

2

L7

SCL/GPIO26

I C/GPIO

V

DDIO

3, 6

L8

UTXD/GPIO15/IRQ9

UART/GPIO/IRQ

DDIO

L9

GND

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

L27

L28

M1

V

DD

GND

V

DD

GND

V

DD

1

Reserved

GND

V

DD

GND

V

DD

GND

V

DD

GND

MCKE1

MA1

V

DDDDR

V

DDDDR

GND

V

DDDDR

MCK1

Reserved

TRST

EE0

DDDDR

1

—

M2

V

DDIO

M3

V

M4

EE1

V

M5

UTP_RCLK/PCI_AD13

UTP_RADDR0/PCI_AD7

UTP_TD8/PCI_AD30

UTOPIA

PCI

UTOPIA

M6

UTOPIA

M7

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

13

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

M8

M9

V

DDIO

DD

V

DD

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

M27

M28

N1

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

DDDDR

V

DDDDR

MCS1

MA13

MA2

MA0

DDDDR

GND

MCK1

Reserved

V

DDDDR

1

—

N2

V

DDIO

N3

TMS

UTP_RD10/PCI_AD14

V

5

N4

UTOPIA

PCI

UTOPIA

V

N5

V

Power

DDIO

N6

UTP_RADDR1/PCI_AD8

UTP_TD9/PCI_AD31

UTOPIA

PCI

UTOPIA

N7

3,

N8

TMR3/PCI_IRDY/GPIO19

TIMER/GPIO

PCI

TIMER/GPIO

UTOPIA

6

/ UTP_TEOP

N9

GND

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

V

DDM3

DD

V

DD

V

DDM3

DD

DDM3

V

DD

V

DDM3

DD

DDM3

V

DD

V

DDM3

DD

DDM3

V

DD

V

DDM3

DD

DDM3

V

DD

V

DDM3

GND

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

14

Freescale Semiconductor

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

N22

N23

N24

N25

N26

N27

N28

P1

GND

MODT1

MCKE0

V

DDDDR

V

DDDDR

MA5

MA6

MA11

Reserved

DDDDR

1

—

5

P2

TDI

V

DDIO

P3

UTP_RD11/PCI_AD15

GND

UTOPIA

PCI

UTOPIA

V

P4

GND

P5

UTP_RADDR3/PCI_AD10

UTP_RADDR2/PCI_AD9

UTOPIA

PCI

UTOPIA

V

DDIO

P6

V

3. 6

P7

PCI_GNT/GPIO29/IRQ7

GPIO/IRQ

PCI

GPIO/IRQ

V

3,

P8

PCI_STOP/GPIO30/IRQ2

6

P9

GND

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

P27

P28

R1

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDDDR

MCS0

MRAS

GND

DDDDR

GND

V

DDDDR

GND

MCK2

Reserved

TCK

DDDDR

1

—

R2

V

DDIO

R3

TDO

V

R4

UTP_RD12/PCI_AD16

UTOPIA

PCI

UTOPIA

V

R5

UTP_RCLAV_PDRPA/

PCI_AD12

R6

UTP_RADDR4/PCI_AD11

UTOPIA

PCI

UTOPIA

V

DDIO

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

15

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

R7

R8

V

DDIO

PCI_REQ

GND

PCI

DDIO

R9

GND

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

T1

GND

MODT0

MDIC1

MDIC0

MCAS

MWE

MCK2

V

DDDDR

1

Reserved

—

T2

UTP_RPRTY/PCI_AD21

UTP_RD13/PCI_AD17

UTOPIA

PCI

UTOPIA

V

DDIO

T3

V

T4

V

DDIO

T5

UTP_RD14/PCI_AD18

UTP_RD15/PCI_AD19

PCI_TRDY

UTOPIA

PCI

UTOPIA

T6

T7

PCI

T8

PCI_DEVSEL/GPIO31/

GPIO/IRQ

PCI

GPIO/IRQ

3, 6

IRQ3

T9

GND

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

16

Freescale Semiconductor

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

T21

T22

T23

T24

T25

T26

T27

T28

U1

GND

V

DDDDR

GND

V

DDDDR

GND

V

DDDDR

GND

V

DDDDR

1

Reserved

—

U2

UTP_TCLK/PCI_AD29

UTP_TADDR4/PCI_AD27

UTP_TADDR2

GND

UTOPIA

PCI

UTOPIA

V

DDIO

U3

V

U4

UTOPIA

V

U5

GND

U6

UTP_REN/PCI_AD20

PCI_AD26

UTOPIA

PCI

UTOPIA

V

DDIO

DDM3

U7

PCI

V

U8

PCI_AD25

1

U9

Reserved

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

U27

U28

V1

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

MDQ7

MDQ3

MDQ4

MDQ5

MDQ1

MDQ0

Reserved

V

DDDDR

1

—

V2

UTP_TD10/PCI_CBE0

UTP_TADDR3

UTOPIA

PCI

UTOPIA

V

DDIO

V3

UTOPIA

V

V4

UTP_TD1/PCI_PERR

UTP_TADDR0/PCI_AD23

UTP_TADDR1/PCI_AD24

UTP_TCLAV/PCI_AD28

UTOPIA

PCI

UTOPIA

V

V5

PCI

UTOPIA

V6

V7

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

17

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

V8

V9

V

DDIO

1

Reserved

GND

DDIO

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

V27

V28

W1

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDDDR

MDQ2

V

DDDDR

MDQ6

GND

DDDDR

GND

V

DDDDR

MDQS0

DDDDR

1

Reserved

—

W2

UTP_TD12/PCI_CBE2

UTP_TD11/PCI_CBE1

UTOPIA

PCI

UTOPIA

V

DDIO

W3

V

W4

V

DDIO

W5

GND

W6

UTP_TD15/PCI_IRDY

UTP_TD0/PCI_SERR

UTP_RSOC/PCI_AD22

UTOPIA

PCI

UTOPIA

V

DDIO

DDM3

W7

PCI

UTOPIA

V

W8

1

W9

Reserved

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

V

DDM3

GND

V

25M3

GND

V

DDM3

25M3

DDM3

V

25M3

V

DDM3

GND

V

25M3

GND

V

DDM3

GND

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

18

Freescale Semiconductor

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

W23

W24

W25

W26

W27

W28

Y1

MDQ10

GND

V

DDDDR

GND

MDQ11

MDM0

GND

V

DDDDR

GND

MDQS0

V

DDDDR

1

Reserved

-

Y2

UTP_TD14/PCI_FRAME

UTOPIA

TDM/GPIO

PCI

UTOPIA

V

DDIO

Y3

TDM5TSYN/PCI_AD18/

PCI

TDM/GPIO

V

3, 6

GPIO12

Y4

Y5

TDM5TCLK/PCI_AD16

TDM4RCLK/PCI_AD7

TDM4TSYN/PCI_AD12

UTP_TPRTY/RC14

TDM

PCI

TDM

V

DDIO

Y6

PCI

Y7

RC14

UTOPIA

Y8

UTP_TEN/PCI_PAR

UTOPIA

PCI

UTOPIA

1

Y9

Reserved

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

Y27

Y28

AA1

AA2

AA3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDDDR

MDQ13

V

DDDDR

GND

MDQ9

V

DDDDR

V

DDDDR

MDQ8

DDDDR

1

Reserved

—

UTP_TD13/PCI_CBE3

TDM5RSYN/PCI_AD15/

UTOPIA

TDM/GPIO

PCI

UTOPIA

V

DDIO

PCI

TDM/GPIO

V

3, 6

GPIO10

AA4

AA5

AA6

TDM5TDAT, AT/PCI_AD17/

GPIO11

TDM/GPIO

V

DDIO

6

TDM5RCLK/PCI_AD13/

GPIO28

3, 6

GND

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

19

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

AA7

AA8

TDM4TCLK/PCI_AD10

TDM4TDAT/PCI_AD11

TDM

PCI

TDM

V

DDIO

DDM3

AA9

V

DDIO

AA10

V

DDM3

AA11 GND

AA12

AA13 GND

AA14

AA15 GND

AA16

AA17 GND

AA18

AA19 GND

AA20

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

AA21 GND

GND

AA22 GND

GND

AA23 MDQ15

AA24 MDQ14

AA25 MDM1

AA26 MDQ12

AA27 MDQS1

AA28 MDQS1

V

DDDDR

1

AB1

AB2

AB3

AB4

Reserved

UTP_TSOC/RC15

-

RC15

UTOPIA

V

DDIO

V

DDIO

TDM6RDAT/PCI_AD20/

GPIO5/IRQ11

TDM/GPIO/ IRQ

TDM/GPIO

PCI

TDM/GPIO/ IRQ

TDM/GPIO

V

3, 6

AB5

AB6

AB7

TDM5RDAT/PCI_AD14/

DDIO

3, 6

GPIO9

TDM6TSYN/PCI_AD24/

GPIO8/ IRQ14

TDM/GPIO/IRQ

3, 6

TDM6RCLK/PCI_AD19/

GPIO4/IRQ10

3, 6

AB8

AB9

TDM4RSYN/PCI_AD9

TDM4RDAT/PCI_AD8

TDM

PCI

TDM

V

DDIO

AB10 GND

AB11

AB12 GND

AB13

AB14 GND

AB15

AB16 GND

AB17

AB18 GND

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

20

Freescale Semiconductor

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

AB19

V

DDM3

AB20 GND

AB21 GND

GND

AB22

V

DDDDR

AB23 MECC7

AB24 MECC1

AB25 MECC4

AB26 MECC5

AB27 MECC2

AB28 ECC_MDQS

DDDDR

1

AC1

AC2

AC3

AC4

AC5

Reserved

—

UTP_RD9/RC13

UTP_RD8/RC12

TDM6TCLK/PCI_AD22

TDM6RSYN/PCI_AD21/

RC13

RC12

UTOPIA

V

DDIO

V

TDM

PCI

TDM

V

TDM/GPIO/IRQ

3, 6

GPIO6/ IRQ12

AC6

AC7

AC8

V

DDIO

TDM3TSYN/RC11

RC11

TDM

PCI

PCI_AD23/GPIO7/IRQ13/

TDM6TDAT /UTP_RMOD

TDM/GPIO/IRQ

TDM

TDM/GPIO/IRQ

reserved

UTOPIA

3, 6

AC9

TDM7TSYN/ PCI_AD4

PCI

V

DDIO

AC10

V

DDM3IO

AC11 GND

AC12

AC13 GND

AC14

AC15 GND

AC16

AC17 GND

AC18

AC19 GND

AC20

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3

GND

V

DDM3IO

1

AC21 Reserved

AC22 MECC6

AC23 MECC3

—

V

DDDDR

AC24 ECC_MDM

AC25

AC26 MECC0

AC27

V

DDDDR

V

DDDDR

AC28 ECC_MDQS

DDDDR

1

AD1

AD2

AD3

Reserved

—

3, 6

GPIO1

GPIO

V

DDIO

TMR0/GPIO13

TIMER/GPIO

V

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

21

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

3, 6

AD4

AD5

AD6

AD7

AD8

AD9

GPIO2

GND

GPIO

V

DDIO

GND

TDM1TCLK

TDM

V

DDIO

TDM3TDAT/RC10

TDM3RSYN/RC9

TDM3RDAT/RC8

RC10

RC9

RC8

V

AD10 GND

AD11

AD12 GND

AD13

AD14 GND

AD15

AD16 GND

AD17

AD18 GND

AD19

GND

V

25M3

GND

V

DDM3

GND

V

25M3

GND

V

DDM3

GND

V

25M3

AD20 GND

GND

1

AD21 Reserved

—

AD22

AD23 GND

AD24

AD25 GND

AD26

AD27 GND

V

DDDDR

GND

V

DDDDR

GND

V

DDDDR

GND

AD28

AE1

AE2

AE3

AE4

AE5

AE6

AE7

AE8

AE9

V

DDDDR

1

Reserved

—

3, 6

GPIO0

GPIO3

GPIO

V

DDIO

V

TDM1RCLK

TDM

V

TDM1TSYN/RC3

TDM1TDAT/RC2

TDM1RSYN/RC1

TDM3RCLK/RC16

TDM3TCLK

RC3

RC2

RC1

RC16

TDM

AE10 TDM2TDAT/RC6

RC6

TDM

3. 6

AE11 GPIO21/IRQ1 /SPICLK

GPIO/IRQ/SPI

AE12 GND

GND

—

1

AE13 Reserved

AE14 GND

GND

—

1

AE15 Reserved

1

AE16 Reserved

—

1

AE17 Reserved

—

AE18 GND

GND

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

22

Freescale Semiconductor

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

AE19 GND

GND

AE20

V

DDM3IO

1

AE21 Reserved

AE22 GND

AE23 GND

AE24 GND

—

GND

AE25

AE26 GND

AE27

AE28 GND

V

DDDDR

GND

V

DDDDR

GND

1

AF1

AF2

AF3

AF4

Reserved

—

V

DDIO

GND

TDM0RDAT/

RCFG_CLKIN_RNG

RCFG_

CLKIN_

RNG

TDM

V

DDIO

AF5

TDM0TSYN/RCW_SRC2

RCW_

SRC2

TDM

V

DDIO

AF6

AF7

AF8

AF9

TDM1RDAT/RC0

RC0

RC4

V

DDIO

V

DDIO

GND

TDM2RDAT/RC4

TDM

V

DDIO

AF10 TDM2TCLK

V

3, 6

AF11 GPIO22/IRQ4 /SPIMOSI

AF12 GND

GPIO/IRQ/SPI

GND

AF13 GND

AF14

V

DDM3IO

AF15 GND

GND

AF16 GND

GND

—

1

AF17 Reserved

AF18

V

DDM3IO

AF19 GND

GND

1

AF20 Reserved

AF21 Reserved

—

AF22 M3_RESET

AF23 GND

DDM3IO

GND

AF24

AF25 GND

AF26

AF27 GND

V

DDDDR

GND

V

DDDDR

GND

AF28

AG1

AG2

AG3

V

DDDDR

1

Reserved

—

3, 6

GPIO16/IRQ0

TDM0TCLK

GPIO/IRQ

TDM

V

DDIO

V

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

23

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

AG4

TDM0RSYN/RCW_SRC0

RCW_

SRC0

TDM

V

DDIO

AG5

AG6

TDM0RCLK

TDM

V

DDIO

TDM0TDAT/RCW_SRC1

RCW_

SRC1

AG7

AG8

AG9

TDM2TSYN/RC7

TDM2RCLK

RC7

TDM

V

DDIO

TDM2RSYN/RC5

RC5

TDM

3, 6

AG10 GPIO24/IRQ6 /SPISEL

GPIO/IRQ/SPI

3, 6

AG11 GPIO23/IRQ5 /SPIMISO

DDIO

1

AG12 Reserved

—

AG13 GND

AG14 GND

AG15 GND

AG16 GND

GND

—

1

AG17 Reserved

1

AG18 Reserved

—

AG19 GND

AG20 GND

GND

AG21

V

DDM3IO

AG22 GND

AG23 GND

AG24 GND

GND

AG25

AG26 GND

AG27

AG28 GND

V

DDDDR

GND

V

DDDDR

GND

1

AH1

AH2

AH3

AH4

AH5

AH6

AH7

AH8

AH9

Reserved

—

Reserved

AH10 Reserved

AH11 Reserved

AH12 Reserved

AH13 Reserved

AH14 Reserved

AH15 Reserved

AH16 Reserved

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

24

Freescale Semiconductor

Electrical Characteristics

Table 1. Signal List by Ball Number (continued)

2

Power-

On

I/O Multiplexing Mode

Ball

Number

Ref.

Supply

Signal Name

Reset

Value

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101)

6 (110)

7 (111)

1

AH17 Reserved

AH18 Reserved

AH19 Reserved

AH20 Reserved

AH21 Reserved

AH22 Reserved

AH23 Reserved

AH24 Reserved

AH25 Reserved

AH26 Reserved

AH27 Reserved

AH28 Reserved

—

1

Notes: 1. Reserved signals should be disconnected for compatibility with future revisions of the device.

2. For signals with same functionality in all modes the appropriate cells are empty.

3. The choice between GPIO function and other function is by GPIO registers setup. For configuration details, see Chapter 23,

GPIO in the MSC8144E Reference Manual.

4. Open-drain signal.

5. Internal 20 KΩ pull-up resistor.

6. For signals with GPIO functionality, the open-drain and internal 20 KΩ pull-up resistor can be configured by GPIO register

programming. See Chapter 23, GPIO of the MSC8144E Reference Manual for configuration details.

2

Electrical Characteristics

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing

specifications. For additional information, see the MSC8144E Reference Manual.

2.1

Maximum Ratings

CAUTION

This device contains circuitry protecting against damage

due to high static voltage or electrical fields; however,

normal precautions should be taken to avoid exceeding

maximum voltage ratings. Reliability is enhanced if unused

inputs are tied to an appropriate logic voltage level (for

example, either GND or V ).

DD

In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification

does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values

in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction.

Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another

specification; adding a maximum to a minimum represents a condition that can never exist.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

25

Electrical Characteristics

Table 2 describes the maximum electrical ratings for the MSC8144E.

Table 2. Absolute Maximum Ratings

Symbol

Rating

Value

Unit

Core supply voltage

PLL supply voltage

V

–0.3 to 1.1

V

dd

V

DDPLL0

DDPLL1

DDPLL2

M3 memory Internal voltage

DDR memory supply voltage

V

–0.3 to 1.32

V

DDM3

V

DDDDR

•

DDR mode

DDR2 mode

–0.3 to 2.75

–0.3 to 1.98

V

DDR reference voltage

MV

–0.3 to 0.51 × V

V

REF

DDDDR

Input DDR voltage

V

–0.3 to V

+ 0.3

DDDDR

V

INDDR

DDGE1

Ethernet 1 I/O voltage

V

–0.3 to 3.465

Input Ethernet 1 I/O voltage

Ethernet 2 I/O voltage

V

–0.3 to V

+ 0.3

V

INGE1

DDGE1

V

–0.3 to 3.465

DDGE2

Input Ethernet 2I/O voltage

V

–0.3 to V

+ 0.3

V

INGE2

DDGE2

I/O voltage excluding Ethernet, DDR, M3, and RapidIO lines

V

–0.3 to 3.465

DDIO

Input I/O voltage

V

–0.3 to V

+ 0.3

V

INIO

DDIO

M3 memory I/O and M3 memory charge pump voltage

V

–0.3 to 2.75

DDM3IO

V

25M3

Input M3 memory I/O voltage

Rapid I/O C voltage

V

–0.3 to V

+ 0.3

V

INM3IO

DDSXC

DDSXP

DDM3IO

–0.3 to 1.21

Rapid I/O P voltage

–0.3 to 1.26

–0.3 to 1.21

–40 to 105

–55 to +150

V

Rapid I/O PLL voltage

V

DDRIOPLL

Operating temperature

T

°C

J

Storage temperature range

Notes: 1. Functional operating conditions are given in Table 3.

T

STG

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permanent damage.

3. PLL supply voltage is specified at input of the filter and not at pin of the MSC8144E (see Figure 44)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

26

Freescale Semiconductor

Electrical Characteristics

2.2

Recommended Operating Conditions

Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.

Table 3. Recommended Operating Conditions

Rating

Symbol

Min

Nominal

Max

Unit

Core supply voltage

PLL supply voltage

V

0.97

1.0

1.05

V

DD

V

DDPLL0

DDPLL1

DDPLL2

M3 memory Internal voltage

DDR memory supply voltage

V

1.213

1.25

1.313

V

DDM3

V

DDDDR

•

DDR mode

DDR2 mode

2.375

1.71

2.5

1.8

2.625

1.89

0.51 × V

DDDDR

V

DDR reference voltage

MV

0.49 × V

0.5 × V

REF

DDDDR

Ethernet 1 I/O voltage

V

DDGE1

•

2.5 V mode

3.3 V mode

2.375

3.135

2.5

3.3

2.625

3.465

V

Ethernet 2 I/O voltage

V

DDGE2

•

2.5 V mode

3.3 V mode

2.375

3.135

2.5

3.3

2.625

3.465

V

I/O voltage excluding Ethernet,

DDR, M3, and RapidIO lines

V

3.135

2.375

0.95

3.3

2.5

1.0

3.465

2.625

1.05

V

DDIO

M3 memory I/O and M3 charge

pump voltage

V

DDM3IO

V

25M3

Rapid I/O C voltage

Rapid I/O P voltage

V

DDSXC

DDSXP

•

Short run (haul) mode

Long run (haul) mode

0.95

1.14

1.0

1.2

1.05

1.26

V

Rapid I/O PLL voltage

V

0.95

1.0

1.05

V

DDRIOPLL

Operating temperature range:

•

Standard

Extended

T

0

–40

—

90

—

105

°C

J

T

A

T

J

Note:

PLL supply voltage is specified at input of the filter and not at pin of the MSC8144E (see Figure 44).

2.3

Default Output Driver Characteristics

Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.

Table 4. Output Drive Impedance

Driver Type

Output Impedance (Ω)

DDR signal

18

DDR2 signal

18

35 (half strength mode)

PCI signals

25

100

50

Rapid I/O signals

Other signals

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

27

Electrical Characteristics

2.4

Thermal Characteristics

Table 5 describes thermal characteristics of the MSC8144E for the FC-PBGA packages.

Table 5. Thermal Characteristics for the MSC8144E

FC-PBGA

²⁹× 29 mm⁵

Characteristic

Symbol

Unit

Natural

200 ft/min

Convection

(1 m/s) airflow

1, 2

Junction-to-ambient

R

20

15

7

15

12

°C/W

θJA

θJB

θJC

1, 3

Junction-to-ambient, four-layer board

4

Junction-to-board (bottom)

5

Junction-to-case

0.8

Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL

SPEC-883 Method 1012.1) with the calculated case temperature.

2.5

Power Characteristics

The estimated typical power dissipation for MSC8144E versus the core frequency is shown in Table 6.

Table 6. Power Dissipation

Extended Core Frequency

Core Frequency

Typical

Unit

266

400

533

667

800

500

667

833

1000

400

600

800

1000

500

750

1000

TBD

W

333

400

500

W

Note:

Measured for 1.0 V core at 25°C junction temperature.

The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No

peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

28

Freescale Semiconductor

Electrical Characteristics

all four cores. It was created using CodeWarrior^®3.0. These values are provided as examples only. Power consumption is

application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining

proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Section 3 of

this document.

At allowable voltage levels, Table 7 lists the estimated power dissipation on the 1.0-V AV_DDsupplies for the MSC8144E PLLs.

Table 7. MSC8144E PLLs Power Dissipation

PLL supply

Typical

Maximum

Unit

V

TBD

10

mW

DDPLL0

DDPLL1

DDPLL2

Note:

Typical value is based on V

= 1.0 V, T = 70°C, T = 105°C.

DDPLLX A J

2.6

DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC8144E.

2.6.1

DDR SDRAM DC Electrical Characteristics

This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144E.

Note: DDR SDRAM uses V_DDDDR(typ) = 2.5 V and DDR2 SDRAM uses V_DDDDR(typ) = 1.8 V.

2.6.1.1

DDR2 (1.8 V) SDRAM DC Electrical Characteristics

Table 8 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144E when

V_DDDDR(typ) = 1.8 V.

Table 8. DDR2 SDRAM DC Electrical Characteristics for V_DDDDR(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

1

I/O supply voltage

V

1.7

1.9

V

DDDDR

2

I/O reference voltage

MV

0.49 × V

0.51 × V

DDDDR

REF

TT

DDDDR

3

I/O termination voltage

Input high voltage

Input low voltage

V

MV

– 0.04

MV

+ 0.04

V

REF

V

MV

+ 0.125

V

+ 0.3

V

IH

REF

DDDDR

V

I

–0.3

MV

– 0.125

V

IL

REF

4

Output leakage current

Output high current (V

–50

–13.4

13.4

50

μA

mA

OZ

OH

= 1.420 V)

I

—

OUT

Output low current (V

= 0.280 V)

I

OL

OUT

Notes: 1.

V

is expected to be within 50 mV of the DRAM V at all times.

DDDDR DD

2. MV

is expected to be equal to 0.5 × V

, and to track V

DC variations as measured at the receiver.

DDDDR

REF

DDDDR

Peak-to-peak noise on MV

may not exceed 2% of the DC value.

REF

3.

V

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

TT

equal to MV

. This rail should track variations in the DC level of V

.

REF

DDDDR

4. ^{Output leakage is measured with all outputs are disabled, 0 V}≤ V

≤ V

.

DDDDR

OUT

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

29

Electrical Characteristics

Table 9 provides the DDR capacitance when V_DDDDR(typ) = 1.8 V.

Table 9. DDR2 SDRAM Capacitance for V_DDDDR(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

C

6

8

pF

IO

C

—

0.5

DIO

Note:

This parameter is sampled. V

= 1.8 V 0.090 V, f = 1 MHz, T = 25°C, V

= V

/2, V

(peak-to-peak) = 0.2 V.

DDDDR

A

OUT

DDDDR

OUT

2.6.1.2

DDR (2.5V) SDRAM DC Electrical Characteristics

Table 10 provides the recommended operating conditions for the DDR SDRAM component(s) of the MSC8144E when

V_DDDDR(typ) = 2.5 V.

Table 10. DDR SDRAM DC Electrical Characteristics for V_DDDDR(typ) = 2.5 V

Parameter/Condition

Symbol

Min

Max

Unit

1

I/O supply voltage

V

2.3

2.7

V

DDDDR

2

I/O reference voltage

MV

0.49 × V

0.51 × V

DDDDR

REF

TT

DDDDR

3

I/O termination voltage

Input high voltage

Input low voltage

V

MV

– 0.04

MV

+ 0.04

V

REF

V

MV

+ 0.15

V

+ 0.3

V

IH

DDDDR

V

I

–0.3

MV

– 0.15

REF

V

IL

4

Output leakage current

Output high current (V

–50

–16.2

16.2

50

μA

mA

OZ

OH

= 1.95 V)

I

—

OUT

Output low current (V

= 0.35 V)

I

OL

OUT

Notes: 1.

V

is expected to be within 50 mV of the DRAM V at all times.

DDDDR DD

2. MV

is expected to be equal to 0.5 × V

, and to track V

DC variations as measured at the receiver.

DDDDR

REF

DDDDR

Peak-to-peak noise on MV

may not exceed 2% of the DC value.

REF

3.

V

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

TT

equal to MV

. This rail should track variations in the DC level of V

.

REF

DDDDR

4. ^{Output leakage is measured with all outputs are disabled, 0 V}≤ V

≤ V

.

DDDDR

OUT

Table 11 provides the DDR capacitance when V_DDDDR(typ) = 2.5 V.

Table 11. DDR SDRAM Capacitance for V_DDDDR(typ) = 2.5 V

Parameter/Condition

Symbol

Min

Max

Unit

Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

Note: This parameter is sampled. V

C

6

8

pF

IO

C

—

0.5

DIO

= 2.5 V 0.125 V, f = 1 MHz, T = 25°C, V

= V

/2, V

(peak-to-peak) = 0.2 V.

OUT

DDDDR

A

OUT

DDDDR

Table 12 lists the current draw characteristics for MV_REF

.

Table 12. Current Draw Characteristics for MV_REF

Parameter / Condition

Symbol

Min

Max

Unit

Current draw for MV

I

—

500

μA

REF

MVREF

Note:

The voltage regulator for MV

must be able to supply up to 500 μA current.

REF

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

30

Freescale Semiconductor

Electrical Characteristics

2.6.2

Serial RapidIO DC Electrical Characteristics

DC receiver logic levels are not defined since the receiver is AC-coupled.

2.6.2.1

DC Requirements for SerDes Reference Clocks

The SerDes reference clocks SRIO_REF_CLK and SRIO_REF_CLK are AC-coupled differential inputs. Each differential

clock input has an internal 50 Ω termination to GND_SXC. The reference clock must be able to drive this termination. The

recommended minimum operating voltage is –0.4 V; the recommended maximum operating voltage is 1.32 V; and the

maximum absolute voltage is 1.72 V.

The maximum average current allowed in each input is 8 mA. This current limitation sets the maximum common mode input

voltage to be less than 0.4 V (0.4 V/50 Ω = 8 mA) while the minimum common mode input level is GND_SXC. For example, a

clock with a 50/50 duty cycle can be driven by a current source output that ranges from 0 mA to 16 mA (0–0.8 V). The input is

AC-coupled internally, so, therefore, the exact common mode input voltage is not critical.

Note: This internal AC-couple network does not function correctly with reference clock frequencies below 90 MHz.

If the device driving the SRIO_REF_CLK inputs cannot drive 50 Ω to GND_SXC, or if it exceeds the maximum input current

limitations, then it must use external AC-coupling. The minimum differential peak-to-peak amplitude of the input clock is 0.4 V

(0.2 V peak-to-peak per phase). The maximum differential peak-to-peak amplitude of the input clock is 1.6 V peak-to-peak (see

Figure 5. The termination to GND_SXCallows compatibility with HCSL type reference clocks specified for PCI-Express

applications. Many other low voltage differential type outputs can be used but will probably need to be AC-coupled due to the

limited common mode input range. LVPECL outputs can produce too large an amplitude and may need to be source terminated

with a divider network to reduce the amplitude. The amplitude of the clock must be at least a 400 mV differential peak-peak for

single-ended clock. If driven differentially, each signal wire needs to drive 100 mV around common mode voltage. The

differential reference clock (SRIO_REF_CLK/ SRIO_REF_CLK) input is HCSL-compatible DC coupled or LVDS-compatible

with AC-coupling.

SRIO_REF_CLK

50 Ω

GND_SXC

50 Ω

SRIO_REF_CLK

Figure 5. SerDes Reference Clocks Input Stage

2.6.2.2

Spread Spectrum Clock

SRIO_REF_CLK/ SRIO_REF_CLK is designed to work with a spread spectrum clock (0 to 0.5% spreading at 3033 kHz rate

is allowed), assuming both ends have same reference clock. For better results use a source without significant unintended

modulation.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

31

Electrical Characteristics

2.6.3

PCI DC Electrical Characteristics

Table 13. PCI DC Electrical Characteristics

Characteristic Symbol Min

Max

Unit

Supply voltage 3.3 V

Input high voltage

Input low voltage

V

3.135

0.5 × V

3.465

V

DDPCI

V

IH

DDPCI

V

–0.5

0.7 × V

0.3 × V

DDPCI

IL

2

Input Pull-up voltage

V

IPU

DDPCI

Input leakage current, 0<V <V

I

IN

–30

30

—

μA

V

IN

DDPCI

Tri-state (high impedance off state) leakage current, 0<V <V

I

OZ

IN

DDPCI

2

Signal low input current, V = 0.4 V

I

IL

L

2

Signal high input current, V = 2.0 V

I

IH

H

Output high voltage, I = –0.5 μA,

V

0.9 × V

DDPCI

OH

except open drain pins

Output low voltage, I = 1.5 μA

V

—

0.1 × V

DDPCI

V

OL

2

Input Pin Capacitance

C

10

pF

IN

Notes: 1. See Figure 6 for undershoot and overshoot voltages.

2. Not tested. Guaranteed by design.

2.6.4

TDM DC Electrical Characteristics

Table 14. TDM DC Electrical Characteristics

Characteristic Symbol Min

Max

Unit

Supply voltage 3.3 V

Input high voltage

Input low voltage

V

3.135

2.0

3.465

0.8

30

V

DDTDM

V

IH

V

I

–0.3

–30

2.4

V

IL

Input leakage current, 0<V <V

μA

V

IN

DDTDM

IN

Tri-state (high impedance off state) leakage current,

I

30

OZ

1

Signal input current,

I

30

L

Output high voltage, I = –1.6 mA,

V

—

OH

Output low voltage, I = 0.4mA

V

—

0.4

8

V

OL

1

Pin Capacitance

Cp

pF

Note:

1. Not tested. Guaranteed by design.

2.6.5

2.6.5.1

Ethernet DC Electrical Characteristics

MII, SMII and RMII DC Electrical Characteristics

Table 15. MII, SMII and RMII DC Electrical Characteristics

Characteristic

Symbol

Min

Max

Unit

Supply voltage 3.3 V

V

3.135

3.465

V

DDGE1

DDGE2

Input high voltage

Input low voltage

V

2.0

–0.3

–30

3.465

0.8

V

IH

V

I

IL

Input leakage current, V = supply voltage

30

μA

IN

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

32

Freescale Semiconductor

Electrical Characteristics

Table 15. MII, SMII and RMII DC Electrical Characteristics (continued)

Characteristic

Symbol

Min

Max

Unit

1

Signal low input current, V = 0.4 V

I

–30

2.4

—

30

μA

V

IL

L

1

Signal high input current, V = 2.4 V

I

IH

H

Output high voltage, I = –4 mA,

V

3.465

0.4

8

OH

Output low voltage, I = 4mA

V

OL

1

Input Pin Capacitance

C

pF

IN

Note:

1. Not tested. Guaranteed by design.

2.6.5.2

RGMII DC Electrical Characteristics

Table 16. RGMII DC Electrical Characteristics

Characteristic

Symbol

Min

Max

Unit

Supply voltage 2.5V

V

2.375

2.625

V

DDGE1

DDGE2

Input high voltage

Input low voltage

V

1.7

–0.3

–30

2.0

2.625

0.7

30

V

IH

V

I

IL

Input leakage current, V = supply voltage

μA

V

IN

1

Signal low input current, V = 0.4 V

I

30

IL

L

1

Signal high input current, V = 2.4 V

I

30

IH

H

Output high voltage, I = –1 mA,

V

2.625

0.4

8

OH

Output low voltage, I = 1 mA

V

—

V

OL

1

Input Pin Capacitance

C

pF

IN

Note:

1. Not tested. Guaranteed by design.

2.6.6

ATM/UTOPIA/POS DC Electrical Characteristics

Table 17. ATM/UTOPIA/POS DC Electrical Characteristics

Characteristic

Symbol

Min

Max

Unit

Supply voltage 3.3 V

Input high voltage

Input low voltage

V

3.135

2.0

3.465

0.8

V

DDIO

V

IH

V

I

–0.3

–30

2.4

V

IL

Input leakage current, V = supply voltage

30

μA

V

IN

1

Signal low input current, V = 0.4 V

I

30

IL

L

1

Signal high input current, V = 2.4 V

I

30

IH

H

Output high voltage, I = –4 mA,

V

3.465

0.5

OH

Output low voltage, I = 4 mA

V

—

V

OL

Notes: 1. Not tested. Guaranteed by design.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

33

Electrical Characteristics

2.6.7

SPI DC Electrical Characteristics

Table 18 provides the SPI DC electrical characteristics.

Table 18. SPI DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

Input low voltage

Input current

V

2.0

OV +0.3

V

IH

DD

V

I

–0.3

0.8

30

—

IL

μA

V

IN

Output high voltage

Output low voltage

V

I

= –4.0 mA

2.4

—

OH

V

I

= 4.0 mA

0.5

V

OL

2

2.6.8

GPIO, UART, TIMER, EE, STOP_BS, I C, IRQn, NMI_OUT, INT_OUT,

CLKIN, JTAG Ports DC Electrical Characteristics

Table 19. GPIO, UART, Timer, EE, STOP_BS, I²C, IRQn, NMI_OUT, INT_OUT, CLKIN, and JTAG Port

DC Electrical Characteristics

Characteristic

Symbol

Min

Max

Unit

Supply voltage 3.3 V

Input high voltage

Input low voltage

V

3.135

2.0

3.465

0.8

V

DDIO

V

IH

V

I

–0;3

–30

2.4

V

IL

Input leakage current, V = supply voltage

30

μA

V

IN

Tri-state (high impedance off state) leakage current, V = supply voltage

I

30

IN

OZ

2

Signal low input current, V = 0.4 V

I

30

IL

L

2

Signal high input current, V = 2.0 V

I

30

IH

H

Output high voltage, I = –2 mA,

V

3.465

OH

except open drain pins

Output low voltage, I = 3.2 mA

V

—

0.4

V

OL

Notes: 1. See Figure 6 for undershoot and overshoot voltages.

2. Not tested. Guaranteed by design.

V_DDIO+ 17%

V_IH

V

_DDIO+ 5%

V_DDIO

GND

GND – 0.3 V

GND – 0.7 V

V_IL

Must not exceed 10% of clock period

Figure 6. Overshoot/Undershoot Voltage for V_IHand V_IL

2.7

AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

34

Freescale Semiconductor

Electrical Characteristics

2.7.1

Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.7.2

describes the clocking characteristics. Section 2.7.3 describes the reset and power-up characteristics. You must use the

following guidelines when starting up an MSC8144E device:

•

PORESET and TRST must be asserted externally for the duration of the power-up sequence using the V_DDIO(3.3 V)

supply. See Table 24 for timing. TRST deassertion does not have to be synchronized with PORESET deassertion.

During functional operation when JTAG is not used, TRST can be asserted and remain asserted after the power ramp.

Note: For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the

V_DDM3IO(2.5 V) supply. See Section 3.1.1, Power-on Sequence for additional design information.

•

CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation

(see Figure 7). 32 cycles should be accounted only after V_DDIOreaches its nominal value.

•

CLKIN and PCI_CLK_IN should either be stable low during the power-up of V_DDIOsupply and start their swings after

power-up or should swing within V_DDIOrange during V_DDIOpower-up., so their amplitude grows as V_DDIOgrows

during power-up.

Figure 7 shows a sequence in which V_DDIOis raised after V_DDand CLKIN begins to toggle with the raise of V_DDIOsupply.

V

= Nominal

DDIO

V_DD= Nominal

1

V

Nominal

3.3 V

1.0 V

DDIO

V_DDNominal

Time

PORESET/TRST asserted

V_DDapplied

PORESET

CLKIN starts toggling

applied

V

DDIO

Figure 7. Start-Up Sequence with V_DDRaised Before V_DDIOwith CLKIN Started with V_DDIO

2.7.2

Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 20 shows the maximum frequency values for

internal (Core, Reference, Bus and DSI) and external (CLKIN, PCI_CLK_IN and CLKOUT. The user must ensure that

maximum frequency values are not exceeded.

Table 20. Clock Frequencies

Characteristic

Symbol

MIN

Max

Unit

CLKIN frequency

F

25

40

150

60

MHz

%

CLKIN

PCI_CLK_IN

PCI_CLK_IN frequency

CLKIN duty cycle

F

D

CLKIN

PCI_CLK_IN duty cycle

D

60

%

PCI_CLK_IN

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

35

Electrical Characteristics

Table 21. Clock Parameters

Characteristic

Min

Max

Unit

CLKIN slew rate (20%-80%)

1

—

V/ns

PCI_CLK_IN slew rate (20%-80%)

2.7.3

Reset Timing

The MSC8144E has several inputs to the reset logic:

•

Power-on reset (PORESET)

External hard reset (HRESET)

External soft reset (SRESET)

Software watchdog reset

JTAG reset

RapidIO reset

Software hard reset

Software soft reset

All MSC8144E reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.

The reset status register indicates the most recent sources to cause a reset. Table 22 describes the reset sources.

Table 22. Reset Sources

Name

Direction

Description

Power-on reset

(PORESET)

Input

Initiates the power-on reset flow that resets the MSC8144E and configures various attributes of the

MSC8144E. On PORESET, the entire MSC8144E device is reset. All PLLs states is reset, HRESET

and SRESET are driven, the extended cores are reset, and system configuration is sampled. The

reset source and word are configured only when PORESET is asserted.

External hard

reset (HRESET)

Input/ Output

Initiates the hard reset flow that configures various attributes of the MSC8144E. While HRESET is

asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and

SRESET are driven, the extended cores are reset, and system configuration is sampled. Note that

the RCW (reset Configuration Word) is not reloaded during HRESET assertion after out of power on

reset sequence. The reset configuration word is described in the Reset chapter in the MSC8144E

Reference Manual.

External soft reset

(SRESET)

Input/ Output

Internal

Initiates the soft reset flow. The MSC8144E detects an external assertion of SRESET only if it occurs

while the MSC8144E is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET

is driven, the extended cores are reset, and system configuration is maintained.

Host reset

command through

the TAP

When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the

soft reset signal and an internal soft reset sequence is generated.

Software

watchdog reset

Internal

When the MSC8144E watchdog count reaches zero, a software watchdog reset is signalled. The

enabled software watchdog event then generates an internal hard reset sequence.

RapidIO reset

When the RapidIO logic asserts the RapidIO hard reset signal, it generates an internal hard reset

sequence.

Software hard

reset

A hard reset sequence can be initialized by writing to a memory mapped register (RCR)

Software soft reset

A soft reset sequence can be initialized by writing to a memory mapped register (RCR)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

36

Freescale Semiconductor

Electrical Characteristics

Table 23 summarizes the reset actions that occur as a result of the different reset sources.

Table 23. Reset Actions for Each Reset Source

Power-OnReset

Hard Reset (HRESET)

(PORESET)

Soft Reset (SRESET)

Reset Action/Reset Source

External or Internal

External or

internal

Software

JTAG Command:

EXTEST, CLAMP, or

HIGHZ

External only

(Software Watchdog,

Software or RapidIO)

Configuration pins sampled (Refer to

Yes

No

Section 2.7.3.2 for details).

PLL state reset

Yes

No

Select reset configuration source

System reset configuration write

HRESET driven

No

Yes

No

IPBus modules reset (TDM, UART, SWT,

DDRC, IPBus master, GIC, HS, and GPIO)

Yes

SRESET driven

Yes

Depends on command

Yes

Extended cores reset

CLASS registers reset

Some

Some registers

registers

Timers, Performance Monitor

Packet Processor, PCI, DMA

Yes

No

Most

Most registers

registers

2.7.3.1

Power-On Reset (PORESET) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 32 CLKIN cycles after

V_DDand V_DDIOare both at their nominal levels.

2.7.3.2

Reset Configuration

The MSC8144E has two mechanisms for writing the reset configuration:

•

Through the I²C port

Through external pins

Through internal hard coded

Twenty-three signals (see Section 1 for signal description details) are sampled during the power-on reset sequence to define the

Reset Word Configuration Source and operating conditions:

•

RCW_SRC[2–0]

RC[16–0]

The RCFG_CLKIN_RNG pin must be valid during power-on or hard reset sequence. The STOP_BS pin must be always valid

and is also sampled during power-on reset sequence for RCW loading from an I²C EEPROM.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

37

Electrical Characteristics

2.7.3.3 Reset Timing Tables

Table 24 and Figure 8 describe the reset timing for a reset configuration.

Table 24. Timing for a Reset Configuration Write

No.

Characteristics

Expression

Max

Min

Unit

1

Required external PORESET duration minimum

32/CLKIN

•

25 MHz <= CLKIN < 44 MHz

44 MHz <= CLKIN < 66 MHz

66 MHz <= CLKIN < 100 MHz

100 MHz <= CLKIN < 133 MHz

1280

728

485

320

727

484

320

241

ns

2

Delay from de-assertion of external PORESET to HRESET deassertion for

external pins and hard coded RCW

•

25 MHz <= CLKIN < 66 MHz

66 MHz <= CLKIN <= 133 MHz

15369/CLKIN

34825/CLKIN

615

528

233

262

μs

Delay from de-assertion of external PORESET to HRESET deassertion for

2

loading RCW the I C interface

•

25 MHz <= CLKIN < 44 MHz

44 MHz <= CLKIN < 66 MHz

66 MHz <= CLKIN < 100 MHz

100 MHz <= CLKIN < 133 MHz

92545/CLKIN

107435/CLKIN

124208/CLKIN

157880/CLKIN

3702

2441

1882

1579

2103

1627

1242

1187

μs

3

Delay from HRESET deassertion to SRESET deassertion

REFCLK = 25 MHz to 133 MHz

•

16/CLKIN

640

120

ns

Note:

Timings are not tested, but are guaranteed by design.

RCW_SRC2,RCW_SRC1,RCW_SRC0,STOP_BS and RCFG_CLKIN_RNG

pins must be valid

1

PORESET

Input

HRESET

Output (I/O)

2

SRESET

Output (I/O)

Reset configuration write

sequence during this

period.

3

Figure 8. Timing for a Reset Configuration Write

See also Reset Errata for PLL lock and reset duration.

2.7.4

DDR SDRAM AC Timing Specifications

This section describes the AC electrical characteristics for the DDR SDRAM interface.

2.7.4.1

DDR SDRAM Input Timings

Table 25 provides the input AC timing specifications for the DDR SDRAM when V_DDDDR(typ) = 2.5 V.

Table 25. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

Parameter

Symbol

Min

Max

– 0.31

REF

Unit

AC input low voltage

V

—

MV

V

IL

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

38

Freescale Semiconductor

Electrical Characteristics

Table 25. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface (continued)

Parameter

Symbol

Min

+ 0.31

REF

Max

Unit

AC input high voltage

Note: At recommended operating conditions with V

V

MV

—

V

IH

of 2.5 5%.

DDDDR

Table 26 provides the input AC timing specifications for the DDR SDRAM when V_DDDDR(typ) = 1.8 V.

Table 26. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

Parameter

Symbol

Min

Max

– 0.25

REF

Unit

AC input low voltage

AC input high voltage

V

—

MV

V

IL

V

MV

+ 0.25

REF

—

IH

Note:

At recommended operating conditions with V

of 1.8 5%.

DDDDR

Table 27 provides the input AC timing specifications for the DDR SDRAM interface.

Table 27. DDR SDRAM Input AC Timing Specifications

Parameter

Symbol

Min

Max

Unit

1

Controller Skew for MDQS—MDQ/MECC/MDM

t

CISKEW

•

400 MHz

333 MHz

266 MHz

200 MHz

–365

–390

–428

–490

365

390

428

490

ps

Notes: 1.

t

represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is

CISKEW

captured with MDQS[n]. Subtract this value from the total timing budget.

2. At recommended operating conditions with V (1.8 V or 2.5 V) 5%

DDDDR

2.7.4.2

DDR SDRAM Output AC Timing Specifications

Table 28 provides the output AC timing specifications for the DDR SDRAM interface.

Table 28. DDR SDRAM Output AC Timing Specifications

1

Parameter

Symbol

Min

Max

Unit

2

MCK[n] cycle time, (MCK[n]/MCK[n] crossing)

t

3

10

ns

MCK

3

ADDR/CMD output setup with respect to MCK

t

DDKHAS

DDKHAX

DDKHCS

DDKHCX

•

400 MHz

333 MHz

266 MHz

200 MHz

1.95

2.40

3.15

4.20

—

ns

3

ADDR/CMD output hold with respect to MCK

t

•

400 MHz

333 MHz

266 MHz

200 MHz

1.95

2.40

3.15

4.20

—

ns

3

MCSn output setup with respect to MCK

t

•

400 MHz

333 MHz

266 MHz

200 MHz

1.95

2.40

3.15

4.20

—

ns

3

MCSn output hold with respect to MCK

•

400 MHz

333 MHz

266 MHz

200 MHz

1.95

2.40

3.15

4.20

—

ns

4

MCK to MDQS Skew

t

–0.6

0.6

ns

DDKHMH

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

39

Electrical Characteristics

Table 28. DDR SDRAM Output AC Timing Specifications (continued)

1

Parameter

Symbol

Min

Max

Unit

5

MDQ/MECC/MDM output setup with respect to MDQS

t

DDKHDS,

•

400 MHz

333 MHz

266 MHz

200 MHz

t

700

900

1100

1200

—

ps

DDKLDS

5

MDQ/MECC/MDM output hold with respect to MDQS

t

DDKHDX,

•

400 MHz

333 MHz

266 MHz

200 MHz

t

700

900

1100

1200

—

ps

DDKLDX

6

MDQS preamble start

t

–0.5 × t

– 0.6

–0.5 × t +0.6

MCK

ns

DDKHMP

MCK

6

MDQS epilogue end

t

–0.6

0.6

DDKHME

Notes: 1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state) (reference)(state)

inputs and t

for outputs. Output hold time can be read as DDR timing

(first two letters of functional block)(reference)(state)(signal)(state)

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H) state until outputs

t

DDKHAS

MCK

(A) are setup (S) or output valid time. Also, t

symbolizes DDR timing (DD) for the time t

memory clock reference

DDKLDX

MCK

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the

ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by

1/2 applied cycle.

4. Note that t

follows the symbol conventions described in note 1. For example, t

describes the DDR timing (DD)

DDKHMH

from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t

can be modified through control

DDKHMH

of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the

CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. See the MSC8144 Reference Manual for a description and understanding of the timing modifications

enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t

follows the

DDKHMP

symbol conventions described in note 1.

7. At recommended operating conditions with V

(1.8 V or 2.5 V) 5%.

DDDDR

Figure 9 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t_DDKHMH).

MCK[n]

t_MCK

t_{DDKHMHmax) = 0.6 ns}

MDQS

t_{DDKHMH(min) = –0.6 ns}

MDQS

Figure 9. Timing for t_DDKHMH

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

40

Freescale Semiconductor

Electrical Characteristics

Figure 10 shows the DDR SDRAM output timing diagram.

MCK[n]

t_MCK

t_DDKHAS, t_DDKHCS

t_DDKHAX,t_DDKHCX

ADDR/CMD

Write A0

t_DDKHMP

NOOP

t_DDKHMH

MDQS[n]

MDQ[x]

t_DDKHME

t_DDKHDS

t_DDKLDS

D0

D1

t_DDKLDX

t_DDKHDX

Figure 10. DDR SDRAM Output Timing

Figure 11 provides the AC test load for the DDR bus.

V_DDDDR/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 11. DDR AC Test Load

2.7.5

Serial RapidIO Timing and SGMII Timing

2.7.5.1

AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK

Table 29 lists AC requirements.

Table 29. SDn_REF_CLK and SDn_REF_CLK AC Requirements

Parameter Description

Symbol

Min

Typical

Max

Units

Comments

REFCLK cycle time

t

—

10 (8, 6.4)

—

ns

8 ns applies only to serial RapidIO system

with 125-MHz reference clock. 6.4 ns

applies only to serial RapidIO systems with

a 156.25 MHz reference clock.

REF

Note:

SGMII uses the 8 ns (125 MHz)

value only.

REFCLK cycle-to-cycle

jitter

t

—

80

40

ps

Difference in the period of any two

adjacent REFCLK cycles

REFCJ

Phase jitter

t

–40

Deviation in edge location with respect to

mean edge location

REFPJ

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

41

Electrical Characteristics

2.7.5.2

Signal Definitions

LP-Serial links use differential signaling. This section defines terms used in the description and specification of differential

signals. Figure 12 shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD)

or a receiver input (RD and RD). Each signal swings between voltage levels A and B, where A > B.

TD or RD

A

TD or RD

B

Differential Peak-Peak = 2

× (A – B)

Figure 12. Differential V_PPof Transmitter or Receiver

Note: This explanation uses generic TD/TD/RD/RD signal names. These correspond to SRIO_TXD/SRIO_TXD/

SRIO_RXD/SRIO_RXD respectively.

Using these waveforms, the definitions are as follows:

1. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a peak-to-peak voltage

(V_PP) swing of A – B.

2. The differential output signal of the transmitter, V_OD, is defined as V_TD– V_TD

3. The differential input signal of the receiver, V_ID, is defined as V_RD– V_RD

.

4. The differential output signal of the transmitter and the differential input signal of the receiver each range from A – B

to –(A – B).

5. The peak value of the differential transmitter output signal and the differential receiver input signal is A – B.

6. The value of the differential transmitter output signal and the differential receiver input signal is 2 × (A – B) V_PP.

To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common

mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values,

the peak-to-peak voltage swing of the signals TD and TD is 500 mV_PP. The differential output signal ranges between 500 mV

and –500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV_PP.

Note: AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud

rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI

electrical interface specified in Clause 47 of IEEE™ Std 802.3ae-2002™. XAUI has similar application goals to

serial RapidIO. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for

XAUI, suitably modified for applications at the baud intervals and reaches described herein.

2.7.5.3

Equalization

With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such

as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye

opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be

used. The most common equalization techniques that can be used are:

•

A passive high pass filter network placed at the receiver. This is often referred to as passive equalization.

The use of active circuits in the receiver. This is often referred to as adaptive equalization.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

42

Freescale Semiconductor

Electrical Characteristics

2.7.5.4

Transmitter Specifications

LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. The differential return

loss, S11, of the transmitter in each case shall be better than

•

–10 dB for (baud frequency)/10 < freq(f) < 625 MHz, and

–10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ freq(f) ≤ baud frequency

The reference impedance for the differential return loss measurements is 100 Ω resistive. Differential return loss includes

contributions from internal circuitry, packaging, and any external components related to the driver. The output impedance

requirement applies to all valid output levels. It is recommended that the 20–80% rise/fall time of the transmitter, as measured

at the transmitter output, have a minimum value 60 ps in each case. It is also recommended that the timing skew at the output

of an LP-Serial transmitter between the two signals comprising a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50

GB, and 15 ps at 3.125 GB.

Table 30. Short Run Transmitter AC Timing Specifications—1.25 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output Voltage,

V

–0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential Output Voltage

Deterministic Jitter

Total Jitter

V

500

800

1000

0.17

0.35

1000

mV

DIFFPP

PP

J

UI

D

J

T

Multiple output skew

S

ps

Skew at the transmitter output between lanes of a

multilane link

MO

Unit Interval

UI

800

ps

100 ppm

Table 31. Short Run Transmitter AC Timing Specifications—2.5 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output Voltage,

V

–0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential Output Voltage

Deterministic Jitter

Total Jitter

V

500

400

1000

0.17

0.35

1000

mV

DIFFPP

PP

J

UI

D

J

T

Multiple Output skew

S

ps

Skew at the transmitter output between lanes of a

multilane link

MO

Unit Interval

UI

400

ps

100 ppm

Table 32. Short Run Transmitter AC Timing Specifications—3.125 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output Voltage,

V

-0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential Output Voltage

Deterministic Jitter

Total Jitter

V

500

320

1000

0.17

0.35

1000

mV

DIFFPP

PP

J

UI

D

J

T

Multiple output skew

S

ps

Skew at the transmitter output between lanes of a

multilane link

MO

Unit Interval

UI

320

ps

100 ppm

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

43

Electrical Characteristics

Table 33. Long Run Transmitter AC Timing Specifications—1.25 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output Voltage,

V

-0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential Output Voltage

Deterministic Jitter

Total Jitter

V

800

1600

0.17

0.35

1000

mV

DIFFPP

PP

J

UI

D

J

T

Multiple output skew

S

ps

Skew at the transmitter output between lanes of a

multilane link

MO

Unit Interval

UI

800

ps

100 ppm

Table 34. Long Run Transmitter AC Timing Specifications—2.5 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output Voltage,

V

-0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential Output Voltage

Deterministic Jitter

Total Jitter

V

800

400

1600

0.17

0.35

1000

mV

DIFFPP

PP

J

UI

D

J

T

Multiple output skew

S

ps

Skew at the transmitter output between lanes of a

multilane link

MO

Unit Interval

UI

400

ps

100 ppm

Table 35. Long Run Transmitter AC Timing Specifications—3.125 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Output Voltage,

V

-0.40

2.30

V

Voltage relative to COMMON of either signal

comprising a differential pair

O

Differential Output Voltage

Deterministic Jitter

Total Jitter

V

800

1600

0.17

0.35

1000

mV

DIFFPP

PP

J

UI

D

J

T

Multiple output skew

S

ps

Skew at the transmitter output between lanes of a

multilane link

MO

Unit Interval

UI

320

ps

100 ppm

For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall

entirely within the unshaded portion of the transmitter output compliance mask shown in Figure 13 with the parameters

specified in Table 36 when measured at the output pins of the device and the device is driving a 100 Ω 5% differential resistive

load. The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce

inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or

minimized.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

44

Freescale Semiconductor

Electrical Characteristics

V_DIFFmax

V_DIFFmin

0

-VDIFF min

-VDIFF max

0

A

B

1-B

1-A

1

Time in UI

Figure 13. Transmitter Output Compliance Mask

Table 36. Transmitter Differential Output Eye Diagram Parameters

Transmitter Type

1.25 GBaud short range

V

min (mV)

V

max (mV)

A (UI)

B (UI)

DIFF

250

400

250

400

250

400

500

800

500

800

500

800

0.175

0.39

1.25 GBaud long range

2.5 GBaud short range

2.5 GBaud long range

3.125 GBaud short range

3.125 GBaud long range

2.7.5.5

Receiver Specifications

LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section. Receiver input impedance

shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to 0.8

× baud frequency. This includes contributions from internal circuitry, the package, and any external components related to the

receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is

100 Ω resistive for differential return loss and 25 Ω resistive for common mode.

Table 37. Receiver AC Timing Specifications—1.25 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Differential Input Voltage

V

J

200

0.37

0.55

1600

mV

Measured at receiver

IN

PP

Deterministic Jitter Tolerance

UI

D

Combined Deterministic and Random

Jitter Tolerance

J

DR

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

45

Electrical Characteristics

Table 37. Receiver AC Timing Specifications—1.25 GBaud (continued)

Range

Characteristic

Symbol

Unit

Notes

Min

0.65

Max

Total Jitter Tolerance

J

UI

Measured at receiver. Total jitter is composed of

three components, deterministic jitter, random jitter

and single frequency sinusoidal jitter. The sinusoidal

jitter may have any amplitude and frequency in the

unshaded region of Figure 14. The sinusoidal jitter

component is included to ensure margin for low

frequency jitter, wander, noise, crosstalk and other

variable system effects.

T

PP

Multiple Input Skew

S

24

ns

Skew at the receiver input between lanes of a

multilane link

MI

–12

Bit Error Rate

Unit Interval

BER

UI

10

800

ps

100 ppm

Table 38. Receiver AC Timing Specifications—2.5 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Differential Input Voltage

V

J

200

0.37

0.55

1600

mV

Measured at receiver

IN

PP

Deterministic Jitter Tolerance

UI

D

Combined Deterministic and Random

Jitter Tolerance

J

DR

Total Jitter Tolerance

J

0.65

UI

Measured at receiver. Total jitter is composed of

three components, deterministic jitter, random jitter

and single frequency sinusoidal jitter. The sinusoidal

jitter may have any amplitude and frequency in the

unshaded region of Figure 14. The sinusoidal jitter

component is included to ensure margin for low

frequency jitter, wander, noise, crosstalk and other

variable system effects.

T

PP

Multiple Input Skew

S

24

ns

Skew at the receiver input between lanes of a

multilane link

MI

–12

Bit Error Rate

Unit Interval

BER

UI

10

400

ps

100 ppm

Table 39. Receiver AC Timing Specifications—3.125 GBaud

Range

Characteristic

Symbol

Unit

Notes

Min

Max

Differential Input Voltage

V

J

200

0.37

0.55

1600

mV

Measured at receiver

IN

PP

Deterministic Jitter Tolerance

UI

D

Combined Deterministic and Random

Jitter Tolerance

J

DR

Total Jitter Tolerance

J

0.65

UI

Measured at receiver. Total jitter is composed of

three components, deterministic jitter, random jitter

and single frequency sinusoidal jitter. The sinusoidal

jitter may have any amplitude and frequency in the

unshaded region of Figure 14. The sinusoidal jitter

component is included to ensure margin for low

frequency jitter, wander, noise, crosstalk and other

variable system effects.

T

PP

Multiple Input Skew

S

22

ns

Skew at the receiver input between lanes of a

multilane link

MI

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

46

Freescale Semiconductor

Electrical Characteristics

Table 39. Receiver AC Timing Specifications—3.125 GBaud (continued)

Range

Characteristic

Symbol

Unit

Notes

Min

Max

–12

Bit Error Rate

Unit Interval

BER

UI

10

320

ps

100 ppm

8.5 UI p-p

Sinusoidal

Jitter

Amplitude

0.10 UI p-p

22.1 kHz

Frequency

1.875 MHz

20 MHz

Figure 14. Single Frequency Sinusoidal Jitter Limits

2.7.5.6

Receiver Eye Diagrams

For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding bit error rate

specification (Table 37, Table 38, and Table 39) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter)

falls entirely within the unshaded portion of the receiver input compliance mask shown in Figure 15 with the parameters

specified in Table 40. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the

device replaced with a 100 Ω 5% differential resistive load.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

47

Electrical Characteristics

V_DIFFmax

V_DIFFmin

0

–V_DIFFmin

–V_DIFFmax

0

1

A

B

1 – B

1 – A

Time (UI)

Figure 15. Receiver Input Compliance Mask

Table 40. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter

Receiver Type

V

min (mV)

V

max (mV)

DIFF

A (UI)

B (UI)

DIFF

1.25 GBaud

2.5 GBaud

100

800

0.275

0.400

3.125 GBaud

2.7.5.7

Measurement and Test Requirements

Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE Std.

802.3ae-2002™, the measurement and test requirements defined here are similarly guided by Clause 47. In addition, the CJPAT

test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter

measurements. Annex 48B of IEEE Std. 802.3ae-2002 is recommended as a reference for additional information on jitter test

methods.

2.7.5.8

Eye Template Measurements

For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (baud

frequency)/1667 is applied to the jitter. The data pattern for template measurements is the continuous jitter test pattern (CJPAT)

defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive

directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined

in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0.

The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10^–12. The eye pattern

shall be measured with AC coupling and the compliance template centered at 0 Volts differential. The left and right edges of

the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 Ω

resistive 5% differential to 2.5 GHz.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

48

Freescale Semiconductor

Electrical Characteristics

2.7.5.9

Jitter Test Measurements

For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud frequency)/1667 is

applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in

Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and

opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A.

Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be

measured with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance

setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE Std.

802.3ae.

2.7.5.10 Transmit Jitter

Transmit jitter is measured at the driver output when terminated into a load of 100 Ω resistive 5% differential to 2.5 GHz.

2.7.5.11 Jitter Tolerance

Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum

of deterministic and random jitter defined in Section 2.7.5.9 and then adjusting the signal amplitude until the data eye contacts

the 6 points of the minimum eye opening of the receive template shown in Figure 15 and Table 40. Note that for this to occur,

the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)

about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using

a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter

specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.

2.7.6

PCI Timing

This section describes the general AC timing parameters of the PCI bus. Table 41 provides the PCI AC timing specifications.

Table 41. PCI AC Timing Specifications

33 MHz

66 MHz

Parameter

Symbol

Unit

Min

Max

Min

Max

Output delay

t

2.0

—

11.0

—

1.0

—

6.0

—

14

—

40

—

ns

PCVAL

High-Z to Valid Output delay

Valid to High-Z Output delay

Input setup

t

PCON

t

28

—

ns

PCOFF

t

7.0

0

3.0

0

ns

PCSU

Input hold

t

—

ns

PCH

Reset active time after PCI_CLK_IN stable

Reset active to output float delay

Reset active time after power stable

HRESET high to first Configuration Access

t

100

—

100

—

μs

PCRST-CLK

PCRST-OFF

40

—

ns

t

1

ms

clocks

PCRST

t

32M

—

32M

PCRHFA

Notes: 1. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.

2. All PCI signals are measured from 0.5 × V

of the rising edge of PCI_CLK_IN to 0.4 × V

of the signal in question for

DDIO

3.3-V PCI signaling levels.

3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

5. The reset assertion timing requirement for HRESET is in Table 24 and Figure 8

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

49

Electrical Characteristics

Figure 16 provides the AC test load for the PCI.

Output

V_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 16. PCI AC Test Load

Figure 17 shows the PCI input AC timing conditions.

CLK

t_PCSU

t_PCH

Input

Figure 17. PCI Input AC Timing Measurement Conditions

Figure 18 shows the PCI output AC timing conditions.

CLK

t_PCVAL

Output Delay

t_PCOFF

t_PCON

High-Impedance

Output

Figure 18. PCI Output AC Timing Measurement Condition

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

50

Freescale Semiconductor

Electrical Characteristics

2.7.7

TDM Timing

Table 42. TDM Timing

Characteristic

Symbol

Expression

Min

Max

Units

1

TDMxRCLK/TDMxTCLK

t

TC

16

7

—

ns

TDMC

4

TDMxRCLK/TDMxTCLK high pulse width

TDMxRCLK/TDMxTCLK low pulse width

t

(0.5 0.1) × TC

TDMCH

t

7

TDMCL

TDM receive all input set-up time related to TDMxRCLK

TDMxTSYN input set-up time related to TDMxTCLK in TSO=0 mode

t

3.6

TDMVKH

TDM receive all input hold time related to TDMxRCLK

1.9

—

ns

TDMXKH

TDMxTSYN input hold time related to TDMxTCLK in TSO=0 mode

2

TDMxTCLK high to TDMxTDAT output active

t

2.5

—

9.8

—

ns

TDMDHOX

TDMDHOV

2

TDMxTCLK high to TDMxTDAT output valid

3

All output hold time (except TDMxTSYN)

t

2.5

—

TDMHOX

TDMDHOZ

TDMSHOV

TDMSHOX

2

TDMxTCLK high to TDMxTDAT output high impedance

t

9.8

9.25

—

2

TDMxTCLK high to TDMxTSYN output valid

—

3

TDMxTSYN output hold time

2.0

Notes: 1. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.

2. Values are based on 20 pF capacitive load.

3. Values are based on 10 pF capacitive load.

4. The expression is for common calculations only.

Figure 19 shows the TDM input AC timing.

t

TDMC

t

TDMCL

TDMCH

TDMxRCLK

t

TDMXKH

t

TDMVKH

TDMxRDAT

t

TDMXKH

t

TDMVKH

TDMxRSYN

Figure 19. TDM Inputs Signals

Note: For some TDM modes receive data and receive sync are being input on other pins. This timing is valid for them as well.

See the MSC8144E Reference Manual.

Figure 20 shows TDMxTSYN AC timing in TSO=0 mode.

TDMxTCLK

t

TDMXKH

t

TDMVKH

TDMxTSYN

Figure 20. TDMxTSYN in TSO=0 mode

Figure 21 shows the TDM Output AC timing

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

51

t

TDMC

t

TDMCL

TDMCH

TDMxTCLK

TDMxTDAT

TDMxTSYN

t

TDMDHOZ

t

TDMDHOV

t

TDMHOX

t

TDMDHOX

t

TDMSHOV

t

TDMSHOX

Figure 21. TDM Output Signals

Note: For some TDM modes transmit data is being output on other pins. This timing is valid for it as well. See the MSC8144E

Reference Manual

2.7.8

UART Timing

Table 43. UART Timing

Characteristics

Symbol

Expression

Min

Max

Unit

URXD and UTXD inputs high/low duration

URXD and UTXD inputs rise/fall time

UTXD output rise/fall time

T

16 × T

160

—

6

ns

UREFCLK

REFCLK

T

UAVKH

UAVXH

5.5

Note:

T

= T

is guaranteed by design.

REFCLK

UREFCLK

Figure 22 shows the UART input AC timing

T

UAVKH

T

UAVKH

UTXD, URXD

inputs

T

UREFCLK

T

UREFCLK

Figure 22. UART Input Timing

Figure 23 shows the UART output AC timing

T

UAVXH

T

UAVXH

UTXD output

Figure 23. UART Output Timing

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

52

Freescale Semiconductor

2.7.9

Timer Timing

Table 44. Timer Timing

Characteristics

Symbol

Min

Unit

TIMERx frequency

T

10.0

4.0

ns

TMREFCLK

TIMERx Input high phase

TIMERx Output low phase

T

TMCH

T

4.0

TMCL

Figure 24 shows the timer input AC timing

T

TMREFCLK

T

T_TMCH

TMCL

TIMERx (Input)

Figure 24. Timer Timing

2.7.10 Ethernet Timing

This section describes the AC electrical characteristics for the Ethernet interface.

There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is

a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8144E

Reference Manual.

2.7.10.1 Management Interface Timing

Table 45. Ethernet Controller Management Interface Timing

Characteristics

Symbol

Min

Max

Unit

ETHMDC clock pulse width high

t

32

10

7

—

70

—

10

ns

MDCH

2

ETHMDC to ETHMDIO delay

t

MDKHDX

MDDVKH

MDDXKH

ETHMDIO to ETHMDC rising edge set-up time

ETHMDC rising edge to ETHMDIO hold time

ETHMDC rise time.

0

t

—

MDCR

ETHMDC fall time.

t

MDHF

Notes: 1. Program the ETHMDC frequency (f

) to a maximum value of 2.5 MHz (400 ns period for t

). The value depends on the

MDC

source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz, to

achieve f = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8144E Reference Manual for

MDC

configuration details.

2. The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of

333 MHz, the delay is 58 ns.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

53

t

MDC

t

MDCR

ETHMDC

t

MDCH

t

MDHF

ETHMDIO

(Input)

t

MDDVKH

MDDXKH

ETHMDIO

(Output)

t

MDKHDX

Figure 25. MII Management Interface Timing

2.7.10.2 MII Transmit AC Timing Specifications

Table 46 provides the MII transmit AC timing specifications.

Table 46. MII Transmit AC Timing Specifications

1

Parameter/Condition

Symbol

Min

Max

Unit

TX_CLK duty cycle

t

35

0

65

25

%

ns

MTXH/ MTX

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

TX_CLK data clock rise

t

MTKHDX

t

1.0

4.0

MTXR

TX_CLK data clock fall

t

MTXF

Notes: 1. Typical TX_CLK period (t

) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.

MTX

2. Program GCR4 as 0x00030CC3.

Figure 26 shows the MII transmit AC timing diagram.

t_MTX

t_MTXR

TX_CLK

t_MTXH

t_MTXF

TXD[3:0]

TX_EN

TX_ER

t_MTKHDX

Figure 26. MII Transmit AC Timing

2.7.10.3 MII Receive AC Timing Specifications

Table 47 provides the MII receive AC timing specifications.

Table 47. MII Receive AC Timing Specifications

1

Parameter/Condition

Symbol

/t

Min

Max

Unit

RX_CLK duty cycle

t

35

65

%

MRXH MRX

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

54

Freescale Semiconductor

Table 47. MII Receive AC Timing Specifications (continued)

1

Parameter/Condition

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

Symbol

Min

Max

Unit

t

10.0

2

—

ns

MRDVKH

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise

MRDXKH

t

1.0

4.0

MRXR

RX_CLK clock fall time

t

MRXF

Notes: 1. Typical RX_CLK period (t

) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.

MRX

2. Program GCR4 as 0x00030CC3.

Figure 27 provides the AC test load.

Output

V_DDGE/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 27. AC Test Load

Figure 28 shows the MII receive AC timing diagram.

t_MRXR

t_MRX

RX_CLK

t_MRXF

Valid Data

t_MRXH

RXD[3:0]

RX_DV

RX_ER

t_MRDVKH

t_MRDXKH

Figure 28. MII Receive AC Timing

2.7.10.4 RMII Transmit and Receive AC Timing Specifications

Table 48 provides the RMII transmit and receive AC timing specifications.

Table 48. RMII Transmit and Receive AC Timing Specifications

1

Parameter/Condition

Symbol

Min

Max

Unit

REF_CLK duty cycle

t

35

2

65

10

—

%

ns

RMXH/ RMX

REF_CLK to RMII data TXD[1–0], TX_EN delay

RXD[1–0], CRS_DV, RX_ER setup time to REF_CLK

RXD[1–0], CRS_DV, RX_ER hold time to REF_CLK

REF_CLK data clock rise

t

RMTKHDX

RMRDVKH

RMRDXKH

t

4.0

2.0

1.0

—

t

4.0

RMXR

REF_CLK data clock fall

t

RMXF

Typical REF_CLK clock period (t

) is 20 ns

RMX

Notes: 1. Typical REF_CLK clock period (t

2. Program GCR4 as 0x00001405

) is 20 ns

RMX

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

55

Figure 29 shows the RMII transmit and receive AC timing diagram.

t_RMXR

t_RMX

REF_CLK

t_RMXH

t_RMXF

TXD[1–0]

TX_EN

t_RMTKHDX

RXD[1–0]

CRS_DV

RX_ER

Valid Data

t_RMRDVKH

t_RMRDXKH

Figure 29. RMII Transmit and Receive AC Timing

Figure 30 provides the AC test load.

Output

V_DDGE/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 30. AC Test Load

2.7.10.5 SMII AC Timing Specification

Table 49. SMII Mode Signal Timing

Characteristics

Symbol

Min

Max

Unit

ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time

ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time

ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay

t

1.5

1.0

1.5

—

ns

SMDVKH

SMDXKH

t

5.0

SMXR

Notes: 1. Typical REF_CLK clock period is 8ns

2. Measured using a 5 pF load.

3. Measured using a 15 pF load

4. REF_CLK duty cycle is TBD.

5. Program GCR4 as 0x00002008

Figure 31 provides the AC test load.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

56

Freescale Semiconductor

ETHCLOCK

t

SMDVKH

SMDXKH

ETHSYNC_IN

ETHRXD

Valid

t

SMXR

ETHSYNC

ETHTXD

Valid

Figure 31. SMII Mode Signal Timing

2.7.10.6 RGMII AC Timing Specifications

Table 50 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.

Table 50. RGMII with On-Board Delay AC Timing Specifications

Parameter/Condition

Data to clock output skew (at transmitter)

Symbol

Min

Typ

Max

Unit

t

-0.5

0.9

7.2

45

40

—

0.5

2.6

8.8

55

ns

%

SKEWT

t

SKEWR

2

Data to clock input skew (at receiver)

3

Clock cycle duration

t

8.0

50

—

RGT

4, 5

Duty cycle for 1000Base-T

t

/t

RGTH RGT

3, 5

Duty cycle for 10BASE-T and 100BASE-TX

Rise time (20%–80%)

/t

60

%

RGTH RGT

t

0.75

—

ns

%

RGTR

Fall time (20%–80%)

t

—

RGTF

6

GTX_CLK125 reference clock period

GTX_CLK125 reference clock duty cycle

t

—

8.0

—

G12

t

/t

47

53

G125H G125

Notes: 1. At recommended operating conditions with LV of 2.5 V +/- 5%.

DD

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will

be added to the associated clock signal.

3. For 10 and 100 Mbps, t

scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.

RGT

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three t

between.

of the lowest speed transitioned

RGT

5. Duty cycle reference is L /2.

Vdd

6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.

7. GCR4 should be programmed as 0x00001004.

Table 51 presents the RGMII AC timing specification for applications required non-delayed clock on board.

Table 51. RGMII with No On-Board Delay AC Timing Specifications

Parameter/Condition

Data to clock output skew (at transmitter)

Symbol

Min

Typ

Max

Unit

t

–2.6

–0.5

7.2

45

—

–0.9

0.5

8.8

55

ns

%

SKEWT

t

SKEWR

2

Data to clock input skew (at receiver)

3

Clock cycle duration

t

8.0

50

—

RGT

4, 5

Duty cycle for 1000Base-T

t

/t

RGTH RGT

3, 5

Duty cycle for 10BASE-T and 100BASE-TX

Rise time (20%–80%)

/t

40

60

%

RGTH RGT

t

—

0.75

—

ns

RGTR

Fall time (20%–80%)

t

—

RGTF

6

GTX_CLK125 reference clock period

t

—

8.0

G12

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

57

Table 51. RGMII with No On-Board Delay AC Timing Specifications (continued)

Parameter/Condition

GTX_CLK125 reference clock duty cycle

Notes: 1. At recommended operating conditions with LV of 2.5 V +/- 5%.

Symbol

/t

Min

Typ

Max

Unit

t

47

—

53

%

G125H G125

DD

2. This implies that PC board design will require clocks to be routed with no additional trace delay

3. For 10 and 100 Mbps, t scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.

RGT

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three t

between.

of the lowest speed transitioned

RGT

5. Duty cycle reference is L /2.

Vdd

6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.

7. GCR4 should be programmed as 0x0004C130.

Figure 32 shows the RGMII AC timing and multiplexing diagrams.

t

RGT

t

RGTH

GTX_CLK

(At Transmitter)

t

SKEWT

TXD[8:5][3:0]

TXD[7:4][3:0]

TXD[8:5]

TXD[7:4]

TXD[3:0]

TXD[9]

TXERR

TXD[4]

TXEN

TX_CTL

t

SKEWR

TX_CLK

(At PHY)

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[8:5]

RXD[7:4]

RXD[3:0]

t

SKEWT

RXD[9]

RXERR

RXD[4]

RXDV

RX_CTL

t

SKEWR

RX_CLK

(At PHY)

Figure 32. RGMII AC Timing and Multiplexing s

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

58

Freescale Semiconductor

2.7.11 ATM/UTOPIA/POS Timing

Table 52 provides the ATM/UTOPIA/POS input and output AC timing specifications.

Table 52. ATM/UTOPIA/POS AC Timing (External Clock) Specifications

Characteristic

Outputs—External clock delay

Symbol

Min

Max

Unit

t

1

4

1

9

ns

UEKHOV

UEKHOX

Outputs—External clock High Impedance

Inputs—External clock input setup time

Inputs—External clock input hold time

t

UEIVKH

UEIXKH

t

Note:

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin. Although the specifications generally reference the rising edge of the clock, these AC timing diagrams also

apply when the falling edge is the active edge.

Figure 33 provides the AC test load for the ATM/UTOPIA/POS.

V_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 33. ATM/UTOPIA/POS AC Test Load

Figure 34 shows the ATM/UTOPIA/UTOPIA timing with external clock.

CLK (input)

Input Signals:

Output Signals:

t_UEIXKH

t_UEIVKH

t_UEKHOV

t_UEKHOX

Figure 34. ATM/UTOPIAPOS AC Timing (External Clock)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

59

2.7.12 SPI Timing

Table 52 provides the SPI input and output AC timing specifications.

Table 53. SPI AC Timing Specifications ¹

2

Characteristic

Symbol

Min

Max

Unit

SPI outputs valid—Master mode (internal clock) delay

SPI outputs hold—Master mode (internal clock) delay

SPI outputs valid—Slave mode (external clock) delay

SPI outputs hold—Slave mode (external clock) delay

SPI inputs—Master mode (internal clock input setup time

SPI inputs—Master mode (internal clock input hold time

SPI inputs—Slave mode (external clock) input setup time

SPI inputs—Slave mode (external clock) input hold time

Notes:

t

6

ns

NIKHOV

0.5

NIKHOX

t

8

NEKHOV

NEKHOX

2

4

0

4

2

t

NIIVKH

NIIXKH

t

NEIVKH

NEIXKH

t

1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.

Timings are measured at the pin.

2. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_NIKHOXsymbolizes the internal timing

(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

Figure 35 provides the AC test load for the SPI.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 35. SPI AC Test Load

Figure 36 through Figure 37 represent the AC timings from Table 52. Note that although the specifications generally reference

the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.

Figure 36 shows the SPI timings in slave mode (external clock).

SPICLK (Input)

t_NEIXKH

t_NEIVKH

Input Signals:

SPIMOSI

(See Note)

t_NEKHOX

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

Figure 36. SPI AC Timing in Slave Mode (External Clock)

Figure 37 shows the SPI timings in master mode (internal clock).

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

60

Freescale Semiconductor

SPICLK (Output)

t_NIIXKH

t_NIIVKH

Input Signals:

SPIMISO

(See Note)

t_NIKHOX

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

Figure 37. SPI AC Timing in Master Mode (Internal Clock)

2.7.13 Asynchronous Signal Timing

Table 54. Signal Timing

Characteristics

Symbol

Type

Min

1

Input

t

Asynchronous

One CLKIN cycle

IN

Output

Note:

t

Application dependent

OUT

1. Relevant for EE0, IRQ[15–0], and NMI only.

The following interfaces use the specified asynchronous signals:

•

GPIO. Signals GPIO[31–0], when used as GPIO signals, that is, when the alternate multiplexed special functions are

not selected.

Note: When used as a GPI, the input should be driven until it is acknowledged by the device; the GPIO input status is read

from a register.

•

EE port. Signals EE0, EE1, EE2_0, EE2_1, EE2_2, and EE2_3.

Boot function. Signal STOP_BS.

I²C interface. Signals I2C_SCL and I2C_SDA.

Interrupt inputs. Signals IRQ[15–0] and NMI.

Interrupt outputs. Signals INT_OUT and NMI_OUT (pulse width is 10 ns).

Figure 38 shows the behavior of the asynchronous signals.

t_IN

Input

t_OUT

Output

Figure 38. Asynchronous Signal Timing

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

61

2.7.14 JTAG Signals

Table 55. JTAG Timing

All frequencies

Characteristics

Symbol

Unit

Min

Max

TCK cycle time

t

36.0

15.0

—

ns

TCKX

TCKH

TCKR

TCK clock high phase measured at V = 1.6 V

t

M

TCK rise and fall times

3.0

—

Boundary scan input data set-up time

Boundary scan input data hold time

TCK fall to output data valid

TCK fall to output high impedance

TMS, TDI data set-up time

TMS, TDI data hold time

t

0.0

15.0

—

BSVKH

BSXKH

—

t

20.0

24.0

—

TCKHOV

t

—

TCKHOZ

t

0.0

5.0

—

TDIVKH

TDIXKH

TDOHOV

t

—

TCK fall to TDO data valid

TCK fall to TDO high impedance

TRST assert time

t

10.0

12.0

—

t

—

TDOHOZ

t

100.0

TRST

Note:

All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.

Figure 39 Shows the Test Clock Input Timing Diagram

t_TCKX

t

TCKH

V

M

V

M

TCK

(Input)

t

TCKR

t

TCKR

Figure 39. Test Clock Input Timing

Figure 40 Shows the boundary scan (JTAG) timing diagram.

TCK

(Input)

t

BSXKH

BSVKH

Data

Inputs

Input Data Valid

t

TCKHOV

Data

Outputs

Output Data Valid

t

TCKHOZ

Data

Outputs

Figure 40. Boundary Scan (JTAG) Timing

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

62

Freescale Semiconductor

Figure 41 Shows the test access port timing diagram

TCK

(Input)

t

TDIXKH

TDIVKH

TDI

TMS

Input Data Valid

(Input)

t

TDOHOV

TDO

(Output)

Output Data Valid

t

TDOHOZ

TDO

(Output)

Figure 41. Test Access Port Timing

Figure 42 Shows the TRST timing diagram.

TRST

(Input)

t

TRST

Figure 42. TRST Timing

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

63

Hardware Design Considerations

3

Hardware Design Considerations

The following sections discuss areas to consider when the MSC8144E device is designed into a system.

3.1

Start-up Sequencing Recommendations

3.1.1

Power-on Sequence

Use the following guidelines for power-on sequencing:

•

There are no dependencies in power-on/power-off sequence between V_DDM3and V_DDsupplies.

There are no dependencies in power-on/power-off sequence between RapidIO supplies: V_DDSXC, V_DDSXP

,

V_DDRIOPLLand other MSC8144E supplies.

•

V_DDPLLshould be coupled with the V_DDpower rail with extremely low impedance path.

External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time,

including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for

configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to 80

mA per input pin per MSC8144E device in the system during start-up. An assertion of the inputs to the high voltage level before

power-up should be with slew rate less than 4V/ns.

The following supplies should rise before any other supplies in any sequence

•

V_DDand V_DDPLLcoupled together

V_DDM3

After the above supplies rise to 90% of their nominal value the following I/O supplies may rise in any sequence (see Figure 43):

•

V_DDGE1

V_DDGE2

V_DDIO

V

_DDDDRand MV_REFcoupled one to another. MV_REFshould be either at same time or after V_DDDDR

V_DDM3IO

V_25M3

.

I/O supplies

V

and V

DDM3, DD, DDPLL

90%

Figure 43. V_DDM3, V_DDM3IOand V_25M3Power-on Sequence

Note: 1. This recommended power sequencing is different from the MSC8122/MSC8126.

2. If no pins that require V_DDGE1as a reference supply are used (see Table 1), V_DDGE1can be tied to GND.

3. If no pins that require V_DDGE2as a reference supply are used (see Table 1), V_DDGE2can be tied to GND.

4. If the DDR interface is not used, V_DDDDRand MV_REFcan be tied to GND.

5. If the M3 memory is not used, V_DDM3, V_DDM3IO, and V_25M3can be tied to GND.

6. If the RapidIO interface is not used, V_DDSX, V_DDSXP, and V_DDRIOPLLcan be tied to GND.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

64

Freescale Semiconductor

Hardware Design Considerations

3.1.2

Start-Up Timing

Section 2.7.1 describes the start-up timing.

3.2

Power Supply Design Considerations

3.2.1

PLL Supplies

Each PLL supply must have an external RC filter for the V_DDPLLinput. The filter is a 10 Ω resistor in series with two 2.2 μF,

low ESL (<0.5 nH) and low ESR capacitors. All three PLLs can connect to a single supply voltage source (such as a voltage

regulator) as long as the external RC filter is applied to each PLL separately (see Figure 44). For optimal noise filtering, place

the circuit as close as possible to its V_DDPLLinputs. These traces should be short and direct.

MSC8144

10 Ω

Voltage Regulator

V_DDPLL0

2.2 μF

10 Ω

V_DDPLL0

2.2 μF

10 Ω

V_DDPLL0

2.2 μF

Figure 44. PLL Supplies

3.2.2

Other Supplies (TBD)

3.3

Clock and Timing Signal Board Layout Considerations

When laying out the system board, use the following guidelines:

•

Keep clock and timing signal paths as short as possible and route with 50 Ω impedance.

Use a serial termination resistor placed close to the clock buffer to minimize signal reflection. Use the following

equation to compute the resistor value:

Rterm = Rim – Rbuf

where Rim = trace characteristic impedance

Rbuf = clock buffer internal impedance.

Note: See MSC8144 CLKIN and PCI_CLK_IN Board Layout (AN3440) for an example layout.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

65

Hardware Design Considerations

3.4

Connectivity Guidelines

Note: Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal

connections in this discussion.

First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following

subsections for board design and connections. The following conventions are used in describing the connectivity requirements:

1. GND indicates using a 10 kΩ pull-down resistor (recommended) or a direct connection to the ground plane. Direct

connections to the ground plane may yield DC current up to 50mA through the I/O supply that adds to overall power

consumption.

2. V_DDindicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.

Direct connections to the supply may yield DC current up to 50mA through the I/O supply that adds to overall power

consumption.

3. Mandatory use of a pull-up or pull-down resistor it is clearly indicated as “pull-up/pull-down”.

4. NC indicates “not connected” and means do not connect anything to the pin.

5. The phrase “in use” indicates a typical pin connection for the required function.

Note: Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of

subset interface connection.

3.4.1

DDR Memory Related Pins

This section discusses the various scenarios that can be used with DDR1 and DDR2 memory.

Note: For information about unused differential/non-differential pins in DDR1/DDR2 modes (that is, unused negative lines

of strobes in DDR1), please refer to Table 56.

3.4.1.1

DDR Interface Is Not Used

Table 56. Connectivity of DDR Related Pins When the DDR Interface Is Not Used

Signal Name

Pin Connection

MDQ[0–31]

MDQS[0–3]

MA[0–15]

MCK[0–2]

MCS[0–1]

MDM[0–3]

MBA[0–2]

MCAS

NC

MCKE[0–1]

MODT[0–1]

MDIC[0–1]

MRAS

MWE

MECC[0–7]

ECC_MDM

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

66

Freescale Semiconductor

Hardware Design Considerations

Table 56. Connectivity of DDR Related Pins When the DDR Interface Is Not Used (continued)

Signal Name

Pin Connection

ECC_MDQS

NC

MV

GND

REF

V

DDDDR

Note:

If the DDR controller is not used, disable the internal DDR clock by writing a 1 to the CLK11DIS bit in the System Clock Control

Register (SCCR[CLK!11DIS]). See Chapter 7, Clocks, in the MSC8144E Reference Manual for details.

3.4.1.2

16-Bit DDR Memory Only

Table 57 lists unused pin connection when using 16-bit DDR memory. The 16 most significant data lines are not used.

Table 57. Connectivity of DDR Related Pins When Using 16-bit DDR Memory Only

Signal Name

Pin connection

MDQ[0–15]

MDQ[16–31]

MDQS[0–1]

MDQS[2–3]

MDQS[0–1]

MDQS[2–3]

MA[0–15]

MCK[0–2]

MCS[0–1]

MDM[0–1]

MDM[2–3]

MBA[0–2]

MCAS

in use

pull-up to V

DDDDR

in use

pull-down to GND

in use

pull-up to V

DDDDR

in use

NC

in use

MCKE[0–1]

MODT[0–1]

MDIC[0–1]

MRAS

MWE

MV

1/2*V

DDDDR

REF

V

2.5 V or 1.8 V

DDDDR

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

67

Hardware Design Considerations

3.4.1.3

ECC Unused Pin Connections

When the error code corrected mechanism is not used in any 32- or 16-bit DDR configuration, refer to Table 58 to determine

the correct pin connections.

Table 58. Connectivity of Unused ECC Mechanism Pins

Signal Name

Pin connection

MECC[0–7]

ECC_MDM

ECC_MDQS

pull-up to V

NC

DDDDR

pull-down to GND

pull-up to V

DDDDR

3.4.2

Serial RapidIO Interface Related Pins

Serial RapidIO interface Is Not Used

3.4.2.1

Table 59. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used

Signal Name

Pin Connection

SRIO_IMP_CAL_RX

SRIO_IMP_CAL_TX

SRIO_REF_CLK

SRIO_RXD[0–3]

SRIO_TXD[0–3]

GND

NC

V

GND

DDRIOPLL

GND

RIOPLL

SXP

SXC

V

DDSXP

DDSXC

V

3.4.2.2

Serial RapidIO Specific Lane Is Not Used

Table 60. Connectivity of Serial RapidIO Related Pins When Specific Lane Is Not Used

Signal Name

Pin Connection

SRIO_IMP_CAL_RX

SRIO_IMP_CAL_TX

SRIO_REF_CLK

SRIO_RXDx

in use

GND

SXC

SRIO_RXDx

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

68

Freescale Semiconductor

Hardware Design Considerations

Table 60. Connectivity of Serial RapidIO Related Pins When Specific Lane Is Not Used (continued)

Signal Name

Pin Connection

SRIO_TXDx

NC

V

in use

DDRIOPLL

GND

RIOPLL

SXP

GND

SXP

SXC

V

1.0 V

DDSXP

DDSXC

Note:

The x indicates the lane number {0,1,2,3} for all unused lanes.

3.4.3

M3 Memory Related Pins

Table 61. Connectivity of M3 Related Pins When M3 Memory Is Not Used

Signal Name

Pin Connection

M3_RESET

NC

V

GND

25M3

DDM3

DDM3IO

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

69

Hardware Design Considerations

3.4.4

Ethernet Related Pins

Ethernet Controller 1 (GE1) Related Pins

3.4.4.1

Note: Table 62 and Table 63 assume that the alternate function of the specified pin is not used. If the alternate function is

used, connect the pin as required to support that function.

3.4.4.1.1

GE1 Interface Is Not Used

Table 62 assumes that the GE1 signals are not used for any purpose (including any multiplexed functions) and that V_DDGE1is

tied to GND.

Table 62. Connectivity of GE1 Related Pins When the GE1 Interface Is Not Used

Signal Name

Pin Connection

GE1_COL

NC

GE1_CRS

GE1_RD[0–4]

GE1_RX_ER

GE1_RX_CLK

GE1_RX_DV

GE1_SGMII_RX

GE1_SGMII_TX

GE1_TD[0–4]

GE1_TX_CLK

GE1_TX_EN

GE1_TX_ER

GND

SXC

NC

3.4.4.1.2

Subset of GE1 Pins Required

When only a subset of the whole GE1 interface is used, such as for RMII, the unused GE1 pins should be connected as described

in Table 63. This table assumes that the unused GE1 pins are not used for any purpose (including any multiplexed function) and

that V_DDGE1is tied to either 2.5 V or 3.3 V.

Table 63. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required

Signal Name

Pin Connection

GE1_COL

GND

GE1_CRS

GE1_RD[0–3]

GE1_RX_ER

GE1_RX_CLK

GE1_RX_DV

GE1_SGMII_RX

GE1_SGMII_TX

GND

SXC

NC

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

70

Freescale Semiconductor

Hardware Design Considerations

Table 63. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)

Signal Name

Pin Connection

GE1_SGMII_TX

GE1_TD[0-3]

GE1_TX_CLK

GE1_TX_EN

GE1_TX_ER

NC

GND

NC

3.4.4.2

Ethernet Controller 2 (GE2) Related Pins

Note: Table 64 and Table 66 assume that the alternate function of the specified pin is not used. If the alternate function is

used, connect the pin as required to support that function.

3.4.4.2.1

GE2 interface Is Not Used

Table 64 assumes that the GE2 pins are not used for any purpose (including any multiplexed function) and that V_DDGE2is tied

to GND.

Table 64. Connectivity of GE2 Related Pins When the GE2 Interface Is Not Used

Signal Name

Pin Connection

GE2_RD[0-3]

GE2_RX_CLK

GE2_RX_DV

GE2_RX_ER

GE2_SGMII_RX

GE2_SGMII_TX

GE2_TCK

NC

GND

SXC

NC

Nc

NC

GE2_TD[0–3]

GE2_TX_EN

3.4.4.2.2

Subset of GE2 Pins Required

When only a subset of the whole GE2 interface is used, such as for RMII, the unused GE2 pins should be connected as described

in Table 65. The table assumes that the unused GE2 pins are not used for any purpose (including any multiplexed functions)

and that V_DDGE2is tied to either 2.5 V or 3.3 B.

Table 65. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required

Signal Name

Pin Connection

GE2_RD[0-3]

GE2_RX_CLK

GE2_RX_DV

GE2_RX_ER

GE2_SGMII_RX

GND

SXC

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

71

Hardware Design Considerations

Table 65. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)

Signal Name

Pin Connection

GND

GE2_SGMII_RX

GE2_SGMII_TX

GE2_TCK

SXC

NC

GE2_TD[0–3]

GE2_TX_EN

3.4.4.3

GE1 and GE2 Management Pins

GE_MDC and GE_MDIO pins should be connected as required by the specified protocol. If neither GE1 nor GE2 is used (that

is, V_DDGE2is connected to GND), Table 66 lists the recommended management pin connections.

Table 66. Connectivity of GE Management Pins When GE1 and GE2 Are Not Used

Signal Name

Pin Connection

GE_MDC

GE_MDIO

NC

3.4.5

UTOPIA/POS Related Pins

Table 67 lists the board connections of the UTOPIA/POS pins when the entire UTOPIA/POS interface is not used or subset of

UTOPIA/POS interface is used. For multiplexing options that select a subset of the UTOPIA/POS interface, use the connections

described in Table 67 for those signals that are not selected. Table 67 assumes that the alternate function of the specified pin is

not used. If the alternate function is used, connect that pin as required to support the selected function.

Table 67. Connectivity of UTOPIA/POS Related Pins When UTOPIA/POS Interface Is Not Used

Signal Name

Pin Connection

UTP_IR

GND

UTP_RADDR[0–4]

UTP_RCLAV_PDRPA

UTP_RCLK

V

DDIO

NC

GND

UTP_RD[0–15]

UTP_REN

V

DDIO

UTP_RPRTY

UTP_RSOC

GND

UTP_TADDR[0–4]

UTP_TCLAV

UTP_TCLK

V

DDIO

NC

GND

NC

UTP_TD[0–15]

UTP_TEN

V

DDIO

UTP_TPRTY

UTP_TSOC

NC

V

3.3 V

DDIO

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

72

Freescale Semiconductor

Hardware Design Considerations

3.4.6

TDM Interface Related Pins

Table 68 lists the board connections of the TDM pins when an entire specific TDM is not used. For multiplexing options that

select a subset of a TDM interface, use the connections described in Table 68 for those signals that are not selected. Table 68

assumes that the alternate function of the specified pin is not used. If the alternate function is used, connect that pin as required

to support the selected function.

Table 68. Connectivity of TDM Related Pins When TDM Interface Is Not Used

Signal Name

Pin Connection

TDMxRCLK

TDMxRDAT

TDMxRSYN

TDMxTCLK

TDMTxDAT

TDMxTSYN

GND

3.3 V

V

DDIO

Notes: 1. x = {0, 1, 2,3, 4, 5, 6, 7}

2. In case of subset of TDM interface usage please make sure to disable unused TDM modules. See Chapter 20, TDM, in the

MSC8144E Reference Manual for details.

3.4.7

PCI Related Pins

Table 69 lists the board connections of the pins when PCI is not used. Table 69 assumes that the alternate function of the

specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function.

Table 69. Connectivity of PCI Related Pins When PCI Is Not Used

Signal Name

Pin Connection

PCI_AD[0–31]

PCI_CBE[0–3]

PCI_CLK_IN

PCI_DEVSEL

PCI_FRAME

PCI_GNT

GND

V

DDIO

PCI_IDS

GND

PCI_IRDY

V

DDIO

PCI_PAR

GND

PCI_PERR

PCI_REQ

V

DDIO

NC

PCI_SERR

PCI_STOP

PCI_TRDY

V

DDIO

V

3.3 V

DDIO

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

73

Hardware Design Considerations

3.4.8

Miscellaneous Pins

Table 70 lists the board connections for the pins if they are required by the system design. Table 70 assumes that the alternate

function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected

function.

Table 70. Connectivity of Individual Pins When They Are Not Required

Signal Name

Pin Connection

CLKOUT

EE0

NC

GND

EE1

NC

GPIO[0–31]

SCL

NC

See the GPIO connectivity guidelines in this table.

NC

SDA

INT_OUT

IRQ[0–15]

NMI

See the GPIO connectivity guidelines in this table.

V

DDIO

NMI_OUT

RC[0–16]

RC_LDF

STOP_BS

TCK

NC

GND

NC

GND

TDI

GND

TDO

NC

TMR[0–4]

TMS

See the GPIO connectivity guidelines in this table.

GND

TRST

GND

See the GPIO connectivity guidelines in this table.

3.3 V

URXD

UTXD

V

DDIO

Note:

When using I/O multiplexing mode 5 or 6, tie the TDM7TSYN/PCI_AD4 signal (ball number AC9) to GND.

Note: For details on configuration, see the MSC8144E Reference Manual. For additional information, refer to the MSC8144

Design Checklist (AN3202).

3.5

External DDR SDRAM Selection

TBD

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

74

Freescale Semiconductor

Ordering Information

4

Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.

Core

Operating

Part

Package Type

Spheres

Frequency Order Number

(MHz)

Voltage Temperature

MSC8144E Flip Chip Plastic Ball Grid Array (FC-PBGA)

Lead-free

1.0 V

–40° to 105°C

0° to 90°C

800

TBD

1000

5

Package Information

Notes:

1. All dimensions in millimeters.

2. Dimensioning and tolerancing

per ASME Y14.5M–1994.

3. Maximum solder ball diameter

measured parallel to Datum A.

4. Datum A, the seating plane, is

determined by the spherical

crowns of the solder balls.

5. Parallelism measurement

should exclude any effect of

marking.

6. Capacitors may not be present

on all devices.

7. Caution must be taken not to

short exposed metal capacitor

pads on package top.

CASE NO. 1842-02

Figure 45. MSC8144E Mechanical Information, 783-ball FC-PBGA Package

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

75

Product Documentation

6

Product Documentation

•

MSC8144E Technical Data Sheet (MSC8144E). Details the signals, AC/DC characteristics, clock signal

characteristics, package and pinout, and electrical design considerations of the MSC8144E device.

MSC8144E Reference Manual (MSC8144ERM). Includes functional descriptions of the extended cores and all the

internal subsystems including configuration and programming information.

•

Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8144E device.

SC3400 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program

control, and instruction set.

•

MSC8144 SC3400 DSP Core Subsystem Reference Manual. Covers core subsystem architecture, functionality, and

registers.

7

Revision History

Table 71 provides a revision history for this data sheet.

Table 71. Document Revision History

Revision

Date

Description

0

1

June. 2007

Sep 2007

•

Initial public release.

•

Updated M3 voltage range in Table 3.

Changed note in Table 7 for PLL power supplies.

DDR voltage designator changed from V_DDto V_DDDDRin Table 8, Table 10, Section 2.7.4.1, Section

2.7.4.2, and Figure 11. Changed range on I_OZin Table 8 and Table 10.

Deleted text before Table 13 and added note 2 to input pin capacitance.

Deleted text before Table 14, added a 1 to the note, and added note 1 to input pin capacitance.

Deleted Section 2.6.5 on page 32 and renumbered subsequent subsections.

Deleted text before new Section 2.6.5.1.

Added a 1 to the note in Table 15 and added note 1 to input pin capacitance.

Deleted ac voltage rows from Table 16. Added note 1 to input pin capacitance.

Changed output high and low voltage levels in Table 17 and Table 18.

Deleted text before Table 19.

Added clock skew ranges in percent in Table 21.

Changed V_REFto MV_REFin Table 26.

Changed V_DDto V_DDIOin Table 41 Updated note 2.

Added note 4 to Table 42. Changed t_TDMSHOXvalue.

Changed V_DDto V_DDGEin Figure 27 and Figure 30.

Changed the value of the data to clock out skew in Table 51.

Changed EE pin timing in Table 55.

Changed the head for the JTAG timing section, now Section 2.7.14.

Updated JTAG timing for TCK cycle time, TCK high phase, and boundary scan input data hold time in

Table 55.

•

Added new Section 3.3 with guidelines for board layout for clock and timing signals. Renumbered

subsequent sections.

2

Sep 2007

Changed leakage current values in Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, and Table 19

from –10 and 10 μa to –30 and 30 μa.

•

Change the minimum value of t_MDDVKHin Table 45 from 5 ns to 7 ns.

Updated note 1 in Table 45.

3

4

Oct 2007

•

Corrected column numbering in Figure 3 and Figure 4.

Updated SPI signal names in Table 1.

•

Updated SPI signal names in Table 1.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

76

Freescale Semiconductor

Revision History

Table 71. Document Revision History

Description

Revision

Date

5

Dec 2007

•

Changed minimum voltage level for V_DDM3to 1.213 (1.25 – 3%) in Table 3.

Added POS to titles in Section 2.6.6.

Added additional signals to titles in Section 2.6.8. Added high and low voltage ranges to Table 19.

Added ATM and POS to headings in Section 2.7.11. Changed characteristics to generic input/output in

Table 52, Figure 33, and Figure 34.

•

Replaced Sections 2.7.13 and 2.7.14 with new Section 2.7.13. Renumbered subsequent sections, tables,

and figures.

•

Added POS to all UTOPIA references in Section 3.4.5.

6

Dec 2007

Changed GCR4 program value to 0x0004C130 in Note 7 in Table 51.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

77

Revision History

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

78

Freescale Semiconductor

Revision History

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

79

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Document Number: MSC8144E

Rev. 6

12/2007


型号：	TBD
厂家：	Freescale
描述：	Quad Core Digital Signal Processor 四核数字信号处理器数字信号处理器
文件：	总80页 (文件大小：2306K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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