FT121_技术文档

Document No.: FT_000648

FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC

Datasheet Version 1.2

Future Technology Devices

International Ltd

.

FT121

(Enhanced USB Device

Controller with SPI Slave IC)

The FT121 is a USB generic interface



Integrated DP pull-up resistor for USB

connection

controller with the following advanced

features:



Supports

applications

bus-powered

or

self-powered



USB 2.0 Full Speed compatible

High performance USB device controller with

integrated SIE, endpoint buffer, transceiver

and voltage regulators



VCC power supply operation at 3.3V or 5V

Internal 1.8V and 3.3V LDO regulators



VCC IO level range from 1.8V to 3.3V

Integrated power-on-reset circuit



Fully integrated clock generation with no

external crystal required

Supports Serial Parallel interface (SPI) slave to

external microcontroller



UHCI/OHCI/EHCI host controller compatible

-40°C to 85°C extended operating temperature

range



Supports up to 8 bi-directional endpoints with

total 2k bytes endpoint buffer

Max packet size is 504 bytes for isochronous



Available in Pb-free TSSOP-16 and QFN-16

packages (RoHS compliant)

endpoint

and

64

bytes

for

control/bulk/interrupt endpoint



Double buffer scheme for any endpoint

increases data transfer throughput

Multiple interrupt modes to facilitate both bulk

and isochronous transfers

USB Battery Charger detection allowing

optimized charging profile

Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced

in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are

supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology

Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your

statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in

which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary

information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by

the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow

G41 1HH United Kingdom. Scotland Registered Company Number: SC136640

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Document No.: FT_000648

FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC

Datasheet Version 1.2

1 Typical Applications



Provide USB port to Microcontrollers

USB Industrial Control



Provide USB port to FPGA’s

Utilising USB to add system modularity

Mass storage data transfers for multitude of

embedded systems applications, including

medical, industrial data-logger, power-

metering, and test instrumentation

Isochronous support for video applications in

security, industrial control, and quality

inspections

1.1 Part Numbers

Part Number

Package

FT121T-x

TSSOP-16

QFN-16

FT121Q-x

Note: Packaging codes for x is:

- R: Taped and Reel, (TSSOP is 2,500pcs per reel, QFN is 6,000pcs per reel).

- U: Tube packing, 96pcs per tube (TSSOP only)

- T: Tray packing, 490pcs per tray (QFN only)

For example: FT121T-R is 2,500pcs taped and reel packing

1.2 USB Compliant

At the time of writing this datasheet, the FT121 was in the process of completing USB compliance testing.

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Datasheet Version 1.2

2 Block Diagrams

Figure 2-1 FT121 Block Diagram

For a description of each function please refer to Section 4.

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FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC

Datasheet Version 1.2

Table of Contents

1

Typical Applications...................................................................... 2

1.1 Part Numbers...................................................................................... 2

1.2 USB Compliant.................................................................................... 2

Block Diagrams ............................................................................ 3

Device Pin Out and Signal Description.......................................... 6

3.1 TSSOP-16 Package Pin Out ................................................................. 6

3.2 QFN-16 Package Pin Out..................................................................... 6

3.3 Pin Description ................................................................................... 7

Function Description..................................................................... 9

4.1 Functional Block Descriptions............................................................. 9

4.2 Interrupt Modes................................................................................ 10

2

3

4

4.3 SPI Slave Interface........................................................................... 10

4.3.1 4-wire write operation................................................................................................ 11

4.3.2 4-wire read operation................................................................................................. 11

4.3.3 3-wire write operation................................................................................................ 12

4.3.4 3-wire read operation................................................................................................. 12

5

6

Endpoint Buffer Management ..................................................... 14

5.1 Endpoint Buffer Management in Default Mode .................................. 14

5.2 Endpoint Buffer Management in Enhanced Mode .............................. 15

Commands and Registers ........................................................... 17

6.1 Command Summary.......................................................................... 17

6.2 Initialization Commands................................................................... 22

6.2.1 Set Address Enable.................................................................................................... 22

6.2.2 Set Endpoint Enable................................................................................................... 22

6.2.3 Set Mode.................................................................................................................. 22

6.2.4 Set Interrupt............................................................................................................. 24

6.2.5 Set Endpoint Configuration (for Enhanced Mode) ........................................................... 24

6.3 Data Flow Commands ....................................................................... 25

6.3.1 Read Interrupt Register.............................................................................................. 25

6.3.2 Select Endpoint ......................................................................................................... 27

6.3.3 Read Last Transaction Status ...................................................................................... 27

6.3.4 Read Endpoint Status................................................................................................. 28

6.3.5 Read Buffer............................................................................................................... 29

6.3.6 Write Buffer .............................................................................................................. 29

6.3.7 Clear Buffer .............................................................................................................. 29

6.3.8 Validate Buffer .......................................................................................................... 29

6.3.9 Set Endpoint Status ................................................................................................... 30

6.3.10

Acknowledge Setup ................................................................................................ 30

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6.4 General Commands........................................................................... 30

6.4.1 Read Current Frame Number....................................................................................... 31

6.4.2 Send Resume............................................................................................................ 31

6.4.3 Set 3-wire Mode ........................................................................................................ 31

6.4.4 Read Vendor ID......................................................................................................... 32

6.4.5 Read Product ID ........................................................................................................ 32

6.4.6 Read FTDI ID ............................................................................................................ 32

6.4.7 Set IO Pad Drive Strength........................................................................................... 32

7

8

Application Information ............................................................. 33

Devices Characteristics and Ratings........................................... 34

8.1 Absolute Maximum Ratings............................................................... 34

8.2 DC Characteristics............................................................................. 35

8.3 AC Characteristics............................................................................. 36

Package Parameters................................................................... 38

9.1 TSSOP-16 Package Dimensions ........................................................ 38

9.2 TSSOP-16 Package Markings ........................................................... 39

9.3 QFN-16 Package Dimensions ............................................................ 40

9.4 QFN-16 Package Markings ............................................................... 41

9.5 Solder Reflow Profile ........................................................................ 41

9

10 Contact Information................................................................... 43

Appendix A – References........................................................................... 44

Appendix B - List of Figures and Tables..................................................... 44

Appendix C - Revision History.................................................................... 46

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Datasheet Version 1.2

3 Device Pin Out and Signal Description

3.1 TSSOP-16 Package Pin Out

Figure 3-1 TSSOP-16 package schematic symbol

3.2 QFN-16 Package Pin Out

Figure 3-2 QFN-16 package schematic symbol

NOTE: Bottom Side centre pads not shown on QFN Pin Out:



Ground

VCCIO

VOUT3V3

VCC

Bottom View Location = Upper right

Bottom View Location = Lower right

Bottom View Location = Lower left

Bottom View Location = Upper left

See QFN Package information in Section 9.3 below for more details. They may be left unconnected.

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3.3 Pin Description

PIN No.

(TSSOP-

16)

PIN No. PIN NAME

(QFN-

16)

TYPE

DESCRIPTION

1

2

3

4

5

6

7

8

15

16

1

BCD_n

SCLK

OD

I

USB Charger detector output

SPI clock input

SS_n

I

SPI slave select input

2

GND

P

Ground

3

VCCIO

SUSPEND

INT_n

MISO

P

IO Supply Voltage; 1.8V, 2.5V or 3.3V

Device suspend (output) and wakeup (input)

Interrupt (Active Low)

4

I,OD

OD

O

5

6

4-wire mode: SPI slave output

3-wire mode: no function. Leave it un-connected

9

7

MOSI

I/IO

4-wire mode: SPI salve input

3-wire mode: SPI data input/output

10

11

12

8

9

VBUS_S

RESET_n

VOUT3V3

I

Vbus sensing input

Asynchronous reset (Active Low)

3.3V regulator output for 5V operation;

10

P

To operate the IC at 3.3 V, supply 3.3 V to both

the VCC and VOUT3V3 pins

13

14

15

16

11

12

13

14

17

VCC

GND

DM

P

Power supply (3.3V or 5V)

Ground

AIO

P

USB data signal minus

USB data signal plus

DP

GND

Ground

Center bottom pad – may be left unconnected

18

19

VCCIO

P

IO Supply Voltage; 1.8V, 2.5V or 3.3V

Center bottom pad – may be left unconnected

VOUT3V3

3.3V regulator output for 5V operation;

To operate the IC at 3.3 V, supply 3.3 V to both

the VCC and VOUT3V3 pins

Center bottom pad – may be left unconnected

20

VCC

P

Power supply (3.3V or 5V)

Center bottom pad – may be left unconnected

Table 3.1 FT121 Pin Description

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Datasheet Version 1.2

Note: a) Pin name with suffix “_n” denotes active low input/output signal.

b) Symbol used for pin TYPE:

OD

O

: Open Drain Output

: Output

IO

I

: Bi-directional Input and Output

: Plain input

AIO

P

: Analog Input and Output

: Power or ground

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Datasheet Version 1.2

4 Function Description

The FT121 is a USB device controller which interfaces with microcontrollers via an SPI slave interface.

4.1 Functional Block Descriptions

The following sections describe the function of each block. Please refer to the block diagram shown in

Figure 2-1.

+1.8V LDO Regulator. The +1.8V LDO regulator generates the +1.8V reference voltage for the internal

core of the IC with input capabilities from 3.3V or 5V.

+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V supply voltage for the USB

transceiver. An external decoupling capacitor needs to be attached to the VOUT3V3 regulator output pin.

The regulator also provides +3.3V power to the 1.5kΩ internal pull up resistor on DP pin. The allowable

input voltages are 5V or 3.3V. When using 3.3V as the input voltage, the VCC and VOUT3V3 pins should

be tied together. This will result in the regulator being by-passed.

USB Transceiver. The USB Transceiver cell provides the USB 1.1 / USB 2.0 full-speed physical interface.

Output drivers provide +3.3V level slew rate control, while a differential input and two single ended input

receivers provide data in, Single-Ended-0 (SE0) and USB reset detection conditions respectfully. A 1.5kΩ

pull up resistor on DP is incorporated.

DPLL. The DPLL cell locks on to the incoming NRZI USB data and generates recovered clock and data

signals.

Internal Oscillator. The Internal Oscillator cell generates a reference clock. This provides an input to

the Clock Multiplier function.

Clock Multiplier. The 12MHz and 48MHz reference clock signals for various internal blocks can be

generated from the reference clock via the oscillator functions and clock multiplier circuitry.

Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial

and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it

performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data

stream.

USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control

endpoint. It handles the low level USB protocol requests generated by the USB host controller. The

Protocol Engine also includes a memory management unit which handles endpoint buffers.

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OUT Buffer. Data sent from the USB host controller to FT121 via the USB data OUT endpoint is stored in

the OUT buffer. Data is removed from the OUT buffer to system memory under control of the parallel

interface block.

IN Buffer. Data from system memory is stored in the IN buffer. The USB host controller removes data

from the IN buffer by sending a USB request for data from the device data IN endpoint.

RESET Generator. The integrated Reset Generator cell provides a reliable power-on reset to the device

internal circuitry at power up. The RESET_n input pin allows an external device to reset the FT121.

SPI Controller Block. The SPI slave controller provides control and data interfaces between the external

MCU and internal registers and endpoint buffers. It supports 4-wire (default) or 3-wire SPI operation.

4.2 Interrupt Modes

The FT121 interrupt pin (INT_n) can be programmed to generate an interrupt in different modes. The

interrupt source can be any bit in the Interrupt Register, an SOF packet being received, or both. The

interrupt modes are selectable by two register bits, one is the SOF-only Interrupt Mode bit (bit 7 of Clock

Division Factor register), and the other is the Interrupt Pin Mode bit (bit 5 of Interrupt Configuration

register).

Interrupt

mode

Bit SOF-only

Interrupt

Mode

Bit Interrupt

Pin Mode

Interrupt source

0

1

2

0

1

0

1

X

Any bit in Interrupt register

Any bit in Interrupt register and SOF

SOF only

Table 4.1 Interrupt modes

4.3 SPI Slave Interface

The SPI slave interface supports 4-wire (default) and 3-wire operation. In 4-wire operation the SPI

master will drive data on the MOSI pin and the SPI slave will drive data on the MISO pin. In 3-wire

operation both SPI master and SPI slave share the same data pin (MOSI pin becomes a bi-directional

pin). Upon power-on or hardware reset, the FT121 SPI slave interface is in 4-wire mode. The 3-wire

operation is enabled when a Set 3-wire command is issued to the FT121.

The SPI protocol will follow a command + data format where a command is transmitted after SS_n is

asserted and each subsequent byte will be a data byte. When all data bytes for this command are

completed the SS_n is de-asserted. This can be seen in Figure 4-1.

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Datasheet Version 1.2

Command

Write Data

SCLK

1

6

7

1

6

7

0

SS_n

MOSI

Command

Write Data

Read Data

MISO

Figure 4-1 SPI access

The SPI slave supports SPI mode 1 (CPOL=0, CPHA=1). This means the rising edge is the driving edge

while the falling edge is the sample edge. The drive edge is always before the sample edge.

The maximum SPI clock supported is 20MHz, for both 4-wire and 3-wire modes. Refer to the AC

characteristics section for SPI timing figures.

4.3.1 4-wire write operation

When the SPI master performs a data write operation, it drives the SS_n line low, sends the 8-bit

command byte on MOSI line, followed by sending of the data bytes. The length of the data byte ranges

from 0 to maximum 506, depending on the command type. The master will signal the end of the data

write operation by drive the SS_n line high.

Figure 4-2 4-wire write operation

4.3.2 4-wire read operation

When the SPI master performs a data read operation, it drives the SS_n line low and sends the 8-bit

command byte on MOSI line. The FT121 will output data bytes on the MISO line. The length of the data

byte ranges from 0 to maximum 506, depending on the command type. The master will signal the end of

the data read operation by drive the SS_n line high.

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Datasheet Version 1.2

Figure 4-3 4-wire read operation

4.3.3 3-wire write operation

When the SPI master performs a data write operation, it drives the SS_n line low, sends the 8-bit

command byte on MOSI line, followed by sending the data bytes. The length of the data byte ranges from

0 to maximum 506, depending on the command type. The master will signal the end of the data write

operation by drive the SS_n line high.

Figure 4-4 3-wire write operation

4.3.4 3-wire read operation

When the SPI master performs a data read operation, it drives the SS_n line low andsends the 8-bit

command byte on MOSI line. The master will stop driving the MOSI line. The FT121 will output data bytes

on the MOSI line. The length of the data byte ranges from 0 to maximum 506, depending on the

command type. The master will signal the end of the data read operation by drive the SS_n line high.

Figure 4-5 3-wire read operation

It is important that bus contention should be avoided during the bus turnaround period – i.e. moving

from the command byte to a read byte. In this instance the master will stop driving at the same clock

edge (rising edge) as the slave starts to drive. To avoid bus contention the FT121 will implement delays

so that it only starts to drive the MOSI line at least 5ns after the SCLK driving edge – this will give the

master a minimum of 5ns to stop driving MOSI, which should ensure no bus contentions. At this bus

turnaround point it’s also more natural for a clash not to occur, as the master is the source of the clock,

so will drive the clock and MOSI off at similar times. For the slave to drive MOSI it has to pass the clock

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through the I/O buffers, into the internal circuits, clock MOSI and then get MOSI out through the output

buffers. This long path in and out of the slave will have an inherent delay of a few nanoseconds.

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5

Endpoint Buffer Management

The FT121 has 2 modes of operation for command and memory management: the default mode and the

enhanced mode. The buffer management schemes are different in these two modes. Upon reset the

default mode is functional. The enhanced mode is activated when any of the Set Endpoint Configuration

commands (B0h – BFh) are received.

5.1 Endpoint Buffer Management in Default Mode

In default mode the FT121 has 3 bi-directional endpoints (EP0, EP1 and EP2). EP0 is the control endpoint,

with 16 bytes maximum packet size for both the control OUT and control IN endpoints. EP1 can be used

as either a bulk endpoint or an interrupt endpoint, with 16 bytes maximum packet size for both OUT and

IN endpoints. Table 5.1 shows the endpoint type and maximum packet size for EP0 and EP1.

Endpoint

Number (EP) Index (EPI)

Endpoint

Direction

Transfer Type

Max Packet Size

0

1

0

1

OUT

IN

Control

16

2

3

OUT

IN

Bulk/Interrupt

16

Table 5.1 Endpoint configuration for EP0 and EP1

EP2 is the primary endpoint. It can be configured as either a bulk/interrupt or isochronous endpoint. The

maximum packet size allowed for EP2 depends on the mode of configuration through the Set Mode

command. Table 5.2 shows all the 4 endpoint configuration modes for EP2.

EP2 Endpoint

Configuration

Mode

Endpoint

Direction

Transfer Type

Max Packet Size

Index (EPI)

0

4

5

OUT

IN

Bulk/Interrupt

64

(default)

1

2

3

4

5

OUT

IN

Isochronous

128

4

5

OUT

IN

Isochronous

64

Table 5.2 Endpoint configuration for EP2

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Datasheet Version 1.2

As the primary endpoint, EP2 is suitable for transmitting or receiving relatively large data. To improve the

data throughput, EP2 is implemented with double buffering. This allows the concurrent operation between

USB bus access and MCU local bus access. For example, for EP2 IN endpoint (EPI5), the USB host can

read data from FT121 Buffer 0 while the local MCU is writing to Buffer 1 at the same time. The USB host

can subsequently read from the FT121 Buffer 1 without waiting for it to be filled. Buffer switching is

handled automatically by FT121.

5.2 Endpoint Buffer Management in Enhanced Mode

In enhanced mode the FT121 supports a dedicated 1kB buffer for IN packets and a dedicated 1kB buffer

for OUT packets. The OUT/IN buffer can be allocated to any endpoint with the same direction, up to a

maximum of 504 bytes double buffered (1008 bytes in total) to one endpoint. 504 is the maximum byte

count as there are 1024 bytes in total per OUT/IN Buffer and 8 bytes for IN and OUT packets on control

endpoint 0 must always be reserved. Control, interrupt and bulk endpoints can have a maximum packet

size of 64 bytes and only isochronous endpoints can be allocated more than 64 bytes.

Isochronous modes can have larger buffer sizes as USB packets can be larger than 64 bytes for

isochronous transfer. Isochronous buffers are managed in the same way as bulk, interrupt and control

buffers – i.e. a buffer is for one USB packet only and will not span more than one USB packet.

An example of buffer configurations follows, where Configuration 1 and 2 have larger isochronous buffers.

Configuration 0

Configuration 1

Configuration 2

EP

7

6

5

4

Buffer

EP

7

(ISO)

7

Buffer

EP

Buffer

1

0

1

0

1

0

1

0

1

0

1

0

1

0

(ISO)

5 (ISO)

1

6

2

1

0

1

0

3

2

1 (ISO)

1

5 (ISO)

0

2

1 (ISO)

0

1

0

1

0

1

0

1

0

1

0

Table 5.3 Example buffer configuration

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The endpoint buffer configurations, settable using the Set Endpoint Configuration command, are as

follows:

Endpoint buffer size register setting (0b’) Non-isochronous endpoint Isochronous endpoint

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

8 bytes

16 bytes

32 bytes

48 bytes

64 bytes

96 bytes

128 bytes

160 bytes

192 bytes

256 bytes

320 bytes

384 bytes

504 bytes

-

16 bytes

32 bytes

64 bytes

-

1100-1111

Table 5.4 Endpoint Maximum Packet Size

Note: 504 is the maximum byte count as there are 1024 bytes in total and 8 bytes IN and OUT packets

for control endpoint 0 must always be reserved.

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6 Commands and Registers

The FT121 supports two command sets: a default command set (Table 6.1) and an enhanced command

set (Table 6.2). The enhanced command set is activated if any of the Set Endpoint Configuration

commands (0xB0-0xBF) are received by the FT121. Otherwise, the default command set shall be valid.

6.1 Command Summary

Command Name

Target

Code (hex) Data phase

Initialization Commands

Set Address Enable

Set Endpoint Enable

Set Mode

Device

D0h

Write 1 byte

Write 2 bytes

Write 1 byte

D8h

F3h

FBh

Set Interrupt

Data Flow Commands

Read Interrupt Register

Select Endpoint

Device

F4h

00h

01h

02h

03h

04h

05h

40h

41h

42h

43h

44h

45h

80h

81h

82h

83h

84h

Read 2 bytes

Endpoint 0 OUT

Endpoint 0 IN

Endpoint 1 OUT

Endpoint 1 IN

Endpoint 2 OUT

Endpoint 2 IN

Endpoint 0 OUT

Endpoint 0 IN

Endpoint 1 OUT

Endpoint 1 IN

Endpoint 2 OUT

Endpoint 2 IN

Endpoint 0 OUT

Endpoint 0 IN

Endpoint 1 OUT

Endpoint 1 IN

Endpoint 2 OUT

Read 1 byte (optional)

Read 1 byte

Read Last Transaction Status

Read 1 byte

Read Endpoint Status

Read 1 byte

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Command Name

Target

Code (hex) Data phase

Endpoint 2 IN

85h

E0h

F0h

50h

51h

52h

53h

54h

55h

F1h

F2h

FAh

Read 1 byte

Read multiple bytes

Write multiple bytes

Write 1 byte

None

Read Buffer

Selected Endpoint

Endpoint 0 OUT

Endpoint 0 IN

Write Buffer

Set Endpoint Status

Endpoint 1 OUT

Endpoint 1 IN

Endpoint 2 OUT

Endpoint 2 IN

Acknowledge Setup

Clear Buffer

Selected Endpoint

General Commands

Device

None

Validate Buffer

None

Read Current Frame Number

F5h

F6h

Read 1 or 2 bytes

None

Send Resume

Device

Table 6.1 FT121 default command set

Command Name

Target

Code (hex) Data phase

Initialization Commands

Set Address Enable

Set Endpoint Enable

Set Mode

Device

D0h

Write 1 byte

Write 2 bytes

Write 1 byte

Device

D8h

F3h

FBh

B0h

B1h

B2h

B3h

B4h

B5h

Device

Set Interrupt

Device

Set Endpoint Configuration

Endpoint 0 OUT

Endpoint 0 IN

Endpoint 1 OUT

Endpoint 1 IN

Endpoint 2 OUT

Endpoint 2 IN

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Command Name

Target

Code (hex) Data phase

Endpoint 3 OUT

Endpoint 3 IN

Endpoint 4 OUT

Endpoint 4 IN

Endpoint 5 OUT

Endpoint 5 IN

Endpoint 6 OUT

Endpoint 6 IN

Endpoint 7 OUT

Endpoint 7 IN

Data Flow Commands

Device

B6h

B7h

B8h

B9h

BAh

BBh

BCh

BDh

BEh

BFh

Write 1 byte

Read Interrupt Register

Select Endpoint

F4h

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

40h

Read 1 to 4 bytes

Endpoint 0 OUT

Endpoint 0 IN

Endpoint 1 OUT

Endpoint 1 IN

Endpoint 2 OUT

Endpoint 2 IN

Endpoint 3 OUT

Endpoint 3 IN

Endpoint 4 OUT

Endpoint 4 IN

Endpoint 5 OUT

Endpoint 5 IN

Endpoint 6 OUT

Endpoint 6 IN

Endpoint 7 OUT

Endpoint 7 IN

Endpoint 0 OUT

Read 1 byte (optional)

Read 1 byte

Read Last Transaction Status

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Command Name

Target

Code (hex) Data phase

Endpoint 0 IN

Endpoint 1 OUT

Endpoint 1 IN

Endpoint 2 OUT

Endpoint 2 IN

Endpoint 3 OUT

Endpoint 3 IN

Endpoint 4 OUT

Endpoint 4 IN

Endpoint 5 OUT

Endpoint 5 IN

Endpoint 6 OUT

Endpoint 6 IN

Endpoint 7 OUT

Endpoint 7 IN

Endpoint 0 OUT

Endpoint 0 IN

Endpoint 1 OUT

Endpoint 1 IN

Endpoint 2 OUT

Endpoint 2 IN

Endpoint 3 OUT

Endpoint 3 IN

Endpoint 4 OUT

Endpoint 4 IN

Endpoint 5 OUT

Endpoint 5 IN

Endpoint 6 OUT

Endpoint 6 IN

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

Read 1 byte

Read Endpoint Status

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Command Name

Target

Code (hex) Data phase

Endpoint 7 OUT

Endpoint 7 IN

Selected Endpoint

Endpoint 0 OUT

Endpoint 0 IN

Endpoint 1 OUT

Endpoint 1 IN

Endpoint 2 OUT

Endpoint 2 IN

Endpoint 3 OUT

Endpoint 3 IN

Endpoint 4 OUT

Endpoint 4 IN

Endpoint 5 OUT

Endpoint 5 IN

Endpoint 6 OUT

Endpoint 6 IN

Endpoint 7 OUT

Endpoint 7 IN

Selected Endpoint

General Commands

Device

8Eh

8Fh

E0h

F0h

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

F1h

F2h

FAh

Read 1 byte

Read multiple bytes

Write multiple bytes

Write 1 byte

None

Read Buffer

Write Buffer

Set Endpoint Status

Acknowledge Setup

Clear Buffer

None

Validate Buffer

None

Send Resume

F6h

F5h

None

Read Current Frame Number

Device

Read 1 or 2 bytes

Set 3-wire Mode

Device

E8h

E9h

None

Set IO Pad Drive Strength

Write 1 byte

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Command Name

Read Vendor ID

Read Product ID

Target

Device

Code (hex) Data phase

EBh

EAh

EDh

Read 2 bytes

Read 1 byte

Read FTDI ID

Table 6.2 enhanced command set

6.2 Initialization Commands

6.2.1 Set Address Enable

Command

: D0h

Data

: Write 1 byte

Bit

Symbol

Reset

Description

6-0 Address

0b’0000000 USB assigned device address. A bus reset will reset all

address bits to 0.

7

Enable

0

Function enable. A bus reset will automatically enable the

function at default address 0.

Table 6.3 Address Enable Register

6.2.2 Set Endpoint Enable

Command

Data

: D8h

: Write 1 byte

Bit

Symbol

Reset

0

Description

0

EP_Enable

Enable all endpoints (Note EP0 is always enabled

regardless the setting of EP_Enable bit). Endpoints can

only be enabled when the function is enabled.

7-1 Reserved

0b’0000000 Reserved, write to 0

Table 6.4 Endpoint Enable Register

6.2.3 Set Mode

Command

Data

: F3h

: Write 2 bytes

Bit

Symbol

Reset

Description

1-0 Reserved

0b’00

Reserved, write to 0

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Bit

2

Symbol

Reset

1

Description

Clock Running

0: internal clocks stop during USB suspend

1: internal clocks continue running during USB suspend

This bit must be set to ‘0’ for bus powered application in

order to meet the USB suspend current requirement.

Note: The programmed value will not be changed by a

bus reset.

3

4

5

Interrupt Mode

1

0

0: interrupt will not generate on NAK or Error

transactions

1: interrupt will generate on NAK and Error transactions

Note: The programmed value will not be changed by a

bus reset.

DP_Pullup

0: Pullup resistor on DP pin disabled

1: Pullup resistor on DP pin enabled when Vbus is

present

Note: The programmed value will not be changed by a

bus reset.

Reserved

0

Reserved, write to 0

7-6 Endpoint Configuration

Mode

0b’00

Set the endpoint configuration mode for EP2.

00: Mode 0 (Non-ISO Mode)

01: Mode 1 (ISO-OUT Mode)

10: Mode 2 (ISO-IN Mode)

11: Mode 3 (ISO-IO Mode)

In Enhanced Mode, these 2 bits are reserved. The

Endpoint Configuration will be done through separate

command. See “Set Endpoint Configuration” commands.

Table 6.5 Configuration Register (Byte 1)

Bit

Symbol

Reset

0b’1011

0b’00

0

Description

Reserved, write to 0b’1111

Reserved, write to 0

3-0 Reserved

5-4 Reserved

6

7

SET_TO_ONE

This bit must be set to 1

0: normal operation

SOF-only Interrupt

Mode

0

1: interrupt will generate on receiving SOF packet only,

regardless of the value of the Interrupt Pin Mode bit in

the Interrupt configuration register.

Table 6.6 Configuration Register (Byte 2)

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6.2.4 Set Interrupt

Command

Data

: FBh

: Write 1 byte

Bit

Symbol

Reset

0b’00000

0

Description

Reserved, write to 0b’00000

4-0 Reserved

5

Interrupt Pin Mode

0: normal operation. Interrupt will generate if any bit in

the interrupt register is set.

1: interrupt will generate upon receiving a SOF packet or

if any bit in the interrupt register is set.

6

7

EPI4 Interrupt Enable

EPI5 Interrupt Enable

0

Interrupt Enable for endpoint index 4.

For enhanced mode this bit has no function. EPI4

interrupt is always enabled.

Interrupt Enable for endpoint index 5.

For enhanced mode this bit has no function. EPI5

interrupt is always enabled

Table 6.7 Interrupt Configuration Register

6.2.5 Set Endpoint Configuration (for Enhanced Mode)

Command

Data

: B0-BFh

: Write 1 byte

Bit

Symbol

Reset

0

Description

0

Endpoint Enabled

Enable or disable the endpoint index associated with the

command

2-1 Endpoint Type

0b’00

Endpoint type

00: control

01: bulk or interrupt

10: isochronous

11: reserved

6-3 Max Packet Size

0b’0000

Maximum USB packet size for this endpoint. Defines the

IN buffer or OUT buffer size for the endpoint. Refer to

Table 5.4 for full details on the buffer configuration.

7

Reserved

0

Reserved, write to 0

Table 6.8 Endpoint Configuration Register

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6.3 Data Flow Commands

6.3.1 Read Interrupt Register

Command

: F4h

Data

: Read 1 or 2 bytes (Default Mode); Read 1-4 bytes (Enhanced Mode)

Bit

Symbol

Reset

0

Description

0

1

2

3

4

5

6

7

Endpoint 0 Out

Endpoint 0 In

Endpoint 1 Out

Endpoint 1 In

Endpoint 2 Out

Endpoint 2 In

Bus Reset

Interrupt for endpoint 0 OUT buffer. Cleared by Read

Last Transaction Status command.

0

Interrupt for endpoint 0 IN buffer. Cleared by Read Last

Transaction Status command.

Interrupt for endpoint 1 OUT buffer. Cleared by Read

Last Transaction Status command.

Interrupt for endpoint 1 IN buffer. Cleared by Read Last

Transaction Status command.

Interrupt for endpoint 2 OUT buffer. Cleared by Read

Last Transaction Status command.

Interrupt for endpoint 2 IN buffer. Cleared by Read Last

Transaction Status command.

Interrupt for bus reset. This bit will be cleared after

reading.

Suspend Change

Interrupt for USB bus suspend status change. This bit

will be set to ‘1’ when FT121 goes to suspend (missing 3

continuous SOFs) or resumes from suspend. This bit will

be cleared after reading.

Table 6.9 Interrupt Register Byte 1

Bit

Symbol

Reset

00h

Description

7-0 Reserved

Reserved

Table 6.10 Interrupt Register Byte 2

Bit

0

Symbol

Reset

0

Description

Endpoint 3 Out

Interrupt for endpoint 3 OUT buffer. Cleared by Read

Last Transaction Status command.

1

2

3

Endpoint 3 In

Endpoint 4 Out

Endpoint 4 In

0

Interrupt for endpoint 3 IN buffer. Cleared by Read Last

Transaction Status command.

Interrupt for endpoint 4 OUT buffer. Cleared by Read

Last Transaction Status command.

Interrupt for endpoint 4 IN buffer. Cleared by Read Last

Transaction Status command.

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Bit

4

Symbol

Reset

0

Description

Endpoint 5 Out

Interrupt for endpoint 5 OUT buffer. Cleared by Read

Last Transaction Status command.

5

6

7

Endpoint 5 In

Endpoint 6 Out

Endpoint 6 In

0

Interrupt for endpoint 5 IN buffer. Cleared by Read Last

Transaction Status command.

Interrupt for endpoint 6OUT buffer. Cleared by Read Last

Transaction Status command.

Interrupt for endpoint 6 IN buffer. Cleared by Read Last

Transaction Status command.

Table 6.11 Interrupt Register Byte 3 (for Enhanced Mode)

Bit

0

Symbol

Reset

0

Description

Endpoint 7 Out

Interrupt for endpoint 7 OUT buffer. Cleared by Read

Last Transaction Status command.

1

Endpoint 7 In

0

Interrupt for endpoint 7 IN buffer. Cleared by Read Last

Transaction Status command.

7-2 Reserved

0b’xxxxxx Reserved

Table 6.12 Interrupt Register Byte 4 (for Enhanced Mode)

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6.3.2 Select Endpoint

Command

: 00-05h (00-0Fh for Enhanced Mode)

Data

: Read 1 byte

Bit

Symbol

Reset

0

Description

0

Full/Empty

0: selected endpoint buffer is empty

1: selected endpoint buffer is not empty

1

Stall

0

0: selected endpoint is not stalled

1: selected endpoint is stalled

7-2 Reserved

0b’xxxxxx Reserved

Table 6.13 Endpoint Status Register

6.3.3 Read Last Transaction Status

Command

: 40-45h (40-4Fh for Enhanced Mode)

Data

: Read 1 byte

Bit

Symbol

Reset

0

Description

0

Data Receive/Transmit

Success

0: indicate USB data receive or transmit not OK

1: indicate USB data receive or transmit OK

4-1 Error Code

0b’0000

Refer to Table 6.15

5

6

7

Setup Packet

0

0: indicate not a setup packet

1: indicate last received packet has a SETUP token

Data 0/1 Packet

0

0: packet has a DATA0 token

1: packet has a DATA1 token

Previous Status not

Read

0: previous transaction status was read

1: previous transaction status was not read

Table 6.14 Endpoint Last Transaction Status Register

Error Code

0000

Result

No error

0001

PID encoding error

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Error Code

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1101

1111

Result

PID unknown

Unexpected packet

Token CRC error

Data CRC error

Time out error

Reserved

Unexpected EOP

Packet NAKed

Sent stall

Buffer overflow

Bit stuff error

Wrong DATA PID

Table 6.15 Transaction error code

6.3.4 Read Endpoint Status

Command

: 80-85h (80-8Fh for Enhanced Mode)

Data

: Read 1 byte

Bit

Symbol

Reset

0b’00

0

Description

1-0 Reserved

Reserved

2

Setup packet

0: indicate not a setup packet

1: indicate last received packet has a SETUP token

4-3 Reserved

0b’xx

Reserved

5

Buffer 0 Full

0

0: buffer 0 is not filled up

1: buffer 0 is filled up

6

Buffer 1 Full

0

0: buffer 1 is not filled up

1: buffer 1 is filled up

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Bit

7

Symbol

Reset

0

Description

Endpoint Stalled

0: endpoint is not stalled

1: endpoint is stalled

Table 6.16 Endpoint Buffer Status Register

6.3.5 Read Buffer

Command

: E0h

Data

: Read multiple bytes

The Read Buffer command is used to read the received packet from the selected endpoint OUT buffer.

The data in the endpoint buffer is organized as follows:

byte 0: length of payload packet, MSB(for default mode this byte is ignored)

byte 1: length of payload packet, LSB

byte 2: Payload packet byte 1

byte 3: Payload packet byte 2

…

byte n+1: Payload packet byte n (n = packet length)

6.3.6 Write Buffer

Command

: F0h

Data

: Write multiple bytes

The Write Buffer command is used to write payload packet to the selected endpoint IN buffer.

The data must be organized in the same way as described in the Read Buffer command. For default mode

byte 0 should always be set to 00h.

6.3.7 Clear Buffer

Command

: F2h

Data

: None

The Clear Buffer command should be issued after all data has been read out from the endpoint buffer.

This is to free the buffer to receive next packet from USB host.

6.3.8 Validate Buffer

Command

: FAh

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Data

: None

The Validate Buffer command should be issued after all data has been written to the endpoint buffer. This

is to set the buffer full flag so that the packet can be sent to USB host when IN token arrives.

6.3.9 Set Endpoint Status

Command

: 50-55h (50-5Fh for Enhanced Mode)

Data

: Write 1 byte

Bit

Symbol

Reset

0

Description

0

Stall

0: Disable the endpoint STALL state.

1: Enable the endpoint STALL state.

For EP0 OUT (control OUT endpoint) the STALL state will

automatically be cleared by receiving a SETUP packet.

When this bit is written to ‘0’, the endpoint will

reinitialize. Any data in the endpoint buffer will be

flushed away, and the PID for next packet will carry

DATA0 flag.

7-1 Reserved

0b’xxxxxxx Reserved

Table 6.17 Endpoint Control Register

6.3.10 Acknowledge Setup

Command

Data

: F1h

: None

When receiving a SETUP packet the FT121 will flush the IN buffer and disable the Validate Buffer and

Clear Buffer commands for both Control IN and Control OUT endpoints. The MCU shall read and process

the SETUP packet, and then issue the Acknowledge Setup command to re-enable the Validate Buffer and

Clear Buffer commands. The Acknowledge Setup command must be sent to both Control IN and Control

OUT endpoints.

6.4 General Commands

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6.4.1 Read Current Frame Number

Command

Data

: F5h

: Read One or Two Bytes

Bit

Symbol

Reset

00h

Description

7-0 Frame Number LSB

Frame number for last received SOF, byte 1 (least

significant byte)

Table 6.18 Frame Number LSB Register

Bit

Symbol

Reset

Description

2-0 Frame Number MSB

0b’000

Frame number for last received SOF, byte 2 (Most

significant byte)

7-3 Reserved

0b’00000

Reserved

Table 6.19 Frame Number MSB Register

6.4.2 Send Resume

Command

Data

: F6h

: None

To perform remote-wakeup when suspended, the MCU needs to issue Send Resume command. The

FT121 will send an upstream resume signal for a period of 10 ms. If the clock is not running during

suspend, the MCU needs to wakeup FT121 by driving the SUSPEND pin to LOW, followed by the Send

Resume command.

6.4.3 Set 3-wire Mode

Command

Data

: E8h

: None

This command is used to enable the 3-wire SPI mode. Once enabled, the MOSI pin will become bi-

directional line and the MISO pin is not functional. Both SPI master and slave will drive data on the MOSI

line.

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6.4.4 Read Vendor ID

Command

: EBh (for Enhanced Mode)

: read 2 bytes

Data

Read the 2 bytes Vendor ID. Shall return 0403h.

6.4.5 Read Product ID

Command

: EAh (for Enhanced Mode)

Data

: read 2 bytes

Read the 2 bytes Product ID. Shall return 6018h.

6.4.6 Read FTDI ID

Command

: EDh (for Enhanced Mode)

Data

: read 1 byte

Read the 1 byte FTDI ID. Shall return 11h.

6.4.7 Set IO Pad Drive Strength

Command

Data

: E9h

: Write 1 byte

Bit

Symbol

Reset

0b’00

Description

Reserved, write to 0b’00

1-0 Reserved

3-2 MISO, MOSI pins

00: 4mA

01: 8mA

10: 12mA

11:16mA

5-4 INT_n, SUSPEND pins

0b’00

00: 4mA

01: 8mA

10: 12mA

11:16mA

7-6 Reserved

0b’00

Reserved, write to 0b’00

Table 6.20 IO Pad Drive Strength Register

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7 Application Information

Figure 7-1 shows a reference application circuit for a USB bus-powered application. Figure 7-1 shows a

reference application circuit for a USB self-powered application.

VCC3V3

VCC

Ferrite

Bead

100nF

1

VCC

DM

DP

10k

27R

2

3

GPIO

SUSPEND

INT_n

SS_n

4

GPIO

SS#

MCU

FT121

47pF

5

VBUS_S

SCLK

MISO

MOSI

10nF

SHIELD

RESET_n

MISO

VCC3V3

VCCIO

MOSI

VOUT3V3

n

_

D

C

VCC

D

N

D

N

G

B

100nF

4.7uF

100nF

+

Figure 7-1 FT121 bus powered application

VCC3V3

VCC

100nF

1M

10k

1

VCC

DM

DP

27R

2

3

SUSPEND

GPIO

SS#

4

INT_n

SS_n

SCLK

MISO

MOSI

470k

1M

MCU

FT121

47pF

5

VBUS_S

SCLK

MISO

MOSI

SHIELD

RESET_n

VCC3V3

VCCIO

VOUT3V3

n

_

D

C

VCC

D

N

D

N

G

B

100nF

4.7uF

100nF

+

Figure 7-2 FT121 self powered application

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8 Devices Characteristics and Ratings

8.1 Absolute Maximum Ratings

The absolute maximum ratings for the FT121 devices are as follows. These are in accordance with the

Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the

device.

Parameter

Value

Unit

Storage Temperature

-65 to 150

168

°C

Floor Life (Out of Bag) At Factory Ambient

(30°C / 60% Relative Humidity)

Hours

(IPC/JEDEC J-STD-033A MSL Level 3

Compliant)*

Ambient Temperature (Power Applied)

Latch-up current

-40 to 85

±200

°C

mA

Electrostatic Discharge Voltage(ESD)

human body model(HBM)

±2

kV

V

Electrostatic Discharge Voltage(ESD)

machine model(MM)

±200

±500

Electrostatic Discharge Voltage(ESD)

charged device model(CDM)

V

VCC Supply Voltage

-0.5 to +6.0

-0.5 to +3.8

V

DC Input Voltage – DP and DM

DC Input Voltage – High Impedance

-0.5 to + (VCC +0.5)

V

Bidirectional

DC Input Voltage – All Other Inputs

-0.5 to + (VCC +0.5)

22

V

DC Output Current – Outputs

mA

Table 8.1 Absolute Maximum Ratings

* If devices are stored out of the packaging beyond this time limit the devices should be baked before

use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours.

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8.2 DC Characteristics

DC Characteristics (Ambient Temperature = -40°C to +85°C).

Parameter

VCC1

Description

Minimum

4.0

Typical

5.0

Maximum

5.5

Units

Conditions

VCC Operating Supply

Voltage

V

Normal Operation

VCC Operating Supply

Voltage

Regulator by-pass

mode Operation

VCC2

3.0

3.3

3.6

VCCIO Operating

Supply Voltage

VCCIO

1.65

3.6

Normal Operation,

USB bus transmit

or receive

Operating Supply

Current

Icc

3.9

mA

USB Suspend,

Clock Running =

‘0’, excluding the

DP_Pullup current

Icc2

Suspend Current

84

μA

VOUT3V3

3.3v regulator output

3.0

3.3

3.6

V

VCC=5V

Table 8.2 Operating Voltage and Current

Parameter

Description

Minimum

Typical

Maximum

Units

Conditions

Voh

Vol

Vih

Vil

Output Voltage High

Output Voltage Low

Input Voltage High

Input Voltage Low

2.9

V

I source = 4mA

I sink = 4mA

0.4

0.8

2.0

-

Table 8.3 digital I/O Pin Characteristics (VCCIO=+3.3V)

Parameter

Description

Minimum

Typical

Maximum

Units

Conditions

Voh

Vol

Vih

Vil

Output Voltage High

Output Voltage Low

Input Voltage High

Input Voltage Low

2.25

V

I source = 4mA

I sink = 4mA

0.4

0.7

1.7

-

Table 8.4 digital I/O Pin Characteristics (VCCIO=+2.5V)

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Parameter

Description

Minimum

Typical

Maximum

Units

Conditions

Voh

Vol

Vih

Vil

Output Voltage High

Output Voltage Low

Input Voltage High

Input Voltage Low

1.62

V

I source = 4mA

I sink = 4mA

0.4

1.17

-

0.63

Table 8.5 digital I/O Pin Characteristics (VCCIO=+1.8V)

Parameter

Description

Minimum

Typical

Maximum

Units

Conditions

R_L= 1.5kΩ to 3.6

I/O Pins Static Output

(High)

V

UVoh

2.8

3.6

V

I/O Pins Static Output

(Low)

UVol

UVse

UCom

UVDif

-

0.3

2.0

2.5

V

R_L= 15kΩ to GND

Single Ended Rx

Threshold

0.8

0.2

Differential Common

Mode

Differential Input

Sensitivity

Including external

27 Ω ±1% series

resistor

Driver Output

Impedance

UDrvZ

29

-

44

Ω

Table 8.6 USB I/O Pin (DP, DM) Characteristics

8.3 AC Characteristics

Symbol

Parameter

VCCIO=3.3V VCCIO=1.8V Unit

Min

50

25

5

Max

Min

60

30

8

Max

t1

t2

t3

t4

SCLK period

ns

SCLK High period

SCLK Low period

SCLK driving edge to MOSI valid (3-wire mode)

SCLK driving edge to MISO valid (4-wire mode)

15

22

t5

t6

MOSI data setup time to sample SCLK edge

MOSI data hold time from sample SCLK edge

5

6

5

ns

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Symbol

Parameter

VCCIO=3.3V VCCIO=1.8V Unit

Min

Max

Min

Max

t7

t8

2

ns

SS_n setup time to rising SCLK edge

2

SS_n hold time from falling sample SCLK edge

Table 8.7 SPI slave timing

Note: All timing figures applied for both 4-wire and 3-wire modes.

Figure 8-1 SPI slave timing

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9 Package Parameters

The FT121 is available in two different packages. The FT121T is the TSSOP-16 package option and the

FT121Q is the QFN-16 package option. The solder reflow profile for both packages is described in section

9.5.

9.1 TSSOP-16 Package Dimensions

Figure 9-1 TSSOP-16 Package Dimensions

The FT121T is supplied in a RoHS compliant 16 pin TSSOP package. The package is lead (Pb) free and

uses a ‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.

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9.2 TSSOP-16 Package Markings

Line 1 – FTDI Logo

YYWW-B

FT121T

Line 2 – Date Code, Revision

Line 3 – FTDI Part Number

Figure 9-2 TSSOP-16 Package Markings

The date code format is YYWW where WW = 2 digit week number, YY = 2 digit year number.

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9.3 QFN-16 Package Dimensions

Figure 9-3 QFN-16 Package Dimensions

The FT121Q is supplied in a RoHS compliant leadless QFN-16 package. The package is lead ( Pb ) free,

and uses a ‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.

This package is nominally 3mm x 3mm. The solder pads are on a 0.50mm pitch. The above mechanical

drawing shows the QFN-16 package. All dimensions are in millimetres.

The center pads at the base of the FT121Q are internally connected to a power signal according to the

following table. These may be left unconnected or routed to the respective power signal:

Pad Number

Signal

Ground

VCCIO

VOUT3V3

VCC

Location – top view

Upper left

Location – bottom view

Upper right

17

18

19

20

Lower left

Lower right

Lower left

Upper right

Upper left

Table 9.1 FT121Q Bottom Pad Assignments

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9.4 QFN-16 Package Markings

Line 1 – FTDI Logo

Line 2 – Date Code, Revision

Line 3 – FTDI Part Number

YYWW-B

FT121Q

Figure 9-4 QFN-16 Package Markings

The date code format is YYWW where WW = 2 digit week number, YY = 2 digit year number.

9.5 Solder Reflow Profile

The FT121 is supplied in Pb free TSSOP-16 and QFN-16 packages. The recommended solder reflow profile

for both package options is shown in Figure 9-5.

t_p

T

p

Critical Zone: when

T is in the range

Ramp Up

T to T

p

L

T

L

t_L

T Max

S

Ramp

Down

T Min

S

t_S

Preheat

25

T = 25º C to T_P

Time, t (seconds)

Figure 9-5 FT121 Solder Reflow Profile

41

Document No.: FT_000648

FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC

Datasheet Version 1.2

The recommended values for the solder reflow profile are detailed in Table 9.2. Values are shown for both

a completely Pb free solder process (i.e. the FT121 is used with Pb free solder), and for a non-Pb free

solder process (i.e. the FT121 is used with non-Pb free solder).

Pb Free Solder

Profile Feature

Non-Pb Free Solder Process

Process

Average Ramp Up Rate (T_sto T_p)

3°C / second Max.

3°C / Second Max.

Preheat

100°C

150°C

- Temperature Min (T_sMin.)

- Temperature Max (T_sMax.)

- Time (t_sMin to t_sMax)

150°C

200°C

60 to 120 seconds

Time Maintained Above Critical

Temperature T_L:

217°C

183°C

- Temperature (T_L)

- Time (t_L)

60 to 150 seconds

Peak Temperature (T_p)

260°C

240°C

Time within 5°C of actual Peak

Temperature (t_p)

20 to 40 seconds

6°C / second Max.

8 minutes Max.

20 to 40 seconds

6°C / second Max.

6 minutes Max.

Ramp Down Rate

Time for T= 25°C to Peak Temperature,

T_p

Table 9.2 Reflow Profile Parameter Values

42

Document No.: FT_000648

FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC

Datasheet Version 1.2

10 Contact Information

Head Office – Glasgow, UK

Branch Office – Tigard, Oregon, USA

Future Technology Devices International Limited

Unit 1, 2 Seaward Place, Centurion Business Park

Glasgow G41 1HH

United Kingdom

Tel: +44 (0) 141 429 2777

Future Technology Devices International Limited

(USA)

7130 SW Fir Loop

Tigard, OR 97223

Tel: +1 (503) 547 0988

Fax: +1 (503) 547 0987

Fax: +44 (0) 141 429 2758

E-mail (Sales)

sales1@ftdichip.com

E-mail (Support)

E-mail (General Enquiries) admin1@ftdichip.com

support1@ftdichip.com

E-Mail (Sales)

E-Mail (Support)

E-Mail (General Enquiries)

us.sales@ftdichip.com

us.support@ftdichip.com

us.admin@ftdichip.com

Branch Office – Taipei, Taiwan

Branch Office – Shanghai, China

Future Technology Devices International Limited

(Taiwan)

2F, No. 516, Sec. 1, NeiHu Road

Taipei 114

Taiwan , R.O.C.

Tel: +886 (0) 2 8791 3570

Fax: +886 (0) 2 8791 3576

Future Technology Devices International Limited

(China)

Room 1103, No.666 West Huaihai Road,

Shanghai, 200052

China

Tel: +86 21 62351596

Fax: +86 21 62351595

E-mail (Sales)

E-mail (Support)

E-mail (General Enquiries) tw.admin1@ftdichip.com

tw.sales1@ftdichip.com

tw.support1@ftdichip.com

E-mail (Sales)

E-mail (Support)

E-mail (General Enquiries)

cn.sales@ftdichip.com

cn.support@ftdichip.com

cn.admin@ftdichip.com

Branch Office – Singapore

Future Technology Devices International Limited (Singapore)

178 Paya Lebar Road

#07-03/04/05

Singapore 409030

Tel: +65 6841 1174

Fax: +65 6841 6071

E-mail (Support)

support1@ftdichip.com

E-mail (General Enquiries) admin1@ftdichip.com

Web Site

http://ftdichip.com

System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future

Technology Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory

and system-level performance requirements. All application-related information in this document (including application

descriptions, suggested FTDI devices and other materials) is provided for reference only. While FTDI has taken care to

assure it is accurate, this information is subject to customer confirmation, and FTDI disclaims all liability for system designs

and for any applications assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is

entirely at the user’s risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages,

claims, suits or expense resulting from such use. This document is subject to change without notice. No freedom to use

patents or other intellectual property rights is implied by the publication of this document. Neither the whole nor any part of

the information contained in, or the product described in this document, may be adapted or reproduced in any material or

electronic form without the prior written consent of the copyright holder. Future Technology Devices International Ltd, Unit

1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number:

SC136640

43

Document No.: FT_000648

FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC

Datasheet Version 1.2

Appendix A – References

Useful Application Notes

http://www.ftdichip.com/Documents/AppNotes/AN_167_FT1248_Parallel_Serial_Interface_Basics.pdf

http://www.ftdichip.com/Support/Documents/TechnicalNotes/TN_100_USB_VID-PID_Guidelines.pdf

http://www.ftdichip.com/Support/Documents/AppNotes/AN_175_Battery%20Charging%20Over%20USB

%20with%20FTEX%20Devices.pdf

http://www.usb.org/developers/devclass_docs/BCv1.2_011912.zip

Appendix B - List of Figures and Tables

List of Figures

Figure 2-1 FT121 Block Diagram.....................................................................................................3

Figure 3-1 TSSOP-16 package schematic symbol..............................................................................6

Figure 3-2 QFN-16 package schematic symbol..................................................................................6

Figure 4-1 SPI access.................................................................................................................. 11

Figure 4-2 4-wire write operation.................................................................................................. 11

Figure 4-3 4-wire read operation .................................................................................................. 12

Figure 4-4 3-wire write operation.................................................................................................. 12

Figure 4-5 3-wire read operation .................................................................................................. 12

Figure 7-1 FT121 bus powered application ..................................................................................... 33

Figure 7-2 FT121 self powered application ..................................................................................... 33

Figure 8-1 SPI slave timing.......................................................................................................... 37

Figure 9-1 TSSOP-16 Package Dimensions..................................................................................... 38

Figure 9-2 TSSOP-16 Package Markings ........................................................................................ 39

Figure 9-3 QFN-16 Package Dimensions ........................................................................................ 40

Figure 9-4 QFN-16 Package Markings............................................................................................ 41

Figure 9-5 FT121 Solder Reflow Profile .......................................................................................... 41

List of Tables

Table 3.1 FT121 Pin Description......................................................................................................7

Table 4.1 Interrupt modes ........................................................................................................... 10

Table 5.1 Endpoint configuration for EP0 and EP1 ........................................................................... 14

Table 5.2 Endpoint configuration for EP2 ....................................................................................... 14

Table 5.3 Example buffer configuration.......................................................................................... 15

Table 5.4 Endpoint Maximum Packet Size ...................................................................................... 16

Table 6.1 FT121 default command set........................................................................................... 18

Table 6.2 enhanced command set................................................................................................. 22

Table 6.3 Address Enable Register ................................................................................................ 22

Table 6.4 Endpoint Enable Register............................................................................................... 22

Table 6.5 Configuration Register (Byte 1) ...................................................................................... 23

Table 6.6 Configuration Register (Byte 2) ...................................................................................... 23

Table 6.7 Interrupt Configuration Register ..................................................................................... 24

44

Document No.: FT_000648

FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC

Datasheet Version 1.2

Table 6.8 Endpoint Configuration Register...................................................................................... 24

Table 6.9 Interrupt Register Byte 1............................................................................................... 25

Table 6.10 Interrupt Register Byte 2 ............................................................................................. 25

Table 6.11 Interrupt Register Byte 3 (for Enhanced Mode)............................................................... 26

Table 6.12 Interrupt Register Byte 4 (for Enhanced Mode)............................................................... 26

Table 6.13 Endpoint Status Register.............................................................................................. 27

Table 6.14 Endpoint Last Transaction Status Register...................................................................... 27

Table 6.15 Transaction error code................................................................................................. 28

Table 6.16 Endpoint Buffer Status Register .................................................................................... 29

Table 6.17 Endpoint Control Register ............................................................................................ 30

Table 6.18 Frame Number LSB Register......................................................................................... 31

Table 6.19 Frame Number MSB Register........................................................................................ 31

Table 6.20 IO Pad Drive Strength Register..................................................................................... 32

Table 8.1 Absolute Maximum Ratings ............................................................................................ 34

Table 8.2 Operating Voltage and Current ....................................................................................... 35

Table 8.3 digital I/O Pin Characteristics (VCCIO=+3.3V).................................................................. 35

Table 8.4 digital I/O Pin Characteristics (VCCIO=+2.5V).................................................................. 35

Table 8.5 digital I/O Pin Characteristics (VCCIO=+1.8V).................................................................. 36

Table 8.6 USB I/O Pin (DP, DM) Characteristics.............................................................................. 36

Table 8.7 SPI slave timing ........................................................................................................... 37

Table 9.1 FT121Q Bottom Pad Assignments ................................................................................... 40

Table 9.2 Reflow Profile Parameter Values ..................................................................................... 42

45

Document No.: FT_000648

FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC

Datasheet Version 1.2

Appendix C - Revision History

Document Title:

DS_FT121

Document Reference No.:

Clearance No.:

FT_000648

FTDI# 312

Product Page:

http://www.ftdichip.com/Products/ICs/FT121.htm

Send Feedback

Document Feedback:

Version Draft

Version 1.0

Version 1.1

Version 1.2

Initial draft

July 2012

Initial release

1^stOctober 2012

15^thJuly 2013

23^rdMar 2015

Updated FT121Q bottom pad assignments

Updated release

46


型号：	FT121
厂家：	FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD.
描述：	FT121 ENHANCED USB DEVICE CONTROLLER WITH SPI SLAVE IC Datasheet Version 1.2
文件：	总46页 (文件大小：1092K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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