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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Future Technology

Devices International Ltd

Vinculum-II

Embedded Dual USB Host

Controller IC

Vinculum-II is FTDI’s 2nd generation of USB Host

device. The CPU has been upgraded from the

previous VNC1L device, dramatically increasing the

processing power. The IC architecture has been

designed to take care of most of the general USB

data transfers, thus freeing up processing power

for user applications. Flash and RAM memory have

been increased providing larger user areas of

memory for the designer to incorporate his own

code. The designers also have the ability to create

their own firmware using the new suite of software

development tools.

.

Eight bit wide FIFO Interface

Firmware upgrades via UART, SPI, and

FIFO interface

.

12MHz oscillator using external crystal

General-purpose timers

+3.3V single supply operation with 5V

safe inputs

.

Software development suite of tools to

create customised firmware. Compiler

Linker – Debugger – IDE

VNC2 has the following advanced features:

Available in six RoHS compliant

packages - 32 LQFP, 32 QFN, 48 LQFP,

48 QFN, 64 LQFP and 64 QFN

.

Embedded processor core

16 bit Harvard architecture

.

VNC2-48L1 package optioncompatible

with VNC1L-1A

Two full-speed or low-speed USB 2.0

interfaces capable of host or slave

functions

44 configurable I/O pins on the 64 pin

device, 28 I/O pins on the 48 pin

device and 12 I/O on the 32 pin device

using the I/O multiplexer

.

256kbytes on-chip E-Flash Memory

(128k x 16-bits)

16kbytes on-chip Data RAM (4k x 32-

bits

.

-40°C to +85°C extended operating

temperature range

.

Programmable UART up to 6Mbaud

Simultaneous multiple file access on

BOMS devices

Two SPI (Serial Peripheral) slave

interfaces and one SPI master

interface

Eight Pulse Width Modulation outputs

to allow connectivity with motor

control applications

.

Reduced power modes capability

Variable instruction length

.

Debugger interface module

SystemSuspend Modes

Native support for 8, 16 and 32 bit

data types

Use of FTDI devicesin life support and/or safety applicationsis entirely at the user’srisk, and the user agrees to

defend, indemnify and hold harmlessFTDI fromany andall damages, claims, suitsor expense resulting from such

use.

1

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

1 Typical Applications



Add USB host capability to embedded

products



Mobile phone to USB Flash drive*

GPS to mobile phone interface

Instrumentation USB Flash drive*

Data-logger USB Flash drive*

Set Top Box - USB device interface

GPS tracker with USB Flash disk storage

USB webcam



Interface USB Flash drive to

MCU/PLD/FPGA – data storage and

firmware updates



USB Flash drive data storage or firmware

updates

USB Flash drive to USB Flash drive file

transfer interface

Flash drive to SD Card data transfer

Vending machine connectivity

TLM Serial converter



Digital camera to USB Flash drive*

PDA to USB Flash drive*

MP3 Player to USB Flash drive or other USB

slave device interface

Geotaggingof photos – GPS location linked

to image



OSI Wireless Interface



Motorcycle systemtelemetry logging

Medical systems

USB wireless process controller

Telecomsystemcalls logging to replace

printer log

PWM applications for motor control

applications e.g. Toys



Data logging



FPGA Interfacing

* Or similar USB slave device interface e.g. USB external drive.

1.1 Part Numbers

Part Number

VNC2-64L

VNC2-64Q

VNC2-48L

VNC2-48Q

VNC2-32L

VNC2-32Q

Package

64 Pin LQFP

64 Pin QFN

48 Pin LQFP

48 Pin QFN

32 Pin LQFP

32 Pin QFN

Table 1.1 Part Numbers

Please refer to section 11 for all package mechanical parameters.

1.2 USB Compliant

At time of writing this data sheet, VNC2 has not completedUSB compliancy testing.

2

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

2 VNC2 Block Diagram

For a description of each function please refer to Section 4.

XTOUT

UART

PWMs

Oscillator/

PLL

Internal Clocks and Timers

XTIN

256K Bytes

E-FLASH

Flash

Programmer

(64K x 32)

FIFO

Interface

Debugger

SPI Master

SPI Slave 1

SPI Slave 0

GPIOS

Embedded

CPU

DMA

0

DMA

1

General

Purpose

Timers

DMA

2

16K Bytes

Data Ram

(4K x 32)

DMA

3

Debugger I/F

USB Host/

Device

Controller

8 bit bus

USB Host/

Device

Transceiver 0

USB1DP

USB1DM

32 bit bus

USB Host/

Device

Controller

USB Host/

Device

Transceiver 1

USB2DP

USB2DM

Figure 2.1 Simplified VNC2 Block Diagram

3

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Table of Contents

1

Typical Applications................................................................... 2

1.1 Part Numbers...........................................................................................2

1.2 USB Compliant .........................................................................................2

2

3

VNC2 Block Diagram.................................................................. 3

Device Pin Out and Signal Description Summary......................... 7

3.1 Pin Out - 32 pin LQFP.............................................................................7

3.2 Pin Out - 32 pin QFN...............................................................................8

3.3 Pin Out - 48 pin LQFP..............................................................................9

3.4 Pin Out - 48 pin QFN.............................................................................10

3.5 Pin Out - 64 pin LQFP...........................................................................11

3.6 Pin Out - 64 pin QFN.............................................................................12

3.7 VNC2 Schematic symbol 32 Pin ............................................................13

3.8 VNC2 Schematic symbol 48 Pin ............................................................14

3.9 VNC2 Schematic symbol 64 Pin ............................................................15

3.10

3.11

3.12

Pin Configuration USB and Power......................................................16

Miscellaneous Signals.........................................................................17

Pin Configuration Input / Output ......................................................18

4

Function Description.................................................................21

4.1 Key Features..........................................................................................21

4.2 Functional Block Descriptions...............................................................21

4.2.1 Embedded CPU..................................................................................................................21

4.2.2 Flash Module......................................................................................................................21

4.2.3 Flash Programming Module ................................................................................................21

4.2.4 Input / Output Multiplexer Module......................................................................................22

4.2.5 Peripheral DMA Modules 0, 1, 2 & 3....................................................................................23

4.2.6 RAM Module.......................................................................................................................23

4.2.7 Peripheral Interface Modules..............................................................................................23

4.2.8 USB Transceivers 0 and 1 ..................................................................................................23

4.2.9 USB Host / Device Controllers............................................................................................23

4.2.10

4.2.11

12MHz Oscillator............................................................................................................23

Power Saving Modes and Standby mode.........................................................................23

5

I/O Multiplexer ........................................................................24

5.1 I/O Peripherals Signal Names ..............................................................29

5.2 I/O Multiplexer Configuration ..............................................................30

5.3 I/O Mux Group 0....................................................................................31

5.4 I/O Mux Group 1....................................................................................32

4

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

5.5 I/O Mux Group 2....................................................................................33

5.6 I/O Mux Group 3....................................................................................34

5.7 I/O Mux Interface Configuration Example...........................................35

6

Peripheral Interfaces................................................................36

6.1 UART Interface ......................................................................................36

6.1.1 UART Mode Signal Descriptions..........................................................................................37

6.2 Serial Peripheral Interface – SPI Modes..............................................39

6.2.1 SPI Clock Phase Modes.......................................................................................................40

6.3 Serial Peripheral Interface – Slave.......................................................41

6.3.1 SPI Slave Signal Descriptions.............................................................................................42

6.3.2 Full Duplex.........................................................................................................................43

6.3.3 Half Duplex, 4 pin..............................................................................................................45

6.3.4 Half Duplex, 3 pin..............................................................................................................46

6.3.5 Unmanaged Mode ..............................................................................................................47

6.3.6 VNC1L Legacy Interface.....................................................................................................48

6.4 Serial Peripheral Interface – SPI Master..............................................53

6.4.1 SPI Master Signal Descriptions...........................................................................................53

6.5 Debugger Interface ...............................................................................56

6.5.1 Debugger Interface Signal description................................................................................56

6.6 Parallel FIFO – Asynchronous Mode .....................................................57

6.6.1 FIFO Signal Descriptions ....................................................................................................57

6.6.2 Read / Write Transaction Asynchronous FIFO Mode ............................................................59

6.7 Parallel FIFO – Synchronous Mode .......................................................61

6.7.1 Read / Write Transaction Synchronous FIFO Mode..............................................................62

6.8 General Purpose Timers ........................................................................63

6.9 Pulse Width Modulation.........................................................................63

6.10

General Purpose Input Output ...........................................................64

7

8

USB Interfaces .........................................................................65

Firmware .................................................................................66

8.1 RTOS.......................................................................................................66

8.2 Device drivers ........................................................................................66

8.3 Firmware – Software Development Toolchain .....................................66

8.4 Precompiled Firmware ..........................................................................67

Device Characteristics and Ratings............................................68

9.1 Absolute Maximum Ratings...................................................................68

9.2 DC Characteristics .................................................................................69

9.3 ESD and Latch-up Specifications ..........................................................71

9

10 Application Examples ...............................................................72

5

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

10.1

Example VNC2 Schematic (MCU – UART Interface)..........................72

11 Package Parameters.................................................................73

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

VNC2 Package Markings ....................................................................73

VNC2, LQFP-32 Package Dimensions.................................................74

VNC2, QFN-32 Package Dimensions ..................................................75

VNC2, LQFP-48 Package Dimensions.................................................76

VNC2, QFN-48 Package Dimensions ..................................................77

VNC2, LQFP-64 Package Dimensions.................................................78

VNC2, QFN-64 Package Dimensions ..................................................79

Solder Reflow Profile ..........................................................................80

12 Contact Information .................................................................82

Appendix A – References .................................................................83

Application, Technical Notes,Toolchain download and precompiled romfile

links .................................................................................................................83

Acronyms and Abbreviations..........................................................................84

Appendix B – List of Figures and Tables............................................85

List of Tables ...................................................................................................85

List of Figures..................................................................................................85

Appendix C – Revision History..........................................................88

6

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3 Device Pin Out and Signal DescriptionSummary

VNC2 is available in six packages: 32 pin LQFP, 32 pin QFN, 48 pin LQFP (pin compatible with VNC1L), 48

pin QFN, 64 pin LQFP and 64 pin QFN. Figure 3.3 shows how the VNC2 pins map to the VNC1L pins

(VNC2 pins labelled in bold text):

3.1 Pin Out - 32 pin LQFP

25

IO BUS6

GND IO

16

15

14

13

12

11

10

9

IO BUS3

IO BUS2

VCCIO 3.3V

IO BUS1

IO BUS0

RESET#

PROG#

26

27

28

29

30

31

32

IO BUS7

GND Core

VCCIO 3.3V

IO BUS8

FTDI

XXXXXXXXXX

VNC2-32L1A

YYWW

IO BUS9

IO BUS10

IO BUS11

Figure 3.1 32 Pin LQFP – Top Down View

7

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.2 Pin Out - 32 pin QFN

GND IO

IO BUS3

IO BUS2

16

15

14

13

25

26

27

28

IO BUS6

IO BUS7

GND Core

VCCIO 3.3V

IO BUS8

FTDI

VCCIO 3.3V

IO BUS1

IO BUS0

RESET#

PROG#

XXXXXXXXXX

12

11

29

30

VNC2-32Q

1A YYWW

IO BUS9

10

9

IO BUS10

IO BUS11

31

32

Figure 3.2 32 Pin QFN – Top Down View

8

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.3 Pin Out - 48 pin LQFP

GND

GND IO

24

23

22

21

20

19

18

17

16

15

14

13

IO BUS18 ADBUS6

IO BUS19 ADBUS7

37

38

39

40

41

42

43

44

45

46

47

48

BCBUS3

BCBUS2

BCBUS1

BCBUS0

BDBUS7

BDBUS6

VCCIO

IO BUS11

IO BUS10

IO BUS9

IO BUS8

IO BUS7

IO BUS6

VCCIO 3.3V

IO BUS5

IO BUS4

IO BUS3

IO BUS2

GND Core

GND

FTDI

VCCIO 3.3V

VCCIO

IO BUS20 ACBUS0

IO BUS21 ACBUS1

IO BUS22 ACBUS2

IO BUS23 ACBUS3

IO BUS24 ACBUS4

IO BUS25 ACBUS5

IO BUS26 ACBUS6

IO BUS27 ACBUS7

XXXXXXXXXX

VNC2-48L1A

BDBUS5

BDBUS4

BDBUS3

BDBUS2

YYWW

ITALIC TEXT = VNC1

BOLD TEXT = VNC2

Figure 3.3 48 Pin LQFP – Top Down View

9

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.4 Pin Out - 48 pin QFN

GND IO

24

IOBUS18

IOBUS19 38

37

23

IOBUS11

GND

VCCIO 3.3V

IOBUS20

39

40

41

42

43

22 IOBUS10

FTDI

IOBUS9

21

IOBUS8

IOBUS7

20

19

18

17

16

15

14

13

XXXXXXXXXX

IOBUS21

IOBUS22

IOBUS6

VNC2-48Q1A

VCCIO 3.3 V

IOBUS5

IOBUS23 44

IOBUS24

IOBUS25

IOBUS26

IOBUS27

45

46

47

48

YYWW

IOBUS4

IOBUS3

IOBUS2

Figure 3.4 48 Pin QFN – Top Down View

10

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.5 Pin Out - 64 pin LQFP

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

IO BUS30

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

IO BUS19

IO BUS18

IO BUS31

IO BUS32

IO BUS33

GND Core

VCCIO 3.3V

IO BUS34

IO BUS35

IO BUS36

IO BUS37

IO BUS38

IO BUS39

IO BUS40

IO BUS41

IO BUS42

IO BUS43

GND IO

IO BUS17

IO BUS16

IO BUS15

IO BUS14

IO BUS13

IO BUS12

IO BUS11

IO BUS10

VCCIO 3.3V

IO BUS9

IO BUS8

IO BUS7

IO BUS6

FTDI

XXXXXXXXXX

VNC2-64L1A

YYWW

Figure 3.5 64 Pin LQFP – Top Down View

11

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.6 Pin Out - 64 pin QFN

IOBUS30

IOBUS31

IOBUS32

IOBUS33

GND CORE

VCCIO 3.3V

IOBUS34

IOBUS35

IOBUS36

IOBUS19

IOBUS18

GND IO

49

50

51

52

53

54

55

56

57

32

31

30

29 IOBUS17

28 IOBUS16

FTDI

XXXXXXXXXX

VNC2-64Q1A

YYWW

IOBUS15

27

26

25

24

IOBUS14

IOBUS13

IOBUS12

IOBUS37 58

23 IOBUS11

IOBUS38

59

IOBUS10

VCCIO 3.3V

IOBUS9

22

21

20

19

IOBUS39

IOBUS40

IOBUS41

60

61

62

IOBUS8

IOBUS42 63

64

18 IOBUS7

IOBUS6

17

IOBUS43

Figure 3.6 64 Pin QFN – Top Down View

12

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.7 VNC2 Schematic symbol 32 Pin

2

28 22 13

3

V

C

P

L

I

V

R

E

G

I

V V

C C

V

C

I

O O

O

17

N

USB1DP

11

12

14

IOBUS0

IOBUS1

IOBUS2

IOBUS3

IOBUS4

18

20

21

N

USB1DM

USB2DP

USB2DM

15

23

24

4

5

XTIN

VNC2

32 Pin

IOBUS5

IOBUS6

IOBUS7

IOBUS8

25

26

29

XTOUT

10

RESET#

PROG#

30

31

32

IOBUS9

IOBUS10

IOBUS11

9

7

8

VREG OUT

NC

G

N

D

P

L

G

N

D

G

N

D

G

N

D

G

N

D

L

1

6

16 19 27

Figure 3.7 Schematic Symbol 32 Pin

13

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.8 VNC2 Schematic symbol 48 Pin

40 30 17

2

3

11

12

13

V V

C C

V

C

I

V

C

P

L

I

V

IOBUS0

IOBUS1

IOBUS2

IOBUS3

IOBUS4

R

E

G

I

O O

O

14

15

16

18

19

25

N

USB1DP

26

28

29

N

IOBUS5

IOBUS6

IOBUS7

USB1DM

USB2DP

USB2DM

20

21

22

IOBUS8

IOBUS9

IOBUS10

IOBUS11

IOBUS12

4

5

23

31

32

33

34

XTIN

XTOUT

VNC2

48 Pin

IOBUS13

IOBUS14

IOBUS15

9

35

36

37

RESET#

PROG#

IOBUS16

IOBUS17

IOBUS18

IOBUS19

IOBUS20

10

38

41

42

43

44

7

8

VREG OUT

NC

IOBUS21

IOBUS22

IOBUS23

G

N

D

45

46

47

48

IOBUS24

IOBUS25

IOBUS26

IOBUS27

G

N

D

G

N

D

G

N

D

G

N

D

P

L

1 6 24 27 39

Figure 3.8 Schematic Symbol 48 Pin

14

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.9 VNC2 Schematic symbol 64 Pin

54 38 21

2

3

11

12

13

V

C

I

V

C

I

V

C

P

L

I

V

C

I

V

IOBUS0

IOBUS1

IOBUS2

IOBUS3

IOBUS4

R

E

G

I

O

O O

14

15

16

17

18

33

N

USB1DP

34

36

37

N

IOBUS5

IOBUS6

IOBUS7

USB1DM

USB2DP

USB2DM

19

20

22

IOBUS8

IOBUS9

IOBUS10

IOBUS11

IOBUS12

4

5

23

24

25

26

27

XTIN

XTOUT

IOBUS13

IOBUS14

IOBUS15

9

28

29

31

RESET#

PROG#

IOBUS16

IOBUS17

IOBUS18

IOBUS19

IOBUS20

10

VNC2

64 Pin

32

39

40

41

42

7

8

VREG OUT

NC

IOBUS21

IOBUS22

IOBUS23

43

44

45

IOBUS24

IOBUS25

IOBUS26

IOBUS27

IOBUS28

46

47

48

49

50

64

IOBUS43

63

62

61

IOBUS42

IOBUS41

IOBUS40

IOBUS29

IOBUS30

IOBUS31

60

59

58

57

IOBUS39

IOBUS38

IOBUS37

IOBUS36

51

52

IOBUS32

IOBUS33

IOBUS34

IOBUS35

55

56

G

N

D

G

N

D

G

N

D

G

N

D

G

N

D

P

L

1 6 30 35 53

Figure 3.9 Schematic Symbol 64 Pin

15

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.10 Pin Configuration USB and Power

Pin No

48 pin

Name

Type

Description

64 pin

32 pin

USB host/slave port 1 - USB Data Signal Plus with

integrated pull-up/pull-down resistor.

33

25

26

28

29

17

USB1DP

USB1DM

USB2DP

USB2DM

I/O

USB host/slave port 1 - USB Data Signal Minus with

integrated pull-up/pull-down resistor.

34

36

37

18

20

21

USB host/slave port 2 - USB Data Signal Plus with

integrated pull-up/pull-down resistor.

USB host/slave port 2 - USB Data Signal Minus with

integrated pull-up/pull-down resistor.

Table 3.1 USB Interface Group

Pin No

48 pin

Name

Type

Description

64 pin

32 pin

1, 30,

35, 53

1, 24,

27, 39

1, 16,

19, 27

GND

PWR

Device groundsupply pins.

3.3V

VREGIN

2

3

2

3

+3.3V supply to the regulator.

+1.8V supply to the internal clock multiplier. This pin

requires a 100nF decouplingcapacitor.

1.8V

VCC PLL

IN

* 48 pin LQFP package only – This power input is internally

connected to VREG_OUT.

3*

PWR

All other packages need this pin connectedto a 1.8V power

source. Most common applications will connect this to

VREG_OUT.

6

7

6

7

GND PLL

PWR

Device analogue ground supply for internal clock multiplier.

1.8V output from regulatorto device core

VREG

OUT

7*

Output

* N/C on 48 pin LQFP package only.

All other packages will typically need to connect pins 7 and

3.

+3.3V supply to the input / output. Interface pins

(IOBUS). Leaving the VCCIO unconnected will leadto

unpredictable operationon the interface pins.

21, 38,

54

17, 30,

40

13, 22,

28

VCCIO

PWR

Table 3.2 Power and Ground

16

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.11 Miscellaneous Signals

Pin No

Name

Type

Description

64 pin

48 pin

32 pin

Input to 12MHz Oscillator Cell. Connect 12MHz crystal

across pins 4 and 5. If drivenby an external source,

reference to 1.8V VCC PLL IN.

4

XTIN

Input

Output from 12MHz Oscillator Cell. Connect 12MHz crystal

across pins 4 and 5. No connect if XTIN is driven by an

external source.

5

XTOUT

Output

8

9

8

9

8

10

9

NC

No Connect (rev C) – (wasTESTRev A, B)

RESET#

PROG#

Input

Can be usedby an external device to reset VNC2.

Asserting PROG# on its own enables programming mode.

10

Table 3.3 Miscellaneous Signal Group

Note 1: # is used to indicate an active low signal.

Note 2: Pin 9 and 10 are 5V safe inputs

17

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

3.12 Pin Configuration Input / Output

VNC2 has multiple interfaces available for connecting to external devices. These are UART, FIFO, SPI

slave, SPI master, GPIO and PWM. The Interface I/O Multiplexer is used to share the available I/O Pins

between each peripheral.

VNC2 is configured with default settings for the I/O pins however they can be easily changed to suit the

needs of a designer. This is explained in Section 5 – I/O Multiplexer. Default configuration for each

package type is shown in Table 3.4- Default I/O Configuration. The signal names are also indicated

for the VNC1L device as it is pin-compatible with the 48 pin LQFP VNC2 device.

Note: The default values of the pins listed in the following table are only available when the

I/O Mux is enabled. A blank VNC2 chip defaults to all I/O pins as inputs.

Pin No

Name

64 Pin

48 Pin

32 PIN

Default

Type Description

(VINC1-L)

Default

64

48

32

IOBUS0

(BDBUS0)

11

debug_if

I/O

GPIO

IOBUS1

(BDBUS1)

12

13

14

15

16

17

18

19

20

22

23

24

25

26

12

13

14

15

16

18

19

20

21

22

23

31

32

33

12

14

15

23

24

25

26

29

30

31

32

-

Input

pwm[1]

pwm[2]

gpio[A1]

gpio[A2]

I/O

GPIO

IOBUS2

(BDBUS2)

Input

IOBUS3

(BDBUS3)

Input

pwm[3]

gpio[A3]

IOBUS4

(BDBUS4)

fifo_data[0]

fifo_data[1]

fifo_data[2]

fifo_data[3]

fifo_data[4]

fifo_data[5]

fifo_data[6]

fifo_data[7]

fifo_rxf#

spi_s0_clk

spi_s0_mosi

spi_s0_miso

spi_s0_ss#

spi_m_clk

spi_m_mosi

spi_m_miso

spi_m_ss_0#

uart_txd

IOBUS5

(BDBUS5)

uart_rxd

IOBUS6

(BDBUS6)

uart_rts#

uart_cts#

spi_s0_clk

spi_s0_mosi

spi_s0_miso

spi_s0_ss#

IOBUS7

(BDBUS7)

IOBUS8

(BCBUS0)

IOBUS9

(BCBUS1)

IOBUS10

(BCBUS2)

IOBUS11

(BCBUS3)

IOBUS12

(ADBUS0)

IOBUS13

(ADBUS1)

-

fifo_txe#

fifo_rd#

uart_rxd

IOBUS14

(ADBUS2)

-

uart_rts#

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Pin No

Name

64 Pin

48 Pin

32 PIN

Default

Type Description

(VINC1-L)

Default

64

48

32

IOBUS15

(ADBUS3)

27

28

29

31

32

39

40

41

42

43

44

45

46

34

35

36

37

38

41

42

43

44

45

46

47

48

-

fifo_wr#

fifo_oe#

Input

uart_cts#

uart_dtr#

uart_dsr#

uart_dcd#

uart_ri#

I/O

GPIO

IOBUS16

(ADBUS4)

IOBUS17

(ADBUS5)

IOBUS18

(ADBUS6)

Input

IOBUS19

(ADBUS7)

Input

IOBUS20

(ACBUS0)

uart_txd

uart_rxd

uart_rts#

uart_cts#

uart_dtr#

uart_dsr#

uart_dcd#

uart_ri#

uart_tx_active

gpio[A5]

IOBUS21

(ACBUS1)

IOBUS22

(ACBUS2)

gpio[A6]

IOBUS23

(ACBUS3)

gpio[A7]

IOBUS24

(ACBUS4)

gpio[A0]

IOBUS25

(ACBUS5)

gpio[A1]

IOBUS26

(ACBUS6)

gpio[A2]

IOBUS27

(ACBUS7)

gpio[A3]

47

48

49

50

51

52

55

56

57

-

IOBUS28

IOBUS29

IOBUS30

IOBUS31

IOBUS32

IOBUS33

IOBUS34

IOBUS35

IOBUS36

uart_tx_active

Input

I/O

GPIO

Input

spi_s0_clk

spi_s0_mosi

spi_s0_miso

spi_s0_ss#

spi_s1_clk

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Pin No

Name

64 Pin

48 Pin

32 PIN

Default

Type Description

(VINC1-L)

Default

64

48

32

58

59

60

61

62

63

64

-

IOBUS37

IOBUS38

IOBUS39

IOBUS40

IOBUS41

IOBUS42

IOBUS43

spi_s1_mosi

spi_s1_miso

spi_s1_ss#

spi_m_clk

I/O

GPIO

spi_m_mosi

spi_m_miso

spi_m_ss_0#

Table 3.4 Default I/O Configuration

Note: All GPIO are 5V safe inputs

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Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

4 Function Description

VNC2 is the second of FTDIs Vinculum family of Embedded USB host controller integrated circuit devices.

VNC2 can encapsulate certain USB device classes by handling the USB Host Interface and data transfer

functions using the in-built EMCU and embedded Flash memory. When interfacing to mass storage

devices, such as USB Flash drives, VNC2 transparently handles the FAT file structure using a simple to

implement command set. VNC2 provides a cost effective solution for introducing USB host capability into

products that previously did not have the hardware resources to do so.

VNC2 has an associated software development tool suite to allow users to create customised firmware.

4.1 Key Features

VNC2 is a programmable SoC device with a powerful embedded microprocessor core and dual USB

interfaces, large RAM and Flash capacity and the ability to develop and customise firmware using the

VNC2 Toolchain. VNC2 has an enhanced feature list over and above VNC1L; however the 48 pin LQFP

package is backward compatible with the VNC1L.

4.2 Functional Block Descriptions

The following paragraphs describe each function within VNC2. Please refer to the block diagram shown in

Figure 2.1

4.2.1 Embedded CPU

The processor core is based on FTDIs proprietary 16-bit embedded MCU architecture. The EMCU has a

Harvard architecture with separate code and data space.

4.2.2 Flash Module

VNC2 has 256k bytes (128k x 16-bits) of embedded Flash (E-FLASH) memory. No special programming

voltages are necessary for programming the on-board E-FLASH as these are provided internally on-chip.

4.2.3 Flash Programming Module

The purpose of the flash programmer module is to perform all necessary operations for programming the

flash, from general usage to first power on sequencing. This block is responsible for handling device

firmware upgrades which can be accessed by the debugger interface, a USB cable or Flash drive

interface.

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Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

4.2.4 Input / Output Multiplexer Module

VNC2 peripheral interfaces are UART, SPI slave0, SPI slave1, SPI master, FIFO-Asynchronous, FIFO-

Synchronous, GPIO, debug interface and PWM.

The I/O multiplexer allows the designer to select which peripherals are connectedto the device I/O pins.

The selectable peripheral interfaces are only limited by the number of I/O pins available. All peripherals

are available across the package range except synchronous FIFO mode which cannot be selected on 32

pin packages. The available configurable I/O pins per package are as follows:



32 pin package – 12 I/O pins

48 pin package – 28 I/O pins

64 pin package – 44 I/O pins

Table 4.1 lists the peripherals which can be multiplexed to I/O and the maximum number of pins

required for each one. The designer can choose any mix of peripheral configurations as long as they are

within the specific package I/O pin count. Depending on the design not all 9 UART pins need to be

configured. Similarly the GIPO peripheral does not need all pins configured.

e.g. The 48 pin package has 28 I/O pins which could be configured as UART – 9 pins, SPI Master – 5

pins, FIFO Asynchronous – 12 pins and GPIO – 2 pins. This makes a total of 28 pins.

Please refer to Section 5 for a detailed description of the I/O multiplexer.

Peripherals

UART

Maximum pins required

9

4

SPI Slave 0

SPI Slave 1

SPI Master

FIFO Asynchronous

FIFO Synchronous

GPIO

4

5

12

14

40

1

Debug

PWM

8

Table 4.1 - Peripheral Pin Requirements

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Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

4.2.5 Peripheral DMA Modules 0, 1, 2 & 3

The peripheral DMA has the capability to transfer data to and from an I/O device. The CPU can offload

the transfer of data between the processor and the peripheral freeing the CPU to execute other

instructions.

The DMA module collects or transmits data from memory to an I/O address space; it is also capable of

copying data in memory and transferring it to another location.

The DMA is not accessible by the user as it automatically controlledby the CPU.

4.2.6 RAM Module

The RAM module consists of 16k bytes on-chip (4k x 32-bits) data memory. The RAM is byte addressable.

4.2.7 Peripheral Interface Modules

VNC2 has nine peripheral interface modules. Full descriptions of each module are described in section 6.



Debugger Interface



SPI Master

UART

PWM

FIFO

SPI Slave 0 & 1

GPIO - General purpose I/O pins

General purpose timers

4.2.8 USB Transceivers 0 and 1

Two USB transceiver cells provide the physical USB device interface supporting USB 1.1 and USB 2.0

standards. Low-speed and full-speed USB data rates are supported. Each output driver provides +3.3V

level slew rate control signalling, whilst a differential receiver and two single ended receivers provide USB

DATA IN, SE0 and USB Reset condition detection. These cells also include integrated internal USB pull-up

or pull-down resistors as required for host or slave mode.

4.2.9 USB Host / Device Controllers

These blocks handle the parallel-to-serial and serial-to-parallel conversion of the USB physical layer. This

includes bit stuffing, CRC generation, USB frame generation and protocol error checking. The Host /

Device controller is autonomous and therefore requires limited load fromthe CPU.

4.2.10 12MHz Oscillator

The 12MHz Oscillator cell generates a 12MHz reference clock input to the Clock Multiplier PLL from an

external 12MHz crystal. The external crystal is connected across Pin 4 – XTIN and Pin 5 – XTOUT in the

configuration shown in Figure 10.1.

4.2.11 Power Saving Modes and Standby mode.

VNC2 can be set to operate in three frequencies allowing the user to select a slower speed to reduce

power consumption. Three operating frequencies available are 12MHz, 24MHz and normal operation of

48MHz. These operating modes can be configured using the RTOS. Full details are available in the RTOS

manual available fromthe FTDI website.

When a particular peripheral is not used, it is powered downinternally thus saving power.

Standby mode is available under firmware control, this mode puts the VNC2 in a state with no clocks

running or system blocks powered. The device will wake up out of this mode by toggling any of the

following signals: USB0/1 DP or DM, SPI slave 0 select (spi_s0_ss#), SPI slave 1select (spi_s1_ss#) or

UART ring indicator (uart_ri#).

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Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

5 I/O Multiplexer

FTDI devices typically have multiple interfaces available to communicate with external devices. VNC2 has

UART, SPI slave0, SPI slave1, SPI master, FIFO, GPIO, and PWM peripherals. The available packages for

VNC2 provide any of these interfaces to be active on the available pins through the use of an I/O

Multiplexer. Table 5.1 lists the signals available for each peripheral. Table 5.2 to 12 explain the use of

the I/O multiplexer.

Multiplexers are used to connect the VNC2 peripherals to the external IOBUS pins. This enables the

designer to select which IOBUS pins he wishes to map a particular peripheral to. Peripheral signals are

allocated to one of four groups, which connect to the I/O multiplexer. Each I/O peripheral signal can

connect to one out of every four external IOBUS pins. The IOBUS pin that a peripheral signal can connect

to is dictated by the peripheral signal’s group. For example, if a peripheral signal is allocated to group 0

then it can connect to IOBUS0, IOBUS4, IOBUS8, and IOBUS12 and so on. If a peripheral signal is

allocated to group 1 then it can connect to IOBUS1, IOBUS5, IOBUS9, and IOBUS13 and so on. Figure

5.1 details the I/O multiplexer concept, where, for example, a white peripheral signal can connect to any

white IOBUS pin; a green peripheral signal can connect to a green IOBUS pin. Figure 5.2, Figure 5.3 and

Figure 5.4 give examples of connecting peripheral signals to differing IOBUS pins.

The IO Multiplexer also provides the following features:



Ability to configure an I/O pad as an input, output or bidirectional pad.

At power on reset, all pins are set as inputs by default. Whenever the I/O Mux is enabled the pins

are configured as their default values listed Table 6 within section3.12.

Note: It is recommended not to reassign the debug interface signal (debug_if) from its default

setting of IOBUS0 (Pin 11 on all packages). This assumes that the debug pin is required in the

application design, if not; pin 11 can be assigned to any other group 0 signal.

An application (IOMUX) within the RTOS is available to aid with pin configuration, Section 5.2 has more

details.

Further details of the IO Multiplexer are available within Application Note AN_139 Vinculum-II IO Mux

Explained.

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Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Peripheral Pin

IOBUS Pin

uart_txd

uart_rxd

IOBUS0

IOBUS1

IOBUS2

IOBUS3

IOBUS4

IOBUS5

IOBUS6

IOBUS7

IOBUS8

IOBUS9

IOBUS10

IOBUS11

IOBUS12

IOBUS13

IOBUS14

IOBUS15

IOBUS16

IOBUS17

IOBUS18

IOBUS19

IOBUS20

IOBUS21

uart_rts#

uart_cts#

uart_dtr#

uart_dsr#

uart_dcd#

uart_ri#

uart_tx_active

Key:

Group 0 allocated pin

Group 1 allocated pin

Group 2 allocated pin

Group 3 allocated pin

IOBUS43

Figure 5.1 IOBUS to Group Relationship-64 Pin

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Figure 5.2 details the UART, SPI slave0 and SPI master connecting to IOBUS pins:

Peripheral Pin

IOBUS Pin

uart_txd

uart_rxd

IOBUS0

IOBUS1

uart_rts#

uart_cts#

uart_dtr#

uart_dsr#

uart_dcd#

uart_ri#

IOBUS2

IOBUS3

IOBUS4

IOBUS5

IOBUS6

IOBUS7

uart_tx_active

IOBUS8

IOBUS9

spi_s0_clk

spi_s0_mosi

spi_s0_miso

spi_s0_ss#

IOBUS10

IOBUS11

IOBUS12

IOBUS13

IOBUS14

IOBUS15

IOBUS16

IOBUS17

IOBUS18

IOBUS19

IOBUS20

IOBUS21

IOBUS22

IOBUS23

IOBUS24

IOBUS25

IOBUS26

IOBUS27

IOBUS28

IOBUS29

IOBUS30

IOBUS31

spi_s1_clk

spi_s1_mosi

spi_s1_miso

spi_s1_ss#

spi_m_clk

spi_m_mosi

spi_m_miso

spi_m_ss_0#

spi_m_ss_1#

gpio[A0]

gpio[A1]

gpio[A2]

gpio[A3]

gpio[A4]

gpio[A5]

gpio[A6]

gpio[A7]

IOBUS43

gpio[E7]

Figure 5.2 IOBUS to UART, SPI slave0 and SPI master example

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Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Figure 5.3 expands upon Figure 5.2 by moving the UART, SPI slave0 and SPI master signals to different

IOBUS positions. The purpose of this diagram to highlight peripherals connected to differing IOBUS

positions.

Peripheral Pin

IOBUS Pin

uart_txd

uart_rxd

IOBUS0

IOBUS1

uart_rts#

uart_cts#

uart_dtr#

uart_dsr#

uart_dcd#

uart_ri#

IOBUS2

IOBUS3

IOBUS4

IOBUS5

IOBUS6

IOBUS7

uart_tx_active

IOBUS8

IOBUS9

spi_s0_clk

spi_s0_mosi

spi_s0_miso

spi_s0_ss#

IOBUS10

IOBUS11

IOBUS12

IOBUS13

IOBUS14

IOBUS15

IOBUS16

IOBUS17

IOBUS18

IOBUS19

IOBUS20

IOBUS21

IOBUS22

IOBUS23

IOBUS24

IOBUS25

IOBUS26

IOBUS27

IOBUS28

IOBUS29

IOBUS30

IOBUS31

spi_s1_clk

spi_s1_mosi

spi_s1_miso

spi_s1_ss#

spi_m_clk

spi_m_mosi

spi_m_miso

spi_m_ss_0#

spi_m_ss_1#

gpio[A0]

gpio[A1]

gpio[A2]

gpio[A3]

gpio[A4]

gpio[A5]

gpio[A6]

gpio[A7]

IOBUS43

gpio[E7]

Figure 5.3 IOBUS to UART, SPI slave0 and SPI master second example

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Document No.: FT_000138 Clearance No.: FTDI#143

With reference to Figure 5.3, it can be seen that IOBUS9-11 and IOBUS16-19 were unused. Figure 5.4

expands upon the previous two figures to detail a fully occupied IOBUS, up to and including IOBUS19.

The gaps at IOBUS9-11 have been filed with 3 GPIO pins, the gaps at IOBUS16-19 have been filled with

the second SPI slave and a further 3 IOBUS pins (17-19) have been allocated to 3 GPIO pins. Note that

GPIO pins A0 and A4 are unusedas a sufficient gap wasn't available.

Peripheral Pin

IOBUS Pin

uart_txd

uart_rxd

IOBUS0

IOBUS1

uart_rts#

uart_cts#

uart_dtr#

uart_dsr#

uart_dcd#

uart_ri#

IOBUS2

IOBUS3

IOBUS4

IOBUS5

IOBUS6

IOBUS7

uart_tx_active

IOBUS8

IOBUS9

spi_s0_clk

spi_s0_mosi

spi_s0_miso

spi_s0_ss#

IOBUS10

IOBUS11

IOBUS12

IOBUS13

IOBUS14

IOBUS15

IOBUS16

IOBUS17

IOBUS18

IOBUS19

IOBUS20

IOBUS21

IOBUS22

IOBUS23

IOBUS24

IOBUS25

IOBUS26

IOBUS27

IOBUS28

IOBUS29

IOBUS30

IOBUS31

spi_s1_clk

spi_s1_mosi

spi_s1_miso

spi_s1_ss#

spi_m_clk

spi_m_mosi

spi_m_miso

spi_m_ss_0#

spi_m_ss_1#

gpio[A0]

gpio[A1]

gpio[A2]

gpio[A3]

gpio[A4]

gpio[A5]

gpio[A6]

gpio[A7]

IOBUS43

gpio[E7]

Figure 5.4 IOBUS to UART, SPI slave0 and SPI master third example

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Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

5.1 I/O Peripherals Signal Names

Peripheral

Signal Name

Outputs Inputs Description

Debugger

debug_if

uart_txd

1

0

8

1

0

1

8

debugger interface

Transmit asynchronous data output

Request to send control output

Data acknowledge (data terminal ready control) output

Enable transmit data for RS485designs

Receive asynchronous data input

Clear to sendcontrol input

uart_rts#

uart_dtr#

uart_tx_active

uart_rxd

UART

uart_cts#

uart_dsr#

uart_ri#

Data request (data set ready control) input

Ring indicator control input

uart_dcd#

fifo_data

Data carrier detect control input

FIFO data bus

When high, do not write data into the FIFO. Whenlow,

data can be written into the FIFO by strobing WR high,

then low.

fifo_txe#

1

0

When high, do not read data fromthe FIFO. Whenlow,

there is data available in the FIFO which canbe read by

strobing RD# low, thenhigh.

Writes the data byte on the D0...D7pins into the

transmit FIFO bufferwhen WR goesfromhigh to low.

Enables the current FIFO data byte on D0...D7 whenlow.

Fetches the next FIFO data byte (if available) fromthe

receive FIFO buffer whenRD#goesfromhigh to low

fifo_rxf#

fifo_wr#

fifo_rd#

1

0

1

FIFO

fifo_oe#

fifo_clkout

gpio

0

40

0

1

0

1

0

1

8

1

40

1

0

1

0

1

0

FIFO output enable – synchronous FIFO only

FIFO clock out – synchronous FIFO only

General purpose I/O

GPIO

spi_s0_clk

spi_s0_ss#

spi_s0_mosi

spi_s0_miso

spi_s1_clk

spi_s1_ss#

spi_s1_mosi

spi_s1_miso

spi_m_clk

spi_m_mosi

spi_m_miso

spi_m_ss_0#

spi_m_ss_1#

pwm

SPI clock input – slave 0

SPI chip select input – slave 0

SPI masterout serial in – slave 0

SPI master in slave out – slave 0

SPI clock input – slave 1

SPI Slave 0

SPI chip select input – slave 1

Master out slave in – slave 1

SPI Slave 1

Master in slave out – slave 1

SPI clock input – master

Master out slave in - master

SPI Master

PWM

Master in slave out - master

Active low slave select 0 from masterto slave 0

Active low slave select 1 from masterto slave 1

Pulse width modulation

Table 5.1 I/O Peripherals Signal Names

Note: # is used to indicate an active low signal.

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Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

5.2 I/O Multiplexer Configuration

The VNC2 I/O Multiplexer allows signals to be routed to different pins on the device. To simplify the

routing of signals, the VNC2 RTOS provides an utility (IOMux) to configure the I/O Multiplexer as the

designer requires.

The IOMux is fully integrated into the VNC2 IDE (Integrated development

Environment) which is available to download: Vinculum-II Toolchain. A screenshot of the IOMux utility is

shown in figure 5.5 below.

The IOMux utility user guide is available to download: VINCULUM-II IO_Mux Configuration Utility User

Guide

The following tables provide a lookup guide to determine what signals are available and the list of pins

that can be used:



Table 5.2 Group 0

Table 5.3 Group 1

Table 5.4 Group 2

Table 5.5 Group 3

Each VNC2 has a default state of IOBUS signals following a hard reset. The number of I/O pins available

is determined by the package size:



Package 32pin (LQFP & QFN)- Twelve I/O pins – IOBUS0 to IOBUS11

Package 48pin (LQFP & QFN)- Twenty eight I/O pins – IOBUS0 to IOBUS27

Package 64pin (LQFP & QFN)- Forty-four I/O pins – IOBUS0 to IOBUS43

Section 3.12 shows the default signal settings for all three package sizes.

Figure 5.5 VNC2 Toolchain App Wizard showing IOMux Configuration

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Document No.: FT_000138 Clearance No.: FTDI#143

5.3 I/O Mux Group 0

64 Pin

Package

48 Pin

Package

32 Pin

Package

Available output

signals

Available Input signals

Available

pins

Available

pins

Available

pins

debug_if

uart_txd

uart_dtr#

uart_tx_active

fifo_data[0]

fifo_data[4]

fifo_rxf#

pwm[0]

debug_if

fifo_data[0]

fifo_data[4]

fifo_oe#

spi_s0_clk

spi_s1_clk

gpio[A0]

gpio[A4]

gpio[B0]

gpio[B4]

gpio[C0]

gpio[C4]

gpio[D0]

gpio[D4]

gpio[E0]

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

pwm[4]

11, 15,

20, 31,

35, 41,

45

spi_m_clk

spi_m_ss_1#

gpio[A0]

11, 23

29

gpio[A4]

gpio[B0]

gpio[B4]

gpio[C0]

gpio[C4]

gpio[D0]

gpio[D4]

gpio[E0]

gpio[E4]

Table 5.2 Group 0

Table 5.2 - Input and output signals that are available for all the IOBUS pins that are in group 0. For

example if using the 48 pin package device this would allow pins 11, 15, 20, 31, 35, 41 and 45 to be

configured as either an input signal (listed in the first column) or a output signal (listed in the second

column).

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Document No.: FT_000138 Clearance No.: FTDI#143

5.4 I/O Mux Group 1

64 Pin

Package

48 Pin

Package

32 Pin

Package

Available output

signals

Available Input signals

Available

pins

Available

pins

Available

pins

fifo_data[1]

fifo_data[5]

fifo_txe#

pwm[1]

uart_rxd

uart_dsr#

fifo_data[1]

fifo_data[5]

spi_s0_mosi

spi_s1_mosi

gpio[A1]

pwm[5]

spi_s0_mosi

spi_s1_mosi

spi_m_mosi

fifo_clkout

gpio[A1]

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

62

12,16,

21, 32,

36, 42,

46

gpio[A5]

12, 24,

30

gpio[B1]

gpio[A5]

gpio[B5]

gpio[B1]

gpio[C1]

gpio[B5]

gpio[C5]

gpio[C1]

gpio[C5]

gpio[D1]

gpio[D5]

gpio[E1]

gpio[D1]

gpio[D5]

gpio[E1]

gpio[E5]

Table 5.3 Group 1

Table 5.3 - Input and output signals that are available for all the IOBUS pins that are in group 1. For

example if using the 64 pin package device this would allow pins 12, 16, 20, 25, 29, 40, 44, 48, 52, 58

and 62 to be configured as either an input signal (listed in the first column) or a output signal (listed in

the second column).

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

5.5 I/O Mux Group 2

64 Pin

Package

48 Pin

Package

32 Pin

Package

Available output

signals

Available Input signals

Available

pins

Available

pins

Available

pins

uart_rts#

fifo_data[2]

fifo_data[6]

pwm[2]

uart_dcd#

fifo_data[2]

fifo_data[6]

fifo_rd#

pwm[6]

spi_m_miso

gpio[A2]

gpio[A6]

gpio[B2]

gpio[B6]

gpio[C2]

gpio[C6]

gpio[D2]

gpio[D6]

gpio[E2]

spi_s0_miso

spi_s1_miso

gpio[A2]

gpio[A6]

gpio[B2]

gpio[B6]

gpio[C2]

gpio[C6]

gpio[D2]

gpio[D6]

gpio[E2]

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

63

13, 18,

22, 33,

37, 43,

47

14, 25,

31

gpio[E6]

Table 5.4 Group 2

Table 5.4 - Input and output signals that are available for all the IOBUS pins that are in group 2. For

example if using the 32 pin package device this would allow pins 14, 25 and 31 to be configured as

either an input signal (listed in the first column) or a output signal (listed in the secondcolumn).

33

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

5.6 I/O Mux Group 3

Available Input signals

Available output

signals

64 Pin

Package

48 Pin

Package

32 Pin

Package

Available

pins

Available

pins

Available

pins

uart_cts#

uart_ri#

fifo_data[3]

fifo_data[7]

pwm[3]

fifo_data[3]

fifo_data[7]

fifo_wr#

pwm[7]

spi_s0_ss#

spi_s1_ss#

gpio[A3]

gpio[A7]

gpio[B3]

gpio[B7]

gpio[C3]

gpio[C7]

gpio[D3]

gpio[D7]

gpio[E3]

spi_m_ss_0#

gpio[A3]

gpio[A7]

gpio[B3]

gpio[B7]

gpio[C3]

gpio[C7]

gpio[D3]

gpio[D7]

gpio[E3]

14, 18,

23, 27,

32, 42,

46, 50,

56, 60,

64

14, 19,

23, 34,

38, 44,

48

15, 26,

32

gpio[E7]

Table 5.5 Group 3

Table 5.5 - Input and output signals that are available for all the IOBUS pins that are in group 3. For

example if you using the 48 pin package device this would allow pins 14, 19, 23, 34, 38, 44 and 48 to be

configured as either an input signal (listed in the first column) or a output signal (listed in the second

column).

34

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

5.7 I/O Mux Interface Configuration Example

This example shows how to set a UART interface on the VNC2 64 pin package. The UART is made up of

two output signals (uart_txd and uart_rts#) and two input signals (uart_rxd and uart_cts#). For PCB

design it is best to have the four pins of the UART interface adjacent to each other. This can be achieved

easily since the four signals are members of each different groups. Figure 5.1 clearly shows that the four

groups are adjacent to each other. So the four adjacent pins can be used for the UART interface as long

as they are selected one from each of the four groups. Tables 9, 10, 11 & 12 can now be used to select

where the UART interface can be placed. Figure 5.6 shows the four UART signal selected on pins 11, 12,

13 & 14 however they could have been selected on any of the other four pins highlighted in blue dashed

lines.

54 38 21

2

3

11

12

13

V

C

I

V

C

I

V

C

I

V

C

uart_txd – group0

uart_rxd – group1

uart_rts# – group2

uart_cts# – group3

IOBUS0

IOBUS1

IOBUS2

IOBUS3

IOBUS4

C

P

L

O

14

15

16

17

18

L

33

USB1DP

34

36

37

IOBUS5

IOBUS6

IOBUS7

USB1DM

USB2DP

USB2DM

19

20

22

IOBUS8

IOBUS9

IOBUS10

IOBUS11

IOBUS12

4

5

23

24

25

26

27

XTIN

XTOUT

IOBUS13

IOBUS14

IOBUS15

9

28

29

31

RESET#

PROG#

IOBUS16

IOBUS17

IOBUS18

IOBUS19

IOBUS20

10

VNC2

64 Pin

32

39

40

41

42

7

8

VREG OUT

NC

IOBUS21

IOBUS22

IOBUS23

43

44

45

IOBUS24

IOBUS25

IOBUS26

IOBUS27

IOBUS28

46

47

48

49

50

64

IOBUS43

63

62

61

IOBUS42

IOBUS41

IOBUS40

IOBUS29

IOBUS30

IOBUS31

60

59

58

57

IOBUS39

IOBUS38

IOBUS37

IOBUS36

51

52

IOBUS32

IOBUS33

IOBUS34

IOBUS35

55

56

G

N

D

G

N

D

G

N

D

G

N

D

G

N

D

P

L

1

6

30 35 53

Figure 5.6 UART Example 64 pin

35

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

6 Peripheral Interfaces

In addition to the two USB Host and Slave blocks, VNC2 contains the following peripheral interfaces:



Universal Asynchronous Receiver Transmitter (UART)

Two Serial Peripheral Interface (SPI) slaves

SPI Master

Debugger Interface

Parallel FIFO Interface (245 mode and synchronous FIFO mode)

General Purpose Timers

Eight Pulse Width Modulation blocks (PWM)

General Purpose Input Output (GPIO)

The following sections describe each peripheral in detail.

6.1 UART Interface

When the data and control bus are configured in UART mode, the interface implements a standard

asynchronous serial UART port with flow control, for example RS232/422/485. The UART can support

baud rates from 183 baud to 6 Mbaud. The maximum UART speed is determined by the CPU speed/8.The

CPU can be run at three frequencies, therefore the following maximumrates apply:

CPU Frequency

48 MHz

Maximum UART Speed

6 Mbaud

24 MHz

3 Mbaud

12 MHz

1.5 Mbaud

Data transfer uses NRZ (Non-Return to Zero) data format consisting of 1 start bit, 7 or 8 data bits, an

optional parity bit, and one or two stop bits. When transmitting the data bits, the least significant bit is

transmitted first. Transmit and receive waveforms are illustrated in Figure 6.1 and Figure 6.2:

Figure 6.1 UART Receive Waveform

Figure 6.2 UART Transmit Waveform

Baud rate (default =9600 baud), flow control settings (default = RTS/CTS), number of data bits

(default=8), parity (default is no parity) and number of stop bits (default=1) are all configurable using

the firmware command interface. Please refer to http://www.ftdichip.com.

uart_tx_active is transmit enable, this output may be used in RS485 designs to control the transmit of

the line driver.

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

6.1.1 UART Mode Signal Descriptions

64 Pin

Package

48 Pin

Package

32 Pin

Package

Name

Type

Description

Available Available Available

pins

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

11, 15,

20, 31,

35, 41,

45

11, 23

29

uart_txd

Output

Transmit asynchronous data output

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

62

12,16,

21, 32,

36, 42,

46

12, 24,

30

uart_rxd

uart_rts#

uart_cts#

uart_dtr#

uart_dcd#

Input

Output

Input

Receive asynchronous data input

Request to send control output

Clear to sendcontrol input

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

63

13, 18,

22, 33,

37, 43,

47

14, 25,

31

14, 18,

23, 27,

32, 42,

46, 50,

56, 60,

64

14, 19,

23, 34,

38, 44,

48

15, 26,

32

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

11, 15,

20, 31,

35, 41,

45

11, 23

29

Data acknowledge (data terminal ready

control) output

Output

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

63

13, 18,

22, 33,

37, 43,

47

14, 25,

31

Input

Data carrier detect control input

37

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

64 Pin

Package

48 Pin

Package

32 Pin

Package

Name

Type

Description

Available Available Available

pins

14, 18,

23, 27,

32, 42,

46, 50,

56, 60,

64

14, 19,

23, 34,

38, 44,

48

15, 26,

32

Ring indicator is usedto wake VNC2

depending on firmware

uart_ri#

Input

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

Enable transmit data for RS485designs.

This signal may be usedto signal that a

transmit operation is in progress. The

uart_tx_active signal will be set high one

bit-time before data is transmitted and

return low one bit time after the last bit

of a data frame hasbeentransmitted.

11, 15,

20, 31,

35, 41,

45

11, 23

29

uart_tx_active

Output

Table 6.1 Data and Control Bus Signal Mode Options – UART Interface

The UART signals can be programmed to a choice of I/O pins depending on the package size. Table 6.1

details the available pins for each of the UART signals. Further details on the configuration of input and

output signals are available in Section 5 - I/O Multiplexer.

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

6.2 Serial Peripheral Interface – SPI Modes

The Serial Peripheral Interface Bus is an industry standard communications interface. Devices

communicate in Master / Slave mode, with the Master initiating the data transfer.

VNC2 has one master module and two slave modules. Each SPI slave module has four signals – clock,

slave select, MOSI (master out – slave in) and MISO (master in – slave out). The SPI Master has the

same four signals as the slave modules but with one additional signal because it requires a slave select

for the second slave module. Table 6.2 lists how the signals are named in each module.

The SPI Master clock can operate up to one half of the CPU system clock depending on what power mode

the device is set to:



Normal power mode 48Mhz would set the SPI maximum clock to 24Mhz

Low power mode 24Mhz would setthe SPI maximum clock to 12Mhz

Lowest power mode 12Mhz would set the SPI maximum clock to 6hMz

Module

Signal Name

Type

Description

spi_s0_clk

spi_s0_ss#

spi_s0_mosi

spi_s0_miso

spi_s1_clk

Input

Clock input – slave 0

Active low chip select input – slave 0

Master out serial in – slave 0

Master in slave out – slave 0

Clock input – slave 1

SPI Slave

0

Input

Output

Input

spi_s1_ss#

spi_s1_mosi

spi_s1_miso

spi_m_clk

Input

Active low chip select input – slave 1

Master out slave in – slave 1

Master in slave out – slave 1

Clock output – master

SPI Slave

1

Input

Output

Input

spi_m_mosi

spi_m_miso

spi_m_ss_0#

spi_m_ss_1#

Master out slave in - master

SPI Master

Master in slave out - master

Output

Active low slave select 0 from masterto slave 0

Active low slave select 1 from masterto slave 1

Table 6.2 SPI Signal Names

The SPI slave protocol by default does not support any form of handshaking. FTDI have added extra

modes to support handshaking, faster throughput of data and reduced pin count. There are 5 modes

(Table 15) of operation in the VNC2 SPI Slave.



Full Duplex – Section 0

Half Duplex, 4 pin - Section 6.3.3

Half Duplex, 3 pin - Section 6.3.4

Unmanaged - Section 6.3.5

VNC1L legacy mode – Section 6.3.6

39

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Mode

Pins

Word Size

Handshaking

Speed

Comments

Read 66%

Write 66%

Read 50%

Write 100%

Read 100%

Write 100%

Read 50%

Write 50%

Read 100%

Write 100%

VNC1L

4

3

4

12

8

Yes

No

Legacy mode

Full Duplex

MOSI becomes

bi-directional

MOSI becomes

bi-directional

Half Duplex 4 pin

Half Duplex 3 pin

Unmanaged

8

Table 6.3 - SPI Slave Speeds

VNC2 SPI Master is described in Section 6.4.1 SPI Master Signal Descriptions.

Table 6.5 shows the SPI master signals and the available pins that they can be mapped to depending on

the package size. Further details on the configuration of input and output signals are available in Section

5 - I/O Multiplexer.

6.2.1 SPI Clock Phase Modes

SPI interface has 4 unique modes of clock phase (CPHA) and clock polarity (CPOL), known

as Mode 0, Mode 1, Mode 2 and Mode 3. Table 6.4 summarizes these modes and available interface and

Figure 6.3 is the function timing diagram.

For CPOL = 0, the base (inactive) level of SCLK is 0.

In this mode:



When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on the

falling edge of SCLK.



When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on the

rising edge of SCLK

For CPOL =1, the base (inactive) level of SCLK is 1.

In this mode:



When CPHA = 0, data v in on the falling edge of SCLK, and data is clocked out on the rising edge

of SCLK



When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on the

falling edge of SCLK.

Half

Duplex

4 pin

Half

Duplex

3 pin

Full

Duplex

VNC1L

Legacy

Mode

CPOL

CPHA

Unmanaged

0

1

2

3

0

1

0

1

0

1

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

Table 6.4 - Clock Phase/Polarity Modes

40

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Figure 6.3 - SPI CPOL CPHA Function

6.3 Serial Peripheral Interface – Slave

CLK

SS#

VNC2 - SPI Slave

External - SPI Master

MOSI

MISO

Figure 6.4 SPI Slave block diagram

VNC2 has two SPI Slave modules both of which use four wire interfaces: MOSI, MISO, CLK and SS#.

Their main purpose is to send data from main memory to the attached SPI master, and / or receive data

and send it to main memory. The SPI Slave is controlled by the internal CPU using internal memory

mapped I/O registers. It operates from the main system clock, although sampling of input data and

transmission of output data is controlled by the SPI clock (CLK). An SPI transfer can only be initiated by

the SPI Master and begins with the slave select signal being asserted. This is followed by a data byte

being clocked out with the master supplying CLK. The master always supplies the first byte, which is

called a command byte. After this the desired number of data bytes are transferred before the

transaction is terminated by the master de-asserting slave select. An SPI Master is able to abort a

transfer at any time by de-asserting its SS# output. This will cause the Slave to end its current transfer

and return to idle state.

41

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

6.3.1 SPI Slave Signal Descriptions

64 Pin

Package

48 Pin

Package

32 Pin

Package

Name

Type

Description

Available Available Available

pins

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

spi_s0_clk

spi_s1_clk

11, 15,

20, 31,

35, 41,

45

11, 23

29

Input

Slave clock input

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

62

12,16,

21, 32,

36, 42,

46

spi_s0_mosi

spi_s1_mosi

Mater Out Slave In

12, 24,

30

Input

Synchronousdata from master to slave

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

63

13, 18,

22, 33,

37, 43,

47

spi_s0_miso

spi_s1_miso

14, 25,

31

Master In Slave Out

Output

Synchronousdata from slave to master

14, 18,

23, 27,

32, 42,

46, 50,

56, 60,

64

14, 19,

23, 34,

38, 44,

48

spi_s0_ss#

spi_s1_ss#

15, 26,

32

Input

Slave chip select

Table 6.5 Data and Control Bus Signal Mode Options - SPI Slave Interface

42

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

6.3.2 Full Duplex

In full duplex mode, the SPI slave sends data on MISO line at the same time as it receives data on MOSI.

During the command phase this data is always the slave status byte. For a write command, write data

can be streamed out of MOSI and status can be sent during each write phase from slave to master. As

long as the slave status indicates that it can receive more data, the master can continue to stream

further write bytes. Figure 6.5 is an example of this.

SS#

MOSI

MISO

8 bit CMD

STATUS

W0

W1

W2

STATUS

Figure 6.5 Full Duplex Data Master Write

When the master is performing a data read, the data and status both need to share the same pin (MISO).

In this case the master and slave will exchange command and status bytes, followed by the slave sending

its data. If the Master keeps SS# active the Slave will send a further status byte after the data followed

by another data byte. This continues until the Master indicates the end of the communications by raising

SS#. Figure 6.6 is an example of this.

SS#

MOSI

MISO

8 bit CMD

STATUS

R0

STATUS

R1

Figure 6.6 Full Duplex Data Master Read

43

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

The command and status formats for this mode can be seen in Figure 6.7 below with a description of

each field in Table 6.6:

Command:

Status:

A2

Z

A1

Z

A0

Z

R/W#

Z

TXE

RXF

ACK

Figure 6.7 SPI Command and Status Structure

Field

Description

Address of slave being used in a multi-slave environment. This would typically be used in the

scenario where a shareddata busis used.

A2:A0

R/W#

Z

Set to ‘1’ for a read and ‘0’ for a write.

Tri-stated.

Transmit Empty.

TXE

When ‘1’ the Slave transmit bufferhas no new data to transmit.

When ‘0’ the Slave transmit bufferdoes have new data.

Receive Full.

RXF

When ‘1’ the Slave receive buffer has new data which has not been read yet.

When ‘0’ the Slave receive buffer is empty and canbe safely written to.

ACK

Set to ‘1’ when a Slave has correctly decodedits address.

Table 6.6 SPI Command and Status Fields

44

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

6.3.3 Half Duplex, 4 pin

In half duplex mode, the MOSI signal is shared for both Master to Slave and Slave to Master

communications. When using 4 pins, the MISO signal carries the status bits. The Master initiates data

write transfer, this by asserting SS# and then sending out a command byte. This has the same format as

that shown in Figure 6.7. The Slave sends status during this command phase and if this indicates that

the Slave can accept data the Master will follow this up with a byte of write data. If the status continues

to indicate that more data can be written, a whole stream of data can be written following one single

command. The operation completes whenthe Master raises SS# again. Figure 6.8 is an example of this.

SS#

MOSI

MISO

8 bit CMD

STATUS

W0

W1

W2

STATUS

Figure 6.8 Half Duplex Data Master Write

Data reads are similar, apart from the MOSI pin changing from Slave input to Slave output after the

command phase. Figure 6.9 is an example. In this diagram, the Master drives the command while the

Slave returns with status. Then the MOSI buffers are turned round and a stream of read data is sent from

the Slave to the Master on the MOSI signal.

Master to Slave

Slave to Master

SS#

MOSI

MISO

8 bit CMD

STATUS

R0

R1

R2

STATUS

Figure 6.9 Half Duplex Data Master Read

45

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

6.3.4 Half Duplex, 3 pin

The 3 pin half duplex mode eliminates the MISO pin from the protocol. This means that status bytes need

to be sent on the MOSI pin. Again the Master initiates a transfer by asserting SS# and sending out a

command byte. The Slave sends status back to the Master. If a write has been requested and the status

indicates that the Slave can accept data, MOSI should be changed to an output again and data will be

sent fromMaster to Slave.

Following this data, the Slave will send a further status byte if SS# remains active. If the status indicates

that more data can be written, the next data byte can be sent to the Slave and this process continues

until SS# is de-asserted. Figure 6.10 is an example of this:

Master to Slave Slave to Master Master to Slave Slave to Master

Master to Slave

SS#

MOSI

8 bit CMD

STATUS

W0

STATUS

W1

Figure 6.10 Half Duplex 3-pin Data Master Write

Data reads are similar expect that after the command byte all data transfer is from Slave to Master.

Figure 6.11 is an example of this:

Master to Slave

Slave to Master

SS#

MOSI

8 bit CMD

STATUS

R0

STATUS

R1

Figure 6.11 Half Duplex 3-pin Data Master Read

46

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

6.3.5 Unmanaged Mode

The VNC2 SPI Slave also supports an unmanaged SPI mode. This is a simple data exchange between

Master and Slave. It operates in the standard 4 pin mode (SS#, CLK, MOSI and MISO) with all transfers

controlled by the SPI Master.

When the CPU wants to send data out of the SPI Slave it writes this into the spi_slave_data_tx register.

This will then be moved into the transfer shift register to wait for the SPI Master to request it. The SPI

Master will at some point assert SS# and start clocking data on MOSI with SCK. As this is shifted into the

transfer shift register, the SPI Slave will also be shifting data in the opposite direction on MISO. At the

end of the transfer the SPI Slave copies the received data from the shift register to spi_slave_data_rx as

seen in Figure 6.12.

SPI Master

SPI Slave

SPI

ss#

Clk Div

clk

mosi

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Shift Register

Rx Shift Register

2

3

4

5

3

4

Tx Shift Register

Shift Register

miso

Figure 6.12 Unmanaged Mode Transfer Diagram

47

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

6.3.6 VNC1L Legacy Interface

VNC2 SPI is compatible with the SPI slave of VNC1L. This is a custom protocol using 4 wires and will be

explained here.

The Master asserts the slave select, but in this case it is an active high signal. Following this, a 3 bit

command is sent on the MOSI pin (see Figure 6.15 for command structure). This has instructions on

whether a read or write is requested and if data or status is to be sent. For a data write, 8 bits of data

are sent on MOSI followed by a status bit being returned on MISO. If this bit is ‘0’ it means the data write

was successful. If it is ‘1’ it means that internal buffer was full and the write should be repeated. Finally,

the slave select is de-asserted. See Figure 6.13 for an example of this.

Figure 6.13 VNC1L Mode Data Write

Data reads are similar, with the data from Slave to Master coming on the MISO pin. If the status bit is ‘0’

it means the data byte sent is new data that has not been read before. If it is ‘1’ it means that it is old

data. See Figure 6.14 for an example.

Figure 6.14 VNC1L Mode Data Read

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

The command and status formats for this mode can be seen in Figure 6.15 below with a description of

each field in Table 6.7.

Command:

Data:

Start

D7

R/W

D6

Addr

D5

D4

D3

D2

D1

D0

Status:

Status

Figure 6.15 VNC1L Compatible SPI Command and Status Structure

Field

Description

Start

Driven to ‘1’.

If set to ‘1’, the SPI Master wishes to read from the slave. If set to ‘0’, the SPI Master wishes to

write to the slave.

R/W

If set to ‘1’, a read operation will return the status byte in the data phase. A write will have no

effect.

Addr

If set to ‘0’, a read or a write will operate on the data register.

D7:D0

Status

Data.

When ‘0’ this means a read or write was successful. When ‘1’ it means a read contains old data,

or a write did not work and needs retried.

Table 6.7 SPI Command and Status Fields

6.3.6.1 SPI Setup Bit Encoding

The VNC1L compatible SPI interface differs from most other implementations in that it uses a 12 clock

sequence to transfer a single byte of data. In addition to a ‘Start’ state, the SPI master must send two

setup bits which indicate data direction and target address. The encoding of the setup bits is shown in

Table 6.8. A single data byte is transmitted in each SPI transaction, with the most significant bit

transmitted first.

After each transaction VNC2 returns a single status bit. This indicates if a Data Write was successful or a

Data Read was valid.

Direction

(R/W)

Target

Address

Operation

Meaning

1

0

1

0

1

Data Read

Status Read

Data Write

N/A

Retrieve byte from Transmit Buffer

Read SPI Interface Status

Add byte to Receive Buffer

N/A

Table 6.8 SPI Setup Bit Encoding

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The VNC2 SPI interface uses 4 signal lines: SCLK, SS, MOSI and MISO. The signals MOSI, MISO and SS

are always clocked on the rising edge of the SCLK signal.

SS signal must be raised high for the duration of the entire transaction. For data transactions, the SS

must be released for at least one clock cycle after a transaction has completed. It is not necessary to

release SS between Status Read operations.

The ‘Start’ state of MOSI and SS high on the rising edge of SCLK initiates the transfer. The transfer

finishes after 13 clock cycles, and the next transfer starts when MOSI is high during the rising edge of

CLK.

The following Figure 6.16 and

Table 6.9 give details of the bus timing requirements.

Figure 6.16 SPI Slave Mode Timing

Time

T1

Description

SCLK period

Minimum

79.37

Typical

83.33

Maximum

Unit

ns

T2

SCLK high period

SCLK low period

39.68

41.67

39.68

ns

T3

39.68

41.67

ns

SCLK driving edge to

MISO/MOSI

T4

T5

T6

0.5

14

3

ns

MISO/SS setup time to sample

SCLK edge

MISO/SS holdtime from sample

SCLK edge

3

Table 6.9 SPI Slave Data Timing

6.3.6.2 SPI Master Data Read Transaction in VNC1L legacy mode

The SPI master must periodically poll for new data in VNC2 Transmit Buffer. It is recommended that this

is done first before sending any command.

The Start and Setup sequence is sent to VNC2 by the SPI master, see Figure 6.17.

The VNC2 clocks out data from its Transmit Buffer on subsequent rising edge clock cycles provided by the

SPI master. This is followed by a status bit generated by VNC2. The Data Read status bit is defined in

Table 6.10.

If the status bit indicates New Data then the byte received is valid. If it indicates Old Data then the

Transmit Buffer in VNC2 is empty and the byte of data received in the current transaction should be

disregarded.

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Status Bit

Meaning

Data in current transaction is valid data.

Byte removed fromTransmit Buffer.

0

New Data

Old Data

This same data hasbeen read in a previous readcycle.

Repeat the readcycle until New Data is received.

1

Table 6.10 SPI Master Data Read Status Bit

Figure 6.17 SPI Master Data Read (VNC2 Slave Mode)

The status bit is only valid until the next rising edge of SCLK after the last data bit.

During the Data Read operation the SS signal must not be de-asserted.

The transfer completes after 12 clock cycles and the next transfer can begin when MOSI and SS are high

during the rising edge of SCLK.

6.3.6.3 SPI Master Data Write Transaction in VNC1L legacy mode

During an SPI master Data Write operation the Start and Setup sequence is sent by the SPI master to

VNC2, see Figure 6.18. This is followed by the SPI master transmitting each bit of the data to be written

to VNC2. The VNC2 then responds with a status bit on MISO on the rising edge of the next clock cycle.

The SPI master must read the status bit at the end of each write transaction to determine if the data was

written successfully to VNC2 Receive Buffer. The Data Write status bit is defined in Table 6.11.The

status bit is only valid until the next rising edge of SCLK after the last data bit.

If the status bit indicates Accept then the byte transmitted has been added to VNC2 Receive Buffer. If it

shows Reject then the Receive Buffer is full and the byte of data transmitted in the current transaction

should be re-transmitted by the SPI master to VNC2.

Any application should poll VNC2 Receive Buffer by retrying the Data Write operation until the data is

accepted.

Status Bit

Meaning

0

1

Accept

Reject

Data from the current transactionwas acceptedand addedto the Receive Buffer

Write data was not accepted. Retry the same write cycle.

Table 6.11 SPI Master Data Write Status Bit

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Figure 6.18 SPI Slave Mode Data Write

6.3.6.4 SPI Master Status Read Transaction in VNC1L legacy mode

The VNC2 has a status byte which determines the state of the Receive and Transmit Buffers. The SPI

master must poll VNC2 and read the status byte.

The Start and Setup sequence is sent to VNC2 by the SPI master, see Figure 6.19. The VNC2 clocks out

its status byte on subsequent rising edge clock cycles from the SPI master. This is followed by a status

bit generated by VNC2 (also on the MISO) which will always be zero (indicating new data).

The meaning of the bits within the status byte sent by VNC2 during a Status Read operation is described

in Table 6.12. The result of the Status Read transaction is only valid during the transaction itself. Data

read and data write transactions must still check the status bit during a Data Read or Data Write cycle

regardless of the result of a Status Read operation.

Bit

0

Description

Receive Buffer Full

RXF#

1

TXE#

Transmit Buffer Empty

2

-

Not used

3

-

Not used

4

RXF IRQEn

Receive Buffer Full Interrupt Enable

Transmit Buffer Empty Interrupt Enable

Not used

5

TXE IRQEn

6

-

7

Not used

Table 6.12 SPI Status Read Byte – bit descriptions

Figure 6.19 SPI Slave Mode Status Read

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6.4 Serial Peripheral Interface – SPI Master

CLK

SS#

External - SPI Slave

VNC2 - SPI Master

MOSI

MISO

Figure 6.20 SPI Master block diagram

The SPI Master interface is used to interface to applications such as SD Cards. The SPI Master provides

the following features:



Synchronous serial data link.

Full and half duplex data transmission.

Serial clock with programmable frequency, polarity and phase.

One slave select output.

Programmable delay between negative edge of slave select and start of transfer.

SD Card interface.

An interface that’s compatible with the VLSI VS1033 SCI mode used for VMUSIC capability

The SPI Master only clocks in and out data that the VNC2 CPU sets up in its register space. The VNC2

CPU interprets the data words that are to be sentand received.

6.4.1 SPI Master Signal Descriptions.

Table 6.13 shows the SPI master signals and the available pins that they can be mapped to depending

on the package size. Further details on the configuration of input and output signals are available in

Section 5 - I/O Multiplexer.

64 Pin

Package

48 Pin

Package

32 Pin

Package

Name

Type

Description

Available Available Available

pins

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

11, 15,

20, 31,

35, 41,

45

11, 23

29

spi_m_clk

Output

SPI masterclock input

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64 Pin

Package

48 Pin

Package

32 Pin

Package

Name

Type

Description

Available Available Available

pins

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

62

12,16,

21, 32,

36, 42,

46

Master Out Slave In

12, 24,

30

spi_m_mosi

Output

Synchronousdata from master to slave

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

63

13, 18,

22, 33,

37, 43,

47

14, 25,

31

Master In Slave Out

spi_m_miso

Input

Synchronousdata from slave to master

14, 18,

23, 27,

32, 42,

46, 50,

56, 60,

64

14, 19,

23, 34,

38, 44,

48

Active low slave select 0 from masterto

slave 0

15, 26,

32

spi_m_ss_0#

Output

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

11, 15,

20, 31,

35, 41,

45

Active low slave select 1 from masterto

slave 1

11, 23

29

spi_m_ss_1#

Output

Table 6.13 SPI Master Signal Names

The main purpose of the SPI Master block is to transfer data between an external SPI interface and the

VNC2. It does this under the control of the CPU and DMA engine via the on chip I/O bus.

An SPI master interface transfer can only be initiated by the SPI Master and begins with the slave select

signal being asserted. This is followed by a data byte being clocked out with the master supplying SCLK.

The master always supplies the first byte, which is called a command byte. After this the desired number

of data bytes are transferred before the transaction is terminated by the master de-asserting slave

select.

The SPI Master will transmit on MOSI as well as receive on MISO during every data stage. At the end of

each byte spi_tx_done and spi_rx_full_int are set. Figure 6.21 Typical SPI Master Timing and

Table 6.14 SPI Master Timing show an example of this.

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Figure 6.21 Typical SPI Master Timing

Time

t1

Description

SCLK period

Minimum

39.68

Typical

41.67

Maximum

Unit

ns

t2

SCLK high period

19.84

20.84

21.93

3

ns

t3

SCLK low period

19.84

20.84

ns

t4

SCLK driving edge to MOSI/SS

-1.5

ns

MISO setup time to sample

SCLK edge

t5

t6

6.5

ns

MISO hold time from sample

SCLK edge

0

Table 6.14 SPI Master Timing

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6.5 Debugger Interface

The purpose of the debugger interface is to provide the Integrated Development Environment (IDE) with

the following capabilities:



Flash Erase, Write andProgram.

Application debug - application code can have breakpoints, be single stepped and can be halted.

Detailed internal debug - memory read/write access.

The single wire interface has the following features:



Half Duplex Operation

1Mbps speed

1 start bit

1 stop bit

8 data bits

Pull up

Further information of the Debugger Interface is available in an Application Note AN_138 Vinculum-II

Debug Interface Description.

6.5.1 Debugger Interface Signal description

64 Pin

Package

48 Pin

Package

32 Pin

Package

Name

Type

Description

Available

pins

Available Available

pins

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

11, 15,

20, 31,

35, 41,

45

Input/

Output

11, 23

29

debug_if

DebuggerInterface

Table 6.15 Debugger Signal Name

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6.6 Parallel FIFO – Asynchronous Mode

Parallel FIFO Asynchronous mode known as ‘245’, is functionally the same as the one that is present in

VNC1L has an eight bit data bus, individual readand write strobes andtwo hardware flow control signals.

6.6.1 FIFO Signal Descriptions

The Parallel FIFO interface signals are described in Table 6.16 They can be programmed to a choice of

I/O pins depending on the package size. Further details on the configuration of input and output signals

are available in Section 5 - I/O Multiplexer.

64 Pin

Package

48 Pin

Package

32 Pin

Package

Name

Type

Description

Available Available Available

pins

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

11, 15,

20, 31,

35, 41,

45

11, 23

29

fifo_data[0]

I/O

FIFO Data Bus Bit 0

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

62

12,16,

21, 32,

36, 42,

46

12, 24,

30

fifo_data[1]

I/O

FIFO Data Bus Bit 1

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

63

13, 18,

22, 33,

37, 43,

47

14, 25,

31

fifo_data[2]

I/O

FIFO Data Bus Bit 2

14, 18,

23, 27,

32, 42,

46, 50,

56, 60,

64

14, 19,

23, 34,

38, 44,

48

15, 26,

32

fifo_data[3]

I/O

FIFO Data Bus Bit 3

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Document No.: FT_000138 Clearance No.: FTDI#143

64 Pin

Package

48 Pin

Package

32 Pin

Package

Name

Type

Description

Available Available Available

pins

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

11, 15,

20, 31,

35, 41,

45

11, 23

29

fifo_data[4]

I/O

FIFO Data Bus Bit 4

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

62

12,16,

21, 32,

36, 42,

46

12, 24,

30

fifo_data[5]

I/O

FIFO Data Bus Bit 5

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

63

13, 18,

22, 33,

37, 43,

47

14, 25,

31

fifo_data[6]

fifo_data[7]

fifo_rxf#

I/O

FIFO Data Bus Bit 6

14, 18,

23, 27,

32, 42,

46, 50,

56, 60,

64

14, 19,

23, 34,

38, 44,

48

15, 26,

32

I/O

FIFO Data Bus Bit 7

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

When high, do not read data fromthe FIFO.

11, 15,

20, 31,

35, 41,

45

11, 23

29

When low, there is data available in the

FIFO which can be read by strobing fifo_rd#

low, then high.

Output

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64 Pin

Package

48 Pin

Package

32 Pin

Package

Name

Type

Description

Available Available Available

pins

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

62

12,16,

21, 32,

36, 42,

46

When high, do not write data into the FIFO.

12, 24,

30

fifo_txe#

Output

When low, data can be writteninto the FIFO

by strobing fifo_wr# high, thenlow.

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

63

Enables the current FIFO data byte on

D0...D7 when low. Fetchesthe next FIFO

data byte (if available) from the receive

FIFO buffer when fifo_rd#goesfromhigh to

low

13, 18,

22, 33,

37, 43,

47

14, 25,

31

fifo_rd#

Input

14, 18,

23, 27,

32, 42,

46, 50,

56, 60,

64

14, 19,

23, 34,

38, 44,

48

Writes the data byte on the D0...D7pins

into the transmit FIFO buffer when fifo_wr#

goes from high to low.

15, 26,

32

fifo_wr#

Input

Table 6.16 Data and Control Bus Signal Mode Options - Parallel FIFO Interface

6.6.2 Read / Write Transaction Asynchronous FIFO Mode

When in Asynchronous FIFO interface mode, the timing of read and write operations on the FIFO

interface are shownin Figure 6.22 and Table 6.17.

In asynchronous mode an external device can control data transfer driving FIFO_WR# and FIFO_RD#

inputs. In contrast to synchronous mode, in asynchronous mode the 245 FIFO module generates the

output enable EN# signal. EN# signal is effectively the read signal RD#.

Current byte is available to be read when FIFO_RD# goes low. When FIFO_RD# goes high, FIFO_RXF#

output will also go high. It will only become low again when there is another byte to read.

When FIFO_WR# goes low FIFO_TXE# flag will always go high. FIFO_TXE# goes low again only when

there is still space for data to be written in to the module.

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Figure 6.22 Asynchronous FIFO mode Read / Write Cycle

Time

t1

Description

RD# inactive to RXF#

Minimum

Maximum

Unit

ns

1

100

1

14

t2

RXF# inactive after RD# cycle

RD# to DATA

t3

14

t4

RD# active pulse width

30

0

t5

RD# active after RXF#

t6

WR# active to TXE# inactive

TXE# inactive after WR# cycle

DATA to TXE# active setup time

DATA hold time after WR# inactive

WR# active pulse width

WR# active after TXE#

1

t7

100

5

t8

t9

5

t10

t11

30

0

Table 6.17 Asynchronous FIFO mode Read / Write Timing

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6.7 Parallel FIFO – Synchronous Mode

The Parallel FIFO Synchronous mode has an eight bit data bus, individual read and write strobes, two

hardware flow control signals, an output enable and a clock out.

The synchronous FIFO mode uses the parallel FIFO interface signals detailed in Table 6.16 and an

additional two signals detailed in Table 6.18.

This mode is not available on the 32 pin packages.

64 Pin

Package

48 Pin

Package

32 Pin

Package

Name

Type

Description

Available Available Available

pins

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

11, 15,

20, 31,

35, 41,

45

11, 23

29

fifo_oe#

I/O

FIFO Output enable

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

62

12,16,

21, 32,

36, 42,

46

12, 24,

30

fifo_clkout

I/O

FIFO Clock out

Table 6.18 Synchronous FIFO control signals

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6.7.1 Read / Write Transaction Synchronous FIFO Mode

When in Synchronous FIFO interface mode, the timing of read and write operations on the FIFO interface

are shown in Figure 6.23 Synchronous FIFO mode Read / Write Cycle and Table 6.19

Synchronous FIFO mode Read / Write Timing

In synchronous mode data can be transmitted to and from the FIFO module on each clock edge. An

external device synchronises to the CLKOUT output and it also has access to the output enable OE# input

to control data flow. An external device should drive output enable OE# low before pulling RD# line

down.

When bursts of data are to be read from the module RD# should be kept low. RXF# remains low when

there is still data to be read. Similarly when bursts of data are to be written to the module WR# should

be kept low. TXE# remains low whenthere is still space available for the data to be written.

Figure 6.23 Synchronous FIFO mode Read / Write Cycle

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Time

t1

Description

CLKOUT period

Minimum

Typical

20.83

Maximum

Unit

ns

t2

CLKOUT high period

CLKOUT low period

CLKOUT to RXF#

9.38

1

10.42

11.46

7.83

ns

t3

10.42

ns

t4

ns

CLKOUT to

read DATA valid

t5

1

7.83

ns

t6

t7

OE# to read DATA valid

CLKOUT to OE#

1

7.83

ns

t8

RD# setup time

12

0

t9

RD# hold time

t10

t11

t12

t13

t14

CLKOUT TO TXE#

Write DATA setup time

Write DATA hold time

WR# setup time

1

7.83

12

0

12

0

WR# hold time

Table 6.19 Synchronous FIFO mode Read / Write Timing

6.8 General Purpose Timers

In VNC2 there are 4 General Purpose Timers available. Three are available to the designer and one is

reserved for the RTOS.

The timers have the following features:



16 bit

Count down

One shot and auto-reload

enable

Interrupt on zero

6.9 Pulse Width Modulation

VNC2 provides 8 Pulse Width Modulation (PWM) outputs. These can be used to generate PWM signals

which can be used to control motors, DC/DC converters, AC/DC supplies, etc. Further information is

available in an Application Note AN_140 - Vinculum-II PWM Example.

The features of the PWM module are as follows:



8 PWM outputs

A trigger input

8-bit prescaler

16-bit counter

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

Generation of up to 4-pulse signal with controlled output enable and configurable initial state

Interrupt

A single PWM cycle can have up to 4 pulses (8 edges). The PWM block uses a 16-bit counter to

determine the period of a single PWM cycle. This counter counts system clocks which can also be divided

by an optional 8-bit prescaler. The PWM drivers allow the user to select when PWM output toggles. These

values correspond to the values of 16-bit counter. For example, on the timing diagram below - Figure

6.24, the 16-bit counter counts to 23 and pwm_out[0] output toggles when the counter’s current value is

equal to 7, 8, 12, 14, 15, 16, 19 and 22.

Figure 6.24 PWM – Timing Diagram

The user can also select the initial state of each of the PWM outputs (HI or LOW). PWM outputs can also

be enabled continuously or a cycle can be repeated 1..255 times. The PWM cycle can be started by the

PWM driver or externally using a trigger input.

6.10 General Purpose Input Output

VNC2 provides up to 40 configurable Input/output pins depending on the package. The Input/output pins

are connected to Ports A through E. These ports are controlled by the VNC2 CPU. All ports are

configurable to be either inputs or outputs and allow level or edge driven interrupts to be generated.

To simplify the use of the 40 available GPIO signals, they have been grouped into 5 "ports", identified as

A, B, C, D and E. Each port is 1 byte wide and the RTOS drivers will allow each port to be individually

accessed.

Each GPIO signal is mapped on to a bit of the port value. For example, gpio[A0] is the least significant

bit of the value read from or written to GPIO port A. Similarly, gpio[A7] is the most significant bit of the

value read fromor written to GPIO port A (see Figure 6.25 GPIO Port Groups)

Each pin can be individually configured as input or output. GPIO port A supports an interrupt that can be

used to detect a state change of any of its 8 pins. Port B features a more sophisticated set of 4

configurable interrupts that can be associated with individual pins and supports several conditions such

as positive edge, negative edge, high or low.

gpio[A0]

gpio[A1]

gpio[C0]

gpio[C1]

gpio[E0]

gpio[E1]

gpio[A2]

gpio[A3]

gpio[A4]

gpio[A5]

gpio[A6]

gpio[A7]

gpio[C2]

gpio[C3]

gpio[C4]

gpio[C5]

gpio[C6]

gpio[C7]

gpio[E2]

gpio[E3]

gpio[E4]

gpio[E5]

gpio[E6]

gpio[E7]

PORT A

PORT C

PORT E

gpio[B0]

gpio[B1]

gpio[D0]

gpio[D1]

gpio[B2]

gpio[B3]

gpio[B4]

gpio[B5]

gpio[B6]

gpio[B7]

gpio[D2]

gpio[D3]

gpio[D4]

gpio[D5]

gpio[D6]

gpio[D7]

PORT B

PORT D

Figure 6.25 GPIO Port Groups

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7 USB Interfaces

VNC2 has two USB 1.1 and USB 2.0 compliant interfaces available either as a USB host or slave device

capable of supporting 1.5Mb/s (Low Speed) and 12Mb/s (full Speed) transactions. The USB specification

defines 4 transfer types that are all supported by VNC2:



Interrupt transfer: Used for legacy devices where the device is periodically polled to see if the

device has data to transfer e.g. Mouse, Keyboard. VNC2 interrupt transfers are valid for low- and

full-speed transactions.



Bulk transfer: Used for transferring large blocks of data that have no periodic or transfer rate

requirement e.g. USB to RS232 (FT232R device), memory sticks. VNC2 bulk transfers are only

valid for full-speed transactions.



Isochronous transfer: Used for transferring data that requires a constant delivery rate e.g. web

cam, wireless modem. VNC2 isochronous transfers are only valid for full-speed transactions.

Control transfer: Used to transfer specific requests to all types USB devices (most commonly

used during device configuration). VNC2 control transfers are valid for low- and full-speed

transfers.

USB 2.0 - 480Mb/s (High Speed) transactions are not supported as the power requirements are deemed

excessive for VNC2 target applications. VNC2 configured to Full speedis supported.

VNC2 has two main USB modes of operation: host mode or client (or Slave) mode. As a client, VNC2 is

able to connect to a PC and act as a USB peripheral. At the same time as being a client the second USB

interface is also able to act as a host and connect to a second USB device using two separate ports (i.e.

Port 0 – Host Port 1- Client). Each USB interface can be either a host or a client. It is not possible to

change from host to client or client to host “on-the-fly”. The following diagrams in figure 7.1 give

examples of possible modes of operation:

USB Device

Port 0

USB Host

VNC2

Port 1

BOMS Flash Disk

Port 0 in Slave mode

Port 0 and 1 in Host mode

Port 0

USB Host

VNC2

Port 1

BOMS Flash Disk

Port 0 in Slave mode and Port 1 in Host mode

Port 0 and 1 in Slave mode (Null Modem type application)

Figure 7.1 USB Modes

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8 Firmware

VNC2 firmware model has evolved considerably since VINC1L. For reasons of code maintainability,

performance, stability and ease of use from the point of view of the customer, VNC2 has a modular

firmware model.

VNC2 firmware can be separatedinto 4 categories:



VNC2 real-time operatingsystem(RTOS).

VNC2 device drivers.

User applications – Toolchain.

Precompiled Firmware.

8.1 RTOS

The VNC2 RTOS (VOS) is a pre-emptive priority-based multi-tasking operating system. VOS has been

developed by FTDI and is available to customers for use in their own VNC2 based systems free of charge.

VOS is supplied as linkable object files.

A full explanation and how to use VOS is available in a separate application note which can be

downloadedfromthe FTDI website.

8.2 Device drivers

To facilitate communication between user applications and the VNC2 hardware peripherals FTDI provides

device drivers which operate with VOS. In addition to the hardware device drivers, FTDI provides

function drivers (available from the FTDI website) which build upon the basic hardware device driver

functionality for a specific purpose. For example, drivers for standard USB device classes may be created

which build upon the USB host hardware driver to implement a BOMS class, CDC, printer class or even a

specific vendor class device driver.

8.3 Firmware – Software Development Toolchain

The VNC2 provides customers with the opportunity to customise the firmware and perform useful tasks

without an external MCU. A Firmware application note is available to download from the FTDI website,

this give further details and operating instructions. The VNC2 Software Development Toolchain consists of

the following components:



Compiler

The compiler will take high-level source code and compile it into object code or direct to

programmable code.



Linker

The linker will take object code and libraries and link the code to produce either libraries or

programmable code. It is designed to be as hardware independent as possible to allow reuse in

future hardware devices.



Debugger

The debugger allows a programmer to test code on the hardware platform using a special

communication channel to the CPU. It is also used to debug code – run, stop, single step,

breakpoints etc.

IDE

All compiler, simulator and debugger functions are integrated into a single application for

programmers. It provides a specialised text editor which is used generally used to develop

application code, debugging and simulation.

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8.4 Precompiled Firmware

VNC2 can be programmed with various pre-compiled firmware profiles to allow a designer to easily

change the functionality of the chip.

The following pre-compiled ROM files are currently available:



V2DAP firmware: USB Host for single Flash Disk and general purpose USB peripherals.

Selectable UART, FIFO or SPI interface command monitor. Offers a migration path from VNC1L

designs withVDAP firmware.

V2DPS firmware: USB Host for single Flash Disk and general purpose USB peripherals and USB

peripheral emulating a FT232 on a Host computer. Offers a migration path for VNC1L designs

with VDPS.



V2F2F firmware: USB Host for two Flash Disks with file copy functions. Offers a migration path

for VNC1L designs with VF2F firmware.

CDC Modem Sample Application: Demonstrates connection of a CDC device to USB Port 1 by

establishing a link between the CDC device andthe UART of the VNC2.

USBHost FT232 UART Echo Sample Application: Demonstrates emulation of a FTDI FT232

device on USB Port 1. Data is looped back.

Designers are advised to refer to the FTDI website for the most current details on available Firmware.

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9 Device CharacteristicsandRatings

9.1 Absolute Maximum Ratings

The absolute maximum ratings for VNC2 are shown in Table 9.1. These are in accordance with the

Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the

device.

Parameter

Value

Unit

°C

Storage Temperature

-65 to +150

168

Hours

Floor Life (Out of Bag) At Factory Ambient

( 30°C / 60% Relative Humidity)

(IPC/JEDEC J-STD-033A

MSL Level 3 Compliant)*

Ambient Temperature (Power Applied)

Vcc Supply Voltage

-40 to +85

0 to +3.63

°C

V

VCC_IO

0 to +3.63

V

VCC_PLL_IN

0 to + 1.98

V

DC Input Voltage - USBDP and USBDM

DC Input Voltage - XTIN

-0.5 to +(Vcc +0.5)

-0.5 to +((1.8V VCC PLL IN) +0.5)

-0.5 to +5.00

V

DC Input Voltage - High Impedance Bidirectional

DC Input Voltage - All other Inputs

DC Output Current - Outputs

DC Output Current - Low Impedance Bidirectional

V

-0.5 to +(Vcc +0.5)

Default 4 **

V

mA

Default 4 **

Table 9.1 Absolute Maximum Ratings

If devices are stored out of the packaging beyond this time limit the devices should be baked

*

before use. The devices should be ramped up to a temperature of 125°C and baked for up to 17

hours.

** The drive strength of the output stage may be configured for either 4mA, 8mA, 12mA or 16mA

depending on the register setting controlledwithin the firmware. The default is 4mA.

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9.2 DC Characteristics

DC Characteristics (Ambient Temperature -40˚C to +125˚C)

Parameter

Description

Minimum

Typical

Maximum Units

Conditions

VCC Operating Supply

Voltage

Vcc1

1.62

1.8

1.98

3.63

1.98

V

VCCIO Operating Supply

Voltage

Vcc2

2.97

1.62

3.3

1.8

VCC_PLL Operating Supply

Voltage

VCC_PLL

Operating Supply Current

48MHz

Icc1

Icc2

25

16

mA

Normal Operation

Low Power Mode

Operating Supply Current

24MHz

Operating Supply Current

12MHz

Lowest Power

Mode

Icc3

Icc4

8

mA

µA

Operating Supply Current

128

USB Suspend

Table 9.2 Operating Voltage and Current

Parameter

Voh

Description

Output Voltage High

Output Voltage Low

Input Switching Threshold

Minimum

Typical

Maximum Units

Conditions

I source = 8mA

I sink = 8mA

2.4

V

Vol

0.4

V

Vin

1.5

Table 9.3 I/O Pin Characteristics

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Parameter

Description

Minimum

Typical

Maximum Units

Conditions

I/O Pins Static Output

( High)

UVoh

2.8

V

I/O Pins Static Output

( Low )

UVol

0.3

V

UVse

UCom

UVdif

Single Ended Rx Threshold

Differential Common Mode

Differential Input Sensitivity

Driver Output Impedance

0.8

0.2

3

2.0

2.5

V

UDrvZ

6

9

Ohms

Table 9.4 USB I/O Pin (USBDP, USBDM) Characteristics

Parameter

Description

Minimum

Typical

Maximum Units

Conditions

Power supply of internal

core cells and I/O to core

interface

VCCK

1.62

1.8

1.98

V

1.8V power supply

Power supply of 1.8V OSC

pad

VCC18IO

1.62

-40

-10

1.8

25

1.98

125

10

V

1.8V power supply

Operating junction

temperature

T_J

I_in

I_oz

°C

µA

I_in= VCC18IO or

0V

Input leackage current

±1

Tri-state output leakage

current

10

Table 9.5 Crystal Oscillator 1.8 Volts DC Characteristics

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9.3 ESD and Latch-up Specifications

Description

Human Body Mode (HBM)

Machine mode (MM)

Charged Device Mode (CDM)

Latch-up

Specification

TBD

> ± 200mA

Table 9.6 ESD and Latch-up Specifications

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10ApplicationExamples

10.1 Example VNC2 Schematic (MCU – UART Interface)

VNC2 can be configured to communicate with a microcontroller using a UART interface. An example of

this is shown in Figure 10.1.

Figure 10.1 VNC2 Schematic (MCU – UART Interface)

NOTES: This sample circuit is not intended to be a complete design. It shows the minimum connections

for a basic VNC2 circuit. The value of the capacitors connected to the crystal will depend on the

requirements of the crystal. The 5V0_SW power signal assumes proper switching and over-current

detection conform to the USB-IF specifications for a USB host port. The 120uF capacitor should be a low-

ESR type. The value of the ferrite beads may need adjusted for EMI compatibility. Input and output

capacitors for the 3.3V regulator should be chosen according to the datasheet of the selected part. The

VNC2 outputs connect to the MCU inputs and MCU outputs to VNC2 inputs (TXD to RXD and RTS# to

CTS# in each direction).

NOTE for VNC2-48L1B ONLY: With the 48-pin LQFP package, pin 7 is not connected (VREGOUT). The

regulator output has an internal connection to VCCPLLIN to accommodate a migration path from VNC1L

designs. In this case, pin 3 (VCCPLLIN) requires only one 100nF capacitor to ground. All other packages

require the external circuitry shown to connect VREGOUT to VCCPLLIN.

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11Package Parameters

VNC2 is available in six RoHS Compliant packages, three QFN packages (64QFN, 48QFN & 32QFN) and

three LQFP packages (64LQFP, 48LQFP & 32LQFP). All packages are lead (Pb) free and use a ‘green’

compound. The packages are fully compliant with EuropeanUnion directive 2002/95/EC.

The mechanical drawings of all six packages are shown in sections 11.2 to 11.7– all dimensions are in

millimetres.

The solder reflow profile for all packages can be viewed in Section 11.8.

11.1 VNC2 Package Markings

An example of the markings on each package is shown in Figure 11.1. The FTDI part number is too long

for the 32 QFN package so in this case the last two digits are wrapped down onto the date code line as

shown in Figure 11.2.

Line 1 – FTDI Logo

FTDl

Line 2 – Wafer Lot Number

XXXXXXXXXX

Line 3 – FTDI Part Number

including revision. In this case it shows Rev

VNC2-64Q1A

A. Please check for most recent revision.

Line 4 - Date Code

YYWW

YY - year year

WW - work week

Figure 11.1 Package Markings

FTDl

XXXXXXXXXX

VNC2-32Q

1A YYWW

Figure 11.2 Markings – 32 QFN

The last letter of the FTDI part number is the silicon revision number. This may change from A to B to C,

etc.,. Please check the part number for the most recent revision.

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11.2 VNC2, LQFP-32 Package Dimensions

FTDl

XXXXXXXX

VNC2-32L1A

YYWW

PIN #32

PIN #1

Figure 11.3 LQFP-32 Package Dimensions

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11.3 VNC2, QFN-32 Package Dimensions

FTDl

XXXXXXXX

VNC2-32Q

1A YYWW

1

Figure 11.4 QFN-32 Package Dimensions

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11.4 VNC2, LQFP-48 Package Dimensions

9

7

FTDl

XXXXXXXX

VNC2-48L1A

YYWW

7

9

PIN#48

Pin#1

0.22+/- 0.05

0.5

1.0

0. 24+/- 0.07

12^o+/- 1^o

0. 09Min

0. 16 Max

0. 09Min

0. 2 Max

0.25

0. 22+/- 0.05

0. 05Min

0. 15 Max

0. 2 Min

0. 6+/- 0.15

Figure 11.5 LQFP-48 Package Dimensions

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11.5 VNC2, QFN-48 Package Dimensions

FTDl

XXXXXXXXXX

VNC2-48Q1A

YYWW

1

Figure 11.2 QFN-48 Package Dimensions

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11.6 VNC2, LQFP-64 Package Dimensions

12

10

FTDl

XXXXXXXX

VNC2-64L1A

YYWW

Pin # 64

Pin # 1

0.5

1.0

o

12 +/-1

o

0. 22+/- 0.05

0. 09Min

0. 16 Max

0. 09Min

0. 2 Max

0.25

Mi

0.05

Mi

n

0.2

Ma

n

0.2+/- 0.03

0.15

0.6 +/-0.15

x

Figure 11.6 64 pin LQFP Package Details

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11.7 VNC2, QFN-64 Package Dimensions

FTDl

XXXXXXXXXX

VNC2-64Q1A

YYWW

Figure 11.7 64 pin QFN Package Details

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11.8 Solder Reflow Profile

Figure 11.8 All packages Reflow Solder Profile

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Pb Free Solder Process

SnPb Eutectic and Pb free (non

Profile Feature

green material) Solder Process

(green material)

Average Ramp Up Rate (T_sto T_p)

3°C / second Max.

3°C / Second Max.

Preheat:

- Temperature Min (T_sMin.)

- Temperature Max (T_sMax.)

- Time (t_sMin to t_sMax)

150°C

200°C

100°C

150°C

60 to 120 seconds

Time Maintained Above Critical

Temperature T_L:

- Temperature (T_L)

- Time (t_L)

217°C

183°C

60 to 150 seconds

Peak Temperature (T_p)

260°C

see Table 11.2

Time within 5°C of actual Peak

Temperature (t_p)

30 to 40 seconds

20 to 40 seconds

Ramp Down Rate

6°C / second Max.

8 minutes Max.

6°C / second Max.

6 minutes Max.

Time for T= 25°C to Peak Temperature, T_p

Table 11.1 Reflow Profile Parameter Values

SnPb Eutectic and Pb free (non green material)

Package Thickness

Volume mm3 < 350

235 +5/-0 °C

Volume mm3 >=350

220 +5/-0 °C

< 2.5 mm

220 +5/-0 °C

≥ 2.5 mm

Pb Free (green material) = 260 +5/-0 °C

Table 11.2 Package Reflow Peak Temperature

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12Contact Information

Head Office – Glasgow, UK

Branch Office – Tigard, Oregon, USA

Future Technology DevicesInternational Limited

Unit 1, 2 Seaward Place, Centurion Business Park

Glasgow G41 1HH

Future Technology DevicesInternational Limited (USA)

7130 SW Fir Loop

Tigard, OR 97223-8160

USA

United Kingdom

Tel: +44 (0) 141 429 2777

Fax: +44 (0) 141 429 2758

Tel: +1 (503) 547 0988

Fax: +1 (503) 547 0987

E-mail (Sales)

E-mail (Support)

sales1@ftdichip.com

support1@ftdichip.com

E-Mail (Sales)

E-Mail (Support)

us.sales@ftdichip.com

us.support@ftdichip.com

E-mail (GeneralEnquiries) admin1@ftdichip.com

E-Mail (General Enquiries) us.admin@ftdichip.com

Branch Office – Taipei, Taiwan

Branch Office – Shanghai, China

Future Technology DevicesInternational Limited

(Taiwan)

2F, No. 516, Sec. 1, NeiHu Road

Taipei 114

Future Technology DevicesInternational Limited (China)

Room 1103, No. 666 West Huaihai Road,

Shanghai, 200052

China

Taiwan , R.O.C.

Tel: +886 (0) 2 8797 1330

Fax: +886 (0) 2 8751 9737

Tel: +86 21 62351596

Fax: +86 21 62351595

E-mail (Sales)

E-mail (Support)

E-mail (GeneralEnquiries) cn.admin@ftdichip.com

cn.sales@ftdichip.com

cn.support@ftdichip.com

E-mail (Sales)

E-mail (Support)

tw.sales1@ftdichip.com

tw.support1@ftdichip.com

E-mail (GeneralEnquiries) tw.admin1@ftdichip.com

Web Site

http://ftdichip.com

Distributor and Sales Representatives

Please visit the SalesNetwork page of the FTDI Web site forthe contact details of ourdistributor(s) and sales

representative(s) in yourcountry.

Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or re produced

in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are

supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology

Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your

statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in

which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary

information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by

the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,

GlasgowG41 1HH,United Kingdom.Scotland Registered Company Number: SC136640

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Appendix A – References

Application, Technical Notes,Toolchain download and precompiled romfile

links

The following VNC2 documents and the full Vinculum-II Toolchain software suite can be downloaded by

clicking on the appropriate links below:

Technical note TN_108

Technical note TN_118

Application note AN_118

Application note AN_137

Application note AN_138

Application note AN_139

Application note AN_140

Application note AN_142

Application note AN_144

Application note AN_145

Application note AN_151

VNC2 FTDI Web Page

Vinculum Chipset Feature Comparison

Vinculum-II Errata Technical Note

Migrating Vinculum Designs FromVNC1L to VNC2-48L1A

Vinculum-II IO Cell Description

Vinculum-II Debug Interface Description

Vinculum-II IO Mux Explained

Vinculum-II PWM Example

Vinculum-II Toolchain Getting Started Guide

Vinculum-II IO_Mux Configuration Utility User Guide

Vinculum-II Toolchain Installation Guide

Vinculum-II User Guide

Vinculum-II Web Page

The following application notes provide pre-compiled example rom files and complete source code to

allow users to get started:



Application note AN_182 : VNC2 UART to FT232 HostBridge

Application note AN_183 : VNC2 UART to CDC ModemBridge

Application note AN_185 : VNC2 UART to USB HID Class HostBridge

Application note AN_186 : an SPI Slave to USB Memory bridge

Application note AN_187 : VNC2 UART to USB Memory Bridge

Application note AN_192 : an SPI Master to a USB HID class host bridge

Application note AN_193 : an SPI Master to a USB HID class host bridge

Application note AN_194 : VNC2 UART to HID Class device bridge

Application note AN_195 : an SPI Master to UART bridge

Application note AN_199 : VNC2 SPI Slave to HID Class device bridge

Application note AN_203 : Loading VNC2 ROM files Using V2PROG Utility

For the most up to date pre-compiled romfiles, please refer to the following FTDI webpage

http://www.ftdichip.com/Firmware/Precompiled.htm

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Acronyms and Abbreviations

Terms

Description

USB

FIFO

SPI

Universal Serial Bus

First In First Out

Serial Peripheral Interface

Pulse Width Modulation

General Purpose Input Output

Input / Output

PWM

GPIO

I/O

VNC1L

VNC2

DMA

IDE

Vinculum-I

Vinculum-II

Direct Memory Access

Integrated Development Environment

Bulk Only Mass Storage

Universal AsynchronousReceiver/Transmitter

Serial Interface Engine

Central ProcessingUnit

System-on-a-chip

BOMS

UART

SIE

CPU

SoC

FAT

File Allocation Table

RTOS

VOS

OSI

Real Time Operating System

Vinculum Operating System

Open SystemInterconnection

Master Out Slave In

MOSI

MISO

SE0

Master In Slave Out

Single Ended Zero

EMCU

FPGA

EmbeddedMicro Central Processing Unit

Field Programmable Gate Array

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Appendix B – List of Figures and Tables

List of Tables

Table 1.1 Part Numbers..........................................................................................................................2

Table 3.1 USB Interface Group.............................................................................................................16

Table 3.2 Power and Ground.................................................................................................................16

Table 3.3 Miscellaneous Signal Group...................................................................................................17

Table 3.4 Default I/O Configuration......................................................................................................20

Table 4.1 - Peripheral Pin Requirements ...............................................................................................22

Table 5.1 I/O Peripherals Signal Names...............................................................................................29

Table 5.2 Group 0 ................................................................................................................................31

Table 5.3 Group 1 ................................................................................................................................32

Table 5.4 Group 2................................................................................................................................33

Table 5.5 Group 3 ................................................................................................................................34

Table 6.1 Data and Control Bus Signal Mode Options – UART Interface .................................................38

Table 6.2 SPI Signal Names..................................................................................................................39

Table 6.3 - SPI Slave Speeds................................................................................................................40

Table 6.4 - Clock Phase/Polarity Modes.................................................................................................40

Table 6.5 Data and Control Bus Signal Mode Options - SPI Slave Interface...........................................42

Table 6.6 SPI Command and Status Fields............................................................................................44

Table 6.7 SPI Command and Status Fields............................................................................................49

Table 6.8 SPI Setup Bit Encoding..........................................................................................................49

Table 6.9 SPI Slave Data Timing...........................................................................................................50

Table 6.10 SPI Master Data Read Status Bit..........................................................................................51

Table 6.11 SPI Master Data Write Status Bit.........................................................................................51

Table 6.12 SPI Status Read Byte – bit descriptions...............................................................................52

Table 6.13 SPI Master Signal Names.....................................................................................................54

Table 6.14 SPI Master Timing ...............................................................................................................55

Table 6.15 Debugger Signal Name.......................................................................................................56

Table 6.16 Data and Control Bus Signal Mode Options - Parallel FIFO Interface.....................................59

Table 6.17 Asynchronous FIFO mode Read / Write Timing.....................................................................60

Table 6.18 Synchronous FIFO control signals........................................................................................61

Table 6.19 Synchronous FIFO mode Read / Write Timing ......................................................................63

Table 9.1 Absolute Maximum Ratings ...................................................................................................68

Table 9.2 Operating Voltage and Current..............................................................................................69

Table 9.3 I/O Pin Characteristics...........................................................................................................69

Table 9.4 USB I/O Pin (USBDP, USBDM) Characteristics........................................................................70

Table 9.5 Crystal Oscillator 1.8 Volts DC Characteristics........................................................................70

Table 9.6 ESD and Latch-up Specifications............................................................................................71

Table 11.1 Reflow Profile Parameter Values ..........................................................................................81

Table 11.2 Package Reflow Peak Temperature ......................................................................................81

List of Figures

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Figure 2.1 Simplified VNC2 Block Diagram..............................................................................................3

Figure 3.1 32 Pin LQFP – Top Down View...............................................................................................7

Figure 3.2 32 Pin QFN – Top Down View................................................................................................8

Figure 3.3 48 Pin LQFP – Top Down View...............................................................................................9

Figure 3.4 48 Pin QFN – Top Down View...............................................................................................10

Figure 3.5 64 Pin LQFP – Top Down View.............................................................................................11

Figure 3.6 64 Pin QFN – Top Down View...............................................................................................12

Figure 3.7 Schematic Symbol 32 Pin.....................................................................................................13

Figure 3.8 Schematic Symbol 48 Pin.....................................................................................................14

Figure 3.9 Schematic Symbol 64 Pin.....................................................................................................15

Figure 5.1 IOBUS to Group Relationship-64 Pin.....................................................................................25

Figure 5.2 IOBUS to UART, SPI slave0 and SPI master example............................................................26

Figure 5.3 IOBUS to UART, SPI slave0 and SPI master second example ................................................27

Figure 5.4 IOBUS to UART, SPI slave0 and SPI master third example....................................................28

Figure 5.5 VNC2 Toolchain App Wizard showing IOMux Configuration....................................................30

Figure 5.6 UART Example 64 pin...........................................................................................................35

Figure 6.1 UART Receive Waveform......................................................................................................36

Figure 6.2 UART Transmit Waveform....................................................................................................36

Figure 6.3 - SPI CPOL CPHA Function....................................................................................................41

Figure 6.4 SPI Slave block diagram ......................................................................................................41

Figure 6.5 Full Duplex Data Master Write..............................................................................................43

Figure 6.6 Full Duplex Data Master Read ..............................................................................................43

Figure 6.7 SPI Command and Status Structure.....................................................................................44

Figure 6.8 Half Duplex Data Master Write .............................................................................................45

Figure 6.9 Half Duplex Data Master Read..............................................................................................45

Figure 6.10 Half Duplex 3-pin Data Master Write ..................................................................................46

Figure 6.11 Half Duplex 3-pin Data Master Read...................................................................................46

Figure 6.12 Unmanaged Mode Transfer Diagram...................................................................................47

Figure 6.13 VNC1L Mode Data Write.....................................................................................................48

Figure 6.14 VNC1L Mode Data Read......................................................................................................48

Figure 6.15 VNC1L Compatible SPI Command and Status Structure ......................................................49

Figure 6.16 SPI Slave Mode Timing.......................................................................................................50

Figure 6.17 SPI Master Data Read (VNC2 Slave Mode)..........................................................................51

Figure 6.18 SPI Slave Mode Data Write.................................................................................................52

Figure 6.19 SPI Slave Mode Status Read ..............................................................................................52

Figure 6.20 SPI Master block diagram...................................................................................................53

Figure 6.21 Typical SPI Master Timing ..................................................................................................55

Figure 6.22 Asynchronous FIFO mode Read / Write Cycle .....................................................................60

Figure 6.23 Synchronous FIFO mode Read / Write Cycle .......................................................................62

Figure 6.24 PWM – Timing Diagram......................................................................................................64

Figure 6.25 GPIO Port Groups...............................................................................................................64

Figure 7.1 USB Modes ..........................................................................................................................65

Figure 10.1 VNC2 Schematic (MCU – UART Interface)...........................................................................72

Figure 11.1 Package Markings ..............................................................................................................73

86

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Figure 11.2 Markings – 32 QFN.............................................................................................................73

Figure 11.3 LQFP-32 Package Dimensions.............................................................................................74

Figure 11.4 QFN-32 Package Dimensions..............................................................................................75

Figure 11.5 LQFP-48 Package Dimensions.............................................................................................76

Figure 11.6 64 pin LQFP Package Details ..............................................................................................78

Figure 11.7 64 pin QFN Package Details................................................................................................79

Figure 11.8 All packages Reflow Solder Profile ......................................................................................80

87

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

Version 1.7

Document No.: FT_000138 Clearance No.: FTDI#143

Appendix C – Revision History

Document Title:

Vinculum-II Embedded Dual USB Host Controller IC Datasheet

Document Reference No.:

Clearance No.:

FT_000138

FTDI# 143

Document Folder:

Document Feedback:

Vinculum-II

Send Feedback

Revision

Changes

Date

Data sheet released as “Preliminary – Subject to change” before

product launch

Prelim

1.0

2010-02-01

2010-02-26

2010-09-09

Initial Release

Changed gpio signal names, fixed minor typographical errors, added

crystal characteristic information, added ESD table

1.1

Revised part numbers to “Rev B” in section 1.2, added notes to

sections 3.12 and 5 – default pin assignments

1.2

2010-10-07

1.3

Added USB transfer/transaction combinations

Table 37 (now 9.6) modified

2011-04-19

2011-05-16

2011-05-17

1.31

1.32

Table 33 (now 9.2) modified

Renumbered andreformatted figures andtables, Added life/safety

notice, Added comments regarding 48LQFP package in table 3.2,

Replaced Figure 5.5 with new screenshot, Updatedlist of pre-

compiled firmware in section 8.4, Replaced schematic and added

notes in Section 10, Updatedheader, Updatedrevision history and

contact information pages

1.4

1.5

2011-10-17

2012-03-14

Added notes (5V safe inputs) in section 3.11, 3.12 and first page.

Added links to pre-compiled rom files.

XTIN is referencedto 1.8V VCC PLL IN

- Tables 3.3 and 9.1

1.6

1.7

2016-07-07

2016-07-21

Pin 8 updated fromTEST to NC for rev C

Removed revision code in table1.1

88


型号：	USB2DM
厂家：	FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD.
描述：	Vinculum-II Embedded Dual USB Host Controller IC
文件：	总88页 (文件大小：2234K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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