EDC4UV6482-60JG-S [FUJITSU]
EDO DRAM Module, 4MX64, 60ns, CMOS, PDMA168;
| 型号： | EDC4UV6482-60JG-S |
| 厂家： | 
FUJITSU |
| 描述： | EDO DRAM Module, 4MX64, 60ns, CMOS, PDMA168 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1996
Revision 1.0
DATA SHEET
EDC4UV6482-(60/70)(J/T)G-S
32MByte (4M x 64) CMOS EDO DRAM Module - 3.3V
General Description
The EDC4UV6482-(60/70)(J/T)G-S is a high performance, EDO (Extended Data Out) 32-megabyte dynamic RAM module orga-
nized as 4M words by 64 bits, in a 168-pins, dual-in-line (DIMM) memory modules.
The module utilizes sixteen, Fujitsu MB81V17805A-(60/70) (PJ/FN) CMOS 2Mx8 EDO dynamic RAMs in a surface mount package
on an epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity.
Control lines provided are such that byte control is possible. Serial PD on the module is provided by using 128 byte serial EEPROM.
Features
• High Density: 32MByte
• Fast Access Time of 60/70 ns (max.)
• Low Power: 3.5/3.2 W (max.) - Active (60/70 ns)
115mW (max.) - Standby (LVTTL)
57mW (max.)
- Standby (CMOS)
• LVTTL-compatible inputs and outputs
• Separate power and ground planes to improve noise immunity
• Single power supply of 3.3V±0.3V
• Height: 1.00 inch
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
-0.5 to +4.6
16
Unit
V
Voltage on any pin relative to V
V
P
SS
T
Power Dissipation
W
T
T
Operating Temperature
Storage Temperate
0 to +70
-55 to +125
50
°C
°C
mA
opr
T
stg
OS
I
Short Circuit Output Current
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to +70 °C)
Symbol
Parameter
Supply Voltage
Min
Typ
Max
3.6
0
Unit
V
V
V
V
3.0
0
3.3
V
V
V
V
CC
SS
IH
Ground
0
-
V
+0.3
Input High voltage
Input Low voltage
2.0
-0.3
CC
-
0.8
IL
Fujitsu Microelectronics, Inc.
1
September 1996
Revision 1.0
EDC4UV6482-(60/70)(J/T)G-S
Functional Diagram
CAS7*
CAS6*
CAS5*
CAS4*
CAS3*
CAS2*
CAS1*
CAS0*
2M x 8
EDO
DRAM
2M x 8
EDO
DRAM
2M x 8
EDO
DRAM
2M x 8
EDO
DRAM
2M x 8
EDO
DRAM
2M x 8
EDO
DRAM
2M x 8
EDO
DRAM
2M x 8
EDO
DRAM
OE0*
OE2*
WE2*
WE0*
RAS0*
RAS2*
2M x 8
EDO
2M x 8
EDO
2M x 8
EDO
2M x 8
EDO
2M x 8
EDO
2M x 8
EDO
2M x 8
EDO
2M x 8
EDO
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
RAS1*
RAS3*
DQ0~DQ63
SA0
SA1
SA2
SCL
SDA
V
V
SS
Serial
EEPROM
Device
CC
Decoupling capacitors
to all devices
(All specifications of the device are subject to change without notice.)
Notes:
1. “*” signifies active low signal.
2. Addresses A0 ~ A10 are connected to all DRAMs.
Fujitsu Microelectronics, Inc.
2
September 1996
Revision 2.0
EDC4UV6482-(60/70)(J/T)G-S
Pin Name
A0~A10
Addresses
Data Inputs/Outputs
Write Enable
Row Address Strobes
Serial Data Input/Output
Output Enable
CAS0*~CAS7*
SA0~SA2
SCL
VCC
VSS
Column Address Strobes
Decode Inputs
Serial Clock
Power Supply
Ground
DQ0~DQ63
WE0*, WE2*
RAS0*~RAS3*
SDA
OE0*, OE2*
NC
No Connection
Pin No.
Pin Designation
Pin No.
43
Pin Designation
Pin No.
85
Pin Designation
Pin No.
127
Pin Designation
V
V
V
V
SS
1
2
3
4
5
6
SS
SS
SS
DQ0
DQ1
DQ2
DQ3
44
OE2*
86
DQ32
DQ33
DQ34
DQ35
128
NC
45
RAS2*
CAS2*
CAS3*
WE2*
87
129
RAS3*
CAS6*
CAS7*
NC
46
88
130
47
89
131
V
V
48
90
132
CC
CC
V
V
7
8
DQ4
DQ5
DQ6
DQ7
DQ8
49
50
51
52
53
54
55
56
57
58
59
91
92
DQ36
DQ37
DQ38
DQ39
DQ40
133
134
135
136
137
138
139
140
141
142
143
CC
CC
NC
NC
NC
NC
NC
NC
NC
NC
9
93
10
11
12
13
14
15
16
17
94
95
V
V
V
V
96
SS
SS
SS
SS
DQ9
DQ16
DQ17
DQ18
DQ19
97
DQ41
DQ42
DQ43
DQ44
DQ45
DQ48
DQ49
DQ50
DQ51
DQ10
DQ11
DQ12
DQ13
98
99
100
101
V
V
CC
CC
V
V
18
19
20
21
22
60
61
62
63
64
DQ20
NC
102
103
104
105
106
144
145
146
147
148
DQ52
NC
CC
CC
DQ14
DQ15
NC
DQ46
DQ47
NC
NC
NC
NC
NC
V
V
NC
NC
SS
SS
V
V
23
24
25
26
27
28
29
30
31
65
66
67
68
69
70
71
72
73
DQ21
DQ22
DQ23
107
108
109
110
111
112
113
114
115
149
150
151
152
153
154
155
156
157
DQ53
DQ54
DQ55
SS
SS
NC
NC
NC
NC
V
V
V
V
CC
SS
CC
SS
WE0*
CAS0*
CAS1*
RAS0*
OE0*
DQ24
DQ25
DQ26
DQ27
NC
DQ56
DQ57
DQ58
DQ59
CAS4*
CAS5*
RAS1*
NC
V
V
CC
CC
V
V
32
33
34
35
36
37
38
39
40
74
75
76
77
78
79
80
81
82
DQ28
DQ29
DQ30
DQ31
116
117
118
119
120
121
122
123
124
158
159
160
161
162
163
164
165
166
DQ60
DQ61
DQ62
DQ63
SS
SS
A0
A2
A4
A6
A8
A10
NC
A1
A3
A5
A7
A9
NC
NC
V
V
SS
SS
NC
NC
NC
SDA
NC
NC
SA0
SA1
V
V
CC
CC
V
41
42
83
84
SCL
125
126
NC
NC
167
168
SA2
CC
V
V
NC
CC
CC
Fujitsu Microelectronics, Inc.
3
September 1996
Revision 1.0
EDC4UV6482-(60/70)(J/T)G-S
DC CHARACTERISTICS
(VCC = 3.3V±0.3V, VSS = 0V, TA = 0 to +70 °C)
60
70
Parameter
Symbol
Test Condition
Unit
Note
Min.
Max.
Min.
Max.
I
RAS*, CAS* cycling; t = min.
Operating Current
-
976
-
896
mA
1, 2
CC1
RC
LVTTL Interface
RAS*, CAS* ≥ V
-
-
32
16
-
-
32
16
mA
mA
IH
D
= HIgh-Z
out
I
Standby current
CC2
CMOS Interface
RAS*, CAS* ≥ V - 0.2V
cc
D
= HIgh-Z
out
CAS* ≥ V ; RAS*, Address
RAS* -only Refresh
Current
IH
I
-
-
976
976
-
-
896
896
mA
mA
2
CC3
cycling @ t = min.
RC
RAS*, CAS* cycling @
CAS*-before-RAS*
Refresh Current
I
CC4
t
= min.
RC
RAS* ≤ V ; CAS*, Address
Hyper Page Mode
Current
IL
I
-
976
160
20
-
896
160
20
mA
µA
µA
1, 3
CC5
cycling @ t = min.
PC
I
0V ≤ Vin ≤ V + 0.3V
Input Leakage Current
Output Leakage Current
-160
-20
-160
-20
LI
CC
0V ≤ Vout ≤ V
CC
I
LO
D
= Disable
out
V
High I = -2mA
Output High Voltage
Output Low Voltage
2.4
0
-
2.4
0
-
V
V
OH
out
V
Low I = 2 mA
0.4
0.4
OL
out
Notes:
1. Values depend on output load condition when the device is selected. Maximum Values are specified at the output open condition.
2. Address can be changed once or less while RAS* = V .
IL
3. Address can be changed once or less while CAS* = V
.
IH
CAPACITANCE
(TA =+25°C, VCC = 3.3V±0.3V)
Parameter
Symbol
Max.
85
Unit
pF
Note
C
Input Capacitance (Address)
1
1
I1
C
Input Capacitance (RAS*)
33
pF
I2
C
Input Capacitance (CAS0*~CAS7*)
Input Capacitance (OE*, WE*)
Input/Output Capacitance (DQ0~DQ63)
20
pF
1
I3
C
61
pF
1
I4
C
20
pF
1, 2
I/O
Notes:
1. Capacitance is measured with Boonton Meter or effective capacitance method.
2. CAS* - V to disable D
.
out
IH
Fujitsu Microelectronics, Inc.
4
September 1996
Revision 2.0
EDC4UV6482-(60/70)(J/T)G-S
AC CHARACTERISTICS
(TA = 0 to +70°C, VCC = 3.3V±0.3V, VSS = 0V)
60
70
Parameter
Symbol
Unit
Notes
Min
110
-
Max
Min
130
-
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Random read/write cycle time
Access time from RAS*
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
RC
60
70
3, 4
3, 4, 5
3, 10
2
RAC
CAC
AA
Access time from CAS*
-
15
-
20
Access time from column address
Transition time (rise and fall)
RAS* precharge time
-
30
-
35
2
50
2
50
T
40
60
15
45
10
20
15
5
-
50
70
20
50
15
20
15
5
-
RP
RAS* pulse width
10000
10000
RAS
RSH
CSH
CAS
RCD
RAD
CRP
ASR
RAH
ASC
CAH
RAL
RCS
RCH
RRH
WCH
WP
RAS* hold time
-
-
CAS* hold time
-
-
CAS* pulse width
10000
10000
RAS* to CAS* delay time
RAS* to column address delay time
CAS* to RAS* precharge time
Row address set-up time
45
50
4
30
35
10
-
-
0
-
0
-
Row address hold time
10
0
-
10
0
-
Column address set-up time
Column address hold time
Column address to RAS* lead time
Read command set-up time
Read command hold time to CAS*
Read command hold time to RAS*
Write command hold time
Write command pulse width
Write command to RAS* lead time
Write command to CAS* lead time
Data-in set-up time
-
-
10
30
5
-
15
35
5
-
-
-
-
-
0
-
0
-
8
0
-
0
-
10
10
15
10
0
-
15
15
20
15
0
-
-
-
-
-
RWL
CWL
DS
-
-
-
-
9
9
Data-in hold time
10
-
-
15
-
-
DH
Refresh period (2048 cycles)
Write command set-up time
CAS* set-up time (CBR refresh)
CAS* hold time (CBR refresh)
RAS* precharge to CAS* hold time
Access time from CAS* precharge
Hyper page mode cycle time
CAS* precharge time (Hyper page)
RAS* pulse width (Hyper page)
32
32
REF
WCS
CSR
CHR
RPC
CPA
HPC
CP
0
-
0
-
7
1
1
10
10
5
-
10
15
5
-
-
-
-
-
-
35
-
40
3, 11
12
25
10
60
-
30
10
70
-
-
-
100000
100000
RASP
Fujitsu Microelectronics, Inc.
5
September 1996
Revision 1.0
EDC4UV6482-(60/70)(J/T)G-S
Notes:
1. An initial pulse of at least 200µs is required after power-up followed by a minimum of eight RAS* cycles before device operation
is achieved.
2.
V
(min.) and V (max.) are reference levels for measuring timing of input signals. Transition times are measured between V
IH IL IH
(min.) and V (max.) and are assumed to be 5 ns for all inputs.
IL
3. Measure with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the t (max.) limit ensures that t (max.) limit can be met; t (max.) is specified as a reference point
RCD
RCD
RAC
only. If t
is greater than the specified t
(max) limit, then access time is controlled exclusively by t
.
RCD
RCD
CAC
5. Assumes that tRCD ≥ t
(max.).
RAD
6. This parameter defines the time at which the output achieves open circuit condition and is not referenced to V or V
.
OH
OL
7.
t
is non restrictive operating parameter. It is included in the data sheet as an electrical characteristic only. If tWCS ≥ t
(min.)
WCS
WCS
the cycle is an early write cycle and the data out pin will remain at high impedance for the duration of the cycle.
8. Either t or t must be satisfied for a read cycle.
RCH
RRH
9. These parameters are referenced to the CAS* leading edge in early write cycles.
10. Operation within the t (max.) limit ensures that t (max.) limit can be met. t (max.) is specified as a reference point only.
RAD
RAD
RAC
If t
is greater than the specified t
(max.) limit, then access time is controlled by t
.
RAD
RAD
AA
11. Access time is determined by the longer of t , t
, or t
.
AA CAC
ACP
12.
t
defines RAS* pulse width in fast page mode cycles.
RASC
Physical Dimensions
168-pin (84x2) DIMM
5.250
Note†
5.171
5.014
0.158
1
11
40
41
84
0.118
2.150
1.450
0.450
0.250
0.250
1.700
2.507
0.050
±0.004
4.550 (Ref.)
5.014
0.350
Front View
Notes:
1. All dimensions are in inches.
2. Pin 85 is behind pin 1 on the back side.
3. Thickness =0.350 for SOJ DRAMs
=0.170 for TSOP DRAMs
Fujitsu Microelectronics, Inc.
6
September 1996
Revision 2.0
EDC4UV6482-(60/70)(J/T)G-S
All Rights Reserved.
Circuit diagrams using fujitsu products are included to illustrate typical semiconductor applications.
Information sufficient for construction purpose may not be shown.
The information contained in this document has been carefully checked and is believed to be reliable.
However, Fujitsu Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent
rights or trademarks claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu
Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
No part of the publication may be copied or reproduced in any form or by any means, or transferred
to any third party without prior written consent of Fujitsu Microelectronics, Inc.
7
September 1996
Revision 1.0
EDC4UV6482-(60/70)(J/T)G-S
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http://www.fujitsumicro.com
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MP-DRAMM-DS-20388-9/96
8
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