FSA4UN3244-60JS-S [FUJITSU]
Fast Page DRAM Module, 4MX32, 60ns, CMOS, PSMA72,;
| 型号： | FSA4UN3244-60JS-S |
| 厂家： | 
FUJITSU |
| 描述： | Fast Page DRAM Module, 4MX32, 60ns, CMOS, PSMA72, 动态存储器 内存集成电路 |
| 文件： | 总8页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1996
Revision 1.0
DATA SHEET
FSA4UN324(2/4)-(60/70)J(G/S)-S
16MByte (4M x 32) CMOS DRAM Module
General Description
The FSA4UN324(2/4)-(60/70)J(G/S)-S is a high performance, 16-megabyte dynamic RAM module organized as 4M words by
32bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package with JEDEC pinout. DM4M4N320 supports 4K refresh.
DM4M2N320 supports 2K refresh.
The module utilizes sixteen, Fujitsu MB811(6/7)400A-(60/70)PJ CMOS 4Mx4 dynamic RAM in a surface mount package on an
epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity.
Control lines provided are such that byte control is possible.
Features
• JEDEC pinout
• High Density: 16MByte
• Fast Access Time of 60/70 ns (max.)
• Low Power:
Active (60/70 ns)
3.52/3.08 W (max.) - 4K
4.40/3.96 W (max.) - 2K
88mW (max.) - Standby (TTL)
44mW (max.) - Standby (CMOS)
• TTL-compatible inputs and outputs
• Separate power and ground planes
• Single power supply of 5V±10%
• PCB footprint of less than 0.85 sq. in.
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
-1 to +7.0
8
Unit
V
Voltage on any pin relative to V
V
SS
T
P
Power Dissipation
W
T
T
Operating Temperature
Storage Temperate
0 to +70
-55 to +125
-50 to +50
°C
°C
mA
opr
T
stg
I
Short Circuit Output Current
OS
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to +70 °C)
Symbol
Parameter
Supply Voltage
Min
Typ
Max
5.5
0
Unit
V
V
V
V
4.5
0
5.0
V
V
V
V
CC
SS
IH
Ground
0
-
V
+1
Input High voltage
Input Low voltage
2.4
-1
CC
-
0.8
IL
Fujitsu Microelectronics, Inc.
1
June 1996
Revision 1.0
FSA4UN324(2/4)-(60/70)J(G/S)-S
Functional Diagram
4M x 8 Block
CAS3*
CAS2*
CAS1*
CAS0*
4M x 4
DRAM
4M x 4
DRAM
4M x 8
Block
4M x 8
Block
4M x 8
Block
4M x 8
Block
RAS2*
RAS0*
DQ0~DQ7
DQ8~DQ15
DQ16~DQ23
DQ24~DQ31
DQ0~DQ35
V
V
SS
CC
Decoupling capacitors
to all devices
(All specifications of the device are subject to change without notice.)
Notes:
1. “*” signifies active low signal.
2. A0 ~ A10/A11 to all devices (A11 is NC for 2K refresh).
3. WE* to all devices.
4. OE* of all devices are grounded.
Fujitsu Microelectronics, Inc.
2
June 1996
Revision 1.0
FSA4UN324(2/4)-(60/70)J(G/S)-S
Pin Name
A0~A10†
A0~A11
A0~A9
DQ0~DQ31
CAS0*~CAS3*
RAS0*, RAS2*
Addresses for 2K Refresh Module
Row Addresses for 4K Refresh Module
Column Addresses for 4K Refresh Module
Data Inputs/Outputs
Column Address Strobes
Row Address Strobes
WE*
PD1~PD4
VCC
VSS
NC
Write Enable
Presence Detects
Power Supply
Ground
No Connection
Presence Detect Pins
Pin
PD1
PD2
PD3
PD4
-60
-70
V
V
SS
SS
NC
NC
NC
NC
V
SS
NC
Pin No.
Pin Designation
Pin No.
Pin Designation
Pin No.
37
Pin Designation
Pin No.
55
Pin Designation
V
1
2
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A10
NC
DQ11
DQ27
DQ12
DQ28
SS
DQ0
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
38
NC
V
56
3
DQ16
DQ1
39
57
SS
4
40
CAS0*
CAS2*
CAS3*
CAS1*
RAS0*
NC
58
V
5
DQ17
DQ2
41
59
CC
6
42
60
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
7
DQ18
DQ3
43
61
8
44
62
9
DQ19
45
63
V
10
11
12
13
14
15
16
17
18
46
NC
64
CC
NC
A0
A1
A2
A3
A4
A5
A6
A11†
47
WE*
65
V
48
NC
66
CC
A8
49
DQ8
67
PD1
A9
50
DQ24
DQ9
68
PD2
NC
51
69
PD3
RAS2*
NC
52
DQ25
DQ10
DQ26
70
PD4
53
71
NC
V
NC
54
72
SS
†: A11 is NC for 2K refresh module.
Fujitsu Microelectronics, Inc.
3
June 1996
Revision 1.0
FSA4UN324(2/4)-(60/70)J(G/S)-S
DC CHARACTERISTICS
(VCC = 5.0V±10%, VSS = 0V, TA = 0 to +70 °C)
60
70
Parameter
Symbol
Test Condition
Refresh
Unit
Note
Min.
Max.
640
Min.
Max.
560
4K
2K
-
-
-
-
I
RAS*, CAS* cycling; t = min.
Operating Current
mA
1, 2
CC1
RC
800
720
TTL Interface
RAS*, CAS* = V
-
-
16
8
-
-
16
8
mA
mA
IH
D
= High-Z
out
I
Standby current
CC2
CMOS Interface
RAS*, CAS* ≥ V - 0.2V
cc
D
= High-Z
out
4K
2K
4K
2K
4K
2K
-
640
800
640
800
560
640
80
-
560
720
560
720
480
560
80
CAS* = V ; RAS*, Address
RAS* -only Refresh
Current
IH
I
mA
mA
2
CC3
cycling @ t = min
RC
-
-
-
-
RAS*, CAS* cycling @
CAS*-before-RAS*
Refresh Current
I
CC4
t
= min.
RC
-
-
-
-
RAS* = V ; CAS*, Address
Fast Page Mode
Current
IL
I
mA
µA
µA
1, 3
CC5
cycling @ t = min
PC
-
-
I
0V ≤ Vin ≤ V +0.5V
Input Leakage Current
Output Leakage Current
-80
-80
LI
CC
0V ≤ Vout ≤ V
CC
I
-10
10
-10
10
LO
D
= Disable
out
V
High I = -5 mA
Output High Voltage
Output Low Voltage
2.4
-
-
2.4
-
-
V
V
OH
out
V
Low I = 4.5 mA
0.4
0.4
OL
out
Notes:
1. Values depend on load condition when the device is selected. Maximum Values are specified at the output open condition.
2. Address can be changed once or less while RAS* = V .
IL
3. Address can be changed once or less while CAS* = V
.
IH
CAPACITANCE
(TA =+25°C, VCC = 5.0V±10%=10V)
Parameter
Input Capacitance (Address)
Symbol
Max.
43
Unit
pF
Note
C
1
1
I1
C
Input Capacitance (RAS0*, RAS2*)
Input Capacitance (CAS0*~CAS3*)
Input Capacitance (WE*)
31
pF
I2
C
17
pF
1
I3
C
60
pF
1
I4
C
Input/Output Capacitance (DQ0~DQ31)
10
pF
1, 2
I/O
Notes:
1. Capacitance is measured with Boonton Meter or effective capacitance method.
2. CAS* = V to disable D
.
out
IH
Fujitsu Microelectronics, Inc.
4
June 1996
Revision 1.0
FSA4UN324(2/4)-(60/70)J(G/S)-S
AC CHARACTERISTICS
(TA = 0 to +70°C, VCC = 5.0V±10%V, VSS = 0V)
60
70
Parameter
Symbol
tRC
Unit
Notes
Min
110
-
Max
Min
130
-
Max
Random read/write cycle time
Access time from RAS*
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAC
tCAC
tAA
60
70
3, 4
3, 4, 5
3, 10
6
Access time from CAS*
-
15
-
20
Access time from column address
Output buffer turn-off time
Transition time (rise and fall)
RAS* precharge time
-
30
-
35
tOFF
tT
0
15
0
20
3
50
3
50
2
tRP
40
60
15
60
15
20
15
5
-
50
70
20
70
20
20
15
5
-
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS* pulse width
10000
10000
RAS* hold time
-
-
CAS* hold time
-
-
CAS* pulse width
10000
10000
RAS* to CAS* delay time
RAS* to column address delay time
CAS* to RAS* precharge time
Row address set-up time
Row address hold time
45
30
-
50
35
-
4
10
0
-
0
-
10
0
-
10
0
-
Column address set-up time
Column address hold time
Column address to RAS* lead time
Read command set-up time
Read command hold time to CAS*
Read command hold time to RAS*
Write command hold time
Write command pulse width
Write command to RAS* lead time
Write command to CAS* lead time
Data-in set-up time
-
-
10
30
0
-
15
35
0
-
-
-
-
-
0
-
0
-
8
0
-
0
-
10
10
15
15
0
-
15
15
20
20
0
-
-
-
tRWL
tCWL
tDS
-
-
-
-
-
-
9
9
tDH
Data-in hold time
10
-
-
15
-
-
ns
ms
ms
ns
(2048 cycles)
(4096 cycles)
32
64
-
32
64
-
tREF
Refresh period
-
-
tWCS
tCSR
tCHR
tRPC
tACP
tPC
Write command set-up time
0
0
7
1
1
CAS* set-up time (CBR refresh)
CAS* hold time (CBR refresh)
RAS* precharge to CAS* hold time
Access time from CAS* precharge
Fast Page mode cycle time
10
10
5
-
10
15
5
-
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
35
-
40
3, 11
12
40
10
60
-
45
10
70
-
tCP
CAS* precharge time (Fast Page)
RAS* pulse width (Fast Page)
-
-
tRASP
200000
200000
Fujitsu Microelectronics, Inc.
5
June 1996
Revision 1.0
FSA4UN324(2/4)-(60/70)J(G/S)-S
Notes:
1. An initial pulse of at least 200µs is required after power-up followed by a minimum of eight RAS* cycles before device operation
is achieved.
2.
V
(min.) and V (max.) are reference levels for measuring timing of input signals. Transition times are measured between V
IH IL IH
(min.) and V (max.) and are assumed to be 5 ns for all inputs.
IL
3. Measure with a load equivalent of 2 TTL loads and 100pF.
4. Operation within the t (max.) limit ensures that t (max.) limit can be met; t (max.) is specified as a reference point
RCD
RCD
RAC
only. If t
is greater than the specified t
(max) limit, then access time is controlled exclusively by t
.
RCD
RCD
CAC
5. Assumes that tRCD ≥ t
(max.).
RCD
6. This parameter defines the time at which the output achieves open circuit condition and is not referenced to V or V
.
OH
OL
7.
t
isanonrestrictiveoperatingparameter. Itisincludedinthedatasheetasanelectricalcharacteristiconly. IftWCS ≥ t
(min.)
WCS
WCS
the cycle is an early write cycle and the data-out pin will remain at high impedance for the duration of the cycle.
8. Either t or t must be satisfied for a read cycle.
RCH
RRH
9. These parameters are referenced to the CAS* leading edge in early write cycles.
10. Operation within the t (max.) limit ensures that t (max.) can be met. t (max.) is specified as a reference point only. If
RAD
RAC
RAD
t
is greater than the specified t
(max.) limit, then access time is controlled by t
.
RAD
RAD
AA
11. Access time is determined by the longer of t , t
, or t
.
AA CAC
ACP
12.
t
defines RAS* pulse width in fast page mode cycles.
RASC
Physical Dimensions
168-pin DIMM
0.2
max.
4.250
3.984
0.125
Dia.
1
72
0.05
0.25
0.08
3.750
± 0.002
0.050
+0.004/-0.003
0.25
(All dimensions are in inches with ±0.005" tolerance unless otherwise specified. Do not scale drawing)
Fujitsu Microelectronics, Inc.
6
June 1996
Revision 1.0
FSA4UN324(2/4)-(60/70)J(G/S)-S
All Rights Reserved.
Circuit diagrams using fujitsu products are included to illustrate typical semiconductor applications.
Information sufficient for construction purpose may not be shown.
The information contained in this document has been carefully checked and is believed to be reliable.
However, Fujitsu Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent
rights or trademarks claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu
Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
No part of the publication may be copied or reproduced in any form or by any means, or transferred
to any third party without prior written consent of Fujitsu Microelectronics, Inc.
7
June 1996
Revision 1.0
FSA4UN324(2/4)-(60/70)J(G/S)-S
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MP-DRAMM-DS-20310-6/96
8
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