MB1519-PF [FUJITSU]
PLL/Frequency Synthesis Circuit, BICMOS, PDSO20,;
| 型号： | MB1519-PF |
| 厂家： | 
FUJITSU |
| 描述： | PLL/Frequency Synthesis Circuit, BICMOS, PDSO20, 信息通信管理 光电二极管 |
| 文件： | 总16页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS04–21314–1E
DATA SHEET
MB1519 ASSP
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 600MHz PRESCALER
The Fujitsu MB1519 is a 600MHz dual serial input PLL (Phase Locked) frequency synthesizer
designed for cellular telephone and cordless telephone applications.
The MB1519 has two PLL circuits on a single chip: one for transmit and the other for reception.
Separate power supply pins are provided for the transmit and reception PLL circuits. Transmit
PLLcontains a low sensitivity charge pumpforeaseofmodulationandreceptionPLLcontainsa
high sensitivity charge pump for faster lock up time.
PLASTIC PACKAGE
DIP-20P-M02
600 MHz dual modulus prescalers are on chip and enables a pulse swallow function.
It operates supply voltage of 3.0V typ. and dissipates 11mA typ. of current realized through the
use of Fujitsu’s unique U-ESBIC Bi-CMOS technology.
•
•
•
•
•
High operating frequency: fin = 600MHz
Low power supply voltage: V = 2.7 to 5.5V
CC
PLASTIC PACKAGE
FPT-20P-M01
Low power supply current: I = 11mA typ, @3V.
CC
Wide operating temperature: T = –40 to 85°C
A
Two charge pumps
Low sensitivity charge pump for transmit
High sensitivity charge pump for reception
Plastic 20-pin dual in line package (Suffix: -P)
Plastic 20-pin flat package (Suffix: -PF)
PIN ASSIGNMENT
•
1
2
20
19
Data
Data
LE
GND
ABSOLUTE MAXIMUM RATINGS (see NOTE)
OSC
IN
OSC
Rating
Symbol
Value
Unit
OUT
3
4
5
6
18
17
16
15
fin
V
fin
1
2
V
CC
–0.5 to 7.0
V
V
CC2
CC1
fr
Power Supply Voltage
TOP
VIEW
fp
V
P
V
to 10.0
CC
LD
V
LD
1
2
7
8
9
14
13
12
Output Voltage
V
–0.5 to V +0.5
V
mA
°C
OUT
CC
V
P2
P1
Output Current
I
±10
D
D
OUT
O2
O1
BS
BS
2
1
10
11
Storage Temperature
T
STG
–55 to +125
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages
to this high impedance circuit.
NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Copyright 1994 by FUJITSU LIMIED
1
MB1519
MB1519 BLOCK DIAGRAM
7
9
10
6
15
14 12
11
8
13
1
Charge
Pump
Charge
Pump
fp
monitor
output
selector
Phase
Detector
Phase
Detector
16
TRANSMIT
SECTION
RECEP-
TION
SECTION
Binary
11-bit
Program-
mable
Binary
11-bit
Program-
mable
Counter
Counter
Reference
Counter
(512,
20-bit
latch
20-bit
latch
1024)
Binary
7-bit
Swallow
Counter
Binary
7-bit
Swallow
Counter
23-bit shift
register
Latch
Selec-
tor
CNT
Crystal
Oscillator
Prescaler
Prescaler
5
Schmitt
Circuit
Schmitt
Circuit
Schmitt
Circuit
4
2
3
17
18
19
20
2
MB1519
BLOCK DESCRIPTIONS
TRANSMIT/RECEPTION BLOCK
•
20-bit latch
•
Programmable divider consisting of:
Binary 7-bit swallow counter (Divide ratio: 0 to 127)
Binary 11-bit programmable counter (Divide ratio: 16 to 2047)
•
•
•
Phase detector with phase polarity change function
600MHz dual modulus prescaler (Divide ratio: 64/65)
Charge pump
COMMON BLOCK
•
23-bit shift register
•
Programmable divider consisting of:
Reference counter (Divide ratio: 512, 1024)
(Divide frequency = 25kHz, 12.5kHz (Crystal oscillator frequency = 12.8MHz)
•
•
•
•
•
Crystal oscillator
fp monitor output selector
Latch selector
Schmitt circuits
Analog switches
3
MB1519
PIN DESCRIPTIONS
Pin No. Pin Name
I/O
Descriptions
GND
OSC
Ground.
1
–
Oscillator input pin.
Oscillator output pin.
2
3
I
O
IN
OSC-
OUT
A crystal is connected between OSC pin and OSC
pin.
IN
OUT
fin
Prescaler input pin of transmit section.
The connection with VCO should be AC connection.
4
5
I
1
V
CC1
Power supply voltage input pin of transmit section.
–
When power is OFF, latched data of transmit section is cancelled.
Monitor pin for programmable reference divider output.
Lock detect signal output pin of transmit section.
fr
6
7
O
O
LD1
Condition
Lock
LD pin output level
H
L
Unlock
V
Power supply voltage input for charge pump and analog switch of transmit section.
8
9
–
P1
D
Charge pump output pin of transmit section.
O
O1
Phase characteristics of the phase detector can be reversed depending upon FC-bit setting.
BS1
BS2
Analog switch output pin of transmit section.
Usually this pin is high-impedance state. During SW is ON (LE = high), charge pump output is con-
nected to this pin.
10
11
12
O
O
O
Analog switch output pin of reception section.
Usually this pin is high-impedance state. During SW is ON (LE = high), charge pump output is con-
nected to this pin.
D
Charge pump output pin of reception section.
O2
Phase characteristics of the phase detector can be reversed depending upon FC-bit setting.
V
Power supply voltage input for charge pump and analog switch of reception section.
Lock detect signal output pin of reception section.
13
14
–
P2
LD2
O
Condition
Lock
LD pin output level
H
L
Unlock
fp
Monitor pin for programmable divider output.
15
O
This pin outputs divided frequency of transmit section or reception section depending upon FP bit set-
ting.
FP bit
Output
H
L
Transmit section (fp1)
Reception section (fp2)
4
MB1519
PIN DESCRIPTIONS (Continued)
Pin No. Pin Name
I/O
Descriptions
V
CC2
Power supply voltage input pin for reception section, programmable reference divider, shift register,
and crystal oscillator.
16
–
When power is OFF, latched data of reception section and reference counter is cancelled.
fin
Prescaler input pin of reception section.
The connection with VCO should be AC conneciton.
17
18
I
I
2
LE
Load enable input pin. This pin involves a schmitt trigger circuit.
When this pin is high, the data stored in the shift register is transferred into the latch depending on a
control data.
At this moment, charge pump output signal is output from BS pin since internal analog swith becomes
ON.
Data
Serial data input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
The stored data in the shift register is transferred to either transmit section or reception section
depending upon a control data.
19
I
Control bit data
The destination of data
Latch of transmit section
Latch of reception section
H
L
Clock
Clock input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
On rising edge of the clock shifts one bit of data into the shift register.
20
I
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(M x N) + A} x fOSC ÷ R (A < N)
fVCO:Output frequency of external voltage controlled ocillator (VCO)
M: Preset divide ratio of dual modulus prescaler (64)
N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127)
f
OSC:Reference oscillator frequency
R: Preset divide ratio of reference counter (512 or 1024)
5
MB1519
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serialdata is input usingthreepins, Datapin, Clockpin, andLEpin. Programmabledivideroftransmitsectionandprogrammabledividerofrecep-
tion section are controlled individually.
Serial data of binary data is input into Data pin.
On rising edge of clock shifts one bit of serial data into the shift register. When load enable signal is high, the data stored in the shift register is
transferred to either the latch of transmit section or the latch of reception section depending upon the control bit data setting.
Control data
Destination of serial data
Latch of transmit section
Latch of reception section
H
L
SHIFT REGISTER CONFIGURATION
Control bit
LSB
Data Flow
MSB
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
C
N
T
R
E
F
F
P
D
M
Y
F
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
N
C
10
11
N1 to N11 : Divide ratio of the programmable counter setting bit (16 to 2047)
A1 to A7
FC
: Divide ratio of the swallow counter setting bit (0 to 127)
: Phase control bit of the phase detector
: Dummy bit (sets to low)
DMY
FP
: Output of the programmable divider control bit (fp1 or fp2)
: Divide ratio of the reference counter setting bit (512 to 1024)
: Control bit
REF
CNT
SERIAL DATA INPUT TIMING
• t , t , t , t , t ≥ 1µs
1
2
3
4
5
Data
N11 = MSB
N10
N1
A7
REF = LSB
C: Control bit
Clock
LE
t
2
t
3
t
4
t
1
t
5
On rising edge of the clock shifts one bit of the data into the shift register.
6
MB1519
BINARY 11-BIT PROGRAMMABLE COUNTER DATA SETTING
Divide
Ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
16
17
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
2047
1
1
1
1
1
1
1
1
1
1
1
Note:Divide ratio less than 16 is prohibited.
Divide ratio (N) range = 16 to 2047
BINARY 7-BIT SWALLOW COUNTER DATA SETTING
Divide
Ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
127
1
1
1
1
1
1
1
Note:Divide ratio (A) range = 0 to 127
DMY : DUMMY BIT INPUT
This bit is set to low in operation.
REF : DIVIDE RATIO (R) OF THE REFERENCE COUNTER SETTING BIT
H = 512 (fr = 25.0 kHz)
L = 1024 (fr = 12.5 kHz)
FP : OUTPUT OF THE PROGRAMMABLE DIVIDER SETTING BIT
H = fp pin (15 pin) outputs programmable divider output frequency (fp1) of transmit section.
L = fp pin (15 pin) outputs programmable divider output frequency (fp2) of reception section.
FC : PHASE CONTROL BIT OF THE PHASE DETECTOR
Output of charge pump is selected by FC pin.
FC = H
FC = L
fr > fp
H
Z
L
Z
(1)
fr = fp
fr < fp
L
H
VCO Polarity
(1)
(2)
VCO Output
Frequency
Note:Z = High-impedance
Depending upon the VCO poratity, FC bit should be set.
(2)
VCO Input Voltage
7
MB1519
PHASE DETECTOR OUTPUT WAVEFORM
fr
fp
t
W
t
W
LD
(FC bit = High)
H
D
Z
Z
O
L
(FC bit = Low)
D
O
Note: • Phase difference detection range = –2π to +2π
• LD output becomes low when phase difference is t or more.
W
LD output becomes high when phase difference less than t is reperated 3 times or more.
W
(e. g. t = 625 to 1250 ns, foscin = 12.8 MHz)
W
• Spike apperance depends on the charge pump characteristics. The spike is output to diminish the dead band.
• When fr > fp or fr < fp, spike might not generate depending up the VCO characteristics.
8
MB1519
ANALOG SWITCH
ON/OFFoftheanalogswitchiscontrolledbythecombinationofthecontroldataandLEsignal. WhentheanalogswitchisON, BS1, BS2pinoutput
the charge pump output (D , D ). When analog switch is OFF, BS pin is set to high impedance.
01
02
Control data = H
Divide ratio of transmit section is set
Control data = L
Divide ratio of reception section is set
LE = H
ON
LE = L
OFF
LE = H
OFF
ON
LE = L
OFF
Analog switch of transmit section
Analog switch of reception section
OFF
OFF
OFF
When a analog switch is inserted between LP1 and LP2, faster lock up time is achieved to reduce LPF time constant during PLL channel switching.
D
O
CHARGE PUMP
LPF-1
LPF-2
V
CO
BISW
ANALOG SW
(CONTROL SIGNALE)
RECOMMENDED OPERATING CONDITIONS
Value
Unit
Note
Parameter
Symbol
Min
Typ
Max
5.5
V
CC
V
CC1
= V
2.7
3.0
V
CC2
Power Supply Voltage
V
P
V
CC
–
–
–
8.0
V
V
Input Voltage
V
GND
V
CC
IN
Operating Temperature
T
°C
–40
+85
A
HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover work-
benches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
9
MB1519
ELECTRICAL CHARACTERISTICS
Value
Typ
Unit
Parameter
Symbol
Condition
Min
Max
I
Reception section is active.
–
5.5
8.0
CC1
Power Supply Current
mA
Transmit/reception section
are active.
I
–
11.0
16.0
CC2
fin
10
–
–
12.8
–
600
20
0
fin
MHz
dBm
Operating Frequency
Input Sensitivity
OSC
f
IN
IN
OSC
V
= 2.7 to 4.0V, 50Ω
= 4.0 to 5.5V, 50Ω
–8
CC
fin
Vfin
V
CC
–4
–
–
–
4
–
–
OSC
V
V
PP
0.5
OSC
High–level Input Voltage
Low-level Input Voltage
V
IH
V
CC
x0.7+0.4
Except fin
V
and OSC
IN
V
V
CC
x0.3–0.4
–
–
–
IL
High–level Input Current
I
IH
1.0
–
Data,
Clock
LE
I
IL
–
–
–1.0
±50
–
–
Low-level Input Current
Input Current
µA
I
OSC
OSC
IN
High–level Output Voltage
Low-level Output Voltage
V
V
CC
= 3.0V
2.2
–
–
–
–
OH
Except D
and OSC
O
OUT
V
0.4
V
OL
V
V
= V to 8.0V
High–impedance Cutoff
Current
P
CC
I
µA
D
–
–
–
1.1
–
OFF
O
= GND to 8.0V
OOP
I
–1.0
OH
Except D
and OSC
O
OUT
I
1.0
–
–
–
–
OL
V
P
= 6V
I
–1
OH
Output Current
mA
D
D
O1
O2
V
V
= 3V
I
–
–
12
–3
–
–
CC
OL
= 6V
I
P
OH
V
CC
= 3V
I
–
–
6
–
–
OL
Analog Switch ON Resistance
R
Ω
25
ON
Notes:
:
fin = 600MHz, OSC = 12.8MHz, V
= V
= 3.0V. The remaining input pins are grounded and output pins are open.
IN
CC1
CC2
: AC coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected.
10
MB1519
TEST CIRCUIT (PRESCALER INPUT SENSITIVITY TEST)
V
P1
V
CC1
X’tal
0.1µF
0.1µF
1000pF
GND
P.G
8
5
3
2
1
4
50Ω
MB1519
16
13
15
18
19
20
17
P.G
1000pF
fp
50Ω
Oscilloscope
V
P2
V
CC2
0.1µF
0.1µF
11
MB1519
APPLICATION EXAMPLE
Output
VCO
LPF
Lock Detector
3V
6V
1000pF
0.1µF
0.1µF
From
Controller
20
19
18
LE
17
fin
16
15
fp
14
13
12
11
Clock
Data
V
CC2
LD
V
P2
D
BS
2
2
2
02
MB1519
GND
1
OSC
2
OSC
fin
4
V
fr
LD
7
V
D
BS
10
IN
OUT
1
CC1
1
P1
01
1
3
5
6
8
9
X’tal
3V
6V
C1
C2
0.1µF
0.1µF
Lock Detector
1000pF
Output
VCO
LPF
Note:
V
, V
: 8 V max.
: depends on the crystal oscillator.
Clock, Data, LE : involve the schmitt circuit.
P1
P2
C1, C2
When input pins are open, please insert the pull down/up resistor individually to prevent the oscillation.
: 12.8MHz
X’tal
12
MB1519
PACKAGE DIMENSIONS
20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-20P-M02)
15°MAX
+.008
–.012
+0.20
–0.30
.970
(24.64
)
INDEX-1
INDEX-2
.244±.010
(6.20±0.25)
.300(7.62)
TYP
.010±.002
(0.25±0.05)
+.012
–0
+.012
–0
.050
.034
+0.30
–0
+0.30
–0
(1.27
)
(0.86
)
.172(4.36)MAX
.118(3.00)MIN
.100(2.54)
TYP
.018±.003
(0.46±0.08)
.020(0.51)MIN
.050(1.27)
MAX
Dimensions in
inches (millimeters)
1991 FUJITSU LIMITED D20003S-3C
13
MB1519
PACKAGE DIMENSIONS (Continued)
20-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M01)
.089(2.25) MAX
+.010
–.008
+0.25
–0.20
(MOUNTING HEIGHT)
.500
(12.70
)
.002(0.05) MIN
(STAND OFF HEIGHT)
.307±.016
(7.80±0.40)
+.016
–.008
+0.40
–0.20
INDEX
.268
(6.80
)
.209±.012
(5.30±0.30)
.020±.008
(0.50±0.20)
.018±.004
+.002
+0.05
–0.02
.050(1.27)
TYP
.006
–.001
(0.15
)
Ø.005(0.13) M
(0.45±0.10)
Details of “A” part
.008(0.20)
“A”
.020(0.50)
.007(0.18)
MAX
.027(0.68)
.004(0.10)
MAX
.450(11.43) REF
Dimensions in
1991 FUJITSU LIMITED F20003S-5C
inches (millimeters)
14
MB1519
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical
semiconductor applications. Complete Information sufficient for construction purposes
is not necessarily given.
The Information contained in this document has been carefully checked and is believed
to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The Information contained in this document does not convey any license under the
copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications without notice.
No part of this publication may be copied or reproduced in any form or by any means, or
transferred to any third party without prior written consent of Fujitsu.
15
MB1519
For further information please contact:
Japan
FUJITSU LIMITED
Electronic Devices
International Operations Department
KAWASAKI PLANT, 1015 Kamikodanaka,
Nakahara–ku, Kawasaki–shi,
Kanagawa 211, Japan
Tel: (044) 754–3753
FAX: (044) 754–3332
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922–9000
FAX: (408) 432–9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10,
63303 Dreieich-Buchschlag,
Germany
Tel: (06103) 690-0
FAX: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
No.51 Bras Basah Road,
Plaza By The Park,
#06-04 to #06-07
Singapore 0718
Tel: 336-1600
FAX: 336-1609
FUJITSU LIMITED 1994
Printed in Japan DS04–21314–1E
16
相关型号：
©2020 ICPDF网 联系我们和版权申明