MB15E07SRPFT [FUJITSU]
Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler; 单串行输入锁相环频率合成片2.5 GHz的预分频器
| 型号： | MB15E07SRPFT |
| 厂家： | 
FUJITSU |
| 描述： | Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler |
| 文件： | 总25页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21378-2E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-chip 2.5 GHz Prescaler
MB15E07SR
■ DESCRIPTION
The Fujitsu MB15E07SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz
prescaler. The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling pulse swallowing
operation.
The supply voltage range is between 2.7 V and 5.0 V. A refined charge pump supplies well-balanced output
currents of 1.0 mA and 4.0 mA. The charge pump current is selectable by serial data.
The phase noise of MB15E07SR was drastically improved comparing wuth the former single PLL, MB15E07SL.
The data format of serial data and the pin assignments except for φP, φR and OSCout pins are same as the former
one, so it is easy to replace the former one.
MB15E07SR is ideally suited for the base station of GSM (Global System for Mobile Communications) and PCS.
■ FEATURES
• High frequency operation: 2.5 GHz Max
• Low power supply voltage: VCC = 2.7 V to 5.0 V
• Ultra Low power supply current:ICC = 8.0 mA Typ (VCC = Vp = 3.75 V, Ta = +25°C, in locking state)
• Direct power saving function:Power supply current in power saving mode
Typ 0.1 µA (VCC = Vp = 3.75 V, Ta = +25°C)
• Dual modulus prescaler: 32/33 or 64/65
(Continued)
■ PACKAGES
16-pin plastic TSSOP
16-pad plastic BCC
(LCC-16P-M06)
(FPT-16P-M07)
MB15E07SR
(Continued)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Software selectable charge pump current
• On-chip phase control for phase comparator
• Built-in digital locking detector circuit to detect PLL locking and unlocking
• Operating temperature: Ta = –40 °C to +85 °C
■ PIN ASSIGNMENTS
16-pin TSSOP
16-pad BCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OSCIN
N.C.
VP
N.C.
N.C.
LD/fout
N.C.
PS
OSCIN
N.C.
1
2
3
4
5
6
16 15 14
13
N.C.
VP
N.C.
LD/fout
N.C.
PS
VCC
DO
12
VCC
DO
Top view
Top view
11
10
GND
Xfin
fin
LE
LE
GND
Xfin
7
8
9
Data
Data
Clock
fin Clock
(LCC-16P-M06)
(FPT-16P-M07)
2
MB15E07SR
■ PIN DESCRIPTIONS
Pin no.
Pin
TSSOP BCC
I/O
Descriptions
name
1
2
3
4
16
1
OSCIN
N.C.
VP
I
Programmable reference divider input. Connection to a TCXO.
No connection.
–
–
–
2
Power supply voltage input for the charge pump.
Power supply voltage input.
3
VCC
Charge pump output.
Phase of the charge pump can be selected via programming of the FC bit.
5
4
DO
O
6
7
5
6
GND
Xfin
–
I
Ground.
Prescaler complementary input, which should be grounded via a capacitor.
Prescaler input.
8
9
7
8
fin
Clock
Data
LE
I
I
I
I
Connection to an external VCO should be done via AC coupling.
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
10
11
9
Load enable signal input. (Open is prohibited.)
When LE is set high, the data in the shift register is transferred to a latch
according to the control bit in the serial data.
10
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
12
13
14
11
12
13
PS
N.C.
I
PS = “H”; Normal mode
PS = “L”; Power saving mode
–
No connection.
Lock detect signal output (LD)/phase comparator monitoring output (fout).
The output signal is selected via programming of the LDS bit.
LDS = “H”; outputs fout (fr/fp monitoring output)
LD/fout
O
LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)
15
16
14
15
N.C.
N.C.
–
–
No connection.
No connection.
3
MB15E07SR
■ BLOCK DIAGRAM
fr
1
OSCIN(16)
SW FC LDS CS
4-bit latch
Binary 14-bit
Reference
oscillator circuit
Phase
comparator
reference couter
14-bit latch
Intermittent
mode control
(power save)
Lock
detector
12
(11)
PS
C
N
T
19-bit shift register
LD/fr/fp
selector
1-bit
control
latch
14
(13)
LD/fout
11
(10)
LE
3
(2)
V
P
Charge
pump
7-bit latch
11-bit latch
5
(4)
DO
Binary 7-bit
swallow
counter
Binary 11-bit
programmable
counter
10
(9)
Data
9
(8)
Clock
fp
7
Prescaler
32/33
Xfin
fin
(6)
8
(7)
64/65
SW
6
(5)
GND
4
CC (3)
V
O : TSSOP
( ) : BCC
4
MB15E07SR
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Condition
Unit
Remark
Min
–0.5
VCC
Max
5.5
VCC
VP
–
V
V
Power supply voltage
Input voltage
–
6.0
VI
–
–0.5
GND
GND
–55
VCC + 0.5
VCC
V
VO
Except Do
V
Output voltage
VO
Do
–
VP
V
Storage temperature
Tstg
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min
2.7
Typ
3.75
–
Max
5.0
VCC
VP
VI
V
V
Power supply voltage
VCC
5.5
Input voltage
GND
–40
–
VCC
+85
V
Operating temperature
Ta
–
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15E07SR
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.7 V to 5.0 V, Ta = –40°C to +85°C)
Value
Unit
Sym-
Parameter
bol
Condition
Min
Typ
8.0
0.1*2
–
Max
–
Power supply current*1
Power saving current
ICC*1
IPS
fIN = 2500 MHz, VCC = VP = 3.75 V
–
–
mA
PS = “L”
20
µA
fin
fIN
50 Ω system
100
3
2500 MHz
Operating frequency
OSCIN OSCIN
–
–
40
+2
+2
VCC
–
MHz
dBm
dBm
Vp-p
100 MHz to 300 MHz
–6
–
fin*3
Pfin
Input sensitivity
300 MHz to 2500 MHz
–15
0.5
–
OSCIN*3
VOSC
VIH
–
–
–
“H” level input voltage
“L” level input voltage
“H” level input current
“L” level input current
Data,
Clock,
LE, PS
VCC × 0.7
–
V
VIL
IIH*4
IIL*4
–
–
–
–
–
–
–
VCC × 0.3
+1.0
Data,
Clock,
LE, PS
–1.0
–1.0
µA
+1.0
“H” level input current
“L” level input current
“H” level output voltage
“L” level output voltage
“H” level output voltage
“L” level output voltage
IIH
–
0
–100
VCC – 0.4
–
–
–
–
–
–
–
+100
0
OSCIN
µA
IIL*4
VOH
VOL
–
VCC = VP = 3.75 V, IOH = –1 mA
VCC = VP = 3.75 V, IOL = 1 mA
–
LD/fout
V
0.4
–
VDOH VCC = VP = 3.75 V, IDOH = –0.5 mA VP – 0.4
Do
Do
V
VDOL
IOFF
IOH
IOL
VCC = VP = 3.75 V, IDOL = 0.5 mA
–
0.4
High impedance cutoff
current
VCC = VP = 3.75 V,
VOFF = 0.5 V to VP – 0.5 V
–
–
2.5
nA
mA
“H” level output current
“L” level output current
–
–
–
1.0
–
–
–
–1.0
–
LD/fout
CS bit = “1”
–4.0
–1.0
4.0
1.0
5
–
“H” level output current
“L” level output current
IDOH*4
VCC = 3.75 V,
CS bit = “0”
VP = 3.75 V,
–
–
Do
mA
VDO = VP/2
Ta = +25°C
CS bit = “1”
–
–
IDOL
CS bit = “0”
–
–
IDOL/IDOH IDOMT*5 VDO = VP/2
–
–
%
%
%
Charge pump current
rate
IDOVD*6
vs VDO
0.5 V ≤ VDO ≤ VP – 0.7 V
–
10
3
–
7
vs Ta IDOTA* – 40°C ≤ Ta ≤ +85°C
–
–
*1: Conditions; fosc = 13 MHz, Vosc = 1.2 VPP , Ta = +25°C, in locking state.
*2: VCC = VP = 3.75 V, fosc = 13 MHz, Vosc = 1.2 VPP , Ta = +25°C, in power saving mode
*3: AC coupling. 1000 pF capacitor is connected under the condition of minimum operating frequency.
*4: The symbol “–” (minus) means direction of current flow.
*5: VCC = VP = 3.0 V, Ta = +25°C
(||I3| – |I4||) / [(|I3| + |I4|) /2] × 100(%)
(Continued)
6
MB15E07SR
(Continued)
*6: VCC = VP = 3.0 V, Ta = +25°C [(||I2| – |I1||) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH)
*7: VCC = VP = 3.0 V, VDO = VP/2 (||IDO(+85°C)| – |IDO(–40°C)|| /2) / (|IDO(+85°C)| + |IDO(–40°C)| /2) × 100(%) (Applied to each IDOL, IDOH)
I1
I3
I2
IDOL
IDOH
I4
I2
I1
0.5
Vp/2
Vp − 0.7 V
Vp
Charge Pump Output Voltage (V)
7
MB15E07SR
■ FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
A
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
M
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
: Preset divide ratio of modulus prescaler (32 or 64)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken
high, stored data is latched according to the control bit data as follows:
Table 1. Control Bit
Control bit (CNT)
Destination of serial data
For the programmable reference divider
For the programmable divider
H
L
(1) Shift Register Configuration
Programmable Reference Counter
LSB
1
MSB
Data Flow
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
R
R
R
R
LDS
10 11 12 13 14 SW FC
CS
CNT
: Control bit
[Table 1]
R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]
SW
FC
LDS
CS
: Divide ratio setting bit for the prescaler (32/33 or 64/65)
: Phase control bit for the phase comparator
: LD/fOUT signal select bit
[Table 5]
[Table 8]
[Table 7]
[Table 6]
: Charge pump current select bit
Note: Start data input with MSB first.
8
MB15E07SR
Programmable Counter
MSB
LSB
1
Data Flow
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
C
N
T
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
N
10 11
CNT
: Control bit
[Table 1]
[Table 3]
[Table 4]
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
Note: Data input with MSB first.
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) R14 R13 R12 R11 R10 R9
R8
0
R7
0
R6
0
R5
0
R4
R3
0
R2
1
R1
1
3
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
4
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide ratio (N) N11 N10
N9
0
N8
0
N7
0
N6
0
N5
0
N4
N3
N2
N1
1
3
0
0
⋅
0
0
⋅
0
0
⋅
0
1
⋅
1
0
⋅
4
⋅
0
0
0
0
0
0
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
9
MB15E07SR
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide ratio (A) A7
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
0
1
0
0
⋅
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
Table 5. Prescaler Data Setting
SW
1
Prescaler divide ratio
32/33
64/65
0
Table 6. Charge Pump Current Setting
CS
1
Current value
4.0 mA
0
1.0 mA
Table 7. LD/fout Output Select Data Setting
LDS
LD/fOUT output signal
1
0
fout signal
LD signal
(2) Relation between the FC Input and Phase Characteristics
The FC bit changes the phase characteristics of the phase comparator. The internal charge pump output level
(DO) is reversed according to the FC bit. Also, the monitor pin (fOUT) output is controlled by the FC bit. The
relationship between the FC bit and DO is shown below.
Table 8. FC Bit Data Setting (LDS = “1”)
FC = 1
LD/fout
FC = 0
LD/fout
DO
H
DO
L
fr > fP
fr < fP
fr = fP
L
fout = fr
H
fout = fp
Z*
Z*
*: High impedance
10
MB15E07SR
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
When the LPF and VCO characteristics are similar
to (1), set FC bit high.
(1)
When the VCO characteristics are similar to (2),
set FC bit low.
VCO
Output
Frequency
PLL
LPF
VCO
(2)
LPF Output Voltage
Note : Give attention to the polarity for using active type LPF.
3. Power Saving Mode (Intermittent Mode Control Circuit)
Table 9. PS Pin Setting
PS pin
Status
H
L
Normal mode
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
11
MB15E07SR
Note: When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
The serial data input after the power supply becames stable, and then the power saving mode is released
after completed the data input.
OFF
ON
≥
tV 1 µs
VCC
Clock
Data
LE
≥
tPS 100 ns
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS: L → H) 100 ns later after setting serial data.
12
MB15E07SR
■ SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit Invalid data
∼
∼
∼
Data
MSB
LSB
Clock
t1
t2
t3
t6
t7
LE
∼
t4
t5
On the rising edge of the clock, one bit of data is transferred into the shift register.
Parameter Min
Typ
–
Max Unit
Parameter Min
Typ
–
Max Unit
t1
t2
t3
t4
20
20
30
30
–
–
–
–
ns
ns
ns
ns
t5
t6
t7
100
20
–
–
–
ns
ns
ns
–
–
–
100
–
–
Note: LE should be “L” when the data is transferred into the shift register.
13
MB15E07SR
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[FC = “H”]
DO
[FC = “L”]
DO
Notes : • Phase error detection range: –2 π to +2 π
• Pulses on Do signal during locked state are output to prevent dead zone.
• LD output becomes low when phase is tWU or more. LD output becomes high when phase
error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency.
tWU > 2/fosc (s) (e. g. tWU > 153.8 ns, fosc = 13 MHz)
tWU < 4/fosc (s) (e. g. tWL < 307.7 ns, fosc = 13 MHz)
• LD becomes high during the power saving mode (PS = “L”).
14
MB15E07SR
■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
1000 pF
0.1 µF
1000 pF
0.1 µF
1000 pF
S.G.
S.G.
N.C.
2
fin
8
Xfin GND DO
VCC
VP
OSCIN
50 Ω
50 Ω
7
6
5
4
3
1
9
10
11
12
13
14
15
16
Clock Data LE
N.C.
N.C.
PS
LD/fout
N.C.
VCC
Oscilloscope
Controller (setting divide ratio)
Note: TSSOP-16
15
MB15E07SR
■ TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
Input sensitivity - Input frequency
Ta = +25 °C
10
0
Catalog guaranteed range
−10
−20
−30
−40
−50
VCC = 2.7 V
VCC = 3.75 V
VCC = 5.0 V
VCC = 5.25 V
SPEC
0
500
1000
1500
2000
2500
3000
3500
4000
Input frequency fIN (MHz)
2. OSCIN Input Sensitivity
Input sensitivity - Input frequency
Ta = +25 °C
10
Catalog
guaranteed
range
0
−10
−20
−30
−40
−50
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.75 V
VCC = 5.0 V
SPEC
0
20
40
60
80
100
120
140
160
180
Input frequency fOSC (MHz)
16
MB15E07SR
3. Do output current
• 1.0 mA mode
IDO - VDO
10.00
Ta = + 25 °C
VCC = 3.75 V
Vp = 3.75 V
2.000
/div
−10.00
0.00
7.00
1.00/div
Charge pump output voltage VDO (V)
• 4.0 mA mode
IDO - VDO
10.00
Ta = + 25 °C
CC = 3.75 V
Vp = 3.75 V
V
2.000
/div
−10.00
7.00
0.00
1.00/div
Charge pump output voltage VDO (V)
17
MB15E07SR
4. fin input impedance
4
22.184 Ω 61.264 Ω 3.9002 nH
2 500.000 000 MHz
1
2
3
:
:
:
78.328
319.34
300 MHz
Ω
Ω
4
−
22.145
77.82
Ω
Ω
−
1 GHz
3
14.324
13.364
Ω
Ω
2 GHz
1
2
START
300.000 000 MHz
STOP 2 500.000 000 MHz
5. OSCIN input impedance
4
32.719 Ω −801.28 Ω 4.9656 pF
2 500.000 000 MHz
1 : 633.5 Ω
−9.258 kΩ
3 MHz
038.63 Ω
2 :
−3.0145 kΩ
10 MHz
083.94 Ω
3 :
−1.5534 kΩ
20 MHz
4
3
21
START
3.000 000 000 MHz
STOP 40.000 000 MHz
18
MB15E07SR
■ REFERENCE INFORMATION
Test Circuit
fVCO = 1730 MHz
KV = 42 MHz/V
fr = 200 kHz
VCC =VP = 3.75 V
VVCO = 3.3 V
Ta = +25 °C
CP : 4.0 mA mode
S.G.
OSCIN
fin
fOSC = 13 MHz
LPF
Do
LPF
27 kΩ
2.7 kΩ
1000 pF
120 pF
Spectrum
Analyzer
VCO
15000 pF
• PLL Reference Leakage
REF −10.0 dB
MKR∆ 200 kHz −80.39 dBc
NOISE/1 Hz
−116.53 dBc/Hz
DELTA MKR
200 kHz
CENTER 1.732004 GHz
SPAN 1.00 MHz
RBW 3 kHz
VBW 30 Hz
SWP 23 s
ATT 10 dB
• PLL Phase Noise
REF −10.0 dB
MKR∆ 1.00 kHz −81.66 dBc/Hz
VAVG 10
NOISE/1 Hz
−81.66 dBc/Hz
DELTA MKR
1.00 kHz
10
10
CENTER 1.73200392 GHz
RBW 30 Hz VBW 100 Hz
SPAN 10.00 kHz
SWP 2.0 s
ATT 10 dB
(Continued)
19
MB15E07SR
(Continued)
1805 MHz→ 1730 MHz within 1 kHz
1730 MHz→ 1805 MHz within 1 kHz
Hch→Lch
375 µs
Lch→Hch
390 µs
∆ Mkr x : 375.00233 µs
y : −75.0818 MHz
∆ Mkr x : 389.98165 µs
y : 74.8653 MHz
100.0050
MHz
100.0050
MHz
2.88
2.88
kHz/01v
kHz/01v
99.99500
MHz
99.99500
MHz
0 s
0 s
2.0000000 µs
2.0000000 µs
∆ Mkr x : 389.98165 µs
∆ Mkr x : 375.08233 µs
y : −75.0018 MHz
y : 74.8653 MHz
100.0050
MHz
250.0000
MHz
50.0000
MHz/01v
2.88
kHz/01v
0
Hz
99.99500
MHz
0 s
0 s
2.0000000 µs
2.0000000 µs
20
MB15E07SR
■ APPLICATION EXAMPLE
OUTPUT
VCO
LPF
Lock Det.
From
a controller
N.C.
16
N.C.
15
N.C.
13
LE
11
Data
10
Clock
9
LD/fout
14
PS
12
MB15E07SR
1
2
3
4
5
6
7
8
OSCIN
N.C.
VP
GND
fin
DO
Xfin
VCC
1000 pF
1000 pF
1000 pF
0.1 µF
0.1 µF
TCXO
VP: 5.5 V Max
Note : TSSOP-16
21
MB15E07SR
■ USAGE PRECAUTIONS
To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting device into or removing device from a socket.
-Protect leads with a conductive sheet when transporting a board-mounted device.
■ ORDERING INFORMATION
Part number
MB15E07SRPFT
MB15E07SRPV1
Package
Remarks
16-pin, Plastic TSSOP
(FPT-16P-M07)
16-pad, Plastic BCC
(LCC-16P-M06)
22
MB15E07SR
■ PACKAGE DIMENSIONS
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) .
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
16-pin plastic TSSOP
(FPT-16P-M07)
15.00±0.10(.197±.004)
*
0.17±0.05
(.007±.002)
16
9
2 4.40±0.10 6.40±0.20
*
(.173±.004) (.252±.008)
INDEX
Details of "A" part
1.05±0.05
(.041±.002)
(Mounting height)
1
8
LEAD No.
"A"
0.65(.026)
0.24±0.08
(.009±.003)
0~8˚
M
0.13(.005)
0.07 +–00..0073 .003 –+..000031
(0.50(.020))
(Stand off)
0.25(.010)
0.60±0.15
(.024±.006)
0.10(.004)
C
2003 FUJITSU LIMITED F16020S-c-3-3
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
(Continued)
23
MB15E07SR
(Continued)
16-pad plastic BCC
(LCC-16P-M06)
4.55±0.10
(.179±.004)
0.80(.031)MAX
Mounting height
3.40(.134)TYP
0.325±0.10
0.65(.026)
TYP
(.013±.004)
0.40±0.10
(.016±.004)
14
9
9
14
0.80(.031)
REF
INDEX AREA
3.40±0.10
(.134±.004)
2.45(.096)
TYP
1.15(.045)
REF
"B"
"A"
0.075±0.025
(.003±.001)
(Stand off)
1.725(.068)
REF
1
6
6
1
Details of "A" part
0.75±0.10
Details of "B" part
0.60±0.10
(.024±.004)
(.030±.004)
0.05(.002)
0.40±0.10
0.60±0.10
(.016±.004)
(.024±.004)
C
1999 FUJITSU LIMITED C16017S-1C-1
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
24
MB15E07SR
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0505
© 2005 FUJITSU LIMITED Printed in Japan
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