MB15F72UL_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS04-21367-1E

ASSP

Dual Serial Input

PLL Frequency Synthesizer

MB15F72UL

■ DESCRIPTION

The Fujitsu MB15F72UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300 MHz and

a 350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9 or a 16/17 for the 350 MHz

prescaler can be selected for the prescaler that enables pulse swallow operation.

The BiCMOS process is used, as a result a supply current is typically 2.5 mA at 2.7 V. The supply voltage range

is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA

selectable by serial data. The data format is the same as the previous one MB15F02SL, MB12F72SP. Fast locking

is achieved for adopting the new circuit.

The new package (BCC20) decreases a mount area of MB15F72UL more than 30% comparing with the former

BCC16 (for dual PLL) .

MB15F72UL is ideally suited for wireless mobile communications, such as CDMA.

■ FEATURES

• High frequency operation : RF synthesizer : 1300 MHz Max.

: IF synthesizer : 350 MHz Max.

• Low power supply voltage : V^CC= 2.4 to 3.6 V

• Ultra low power supply current : ICC = 2.5 mA Typ.

(VCC = Vp = 2.7 V, SWIF = SWRF = 0, Ta = +25 °C, in IF, RF locking state)

(Continued)

■ PACKAGES

20-pin plastic TSSOP

20-pad plastic BCC

(FPT-20P-M06)

(LCC-20P-M05)

MB15F72UL

(Continued)

• Direct power saving function : Power supply current in power saving mode

Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25 °C)

Max. 10 µA (VCC = Vp = 2.7 V)

• Software selectable charge pump current : 1.5 mA/6.0 mA Typ.

• Dual modulus prescaler : 1300 MHz prescaler (64/65 or 128/129 ) /350 MHz prescaler (8/9 or 16/17)

• 23 bit shift resister

• Serial input 14-bit programmable reference divider : R = 3 to 16,383

• Serial input programmable divider consisting of :

- Binary 7-bit swallow counter : 0 to 127

- Binary 11-bit programmable counter : 3 to 2,047

• On−chip phase control for phase comparator

• On−chip phase comparator for fast lock and low noise

• Built-in digital locking detector circuit to detect PLL locking and unlocking.

• Operating temperature : Ta = −40 °C to +85 °C

• Serial data format compatible with MB15F02SL

• Small package BCC20 (3.4 mm × 3.6 mm × 0.6 mm)

■ PIN ASSIGNMENTS

(TSSOP-20)

TOP VIEW

(BCC-20)

TOP VIEW

Data

Clock

OSCIN

GND

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

Clock

Data

OSCIN

GND

finIF

LE

finIF

1

2

3

4

5

6

20 19 18 17 16

finRF

XfinIF

GNDIF

VCCIF

PSIF

finRF

XfinIF

15

14

13

12

XfinRF

GNDRF

VCCRF

PSRF

VpRF

DoRF

XfinRF

GNDRF

VCCRF

GNDIF

VCCIF

PSIF

VpIF

10

9

PSRF

8

11

7

DoIF

LD/fout 10

DoRF

VpRF

LD/fout

(FPT-20P-M06)

(LCC-20P-M05)

2

MB15F72UL

■ PIN DESCRIPTION

Pin no.

Pin name I/O

Descriptions

TSSOP BCC

The programmable reference divider input. TCXO should be connected with an

AC coupling capacitor.

1

2

3

19

20

1

OSC^IN

GND

fin^IF

I

Ground for OSC input buffer and the shift register circuit.

Prescaler input pin for the IF-PLL.

Connection to an external VCO should be via AC coupling.

I

Prescaler complimentary input pin for the IF-PLL section.

This pin should be grounded via a capacitor.

4

5

6

2

3

4

Xfin^IF

GND^IF

V^CCIF

Ground for the IF-PLL section.

Power supply voltage input pin for the IF-PLL section (except for the charge

pump circuit) , the OSC input buffer and the shift register circuit.

Power saving mode control for the IF-PLL section. This pin must be set at “L”

when the power supply is started up. (Open is prohibited.)

7

5

PS^IF

I

PS^IF= “H” ; Normal mode / PS^IF= “L” ; Power saving mode

8

9

6

7

Vp^IF

D^OIF

Power supply voltage input pin for the IF-PLL charge pump.

Charge pump output pin for the IF-PLL section.

O

Lock detect signal output (LD) /phase comparator monitoring

output (fout) pins.The output signal is selected by LDS bit in the serial data.

LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal

10

8

LD/fout

11

12

9

D^ORF

Vp^RF

Charge pump output pin for the RF-PLL section.

10

Power supply voltage input pin for the RF-PLL charge pump.

Power saving mode control pin for the RF-PLL section. This pin must be set at

“L” when the power supply is started up. (Open is prohibited.)

PS^RF= “H” ; Normal mode / PS^RF= “L” ; Power saving mode

13

11

PS^RF

I

Power supply voltage input pin for the RF-PLL section (except for the charge

pump circuit)

14

15

16

12

13

14

V^CCRF

GND^RF

Xfin^RF

Ground for the RF-PLL section

Prescaler complimentary input pin for the RF-PLL section.

This pin should be grounded via a capacitor.

I

Prescaler input pin for the RF-PLL.

Connection to an external VCO should be via AC coupling.

17

18

15

16

fin^RF

LE

Load enable signal input pin (with the schmitt trigger circuit)

When LE is set “H”, data in the shift register is transferred to the

corresponding latch according to the control bit in the serial data.

I

Serial data input pin (with the schmitt trigger circuit)

Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,

RF-ref. counter, RF-prog. counter) according to the control bit in

the serial data.

19

20

17

18

Data

I

Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)

One bit of data is shifted into the shift register on a rising edge of the clock.

Clock

3

MB15F72UL

■ BLOCK DIAGRAM

VpIF

VCCIF GNDIF

(3)

(6)

(4)

6

5

8

Intermittent

mode control

(IF-PLL)

3 bit latch

PSIF 7

7 bit latch

Binary 7-bit

11 bit latch

Binary 11-bit

(5)

fpIF

Phase

comp.

(IF-PLL)

Charge

pump

(IF-PLL)

9

(7)

DoIF

Current

Switch

swallow counter programmable

(IF-PLL)

counter (IF-PLL)

finIF 3

(1)

XfinIF 4

(2)

Prescaler

(IF-PLL)

(8/9, 16/17

Lock Det.

(IF-PLL)

2 bit latch

14 bit latch

1 bit latch

LDIF

Binary 14-bit pro-

grammable ref.

counter(IF-PLL)

C/P setting

counter

T1 T2

frIF

Fast

lock

Tuning

OSCIN 1

(19)

Selector

AND

LDRF

frRF

LD

frIF

frRF

fpIF

fpRF

Binary 14-bit pro-

grammable ref.

counter (RF-PLL))

C/P setting

counter

T1 T2

10

(8) fout

LD/

OR

2 bit latch

14 bit latch

1 bit latch

(15)

finRF 17

Prescaler

(RF-PLL)

(64/65, 128/129)

Lock Det.

(RF-PLL)

XfinRF 16

(

14

)

Phase

comp.

(RF-PLL)

Charge

pump

(RF-PLL)

Binary 11-bit

programmable

counter (RF-PLL)

Binary 7-bit

swallow counter

(RF-PLL)

Current

Switch

11

(9)

DoRF

Intermittent

mode control

(RF-PLL)

PSRF 13

fpRF

3 bit latch

7 bit latch

11 bit latch

(11)

Schmitt

circuit

LE 18

(16)

Latch selector

(17)

Data 19

Schmitt

circuit

C

N

1

C

N

2

23-bit shift register

Schmitt

circuit

Clock 20

(18)

2 (20)

GND

(12) 14

15 (13)

GNDRF

12(10)

VpRF

VCCRF

O : TSSOP

( ) : BCC

4

MB15F72UL

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min.

−0.5

VCC

Max.

4.0

V^CC

Vp

V

Power supply voltage

Input voltage

4.0

V^I

−0.5

GND

−55

VCC + 0.5

VCC

V

LD/fout

VO

Output voltage

DoIF, DoRF

VDO

Tstg

Vp

V

Storage temperature

+125

°C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Remarks

Min.

2.4

Typ.

2.7

Max.

3.6

V^CC

Vp

V^I

V

VCCRF = VCCIF

Power supply voltage

VCC

2.7

3.6

Input voltage

GND

−40

VCC

+85

V

Operating temperature

Ta

°C

Note : • VCCRF, VpRF, VCCIF and VpIF must supply equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VpRF, VCCIF and VpIF to keep

them equal.

It is recommended that the non-use PLL is controlled by power saving function.

• Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry

has been improved in electrostatic protection, observe the following precautions when handling the device.

• When storing and transporting the device, put it in a conductive case.

• Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as

well as yourself. Use a conductive sheet on working bench.

• Before fitting the device into or removing it from the socket, turn the power supply off.

• When handling (such as transporting) the device mounted board, protect the leads with a conductive

sheet.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

5

MB15F72UL

■ ELECTRICAL CHARACTERISTICS

(V^CC= 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)

Value

Unit

Sym-

Parameter

bol

Condition

Min.

Typ.

Max.

fin^IF= 270 MHz

V^CCIF= Vp^IF= 2.7 V

*1

I^CCIF

0.6

1.0

1.7

mA

Power supply current

fin^RF= 910 MHz

V^CCRF= Vp^RF= 2.7 V

I^CCRF

1.0

1.5

2.5

I^PSIF

PS^IF= PS^RF= “L”

0.1^*2

10

µA

Power saving current

Operating frequency

I^PSRF

*3

fin^IF

fin^IFIF PLL

fin^RFRF PLL

f^OSC

50

100

3

350

1300

40

MHz

dBm

V^P− ^P

*3

fin^RF

OSC^IN

fin^IF

Pfin^IFIF PLL, 50 Ω system

Pfin^RFRF PLL, 50 Ω system

V^OSC

−15

0.5

+2

Input sensitivity

fin^RF

+2

OSC^IN

V^CC

Data,

LE,

Clock

“H” level input voltage

“L” level input voltage

V^IH

V^IL

Schmitt trigger input

0.7 V^CC+ 0.4

V

0.3 V^CC− 0.4

“H” level input voltage

“L” level input voltage

V^IH

V^IL

0.7 V^CC

V

PS^IF,

PS^RF

0.3 V^CC

Data,

LE,

Clock,

PS^IF,

PS^RF

*4

“H” level input current

“L” level input current

I^IH

−1.0

+1.0

µA

*4

I^IL

+1.0

“H” level input current

“L” level input current

I^IH

0

+100

µA

OSC^IN

*4

I^IL

−100

0

V^CC= Vp = 2.7 V,

I^OH= −1 mA

“H” level output voltage

“L” level output voltage

“H” level output voltage

V^OH

V^OL

V^CC− 0.4

Vp − 0.4

V

LD/fout

V^CC= Vp = 2.7 V, I^OL= 1 mA

0.4

V^CC= Vp = 2.7 V,

I^DOH= −0.5 mA

V^DOH

Do^IF,

Do^RF

V^CC= Vp = 2.7 V,

I^DOL= 0.5 mA

“L” level output voltage

V^DOL

I^OFF

0.4

V

High impedance

cutoff current

Do^IF,

Do^RF

V^CC= Vp = 2.7 V

V^OFF= 0.5 V to Vp − 0.5 V

2.5

nA

*4

“H” level output current

“L” level output current

I^OH

V^CC= Vp = 2.7 V

−1.0

mA

LD/fout

I^OL

1.0

(Continued)

6

MB15F72UL

(Continued)

(V^CC= 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)

Value

Unit

Parameter

Symbol

Condition

V^CC= Vp = 2.7 V,

V^DOH= Vp / 2,

Ta = +25 °C

Min.

Typ.

Max.

CS bit = “H”

CS bit = “L”

CS bit = “H”

CS bit = “L”

−8.2

−6.0

−4.1

mA

*8

“H” level output

current

Do^IF

Do^RF

*4

I^DOH

−2.2

4.1

−1.5

6.0

−0.8

8.2

V^CC= Vp = 2.7 V,

V^DOL= Vp / 2,

Ta = +25 °C

*8

“L” level output

current

Do^IF

I^DOL

Do^RF

0.8

1.5

2.2

*5

I^DOL/I^DOHI^DOMT

vs. V^DOI^DOVD

V^DO= Vp / 2

3

%

*6

*7

Charge pump

current rate

0.5 V ≤ V^DO≤ Vp − 0.5 V

10

−40 °C ≤ Ta ≤ +85 °C,

V^DO= Vp / 2

vs.Ta

I^DOTA

5

%

*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “L” in locking state.

*2 : V^CCIF= Vp^IF= V^CCRF= Vp^RF= 2.7 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode

PS^IF= PS^RF= GND, V^IH= V^CCV^IL= GND (at CLK, Data, LE)

*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min. operating frequency.

*4 : The symbol “–” (minus) means the direction of current flow.

*5 : V^CC= Vp = 2.7 V, Ta = +25 °C (||I³| − |I⁴||) / [ (|I³| + |I⁴|) / 2] × 100 (%)

*6 : V^CC= Vp = 2.7 V, Ta = +25°C [ (||I²| − |I¹||) / 2] / [ (|I¹| + |I²|) / 2] × 100 (%) (Applied to both l^DOLand l^DOH)

*7 : V^CC= Vp = 2.7 V, [||I^{DO (}⁺⁸⁵^°^C)| − |I^{DO (–40}^°^C)|| / 2] / [|I^{DO (}⁺⁸⁵^°^C)| + |I^{DO (–40}^°^C)| / 2] × 100 (%) (Applied to both I^DOLand I^DOH)

*8 : When Charge pump current is measured, set LDS = “L” , T1 = “L” and T2 = “H”.

I1

I3

I4

I2

IDOL

IDOH

I1

Vp/2

Vp − 0.5 Vp

0.5

Charge pump output voltage (V)

7

MB15F72UL

■ FUNCTIONAL DESCRIPTION

1. Pulse swallow function :

f^VCO= [ (P × N) + A] × f^OSC÷ R

f^VCO: Output frequency of external voltage controlled oscillator (VCO)

P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)

N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)

A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)

f^OSC: Reference oscillation frequency (OSC^INinput frequency)

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

2. Serial Data Input

The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/

RF-PLL sections, and programmable reference dividers of IF/RF-PLL sections are controlled individually.

The serial data of binary data is entered through Data pin.

On a rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load

enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit

data setting.

The programmable The programmable

The programmable

reference counter

for the IF-PLL

reference counter counter and the swallow counter and the swallow

for the RF-PLL

counter for the IF-PLL

counter for the RF-PLL

CN1

CN2

0

1

0

1

(1) Shift Register Configuration

• Programmable Reference Counter

(LSB)

Data Flow

(MSB)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS

X

CS

R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)

T1, T2 : LD/fout output setting bit.

CN1, CN2 : Control bit

: Charge pump current select bit

X

: Dummy bits (Set “0” or “1”)

Note : Data input with MSB first.

8

MB15F72UL

• Programmable Counter

(LSB)

Data Flow

(MSB)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SW^IF/FC^IF/

CN1 CN2 LDS

A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11

RF

A1 to A7

: Divide ratio setting bits for the swallow counter (0 to 127)

N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)

LDS

: LD/fout signal select bit

SW^IF/RF

FC^IF/RF

: Divide ratio setting bit for the prescaler (IF : SW^IF, RF : SW^RF)

: Phase control bit for the phase detector (IF : FC^IF, RF : FC^RF)

CN1, CN2 : Control bit

Note : Data input with MSB first.

(2) Data setting

• Binary 14-bit Programmable Reference Counter Data Setting (R1 to R14)

Divide ratio

R14 R13 R12 R11 R10 R9

R8

R7

R6

R5

R4

R3 R2

R1

3

0

1

4

•

0

•

0

•

0

•

0

•

0

•

0

•

0

•

0

•

0

•

0

•

0

•

1

•

0

•

0

•

16383

1

Note : Divide ratio less than 3 is prohibited.

• Binary 11-bit Programmable Counter Data Setting (N1 to N11)

Divide ratio

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

3

0

1

4

•

0

•

0

•

0

•

0

•

0

•

0

•

0

•

0

•

1

•

0

•

0

•

2047

1

Note : Divide ratio less than 3 is prohibited.

• Binary 7-bit Swallow Counter Data Setting (A1 to A7)

Divide ratio

A7

A6

A5

A4

A3

A2

A1

0

1

•

0

•

0

•

0

•

0

•

0

•

0

•

1

•

127

1

9

MB15F72UL

• Prescaler Data Setting (SW)

Divide ratio

SW = “1”

8/9

SW = “0”

16/17

Prescaler divide ratio IF-PLL

Prescaler divide ratio RF-PLL

64/65

128/129

• Charge Pump Current Setting (CS)

Current value

±6.0 mA

CS

1

±1.5 mA

0

• LD/fout output Selectable Bit Setting

LD/fout pin state

LD output

fr^IF

LDS

0

T1

0

T2

0

1

0

1

0

fr^RF

fp^IF

1

0

fout

outputs

1

0

1

fp^RF

1

• Phase Comparator Phase Switching Data Setting (FC^IF, FC^RF)

FC^IF= “1” FC^RF= “1” FC^IF= “0” FC^RF= “0”

Do^IFDo^RFDo^IFDo^RF

Phase comparator input

fr > fp

fr < fp

H

L

H

Z

fr = fp

Z

Z : High-impedance

Depending upon the VCO and LPF polarity, FC bit should be set.

High

(1)

(1) VCO polarity FC = “1”

(2) VCO polarity FC = “0”

VCO Output

Frequency

(2)

Max.

LPF Output voltage

Note : Give attention to the polarity for using active type LPF.

10

MB15F72UL

3. Power Saving Mode (Intermittent Mode Control Circuit)

Status

PS^IF/PS^RFpins

Normal mode

H

L

Power saving mode

The intermittent mode control circuit reduces the PLL power consumption.

By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption.

See the Electrical Characteristics chart for the specific value.

The phase detector output, Do, becomes high impedance.

For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.

Setting the PS pins high, releases the power saving mode, and the device works normally.

The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.

When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is

because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)

which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase

in lockup time.

To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error

signal from the phase detector when it returns to normal operation.

Notes • When power (V^CC) is first applied, the device must be in standby mode, PS^IF= PS^RF= Low, for at least 1 µs.

• PS pins must be set at “L” at Power-ON.

OFF

ON

VCC

tV

1 s

Clock

Data

LE

PSIF

tPS > 100 ns

PSRF

(1)

(2)

(3)

(1) PS^IF= PS^RF= “L” (power saving mode) at Power-ON

(2) Set serial data at least 1 µs after the power supply becomes stable (V^CC≥ 2.2 V) .

(3) Release power saving mode (PS^IF, PS^RF: “L” → “H”) at least 100 ns after setting serial

data.

11

MB15F72UL

4. Serial Data Input Timing

Frequency multiplier setting is performed through a serial interface using the Data pin, Clock pin, and LE pin.

Setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of

the LE signal. The following diagram shows the data input timing.

1st data

2nd data

Control bit Invalid data

LSB

Data

MSB

Clock

t1

t2

t3

t6

t7

LE

t4

t5

Parameter

Min. Typ. Max. Unit

Parameter

Min. Typ. Max. Unit

t¹

t²

t3

t4

20

30

ns

t⁵

t⁶

t7

100

20

ns

100

Note : LE should be “L” when the data is transferred into the shift register.

12

MB15F72UL

■ PHASE COMPARATOR OUTPUT WAVEFORM

frIF/frRF

fpIF/fpRF

tWU

tWL

LD

(FC bit = "1")

H

DoIF/DoRF

Z

L

(FC bit = "0")

H

Z

L

• LD Output Logic

IF-PLL section

RF-PLL section

Locking state/Power saving state

Unlocking state

LD output

Locking state/Power saving state

Unlocking state

H

L

Locking state/Power saving state

Unlocking state

Notes : • Phase error detection range = −2π to +2π

• Pulses on Do^IF/Do^RFsignals are output to prevent dead zone during locking state.

• LD output becomes low when phase error is t^WUor more.

• LD output becomes high when phase error is t^WLor less and continues to be so for three cycles

or more.

• t^WUand t^WLdepend on OSC^INinput frequency as follows.

t^WU≥ 2/fosc : e.g. t^WU≥ 156.3 ns when fosc = 12.8 MHz

t^WU≤ 4/fosc : e.g. t^WL≤ 312.5 ns when fosc = 12.8 MHz

13

MB15F72UL

■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSC^IN)

fout

Oscilloscope

1000 pF

VCCIF

VpIF

1000 pF

S.G.

50 Ω

0.1 µF

1000 pF

S.G.

LD/

fout

50 Ω

DoIF

9

VpIF

8

PSIF

VCCIF

GNDIF XfinIF

finIF

3

GND

2

OSCIN

10

7

6

5

4

1

11

12

13

14

15

16

17

18

LE

19

20

XfinRF

finRF

VpRF

PSRF

VCCRF

DoRF

GNDRF

Data

Clock

1000 pF

Controller

(divide ratio setting)

1000 pF

VpRF

VCCRF

S.G.

50 Ω

0.1 µF

Note : Terminal number shows that of TSSOP-20.

14

MB15F72UL

■ TYPICAL CHARACTERISTICS

1. fin input sensitivity

RF-PLL input sensitivity vs. Input frequency

10

0

SPEC

−10

−20

−30

−40

−50

VCC = 2.4 V

VCC = 2.7 V

VCC = 3.0 V

VCC = 3.6 V

SPEC

0

200

400

600

800

1000 1200 1400 1600 1800 2000 2200 2400

fin^RF(MHz)

IF-PLL input sensitivity vs. Input frequency

10

0

SPEC

−10

−20

−30

−40

−50

VCC = 2.4 V

VCC = 2.7 V

VCC = 3.0 V

VCC = 3.6 V

SPEC

0

100

200

300

400

500

600

700

800

fin^IF(MHz)

15

MB15F72UL

2. OSC^INinput sensitivity

10

Input sensitivity vs. Input frequency

SPEC

0

−10

−20

−30

−40

−50

−60

VCC = 2.4 V

VCC = 2.7 V

VCC = 3.0 V

VCC = 3.6 V

SPEC

0

50

100

150

200

250

300

Input frequency f^OSC(MHz)

16

MB15F72UL

3. RF-PLL Do output current

• 1.5 mA mode

IDO - VDO

10.0

VCC = Vp = 2.7 V

0

−10.0

0.0

1.0

2.0

3.0

Charge pump output voltage VDO (V)

• 6.0 mA mode

I^DO- VDO

10.0

VCC = Vp = 2.7 V

0

−10.0

0.0

1.0

2.0

3.0

Charge pump output voltage V^DO(V)

17

MB15F72UL

4. IF-PLL Do output current

• 1.5 mA mode

IDO − VDO

10.0

VCC = VP = 2.7 V

0

−10.0

0.0

1.0

2.0

3.0

Charge pump output voltage VDO (V)

• 6.0 mA mode

I^DO− VDO

10.0

VCC = Vp = 2.7 V

0

−10.0

0.0

1.0

2.0

3.0

Charge pump output voltage VDO (V)

18

MB15F72UL

5. fin input impedance

fin^RFinput impedance

4 : 8.252 Ω

−58.291 Ω

2.1 pF

1 300.140 000 MHz

1 : 332.28 Ω

−811.72 Ω

100 MHz

2 : 21.805 Ω

−182.83 Ω

500 MHz

3 : 9.6133 Ω

−83.98

Ω

1 GHz

1

2

4

3

STOP 1 500.000 000 MHz

START 100.000 000 MHz

fin^IFinput impedance

4 : 21.344 Ω

−181.55 Ω

1.7532 pF

500.000 000 MHz

1 : 939.62 Ω

−1.135 Ω

50 MHz

2 : 332.03 Ω

−802.69 Ω

100 MHz

3 : 45.953 Ω

−303.47 Ω

300 MHz

1

2

3

4

START 50.000 000 MHz

STOP 500.000 000 MHz

19

MB15F72UL

6. OSC^INinput impedance

OSC^INinput impedance

4 : 25.125 Ω

−686.59 Ω

2.318 pF

100.000 000 MHz

1 :10.781 kΩ

−13.358 kΩ

3 MHz

2 : 1.534 kΩ

−6.5593 kΩ

10 MHz

3 : 119.25 Ω

−1.7281 kΩ

40 MHz

2

4

1

3

START 3.000 000 MHz

STOP 100.000 000 MHz

20

MB15F72UL

■ REFERENCE INFORMATION

(for Lock-up Time, Phase Noise and Reference Leakage)

Test Circuit

fVCO = 720.5 MHz V^CC= 3.0 V

KV = 31

fr = 12.5 kHz

fOSC = 19.2 MHz CP : 6 mA mode

VVCO = 3.0 V

Ta = +25 °C

S.G.

OSCIN

fin

LPF

D^O

LPF

9.1 kΩ

Spectrum

Analyzer

VCO

2 kΩ

3300 pF

6800 pF

0.1 µF

• PLL Reference Leakage

ATTEN 10 dB

RL 0 dBm

VAVG 24

10 dBm

∆MKR −70.33 dB

12.7 kHz

∆MKR

12.7 kHz

−70.33 dB

D

S

CENTER 720.5000 MHz

SPAN 200.0 kHz

SWP 500 ms

RBW 1.0 kHz

VBW 1.0 kHz

• PLL Phase Noise

ATTEN 10 dB

RL 0 dBm

VAVG 34

10 dBm

∆MKR −50.16 dB

3.07 kHz

∆MKR

3.07 kHz

−50.16 dB

D

S

CENTER 720.5000 MHz

RBW 100 Hz VBW 100 Hz

SPAN 20.0 kHz

SWP 1.60 s

(Continued)

21

MB15F72UL

(Continued)

• PLL Lock Up time

720.5 MHz→757.5 MHz within ± 1 kHz

Lch→Hch 2.533 ms

757.5 MHz→720.5 MHz within ± 1 kHz

Hch→Lch 2.511 ms

757.504500 MHz

720.504250 MHz

757.500500 MHz

720.500250 MHz

757.496500 MHz

720.496250 MHz

−5.000 ms

0.00 s

5.000 ms

−5.000 ms

0.00 s

5.000 ms

1.000 ms/div

22

MB15F72UL

■ APPLICATION EXAMPLE

OUTPUT

VCO

2.7 V

LPF

2.7 V

1000 pF

from controller

1000 pF

0.1 µF

Clock

20

Data

19

LE

18

XfinRF GNDRF

16 15

PSRF

13

VpRF

DoRF

11

finRF

17

VCCRF

14

12

MB15F72UL

1

2

3

4

5

6

7

8

9

10

finIF

XfinIF

VCCIF

GNDIF

DoIF

LD/fout

PSIF

VpIF

GND

OSCIN

Lock Det.

2.7 V

1000 pF

0.1 µF

TCXO

OUTPUT

VCO

LPF

Notes : • Clock, Data, LE:Theschmitttriggercircuitisprovided(insertapull-downorpull-upregister

to prevent oscillation when open-circuit in the input) .

• The terminal number shows that of TSSOP-20.

23

MB15F72UL

■ USAGE PRECAUTIONS

(1) V^CCRF, Vp^RF, V^CCIFand Vp^IFmust be equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to V^CCRF, Vp^RF, V^CCIFand Vp^IFto

keep them equal. It is recommended that the non-use PLL is controlled by power saving function.

(2) To protect against damage by electrostatic discharge, note the following handling precautions :

-Store and transport devices in conductive containers.

-Use properly grounded workstations, tools, and equipment.

-Turn off power before inserting or removing this device into or from a socket.

-Protect leads with conductive sheet, when transporting a board mounted device.

■ ORDERING INFORMATION

Part number

MB15F72ULPFT

MB15F72ULPVA

Package

Remarks

20-pin plastic TSSOP

(FPT-20P-M06)

20-pad plastic BCC

(LCC-20P-M05)

24

MB15F72UL

■ PACKAGE DIMENSIONS

20-pin plastic TSSOP

(FPT-20P-M06)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

*

6.50±0.10(.256±.004)

0.17±0.05

(.007±.002)

20

11

*

4.40±0.10 6.40±0.20

(.173±.004) (.252±.008)

INDEX

Details of "A" part

1.05±0.05

(.041±.002)

(Mounting height)

1

10

LEAD No.

"A"

0.65(.026)

0.24±0.08

(.009±.003)

0~8°

M

0.13(.005)

0.07 ⁺^–0⁰^.^.⁰⁰⁷³.003 ^–⁺^.^.⁰⁰⁰⁰³¹

(0.50(.020))

(Stand off)

0.25(.010)

0.45/0.75

(.018/.030)

0.10(.004)

C

1999 FUJITSU LIMITED F20026S-2C-2

Dimensions in mm (inches)

(Continued)

25

MB15F72UL

(Continued)

20-pad plastic BCC

(LCC-20P-M05)

3.00(.118)TYP

0.25±0.10

3.60±0.10(.142±.004)

0.55±0.05

(.022±.002)

(Mounting height)

(.010±.004)

16

11

16

0.50(.020)

TYP

0.25±0.10

(.010±.004)

INDEX AREA

3.40±0.10

(.134±.004)

2.70(.106)

TYP

"D"

"A"

"B"

"C"

1

6

1

0.50(.020)

TYP

2.80(.110)REF

0.075±0.025

(.003±.001)

(Stand off)

0.05(.002)

Details of "A" part

Details of "B" part

Details of "C" part

Details of "D" part

0.50±0.10

0.30±0.10

(.020±.004)

(.012±.004)

C0.20(.008)

0.60±0.10

(.024±.004)

0.30±0.10

(.012±.004)

0.60±0.10

(.024±.004)

0.40±0.10

(.016±.004)

C

2001 FUJITSU LIMITED C20056S-c-2-1

Dimensions in mm (inches)

26

MB15F72UL

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Marketing Division

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Electronic Devices

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3353

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The products described in this document are designed, and

manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use,

and household use, but are not designed, developed and

manufactured as contemplated (1) for use accompanying fatal risks

or dangers that, unless extremely high safety is secured, could have

a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

http://www.fujitsu-fme.com/

Asia Pacific

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

http://www.fmal.fujitsu.com/

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0106

FUJITSU LIMITED Printed in Japan


型号：	MB15F72UL
厂家：	FUJITSU
描述：	Dual Serial Input PLL Frequency Synthesizer 双串行输入锁相环频率合成器
文件：	总27页 (文件大小：266K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB15F72UL [FUJITSU]

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