概述
数据手册MB15F83ULPVA 概述
Fractional-N PLL Frequency Synthesizer 小数N分频PLL频率合成器
MB15F83ULPVA 数据手册
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PDF下载FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21371-1E
ASSP
Fractional-N
PLL Frequency Synthesizer
MB15F83UL
■ DESCRIPTION
The Fujitsu MB15F83UL is Fractional-N Phase Locked Loop (PLL) frequency synthesizer with fast lock up function.
The Fractional-N PLL operating up to 2000 MHz and the integer PLL operating up to 600 MHz are integrated on
one chip.
The MB15F83UL is used, as charge pump which is well-balanced output current with 1.5 mA and 6 mA selectable
by serial data, direct power save control and digital lock detector. In addition, the MB15F83UL adopts a new
architecture to achieve fast lock.
The new package (Thin Bump Chip Carrier20) decreases a mount area of MB15F83UL more than 30% comparing
with the former B.C.C.16 (for dual PLL, MB15F03SL) .
The MB15F83UL is ideally suited for wireless mobile communications, such as GSM.
■ FEATURES
• High frequency operation
: RF synthesizer : 2000 MHz Max.
: IF synthesizer : 600 MHz Max.
: VCC = 2.7 V to 3.6 V
• Low power supply voltage
• Ultra Low power supply current : ICC = 5.8 mA Typ. (VCC = Vp = 3.0 V, Ta = +25 °C, SW = 0 in IF and RF locking
state)
(Continued)
■ PACKAGES
20-pin, Plastic TSSOP
20-pad, Plastic BCC
(FPT-20P-M06)
(LCC-20P-M05)
MB15F83UL
(Continued)
• Direct power saving function : Power supply current in power saving mode
Typ. 0.1 µA (VCC = Vp = 3.0 V, Ta = +25 °C) , Max. 10 µA (VCC = Vp = 3.0 V)
• Fractional function : modulo 13 fixed (implemented in RF-PLL)
• Dual modulus prescaler : 2000 MHz prescaler (16/17 fixed) /600 MHz prescaler (8/9 or 16/17)
• Serial input programmable reference divider : RF : 7 bit (3 to 127) /IF : 14 bit (3 to 16383)
• Serial input programmable divider consisting of :
RF section- Binary 4-bit swallow counter : 0 to 15
- Binary 10-bit programmable counter : 18 to 1,023
- Binary 4-bit fractional counter numerator : 0 to 15
IF section - Binary 4-bit swallow counter : 0 to 15
- Binary 11-bit programmable counter : 3 to 2,047
• On-chip phase comparator for fast lock and low noise
• Operating temperature : Ta = −40 °C to +85 °C
• Small package Bump Chip Carrier.0 (3.4 mm × 3.6 mm × 0.6 mm)
■ PIN ASSIGNMENTS
(BCC-20)
TOP VIEW
(TSSOP-20)
TOP VIEW
OSCIN Data
GND Clock
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
Clock
Data
OSCIN
GND
finIF
LE
finIF
1
2
3
4
5
20 19 18 17 16
LE
finRF
XfinIF
GNDIF
VCCIF
PSIF
XfinIF
15
14
13
12
finRF
XfinRF
GNDRF
VCCRF
PSRF
VpRF
DORF
GNDIF
VCCIF
XfinRF
GNDRF
VCCRF
PSIF
VpIF
VpIF
6
7
8
9
10 11
PSRF
DOIF
DOIF
LD/fout
DORF
LD/fout 10
VpRF
(LCC-20P-M05)
(FPT-20P-M06)
2
MB15F83UL
■ PIN DESCRIPTION
Pin no.
Pin
I/O
Descriptions
name
TSSOP BCC
The programmable reference divider input pin. TCXO should be connected with
an AC coupling capacitor.
1
2
3
19
20
1
OSCIN
GND
finIF
I
Ground pin for OSC input buffer and the shift register circuit.
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.
I
I
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
4
5
2
3
XfinIF
GNDIF
Ground pin for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section (except for the charge
pump circuit) , the shift register and the oscillator input buffer.
When power is OFF, latched data of IF-PLL is lost.
6
7
4
5
VCCIF
PSIF
Power saving mode control signal pin for the IF-PLL section. This pin must be set
at “L” when the power supply is started up. (Open is prohibited.)
PSIF = “H”; Normal mode / PSIF = “L”; Power saving mode
I
8
9
6
7
VpIF
Power supply voltage input pin for the IF-PLL charge pump.
Charge pump output pin for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
DoIF
O
O
O
Look detect signal output (LD) /phase comparator monitoring output (fout) pins.
The output signal is selected by an LDS bit in a serial data.
LDS bit = “H”; outputs fout signal / LDS bit = “L”; outputs LD signal
10
8
LD/fout
Charge pump output pin for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
11
12
9
DoRF
10
VpRF
Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control pin for the RF-PLL section. This pin must be set at
“L” when the power supply is started up. (Open is prohibited. )
PSRF = “H”; Normal mode / PSRF = “L”; Power saving mode
13
11
PSRF
I
Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit) .
14
15
16
12
13
14
VCCRF
GNDRF
XfinRF
Ground pin for the RF-PLL section.
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
I
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be AC coupling.
17
18
15
16
finRF
Load enable signal input pin (with the schmitt trigger circuit.)
On a rising edge of load enable, data in the shift register is transferred to the cor-
responding latch according to the control bit in a serial data.
LE
I
Serial data input pin (with the schmitt trigger circuit.)
19
20
17
18
Data
I
I
A data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the clock.
Clock
3
MB15F83UL
■ BLOCK DIAGRAM
VCCIF GNDIF
(4) (3)
VpIF
(6)
6
5
8
4-bit latch
11-bit latch
Power
7
(5)
PSIF
fpIF
Binary 11-bit
programmable
counter (IF-PLL)
saving
Binary 4-bit
Phase
Charge
IF-PLL
swallow counter
9
DoIF
comp.
pump
(IF-PLL)
(IF-PLL)
(IF-PLL)
(7)
(1)
3
4
Prescaler
(IF-PLL)
finIF
XfinIF
8/9, 16/17
(2)
14-bit latch
Lock
Binary 14-bit pro-
grammable ref.
counter (IF-PLL)
Det.
(IF-PLL)
6-bit latch
LDIF
Slector
OSCIN
1
LDIF
LDRF
frIF
(19)
10
LD/fout
(8)
Binary 7-bit pro-
grammable ref.
counter (RF-PLL)
frRF
fpIF
fpRF
OR
Lock
7-bit latch
5-bit latch
Det.
(RF-PLL)
frRF
MD2
frRF
Fractional
Counter
13
Selector
fpRF
OR
Phase
(15)
Prescaler
(RF-PLL)
16/17
comp.
finRF 17
MD1
(RF-PLL)
fpRF
16
XfinRF
(14)
Binary 10-bit
programmable
counter (RF-PLL)
F
1
F
2
F
3
F
4
Binary 4-bit
Charge
swallow counter
11
DoRF
pump
(RF-PLL)
Power
(9)
(RF-PLL)
13
PSRF
saving
4-bit latch
4-bit latch
10-bit latch
(11)
RF-PLL
Schmitt
circuit
18
LE
Latch selector
SC
(16)
(RF-PLL)
SC1
SC2
Schmitt
circuit
C
N
C
N
C
N
19
Data
23-bit shift
register
(17)
Schmitt
circuit
20
Clock
1
2
3
(18)
(20)
(12) 14
15 (13) 12 (10)
2
GND
VccRF GNDRF VpRF
O : TSSOP 20
( ) : BCC 20
4
MB15F83UL
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min.
−0.5
VCC
Max.
VCC
Vp
+4.0
+4.0
V
V
Power supply voltage
Input voltage
VI
−0.5
GND
GND
−55
VCC + 0.5
VCC
V
LD / fout
VO
V
Output voltage
Do
VDO
Tstg
Vp
V
Storage temperature
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
2.7
Typ.
3.0
Max.
3.6
VCC
Vp
VI
V
V
VCCRF = VCCIF
Power supply voltage
VCC
3.0
3.6
Input voltage
GND
−40
VCC
+85
V
Operating temperature
Ta
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15F83UL
*
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
finIF = 480 MHz, SWC = 0
VCCIF = VpIF = 3.0 V
*1
ICCIF
1.0
1.6
2.3
mA
mA
Power supply current
finRF = 2000 MHz
VCCRF = VpRF = 3.0 V
*1
ICCRF
2.8
4.2
5.8
IPSIF
IPSRF
finIF
PS = “L”
PS = “L”
IF PLL
0.1*2
0.1*2
10
10
µA
Power saving current
Operating frequency
µA
*3
finIF
100
400
3
600
2000
40
MHz
MHz
MHz
dBm
dBm
Vp-p
*3
finRF
finRF
fOSC
RF PLL
OSCIN
finIF
PfinIF
IF PLL, 50 Ω system
−15
−15
0.5
+2
Input sensitivity
finRF
PfinRF RF PLL, 50 Ω system
+2
OSCIN
VOSC
VCC
0.7 VCC
+ 0.4
“H” level input voltage
“L” level input voltage
VIH
VIL
Schmitt triger input
Schmitt triger input
Data,
Clock,
LE
V
V
0.3 VCC
− 0.4
“H” level input voltage
“L” level input voltage
VIH
0.7 VCC
PSIF
PSRF
VIL
0.3 VCC
Data,
Clock,
LE,
PSIF,
PSRF
*4
“H” level input current
IIH
−1.0
−1.0
+1.0
µA
*4
“L” level input current
IIL
+1.0
“H” level input current
“L” level input current
“H” level output voltage
“L” level output voltage
“H” level output voltage
“L” level output voltage
IIH
0
+100
OSCIN
µA
*4
IIL
−100
0
VOH
VOL
VCC = Vp = 3.0 V, IOH = −1 mA
VCC = Vp = 3.0 V, IOL = 1 mA
VCC − 0.4
LD/
fout
V
0.4
VDOH
VDOL
VCC = Vp = 3.0 V, IDOH = −0.5 mA Vp − 0.4
VCC = Vp = 3.0 V, IDOL = 0.5 mA
DoIF
DoRF
V
0.4
2.5
High impedance
cutoff current
DoIF
DoRF
VCC = Vp = 3.0 V
VOFF = 0.5 V to Vp − 0.5 V
IOFF
nA
mA
*4
“H” level output current
“L” level output current
IOH
VCC = Vp = 3.0 V
−1.0
LD/
fout
IOL
VCC = Vp = 3.0 V
1.0
(Continued)
6
MB15F83UL
(Continued)
(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)
Value
Unit
Parameter
Symbol
Condition
VCC = Vp = 3.0 V
VDOH = Vp / 2
Ta = +25 °C
Min.
Typ.
Max.
CS bit = “H”
CS bit = “L”
CS bit = “H”
CS bit = “L”
−8.2
−6.0
−4.1
mA
mA
mA
mA
“H” level output
current
*4
IDOH
−2.2
4.1
−1.5
6.0
−0.8
8.2
DoIF
DoRF
VCC = Vp = 3.0 V
VDOL = Vp / 2
Ta = +25 °C
“L” level output
current
IDOL
0.8
1.5
2.2
*5
IDOL/IDOH IDOMT
VDO = Vp / 2
3
%
%
*6
*7
Charge pump
current rate
vs VDO
IDOVD
0.5 V ≤ VDO ≤ Vp − 0.5 V
10
−40 °C ≤ Ta ≤ +85 °C,
VDO = Vp / 2
vs Ta
IDOTA
5
%
*1 : Conditions ; fosc = 13 MHz, Ta = +25 °C in locking state.
*2 : VCCIF = VpIF = VCCRF = VpRF = 3.0 V, fosc = 13 MHz, Ta = +25 °C, in power saving mode.
*3 : AC coupling. 1000 pF capacitor is connected.
*4 : The symbol “–” (minus) means direction of current flow.
*5 : VCC = Vp = 3.0 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%)
*6 : VCC = Vp = 3.0 V, Ta = +25 °C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to each lDOL and lDOH)
*7 : VCC = Vp = 3.0 V, Ta = +25 °C[ (||IDO (85 °C) | − |IDO (–40 °C) ||) / 2] / [ (|IDO (85 °C) | + |IDO (–40 °C) |) / 2] × 100 (%) (Applied
to each IDOL and IDOH)
I2
I3
I1
IDOL
IDOH
I1
I4
I2
0.5
Vp/2
Vp − 0.5
Vp
output voltage (V)
7
MB15F83UL
■ FUNCTIONAL DESCRIPTION
1. Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections and programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary code is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
The programmable
counter and the
swallow counter for the
IF-PLL
The prgrammable
counter and the
swallow counter for
the RF-PLL
The programmable
reference counter for
the IF-PLL
The programmable
reference counter for
the RF-PLL
CN1
CN2
CN3
0
0
0
1
0
0
0
1
0
1
1
0
Note : (CN3 = 1 is pohibited)
(1) Serial data format
LSB
Direction of data shift
MSB
1
0
1
0
1
2
0
0
1
1
3
0
0
0
0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 LDS T1 T2 SWC FCC CSC
AC1 AC2 AC3 AC4 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11
RF1 RF2 RF3 RF4 RF5 RF6 RF7
AF1 AF2 AF3 AF4 NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF8 NF9 NF10 F1 F2 F3 F4
0
0
0
X
X
0
0
0
0
0
0
0
0
SC1 SC2
1
FCF CSF
0
0
Control bit (CN3)
Control bit (CN2)
Control bit (CN1)
RC1 to RC14
AC1 to AC4
NC1 to NC11
: Divide ratio setting bits for the reference counter of the IF (3 to 16383)
: Divide ratio setting bits for the swallow counter of the IF (0 to 15, A < N)
: Divide ratio setting bits for the programmable counter of the IF (3 to 2047)
LDS, T1, T2 : Select bits for the lock detect output or a monitoring phase comparison frequency
SWC
: Divide ratio setting for the prescaler of the IF
FCC
: Phase control bit for the phase detector of the IF
: Charge pump current select bit of the IF
CSC
RF1 to RF7
AF1 to AF4
NF1 to NF10
F1 to F4
SC1, SC2
FCF
: Divide ratio setting bits for the reference counter of the RF (3 to 127)
: Divide ratio setting bits for the swallow counter of the RF (0 to 15, A < N − 2)
: Divide ratio setting bits for the programmable counter of the RF (18 to 1023)
: Fractional-N increment setting bit for the fractional accumulator (0 to 15, F < Q)
: Spurious cancel set bit of the RF.
: Phase control bit for the phase detector of the RF.
: Charge pump current select bit of the RF
CSF
X
: Dummy bit (Set “0” or “1”)
Note: Data input with MSB first.
8
MB15F83UL
(2) Data Setting
• RF synthesizer Data Setting (Fractional-N)
The divide ratio can be calculated using the following equation :
fVCORF = NTOTAL × fosc÷R
NTOTAL = P × N + A + F / Q
←
(A < N − 2, F < Q)
fVCORF
NTOTAL
fosc
R
: Output frequency of external voltage controlled oscillator (VCO)
: Total division ratio from prescaler input to the phase detector input
: Output frequency of the reference frequency oscillator
: Preset divide ratio of binary 7 bit reference counter (3 to 127)
: Preset divide ratio of modulus prescaler (16 fixed)
P
N
: Preset divide ratio of binary 10 bit programmable counter (18 to 1023)
: Preset divide ratio of binary 4 bit swallow counter (0 to 15)
: A numerator of fractional-N (0 to 15)
A
F
Q
: A denominator of fractional-N, modulo 13
• Binary 7-bit Programmable Reference Counter Data Setting (RF1 to RF7)
Divide ratio (R)
RF7
0
RF6
0
RF5
0
RF4
0
RF3
0
RF2
1
RF1
1
3
4
0
0
0
0
1
0
0
52
0
1
1
1
1
1
0
1
1
1
0
1
0
1
127
Note : Divide ratio less than 3 is prohibited.
• Fractional-N incremant of the fractional accumulator Data Setting (F1 to F4)
Setting value(F)
F4
0
F3
0
F2
0
F1
0
0
1
2
0
0
0
1
0
0
1
0
15
1
1
1
1
Note : F < Q
9
MB15F83UL
• Binary 10-bit Programable Counter Data Setting (NF1 to NF10)
Divide ratio (N)
NF10
0
NF9
0
NF8
0
NF7
0
NF6
0
NF5
1
NF4
0
NF3
0
NF2
1
NF1
0
18
19
0
0
0
0
0
1
0
0
1
1
32
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1023
Note : Divide ratio less than 18 is prohibited.
• Binary 4-bit Swallow Counter Data Setting (AF1 to AF4)
Divide ratio (A)
AF4
0
AF3
0
AF2
0
AF1
0
1
2
0
1
0
0
0
0
0
0
1
15
1
1
1
1
Note : A < N − 2
• Spurious cancel Bit Setting
Spurious cancel amount
SC1
SC2
Large
Midium
Small
0
0
1
0
1
0
Note : The bits set how much the amount of spurious cancel.
If the Large is selected, a spurious is tended to become small.
• Phase Comparator Phase Switching Data Setting
FCF = High
FCF = Low
DO
H
Z
DO
L
fr > fp
fr = fp
Z
fr < fp
L
H
2
VCO polarity
1
Notes : • Z = High-Z
• Depending upon the VCO and LPF polarity, FC bit should be set.
• Charge pump current select Bit Setting
CSF
1
Current value
± 6.0 mA
0
± 1.5 mA
10
MB15F83UL
• IF synthesizer Data Setting (Integer)
The divide ratio can be calculated using the following equation :
fVCOIF = [ (P × N) + A] × fosc÷R (A < N)
fVCOIF
P
: Output frequency of external voltage controlled oscillator (VCO)
: Preset divide ratio of modulus prescaler (8 or 16)
N
: Preset divide ratio of binary 11 bit programmable counter (3 to 2047)
: Preset divide ratio of binary 4 bit swallow counter (0 to 15)
: Output frequency of the reference frequency oscillator
A
fosc
R
: Preset divide ratio of binary 14 bit reference counter (3 to 16383)
• Binary 14-bit Programmable Reference Counter Data Setting (RC1 to RC14)
Divide ratio
RC14
RC13
RC12
RC11
RC10
RC9
RC8
RC7
RC6
RC5
RC4
RC3
RC2
RC1
(R)
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
4
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
• Binary 11-bit Programmable Counter Data Setting (NC1 to NC11)
Divide ratio (N) NC11 NC10
NC9
0
NC8
0
NC7
0
NC6
0
NC5
0
NC4
0
NC3
NC2
NC1
3
4
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
2047
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
• Binary 4-bit Swallow Counter Data Setting (AC1 to AC4)
Divide ratio (A) AC4
AC3
0
AC2
0
AC1
0
0
1
2
0
0
0
0
0
1
0
1
0
15
1
1
1
1
Note : A < N
• Prescaler Data Setting (SWC)
SWC
Prescaler divide ratio
1
0
8/9
16/17
11
MB15F83UL
• Phase Comparator Phase Switching Data Setting
FCC = High
FCC = Low
DO
H
Z
DO
L
fr > fp
fr = fp
fr < fp
Z
L
H
Notes : • Z = High-Z
• Depending upon the VCO and LPF polarity, FC bit should be set.
•Charge pump current select Data Setting (CSC)
CSC
1
Do current
± 6.0 mA
± 1.5 mA
0
• Common setting
• LD/fout Output Select Data Setting
LD/fout
LDS
T1
T2
LD output
0
1
1
1
1
frIF
0
1
0
1
0
0
1
1
frRF
fpIF
fout
output
fpRF
• FC bit Setting
When designing a synthesizer, the FC bit setting depends on the VCO and LPF characteristics.
When the LPF and VCO characteristics are similar to (1) ,
set FC bit “H”.
When the VCO characteristics are similar to (2) ,
set FC bit “L”.
High
(1)
VCO output
frequency
(2)
LPF output voltage
Max.
12
MB15F83UL
2. Power Saving Mode (Intermittent Mode Control)
• PS Pin Setting
PS pin
Status
H
L
Normal mode
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters the power saving mode, reducing the current consumption.
See “■ ELECTRICAL CHARACTERISTICS” for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is shown in “■PHASE DETECTOR OUTPUT WAVEFORM the LD Output
Logic table.
Setting the PS pin high releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth start-up when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes: •When power (VCC) is first applied, the device must be in standby mode and PS = Low, for at least 1 µs.
•PS pin must be set “L” for Power ON.
OFF
ON
VCC
tV ≥ 1 µs
Clock
Data
LE
PS
tPS ≥ 100 ns
(2)
(1)
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 µs after power supply remains stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PS : L → H) 100 ns after setting serial data.
13
MB15F83UL
3. Serial Data Input Timing
1st data
2nd data
Control bit Invalid data
LSB
Data
MSB
Clock
LE
t4
t3
t1
t2
t5
t6
t7
On the rising edge of the clock, one bit of data is transferred into shift register.
Parameter Min.
Typ.
Max.
Unit
ns
Parameter
Min. Typ. Max.
Unit
ns
t1
t2
t3
t4
20
20
30
30
t5
t6
t7
100
20
ns
ns
ns
100
ns
ns
Note : LE should be “L” when the data is transferred into the shift register.
14
MB15F83UL
■ PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
H
DOIF/RF
Z
L
(FC bit = Low)
H
DOIF/RF
Z
L
LD Output Logic Table
IF-PLL section
RF-PLL section
LD output
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
Locking state/Power saving state
Unlocking state
H
L
L
L
Locking state/Power saving state
Unlocking state
Unlocking state
Notes: • Phase error detection range = −2 π to +2 π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency as follows.
tWU ≥ 2/fosc [s] : i.e. tWU ≥ 153.8 ns when fosc = 13.0 MHz
tWU ≤ 4/fosc [s] : i.e. tWL ≤ 307.7 ns when fosc = 13.0 MHz
15
MB15F83UL
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout
Oscilloscope
VpIF
VCCIF
0.1 µF
0.1 µF
1000 pF
1000 pF
P.G
1000 pF
S.G
50 Ω
LD/fout DOIF VpIF PSIF VCCIF GNDIF XfinIF finIF GND OSCIN
50 Ω
10
9
8
7
6
5
4
3
2
1
MB15F83UL
11
12
13
14
15
16
17
18
19
20
DORF VpRF PSRF VCCRFGNDRFXfinRF finRF LE Data Clock
1000 pF
S.G
1000 pF
Controller (divide
ratio setting)
VpRF
VCCRF
50 Ω
0.1 µF
0.1 µF
Note : TSSOP-20
16
MB15F83UL
■ TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF-PLL input sensitivity vs. Input frequency
Ta = + 25 °C
10
0
2.7 V
3.0 V
SPEC
−10
−20
−30
−40
−50
3.6 V
SPEC
3.3 V
0
500
1000
1500
2000
2500
finRF (MHz)
IF-PLL input sensitivity vs. Input frequency
Ta = + 25 °C
10
0
−10
−20
−30
−40
−50
2.7 V
3.0 V
SPEC
3.3 V
3.6 V
0
500
1000
1500
2000
finIF (MHz)
17
MB15F83UL
2. OSCIN input sensitivity
Input sensitivity vs. Input frequency
Ta = + 25 °C
10
SPEC
0
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
−10
−20
−30
−40
−50
−60
0
50
100
150
200
250
300
Input frequency fOSC (MHz)
18
MB15F83UL
3. RF-PLL Do output current
• 1.5 mA mode
IDO − VDO
20
0
−20
0
1
2
3
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO − VDO
20
0
−20
0
1
2
3
Charge pump output voltage VDO (V)
19
MB15F83UL
4. IF-PLL Do output current
• 1.5 mA mode
IDO − VDO
10.0
VCC = Vp = 2.7 V
0
−10.0
0.0
2.0
1.0
3.0
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO − VDO
10.0
VCC = Vp = 2.7 V
0
−10.0
2.0
3.0
1.0
0.0
Charge pump output voltage VDO (V)
20
MB15F83UL
5. fin input impedance
finR input impedance
1.1765 pF
1 : 45.859 Ω
−188.77 Ω
1 GHz
2 : 25.48 Ω
−103.67 Ω
1.7 GHz
3 : 22.152 Ω
−83.391 Ω
2 GHz
1
2
3
START 1 000.000 000 MHz
STOP 2 600.000 000 MHz
finIF input impedance
4 : 9.3437 Ω
−75.625 Ω
2.1045 pF
1 000.000 000 MHz
1 : 325.78 Ω
−732.22 Ω
100 MHz
2 : 21.516 Ω
−170.72 Ω
500 MHz
3 : 12.422 Ω
−108.38 Ω
750 MHz
1
2
4
3
START .030 000 MHz
STOP 1 000.000 000 MHz
21
MB15F83UL
6. OSCIN input impedance
OSCIN input impedance
4 : 092.56 Ω
-1.3177 kΩ
2.4157 pF
50.000 000 MHz
1 : 28.625 Ω
−667.75 Ω
100 MHz
2 : 2.1273 kΩ
−5.9445 kΩ
10 MHz
3 : 2.1273 kΩ
−5.9445 kΩ
4
10 MHz
3
32
1
START .030 000 MHz
STOP 100.000 000 MHz
22
MB15F83UL
■ REFERENCE INFORMATION
(for Lock-up Time, Phase Noise and Reference Leakage)
fVCO = 1733 MHz
VCC = 3.0 V
Test Circuit
OSC IN
KV = 44 MHz/V
fr = 200 kHz
fOSC = 13 MHz
LPF
VVCO = 3.5 V
Ta = +25 °C
CP : 6 mA mode
QM = 13
S.G.
LPF
DO
fin
10 kΩ
Spectrum
Analyzer
VCO
3.0 kΩ
82 pF
390 pF
3900 pF
• PLL Reference Leakage
ATTEN 10 dB
RL 0 dBm
VAVG 100
∆MKR −69.00 dB
200 kHz
10 dB/
∆MKR
200 kHz
−69.00 dB
D
CENTER 1.733000 GHz
RBW 10 kHz
SPAN 1.000 MHz
SWP 50.0 ms
VBW 10 kHz
• PLL Phase Noise
ATTEN 10 dB
RL 0 dBm
VAVG 24
10 dB/
∆MKR −63.17 dB
1.00 kHz
∆MKR
1.00 kHz
−63.17 dB
D
CENTER 1.73299933 GHz
RBW 100 Hz VBW 100 Hz
SPAN 10.00 kHz
SWP 802 ms
23
MB15F83UL
• PLL Lock Up time
1733 MHz→1803 MHz within ± 1 kHz
• PLL Lock Up time
1803 MHz→1733 MHz within ± 1 kHz
Lch→Hch
189 µs
Hch→Lch
167 µs
1.733004500 GH
z
1.803004500 GH
z
1.803000500 GHz
1.733000500 GH
z
1.802996500 GHz
1.732996500 GH
z
−956 µs
1.544 ms
500.0 µs/div
−956 µs
1.544 ms
500.0 µs/div
4.044 ms
4.044 ms
24
MB15F83UL
■ APPLICATION EXAMPLE
OUTPUT
VCO
3.0 V
LPF
3.0 V
from controller
1000 pF
1000 pF
0.1 µF
0.1 µF
Clock
20
DATA
19
LE
18
finRF
XfinRF GNDRF VCCRF
PSRF
13
VpRF
DORF
17
16
15
14
12
11
MB15F83UL
1
2
3
4
5
6
7
8
9
10
OSCIN
GND
finIF
XfinIF
GNDIF
VCCIF
PSIF
VpIF
DOIF
LD/fout
3.0 V
3.0 V
Lock Det.
1000 pF
1000 pF
1000 pF
0.1 µF
0.1 µF
TCXO
OUTPUT
VCO
LPF
Notes:• Schmit trigger circuit is provided (insert a pull-up or pull-down resistor to prevent oscillation
when open-circuited in the input) .
• TSSOP-20
25
MB15F83UL
■ USAGE PRECAUTIONS
(1) VCCRF, VpRF, VCCIF and VpIF must be equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VpRF, VCCIF and VpIF to
keep them equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions :
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
■ ORDERING INFORMATION
Part number
MB15F83ULPFT
MB15F83ULPVA
Package
Remarks
20-pin plastic TSSOP
(FPT-20P-M06)
20-pad plastic BCC
(LCC-20P-M05)
26
MB15F83UL
■ PACKAGE DIMENSIONS
20-pin Plastic TSSOP
(FPT-20P-M06)
* : These dimensions do not include resin protrusion.
*
6.50±0.10(.256±.004)
0.17±0.05
(.007±.002)
20
11
*
4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
1.05±0.05
(Mounting height)
(.041±.002)
1
10
LEAD No.
"A"
0.65(.026)
0.24±0.08
(.009±.003)
0~8°
M
0.13(.005)
0.07 +–00..0073 .003 –+..000031
(0.50(.020))
(Stand off)
0.25(.010)
0.45/0.75
(.018/.030)
0.10(.004)
C
1999 FUJITSU LIMITED F20026S-2C-2
(
)
Dimensions in mm inches
(Continued)
27
MB15F83UL
(Continued)
20-pad plastic BCC
(LCC-20P-M05)
3.00(.118)TYP
0.25±0.10
3.60±0.10(.142±.004)
0.55±0.05
(.022±.002)
(Mounting height)
(.010±.004)
16
11
11
16
0.50(.020)
TYP
0.25±0.10
(.010±.004)
INDEX AREA
3.40±0.10
(.134±.004)
2.70(.106)
TYP
"D"
"A"
"B"
"C"
1
6
6
1
0.50(.020)
TYP
2.80(.110)REF
0.075±0.025
(.003±.001)
(Stand off)
0.05(.002)
Details of "A" part
Details of "B" part
Details of "C" part
Details of "D" part
0.50±0.10
0.50±0.10
0.50±0.10
0.30±0.10
(.020±.004)
(.020±.004)
(.020±.004)
(.012±.004)
C0.20(.008)
0.60±0.10
(.024±.004)
0.30±0.10
(.012±.004)
0.60±0.10
(.024±.004)
0.40±0.10
(.016±.004)
C
2001 FUJITSU LIMITED C20056S-c-2-1
(
)
Dimensions in mm inches
28
MB15F83UL
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0107
FUJITSU LIMITED Printed in Japan
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