MB2146-303A_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12609-3E

8-bit Microcontroller

CMOS

F²MC-8FX MB95160M Series

MB95F168M/F168N/F168J/FV100D-103

■ DESCRIPTION

The MB95160M series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,

the microcontrollers contain a variety of peripheral functions.

Note : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURE

• F²MC-8FX CPU core

Instruction set optimized for controllers

• Multiplication and division instructions

• 16-bit arithmetic operations

• Bit test branch instruction

• Bit manipulation instructions etc.

• Clock

• Main clock

• Main PLL clock

• Sub clock

• Sub PLL clock

(Continued)

Be sure to refer to the “Check Sheet” for the latest cautions on development.

“Check Sheet” is seen at the following support page

URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system

development.

MB95160M Series

(Continued)

• Timer

• 8/16-bit compound timer × 2 channels

Can be used to interval timer, PWC timer, PWM timer and input capture.

• 8/16-bit PPG × 2 channels

• 16-bit PPG × 1 channel

• Time-base timer × 1 channel

• Watch prescaler × 1 channel

• LIN-UART × 1 channel

• LIN function, clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

• Full duplex double buffer

• UART/SIO × 1 channel

• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable

• Full duplex double buffer

• I²C* × 1 channel

Built-in wake-up function

• External interrupt × 8 channels

• Interrupt by edge detection (rising, falling, or both edges can be selected)

• Can be used to recover from low-power consumption (standby) modes.

• 8/10-bit A/D converter × 8 channels

8-bit or 10-bit resolution can be selected.

• LCD controller (LCDC)

• 32 SEG × 4 COM (Max 128 pixels)

• With blinking function

• Low-power consumption (standby) mode

• Stop mode

• Sleep mode

• Watch mode

• Time-base timer mode

• I/O port

• The number of maximum ports : Max 53

• Port configuration

- General-purpose I/O ports (N-ch open drain) : 2 ports

- General-purpose I/O ports (CMOS)

: 51 ports

• Programmable input voltage levels of port

Automotive input level / CMOS input level / hysteresis input level

• Flash memory security function

Protects the content of Flash memory

* : Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these

components in an I²C system provided that the system conforms to the I²C Standard Specification as defined

by Philips.

2

MB95160M Series

■ PRODUCT LINEUP

Part number*¹

Parameter

MB95F168M

MB95F168N

MB95F168J

Type

Flash memory product

60 Kbytes

ROM capacity

RAM capacity

Reset output

Clock system

2 Kbytes

Yes

No

Dual clock

Low voltage

detection reset

No

Yes

Clock supervisor

Yes

Number of basic instructions

Instruction bit length

Instruction length

: 136

: 8 bits

: 1 to 3 bytes

: 1, 8, and 16 bits

CPU functions

Data bit length

Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25

MHz)

Interrupt processing time

: 0.6 µs (at machine clock frequency 16.25 MHz)

General-purpose I/O port (N-ch open drain) : 2 ports

General-purpose I/O port (CMOS)

Programmable input voltage levels of port :

: 51 ports

Ports (Max 53 ports)

Automotive input level / CMOS input level / hysteresis input level

Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)

Reset generated cycle

Time-base timer

(1 channel)

Watchdog timer

Wild register

At main oscillation clock 10 MHz

At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms

: Min 105 ms

Capable of replacing 3 bytes of ROM data

Master/slave sending and receiving

Bus error function and arbitration function

Detecting transmitting direction function

Start condition repeated generation and detection functions

Built-in wake-up function

I²C

(1 channel)

Data transfer capable in UART/SIO

Full duplex double buffer,

UART/SIO

(1 channel)

variable data length (5/6/7/8-bit), built-in baud rate generator

NRZ type transfer format, error detected function

LSB-first or MSB-first can be selected.

Clock synchronous (SIO) or clock asynchronous (UART) serial data transfer capable

Dedicated reload timer allowing a wide range of communication speeds to be set.

Full duplex double buffer.

Capable of serial data transfer synchronous or asynchronous to clock signal.

LIN functions available as the LIN master or LIN slave.

LIN-UART

(1 channel)

8/10-bit A/D converter

(8 channels)

8-bit or 10-bit resolution can be selected.

(Continued)

3

MB95160M Series

(Continued)

Part number*¹

MB95F168M

MB95F168N

MB95F168J

Parameter

COM output

SEG output

LCD drive power supply (bias) pin

: 4 (Max)

: 32 (Max)

: 4

LCD controller

(LCDC)

32 SEG × 4 COM : 128 pixels can be displayed.

Duty LCD mode

Operable in LCD standby mode

With blinking function

Built-in division resistance for LCD drive

Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer ×

1 channel”.

Built-in timer function, PWC function, PWM function, capture function, and square

wave form output

8/16-bit compound

timer (2 channels)

Count clock : 7 internal clocks and external clock can be selected.

PWM mode or one-shot mode can be selected.

Counter operating clock : Eight selectable clock sources

Support for external trigger start

16-bit PPG

(1 channel)

Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1

channel”.

Counter operating clock : Eight selectable clock sources

8/16-bit PPG

(2 channels)

Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)

Counter value can be set from 0 to 63. (Capable of counting for 1 minute when

selecting clock source 1 second and setting counter value to 60)

Watch counter

Watch prescaler

(1 channel)

4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)

External interrupt

(8 channels)

Interrupt by edge detection (rising, falling, or both edges can be selected.)

Can be used to recover from standby modes.

Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of write/erase cycles (Minimum) : 10000 times

Data retention time: 20 years

Flash memory

Erase can be performed on each block

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash

Standby mode

Sleep, stop, watch, and time-base timer

*1 : MASK ROM products are currently under consideration.

*2 : For details of option, refer to “■ MASK OPTION”.

Note : Part number of evaluation product in MB95160M series is MB95FV100D-103. When using it, the MCU board

(MB2146-303A) is required.

4

MB95160M Series

■ OSCILLATION STABILIZATION WAIT TIME

The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum

value is shown as follows.

Oscillation stabilization wait time

Remarks

(2¹⁴-2) /FCH

Approx. 4.10 ms (at main oscillation clock 4 MHz)

■ PACKAGES AND CORRESPONDING PRODUCTS

Part number

MB95F168M/F168N/F168J

Package

MB95FV100D-103

FPT-64P-M23

FPT-64P-M24

BGA-224P-M08

: Available

: Unavailable

5

MB95160M Series

■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS

• Notes on Using Evaluation Products

The evaluation product has not only the functions of the MB95160M series but also those of other products to

support software development for multiple series and models of the F²MC-8FX family. The I/O addresses for

peripheral resources not used by the MB95160M series are therefore access-barred. Read/write access to these

access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in

unexpected malfunctions of hardware or software.

Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are

used, the address may be read or written unexpectedly).

Also, as the read values of prohibited addresses on the evaluation product are different to the values on the

Flash memory products, do not use these values in the program.

The functions corresponding to certain bits in single-byte registers may not be supported on some Flash memory

products. However, reading or writing to these bits will not cause malfunction of the hardware. Also, as the

evaluation and Flash memory products are designed to have identical software operation, no particular precau-

tions are required.

• Difference of Memory Spaces

If the amount of memory on the evaluation product is different from that of the Flash memory products, carefully

check the difference in the amount of memory from the model to be actually used when developing software.

For details of memory space, refer to “■ CPU CORE”.

• Current Consumption

For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.

• Package

For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and

“■ PACKAGE DIMENSIONS”.

• Operating voltage

The operating voltage is different among the evaluation and Flash memory products.

For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”

6

MB95160M Series

■ PIN ASSIGNMENT

(TOP VIEW)

AV^CC

AVR

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P60/SEG16/PPG10

PC7/SEG15

PC6/SEG14

PC5/SEG13

PC4/SEG12

PC3/SEG11

PC2/SEG10

PC1/SEG09

PC0/SEG08

PB7/SEG07

PB6/SEG06

PB5/SEG05

PB4/SEG04

PB3/SEG03

PB2/SEG02

PB1/SEG01

2

P14/PPG0

P13/TRG0/ADTG

P12/UCK0

P11/UO0

3

4

5

6

P10/UI0

7

P24/EC0/SDA0

P23/TO01/SCL0

P22/TO00

P21/PPG01

P20/PPG00

MOD

8

LQFP-64

9

10

11

12

13

14

15

16

X0

X1

V

SS

(FPT-64P-M23,FPT-64P-M24)

7

MB95160M Series

■ PIN DESCRIPTION

I/O circuit

type*

Pin no.

Pin name

Function

A/D converter power supply pin

1

2

AV^CC

AVR

⎯

A/D converter reference input pin

General-purpose I/O port.

The pin is shared with 16-bit PPG ch.0 output.

3

P14/PPG0

General-purpose I/O port.

The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and

A/D converter trigger input (ADTG) .

P13/TRG0/

ADTG

4

H

General-purpose I/O port.

The pin is shared with UART/SIO ch.0 clock I/O.

5

6

7

P12/UCK0

P11/UO0

P10/UI0

General-purpose I/O port.

The pin is shared with UART/SIO ch.0 data output.

General-purpose I/O port.

The pin is shared with UART/SIO ch.0 data input.

G

I

General-purpose I/O port.

P24/EC0/

SDA0

8

9

The pin is shared with 8/16-bit compound timer ch.0 clock input

(EC0) and I²C ch.0 data I/O (SDA0) .

General-purpose I/O port.

P23/TO01/

SCL0

The pin is shared with 8/16-bit compound timer ch.0 output (TO01)

and I²C ch.0 clock I/O (SCL0) .

General-purpose I/O port.

The pin is shared with 8/16-bit compound timer ch.0 output.

10

11

12

P22/TO00

P21/PPG01

P20/PPG00

General-purpose I/O port.

The pin is shared with 8/16-bit PPG ch.0 output.

H

General-purpose I/O port.

The pin is shared with 8/16-bit PPG ch.0 output.

13

14

15

16

17

18

19

20

21

22

23

24

25

MOD

X0

B

A

Operating mode designation pin

Main clock oscillation pin

X1

V^SS

⎯

Power supply pin (GND)

Power supply pin

V^CC

C

Capacitor connection pin

X1A

A

Sub clock oscillation pins (32 kHz)

Reset pin

X0A

RST

P90/V3

P91/V2

P92/V1

P93/V0

B’

General-purpose I/O port.

The pins are shared with power supply pin for LCDC drive.

R

(Continued)

8

MB95160M Series

I/Ocircuit

type*

Pin no.

Pin name

Function

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

P94

S

General-purpose I/O port.

P95

PA0/COM0

PA1/COM1

PA2/COM2

PA3/COM3

PB0/SEG00

PB1/SEG01

PB2/SEG02

PB3/SEG03

PB4/SEG04

PB5/SEG05

PB6/SEG06

PB7/SEG07

PC0/SEG08

PC1/SEG09

PC2/SEG10

PC3/SEG11

PC4/SEG12

PC5/SEG13

PC6/SEG14

PC7/SEG15

M

The pins are shared with LCDC COM output (COM0 to COM3).

General-purpose I/O port.

The pins are shared with LCDC SEG output (SEG00 to SEG07).

M

General-purpose I/O port.

The pins are shared with LCDC SEG output (SEG08 to SEG15).

M

P60/SEG16/

PPG10

48

49

General-purpose I/O port.

The pins are shared with LCDC SEG output (SEG16, SEG17) and

8/16-bit PPG ch.1 output (PPG10, PPG11) .

P61/SEG17/

PPG11

M

General-purpose I/O port.

The pin is shared with LCDC SEG output (SEG18) and 8/16-bit

compound timer ch.1 output (TO10) .

P62/SEG18/

TO10

50

(Continued)

9

MB95160M Series

(Continued)

I/Ocircuit

type*

Pin no.

Pin name

Function

General-purpose I/O port.

The pin is shared with LCDC SEG output (SEG19) and 8/16-bit

compound timer ch.1 output (TO11) .

P63/SEG19/

TO11

51

General-purpose I/O port.

The pin is shared with LCDC SEG output (SEG20) and 8/16-bit

compound timer ch.1 clock input (EC1) .

P64/SEG20/

EC1

52

53

54

55

M

General-purpose I/O port.

The pin is shared with LCDC SEG output (SEG21) and LIN-UART

clock I/O (SCK) .

P65/SEG21/

SCK

General-purpose I/O port.

The pin is shared with LCDC SEG output (SEG22) and LIN-UART

data output (SOT) .

P66/SEG22/

SOT

General-purpose I/O port.

The pin is shared with LCDC SEG output (SEG23) and LIN-UART

data input (SIN) .

P67/SEG23/

SIN

N

P07/INT07/

AN07/SEG24

56

57

58

59

60

61

62

P06/INT06/

AN06/SEG25

P05/INT05/

AN05/SEG26

P04/INT04/

AN04/SEG27

General-purpose I/O port.

The pins are shared with external interrupt input (INT00 to INT07) ,

A/D analog input (AN00 to AN07) and LCDC SEG output (SEG24 to

SEG31) .

F

P03/INT03/

AN03/SEG28

P02/INT02/

AN02/SEG29

P01/INT01/

AN01/SEG30

P00/INT00/

AN00/SEG31

63

64

AV^SS

⎯

Power supply pin (GND) of A/D converter

* : Refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types.

10

MB95160M Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Oscillation circuit

• High-speed side

Feedback resistance : approx. 1 MΩ

• Low-speed side

X1 (X1A)

X0 (X0A)

Clock input

N-ch

Feedback resistance : approx. 10 MΩ

Standby control

B

• Only for input

• Hysteresis input

Mode input

Reset input

B’

• Hysteresis input

• Reset output

Reset output

N-ch

F

• CMOS output

• LCD output

• Hysteresis input

• Analog input

P-ch

N-ch

Digital output

• Automotive input

Analog input

LCD output

Hysteresis input

A/D control

LCD control

Automotive input

Standby control

External interrupt

control

G

• CMOS output

• CMOS input

R

P-ch

Pull-up control

• Hysteresis input

• With pull-up control

• Automotive input

P-ch

N-ch

Digital output

CMOS input

Hysteresis input

Automotive input

Standby control

(Continued)

11

MB95160M Series

Type

Circuit

Remarks

H

• CMOS output

• Hysteresis input

• With pull-up control

• Automotive input

R

P-ch

Pull-up control

Digital output

P-ch

Digital output

N-ch

Hysteresis input

Automotive input

Standby control

I

• N-ch open drain output

• CMOS input

• Hysteresis input

• Automotive input

Digital output

CMOS input

N-ch

Hysteresis input

Automotive input

Standby control

M

• CMOS output

• LCD output

• Hysteresis input

• Automotive input

P-ch

Digital output

N-ch

LCD output

Hysteresis input

Automotive input

LCD control

Standby control

N

• CMOS output

• LCD output

• CMOS input

• Hysteresis input

• Automotive input

P-ch

N-ch

Digital output

LCD output

CMOS input

Hysteresis input

Automotive input

LCD control

Standby control

(Continued)

12

MB95160M Series

(Continued)

Type

Circuit

Remarks

R

• CMOS output

P-ch

• LCD power supply

• Hysteresis input

• Automotive input

Digital output

N-ch

LCD built-in internal split

resistor I/O

Hysteresis input

Automotive input

Standby control

LCD control

S

• CMOS output

P-ch

N-ch

• LCD power supply

• Hysteresis input

• Automotive input

Digital output

Hysteresis input

Automotive input

Standby control

13

MB95160M Series

■ HANDLING DEVICES

• Preventing Latch-up

Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.

Latch-up may occur on CMOS ICs if voltage higher than V^CCor lower than VSS is applied to input and output pins

other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between V^CC

pin and VSS pin.

When latch-up occurs, power supply current increases rapidly and might thermally damage elements.

• Stable Supply Voltage

Supply voltage should be stabilized.

A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range

of the Vcc power-supply voltage.

For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range

(50/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient

variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.

• Precautions for Use of External Clock

Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up

from sub clock mode or stop mode.

PIN CONNECTION

• Treatment of Unused Pin

Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent dam-

age. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused

input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused

input pins. If there is unused output pin, make it to open.

• Power Supply Pins

In products with multiple V^CCor VSS pins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply

and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V^CCand VSS pins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between V^CCand VSS pins

near this device.

14

MB95160M Series

• Mode Pin (MOD)

Connect the MOD pin directly to V^CCor VSS.

To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to

minimize the distance from the MOD pin to V^CCor VSS and to provide a low-impedance connection.

Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of V^CCpin

must have a capacitance value higher than C^S. For connection of smoothing capacitor CS, refer to the diagram

below.

• C pin connection diagram

C

CS

• Analog Power Supply

Always set the same potential to AV^CCand VCC pins. When VCC > AVCC, the current may flow through the AN00

to AN07 pins.

• Treatment of Power Supply Pins on A/D Converter

Connect to be AV^CC= VCC and AVSS = AVR = VSS even if the A/D converter is not in use.

Noise riding on the AV^CCpin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor

as a bypass capacitor between AV^CCand AVSS pins in the vicinity of this device.

15

MB95160M Series

■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL

PROGRAMMER

• Supported Parallel Programmers and Adapters

The following table lists supported parallel programmers and adapters.

Package

Applicable adapter model

Parallel programmers

FPT-64P-M23

TEF110-95F168HPMC

AF9708 (Ver 02.35G or more)

AF9709/B (Ver 02.35G or more)

AF9723+AF9834 (Ver 02.08E or more)

FPT-64P-M24

TEF110-95F168HPMC1

Note : For information on applicable adapter models and parallel programmers, contact the following:

Flash Support Group, Inc. TEL: +81-53-428-8380

• Sector Configuration

The individual sectors of Flash memory correspond to addresses used for CPU access and programming by

the parallel programmer as follows:

Flash memory

60 Kbytes

CPU address

1000^H

Programmer address*

11000H

FFFFH

1FFFFH

*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer

programs data into Flash memory.

These programmer addresses are used for the parallel programmer to program or erase data in

Flash memory.

• Programming Method

1) Set the type code of the parallel programmer to 17222.

2) Load program data to programmer addresses 11000^Hto 1FFFFH.

3) Programmed by parallel programmer

16

MB95160M Series

■ BLOCK DIAGRAM

F²MC-8FX CPU

RST

Reset control

Clock control

ROM

RAM

X0/X1

X0A/X1A

Interrupt control

Wild register

Watch prescaler

Watch counter

P00/INT00 to

P07/INT07

External interrupt

P60/SEG16/PPG10

P61/SEG17/PPG11

8/16-bit PPG ch.1

8/16-bit

P10/UI0

P11/UO0

P12/UCK0

UART/SIO

P62/SEG18/TO10

P63/SEG19/TO11

P64/SEG20/EC1

compound timer ch.1

P13/TRG0/ADTG

P14/PPG0

16-bit PPG

P65/SEG21/SCK

P66/SEG22/SOT

P67/SEG23/SIN

LIN-UART

P20/PPG00

P21/PPG01

8/16-bit PPG ch.0

P90/V3 to P93/V0

P22/TO00

P23/TO01/SCL0

P24/EC0/SDA0

8/16-bit

compound timer ch.0

PA0/COM0 to PA3/COM3

PB0/SEG00 to PB7/SEG07

PC0/SEG08 to PC7/SEG15

(P00/SEG31 to P07/SEG24)

LCDC

I²C

(P00/AN00 to

P07/AN07)

8/10-bit

A/D converter

AVCC

AVSS

AVR

P94/P95

Port

Other pins

MOD, VSS, VCC, C

17

MB95160M Series

■ CPU CORE

1. Memory space

Memory space of the MB95160M series is 64 Kbytes and consists of I/O area, data area, and program area.

The memory space includes special-purpose areas such as the general-purpose registers and vector table.

Memory map of the MB95160M series is shown below.

• Memory Map

MB95F168M

MB95F168N

MB95FV100D-103

MB95F168J

0000H

I/O

0080H

0100H

0200H

0080H

0100H

0200H

RAM 2Kbytes

RAM 3.75Kbytes

Register

0880^H

0F80H

1000H

Access prohibited

0F80H

Exterded I/O

1000H

Flash memory

60Kbytes

Flash memory

60Kbytes

FFFFH

18

MB95160M Series

2. Register

The MB95160M series has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The dedicated registers are as follows:

Program counter (PC)

: A 16-bit register to indicate locations where instructions are stored.

Accumulator (A)

: A 16-bit register for temporary storage of arithmetic operations. In the case of

an 8-bit data processing instruction, the lower 1 byte is used.

Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.

In the case of an 8-bit data processing instruction, the lower 1 byte is used.

Index register (IX)

Extra pointer (EP)

Stack pointer (SP)

Program status (PS)

: A 16-bit register for index modification.

: A 16-bit pointer to point to a memory address.

: A 16-bit register to indicate a stack area.

: A 16-bit register for storing a register bank pointer, a direct bank pointer, and

a condition code register.

Initial Value

16-bit

FFFD^H

0000H

0030H

: Program counter

: Accumulator

PC

AH

TH

AL

TL

: Temporary accumulator

: Index register

IX

: Extra pointer

EP

SP

PS

: Stack pointer

: Program status

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer

(DP) and the lower 8 bits for use as a condition code register (CCR). (Refer to the diagram below.)

• Structure of the Program Status

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

R4

R3

R2

R1

R0 DP2 DP1 DP0

H

I

IL1

IL0

N

Z

PS

C

V

RP

DP

CCR

19

MB95160M Series

The RP indicates the address of the register bank currently being used. The relationship between the content

of RP and the real address conforms to the conversion rule illustrated below:

• Rule for Conversion of Actual Addresses in the General-purpose Register Area

RP upper

OP code lower

"0" "0" "0" "0" "0" "0" "0" "1"

R4 R3 R2 R1 R0 b2

b1

b0

Generated address

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct

addresses to 0080H to 00FFH.

Direct bank pointer (DP2 to DP0)

Specified address area

Mapping area

0000H to 007FH (without mapping)

0080H to 00FFH (without mapping)

0100H to 017FH

XXX^B(no effect to mapping)

0000H to 007FH

000^B(initial value)

001^B

010B

011B

100B

101B

110B

111B

0180H to 01FFH

0200H to 027FH

0080^Hto 00FFH

0280H to 02FFH

0300H to 037FH

0380H to 03FFH

0400H to 047FH

The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that

control CPU operations at interrupt.

H flag

I flag

Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to “0” otherwise. This flag is for decimal adjustment instructions.

Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.

The flag is set to “0” when reset.

Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level

is higher than the value indicated by these bits.

:

IL1, IL0

IL1

0

IL0

0

Interrupt level

Priority

0

1

2

High

0

1

0

1

3

Low (no interruption)

N flag

Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the

bit is set to “0”.

:

Z flag : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.

V flag

Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”

otherwise.

:

C flag

Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared

to “0” otherwise. Set to the shift-out value in the case of a shift instruction.

:

20

MB95160M Series

The following general-purpose registers are provided:

General-purpose registers: 8-bit data storage registers

The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains

8-register. Up to a total of 32 banks can be used on the MB95160M series. The bank currently in use is specified

by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)

to general-purpose register 7 (R7).

• Register Bank Configuration

8-bit

1F8_H

This address = 0100^H+ 8 × (RP)

Address 100_H

R0

R1

R0

R1

R0

R1

R2

R3

R4

R5

R6

R7

R2

R3

R4

R5

R6

R7

R2

R3

R4

R5

R6

R7

1FF_H

Bank 31

107_H

32 banks

32 banks (RAM area)

The number of banks is

limited by the usable RAM

capacitance.

Bank 0

Memory area

21

MB95160M Series

■ I/O MAP

Register

abbreviation

Address

Register name

R/W

Initial value

0000^H

0001H

0002H

0003H

0004H

0005^H

0006H

0007H

0008H

0009H

000AH

000BH

000CH

000DH

000E^H

000FH

PDR0

DDR0

PDR1

DDR1

⎯

Port 0 data register

Port 0 direction register

Port 1 data register

R/W

⎯

00000000B

⎯

Port 1 direction register

(Disabled)

WATR

PLLC

SYCC

STBC

RSRR

TBTC

WPCR

WDTC

⎯

Oscillation stabilization wait time setting register

PLL control register

R/W

11111111B

00000000B

1010X011B

00000000B

System clock control register

Standby control register

Reset factor register

R/W XXXXXXXXB

Time-base timer control register

Watch prescaler control register

Watchdog timer control register

(Disabled)

R/W

⎯

00000000B

⎯

PDR2

DDR2

Port 2 data register

R/W

00000000B

Port 2 direction register

0010H

to

0015^H

⎯

(Disabled)

⎯

0016^H

0017H

PDR6

DDR6

Port 6 data register

R/W

00000000B

Port 6 direction register

0018H

to

001B^H

⎯

(Disabled)

⎯

001C^H

001DH

001EH

001FH

0020H

0021H

0022H

0023H

PDR9

DDR9

PDRA

DDRA

PDRB

DDRB

PDRC

DDRC

Port 9 data register

Port 9 direction register

Port A data register

R/W

00000000B

Port A direction register

Port B data register

Port B direction register

Port C data register

Port C direction register

0024H

to

002C^H

⎯

(Disabled)

⎯

(Continued)

22

MB95160M Series

Register

abbreviation

Address

Register name

R/W Initial value

002D^H

002EH

PUL1

PUL2

Port 1 pull-up register

Port 2 pull-up register

R/W

00000000B

002FH

to

0035^H

⎯

(Disabled)

⎯

0036^H

0037H

0038H

0039H

003AH

003BH

003CH

003DH

T01CR1

T00CR1

T11CR1

T10CR1

PC01

8/16-bit compound timer 01 control status register 1 ch.0

8/16-bit compound timer 00 control status register 1 ch.0

8/16-bit compound timer 11 control status register 1 ch.1

8/16-bit compound timer 10 control status register 1 ch.1

8/16-bit PPG1 control register ch.0

R/W

00000000B

PC00

8/16-bit PPG0 control register ch.0

PC11

8/16-bit PPG1 control register ch.1

PC10

8/16-bit PPG0 control register ch.1

003EH

to

0041^H

⎯

(Disabled)

⎯

0042^H

0043H

PCNTH0

PCNTL0

16-bit PPG status control register (upper byte) ch.0

16-bit PPG status control register (lower byte) ch.0

R/W

00000000B

0044H

to

0047^H

⎯

(Disabled)

⎯

0048^H

0049H

004AH

004BH

EIC00

EIC10

EIC20

EIC30

External interrupt circuit control register ch.0/ch.1

External interrupt circuit control register ch.2/ch.3

External interrupt circuit control register ch.4/ch.5

External interrupt circuit control register ch.6/ch.7

R/W

00000000B

004CH

to

004F^H

⎯

(Disabled)

⎯

0050^H

0051H

0052H

0053H

0054H

0055H

0056H

0057H

0058H

SCR

SMR

LIN-UART serial control register

LIN-UART serial mode register

R/W

00000000B

00001000B

00000000B

00000100B

000000XXB

00000000B

00100000B

SSR

LIN-UART serial status register

RDR/TDR

ESCR

ECCR

SMC10

SMC20

SSR0

LIN-UART reception/transmission data register

LIN-UART extended status control register

LIN-UART extended communication control register

UART/SIO serial mode control register 1 ch.0

UART/SIO serial mode control register 2 ch.0

UART/SIO serial status register ch.0

00000001B

(Continued)

23

MB95160M Series

Register

Address

Register name

R/W Initial value

abbreviation

0059^H

005AH

TDR0

RDR0

UART/SIO serial output data register ch. 0

UART/SIO serial input data register ch.0

R/W

R

00000000B

005BH

to

005F^H

⎯

(Disabled)

⎯

0060^H

0061H

0062H

0063H

0064H

0065H

IBCR00

IBCR10

IBSR0

IDDR0

IAAR0

ICCR0

I²C bus control register 0 ch.0

I²C bus control register 1 ch.0

I²C bus status register ch.0

I²C data register ch.0

I²C address register ch.0

I²C clock control register ch.0

R/W

R

00000000B

R/W

0066H

to

006B^H

⎯

(Disabled)

⎯

006C^H

006DH

006EH

006FH

0070H

0071H

0072^H

0073H

0074H

0075H

0076^H

0077H

ADC1

ADC2

ADDH

ADDL

WCSR

⎯

8/10-bit A/D converter control register 1

8/10-bit A/D converter control register 2

8/10-bit A/D converter data register (upper byte)

8/10-bit A/D converter data register (lower byte)

Watch counter status register

R/W

⎯

00000000B

⎯

(Disabled)

FSR

Flash memory status register

R/W

⎯

000X0000B

00000000B

⎯

SWRE0

SWRE1

⎯

Flash memory sector writing control register 0

Flash memory sector writing control register 1

(Disabled)

WREN

WROR

Wild register address compare enable register

Wild register data test setting register

R/W

00000000B

Register bank pointer (RP) ,

Mirror of direct bank pointer (DP)

0078H

⎯

0079^H

007AH

007BH

007CH

007DH

007EH

007FH

0F80^H

ILR0

ILR1

Interrupt level setting register 0

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Interrupt level setting register 4

Interrupt level setting register 5

(Disabled)

R/W

⎯

11111111B

⎯

ILR2

ILR3

ILR4

ILR5

⎯

WRARH0

Wild register address setting register (upper byte) ch.0

R/W

00000000B

(Continued)

24

MB95160M Series

Register

abbreviation

Address

Register name

R/W

Initial value

0F81^H

0F82H

0F83H

0F84H

0F85H

0F86H

0F87H

0F88H

WRARL0

WRDR0

WRARH1

WRARL1

WRDR1

WRARH2

WRARL2

WRDR2

Wild register address setting register (lower byte) ch.0

Wild register data setting register ch.0

R/W

00000000B

Wild register address setting register (upper byte) ch.1

Wild register address setting register (lower byte) ch.1

Wild register data setting register ch.1

Wild register address setting register (upper byte) ch.2

Wild register address setting register (lower byte) ch.2

Wild register data setting register ch.2

0F89H

to

0F91^H

⎯

(Disabled)

⎯

0F92^H

0F93H

0F94H

0F95H

T01CR0

T00CR0

T01DR

T00DR

8/16-bit compound timer 01 control status register 0 ch.0

8/16-bit compound timer 00 control status register 0 ch.0

8/16-bit compound timer 01 data register ch.0

R/W

00000000B

8/16-bit compound timer 00 data register ch.0

8/16-bit compound timer 00/01 timer mode control

register ch.0

0F96H

TMCR0

R/W

00000000^B

0F97H

0F98H

0F99H

0F9AH

T11CR0

T10CR0

T11DR

T10DR

8/16-bit compound timer 11 control status register 0 ch.1

8/16-bit compound timer 10 control status register 0 ch.1

8/16-bit compound timer 11 data register ch.1

R/W

00000000B

8/16-bit compound timer 10 data register ch.1

8/16-bit compound timer 10/11 timer mode control

register ch.1

0F9BH

TMCR1

R/W

00000000^B

0F9CH

0F9DH

0F9EH

0F9FH

0FA0H

0FA1H

0FA2H

0FA3H

0FA4H

0FA5H

PPS01

PPS00

PDS01

PDS00

PPS11

PPS10

PDS11

PDS10

PPGS

8/16-bit PPG1 cycle setting buffer register ch.0

8/16-bit PPG0 cycle setting buffer register ch.0

8/16-bit PPG1 duty setting buffer register ch.0

8/16-bit PPG0 duty setting buffer register ch.0

8/16-bit PPG1 cycle setting buffer register ch.1

8/16-bit PPG0 cycle setting buffer register ch.1

8/16-bit PPG1 duty setting buffer register ch.1

8/16-bit PPG0 duty setting buffer register ch.1

8/16-bit PPG start register

R/W

11111111B

00000000B

REVC

8/16-bit PPG output inversion register

0FA6H

to

0FA9^H

⎯

(Disabled)

⎯

(Continued)

25

MB95160M Series

Register

Address

Register name

R/W Initialvalue

abbreviation

0FAA^H

0FABH

0FACH

0FADH

0FAEH

0FAFH

PDCRH0

PDCRL0

PCSRH0

PCSRL0

PDUTH0

PDUTL0

16-bit PPG down counter register (upper byte) ch.0

16-bit PPG down counter register (lower byte) ch.0

16-bit PPG cycle setting buffer register (upper byte) ch.0

16-bit PPG cycle setting buffer register (lower byte) ch.0

16-bit PPG duty setting buffer register (upper byte) ch.0

16-bit PPG duty setting buffer register (lower byte) ch.0

R

00000000B

11111111B

R

R/W

0FB0H

to

0FBB^H

⎯

(Disabled)

⎯

0FBC^H

0FBDH

BGR1

BGR0

LIN-UART baud rate generator register 1

LIN-UART baud rate generator register 0

R/W

00000000B

UART/SIO dedicated baud rate generator prescaler selecting

register ch.0

0FBEH

PSSR0

BRSR0

R/W

00000000^B

00000000B

0FBFH

UART/SIO dedicated baud rate generator setting register ch.0 R/W

0FC0H

to

0FC2^H

⎯

(Disabled)

⎯

0FC3^H

0FC4H

0FC5H

0FC6H

0FC7H

0FC8H

0FC9H

0FCAH

0FCB^H

0FCCH

AIDRL

LCDCC

LCDCE1

LCDCE2

LCDCE3

LCDCE4

LCDCE5

⎯

A/D input disable register (lower byte)

LCDC control register

R/W

⎯

00000000B

00010000B

00110000B

00000000B

⎯

LCDC enable register 1

LCDC enable register 2

LCDC enable register 3

LCDC enable register 4

LCDC enable register 5

(Disabled)

LCDCB1

LCDCB2

LCDC blinking setting register 1

LCDC blinking setting register 2

R/W

00000000B

0FCDH

to

LCDRAM

LCDC display RAM

R/W

00000000B

0FDC^H

0FDDH

to

0FE2^H

⎯

(Disabled)

⎯

0FE3^H

WCDR

Watch counter data register

R/W

00111111B

(Continued)

26

MB95160M Series

(Continued)

Register

abbreviation

Address

Register name

R/W

Initial value

0FE4^H

to

0FE6^H

⎯

(Disabled)

⎯

0FE7^H

ILSR2

⎯

Input level select register 2

(Disabled)

R/W

⎯

00000000B

⎯

0FE8H,

0FE9^H

0FEA^H

CSVCR

Clock supervisor control register

R/W

00011100B

0FEBH

to

0FED^H

⎯

(Disabled)

⎯

0FEE^H

0FEFH

ILSR

Input level selecting register

Interrupt pin control register

R/W

00000000B

01000000B

WICR

0FF0H

to

0FFF^H

⎯

(Disabled)

⎯

• R/W access symbols

R/W : Readable/Writable

R

W

: Read only

: Write only

• Initial value symbols

0

1

X

: The initial value of this bit is “0”.

: The initial value of this bit is “1”.

: The initial value of this bit is undefined.

Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.

27

MB95160M Series

■ INTERRUPT SOURCE TABLE

Vector table address

Same level

priority order

(atsimultaneous

occurrence)

Interrupt

request

number

Bit name of

interrupt level

setting register

Interrupt source

Upper

FFFA^H

FFF8^H

FFF6^H

FFF4^H

Lower

FFFBH

FFF9H

FFF7H

FFF5H

External interrupt ch.0

External interrupt ch.4

External interrupt ch.1

External interrupt ch.5

External interrupt ch.2

External interrupt ch.6

External interrupt ch.3

External interrupt ch.7

UART/SIO ch.0

High

IRQ0

IRQ1

IRQ2

IRQ3

L00 [1 : 0]

L01 [1 : 0]

L02 [1 : 0]

L03 [1 : 0]

IRQ4

IRQ5

FFF2^H

FFF0^H

FFEE^H

FFEC^H

FFEA^H

FFE8^H

FFE6^H

FFE4^H

FFE2^H

FFE0^H

FFDE^H

FFDC^H

FFDAH

FFD8^H

FFD6^H

FFD4^H

FFD2^H

FFD0^H

FFCE^H

FFCC^H

FFF3H

FFF1H

FFEFH

FFEDH

FFEBH

FFE9H

FFE7H

FFE5H

FFE3H

FFE1H

FFDFH

FFDDH

FFDBH

FFD9H

FFD7H

FFD5H

FFD3H

FFD1H

FFCFH

FFCDH

L04 [1 : 0]

L05 [1 : 0]

L06 [1 : 0]

L07 [1 : 0]

L08 [1 : 0]

L09 [1 : 0]

L10 [1 : 0]

L11 [1 : 0]

L12 [1 : 0]

L13 [1 : 0]

L14 [1 : 0]

L15 [1 : 0]

L16 [1 : 0]

L17 [1 : 0]

L18 [1 : 0]

L19 [1 : 0]

L20 [1 : 0]

L21 [1 : 0]

L22 [1 : 0]

L23 [1 : 0]

8/16-bit compound timer ch.0 (Lower)

8/16-bit compound timer ch.0 (Upper)

LIN-UART (reception)

LIN-UART (transmission)

8/16-bit PPG ch.1 (Lower)

8/16-bit PPG ch.1 (Upper)

(Unused)

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IRQ16

IRQ17

IRQ18

IRQ19

IRQ20

IRQ21

IRQ22

IRQ23

8/16-bit PPG ch.0 (Upper)

8/16-bit PPG ch.0 (Lower)

8/16-bit compound timer ch.1 (Upper)

16-bit PPG ch.0

I²C ch.0

(Unused)

8/10-bit A/D converter

Time-base timer

Watch prescaler/Watch counter

(Unused)

8/16-bit compound timer ch.1 (Lower)

Flash memory

Low

28

MB95160M Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

VCC,

AV^CC

Vss − 0.3

Vss + 6.0

*2

Power supply voltage*¹

V

AVR

*2

*3

Power supply voltage

for LCD

V0 to V3

Input voltage*¹

Output voltage*¹

VI

VO

Vss − 0.3

− 2.0

Vss + 6.0

+ 2.0

V

*4

Maximum clamp current

I^CLAMP

mA Applicable to pins*⁵

Total maximum clamp

current

Σ|I^CLAMP|

⎯

20

15

mA Applicable to pins*⁵

“L” level maximum

output current

I^OL

mA Applicable to pins*⁵

Applicable to pins*⁵

“L” level average

current

Average output current =

I^OLAV

⎯

4

mA

operating current × operating ratio

(1 pin)

“L” level total maximum

output current

ΣI^OL

ΣI^OLAV

I^OH

⎯

100

50

mA

Total average output current =

mA operating current × operating ratio

(Total of pins)

“L” level total average

output current

“H” level maximum

output current

− 15

mA Applicable to pins*⁵

Applicable to pins*⁵

“H” level average

current

Average output current =

I^OHAV

⎯

− 4

mA

operating current × operating ratio

(1 pin)

“H” level total maximum

output current

ΣI^OH

⎯

− 100

− 50

mA

Total average output current =

mA operating current × operating ratio

(Total of pins)

“H” level total average

output current

ΣI^OHAV

Power consumption

Operating temperature

Storage temperature

Pd

T^A

⎯

320

+ 85

+ 150

mW

°C

− 10

− 55

Tstg

°C

(Continued)

29

MB95160M Series

(Continued)

*1 : The parameter is based on V^SS= 0.0 V.

*2 : Apply equal potential to AV^CCand VCC. AVR should not exceed AVCC + 0.3 V.

*3 : V0 to V3 should not exceed V^CC+ 0.3 V.

*4 : V^Iand Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current

to/from an input is limited by some means with external components, the I^CLAMPrating supersedes the VI rating.

*5 : Applicable to pins :

P00 to P07, P10 to P14, P20 to P22,P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7

• Use within recommended operating conditions.

• Use at DC voltage (current).

• + B signal is an input signal that exceeds V^CCvoltage. The + B signal should always be applied a limiting

resistance placed between the + B signal and the microcontroller.

• The value of the limiting resistance should be set so that when the + B signal is applied the input current

to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this affects

other devices.

• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the

resulting power supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the + B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept

+ B signal input.

• Sample recommended circuits :

• Input/Output Equivalent circuits

Protective diode

Vcc

Limiting

P-ch

resistance

+ B input (0 V to 16 V)

N-ch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

30

MB95160M Series

2. Recommended Operating Conditions

Condi-

(Vss = 0.0 V)

Value

Max

2.42*^1,*²5.5*¹

Parameter

Symbol

Unit

Remarks

tions

Min

In normal operating

Other than

MB95FV100D-

103

Hold condition in STOP

mode

2.3

2.7

2.3

5.5

Power supply

voltage

V^CC,

AV^CC

V

In normal operating

MB95FV100D-

103

Hold condition in STOP

mode

The range of liquid crystal power supply:

without up-conversion (The optimal value

depends on liquid crystal display elements

used.)

V0

to

V3

Power supply

voltage for LCD

⎯

V^SS

4.0

VCC

V

A/D converter

reference input voltage

AVR

C^S

AV^CC

Smoothing capacitor

0.1

− 10

+ 5

1.0

µF *3

+ 85

+35

°C Other than MB95FV100D-103

°C MB95FV100D-103

Operating temperature

T^A

*1 : The values vary with the operating frequency, machine clock or analog guarantee range.

*2 : The value is 2.88 V when the low voltage detection reset is used. The device operates normally during the time

between 2.88 V and low voltage detection, and between release voltage and 2.88 V.

(Continued)

31

MB95160M Series

(Continued)

*3 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of V^CC

pin must have a capacitor value higher than C^S. For connection of smoothing capacitor CS, refer to the diagram

below.

• C pin connection diagram

C

CS

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

32

MB95160M Series

3. DC Characteristics

(Vcc = 5.0 V 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

Parameter

bol

Pin name

Conditions

Unit

Remarks

Min

Typ

Max

When selecting

CMOS input level

V^IH1P10, P67

*1

0.7 VCC

⎯

VCC + 0.3

VSS + 5.5

V

V^IH2P23, P24

⎯

P00 to P07,

P10 to P14,

P20 to P22,

P60 to P67,

P90 to P95,

PA0 to PA3,

PB0 to PB7,

PC0 to PC7

Port inputs if Auto-

motive input levels

are selected

V^IHA

⎯

0.8 V^CC

⎯

VCC + 0.3

V

“H” level input

voltage

P00 to P07,

P10 to P14,

P20 to P22,

P60 to P67,

P90 to P95,

PA0 to PA3,

PB0 to PB7,

PC0 to PC7

V^IHS1

*1

0.8 V^CC

VCC + 0.3

Hysteresis input

CMOS input

V^IHS2P23, P24

V^IHMRST, MOD

*1

0.8 VCC

0.7 VCC

⎯

VSS + 5.5

VCC + 0.3

V

⎯

Hysteresis input

(When selecting

CMOS input level)

V^ILP10,P23, P24,P67

*1

VSS − 0.3

⎯

0.3 VCC

V

P00 to P07,

P10 to P14,

P20 to P24,

P60 to P67,

P90 to P95,

PA0 to PA3,

PB0 to PB7,

PC0 to PC7

Port inputs if

Automotive input

levels are selected

V^ILA

⎯

V^SS− 0.3

⎯

0.5 VCC

V

“L” level input

voltage

P00 to P07,

P10 to P14,

P20 to P24,

P60 to P67,

P90 to P95,

V^ILS

*1

V^SS− 0.3

⎯

0.2 VCC

V

Hysteresis input

PA0 to PA3,

PB0 to PB7,

PC0 to PC7

V^ILMRST, MOD

⎯

VSS − 0.3

V^cc− 0.5

⎯

0.3 VCC

V

Hysteresis input

“H” level

output voltage

Output pins other

V^OH

IOH =

⎯

than P00 to P07

− 4.0 mA

(Continued)

33

MB95160M Series

(Vcc = 5.0 V 10%, Vss = 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Remarks

Min Typ Max

Output pins other

“L” level output

voltage

V^OLthan P00 to P07,

IOL = 4.0 mA

⎯

0.4

V

RST*²

Input leakage

current (Hi-Z

output leakage

current)

Ports other than

P23, P24

When the pull-up

prohibition setting

I^LI

0.0 V < V^I< VCC

− 5

+ 5

µA

P10 to P14,

P20 to P22

When the pull-up

permission setting

Pull-up resistor R^PULL

V^I= 0.0 V

f = 1 MHz

25

50

5

100

15

kΩ

Input

Other than AVCC,

AV^SS, AVR, VCC, VSS

C^IN

⎯

pF

capacitance

At other than Flash

9.5 12.5 mA memory writing

and erasing

F^CH= 20 MHz

F^MP= 10 MHz

Main clock mode

(divided by 2)

⎯

At Flash memory

30.0 35.0 mA

writing and erasing

ICC

At other than Flash

15.2 20.0 mA memory writing

and erasing

F^CH= 32 MHz

F^MP= 16 MHz

Main clock mode

(divided by 2)

At Flash memory

35.7 42.5 mA

writing and erasing

FCH = 20 MHz

F^MP= 10 MHz

Main Sleep mode

(divided by 2)

⎯

4.5

7.5

mA

I^CCS

F^CH= 32 MHz

F^MP= 16 MHz

Main Sleep mode

(divided by 2)

VCC

Power supply

current*³

(External clock

operation)

7.2 12.0 mA

FCL = 32 kHz

F^MPL= 16 kHz

Sub clock mode

(divided by 2)

T^A= + 25 °C

I^CCL

⎯

45

10

100

81

µA

FCL = 32 kHz

F^MPL= 16 kHz

Sub sleep mode

(divided by 2)

T^A= + 25 °C

I^CCLS

⎯

µA

FCL = 32 kHz

Watch mode

Main stop mode

T^A= + 25 °C

I^CCT

4.6 27.0

(Continued)

34

MB95160M Series

(Continued)

(Vcc = 5.0 V 10%, Vss = 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit Remarks

Min

Typ

Max

F^CH= 4 MHz

F^MP= 10 MHz

Main PLL mode

(multiplied by 2.5)

⎯

9.3

12.5 mA

20.0 mA

ICCMPLL

F^CH= 6.4 MHz

F^MP= 16 MHz

Main PLL mode

(multiplied by 2.5)

⎯

14.9

160

VCC

FCL = 32 kHz

(External clock

I^CCSPLLoperation)

F^MPL= 128 kHz

Sub PLL mode

(multiplied by 4) ,

TA = + 25 °C

400

µA

Power supply

current*³

FCH = 10 MHz

Time-base timer

mode

I^CTS

0.15

1.10 mA

T^A= + 25 °C

Sub stop mode

T^A= + 25 °C

I^CCH

⎯

5

20

µA

FCH = 16 MHz

At operating of A/D

conversion

I^A

2.4

4.7

mA

AVCC

FCH = 16 MHz

At stopping of A/D

conversion

I^AH

⎯

1

5

µA

T^A= + 25 °C

LCD internal

division resistance

R^LCD

⎯

Between V3 and VSS

⎯

300

⎯

5

kΩ

COM0 to COM3

output impedance

R^VCOMCOM0 to COM3

R^VSEGSEG00 to SEG31

V1 to V3 = 5.0 V

SEG00 to SEG31

output impedance

⎯

7

V0 to V3,

LCD leak current

I^LCDLCOM0 to COM3

SEG00 to SEG31

⎯

− 1

⎯

+ 1

µA

*1 : The value is 2.88 V when the low voltage detection reset is used.

*2 : Product without clock supervisor only

*3 : • The power-supply current is determined by the external clock. When both low voltage detection option

and clock supervisor option are selected, the power-supply current will be a value of adding current

consumption of the low voltage detection circuit (I^LVD) and current consumption of built-in CR oscillator (ICSV)

to the specified value.

• Refer to “4. AC Characteristics (1) Clock Timing” for F^CHand FCL.

• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for F^MPand FMPL.

35

MB95160M Series

4. AC Characteristics

(1) Clock Timing

(Vcc = 2.42 V to 5.5 V, Vss = 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name Conditions

Unit

Remarks

Min

Typ

Max

When using main

oscillation circuit

1.00

⎯

16.25 MHz

1.00

3.00

⎯

32.50 MHz When using external clock

10.00 MHz Main PLL multiplied by 1

8.13 MHz Main PLL multiplied by 2

6.50 MHz Main PLL multiplied by 2.5

4.06 MHz Main PLL multiplied by 4

When using sub

F^CH

X0, X1

Clock frequency

⎯

32.768

⎯

kHz

oscillation circuit

F^CL

X0A, X1A

X0, X1

kHz When using sub PLL

⎯

When using oscillation

circuit

61.5

1000

ns

t^HCYL

Clock cycle time

30.8

⎯

1000

ns When using external clock

t^LCYLX0A, X1A

⎯

30.5

⎯

µs When using sub clock

t^WH1

tWL1

X0

61.5

⎯

15.2

⎯

5

ns

When using external clock

Duty ratio is about 30% to

70%.

Input clock pulse

width

t^WH2

X0A

tWL2

µs

Input clock rise time

and fall time

t^CR

X0, X0A

tCF

⎯

ns When using external clock

36

MB95160M Series

• Input wave form for using external clock (main clock)

tHCYL

tWH1

tWL1

tCR

tCF

0.8 VCC 0.8 VCC

X0

0.2 VCC

• Figure of Main Clock Input Port External Connection

When using a crystal or

ceramic oscillator

When using external clock

Microcontroller

X0

X1

X0

X1

Open

F^CH

C2

F^CH

C1

• Input wave form for using external clock (sub clock)

tLCYL

tWH2

tWL2

tCR

tCF

0.8 VCC 0.8 VCC

X0A

0.2 VCC

• Figure of Sub clock Input Port External Connection

When using a crystal or

ceramic oscillator

When using external clock

Microcontroller

X0A

X1A

X0A

X1A

Open

F^CL

C2

F^CL

C1

37

MB95160M Series

(2) Source Clock/Machine Clock

(Vcc = 5.0 V 10%, Vss = 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Typ

Sym- Condi-

Parameter

Unit

Remarks

bol tions

Min

Max

When using main clock

Min : F^CH= 8.125 MHz,

PLL multiplied by 2

Max : F^CH= 1 MHz, divided by 2

When using sub clock

61.5

⎯

2000

ns

Source clock cycle time*¹

(Clock before setting

division)

tSCLK

7.6

⎯

61.0

µs Min : F^CL= 32 kHz, PLL multiplied by 4

Max : F^CL= 32 kHz, divided by 2

F^SP

0.50

⎯

16.25 MHz When using main clock

131.072 kHz When using sub clock

When using main clock

Source clock frequency

F^SPL

16.384

⎯

61.5

7.6

⎯

32000

ns Min : FSP = 16.25 MHz, no division

Machine clock cycle

time*²

(Minimum instruction

execution time)

Max : F^SP= 0.5 MHz, divided by 16

t^MCLK

When using sub clock

976.5

µs Min : F^SPL= 131 kHz, no division

Max : F^SPL= 16 kHz, divided by 16

F^MP

0.031

1.024

⎯

16.250 MHz When using main clock

131.072 kHz When using sub clock

Machine clock

frequency

F^MPL

*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This

source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it

becomes the machine clock. Further, the source clock can be selected as follows.

• Main clock divided by 2

• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)

• Sub clock divided by 2

• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)

*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.

• Source clock (no division)

• Source clock divided by 4

• Source clock divided by 8

• Source clock divided by 16

38

MB95160M Series

• Outline of clock generation block

F

CH

Divided by 2

(main oscillation)

Main PLL

× 1

× 2

× 2.5

× 4

Division

circuit

× 1

× 1/4

× 1/8

× 1/16

SCLK

( source clock )

MCLK

( machine clock )

F

CL

Divided by 2

(sub oscillation)

Clock mode select bit

( SYCC : SCS1, SCS0 )

Sub PLL

× 2

× 3

× 4

39

MB95160M Series

• Operating voltage - Operating frequency (When T^A= − 40 °C to + 85 °C)

• MB95F168M/F168N/F168J

Sub PLL, sub clock mode and

watch mode operation guarantee range

Main clock mode and main PLL mode

operation guarantee range

5.5

3.5

2.42

0.5 MHz 3 MHz

10 MHz

16.25 MHz

16.384 kHz

32 kHz

131.072 kHz

PLL operation guarantee range

Main clock operation guarantee range

Source clock frequency (FSP)

Source clock frequency (FSPL)

• Operating voltage - Operating frequency (When T^A= + 5 °C to + 35 °C)

• MB95FV100D-103

Sub PLL, sub clock mode and

watch mode operation guarantee range

Main clock mode and main PLL mode

operation guarantee range

5.5

2.7

3.5

2.7

0.5MHz 3 MHz

10 MHz

16.25 MHz

16.384 kHz

32 kHz

131.072 kHz

PLL operation guarantee range

Main clock operation guarantee range

Source clock frequency (FSP)

40

MB95160M Series

• Main PLL operation frequency

[MHz]

16.25

16

15

× 4

12

10

× 2.5

× 1

× 2

7.5

6

5

3

[MHz]

10

0

3

4

5

6.4

6.5

8

4.062

8.125

Main clock frequency (FMP)

41

MB95160M Series

(3) External Reset

(Vcc = 5.0 V 10%, Vss = 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol

name

Condi-

tions

Parameter

Unit

Remarks

Min

Max

2 t^MCLK*¹

⎯

ns At normal operating

At stop mode,

Oscillation time of oscillator*²

sub clock mode,

sub sleep mode,

RST “L” level

pulse width

⎯

µs

t^RSTL

RST

⎯

+ 100

and watch mode

At time-base timer

mode

100

µs

*1 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation

time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of

µs and several ms. In the external clock, the oscillation time is 0 ms.

• At normal operating

tRSTL

RST

0.2 VCC

• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal

operating

clock

100 µs

Oscillation stabilization wait time

Oscillation

time of

oscillator

Execute instruction

Internal reset

42

MB95160M Series

(4) Power-on Reset

Parameter

(Vss = 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Symbol Pin name Conditions

Unit

Remarks

Min

Max

Power supply rising

time

t^R

⎯

50

ms

VCC

⎯

Powersupplycutoff

time

Waiting time until

power-on

t^OFF

1

⎯

tR

t

OFF

2.5 V

0.2 V

VCC

Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power

supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.

VCC

Limiting the slope of rising within

30 mV/ms is recommended.

2.3 V

Hold condition in stop mode

VSS

43

MB95160M Series

(5) Peripheral Input Timing

(Vcc = 5.0 V 10%, Vss = 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

Peripheral input

“H” pulse width

t^ILIH

t^IHIL

2 t^MCLK*

⎯

ns

INT00 to INT07,

EC0, EC1, TRG0/ADTG

⎯

Peripheral input

“L” pulse width

2 tMCLK*

⎯

* : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tILIH

tIHIL

INT00 to INT07,

EC0, EC1,

0.8 VCC 0.8 VCC

TRG0/ADTG

0.2 VCC

44

MB95160M Series

(6) UART/SIO, Serial I/O Timing

Parameter

(Vcc = 5.0 V 10%, Vss = 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Symbol

Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

UCK ↓ → UO time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

t^SHSL

t^SLSH

t^SLOV

t^IVSH

t^SHIX

UCK0

UCK0, UO0

UCK0, UI0

UCK0

4 t^MCLK*

− 190

ns

Internal clock

operation

+ 190

⎯

output pin : C^L= 80 pF

Valid UI → UCK ↑

2 tMCLK*

4 tMCLK*

⎯

+ 1TTL.

UCK ↑ → valid UI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

UCK ↓ → UO time

⎯

External clock

operation

UCK0

⎯

UCK0, UO0

UCK0, UI0

190

⎯

output pin : CL = 80 pF

Valid UI → UCK ↑

2 tMCLK*

+ 1TTL.

UCK ↑ → valid UI hold time

⎯

* : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

• Internal shift clock mode

tSCYC

2.4 V

UCK0

0.8 V

tSLOV

UO0

UI0

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

UCK0

tSLSH

tSHSL

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tSLOV

UO0

UI0

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

45

MB95160M Series

(7) LIN-UART Timing

Sampling at the rising edge of sampling clock*¹and prohibited serial clock delay*²

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)

(Vcc = 5.0 V 10%, Vss = 0.0 V, T^A= −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

5 t^MCLK*³

−95

Max

Serial clock cycle time

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SCYC

SCK

⎯

ns

Internal clock

operation output pin :

C^L= 80 pF + 1 TTL.

t^SLOVISCK, SOT

+ 95

t^IVSHI

t^SHIXI

t^SLSH

t^SHSL

SCK, SIN

SCK

tMCLK*³+ 190

⎯

SCK ↑ → valid SIN hold time

Serial clock “L” pulse width

Serial clock “H” pulse width

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

0

3 t^MCLK*³− tR

tMCLK*³+ 95

⎯

SCK

⎯

t^SLOVESCK, SOT

2 tMCLK*³+ 95

External clock

t^IVSHESCK, SIN operation output pin :

190

⎯

10

C^L= 80 pF + 1 TTL.

SCK ↑ → valid SIN hold time

SCK fall time

t^SHIXESCK, SIN

tMCLK*³+ 95

⎯

t^F

SCK

SCK rise time

t^R

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

46

MB95160M Series

• Internal shift clock mode

t

SCYC

2.4 V

SCK

0.8 V

t

SLOVI

2.4 V

SOT

SIN

0.8 V

t

IVSHI

tSHIXI

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

SCK

tSHSL

tSLSH

0.8 VCC

0.2 VCC

t

R

t

F

t

SLOVE

2.4 V

0.8 V

SOT

SIN

t

IVSHE

t

SHIXE

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

47

MB95160M Series

Sampling at the falling edge of sampling clock*¹and prohibited serial clock delay*²

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)

(V^CC= 5.0 V 10%, VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

5 t^MCLK*³

−95

Max

Serial clock cycle time

SCK↑→ SOT delay time

Valid SIN→SCK↓

t^SCYC

t^SHOVI

t^IVSLI

t^SLIXI

t^SHSL

t^SLSH

SCK

SCK, SOT

SCK, SIN

SCK

⎯

ns

Internal clock

operation output pin :

C^L= 80 pF + 1 TTL.

+ 95

tMCLK*³+ 190

⎯

SCK↓→ valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK↑ →SOT delay time

Valid SIN→SCK↓

0

3 t^MCLK*³− tR

tMCLK*³+ 95

⎯

SCK

⎯

t^SHOVESCK, SOT

2 tMCLK*³+ 95

External clock

t^IVSLE

t^SLIXE

t^F

SCK, SIN operation output pin :

190

⎯

10

C^L= 80 pF + 1 TTL.

SCK↓→ valid SIN hold time

SCK fall time

SCK, SIN

tMCLK*³+ 95

⎯

SCK

SCK rise time

t^R

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of

the serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

48

MB95160M Series

• Internal shift clock mode

SCK

t

SCYC

2.4 V

0.8 V

t

SHOVI

2.4 V

0.8 V

SOT

SIN

tSLIXI

tIVSLI

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

SCK

tSHSL

tSLSH

0.8 VCC

0.2 VCC

tF

t

R

tSHOVE

2.4 V

0.8 V

SOT

SIN

tIVSLE

tSLIXE

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

49

MB95160M Series

Sampling at the rising edge of sampling clock*¹and enabled serial clock delay*²

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)

(V^CC= 5.0 V 10%, VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

SCK↑→ SOT delay time

Valid SIN→SCK↓

t^SCYC

t^SHOVI

t^IVSLI

SCK

5 t^MCLK*³

ns

SCK, SOT

−95

+ 95

⎯

Internal clock

SCK, SIN operation output pin : tMCLK*³+ 190

C^L= 80 pF + 1 TTL.

SCK↓→ valid SIN hold time

SOT→SCK↓ delay time

t^SLIXI

SCK, SIN

SCK, SOT

0

⎯

4 tMCLK*³

t^SOVLI

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of

the serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tSCYC

2.4 V

SCK

0.8 V

tSHOVI

t

SOVLI

2.4 V

0.8 V

2.4 V

0.8 V

SOT

SIN

tSLIXI

tIVSLI

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

50

MB95160M Series

Sampling at the falling edge of sampling clock*¹and enabled serial clock delay*²

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)

(V^CC= 5.0 V 10%, VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

SCK↓→SOT delay time

Valid SIN→SCK↑

t^SCYC

t^SLOVI

t^IVSHI

t^SHIXI

t^SOVHI

SCK

5 t^MCLK*³

ns

SCK, SOT

−95

+ 95

⎯

Internal clock

SCK, SIN operation output pin : tMCLK*³+ 190

C^L= 80 pF + 1 TTL.

SCK↑ → valid SIN hold time

SOT→SCK↑ delay time

SCK, SIN

SCK, SOT

0

⎯

4 tMCLK*³

⎯

*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the

serial clock.

*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.

*3 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tSCYC

2.4 V

SCK

0.8 V

tSOVHI

t^SLOVI

2.4 V

0.8 V

2.4 V

0.8 V

SOT

SIN

tSHIXI

tIVSHI

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

51

MB95160M Series

(8) I²C Timing

(V^CC= 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Conditions Standard-mode

name

Parameter

Symbol

Fast-mode

Unit

Min

Max

Min

Max

SCL clock frequency

f^SCL

SCL0

0

100

0

400

kHz

(Repeat) Start condition hold time

SDA ↓ → SCL ↓

SCL0

SDA0

t^HD;STA

4.0

⎯

0.6

⎯

µs

SCL clock “L” width

SCL clock “H” width

t^LOW

t^HIGH

SCL0

4.7

4.0

⎯

1.3

0.6

⎯

µs

(Repeat) Start condition setup time

SCL ↑ → SDA ↓

SCL0

SDA0

t^SU;STA

t^HD;DAT

4.7

0

⎯

3.45*²

⎯

0.6

0

⎯

0.9*³

⎯

µs

R = 1.7 kΩ,

C = 50 pF*¹

SCL0

SDA0

Data hold time SCL ↓ → SDA ↓ ↑

SCL0

SDA0

Data setup time SDA ↓ ↑ → SCL ↑ t^SU;DAT

0.25*⁴

4.0

0.1*⁴

0.6

1.3

Stop condition setup time

t^SU;STO

SCL0

SDA0

⎯

SCL ↑ → SDA ↑

Bus free time between stop

t^BUF

SCL0

SDA0

4.7

⎯

condition and start condition

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t^HD;DAThave only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.

*3 : A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement

t^SU;DAT≥ 250 ns must then be met.

*4 : Refer to “ • Note of SDA and SCL set-up time”.

• Note of SDA and SCL set-up time

SDA0

Input data set-up time

SCL0

6 tcp

Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on

the load capacitance or pull-up resistor.

Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be

satisfied.

52

MB95160M Series

t^WAKEUP

SDA0

SCL0

tHD;STA

tHD;DAT

tHIGH

tBUF

tLOW

tSU;STO

tHD;STA

tSU;DAT

tSU;STA

53

MB95160M Series

(V^CC= 5.0 V 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value*²

Sym- Pin

bol name

Condi-

tions

Parameter

Unit

Remarks

Min

Max

SCL clock

“L” width

(2 + nm / 2) tMCLK − 20

t^LOWSCL0

t^HIGHSCL0

⎯

ns Master mode

SCL clock

“H” width

(nm / 2) tMCLK − 20

(nm / 2 ) tMCLK + 20

ns Master mode

Master mode

Maximum value is

applied when m,

ns n = 1, 8.

Start condition

hold time

SCL0

t^HD;STA

(−1 + nm / 2) tMCLK − 20

(−1 + nm) tMCLK + 20

SDA0

Otherwise, the

minimum value is

applied.

Stop condition

setup time

SCL0

t^SU;STO

(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns Master mode

SDA0

Start condition

setup time

SCL0

t^SU;STA

SDA0

Bus free time

between stop

condition and

start condition

SCL0

t^BUF

(2 nm + 4) tMCLK − 20

3 tMCLK − 20

⎯

ns

SDA0

SCL0

SDA0

Data hold time t^HD;DAT

ns Master mode

Master mode

R = 1.7 kΩ,

C = 50 pF*¹

When assuming

that “L” of SCL is

not extended, the

minimum value is

Data setup

t^SU;DAT

SCL0

SDA0

(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns applied to first bit

time

of continuous

data.

Otherwise,

the maximum

value is applied.

Minimum value is

appliedtointerrupt

at 9th SCL↓.

Maximum value is

appliedtointerrupt

at 8th SCL↓.

Setup time

between

clearing

interrupt and

SCL rising

t^SU;INTSCL0

(nm / 2) tMCLK − 20

(1 + nm / 2) tMCLK + 20 ns

SCL clock “L”

width

4 tMCLK − 20

t^LOWSCL0

t^HIGHSCL0

⎯

ns At reception

SCL clock “H”

width

Undetected when

ns 1 tMCLK is used at

reception

Start condition

detection

SCL0

t^HD;STA

2 tMCLK − 20

⎯

SDA0

(Continued)

54

MB95160M Series

(Continued)

(V^CC= 5.0 V 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)

Value*²

Sym- Pin

bol name

Condi-

tions

Parameter

Unit

Remarks

Min

Max

Undetected when 1

ns tMCLK is used at

reception

Stop condition

detection

SCL0

t^SU;STO

2 tMCLK − 20

⎯

SDA0

Undetected when 1

ns tMCLK is used at

reception

Restart condition

detection condition

SCL0

t^SU;STA

2 tMCLK − 20

⎯

SDA0

SCL0

t^BUF

Bus free time

2 tMCLK − 20

tLOW − 3 tMCLK − 20

0

⎯

ns At reception

SDA0

SCL0

t^HD;DAT

At slave transmission

mode

Data hold time

Data setup time

Data hold time

Data setup time

ns

SDA0

R = 1.7 kΩ,

C = 50 pF*¹

SCL0

t^SU;DAT

At slave transmission

mode

ns

SDA0

SCL0

t^HD;DAT

ns At reception

SDA0

SCL0

t^SU;DAT

tMCLK − 20

SDA0

Oscillation

stabilization

wait time +

2 t^MCLK− 20

SDA↓→SCL↑

(at wakeup function)

t^WAKE-SCL0

⎯

ns

UP

SDA0

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : • Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

• m is CS4 bit and CS3 bit (bit 4 and bit 3) of I²C clock control register (ICCR) .

• n is CS2 bit to CS0 bit (bit 2 to bit 0) of I²C clock control register (ICCR) .

• Actual timing of I²C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of

ICCR0 register.

• Standard-mode :

m and n can be set at the range : 0.9 MHz < t^MCLK(machine clock) < 10 MHz.

Setting of m and n determines the machine clock that can be used below.

(m, n) = (1, 8)

: 0.9 MHz < t^MCLK≤ 1 MHz

(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < t^MCLK≤ 2 MHz

(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < t^MCLK≤ 4 MHz

(m, n) = (1, 98)

• Fast-mode :

: 0.9 MHz < t^MCLK≤ 10 MHz

m and n can be set at the range : 3.3 MHz < t^MCLK(machine clock) < 10 MHz.

Setting of m and n determines the machine clock that can be used below.

(m, n) = (1, 8)

(m, n) = (1, 22) , (5, 4)

(m, n) = (6, 4)

: 3.3 MHz < t^MCLK≤ 4 MHz

: 3.3 MHz < t^MCLK≤ 8 MHz

: 3.3 MHz < t^MCLK≤ 10 MHz

55

MB95160M Series

(9) Low Voltage Detection

(Vss = 0.0 V, T^A= −10 °C to + 85 °C)

Value

Typ

2.70

2.60

100

⎯

Sym- Condi-

Parameter

Release voltage

Unit

Remarks

bol

tions

Min

2.52

2.42

70

Max

2.88

2.78

⎯

V^DL+

V^DL-

V^HYS

V^off

V

At power-supply rise

At power-supply fall

Detection voltage

Hysteresis width

mV

V

Power-supply start voltage

Power-supply end voltage

⎯

2.3

V^on

4.9

⎯

V

Slope of power supply that reset

release signal generates

0.3

⎯

3000

⎯

µs

Power-supply voltage

change time

(at power supply rise)

t^r

Slope of power supply that reset

⎯

µs release signal generates within

⎯

rating (V^DL+)

Slope of power supply that reset

detection signal generates

300

⎯

µs

Power-supply voltage

change time

(at power supply fall)

t^f

Slope of power supply that reset

µs detection signal generates within

rating (V^DL-)

300

Reset release delay time

Reset detection delay time

t^d1

t^d2

⎯

400

30

µs

Current consumption of low

µA

Current consumption

I^LVD

⎯

38

50

voltage detection circuit only

Vcc

Von

Voff

Vcc

Time

tr

tf

VDL+

VDL-

VHYS

Internal reset signal

Time

td1

td2

56

MB95160M Series

(10) Clock Supervisor Clock

(Vcc = 5.0 V 10%, Vss = 0.0 V, T^A= −40 °C to + 85 °C)

Value

Condi-

tions

Parameter

Symbol

Unit

Remarks

Min

50

Typ

100

⎯

Max

200

10

Oscillation frequency

Oscillation start time

f^OUT

t^wk

kHz

⎯

µs

⎯

Current consumption of

built-in CR oscillator, at

100 kHz oscillation

Current consumption

I^CSV

⎯

20

36

µA

57

MB95160M Series

5. A/D Converter

(1) A/D Converter Electrical Characteristics

(AV^CC= VCC = 4.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Typ

⎯

Sym- Condi-

Parameter

Unit

Remarks

bol

tions

Min

⎯

Max

10

Resolution

Total error

bit

− 3.0

− 2.5

⎯

+ 3.0

+ 2.5

LSB

⎯

Linearity error

⎯

Differential

linear error

− 1.9

⎯

+ 1.9

LSB

Zero

transition

voltage

V^OT

AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB

AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB

V

Full-scale

transition

voltage

V^FST

V

0.9

1.8

⎯

16500

µs 4.5 V ≤ AVcc ≤ 5.5 V

µs 4.0 V ≤ AVcc < 4.5 V

Compare time

⎯

4.5 V ≤ AVcc ≤ 5.5 V,

µs At external

⎯

0.6

1.2

⎯

∞

impedance < 5.4 kΩ

Sampling time

⎯

4.0 V ≤ AVcc < 4.5 V,

µs At external

impedance < 2.4 kΩ

Analog input

current

I^AIN

V^AIN

⎯

− 0.3

AVSS

⎯

+ 0.3

AVR

AVCC

900

5

µA

Analog input

voltage

V

Reference

voltage

AV^SS+ 4.0

⎯

V

AVR pin

AVR pin,

during A/D operation

I^R

600

⎯

µA

Reference

voltage supply

current

AVR pin,

at stop mode

I^RH

⎯

58

MB95160M Series

(2) Notes on Using A/D Converter

• About the external impedance of analog input and its sampling time

A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/

D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship

between the external impedance and minimum sampling time and either adjust the register value and operating

frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,

if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• Analog input equivalent circuit

R

Analog input

Comparator

C

During sampling : ON

R

C

4.5 V ≤ V^CC≤ 5.5 V

4.0 V ≤ V^CC< 4.5 V

2.0 kΩ (Max)

8.2 kΩ (Max)

16 pF (Max)

Note : The values are reference values.

• The relationship between external impedance and minimum sampling time

(External impedance = 0 kΩ to 20 kΩ)

(External impedance = 0 kΩ to 100 kΩ)

100

20

18

90

VCC ≥ 4.5 V

80

16

VCC ≥ 4.5 V

70

14

60

12

V^CC≥ 4.0 V

50

10

40

30

20

10

0

8

6

4

2

0

8

14

0

2

4

6

10

12

0

1

2

3

4

Minimum sampling time [µs]

• About errors

As |V^CC− VSS| becomes smaller, values of relative errors grow larger.

59

MB95160M Series

(3) Definition of A/D Converter Terms

• Resolution

The level of analog variation that can be distinguished by the A/D converter.

When the number of bits is 10, analog voltage can be divided into 2¹⁰= 1024.

• Linearity error (unit : LSB)

The deviation between the value along a straight line connecting the zero transition point

(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point

(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.

• Differential linear error (Unit : LSB)

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

• Total error (unit: LSB)

Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,

linearity error, quantum error, and noise.

Ideal I/O characteristics

Total error

VFST

3FFH

3FEH

3FDH

3FF^H

3FEH

3FDH

Actual conversion

characteristic

1.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

004H

003H

002H

001H

004H

003H

002H

001H

VNT

V^OT

Actual conversion

characteristic

1 LSB

0.5 LSB

Ideal characteristics

VSS

VCC

Analog input

Total error of

digital output N

V^CC− Vss

1024

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

=

1 LSB =

(V)

[LSB]

1 LSB

N

: A/D converter digital output value

V^NT: A voltage at which digital output transits from (N − 1) H to NH

(Continued)

60

MB95160M Series

(Continued)

Full-scale transition error

Zero transition error

004H

Ideal characteristics

Actual conversion

characteristic

3FFH

3FEH

3FDH

3FCH

Actual conversion

characteristic

003H

002H

001H

Ideal

characteristics

VFST

(measurement

value)

Actual conversion

characteristic

Actual conversion

characteristic

VOT (measurement value)

VSS

VCC

VSS

VCC

Analog input

Linearity error

Differential linear error

Ideal characteristics

Actual conversion

characteristic

3FFH

3FEH

3FDH

(N+1)H

NH

Actual conversion

{1 LSB × N + VOT}

characteristic

V (N+1)T

V^FST

(measurement

value)

V^NT

004H

003H

002H

001H

(N-1)H

(N-2)H

VNT

Actual conversion

characteristic

Actual conversion

characteristic

Ideal characteristics

VOT (measurement value)

VSS

VCC

VSS

VCC

Analog input

Linearity error in

digital output N

V^NT− {1 LSB × N + VOT}

V ^(N+ 1) T − VNT

Differential linear error

in digital output N

=

− 1

1 LSB

N

: A/D converter digital output value

V^NT: A voltage at which digital output transits from (N − 1) H to NH

VOT (Ideal value) = VSS + 0.5 LSB [V]

V^FST(Ideal value) = VCC − 1.5 LSB [V]

61

MB95160M Series

6. Flash Memory Program/Erase Characteristics

Value

Condi-

tions

Parameter

Unit

Remarks

Min

Typ

Max

Excludes 00^Hprogramming

prior erasure.

Chip erase time

⎯

1*¹

15*²

s

Excludes system-level

overhead.

Byte programming time

Erase/program cycle

⎯

10000

4.5

32

⎯

3600

⎯

µs

cycle

V

⎯

Power supply voltage at

erase/program

5.5

Flash memory data retention

time

20*³

⎯

year Average TA = + 85 °C

*1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles

*2 : T^A= + 85 °C, VCC = 4.5 V, 10000 cycles

*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at +85 °C) .

62

MB95160M Series

■ EXAMPLE CHARACTERISTICS

• Power supply current temperature

ICC − VCC

I^CC− TA

TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)

Main clock mode, at external clock operating

VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)

Main clock mode, at external clock operating

20

15

F

MP = 16 MHz

MP = 10 MHz

F

MP = 16 MHz

MP = 10 MHz

10

5

10

5

F

MP = 8 MHz

F

MP = 4 MHz

FMP = 2 MHz

0

-50

0

+50

[°C]

+100

+150

2

3

4

5

6

7

VCC [V]

T

A

I^CCS− VCC

I^CCS− TA

TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)

VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)

Main sleep mode, at external clock operating

20

15

10

20

15

10

F

MP = 16 MHz

MP = 10 MHz

F

MP =16 MHz

=10 MHz

5

0

FM^MP^P= 8 MHz

F

FM^MP^P= 2 MHz

F

= 4 MHz

0

-50

0

+50

[°C]

+100

+150

2

3

4

5

6 7

V

CC [V]

T

A

I^CCMPLL− VCC

I^CCMPLL− TA

TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz

VCC = 5.5 V, FMP = 10, 16 MHz (Main PLL multiplied by 2.5)

(Main PLL multiplied by 2.5)

Main PLL mode, at external clock operating

20

15

F

MP = 16 MHz

MP = 10 MHz

F

MP = 16 MHz

10

5

10

5

F

MP = 10 MHz

MP = 8 MHz

F

MP = 4 MHz

MP = 2 MHz

0

-50

0

+50

[°C]

+100

+150

2

3

4

5

6

7

V

CC [V]

T

A

(Continued)

63

MB95160M Series

ICCL − VCC

ICCL − TA

TA = + 25 °C, FMPL = 16 kHz (divided by 2)

Sub clock mode, at external clock operating

VCC = 5.5 V, FMPL = 16 kHz (divided by 2)

Sub clock mode, at external clock operating

100

75

50

25

0

75

50

25

0

2

3

4

5

6

7

−50

0

+50

[°C]

+100

+150

V

CC [V]

T

A

I^CCLS− VCC

I^CCLS− TA

TA = + 25 °C, FMPL = 16 kHz (divided by 2)

VCC = 5.5 V, FMPL = 16 kHz (divided by 2)

Sub sleep mode, at external clock operating

100

75

50

25

0

75

50

25

0

2

3

4

5

6

−50

0

+50

+100

+150

VCC [V]

T

A

[°C]

ICCT − VCC

I^CCT− TA

TA = + 25 °C, FMPL = 16 kHz (divided by 2)

VCC = 5.5 V, FMPL = 16 kHz (divided by 2)

Clock mode, at external clock operating

100

75

50

25

0

75

50

25

0

2

3

4

5

6

−50

0

+50

[°C]

+100

+150

VCC [V]

T

A

(Continued)

64

MB95160M Series

ICCSPLL − VCC

ICCSPLL − TA

TA = + 25 °C, FMPL = 128 kHz (Main PLL multiplied by 4)

Sub PLL mode, at external clock operating

VCC = 5.5 V, FMPL = 128 kHz (Main PLL multiplied by 4)

Sub PLL mode, at external clock operating

200

175

150

125

100

75

200

175

150

125

100

75

50

25

0

2

3

4

5

6

7

−50

0

+50

[°C]

+100

+150

VCC [V]

T

A

I^CTS− VCC

I^CTS− TA

TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)

VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)

Time-base timer mode, at external clock operating

2.0

1.5

FMP = 16 MHz

1.0

0.5

0.0

1.0

F

MP = 10 MHz

MP = 8 MHz

FMP = 10 MHz

F

MP = 4 MHz

MP = 2 MHz

0.5

0.0

2

3

4

5

6

7

−50

0

+50

T^A[°C]

+100

+150

VCC [V]

ICCH − VCC

I^CCH− TA

VCC = 5.5 V, FMPL = (stop)

Sub stop mode, at external clock stopping

TA = + 25 °C, FMPL = (stop)

Sub stop mode, at external clock stopping

20

15

10

5

15

10

5

0

2

3

4

5

6

7

−50

0

+50

A [°C]

+100

+150

VCC [V]

T

(Continued)

65

MB95160M Series

(Continued)

IA − AVCC

I^A− TA

TA = + 25 °C, FMP = 16 MHz (divided by 2)

Main clock mode, at external clock operating

VCC = 5.5 V, FMP = 16 MHz (divided by 2)

Main clock mode, at external clock operating

4

3

2

1

0

3

2

1

0

2

3

4

5

6

7

−50

0

+50

+100

+150

AV^CC[V]

T

A

[°C]

I^R− AVCC

I^R− TA

TA = + 25 °C, FMP = 16 MHz (divided by 2)

VCC = 5.5 V, FMP = 16 MHz (divided by 2)

Main clock mode, at external clock operating

4

3

2

1

0

3

2

1

0

2

3

4

5

6

7

−50

0

+50

T^A[°C]

+100

+150

AV^CC[V]

66

MB95160M Series

• Input voltage

VIH1 − VCC and VIL − VCC

TA = + 25 °C

V^IHS1− VCC and VILS − VCC

TA = + 25 °C

5

4

3

2

1

5

4

3

2

1

0

V

IHS1

ILS

V

IH1

V

IL

0

2

3

4

5

6

7

2

3

4

5

6

7

V

CC [V]

VCC [V]

V^IH2− VCC and VIL − VCC

TA = + 25 °C

V^IHS2− VCC and VILS − VCC

TA = + 25 °C

5

4

3

2

1

5

4

3

2

1

0

V

IHS2

V

IH2

VIL

V

ILS

0

2

3

4

5

6

3

4

5

6

VCC [V]

V^IHA− VCC and VILA − VCC

TA = + 25 °C

VIHM − VCC and VILM − VCC

TA = + 25 °C

5

4

3

2

1

5

4

3

2

1

0

VIHA

VILA

V

IHM

ILM

V

0

2

3

4

5

6

3

4

5

6

VCC [V]

67

MB95160M Series

• Output voltage

VOH1 − IOH

TA = + 25 °C

1.0

0.8

0.6

0.4

0.2

V

CC = 4 V

VCC = 4.5 V

VCC = 5.0 V

VCC = 5.5 V

VCC = 2.45 V

0.0

0

-2

-4

-6

OH [mA]

-8

-10

I

V^OL1− IOL

TA = + 25 °C

VOL2 − IOL

TA = + 25 °C

1.0

VCC = 3.3 V

1.0

V

CC = 2.5 V

V

CC = 3.5 V

0.8

0.6

0.4

0.2

0.0

VCC = 2.5 V

VCC = 4.0 V

V

CC = 2.7 V

V

= 4.5 V

^CC= 5.0 V

C^CC^C= 5.5 V

0.6

0.4

0.2

0.0

CC = 3.0 V

CC = 3.3 V

CC = 3.5 V

= 4.0 V

^CC= 5.0 V

C^CC^C= 2.5 V

V

CC = 2.45 V

0.0

2.0

4.0

I

6.0

OL [mA]

8.0

10.0

0

2

4

6

8

10

IOL [mA]

• Pull-up

RPULL − VCC

TA = + 25 °C

250

200

150

100

50

0

2

3

4

5

6

VCC [V]

68

MB95160M Series

■ MASK OPTION

Part number

Specifying procedure

Clock mode select*

MB95F168M/F168N/F168J

Setting disabled

MB95FV100D-103

Setting disabled

No.

1

• Single-system clock mode

Dual-system clock mode

Specified by part number

Changing by the switch on MCU board

• Dual-system clock mode

Low voltage detection reset*

• With low voltage detection reset

• Without low voltage detection

reset

2

3

Clock supervisor*

• With clock supervisor

• Without clock supervisor

MCU board switch sets as follows;

• With clock supervisor:

Without reset output

Reset output*

• With reset output

• Without reset output

4

5

Specified by part number

• Without clock supervisor:

With reset output

Fixed to oscillation stabilization Fixed to oscillation stabilization wait

Oscillation stabilization wait time

wait time of (2¹⁴− 2) /FCH

time of (2¹⁴− 2) /FCH

* : Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset output.

Part number

MB95F168M

Clock mode select Low voltage detection reset Clock supervisor Reset output

No

Yes

No

Yes

No

Dual-system

Single-system

Dual-system

MB95F168N

MB95F168J

Yes

No

Yes

No

Yes

No

Yes

No

MB95FV100D-103

Yes

No

Yes

No

Yes

69

MB95160M Series

■ ORDERING INFORMATION

Part number

Package

MB95F168MPMC

MB95F168NPMC

MB95F168JPMC

64-pin plastic LQFP

(FPT-64P-M23)

MB95F168MPMC1

MB95F168NPMC1

MB95F168JPMC1

64-pin plastic LQFP

(FPT-64P-M024)

MCU board

224-pin plastic PFBGA

MB2146-303A

(MB95FV100D-103PBT)

(

)

(BGA-224P-M08)

70

MB95160M Series

■ PACKAGE DIMENSIONS

64-pin plastic LQFP

Lead pitch

0.65 mm

12.0 × 12.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Plastic mold

1.70 mm MAX

P-LFQFP64-12×12-0.65

Code

(Reference)

(FPT-64P-M23)

64-pin plastic LQFP

(FPT-64P-M23)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

14.00 0.20(.551 .008)SQ

*12.00 0.10(.472 .004)SQ

0.145 0.055

(.0057 .0022)

48

33

49

32

0.10(.004)

Details of "A" part

1.50 ^–⁺⁰⁰^.^.¹²⁰⁰

(Mounting height)

.059 ^–⁺^.^.⁰⁰⁰⁰⁴⁸

0.25(.010)

INDEX

0~8˚

64

17

0.50 0.20

(.020 .008)

0.10 0.10

(.004 .004)

(Stand off)

"A"

1

16

0.60 0.15

(.024 .006)

0.65(.026)

0.32 0.05

(.013 .002)

M

0.13(.005)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2003 FUJITSU LIMITED F64034S-c-1-1

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

(Continued)

71

MB95160M Series

(Continued)

64-pin plastic LQFP

Lead pitch

0.50 mm

10.0 × 10.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm MAX

0.32g

Code

(Reference)

P-LFQFP64-10×10-0.50

(FPT-64P-M24)

64-pin plastic LQFP

(FPT-64P-M24)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

12.00 0.20(.472 .008)SQ

*

10.00 0.10(.394 .004)SQ

0.145 0.055

(.006 .002)

48

33

49

32

Details of "A" part

0.08(.003)

1.50 ⁺^–0⁰^.^.¹²⁰⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

INDEX

0.10 0.10

(.004 .004)

(Stand off)

0˚~8˚

64

17

"A"

0.25(.010)

0.50 0.20

(.020 .008)

1

16

LEAD No.

0.60 0.15

(.024 .006)

0.50(.020)

0.20 0.05

(.008 .002)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2005 FUJITSU LIMITED F64036S-c-1-1

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

72

MB95160M Series

■ MAIN CHANGES (The Main Changes from the First Edition to This Edition)

Page

⎯

Section

Change Results

⎯

Preliminary Data Sheet → Data Sheet

22

■ I/O MAP

Changed as follows for R/W of Reset factor register

R → R/W

29

31

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

The Min value in the row of “Operating temperature” is

changed as follows;

− 40 → − 10

■ ELECTRICAL CHARACTERISTICS

The Min value in the row of “Operating temperature” is

2. Recommended Operating Conditions changed as follows;

− 40 → − 10

36

38

4. AC Characteristics (1) Clock Timing Added “Main PLL multiplied by 4” in the Clock frequency

(2) Source Clock/Machine Clock

• Changed in the remarks of source clock cycle time

(when using main clock)

Min : F^CH= 16.25 MHz, PLL multiplied by 1 →

Min : F^CH= 8.125 MHz, PLL multiplied by 2

• Changed the footnote of *1;

PLL multiplication of main clock (select from 1, 2, 2.5

multiplication) → PLL multiplication of main clock

(select from 1, 2, 2.5, 4 multiplication)

39

41

• Added “ × 4” in the Main PLL of “• Outline of clock

generation block”

Changed the figure of “• Main PLL operation frequency”

Added the characteristics

52 to 55 (8) I²C Timing

63 to 68 ■ EXAMPLE CHARACTERISTICS

Added the ■ EXAMPLE CHARACTERISTICS

The vertical lines marked in the left side of the page show the changes.

73

MB95160M Series

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

The company names and brand names herein are the trademarks or

registered trademarks of their respective owners.

Edited

Business Promotion Dept.

F0709


型号：	MB2146-303A
厂家：	FUJITSU
描述：	8-bit Microcontroller 8位微控制器微控制器
文件：	总74页 (文件大小：1443K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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