MB39C022LPNE1_技术文档

FUJITSU MICROELECTRONICS

DATA SHEET

DS04-27271-2E

ASSP for Power Management Applications

Buck DC/DC Converter +

Low noise LDO

MB39C022G/MB39C022J/MB39C022L

MB39C022N

■ DESCRIPTION

The MB39C022 is a 2 channels power supply IC. It consists of one channel Buck DC/DC Converter and one

channel LDO regulator. The DC/DC converter has fast transient response with current mode control topology.

Moreover, the integrated LDO provides an auxiliary output supply for noise sensitive circuit.

■ FEATURES

• Power supply voltage range

: 2.5 V to 5.5 V

• For Buck DC/DC included SW FET (CH1) : output 0.8 V to 4.5 V, 600 mA Max DC

• For LDO (CH2)

: output 3.30 V (MB39C022G) 300 mA Max DC

output 2.85 V (MB39C022J) 300 mA Max DC

output 1.80 V (MB39C022L) 300 mA Max DC

output 1.20 V (MB39C022N) 300 mA Max DC

: 0.3 V (2.5%) (CH1)

• Error amplifier threshold voltage

• Fast line transient response with current mode topology (CH1)

• PFM mode at light load current with VO1/VIN1 ≤ 80% (IO1 ≤ 10 mA) (CH1)

• Power-on-reset with 66 ms delay (CH1)

• Built-in short circuit protect (CH2)

• Built-in over current protect (CH1, CH2)

• Built-in thermal protection function

• Small size plastic SON-10 (3 mm × 3 mm) package

■ APPLICATIONS

• Portable Equipment

• PND, GPS

• PMP

• Mobile TV, USB-dongle (CMMB, DVB-T, DMB-T)

• Smart-phone

• MP3

2009.11

MB39C022

■ PIN ASSIGNMENT

(TOP VIEW)

GND1

10

LX

9

VIN1

EN1

7

FB

6

8

1

2

3

4

5

EN2

VIN2

VOUT2

POR

GND2

(LCC-10P-M04)

■ PIN DESCRIPTIONS

Block

CH1 (Buck DC/DC)

CH2 (LDO)

Pin No.

Pin name

I/O

Descriptions

6

9

FB

LX

I

CH1 Error Amplifier input pin

CH1 Inductor connection pin

CH2 LDO output pin

O

I

3

VOUT2

EN1

7

CH1 Control pin (L : shutdown / H : operation)

CH2 Control pin (L : shutdown / H : operation)

CH1 Power supply pin

Control

1

EN2

I

8

VIN1

VIN2

GND1

GND2

POR

⎯

O

2

CH2 Power supply pin

Power

10

5

CH1 Ground pin

CH2 Ground pin

Power-on Reset

4

CH1 Power on reset output pin (NMOS open drain)

2

DS04-27271-2E

MB39C022

■ I/O TERMINAL EQUIVALENT CIRCUIT DIAGRAM

VIN1

EN∗

POR

∗

GND2

VIN1

∗

LX

FB

∗

GND1

GND2

VIN2

∗

VOUT2

GND2

* : ESD Protection device

DS04-27271-2E

3

MB39C022

■ BLOCK DIAGRAM

<<CH1 Buck DC/DC>>

VIN1

LX

Error

Amp.

6

8

9

FB

IO1 (600 mA Max)

VO1 (0.8 V to 4.5 V)

ICOMP

PFM

PWM

Logic

DRV

Control

Current

Limit

LEVEL

CONV.

OSC

GND1

10

VIN or VO1

POR

<<CH2: LDO>>

VIN2

2

3

Error

Amp.

4

VOUT2

POR

IO2 (300 mA Max)

VO2

3.3 V: MB39C022G

2.85 V: MB39C022J

1.8 V: MB39C022L

1.2 V: MB39C022N

OCP/SCP

VIN

GND2

(2.5 V to 5.5 V)

5

OTP

VREF

UVLO

EN1

EN2

7

1

enb1 (H: CH1 ON)

enb2 (H: CH2 ON)

<<10 PIN>>

4

DS04-27271-2E

MB39C022

■ FUNCTION DESCRIPTIONS

(1) PFM/PWM Logic Control Block (CH1)

The built-in P-ch and N-ch MOS FETs are controlled for synchronization rectification according to the frequency

(2.0 MHz) oscillated from the built-in oscillator (square wave oscillation circuit). Under light load, it operates

intermittently.

This circuit protects the through current caused by synchronous rectification and the reverse current in

Discontinuous Conduction Mode.

Since the PWM control circuit of this IC is in the control method in current mode, the current peak value is

monitored and controlled as required.

(2) Level converter and Iout Comparator circuit (CH1)

The Level converter circuit detects the current (ILX) which flows to the external inductor from the built-in P-ch

MOS FET. By comparing VIDET obtained through I-V conversion of peak current I^PKof ILX with the Error Amp.

output, the Iout Comparator turns off the built-in P-ch MOS FET via the PWM Logic Control circuit.

(3) Error Amp. circuit (CH1)

The error amplifier (Error Amp.) detects the output voltage from the DC/DC converter and output to the current

comparators (ICOMP). The output voltage setting resistor externally connected to FB allows an arbitrary output

voltage to be set.

(4) LDO Block (CH2)

The integrated low noise low dropout regulator (LDO) is available up to 300 mA current capability and 700 mA

over current protection (OCP) 350 mA short circuit protection (SCP). The LDO output VOUT2 requires a 4.7 μF

capacitor for MB39C022G and MB39C022N and a 1.0 μF capacitor for MB39C022J and MB39C022L for stability.

MB39C022G, MB39C022J, MB39C022L and MB39C022N have fixed 3.3 V, 2.85 V, 1.8 V and 1.2 V output

voltages respectively, eliminating the need for an external resistor divider.

(5) POR Block

The POR circuit monitors the VO1 through the FB pin voltage. When the FB pin voltage reaches 97% of V^FBTH,

POR pin becomes high level after the hold time of 66 ms. The POR pin is an open-drain output and pulled up

to VIN or VO1 with an external resistor.

Timing Chart : (POR pin pulled up to VIN with resistor)

VUVLO

VIN

EN1

VTH × 97%

FB

POR

thold

VUVLO : UVLO threshold voltage (VTLH = 2.050 V)

V^TH: FB pin threshold voltage (VTH = 0.3 V)

DS04-27271-2E

5

MB39C022

(6) Reference Voltage Block (VREF)

A high accuracy reference voltage is generated with BGR (bandgap reference) circuit.

(7) Under Voltage Lockout Protection Circuit Block (UVLO)

The circuit protects against IC malfunction and system destruction/deterioration in a transitional state or a

momentary drop of when the internal reference voltage starts. It detects a voltage drop at the VIN1 pin and stops

IC operation. When voltages at the VIN1 pin exceed the threshold voltage of the under voltage lockout protection

circuit, the system is restored.

(8) Over Temperature Protection Block (OTP)

The circuit protects an IC from heat-destruction. If the junction temperature reaches 135 °C, the circuit turns off

the CH1 and CH2 operation, When the junction temperature comes down to + 110 °C, the CH1 and CH2 are

returned to the normal operation.

(9) Control Block (CTL)

• Control function table

EN1

L

EN2

L

CH1 and POR

CH2

OFF

ON

VREF, UVLO, OTP

OFF

ON

OFF

ON

H

L

H

OFF

ON

H

ON

6

DS04-27271-2E

MB39C022

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Condition

VIN1 pin

Unit

Max

Min

− 0.3

⎯

VIN1

VIN2

VFB

+ 6.0

VIN1 + 0.3

+ 6.0

V

A

Power supply voltage

VIN2 pin

FB pin

Input voltage

VEN1

VEN2

VPOR

VLX

EN1 pin

EN2 pin

+ 6.0

POR pull-up voltage

LX voltage

POR pin

LX pin

+ 6.0

VIN1 + 0.3

1.6

LX peak current

VOUT2 peak current

ILX

LX pin AC

VOUT2 pin AC

IO2

⎯

0.8

⎯

2632*^1,*²

980*^1,*³

Ta ≤ + 25 °C

⎯

Power dissipation

PD

mW

⎯

1053*^1,*^2,*⁴

392*^1,*^3,*⁴

+ 125

Ta = + 85 °C

⎯

Storage temperature

TSTG

− 55

°C

⎯

*1: When mounted on four layer epoxy board of 11.7 cm × 8.4 cm

*2: At connect the exposure pad and with thermal via (Thermal via 4 pcs).

*3: At connect the exposure pad and not thermal via.

*4: Power dissipation value between + 25 °C and + 85 °C is obtained by connecting these two points with a straight

line

Notes: • The use of negative voltages below − 0.3 V to the GND pin may create parasitic transistors on LSI lines,

which can cause abnormal operation.

• If LX terminal is short-circuited to VIN1 or VIN2 or GND line, there is a possibility to destroy it. Such usage

is prohibit

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

DS04-27271-2E

7

MB39C022

■ RECOMMENDED OPERATING CONDITIONS

Value

Typ

Parameter

Symbol

Condition

Unit

Min

Max

VIN1

VIN2

VFB

VIN1 pin*^1,*^3,*^4,*⁵

VIN2 pin*^2,*³

FB pin

Power supply voltage

2.5

3.7

5.5

V

⎯

0

0.30

⎯

V

A

Input voltage

VEN1

VEN2

VO1

ILX

EN1 pin

5.5

4.5

0.6

0.3

EN2 pin

0

⎯

Output voltage

Output current

CH1 : Buck DC/DC*^1,*⁵

0.8

⎯

LX pin DC

⎯

IVOUT2 VOUT2 pin DC

⎯

Operating ambient

temperature

Ta

⎯

− 40

+ 25

+ 85

°C

*1 : The minimum VIN1 has to meet two conditions : VIN1 ≥ (VIN1 Min) and VIN1 ≥ VO1 + 0.5 V

*2 : The minimum VIN2 has to meet two conditions : VIN2 ≥ (VIN2 Min) and VIN2 ≥ VO2 + Vdrop (VO2 and Vdrop

values are specified in “■ ELECTRICAL CHARACTERISTICS”)

*3 : VIN1 ≥ VIN2

*4 : VIN1 startup rise time ≤ 1 ms is recommended

*5 : PFM mode at light load current with VO1/VIN1 ≤ 80% (IO1 ≤ 10 mA)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

8

DS04-27271-2E

MB39C022

■ ELECTRICAL CHARACTERISTICS

(Ta = + 25 °C, VIN1 = VIN2 = 3.7 V)

Value

Unit

Sym-

bol

Parameter

Pin No.

Condition

Min

Typ

0.3

0

Max

Threshold voltage

Input Bias current

VTH

IFB

6

FB pin

− 2.5%

− 100

+ 2.5%

+ 100

V

FB = 0 V

nA

SW PMOS-Tr On

resistor

RPON

RNON

8,9

ILX = − 100 mA

⎯

0.35

0.25

⎯

Ω

CH1

[ Buck

DC/DC ]

SW NMOS-Tr On

resistor

9,10 ILX = 100 mA

Line regulation

Load regulation

Vline1

⎯

VIN1 = 2.5 V to 5.5 V*¹

⎯

10

⎯

mV

Vload1

IO1 = 100 mA to 600 mA

Over current

protect

ILIM1

9

VOUT1 × 0.9

0.9

1.2

1.5

A

V

IO2 = 0 mA to − 300 mA

MB39C022G

− 2.5% 3.30

− 2.5% 2.85

− 2.5% 1.80

− 2.5% 1.20

+ 2.5%

IO2 = 0 mA to − 300 mA

MB39C022J

Output voltage

VO2

3

IO2 = 0 mA to − 300 mA

MB39C022L

IO2 = 0 mA to − 300 mA

MB39C022N

Line regulation

Load regulation

Vline2

3

VIN2 = 2.5 V to 5.5 V*²

IO2 = 0 mA to − 300 mA

⎯

10

25

mV

Vload2

IO2 = − 300 mA,

Drop out voltage

Vdrop

3

VIN2 = VO2 :

⎯

200

⎯

mV

MB39C022G, MB39C022J

f = 1 kHz

MB39C022G*³

⎯

70*⁴

65*⁴

60*⁴

55*⁴

⎯

dB

CH2

[ LDO ]

f = 10 kHz

f = 1 kHz

MB39C022J*³

f = 10 kHz

Power supply

rejection ratio

PSRR

3

f = 1 kHz

MB39C022L*³

f = 10 kHz

f = 1 kHz

MB39C022N*³

f = 10 kHz

Output noise

voltage

f = 10 Hz to 100 kHz,

EN1 = 0 V

Vnoise

ILIM2

3

⎯

55*⁴

700

350

⎯

μVrms

mA

Over current

protect

VO2 × 0.9

VO2 = 0 V

500

150

980

700

Short circuit

protect

ISCP2

mA

(Continued)

DS04-27271-2E

9

MB39C022

(Continued)

(Ta = + 25 °C, VIN1 = VIN2 = 3.7 V)

Value

Unit

Parameter

Symbol Pin No.

Condition

fosc = 2 MHz

Min

52.8

⎯

Typ

66

⎯

Max

79.2

0.1

1

Hold time

Thold

VPOR

IPOR

4

ms

V

Power On

Reset

[ POR ]

Output voltage

Output current

POR = 250 μA

POR = 5.5 V

⎯

μA

Under Voltage Threshold

VTHL

VH

2, 8 VIN1

1.95

2.10

0.20

+ 135

+ 25

2.25

⎯

V

Lockout

voltage

Protection

Circuit Block

[ UVLO ]

Hysteresis

width

2, 8

⎯

V

Over

Stop

TOTPH

TOTPHYS

⎯

°C

Temperature temperature

Protection

Hysteresis

width

Block

[ OTP ]

⎯

Oscillator

Output

Block

fosc

9

⎯

1.6

2.0

2.4

MHz

frequency

[ OSC ]

VIH

VIL

1, 7 EN1, EN2 ON

1, 7 EN1, EN2 OFF

1, 7 EN1, EN2 = 0 V

1.5

⎯

0

⎯

0.4

+ 100

1

V

Input voltage

Input current

Control Block

[CTL ]

IEN

− 100

⎯

nA

μA

Shut down

power supply

current

ICC1

8

2

8

2

8

2

8

2

EN1, EN2 = 0 V

0

ICC1

ICC2

ICC3

ICC4

⎯

0

30

0

1

μA

Standby power

supply current

(DC/DC)

60

EN1 = VIN1, EN2 = 0 V

IO1 = 0 mA, VFB = VIN1

μA

1

General

Standby power

supply current

(LDO)

10

60

0.9

60

18

EN1 = 0 V, EN2 = VIN1

IO2 = 0 mA

μA

120

1.5

120

Power-on

invalid

current

mA

EN1, EN2 = VIN1,

VFB = 0.2 V

μA

*1 : The minimum VIN1 has to meet two conditions : VIN1 ≥ (VIN1 Min) and VIN1 ≥ VO1 + 0.5 V

*2 : The minimum VIN2 has to meet two conditions : VIN2 ≥ (VIN2 Min) and VIN2 ≥ VO2 + Vdrop (VO2 and Vdrop

values are specified in “■ ELECTRICAL CHARACTERISTICS”)

*3 : VIN2 = VO2 + 1 V, (MB39C022N: VIN2 = 2.5 V), IO2 = 100 mA

*4 : This value is not be specified. This should be used as a reference to support designing the circuits.

10

DS04-27271-2E

MB39C022

■ TEST CIRCUIT FOR MEASURING TYPICAL OPERATING CHARACTERISTICS

EN2

GND1

LX

C2

VIN2

VO1

C4

C5

L1

VO2

VOUT2

POR

VIN1

EN1

FB

VIN

C1

POR

EN1

R3

R5

R6

C3

GND2

Component

Item

Specification

Remarks

C1

C2

C3

C4

Ceramic capacitor

10 μF

4.7 μF

22 pF

4.7 μF

1 μF

for MB39C022J, MB39C022L

for MB39C022G, MB39C022N

C5

Ceramic capacitor

4.7 μF

2.2 μH

1 MΩ

L1

R3

R5

R6

Inductor

Resistor

600 kΩ

200 kΩ

at VO1 = 1.2 V*

* : The output voltage of VO1 can be adjusted by the external resistor divider R5.

(R5 + R6)

(600 kΩ + 200 kΩ)

200 kΩ

V^O1= Vref ×

= 0.3 V ×

= 1.2 V

R6

DS04-27271-2E

11

MB39C022

■ APPLICATION NOTES

[1] Selection of components

Selection of an external inductor for DC/DC

This IC is designed to operate well with a 2.2 μH inductor. Choosing larger values would lead to larger overshoot/

undershoot during load transient. Choosing a smaller value would lead to larger ripple voltage.

The inductor should be rated for a saturation current higher than the LX peak current value during normal

operating conditions, and should have a minimal DC resistance. (100 mΩ or less is recommended to improve

efficiency.)

LX peak current value I^PKis obtained by the following formula.

V^IN− VOUT

D

1

2

(V^IN− VOUT) × VOUT

2 × L × fosc × VIN

I^PK= IOUT +

×

= IOUT +

L

fosc

L

: External inductor value

I^OUT: Load current (DC)

V^IN: Power supply voltage

V^OUT: Output setting voltage

: ON- duty to be switched ( = V^OUT/VIN)

fosc : Switching frequency (2.0 MHz)

D

ex) At V^IN= 3.7 V, VOUT = 1.2 V, IOUT = 0.6 A, L = 2.2 μH, fosc = 2.0 MHz

The maximum peak current value I^PK;

(V^IN− VOUT) × VOUT

(3.7 V − 1.2 V) × 1.2 V

IPK = IOUT +

= 0.6 A +

= 0.69 A

2 × L × fosc × V^IN

2 × 2.2 μH × 2 MHz × 3.7 V

I/O capacitor selection

• DC/DC's output capacitor's finite equivalent series resistance (ESR) causes ripple voltages on output equal

to the amount of current variation multiplied by the ESR value. The output capacitor value also has a significant

impact on the operating stability of the device when used as a DC/DC converter. Therefore, FUJITSU

MICROELECTRONICS generally recommends C2 = 4.7 μF as DC/DC output capacitor, or a larger capacitor

value can be used if ripple voltages are not suitable.

• For DC/DC, select a low ESR for the VIN1/VIN2 input capacitor to suppress dissipation from ripple currents.

In addition, to reduce startup overshoot for DC/DC and LDO, it is recommended that larger ceramic capacitor

be used for input capacitors C1 and C4. Recommended values are C1 = 10 μF, C4 = 4.7 μF.

• Types of capacitors

Ceramic capacitors are effective for reducing the ESR and afford smaller DC/DC converter circuit. However,

power supply functions as a heat generator, therefore avoid using capacitor with the F-temperature rating

( − 80% to + 20%). FUJITSU MICROELECTRONICS recommends capacitors with the B-temperature rating

(

10% to 20%).

Normal electrolytic capacitors are not recommended due to their high ESR.

Tantalum capacitor will reduce ESR, however, it is dangerous to use because it turns into short mode when

damaged. If you insist on using a tantalum capacitor, FUJITSU MICROELECTRONICS recommends the type

with an internal fuse.

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DS04-27271-2E

MB39C022

[2] DC/DC Output voltage setting

The output voltage V^O1of this IC is defined by the external resistive divider R5 & R6. Note that C3 is a capacitor

used for improving stability. Use a 22 pF cap for C3 should be suitable in all cases.

R5 + R6

600 kΩ + 200 kΩ

200 kΩ

V^O1= Vref ×

= 0.3 V ×

= 1.2 V

R6

VO1

MB39C022

C3

R5

6

FB

Vref

(0.3 V)

-

R6

+

[3] Power On Reset (POR)

R3 and R4 are the pull-up resistors for POR (Pin 4). A 1 MΩ resistor is required to placed at either R3 or R4.

When R3 has a 1 MΩ resistor and R4 is open; the POR will be connected VIN. When R4 has a 1 MΩ resistor

and R3 is open; the POR pin will be connected to VO1.

By default, only R3 require a 1 MΩ resistor while R4 is open.

DS04-27271-2E

13

MB39C022

[4] Power dissipation and heat considerations

The DC/DC is so efficient that no consideration is required in most cases. The LDO, on the other hand, would

be the dominant heat generator due to its inherent efficiency loss. Thus, if the IC is used at a high power supply

voltage, heavy load, and low LDO output voltage, or high temperature, it requires further consideration.

The internal loss (Pc) is roughly obtained from the following formula :

2

P^C= PC1 + PC2 = IO1 × (RDC + D × RONP + (1 − D) × RONN) + IO2 × Vdrop

P^C1

P^C2

RDC

D

: DC/DC continuity loss

: LDO continuity loss

: External inductor series resistance ( < 100 mΩ recommended)

: Switching ON-duty cycle ( = V^OUT/ VIN)

: Internal P-ch SW FET ON resistance

: Internal N-ch SW FET ON resistance

: DC/DC Load current

R^ONP

R^ONN

I^O1

I^O2

: LDO Load current

V^drop

: LDO Dropout voltage

The loss expressed by the above formula is continuity loss. The internal loss includes the switching loss and the

control circuit loss as well but they are so small compared to the continuity loss they can be ignored.

For P^C1, consider the scenario with high temperature and heavy load (VIN = 3.7 V, VO1 = 1.2 V, IO1 = 0.6 A, Ta =

+ 70 °C). Here, R^ONP=: 0.4 Ω and RONN =: 0.3 Ω according to the graph “MOS FET ON resistance vs. Operating

ambient temperature”. P^C1= 156 mW.

For P^C2, consider the scenario with low output voltage (MB39C022N), high temperature and heavy load

(VIN = 3.7 V, V^O2= 1.2 V, IO2 = 0.3 A, Ta = + 70 °C). Here, PC2 = 0.75 W. Note that PC2 >> PC1.

According to the graph “Power dissipation vs. Operating ambient temperature”, the maximum permissible power

dissipation at an operating ambient temperature Ta of + 70 °C is 1.4 W. The internal loss is lower than the

maximum permissible power dissipation.

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DS04-27271-2E

MB39C022

[5] Board layout, design example

Some basic design guidelines should be used when physically placing the MB39C022 on a Printed Circuit Board

(PCB).

• Regarding to GND pattern of PCB layout of MB39C022, It needs to separate like AGND (analog ground) and

PGND (power ground). By separating grounds, it is possible to minimize the switching frequency noise on the

LDO output.

• Arrange the input capacitor C1 and C4 as close as possible between VIN1 & PGND pins and VIN2 & AGND

pins. Make a through hole near the pins of this capacitor if the board has planes for power and GND.

• Large AC currents flow between this IC and the input capacitor (C1), output capacitor (C2), and external

inductor (L1). Group these components as close as possible to this IC to reduce the overall loop area occupied

by this group. Also try to mount these components on the same surface and arrange wiring without through

hole wiring. Use thick, short, and straight routes to wire the net (The layout by planes is recommended.).

• The C1 and C2 capacitor returns are connected closely together at the PGND plane.

• The LDO input capacitor (C4) and LDO output capacitor (C5) are returned to the AGND plane.

• The analog ground plane and power ground plane are connected at one point.

• All other signals (EN1, EN2, FB) should be referenced to AGND and have the AGND plane underneath them.

• The feedback wiring to the V^O1and the VO1 pin should be wired closest to the output capacitor (C2). The

resistive divider and FB pin is extremely sensitive and should thus be kept wired away from the LX pin of this

IC as far as possible.

• Try to make a GND plane on the surface to which this IC will be mounted. For efficient heat dissipation when

using the SON-10 package, FUJITSU MICROELECTRONICS recommends providing a thermal via in the

footprint of the thermal pad.

Layout Example of IC components

PGND

Plane

VO1

L1

PGND

C2

AGND Plane

C4

VVIINN22

PGND

AGND

CC11

C5

VIN1

VVOO22

RR66

R5

DS04-27271-2E

15

MB39C022

■ EXAMPLE OF STANDARD OPERATION CHARACTERISTICS

(Shown below is an example of characteristics for connection according to “■ TEST CIRCUIT FOR MEASURING

TYPICAL OPERATING CHARACTERISTICS”.)

(1) DC/DC Conversion Efficiency

CH1 Test Condition :

EN1 = VIN; EN2 = 0 V

VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF

100

90

80

70

60

50

40

30

20

10

0

VIN = 3.7 V

VIN = 4.3 V

VIN = 5.5 V

0.001

0.01

0.1

1

Load Current IO1 (A)

(2) DC/DC Load Regulation

CH1 Test Condition :

EN1 = VIN; EN2 = 0 V

VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF

1.3

1.28

VIN = 3.7 V

VIN = 4.3 V

VIN = 5.5 V

1.26

1.24

1.22

1.2

1.18

1.16

1.14

1.12

1.1

0

0.2

0.4

0.6

Load Current IO1 (A)

16

DS04-27271-2E

MB39C022

(3) DC/DC Line Regulation

CH1 Test Condition :

EN1 = VIN; EN2 = 0 V

VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF

1.3

1.28

1.26

1.24

1.22

1.2

IO1 = 0 mA

IO1 = 300 mA

IO1 = 600 mA

1.18

1.16

1.14

1.12

1.1

3.2

3.7

4.2

4.7

5.2

Input Voltage VIN (V)

(4) DC/DC Switching Waveform

CH1 Test Condition :

EN1 = EN2 = VIN = 3.7 V;

VO1 = 1.8 V; IO1 = 250 mA; C1 = 10 μF; C2 = 4.7 μF

VO2 = 3.3 V; IO2 = 150 mA; C4 = C5 = 4.7 μF

VLx

5 V/div

ILx

100 mA/div

VO1

20 mV/div

VO2

20 mV/div

500 ns/div

DS04-27271-2E

17

MB39C022

(5) LDO Load Regulation

MB39C022G CH2 Test Condition :

EN2 = VIN; EN1 = 0 V

VO2 = 3.3 V; C4 = C5 = 4.7 μF

3.4

VIN = 3.7 V

3.38

VIN = 4.3 V

3.36

VIN = 5.5 V

3.34

3.32

3.3

3.28

3.26

3.24

3.22

3.2

0.25

0

0.05

0.1

0.15

0.2

0.3

Load Current IO2 (A)

(6) LDO Line Regulation

MB39C022G CH2 Test Condition :

EN2 = VIN; EN1 = 0 V

VO2 = 3.3 V; C4 = C5 = 4.7 μF

3.4

3.38

IO2 = 0 mA

3.36

3.34

3.32

3.3

IO2 = 120 mA

IO2 = 300 mA

3.28

3.26

3.24

3.22

3.2

3.6

4.1

4.6

5.1

Input Voltage VIN (V)

18

DS04-27271-2E

MB39C022

(7) LDO Power Supply Rejection Ratio

MB39C022G CH2 Test Condition :

EN2 = VIN = 3.7 V; EN1 = 0 V

VO2 = 3.3 V; IO2 = 100 mA; C1 = C4 = 0 μF

0

10

20

30

40

50

60

70

80

90

−

VIN = 3.7 V

VIN = 4.3 V

10

100

1000

10000

100000

1000000

Frequency (Hz)

(8) DC/DC Load Transient Waveforms

Test Condition :

VIN = EN1 = EN2 = 3.7 V; VO1 = 1.2 V; C1 = 10 μF; C2 = 4.7 μF; VO2 = 3.3 V; C4 = C5 = 4.7 μF

T

IO1 = 10 mA to 400 mA

IO1

500 mA/div

VO1

100 mV/div

VO2

IO2 = 150 mA

20 mV/div

100 μs/div

CH1 Load Transient Waveforms

DS04-27271-2E

19

MB39C022

(9) DC/DC Power MOS FET ON Resistance

P-ch MOS FET ON Resistance vs.

Operating Ambient Temperature

MOS FET ON Resistance vs. Input Voltage

0.6

0.5

0.6

0.5

0.4

0.3

0.2

0.1

0.0

P-ch

V

IN = 3.7 V

0.4

0.3

0.2

N-ch

V

IN = 5.5 V

0.1

0.0

2.0

3.0

4.0

5.0

6.0

-50

0

50

100

Input voltage VIN (V)

Operating Ambient Temperature Ta ( °C)

N-ch MOS FET ON Resistance vs.

Operating Ambient Temperature

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V

IN = 3.7 V

V

IN = 5.5 V

-50

0

50

100

Operating Ambient Temperature Ta ( °C)

20

DS04-27271-2E

MB39C022

Permissible Power Dissipation vs. Operating Ambient Temperature

3000

2630

2500

2000

1500

1000

500

0

-40

-20

0

20

40

60

80

100

Operating Ambient Temperature Ta ( °C)

DS04-27271-2E

21

MB39C022

■ APPLICATION CIRCUITS EXAMPLES

EXAMPLE 1 (VIN1 = VIN2)

VIN1 and VIN2 are connected together and POR is pulled up to VIN

(MB39C022)

EN2

GND1

LX

C2

VO1

VIN2

IO1 ≤ 600 mA

C4

C5

L1

VO2

IO2 ≤ 300 mA

VOUT2

POR

VIN1

EN1

FB

VIN

C1

POR

EN1

R3

R6

R5

C3

GND2

EXAMPLE 2 (VIN2 = VO1)

• VIN2 is connected to VO1 and POR is pulled up to VIN

• It is possible to maximize LDO efficiency by connecting DC/DC Output to LDO supply.

• Maximum DC/DC output current ( = IO1) is limited by VIN2 input current (=: IO2)

(MB39C022)

EN2

GND1

LX

C2

VO1

VIN2

IO1 ≤ 600 mA - IO2

C4

C5

L1

VO2

VOUT2

POR

VIN1

EN1

FB

IO2 ≤ 300 mA

VIN

C1

POR

EN1

R3

R6

C3

GND2

R5

22

DS04-27271-2E

MB39C022

EXAMPLE 3 (POR and RC delay channel control)

• EN1 is controlled by RC delay and EN2 is controlled by POR output.

• It is possible to control each channel without signal from MCU

R3

(MB39C022)

EN2

GND1

LX

C2

VO1

VIN2

IO1 ≤ 600 mA

C4

C5

L1

VO2

IO2 ≤ 300 mA

VOUT2

POR

VIN1

EN1

FB

VIN

C1

100 kΩ

POR

1 μF

R5

R6

C3

GND2

Timing chart

VIN

VUVLO

Vth(POR)

VO1

(1.2 V)

VO2

tc

td

(1.8 V)

ta

tb

Start up control

t^a: RC delay time (28 ms at VIN = 3.7 V, R = 100 kΩ, C = 1 μF)

t^b: POR hold time (66 ms fixed)

Power down control

t^c, td : depend on internal discharge path and output loading

DS04-27271-2E

23

MB39C022

■ USAGE PRECAUTIONS

1. Never use setting exceeding maximum rated conditions.

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,

etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

2. Use the devices within recommended conditions

It is recommended that devices be operated within recommended conditions.

Exceeding the recommended operating condition may adversely affect devices reliability.

Nominalelectricalcharacteristicsarewarrantedwithintherangeofrecommendedoperatingconditionsotherwise

specified on each parameter in the section of electrical characteristics.

3. Design the ground line on printed circuit boards with consideration of common impedance.

4. Take appropriate measures against static electricity.

The LX pin has less built-in ESD protection than other pins.

LX pin : 150 V (MM), 1500 V (HBM), Other pins : 200 V (MM), 2000 V (HBM)

Containers for semiconductor materials should have anti-static protection or be made of conductive material.

After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.

Work platforms, tools, and instruments should be properly grounded.

Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.

5. Do not apply negative voltages

The use of negative voltages below − 0.3 V may activate parasitic transistors on the device, which can cause

abnormal operation.

24

DS04-27271-2E

MB39C022

■ ORDERING INFORMATION

Part number

MB39C022GPN

MB39C022JPN

Package

Remarks

10-pin plastic SON

(LCC-10P-M04)

MB39C022LPN

MB39C022NPN

DS04-27271-2E

25

MB39C022

■ RoHS COMPLIANCE INFORMATION OF LEAD(Pb) FREE VERSION

The LSI products of FUJITSU MICROELECTRONICS with “E1” are compliant with RoHS Directive, and has

observed the standard of lead, cadmium, mercury, chromium, polybrominated biphenyls (PBB), and polybromi-

nated diphenylethers (PBDE).

A product whose part number has trailing characters “E1” is RoHS compliant.

26

DS04-27271-2E

MB39C022

■ PACKAGE DIMENSION

10-pin plastic SON

Lead pitch

0.50 mm

3.00 mm × 3.00 mm

Plastic mold

Package width ×

package length

Sealing method

Mounting height

Weight

0.75 mm MAX

0.018 g

(LCC-10P-M04)

10-pin plastic SON

(LCC-10P-M04)

3.00±0.10

(.118±.004)

2.40±0.10

(.094±.004)

10

6

INDEX AREA

1.70±0.10

(.067±.004)

3.00±0.10

(.118±.004)

0.40±0.10

(.016±.004)

1

5

1PIN CORNER

(C0.30(C.012))

0.50(.020)

TYP

0.25±0.03

(.010±.001)

0.75(.030)

MAX

0.15(.006)

0.05(.002)

0.00 ⁺^–0⁰^.^.⁰⁰⁰⁵

+.002

(.000

)

–.000

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2008 FUJITSU MICROELECTRONICS LIMITED C10004S-c-1-2

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

DS04-27271-2E

27

MB39C022

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Japan

Tel: +81-3-5322-3329

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department


型号：	MB39C022LPNE1
厂家：	FUJITSU
描述：	Switching Regulator, Current-mode, 1.6A, 2400kHz Switching Freq-Max, PDSO10, 3 X 3 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, PLASTIC, SON-10 开关光电二极管
文件：	总28页 (文件大小：1115K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB39C022LPNE1 [FUJITSU]

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