MB40168-PF [FUJITSU]
Analog Circuit, 1 Func, BIPolar, PQFP44, PLASTIC, QFP-44;
| 型号： | MB40168-PF |
| 厂家： | 
FUJITSU |
| 描述： | Analog Circuit, 1 Func, BIPolar, PQFP44, PLASTIC, QFP-44 |
| 文件： | 总21页 (文件大小：687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-28501-2E
ASSP
Single Chip 8-Bit A/D and 9-Bit
D/A Converter
MB40168/MB40178
■ DESCRIPTION
The Fujitsu MB40168 and MB40178 are high speed, low power single chip A/D and D/A converters designed
for video processing applications. The A/D converter has a resolution of 8 bits while the D/A converter has 9-
bit resolution. They are fabricated in Fujitsu’s advanced bipolar technology, and housed in a 48-pin plastic shrink
DIP or 44-pin plastic QFP package.
■ FEATURES
• Resolution
A/D: 8 bits
D/A: 9 bits
• Conversion Rate
• Linearity Error
A/D: Max. 20 MSPS
D/A: Max. 40 MSPS
A/D: Max. + 0.3%
D/A: Max. + 0.2%
• On-chip reference voltage generator (resistor divided method) and clamp circuit
• Analog Input Voltage
3 to 5 V without clamp circuit
0 to 3 V in 1.95 VP-P clamp circuit
3 to 5 V
• Analog Output Voltage
(Continued)
■ PACKAGES
44 pin, Plastic QFP
48 pin, Plastic SH-DIP
(DIP-48P-M01)
(FPT-44P-M11)
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
MB40168/MB40178
(Continued)
• Digital Input/Output Interface
• Power Supply Voltage
• Power Dissipation
TTL Levels
+ 5.0 V single power supply
Typ. 350 mW
• Package Options
48-pin Plastic Shrink DIP/
44-pin Plastic QFP Package
■ PIN ASSIGNMENTS
• MB40168
(TOP VIEW)
D.GND
DACLK
(LSB) D D9
D D8
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A.GND
V CCD
V CCA
A.OUT
COMP
V RIN
(TOP VIEW)
2
3
4
D D7
5
D D6
6
44 43 42 41 40 39 38 37 36 35 34
1
V RIN
D D6
D D5
33
32
31
30
29
28
27
26
25
24
23
D D5
7
V REF
V RB
2
V REF
V RB
D D4
8
3
D D4
D D3
9
NC
4
D.GND
A.GND
V CCD
V CCA
V RM
D D3
D D2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D.GND
A.GND
V CCD
V CCD
V CCA
V CCA
V RM
5
D D2
(MSB) D D1
NC
6
(MSB) D D1
(LSB) D A8
D A7
7
NC
8
NC
9
V INA
D A6
(LSB) D A8
D A7
10
11
V CLMP
V OUTC
D A5
D A6
V INA
D A4
12 13 14 15 16 17 18 19 20 21 22
D A5
V CLMP
V OUTC
V INC
D A4
D A3
D A2
V RT
(MSB) D A1
ADCLK
D.GND
V CCA
V CCD
A.GND
(FPT-44P-M11)
(DIP-48P-M01)
2
MB40168/MB40178
• MB40178
(TOP VIEW)
D.GND
DACLK
(MSB) D D1
D D2
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A.GND
V CCD
V CCA
A.OUT
COMP
V RIN
(TOP VIEW)
2
3
4
D D3
5
D D4
6
44 43 42 41 40 39 38 37 36 35 34
1
V RIN
D D4
D D5
D D6
D D7
D D8
33
32
31
30
29
28
27
26
25
24
23
D D5
7
V REF
V RB
2
V REF
V RB
D D6
8
3
D D7
9
NC
4
D.GND
A.GND
V CCD
V CCA
V RM
D D8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D.GND
A.GND
V CCD
V CCD
V CCA
V CCA
V RM
5
(LSB) D D9
NC
6
(LSB) D D9
(LSB) D A8
D A7
7
NC
8
NC
9
V INA
D A6
(LSB) D A8
D A7
10
11
V CLMP
V OUTC
D A5
D A6
V INA
D A4
12 13 14 15 16 17 18 19 20 21 22
D A5
V CLMP
V OUTC
V INC
D A4
D A3
D A2
V RT
(MSB) D A1
ADCLK
D.GND
V CCA
V CCD
A.GND
(FPT-44P-M11)
(DIP-48P-M01)
3
MB40168/MB40178
■ PIN DESCRIPTION
Pin No.
Symbol
I/O
Name & Function
Digital Power Supply pins (+ 5 V).
QFP-44
SH-DIP-48
VCCD
VCCA
19, 28, 37 26, 36, 37, 47
20, 27, 36 27, 34, 35, 46
—
—
Analog Power Supply pins (+ 5 V).
16, 30,
1, 24, 39
39, 40
Digital Ground (0 V). These pins should be connected to the
analog ground on the application system.
DGND
AGND
—
—
17, 18,
Analog Ground (0 V). These pins should be connected to the
analog ground on the application system.
25, 38, 48
29, 38
DA8 - DA1
ADCLK
VRT
7 - 14
15
15 - 22
23
O
I
ADC Digital Output pins. TTL level.
ADC Clock Input pin. TTL level.
21
28
I
ADC Reference Voltage Input pin. (5 V Input)
Sync Tip Clamp Circuit Analog Input pin. (0 - 3 V, 1.95 VP-P).
When a clamp circuit is not used, this pin is connected to
ground.
VINC
22
23
29
30
I
Clamp Circuit Analog Output pin. It is used by adding a
capacitor (1 µF or more) between VCLMP and VOVTC pins.
When a clamp circuit is not used, this pin is left open.
VOUTC
O
Clamp Voltage Output pin (3.05V Output). When a clamp
circuit is not used, this pin is left open.
VCLMP
VINA
VRM
24
25
26
31
31
32
33
41
O
I
ADC Analog Signal Input pin. (3 - 5 V)
ADC Middle Reference Voltage Monitor pin. (Mid of VRT - VRB
is set to this pin). Normally this pin is left open.
—
I
VRB
ADC Reference Voltage Input pin. (3 V)
Reference Voltage Output pin. (Resistor Divider, 3 V)
By connecting this pin to VRB pin, 3V Voltages are generated.
When a reference voltage is not used, this pin is left open.
VREF
VRIN
32
33
34
42
43
44
O
I
DAC Reference Voltage Input pin (3 V)
Phase Compensation Capacitor pin. (Capacitor greater than
0.1 µF should be connected between this pin and Analog
Ground.)
COMP
—
AOUT
35
41
45
2
O
I
Analog Signal Output pin
DACLK
DAC Clock Input pin. TTL level.
1 - 6 *1
42 - 44
3 - 11*2
DD9 - DD1
I
DAC Digital Data Input pins. TTL level.
*1: MB40168 (MSB: 6 pin, LSB: 42 pin), MB40178 (MSB: 42 pin, LSB: 6 pin)
*2: MB40168 (MSB: 11 pin, LSB: 3 pin), MB40178 (MSB: 3 pin, LSB: 11 pin)
4
MB40168/MB40178
■ BLOCKDIAGRAM
VCCD
VCCA
VINA
ADCLK
VRT
R1
R
1
2
DA1 (MSB)
DA2
DA3
R
127
128
Latch
&
Buffer
255 to 8
Encoder
DA4
R/2
VRM
DA5
R/2
DA6
DA7
R
R
254
255
DA8 (LSB)
R2
VRB
VINC
Reference
voltage
generator
VOUTC
Clamp
≈ 0.6VCCA + 50mV
VCLMP
0.6VCCA
VREF
VRIN
COMP
Reference
resistor
Amp
DACLK
DD9 (LSB)
R-2R Ladder
resistor
network
Master
Slave
register
9
9
9
9
9
Input
buffer
Buffer
Current
switch
AOUT
DD1 (MSB)
DGND
AGND
5
MB40168/MB40178
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Analog input voltage
Reference voltage
Symbol
VCCA, VCCD
VINA
Rating
Unit
V
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to VCC + 0.5
–0.5 to VCC + 0.5
–0.5 to 7.0
V
VRT, VRB, VRIN
VINC
V
Clamp circuit input voltage
Digital input voltage
V
VIND
V
Storage temperature
TSTG
–55 to +125
°C
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6
MB40168/MB40178
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min.
4.75
Typ.
5.00
—
Max.
5.25
Power supply voltage *1
Clamp circuit input voltage *2
Analog input voltage
VCCA, VCCD
VINC
V
V
V
V
0
3
VINA
VRB
—
VRT
Top
VRT
VCCA – 0.1
VCCA
VCCA + 0.1
ADC reference voltage *3
DAC reference voltage
Bottom
VRB
VCCA - VRIN
VRIN
2.75
0.7
2.65
2.0
—
3.0
2.0
3.0
—
3.25
2.2
4.3
—
V
V
V
Digital input high voltage
Digital input low voltage
Digital output high current
Digital output low current
VIHD
VILD
IOH
V
—
0.8
—
V
–400
—
—
µA
mA
MHz
IOL
—
1.6
20
A/D
D/A
A/D
D/A
A/D
D/A
fCLKAD
fCLKDA
tWHAD
tWHDA
tWLAD
tWLAD
—
—
Clock frequency
—
—
—
—
—
40
—
—
—
MHz
ns
22.5
10.5
22.5
Minimum high clock pulse
width
ns
ns
Minimum Low clock pulse
width
10.5
10
4
—
—
—
—
—
—
—
—
ns
ns
ns
µF
µF
oC
Set up time
tSU
tH
Hold time
—
Clamp capacitance
CCLMP
CCOMP
Ta
1
—
Phase compensation capacitance
Ambient operating temperature
0.1
–20
—
+70
*1: VCCA and VCCD must be used in the same voltage level.
*2: VINC must have an amplitude of VRT - VCLMP.
*3: VRT - VRB must have 2.0V±0.1V.
7
MB40168/MB40178
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
• Analog Block
(VCCA = VCCD = 4.75 V to 5.25 V, Ta = –20 oC to +70 oC)
Value
Parameter
ADC resolution
Symbol
Condition
Unit
Min.
—
Typ.
Max.
—
—
—
—
—
8
9
bits
bits
%
DAC resolution
—
—
ADC linearity error
LEAD
DC accuracy
VCCA = VCCD =
5.0 V
—
± 0.15
± 0.3
DAC linearity error
LEDA
RINA
—
± 0.1
± 0.2
%
VRT –VRB
RINA =
Analog input equivalent
impedance
0.3
1.3
—
MΩ
IIHA – IILA
Analog input capacitance
Analog input high current
Analog input low current
CINA
IIHA
IILA
fINA = 1 MHz
VINA = VRT
VINA = VRB
—
—
—
40
—
—
—
45
40
pF
µA
µA
VREF, VRB, VRIN
shorted
together
0.6VCCA –
0.1
0.6VCCA+
0.1
Reference output voltage
Clamp voltage
VREF
0.6VCCA
V
V
VREF + 50
mV
VCLMP
—
—
—
ADC reference current
DAC reference current
IRB
—
–8.5
—
–5.5
—
–3.0
10
mA
IRIN
VRIN = 3.000 V
µA
Clamp circuit input
current
IINC
VINC = 0 V
—
–600
–200
VCCA
—
—
µA
Full scale output voltage
VOFS
VCCA–20mV
V
VCCA = 5.00 V
VCCD = 5.00 V
VRIN = 3.000 V
Zero scale output voltage
VOZS
2.934
3.004
3.072
V
Ta = +25 oC
—
Output impedance
Supply current
RO
ICC
192
—
240
70
288
125
Ω
mA
8
MB40168/MB40178
• Digital Block
(VCCA = VCCD = 4.75 V to 5.25 V, Ta = –20 oC to +70 oC)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
Digital output high
voltage
VOHD
IOH = –400 µA
2.7
—
—
V
Digital output low voltage
Digital input high voltage
Digital input low voltage
Digital input high current
Digital input low curent
VOLD
VIHD
VILD
IIHD
IOL = 1.6 mA
—
—
2.0
—
—
—
—
—
—
0.4
—
V
V
—
0.8
20
—
V
VIHD = 2.7 V
VILD = 0.4 V
—
µA
µA
IILD
–100
2. AC CHARACTERISTICS
(VCCA = VCCD = 4.75 V to 5.25 V, Ta = –20 oC to +70 oC)
Value
Parameter
Symbol
Condition
Unit
Min.
20
40
8
Typ.
—
—
15
10
5
Max.
—
A/D
D/A
fSAD
fSDA
tpd AD
tpd DA
tr
—
—
—
MSPS
MSPS
ns
Maximum conversion rate
—
Digital output delay time
Analog output delay time
Analog output rise time
Analog output fall time
30
—
—
ns
CL = 15 pF
—
—
ns
Terminating
resistor
AOUT = 240 Ω
tf
—
5
—
ns
tset LH,
tset HL
Settling time
—
16
—
ns
9
MB40168/MB40178
■ LINEARITY ERROR OF A/D CONVERSION
• Ideal Characteristic
Step Output Code
255
254
11111111
11111110
253
11111101
•
•
•
•
•
•
129
10000001
128
127
10000000
01111111
•
•
•
•
•
2
•
00000010
1
0
00000001
00000000
VFT 4.996V
VZT 3.006V
VINA
Note: The values for VZT and VFT are typical values under conditions that VCCA = VCCD = VRT = 5.000V and VRB = 3.000V.
• Actual Characteristic
Step
255
Output Code
11111111
11111110
254
253
11111101
•
•
•
•
•
•
LE253
129
10000001
128
10000000
LE129
LE128
127
01111111
•
•
•
•
•
•
LE127
2
00000010
1
0
00000001
00000000
LE2
LE1
VZT
VINA
VFT
10
MB40168/MB40178
■ OUTPUT VOLTAGE CHARACTERISTIC OF D/A CONVERTER BLOCK
Input
Output
A.OUT
DD1 ~ DD9
511
5.000V
5.000V
(VCCA)
VOFS
3.004V
3.000V
VOZS
0
(VRIN)
1 LSB = 4mV
■ CALCULATION OF DAC OUTPUT VOLTAGE WHEN THE IDEAL CONVERSION IS PER-
FORMED
511-N
AOUTN = VCCA –
x (VCCA – VRIN)
512
(N: Digital code (0 ~ 511)
VOFS = VCCA
511
512
VOZS = VCCA –
x (VCCA – VRIN)
11
MB40168/MB40178
■ EQUIVALENT CIRCUITS OF ADC BLOCK
• Analog Input Equivalent Circuit
VCCA
VINA
VCCA
VINA
VD
CINA
RINA
IBIAS
A.GND
A.GND
x 255 circuits
A.GND
VRB
CINA: Junction Capacitance of non-linear emitter follower
RINA: Linear resistance model of input current by the comparator switching
VINA < VRB: ∞
CLK = “H”: ∞
VRB: This is the voltage on VRB Pin, not VRB Pin itself.
IBIAS: Constant input bias current
VD: Base-Collector junction diode of emitter follower transistor
• Clamp Input Equivalent Circuit
VCCA
2.0mA
0.6 x VCC + 50mV +VBE
850kΩ
VINC
A.GND
VOUTC
VCLMP
-
+
CCLMP
12
MB40168/MB40178
• Digital Input Equivalent Circuit
VCCD
6.5kΩ
50kΩ
50kΩ
3.2kΩ
3.2kΩ
Clock Input
ADCLK
VTH = 1.4V
D.GND
• Digital Output Load Circuit
To pin tested
Test point
CL = 15pF
D.GND
NOTE: CL includes the floating capacitance of probe and jig.
13
MB40168/MB40178
■ EQUIVALENT CIRCUITS OF DAC BLOCK
• Digital Input Equivalent Circuit
VCCD
50kΩ
50kΩ
Digital Input
D01 - D09
DACLK
VTH = 1.4V
D.GND
• Analog Output Equivalent Circuit
VCCA
RO = 240Ω
A.OUT
IO
A.GND
• Reference Voltage Generator Equivalent Circuit
VCCA
20kΩ
Buffer
VREF
IRB
30kΩ
A.GND
14
MB40168/MB40178
■ TYPICAL CONNECTION CIRCUITS
Example 1: Video Signal Input to VINC Pin
+ 5 V
+ 5 V
VCCA
VCCD
Video Signal Input
VINC
VOUTC
MB40168/MB40178
-
1 µF
+
VCLMP
VINA
AGND
DGND
Example 2: Video Signal Input to VCLMP and VINA Pins
+ 5 V
+ 5 V
VCCA
VCCD
VINC
+ 9 V
VOUTC
MB40168/MB40178
External Circuit
VCLMP
2.2 kΩ
1 µF
+
-
VINA
Video Signal
Input
AGND
DGND
2SA933
AGND
15
MB40168/MB40178
■ CLAMP CIRCUIT OPERATION
Clamp Circuit
Clamp Voltage is set at 0.6 x VCC + 50 mV (typ.)
VCCA
VCCA
I ≈ 2 mA
Bias Circuit
VINC
AGND
≈ 3.05 V
VOUTC
-
CCLMP
+
VCLMP
VINA
A/D Converter
Signal Level at VINA pin
VCCA = 5.0 V
Signal Level at VINC pin
VCLMP ≈ 3.05 V
VREF ≈ 3.0 V
AGND
Note: When Clamp Circuit is not applied the signals should be connected as follows:
VINC:
VOUTC:
VCLMP:
Connect to GND.
Leave open.
Leave open.
16
MB40168/MB40178
■ TYPICAL CONNECTION CIRCUIT(Example)
System
Analog
Ground
DAC
Clock
Input
AGND
48
47
DGND
DACLK
(LSB) DD9
DD8
1
2
3
4
5
System
Analog
Power
VCCD
0.1 µF
Supply
VCCA 46
Analog
O/P
(DAC)
45
44
AOUT
COMP
DD7
DD6
0.1 µF
0.1 µF
Digiral
Input
(DAC)
43
VRIN
6
7
VREF 42
DD5
DD4
DD3
DD2
VRB
41
40
39
8
NC
9
DGND
10
MB40168
AGND
VCCD
38
37
(MSB) DD1
11
12
13
Open
Open
Open
NC
NC
VCCD 36
VCCA
2 µF
35
14 NC
VCCA 34
15
16
(LSB) DA8
VRM
33
Open
DA7
DA6
DA5
Digiral
Output
(DAC)
32
VINA
17
18
VCLMP 31
VOUTC 30
1 µF
19
20
21
DA4
Analog
Input
(ADC)
VINC
VRT
29
28
DA3
DA2
ADC
Clock
Input
27
26
VCCA
(MSB) DA1
ADCLK
22
23
1 µF
VCCD
AGND 25
24
DGND
17
MB40168/MB40178
■ NOTES ON PCB LAYOUT
Power Supply Lines
The device’s power supply lines (VCCA, VCCD, AGND and DGND) should be laid out as analog lines and should
be separated in so far as possible from other digital lines in order to reduce noise. Also the track widths of these
lines should be as wide as possible to reduce parasitic impedance.
Coupling Capacitors
The device’s power supply lines VCCA and VCCD and the reference voltage pins VRIN, VREF, VRB, and VRT should
be decoupled to analog ground by means of approx. 1 µF capacitors which should be placed as close as possible
to these pins.
Digital Output Load
The load at the digital outputs should be kept as low as possible to prevent noise in the power supply lines
caused by digital output switching. If, due to long wiring, the load becomes large then a buffer with small input
capacitance should be inserted to reduce load capacitance.
■ OTHER NOTES ON OPERATION
When using the D/A converter with its VRIN pin connected to the VREF pin, the A/D converter’s VRB pin must also
be connected to the VREF because otherwise the internal reference voltage generation circuitry cannot output 3 V.
When using the D/A converter with 8 bit resolution the DD9 (LSB) pin should be grounded.
18
MB40168/MB40178
■ PACKAGE DIMENSIONS
48 pin, Plastic SH-DIP
(DIP-48P-M01)
+0.20
43.69–0.30
+.008
1.720–.012
INDEX-1
INDEX-2
13.80±0.25
(.543±.010)
0.51(.020)MIN
5.25(.207)
MAX
0.25±0.05
(.010±.002)
3.00(.118)
MIN
+0.50
1.00–0
0.45±0.10
(.018±.004)
15.24(.600)
+.020
TYP
15°MAX
.039–0
1.778±0.18
(.070±.007)
1.778(.070)
MAX
40.894(1.610)REF
C
1994 FUJITSU LIMITED D48002S-3C-3
Dimensions in mm (inches).
(Continued)
19
MB40168/MB40178
44 pin, Plastic QFP
(FPT-44P-M11)
14.40±0.40SQ
(.567±.016)
2.35(.093)MAX
10.00±0.20SQ
(.394±.008)
0.05(.002)MIN
(STAND OFF)
33
23
Details of "A" part
34
22
0.15(.006)
0.20(.008)
8.00
(.315)
REF
11.60±0.30
(.457±.012)
INDEX
"A"
0.18(.007)MAX
0.53(.021)MAX
44
12
Details of "B" part
1
11
LEAD No.
0.80(.0315)TYP
0.15±0.05
(.006±.002)
0.30±0.10
(.012±.004)
M
0.16(.006)
0~10°
"B"
1.40±0.30
(.055±.012)
0.10(.004)
C
1994 FUJITSU LIMITED F44018S-1C-1
Dimensions in mm (inch).
20
MB40168/MB40178
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3753
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
Fax: (408) 432-9044/9045
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281 0770
Fax: (65) 281 0220
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9703
FUJITSU LIMITED Printed in Japan
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