MB42M001PV_技术文档

FUJITSU MICROELECTRONICS

DATA SHEET

DS04–29135–1E

ASSP

3ch Capacitive Sensor IC with Internal Non-volatile Memory

3ch Sensor Conditioner IC

MB42M001

■ DESCRIPTION

The MB42M001 IC converts changes in the capacitance of a capacitive sensor into changes in the output

voltage.

The IC integrates a C-V (Capacitance - Voltage) converter circuit, a voltage amplifier, and a regulator circuit

and can be adjusted to provide an optimal match with the characteristics of the sensor. The adjustment

circuit can be controlled externally via a serial interface and the adjustment data can be stored in internal

non-volatile memory. The IC supports up to three capacitive sensor channels, each of which can be

adjusted independently.

■ APPLICATION

• Detection of capacitance changes in capacitive sensors

• 3-axis capacitive acceleration sensors

• Capacitive pressure sensors

■ FEATURES

• Convert and amplify the changes in the capacitance of a capacitive sensor and output this as an analog

voltage

• Can connect up to three capacitive sensor channels

• Sensor capacitance tolerance: 0 pF to 100 pF(depends on sensitivity setting in IC)

• Sensor capacitance detection tolerance: 0.05 V/pF to 100 V/pF

• The C-V conversion gain and offset adjustment can be set via the serial interface

• Internal non-volatile flash memory (1280 bit) can store the gain and offset adjustment for the C-V

conversion circuit

• The temperature characteristics of the sensor can be corrected by adjusting the offset which incorporates

a temperature coefficient

• Includes a shutdown function

• Supply voltage: V^DD= 2.7 V to 5.5 V

• Power supply current in 3ch mode: IDD (normal) = 280 µA@VDD = 3 V, 1ch mode: IDD (normal) =

220 µA@VDD = 3 V

2008.12

MB42M001

■ PIN ASSIGNMENT

• Package: BCC-32

(TOP VIEW)

24 23 22 21 20 19 18

25

26

17

16

SIN1C

SIN2C

AGND2

SIN1A

SIN2A

DGND

SIN1B

SIN2B

VOUT_B

VOUT_C

VDD

27

28

29

30

31

32

15

14

13

12

11

10

AGND1

VREF

VFA

SD

9

VDD_M

1

2

3

4

5

6

7

8

(LCC-32P-M08)

No.

Pin Name

Pin Description

Pin Name

Pin Description

No.

17

18

19

20

21

1

TEST_ME Pin for IC shipping test

TEST_MV Pin for IC shipping test

VOUT_A A channel output pin

2

FLT2B

FLT2A

B channel output filter 2

A channel output filter 2

A channel output filter 1

B channel output filter 1

3

CS

CLK

DIN

Serial I/F chip select

Serial I/F clock input

Serial I/F data input

4

FLT1A

FLT1B

FLT1C/

VSRV

5

6

DOUT

Serial I/F data output

22

23

C channel output filter 1/VSRV

7

ALARM Monitor I/O

VMT Monitor I/O

VDD_M Powersupplypinformemory

FLT2C

C channel output filter 2

8

24 SIN_COM COM (common) pin of capacitance sensor

9

25

26

27

28

29

30

31

32

SIN1C

SIN2C

C channel sensor connection pin

10

11

12

13

14

SD

VFA

Shutdown input

Regulator output

AGND2 Analog GND pin

VREF

Reference voltage output

SIN1A

SIN2A

DGND

SIN1B

SIN2B

A channel sensor connection pin

AGND1 Analog GND pin

VDD Power supply pin

A channel sensor connection pin

Digital GND pin

15 VOUT_C C channel output pin

16 VOUT_B B channel output pin

B channel sensor connection pin

2

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MB42M001

■ DESCRIPTION OF PIN FUNCTIONS

1. Power Supply Pins

Pin Name

I/O

Description of Pin Function

VDD is a power supply pin.

I/O Equivalent Circuit

VDD_M is a power supply pin for memory.

• Connect a power supply stabilization capacitor

close to the IC pin(chip capacitor 1 µF or more).

[Normal operation]

Power supply

VDD_M

To memory

circuitpower

supply

VDD_M

(2.7 V to 5.5 V)

Power

VDD,

VDD

IC

VDD_M

supply pins

To analog

circuitpower

supply

VDD

[When writing to memory]

Power supply 5.0 V

VDD_M

Power supply (2.7 V to 5.5 V)

VDD

IC

AGND1 and AGND2 are the analog GND pins.

DGND is the digital GND pin.

AGND1,

AGND2,

DGND

GND pins

In the connection to the external power supply,

connect all GND pin to a common point.

2. Reference Voltage Source, Regulator Pin

Pin Name

I/O

Description of Pin Function

I/O Equivalent Circuit

Capacitor connection pin for the regulator for the

IC internal circuit.

VDD (2.7 V to 5.5 V)

• Connect a capacitor (1 µF or more

recommended) between the VFA pin and GND

to stabilize the voltage. Use a ceramic capacitor

and connect close to the VFA pin.

To analog

output pin

VFA

• The VFA voltage is used as the power supply

for the internal circuits in the IC (VFA = 2.6 V to

2.87 V).

VFA

Capacitor connection pin for the reference

voltage for analog circuits.

VDD / VFA

Connect a capacitor (1 µF or more

recommended) between VREF pin and GND to

stabilize the voltage. Use a ceramic capacitor

and connect close to the VREF pin.

To analog

output pin

VREF

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MB42M001

3. Pins for Connecting Sensor Element

Pin Name

I/O

Description of Pin Function

I/O Equivalent Circuit

These pins connect to the sensor elements.

1) SIN1A/SIN2A: connection pin for A channel

2) SIN1B/SIN2B: connection pin for B channel

3) SIN1C/SIN2C: connection pin for C channel

VDD / VFA

SIN1A,

SIN2A,

SIN1B,

SIN2B,

SIN1C,

SIN2C

To analog When the capacitances are such that

SINxx

I/O pin

SIN1x>SIN2x, the output voltage becomes

positive. (The capacitance is the total

capacitance internal and external to the IC.)

Note: Take care to prevent any DC path from the

SINxx pins. This excludes the case when

the CV amplifier is in V mode.

These pins connect to the sensor elements.

1) When the CV amplifier is operating in C mode

Connect to the COM (common) pin of the pair

capacitance sensor. Install a GND shield

between the SIN_COM pin and SINxx pins if

possible.

VDD / VFA

To analog

input pin

SIN_COM

2) Leave open circuit when the CV amplifier is

operating in V or T mode.

4. Filter Pins

Pin Name

I/O

Description of Pin Function

I/O Equivalent Circuit

These pins connect to the low pass filter

capacitors.

1) FLT1A and FLT2A are the connection pins for

A channel.

2) FLT1B and FLT2B are the connection pins for

B channel.

VFA VDD

FLT1A,

FLT2A

Amp3

FLT2x

FLT1x

Approx.

110 kΩ

Approx.

110 kΩ

To analog

output pin

3) FLT2C is the connection pin for C channel.

FLT1B,

FLT2B

Notes : • Connect a capacitance (4.7 nF or more)

to FLT2x.

FLT2C

Amp2

• Connect to FLT1x if needed.

Example : C^FLT1= 10 nF , CFLT2 = 15 nF

The function of the FLT1C/VSRV pin is selected

by the SRV register setting.

VFA VDD

Amp3

FLT2C

[Function 1 : FLT1C]

Connect the low pass filter capacitor used for the

C channel filter.

FLT1C/

VSRV

To analog

output pin

Amp2

FLT1C/

VSRV

[Function 2 : VSRV]

Connect a capacitor (1 µF or more) between the

AGND pins to stabilize the VSRV voltage which

uses SRV to bias the CV amplifier.

VSRV

4

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MB42M001

5. Serial Interface and Shutdown Pins

Pin Name

I/O

Description of Pin Function

I/O Equivalent Circuit

Chip select for the serial interface

• CMOS digital input pin

VDD

• With pull-down resistor (250 kΩ typical)

• CS = “H”: Enables communication

• CS = “L”: Disables communication. The DOUT

pin output goes to “Z”.

Digital

input pin

CS

Clock input for the serial interface

• CMOS digital input pin

VDD

• With pull-down resistor (120 kΩ typical)

Digital

input pin

CLK

DIN

CLK

Data input for the serial interface

• CMOS digital input pin

• With pull-down resistor (approx. 500 kΩ)

VDD

Digital

input pin

DIN

Data output for the serial interface

VDD

1) Tri-state CMOS digital output pin

When the CS pin is “L”, the DOUT output goes

to “Z”.

Digital

DOUT

DOUT output pin

(Tri-state)

2) Outputs the busy state during serial

communications or while the sequencer inside

IC is operating (Normal is Low, busy state is

High).

3) Outputs flash memory data.

Shutdown pin

• CMOS input pin, no pull-down resistor.

VDD

4 types of mode can be selected by combination

of the SD, DIN and CS pins.

SD

For detail, see “■POWER-ON AND SHUTDOWN

FUNCTIONS 4 Operation modes specified by the

SD pin and serial interface input pins”.

Digital

SD

input pin

Note: Notation used for logic levels

“H” : CMOS logical “High” (VDD voltage level), “L”: CMOS logical “Low” (GND voltage level)

“Z” : High impedance (1 MΩ or more)

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MB42M001

6. Amplifier Output Pins

Pin Name

I/O

Description of Pin Function

I/O Equivalent Circuit

Output pins of the sensor conditioner IC.

VDD

1) VOUT_A: output pin for A channel

2) VOUT_B: output pin for B channel

3) VOUT_C: output pin for C channel

VOUT_A,

VOUT_B,

VOUT_C

Analog

output pin

VOUT_x

7. Voltage Monitor/Test Pins

Pin Name

I/O

Description of Pin Function

Voltage monitor pin

I/O Equivalent Circuit

IC internal voltages can be monitored by setting

the AMT register. By backing up the AMT register

setting in flash memory, the voltage can be

output from the VMT pin permanently. For

example, you can output the internal temperature

sensor voltage or internal reference voltage.

Normally

used as an

analog

VDD

output pin

VMT

Used as an

analog/

digital I/O

pin during

testing

Notes: • The VMT pin has no output drive

capability. Since the voltage may vary

depending on the load resistance,

provide a load of 500 kΩ or more if the

voltage precision is needed.

• Although this pin can be set as a test

input pin by setting the TMR register,

please do not use this function.

Alarm detection output pin

Outputs Low ( = 0 V) when no alarm exists, and

High ( = VDD) during sequence operation or

when an alarm is detected.

• When SD = H, the ALARM output is preset to

“H”.

Normally

used as a

digital

VDD

output pin

ALARM

• An alarm is detected if a CRC error occurs

when writing to flash memory or an error occurs

when transferring data from memory to

registers.

ALARM

Used as an

analog/

digital I/O

pin during

testing

Note : Although this pin can be set as a test input

pin by setting the TMR register, please do

not use this function.

Test pins for flash memory.

Connect to GND or leave open circuit.

TEST_MV, Analog/

TEST_ME, digitalinput

TEST_MN pin

TEST_Mx

Note: There is no package pin that corresponds

to the TEST_MN terminal (TEST_MN is a

pad on the IC chip only).

6

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MB42M001

■ BLOCK DIAGRAM

Note: The TEST_MN terminal can use only wafer (chip) product.

DS04–29135–1E

7

MB42M001

Block Description

• CV-Amp / Drv (capacitance-voltage conversion amplifier)

CV-Amp is an amplifier that converts capacitance changes to a voltage. Drv is a drive circuit used to provide

voltage pulses to capacitance sensor elements. The conversion gain is expresed as V/pF and is defined as

the conversion of the change in capacitance at input pin SINxx to a change in voltage.

(1 V/pF value of 1 indicates that an output of 1 V represents a capacitance change ∆C = 1pF.)

The CVA, COF, and CVM registers specify the detection sensitivity and range adjustments for the CV-Amp.

• Amp1 (Amplifier1)

• Voltage amplifier for the CV-Amp output signal.

• The VGA1 register adjusts the Amp1 gain and the VOF1 register adjusts the offset prior to the Amp1 input.

• Amp2 (Amplifier2)

• A buffer amplifier. (Gain × 2)

• The VOF2 register adjusts the offset after the Amp2 output. The TOF register adjusts the temperature

characteristics of the Amp2 output offset.

• Amp3 (Amplifier3)

• An output amplifier. (Gain × 7)

• The FLT1x and FLT2x pins on the Amp3 input are provided to connect the capacitor for a low pass filter.

• VREG, VBGR, VTMP, VREF (bias circuit)

• VREG outputs the VFA voltage from the internal regulator circuit in the IC.

• VBGR, VTMP, and VREF are reference voltage sources in the IC. The voltages are adjusted by the TREF

and VREF registers.

• Monitor/TEST (Monitor/Test circuit)

• A test circuit used to monitor voltages in the IC.

• The AMT register is used to select and test the voltage to monitor.

• OSC (Internal oscillator circuit)

• An oscillator circuit for the CV-Amp and digital circuits.

• POR (Power-on reset)

• A power-on reset circuit.The internal circuits are reset at power-on or via the SD pin.

• Digital I/F, Test (Serial interface, memory circuit test)

• There include testing of the digital circuits for the serial interface, access circuits for the internal IC

registers and non-volatile memory, and digital circuits.

• E²PROM (Flash Memory)

• Small non-volatile memory. Used to store the adjusted register data.

8

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MB42M001

■ ABSOLUTE MAXIMUM RATINGS

Rating

Typ

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

Power supply voltage

V^DD

VDD = VDD_M

− 0.3

⎯

+ 6

V

VDD + 0.3

and

5.7 V

Pinsbelongingtothe

PinVDD applied

voltage pin group

VIO5

− 0.3

⎯

Pin voltage

VFA is the voltage

for the internal

regulator in the IC

(approx. 2.5V to 3 V)

VFA + 0.5

and

Pins belonging to

the PinVFA applied

voltage pin group

V^IO3

− 0.3

⎯

V

4.0 V

Output current

I^IO

⎯

− 5

⎯

+ 5

mA

Storage temperature

T^ST

− 55

+ 125

°C

Operating

temperature

TOP

⎯

− 40

⎯

+ 85

°C

[Pin group: PinVDD]

VOUT_A, VOUT_B, VOUT_C, VMT, ALARM, SD, CS, CLK, DIN, DOUT, TEST_MV, TEST_ME

[Pin group: PinVFA]

VFA, FLT1A. FLT2A. FLT1B, FLT2B, FLT2C, FLT1C/VSRV, VREF, SIN_COM, SIN1A, SIN2A, SIN1B, SIN2B,

SIN1C, SIN2C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Condition

VDD = VDD_M

Unit

Remarks

Min

Typ

Max

V^DD

2.7

3.3

5.5

V

Power supply

voltage

VDD_M pin voltage for flash

memory programming

V^DDM

4.5

⎯

5

5.5

External serial

interface clock

f^CLK

⎯

100

⎯

300

kHz

No. of flash

memory rewrites

VDD = 5.0 V, Ta = + 25°C

⎯

2000 Times

Ta1

Ta2

VDD ≥ 2.7 V

VDD ≥ 2.9 V

− 30

− 40

+ 25

+ 85

°C

Operating

temperature

Ambient

temperature

Notes: • When data is written to flash memory, pin VDD_M on the IC must be set to 5 V.

• If flash memory programming (Write) is operated when the VDD_M voltage is outside the range

(4.5 V to 5.5 V), the data stored in the flash memory cannot be held for a long time.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

onthedatasheet.Usersconsideringapplicationoutsidethelistedconditionsareadvisedtocontact

their representatives beforehand.

DS04–29135–1E

9

MB42M001

■ ELECTRICAL CHARACTERISTICS

1. Supply Voltage, Reference Voltage

(Unless specified, VDD = VDD_M = 2.7 V to 5.5 V, Ta = + 25°C )

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Remarks

VDD = VDD_M = 3 V,

No input signal

Register standard setting

IDD3

⎯

280

⎯

µA

VDD = VDD_M = 3 V,

No input signal

Register 1 channel mode

setting

Power supply

current

I^DD31

⎯

220

⎯

µA

*

VDD = VDD_M = 5 V,

No input signal

Register standard setting

I^DD5

I^DSD3

I^DSD5

⎯

310

⎯

µA

VDD = VDD_M = 3 V,

No input signal

SD = 3 V

⎯

Power supply

current

shutdown

Does not

include pin leak

current*

VDD = VDD_M = 5 V,

No input signal

SD = 5 V

⎯

µA

Regulator

output

VFA voltage

V^FA

VDD = 3.0 V

2.67

V

Reference

voltage output

VREF voltage

V^REF

⎯

0.6

⎯

V

Internal

Register AMT = 05H,

after TREF register

adjusted

temperature

sensor output

voltage

V^MT1

⎯

1.97

⎯

mV/°C

Register AMT = 06H,

after TREF register

adjusted

VMT voltage

Internal BGR

voltage

V^MT2

1.223

V

Register AMT = 07H,

after VREF register

adjusted

Internal

reference

voltage

V^MT3

⎯

0.6

⎯

V

* : Standard measurement conditions

• For the register settings, set the bias voltage adjustment in VREF and TREF, set the CV conversion

amplifier adjustment in CVA and COF, and set the other registers to “00”.

• Set the pins or connect to external components as specified in the table below.

Pin Type

Logic input pin

Logic output pin

Pin Name

CS, CLK, DIN, SD

Pin Condition

GND

DOUT

Open

SIN1A, SIN2A, SIN1B, SIN2B,

SIN1C, SIN2C, SIN_COM

Analog input pin

Open or sensor capacitance

Analog output pin

Filter pin 1

VOUT_A, VOUT_B, VOUT_C

FLT1A, FLT1B, FLT1C/VSRV

FLT2A, FLT2B, FLT2C

Open

Open or external capacitor

External capacitor (chip capacitor 1µF)

External capacitor (chip capacitor 1µF or more)

Open

Filter pin 2

Reference voltage output VFA, VREF

Monitor pin

Test pin

VMT, ALARM

TEST_MV, TEST_ME

GND or open

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MB42M001

2. Sensor Capacitance Conditions, C-V Conversion Gain Characteristics

[C-V amplifier/C mode operation]

(Unless specified, VDD = VDD_M = 2.7 V to 5.5 V, Ta = + 25°C )

Parameter

Sensor

capacitance

tolerance

Symbol

C^SIN

Condition

Min

Typ

Max Unit

Remarks

Capacitance

between package

input pin and

CVA register setting is

N>144

0

⎯

100*

pF

external circuit

Sensor

capacitance

offset tolerance

Difference

COF and VOF registers

adjustment is required

C^SOF

− 50*

0

+ 50* pF between pair

capacitances

Detectable

range of sensor

capacitance

changes

Sensitivity adjustments for

each register are required

For a final change

in output of 1 V

C^D

0.01*

⎯

20*

pF

C-V conversion

gain

VOUT (final output)

converted value

ACVO

0.05*

⎯

100* V/pF

kHz 1ch mode

C-V conversion

drive frequency

f^DRV

⎯

24

⎯

* : The rated values for sensor capacitance vary depending on the parasitic capacitance and sensitivity

settings.

The detection sensitivity and tolerance vary depending on the sensor element structure, equivalent circuit

of detected capacitance, number of channels, IC settings, and similar.

• Example of Capacitance Sensor Connection

• The tolerance for the detected capacitance and

parasitic capacitance increase or decrease

depending on the sensor element and IC settings.

Sensor elements

SIN_COM

Cs1_C

• An indicative tolerance for a CVA register value of

N is:

Tolerance < (N × 0.625 + 10) pF

SIN1C

SIN2C

Cp_COM

Cp2_C

Cp2_A

Cp2_B

Cp1_C

Cs2_C

Cs1_A

MB42M001

SIN1A

SIN2A

Note: The actual value will vary depending on the

conditions.

Cp1_A

Cp1_B

Cs2_A

Cs1_B

SIN1B

SIN2B

Example: Setting condition: Set CVA register to

N>144

Cs2_B

Parameter

Capacitances

Tolerance

Detected

capacitance

Cs1_*, Cs2_*

< 100 pF

Cp1_*, Cp2_*

Cp_COM

< 100 pF

Parasitic

capacitance

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MB42M001

3. Voltage Amplifier, Output Characteristics

(Unless specified, VDD = VDD_M = 2.7 V to 5.5 V, Ta = + 25°C )

Parameter

Voltage

amplifier gain

adjustment

Symbol

A^VGA

Condition

Min

Typ

Max

Unit

Remarks

Based on the register VGA

adjustment of the total gain

for Amp1 to Amp3

14

⎯

112

Times

VOUT_xoutput

offset

adjustment

VOUT_x output voltage

after registers VOF1 and

VOF2 are adjusted

V^OF

V^TOF

fvout

⎯

0

⎯

mV

*

VOUT_x output voltage

after register TOF adjusted

(A channel: 255 adjustment

steps)

(B and C channels: 31

adjustment steps)

VOUT_xoutput

offset

temperature

adjustment

mV/

°C

VOUT_xoutput

response

frequency

100

Hz

Internal resistor

approx. 110 kΩ

Filter1 (LPF)

Filter2 (LPF)

f^LPF1

f^LPT2

CFLT1 = 10 nF

CFLT2 = 15 nF

⎯

145

96

0

⎯

Hz

Internal resistor

approx. 110 kΩ

3.6 V < VDD < 5.5 V

∆VOUT < 20mV

⎯

mA

0.4 V < V^OUT

VOUT < VDD − 0.4 V

*

VOUT_xoutput

drive capability

I^OUTL

2.7 V < V^DD< 3.6 V

∆VOUT < 40 mV

⎯

0

VDD −

0.1

VOUT_xoutput

voltage range

V^OUTD

IOUT =

0.1 mA

0.1

⎯

V

*

aF

C^NZ1

⎯

4

8

⎯

rms/ 1 ch operation

Hz

Low-passnoise

input converted

value

Band width frequency <

100 Hz

aF

C^NZ23

rms/ 3 ch operation

Hz

* : “VOUT_x” is VOUT_A, VOUT_B, and VOUT_C pins.

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4. Digital I/O Block

(Unless specified, VDD = VDD_M = 2.7 V to 5.5 V, Ta = + 25°C )

Parameter

Symbol

V^IH

Condition

Min

Typ

Max

Unit Remarks

VDD × 0.7

+ 0.4

⎯

V

Input voltage CLK,

DIN, CS, and SD

pins

VDD ×

0.3 − 0.4

V^IL

⎯

V

I^IH

I^IL

VDD = 5 V, VIH = 5 V

VDD = 5 V, VIL = 0 V

⎯

1.0

µA

Input current SD

− 1.0

⎯

With

µA pull-down

resistor

IIH

VDD = 5V, VIH = 5 V

⎯

60

Input current CLK,

DIN and CS pins

IIL

VDD = 5 V, VIL = 0 V

IOH = − 1 mA

− 1.0

⎯

µA

Output voltage

DOUTandALARM

pins

V^OH

VDD − 0.4

V

V^OL

IOL = 1 mA

⎯

0.4

V

VDD = 5 V, VOH =

VDD − 0.4 V

Output current

DOUTandALARM

pins

I^OH

I^OL

⎯

1.0

⎯

− 1.0

⎯

mA

µA

VDD = 5 V, VOL = 0.4 V

VDD = 5 V, VIH = 5 V

CS pin = 0 V

I^OZH

− 1.0

High-z input

current DOUT pin

VDD = 5 V, VIL = 0 V

CS pin = 0 V

IOZL

1.0

⎯

µA

5. Flash Memory Block

Parameter Symbol

(VDD = VDD_M = 5.0 V, Ta = + 25°C )

Condition

Min

Typ

Max

Unit Remarks

From issuing an 8-byte data

write

Write time

write time command until the write

operation completes:

f^CLK= 300 kHz

⎯

63.8

ms

From issuing an 8-byte data

read

read time command until the read

operation completes:

f^CLK= 300 kHz

Read time

⎯

217

µs

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13

MB42M001

6. Serial Interface I/O Timing

(Unless specified, VDD = VDD_M = 2.7 V to 5.5 V, Ta = + 25°C )

Parameter

CLK clock frequency

CLK “L” time

Symbol

f^CLK

Min

⎯

Typ

⎯

Max

300

⎯

Unit

kHz

µs

Remarks

t^Low

1.3

⎯

CLK “H” time

t^High

⎯

µs

Rising time

tr

0.3

⎯

µs

CLK, DIN, CS

Falling time

t^f

⎯

µs

Data setup time

Data hold time

t^SU:data

tHD:data

t^bus

0.1

0

µs

⎯

µs

Data bus switching time

CS to CLK hold time

Condition setup time

1.0

⎯

µs

t^HD:CS

tSU:cond

⎯

µs

⎯

µs

tr

tf

tHigh tLow

tHD:CS

CLK

DIN

tsu:cond

tSU:data tHD:data

tHD:data

tSU:data

DOUT

HiZ

tbus

CS

Since “H” is output from DOUT if the

sequencer inside IC is operating, start

communications only after the output goes

to “L”.

DOUT goes to “L” immediately after setting CS

to High, next, the output goes to “Z” on the

rising edge of the clock.

14

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MB42M001

■ SENSOR CONDITIONER FUNCTION

• The sensor conditioner function sets IC register data to adjust the gains and offsets to correct for the sensor

characteristics and sensor scatter.

• A register name and address are defined for each register and adjustment can be performed by modifying

these register settings via the serial interface.

Refer to the following chapter “■ DESCRIPTION OF THE SERIAL INTERFACE” and “■ HOW to MAKE

SETTINGS” for information about the register settings.

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15

MB42M001

1. Memory Map

This section defines the memory map that represents the continuous address ranges corresponding to the

registers and the flash memory (non-volatile memory).

1) Register area: 00^Hto 57H

The register area (User area) available to users is 10^Hto 2FH.

2) Flash memory (non-volatile memory) area: 58H to FFH

• The flash memory area available to users is 70H to B7H.

• The data at addresses 70^Hto 8FH in flash memory are automatically transferred to addresses 10H to

2FH in the register area at power-on or when a power-on reset occurs.

Address

00H

08H

10H

18H

20H

28H

30H

38H

40H

48H

50H

58H

60H

68H

70H

78H

80H

88H

90H

98H

A0H

A8H

B0H

B8H

C0H

C8H

D0H

D8H

E0H

E8H

F0H

F8H

+0

+1

+2

+3

+4

+5

+6

+7

mode

AMT

CVM

CTL

TREF

VREF

SRV

TGA

CVA (A) CVA (B) CVA (C) COF (A) COF (B) COF (C)

User

MOD VGA1 (A) VGA1 (B) VGA1 (C) VOF1 (A) VOF1 (B) VOF1 (C)

Register

area

LTC

TOF (A) TOF (B) TOF (C) VOF2 (A) VOF2 (B) VOF2 (C)

FMTM

DTM

CTL

TMR

Mainte

CRC

CRC Module

CRC

AMT

CVM

TREF

VREF

SRV

TGA

CVA (A) CVA (B) CVA (C) COF (A) COF (B) COF (C) CRC

MOD VGA1 (A) VGA1 (B) VGA1 (C) VOF1 (A) VOF1 (B) VOF1 (C) CRC

LTC TOF (A) TOF (B) TOF (C) VOF2 (A) VOF2 (B) VOF2 (C) CRC

CRC User

CRC

Flash

Memory

area

Module

CRC

CRC Mainte

CRC

Note : CRC : CRC (error checking code) data is added for each block of 8 bytes (7 data bytes + 1 CRC byte).

16

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MB42M001

2. Register Name List

Register

Name

Memory

Address

Function

Address*¹

10

11

AMT

Various control settings

Selects the signal to monitor from the VMT pin.

70H

71H

CTL

Used to adjust the reference voltage VBGR and the temperature sensor

voltage VTMP at room temperature ( + 25°C).

12

TREF

VREF

72H

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

Adjusts the VREF reference voltage in the IC.

Register 14H and memory 74H have no function.

73H

74H

75H

76H

77H

78H

79H

7AH

7BH

7CH

7DH

7EH

7FH

80H

81H

82H

83H

84H

85H

86H

87H

88H

89H

8AH

8BH

8CH

8DH

8EH

8FH

SRV

TGA

Selects the VSRV drive voltage for the CV amplifier.

Temperature dependence gain adjustment

Register 17H has no function. Set a CRC*²code in memory location 77H.

CVM

CVA

Selects the CV amplifier modes.

Ach Adjusts the CV amplifier conversion gain for A channel.

Bch Adjusts the CV amplifier conversion gain for B channel.

Cch Adjusts the CV amplifier conversion gain for C channel.

Ach Adjusts the sensor input offset for A channel.

Bch Adjusts the sensor input offset for B channel.

Cch Adjusts the sensor input offset for C channel.

Register 1FH has no function. Set a CRC*²code in memory location 7FH.

MOD function (A channel output monitor)

COF

MOD

Ach Adjusts the Amplifier 1 gain for A channel.

VGA1 Bch Adjusts the Amplifier 1 gain for B channel.

Cch Adjusts the Amplifier 1 gain for C channel.

Ach Adjusts the pre-input offset for Amplifier 1 for the A channel.

VOF1 Bch Adjusts the pre-input offset for Amplifier 1 for the B channel.

Cch Adjusts the pre-input offset for Amplifier 3 for the C channel.

Register 27H has no function. Set a CRC*²code in memory location 87H.

LTC

Adjusts the linearity for A channel.

Ach Adjusts the temperature dependence characteristic of A channel.

Bch Adjusts the temperature dependence characteristic of B channel.

Cch Adjusts the temperature dependence characteristic of C channel.

Ach Adjusts the pre-input offset for Amplifier 3 for the A channel.

TOF

VOF2 Bch Adjusts the pre-input offset for Amplifier 3 for the B channel.

Cch Adjusts the pre-input offset for Amplifier 3 for the C channel.

Register 2FH has no function. Set a CRC*²code in memory location 8FH.

54

TMR

Enables writing directly from the serial interface to a register.

None

*1 : Addresses are in hexadecimal.

*2 : CRC: CRC (error checking code) data is added for each block of 8 bytes (7 data bytes + 1 CRC byte).

DS04–29135–1E

17

MB42M001

3. Example Register Setting Order

Using the following sequence to set registers is recommended:

1) Preparation

Initially, set the amplifier gain and offset settings to their default or minimum values.

Normally, adjustment is performed with the sensor zeroed and at a temperature of + 25°C.

2) Set Each Register

To start setting the register data, first set the TMR register.

Note that turning off the power or a power-on reset initialize the register data.

(To invoke a power-on reset, change the SD pin from 0 V → VDD → 0 V.)

Use the serial interface to set the registers as described in the “■ How to Create Setting Data” section.

3) Reference Voltage Circuit Adjustment (Registers: TREF, VREF)

Measure the VMT pin (Voltage Monitor Test) voltage as you adjust the TREF and VREF registers.

The VMT pin can be switched between outputting the VBGR (reference voltage), VREF (reference voltage),

and VTMP (temperature sensor voltage) voltages by changing the AMT register settings. However, the VMT

pin output voltage is offset from the internal voltage being monitored by the offset voltage of the VMT output

buffer amplifier.

First, set the upper 3 bits of the TREF register to adjust the VBGR voltage.

Next, use the VREF register to adjust the VREF voltage and then use the lower 5 bits of the TREF register

to adjust the internal temperature sensor.

4) CV Amplifier Adjustment (Registers: CVA, COF, CVM, SRV)

Adjust the CVA and COF registers.

The IC can be adjusted to support a wide range of sensors by setting the CVM and SRV registers.The

normal settings are CVM = 0 and SRV = 0.

To monitor the adjustment voltage, set the Amplifier 1 and 2 gains to their minimum settings and then set

the AMT register to monitor the FLT pin voltage for each channel from the VMT pin.

First, specify the CV conversion value in the CVA register.As increasing the CV conversion value may

exceed the tolerance range for the input capacitance, set the CVA register based on the tolerance range for

the input capacitance. Next, use the COF register to adjust the SIN1 and SIN2 offset capacitance.

5) Latter Stage Amplifier Adjustment (Registers: VGA, VOF1, VOF2)

Use the VGA register to adjust the Amplifier 1 gain if the gain is insufficient with CVA only (the normal setting

is × 1). Use the VOF1 register to adjust the Amplifier 1 input stage offset. Adjust by using the AMT register

setting to monitor the FLT pin voltage for each channel via the VMT pin.

Use the VOF2 register to adjust the Amplifier 3 input stage offset. Monitor the output pin VOUT voltage while

adjusting.

6) Temperature Dependence Characteristic Adjustment (Register: TOF)

Adjust the TOF register to apply a linear correction to the offset temperature dependence characteristic.

18

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MB42M001

4. Adjustment Function Explanation

The key words used to explain the registers settings are defined as follows:

• Notation for bit settings

The following notation is used in the register explanations.

N (Decimal) ← (B3, B2, B1, B0),

S (Sign bit) ← S

This indicates that the binary bit setting values, B3, B2, B1, and B0, are converted to decimal.

N = 2³• B3 + 2²• B2 + 2¹• B1 + 2⁰• B0

When the sign bit S is used, S = 0 indicates positive and S = 1 indicates a negative value.

• <Optional>

<Optional> is used in some register explanations.

This indicates that the <Optional> function can be used but that the characteristics specified in this manual

are not guaranteed.

Use the function for prototypes or testing.

• <Test>

<Test> is used in some register explanations.

This indicates that the <Test> function can be used but that the operation is not guaranteed.

Use the function for testing or similar.

• Do not set addresses or data that is not described in the register explanations.

1) Test Mode Settings

TMR register (Test Mode Register: Permit direct access to registers)

Enables the register to be written directly from the serial interface.

Address: 54H (1 byte access)

Bit setting

7

6

5

4

3

2

1

0

B7 B6 B5 B4 B3 B2 B1 B0

0

1

0

1

0

Normal use status

Register access mode. Writing to 10^Hto 2FH is enabled.

Notes: • Setting the bits to any value other than that above is prohibited.

• Setting the data at 54^Hfrom A0H back to 00H clears register access mode. Immediately after clearing

access mode, a power-on reset is invoked and the current register data is lost.

The data in the flash memory data area (70^Hto 8FH) is then copied to the register data area (10H

to 2FH).

DS04–29135–1E

19

MB42M001

2) Reference Voltage Circuit Adjustment

VREF (Voltage reference : IC internal reference voltage adjustment)

Address: 13H

Bit setting

Adjusts the VREF reference voltage in the IC.

Monitor the VREF voltage from the VMT pin and adjust to

600 mV (Tj = + 25°C).

The VREF voltage is generated based on the BGR voltage.

7

6

5

4

3

2

1

0

S

B4 B3 B2 B1 B0

• For no correction

:S = 0, N = 0

• For correction to + side :S = 0, correction amount =

about +N × 2.36 mV (N = 1 to 31)

• For correction to - side :S = 1, correction amount =

about -N × 2.36 mV (N = 0 to 31)

• N (Decimal) ← (B4, B3, B2, B1, B0)

• S (Sign bit) ← S

Note : Set the VMT pin to monitor the VREF voltage (see the

“ 9) Monitor Circuit Selection”).

TREF (Voltage temperature reference: BGR voltage and IC internal temperature sensor adjustment

(1) Adjust the internal temperature sensor.

Set the VMT pin to monitor the VTMP voltage and adjust

VREF to (600 mV) (Tj = + 25°C).

Address: 12^H

Bit setting

7

6

5

4

3

2

1

0

• For no correction

• For correction to + side :S = 0, correction amount =

about +N × 2.9 mV (N = 1 to 15)

• For correction to - side :S = 1, correction amount =

about -N × 2.9 mV (N = 0 to 15)

:S = 0, N = 0

R2 R1 R0

S

T3 T2 T1 T0

1) VTMP voltage adjustment

• N (Decimal) ← (T3, T2, T1, T0)

• S (Sign bit) ← S

Notes : • Set the VMT pin to monitor the TREF voltage (see

the“ 9) Monitor Circuit Selection”).

2) VBGR voltage adjustment

• Select using the R2, R1, and R0 bits

• The adjustment step amounts might not be equal.

• The VTMP voltage change can be estimated as

∆VTMP = 1.97 mV/∆T + 0.6 µV/∆T².

(2) Adjust the VBGR reference voltage in the IC.

Set the VMT pin to monitor the VBGR voltage and adjust to

be in the range 1.220 V to (1.223 V) to 1.240 V (Tj = + 25°C).

Note : Set the VMT pin to monitor the BGR voltage (see the

“ 9) Monitor Circuit Selection”).

VBGR Voltage Bit Setting Table

R2

*

R1

0

R0

0

Correction Amount

No correction (Standard)

[Not available] About − 30 mV

Approximately − 15mV

0

*

0

1

0

1

No correction (Standard)

Approximately + 15 mV

Approximately + 30 mV

1

0

1

0

20

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MB42M001

3) CV Amplifier Adjustment

CVA (CV-amp: Adjusts the CV amplifier capacitance and voltage conversion gain)

(1) Use the CVA register to adjust the CV amplifier CV

(capacitance - voltage) conversion value.

Address:

A channel adjustment

19H

1AH

1BH

B channel adjustment

C channel adjustment

Note : The adjustment step amount might not be equal.

Approximate CV conversion value

= 16 / ( N+16 ) × Vsrv [V/pF] (N = 16 to 255 )

Bit setting:

7

6

5

4

3

2

1

0

• Vsrv is the value specified by the SRV register (the default

value is about 2.65 V).

B7 B6 B5 B4 B3 B2 B1 B0

• The change in CV amplifier output voltage ∆V for a change

in capacitance of ∆C[pF] can be estimated as ∆V = 16 /

(N+16) × Vsrv × ∆C.

N ← (B7, B6, B5, B4, B3, B2, B1, B0)

N is the value in decimal.

• For example, if Vsrv = 2.6 V and CVA = 48, the

approximate value is ∆V [V] = 0.65 [V/pF] × ∆C [pF].

(N:0 to 15 is prohibited)

(2) Ensure that the adjustment does not exceed the

permitted input range of the CV amplifier.

The conversion value setting is restricted by the maximum

total value of all the capacitances connected to CV amplifier

input. Under all conditions, ensure that 0.5 V< CV amplifier

output voltage< 0.8 V.

Since the CV amplifier output voltage cannot be measured

directly, set the Amplifier 1 gain to 1 and set the Amplifier 2

gain to 2, then calculate from the FLTxx pin voltage. The FLT

pin voltage can be monitored from the VMT pin.

Note : The maximum capacitance value = IC internal

capacitance + IC package capacitance + Sensor

connector (wiring) capacitance + Sensor initial

capacitance + Sensor maximum change capacitance

(3) CVA expansion mode

The adjustment amount can be increased by using the A8 bit

in the VGA register.

B8 = A8 bit in the VGA register

N ← (B8, B7, B6, B5, B4, B3, B2, B1, B0)

Conversion value = (16 /(N + 16)) × Vsrv [V/pF] (N = 16 to

511)

(Continued)

DS04–29135–1E

21

MB42M001

(Continued)

COF (CV-amp input offset : CV amplifier input offset capacitance adjustment)

(1) Use the COF register to adjust the CV amplifier input

offset

Address

A channel adjustment

1CH

1DH

1EH

B channel adjustment

C channel adjustment

Note : The adjustment step amount might not be equal.

• For no correction

: S = 0, N = 0

• For correction to + side : S = 0, N = 1 to 127

Correction amount =

Bit setting

About +N × 0.0625 pF

7

6

5

4

3

2

1

0

• For correction to - side : S = 1, N = 1 to 127

Correction amount =

S

B6 B5 B4 B3 B2 B1 B0

About-N × 0.0625 pF

• N (Decimal) ← (B6, B5, B4, B3, B2, B1,

B0)

• S (Sign bit) ← S

(2) CV amplifier output voltage is adjusted in the range

of 500 mV to 599 mV

Since the CV amplifier output voltage cannot be measured

directly, set the Amplifier 1 gain to 1 and set the Amplifier 2

gain to 2, then calculate from the FLT2x pin voltage.

(3) COF expansion mode

The adjustment amount can be increased by using (F9, F8,

F7) in the VGA register.

• The A channel can expand three bits: B9, B8, and B7.

N (Decimal) ← (B9, B8, B7, B6, B5, B4, B3, B2, B1, B0)

• The B channel and C channel can expand one bit: B7.

N (Decimal) ← (B7, B6, B5, B4, B3, B2, B1, B0)

22

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4) CV Amplifier Mode Settings

CVM (CV-amp mode: CV amplifier mode settings)

Address: 18H

Various CV amplifier modes can be specified. Normally, all of B7 to B0 are set to“0”.

(1) CV amplifier operating mode

For selection modes details, see the section describing CV amplifier operation selection.

7

6

5

4

3

2

1

0

B7 B6 B5 B4 B3 B2 B1 B0

CV amplifier operating mode selection

Normal use status.

0

Switches to 1 channel mode.

*

B4

*

For B4 = 0 sets normal mode (3ch operation). If B4 = 1, Ach only is

operated (Bch and Cch are not operated.).

Sets the CV amplifier to normal operating mode “C mode”.

A pair capacitance is connected to SIN1 and SIN2 and the common

pin of the pair is connected to SIN_COM.

*

0

1

For the conversion gain setting, see the “3) CV amplifier adjustment”.

<Test> Set the CV amplifier to “S mode”.

[Valid only when 1 channel mode is used] Capacitances are

connected to SIN1 and SIN_COM and SIN2 and SIN_COM

respectively. (SIN2 side can be opened.)

When this mode is specified, the capacitance connected to the SIN1

pin and IC internal capacitance of about 24 pF seem to be in series.

This increases the permitted capacitance value for the SIN1 pin.

Note: The linearity becomes worse. The COF adjustment can only be

adjusted in the negative direction (SIN2 side).

<Test> Sets the CV amplifier to “T mode”.

This detects the change in the capacitance connected between SIN1

and GND.

The SIN2 pin is left open circuit and the VSRV register is set to 0.6 V.

The gain setting is adjusted using the CVA register (N<512).

(Conversion gain = 9.6/(N+16) [V/pF] )

Note: The accuracy deteriorates because the detected capacitance

includes all parasitic capacitances inside and outside the IC.

*

1

0

1

<Test> The CV amplifier is set to “V mode” (Voltage input mode, input

range = 0 V to VFA+0.3 V).

Apply the difference voltage between SIN1 and SIN2, and leave

SIN_COM open circuit.

The gain setting is adjusted using the CVA register (N<512) (Voltage

gain = 512/(N+16) [V/V] ).

*

B2

*

<Test> Setting B2 = 1 turns off the CV amplifier output.

<Test> When B3 = 1, the connection between SIN pin and IC internal

circuit is cut.

B3

(Continued)

DS04–29135–1E

23

MB42M001

(Continued)

CVM (CV-amp mode: CV amplifier mode settings)

(2) Performs a test by varying the CV amplifier drive frequency.

Normally, use B7 = 0, B6 = 0, and B5 = 0.

7

6

5

4

3

2

1

0

B7 B6 B5 B4 B3 B2 B1 B0

Drive Frequency

Drive Frequency: Typ. fDRV = 24 kHz, sampling: fDRV/3 (3ch mode),

fDRV (1ch mode)

0

*

0

1

0

1

0

1

0

1

0

1

0

1

*

<Optional> Drive frequency: fDRV × 0.67

<Optional> Drive frequency: fDRV × 0.33

<Test> Drive frequency: fDRV × 1.3

<Test> Drive frequency: fDRV × 2

<Test> The drive oscillation output is stopped (Ach setting).

<Test> The drive oscillation output is stopped (Bch setting).

<Test> The drive oscillation output is stopped (Cch setting).

24

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MB42M001

5) CV Amplifier Drive Condition Setting

SRV (Sensor drive voltage: CV amplifier drive voltage setting for capacitance detection)

Address: 15H

Selects the setting for the VSRV drive voltage of the CV amplifier.

The CV conversion gain is proportional to the VSRV value. For the VSRV value, either the existing pin

voltage can be used or the mode in which the FLT1C pin function is changed to the VSRV pin function

can be selected.

(1) VSRV voltage selection without using SRV

Selects the drive voltage for the CV amplifier. Either the VFA pin voltage or VREF pin voltage can be

selected for the drive voltage.

Set B3 = 0 and B2 = 0 and use B0 to specify the selection.

7

6

5

4

3

2

1

0

B

7

B

6

B

5

B

4

B

3

B

2

B

1

B

0

FLT1C/ VSRV Pin, VSRV Voltage Value

*

0

*

0 The FLT1C pin functions as FLT1C. Internal VSRV ≈ VFA

1 The FLT1C pin functions as FLT1C. Internal VSRV ≈ VREF (0.6 V)

(2) [Optional] VSRV voltage value selection when SRV is used (No VDD ratiometric)

When the use of SRV is specified, the FLT1C pin function is switched to the VSRV pin function

automatically.

Connect a capacitor of 1µF to the VSRV pin. (Note: The C channel filter is FLT2C only.)

Set B3 = 1 and B2 = 0 and use B1 and B0 to specify the selection.

7

6

5

4

3

2

1

0

B7 B6 B5 B4 B3 B2 B1 B0

FLT1C/ VSRV Pin, VSRV Voltage Value

*

1

0

1

0

1

0

1

<Optional> The FLT1C pin functions as VSRV (1 µF connection). VSRV ≈ 0.6V

<Optional> The FLT1C pin functions as VSRV (1 µF connection). VSRV ≈ 2.04 V

<Optional> The FLT1C pin functions as VSRV (1 µF connection). VSRV ≈ 0.1 V

<Optional> The FLT1C pin functions as VSRV (1 µF connection). VSRV ≈ 0.05 V

(3) [Test] VSRV voltage value selection when SRV is used (with VDD ratiometric)

When the use of SRV is specified, the FLT1C pin function is switched to the VSRV pin function

automatically.

Connect a capacitor of 1 µF to the VSRV pin. (Note: The C channel filter is FLT2C only.)

Set B3 = 1 and B2 = 1 and use B1 and B0 to specify the selection.

7

6

5

4

3

2

1

0

B7 B6 B5 B4 B3 B2 B1 B0

FLT1C/ VSRV Pin, VSRV Voltage Value

<Test> The FLT1C pin functions as VSRV (1 µF connection). VSRV ≈ VDD × 0.06 V

<Test> The FLT1C pin functions as VSRV (1 µF connection). VSRV ≈ VDD × 0.213 V

<Test> The FLT1C pin functions as VSRV (1 µF connection). VSRV ≈ VDD × 0.378 V

<Test> The FLT1C pin functions as VSRV (1 µF connection). VSRV ≈ VDD × 0.0095 V

*

1

0

1

0

1

0

1

Note : When the SRV function is used, the current dissipation might increase by 20 µA (VDD = 3 V) depending

on the settings.

DS04–29135–1E

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MB42M001

6) Amplifier Gain and Offset Adjustment

VGA1 (Voltage gain control amp1: Gain adjustment for Amplifier 1 and expansion bit for CVA/COF/CVM)

(1)The Amplifier 1 gain is adjusted using the VGA register.

Address

A channel adjustment

21H

22H

23H

B2 B1 B0 N (Decimal) ← (B2, B1, B0)

B channel adjustment

C channel adjustment

(Decimal) ← (B2, B1, B0)

• The gain can be set independently for channels A, B, and C.

N

0

1

2

3

4

5

6

7

Bit setting for A channel

× 0 × 1 1.62 × 2 3.2 × 4 6.2 × 8

7

6

5

4

3

2

1

0

Gain

R

F9 F8 F7 A8 B2 B1 B0

Note : N = 0 is for testing and therefore the Amplifier 1 signal

is not transmitted.

Bit setting for B channel and C channel

(2) Expansion bit in the CVA register

7

6

5

4

3

2

1

0

Corresponds to expansion bit B8 in the CVA

A8

register.

M

F7 A8 B2 B1 B0

→ See the “3) CV amplifier adjustment”.

(3) Expansion bit in the COF register

Corresponds to the expansion bit

F7

in the COF register for the B and

C channels.

• Bit B7 in the COF register only is used for the B channel and

C channel.

→ See the “3) CV amplifier adjustment”.

Corresponds to the expansion bit

F9

F8

F7

in the COF register for the A

channel.

• Corresponds to B9, B8, and B7 in the COF register for A

channel.

→ See the “3) CV amplifier adjustment”.

(4) <Test> CVM register expansion bit

For an operating mode test (not used normally)

M

Sets B and C channels to V mode.

• Normally, M = 0

• When the B channel register is M = 1, the CV amplifier

switches to V mode for B channel only.

• When the C channel register is M = 1, the CV amplifier

switches to V mode for C channel only.

(5)<Test> Average mode (for disturbance noise measures)

For an operating mode test (not used normally)

The FLT pin voltage is averaged (used in 1ch

mode).

R

• Normally, R = 0

• The detection voltage is averaged. The output noise and

output voltage are decreased. (The VOUT output voltage is

increased about 0.3 to 0.5 times normal in 1ch mode.)

(Continued)

26

DS04–29135–1E

MB42M001

(Continued)

VOF1 (Voltage offset control 1: Amplifier 1 input offset adjustment)

Adjusts the offset from the CV amplifier output to

Amplifier 1 input.

Address

A channel adjustment

24H

25H

26H

B channel adjustment

C channel adjustment

• For no correction

: N = 0

• Positive correction only available:

N = 1 to 255

Bit setting

• N (Decimal) ← (B6, B5, B4, B3, B2, B1, B0)

Correction amount = About +N ×

(Amplifier 1 gain) × 2 × 0.64 mV

7

6

5

4

3

2

1

0

Notes : • The correction amount is the value measured from

the FLT2x pin. (FLT2x = FLT2A, FLT2B, FLT2C) For

example, the FLT2x pin voltage is adjusted to be

between 590 mV to 610 mV.

B7 B6 B5 B4 B3 B2 B1 B0

• The AMT register can be set so that the FLT2x pin

can be monitored from the VMT pin.

• The VOF1 adjustment does not allow negative

corrections. Accordingly, first use the COF register

adjustment to set in the range 500 mV to 599 mV.

• The adjustment step amount might not be equal.

VOF2 (Voltage offset control 1: Amplifier 3 input offset adjustment)

Adjusts the offset from Amplifier 2 output to Amplifier 3

input.

Address

A channel adjustment

2C^H

2DH

2EH

• For no correction

• For correction to + side : S = 0, N = 1 to 63

Correction amount =

: S = 0, N = 0

B channel adjustment

C channel adjustment

About +N × 5.53 mV

• For correction to - side : S = 1, N = 0 to 63

Correction amount =

Bit setting

7

6

5

4

3

2

1

0

About-N × 5.53 mV

F

S

B5 B4 B3 B2 B1 B0

Notes : • The correction amount is the value measured from

the VOUTx pin.

• N (Decimal) ← (B5, B4, B3, B2, B1, B0)

• S (Sign bit) ← S

• F ← Normally set to “0”. If the MOD function

is used, B7 in the B/C channel register is

used as the sign bit for the MOD

function.For details, see the MOD register

explanation.

For example, the VOUTx pin voltage is adjusted to

VDD × 0.5.

• The adjustment step amount might not be equal.

DS04–29135–1E

27

MB42M001

7) Temperature Dependence Gain Adjustment (Optional function)

TGA (Temperature gain control amp: Temperature dependence gain adjustment)

TGA is not used normally. If it is used, set A <Optional> Adjusts the gain temperature characteristic.

(bit7) to A = 1.

A first order linear temperature gradient is used as the gain

Address

temperature dependence for all channels.

All channels

16^H

• When TGA is not used : A = 0, S = *, N = *

• For a positive correction slope :

Bit setting

A = 1, S = 0, N = 1 to 31

7

6

5

4

3

2

1

0

Correction amount =

About +N × 1E-4 [time/°C]

• For a negative correction slope :

A

S

B4 B3 B2 B1 B0

• N (Decimal) ← (B4, B3, B2, B1, B0)

• S (Sign bit) ← S

• A (Available bit) ← A

A = 1, S = 1, N = 1 to 31

Correction amount =

About -N × 1E-4 [time/°C]

Note : • Positive slope: Gain increases at higher

temperatures. The correction amount is the change

in the gain, where the gain at + 25°C is 1.

Example) For S = 0,N = 31

Gain

When the

temperature

increases by

∆50°C, the gain

changes by

+15%.

Av×1.15

Av×1.0

Tempe-

+75C° rature

+25C°

• When the TGA function is used, the current

dissipation might increase by 20 µA (VDD = 3 V)

depending on the settings.

• The adjustment step amount might not be equal.

28

DS04–29135–1E

MB42M001

8) Temperature Dependence Offset Adjustment

TOF (Temperature offset control: Temperature dependence offset adjustment)

Address

A channel adjustment

Adjusts the offset voltage temperature dependence

characteristic.

A first order linear temperature gradient is used for the output

offset.

An 8-bit + sign bit value can be specified for the A channel

and a 5-bit + sign bit value for the B and C channels.

29^H

2AH

2BH

B channel adjustment

C channel adjustment

• Bit setting for A channel

29^H

• When TOF is not used : A = 0, S = *, N = *

Disables the TOF setting for all

channels.

7

6

5

4

3

2

1

0

B7 B6 B5 B4 B3 B2 B1 B0

• N (Decimal) ← (B7, B6, B5, B4, B3, B2, B1,

B0)

• S (Sign bit) ← SA

<<SA: Bit 7 at address 2AH>>

• For correction to + side : S = 0

• A channel : N = 1 to 255,

Correction amount = About +N × 36 µV/°C

• B/C channel: N = 1 to 31,

Correction amount = About +N × 290 µV/°C

• Bit setting for B channel

2AH

• For correction to - side: S = 1

7

6

5

4

3

2

1

0

• A channel : N = 1 to 255,

Correction amount = About -N × 36 µV/°C

• B/C channel: N = 1 to 31,

SA

A

S

B4 B3 B2 B1 B0

• N (Decimal) ← (B4, B3, B2, B1, B0)

• S (Sign bit) ← S

Correction amount = About -N × 290 µV/°C

Notes: • Positive slope: The offset increases at higher

temperatures.The correction amount is the change

in offset, where the offset at 25°C is 0.

SA

A

A channel sign bit

TOF available bit

• The correction amount is the value measured from

the VOUTx pin.

• Bit setting for C channel

2BH

Example) For Ach, S = 0, and N = 88

7

6

5

4

3

2

1

0

Offset

When the

S

B4 B3 B2 B1 B0

temperature

increases by

∆50°C, the

Vofs+158mV

Vofs+0mV

• N (Decimal) ← (B4, B3, B2, B1, B0)

• S (Sign bit) ← S

offset changes

by +158 mV.

Tempe-

rature

+75C°

+25C°

• When the TOF function is used, the current

dissipation might increase by 20 µA (VDD = 3 V)

depending on the settings.

• The adjustment step amount might not be equal.

DS04–29135–1E

29

MB42M001

9) Monitor Circuit Selection

AMT (Analog Monitor Test: Controls the monitor circuit for testing)

Address: 10H

(1) Selects the signal to monitor from the VMT pin (uses the B2, B1, and B0 bits).

The VMT (voltage monitor) pin can be set to monitor different signals to allow measurement of the voltages

being adjusted.

Since the output is from the internal output buffer, any monitor voltage can be used.

7

6

5

4

3

2

1

0

B7 B6 B5 B4 B3 B2 B1 B0

Selects the signal to monitor from the VMT pin.

No VMT buffer output.

*

0

1

<Test> Monitors the CV amplifier output voltage.The

waveform cannot be observed.

0

Monitors the temperature reference voltage from the VMT pin.

(Slope of about +2 mV/°C) Monitoring the temperature

reference voltage allows the system to be used as a

temperature sensor.Check the offset deviation in the VMT

output and then adjust the TREF (B4 to B0) register.

*

0

1

0

1

Monitors the BGR voltage (1.223 V) from the VMT pin. Check

the offset deviation in the VMT output and then adjust the

TREF (B7 to B5) register.

*

0

1

0

1

Monitors the reference voltage VREF pin voltage (600 mV)

from the VMT pin.Check the offset deviation in the VMT

output and then adjust the VREF (B4 to B0) register.

*

1

0

1

0

1

<Test> Monitors the FLT2A pin voltage from the VMT pin.

<Test> Monitors the FLT2B pin voltage from the VMT pin.

<Test> Monitors the FLT2C pin voltage from the VMT pin.

<Test> The temperature sensor output is connected to FLT2A

and output to VMT.

*

1

0

1

0

1

<Test> The BGR voltage is connected to FLT2B and output

to VMT.

<Test> The VREF voltage is connected to FLT2C and output

to VMT.

(2) <Test> Selects the operation of the VMT pin output buffer amplifier (Uses bit B7, B6, B5, and B4)

7

6

5

4

3

2

1

0

B7 B6 B5 B4 B3 B2 B1 B0

Buffer amplifier mode selection for the VMT pin

Normal use status

0

*

<Test> Performs a comparison with VREF (0.6 V) and

outputs the comparator output from VMT (High = VFA

voltage).

0

*

1

*

<Test> Performs a comparison with VREF (0.6 V) and

outputs the comparator output from VMT while also outputing

a logic value from the ALARM pin (High = VDD).

1

*

1

*

<Test> Used to test the VMT output offset (changes to a

differential input transistor for the buffer).

0

*

1

*

1

<Test> Increases the VMT output drive capability.

(Continued)

30

DS04–29135–1E

MB42M001

(Continued)

AMT (Analog Monitor Test: Controls the monitor circuit for testing)

(3) <Test> ALARM pin monitor signal test (uses bits B7, B6, and B5)

7

6

5

4

3

2

1

0

B7 B6 B5 B4 B3 B2 B1 B0

Alarm monitor test for ALARM pin

Normal use status. CRC errors and the verification result are

output to the ALARM pin.

0

1

0

1

0

1

0

*

<Test> Outputs only CRC errors to the ALARM pin.

<Test> Outputs only the verification result to the ALARM pin

during register transfer from the memory.

<Test> Uses a pulse output to the ALARM pin for the

verification result during register transfer from the memory.

1

*

Note: Setting bits not specified in the table is prohibited.

“*” indicates either “0” or “1”.

10) Control settings

CTL (Control register: Various control settings)

Address: 11H

(1) Various functions can be selected (Uses bits B3, B2, B1 and B0 bits).

7

6

5

4

3

2

1

0

B7 B6 B5 B4 B3 B2 B1 B0

0

*

0

Normal use state

<Test> Selects the gain for amplifier 2.

*

B0 [B0 = 0 is normally used.]

B0 = 0: Gain × 2, B0 = 1: Gain × 4

Reference voltage of amplifier 3 = 0.5 × VDD, VOUT output

range 0<VOUT<VDD

*

0

1

*

Note : Condition: 2.9 V ≤ VDD Although the same operation

as below is performed, there is a possibility that noise

is improved.

This setting should be used normally.

Reference voltage of amplifier 3 = 0.5 × VDD, VOUT output

range 0<VOUT<VDD

*

Reference voltage of amplifier 3 = Approx. 1.5 V, VOUT output

*

1

*

0

1

*

range 0 V to 4 V (<VDD)

Reference voltage of amplifier 3 = Approx. 2.5 V, VOUT output

range 0 V to 5V (<VDD)

<Test> Stops the internal oscillator and can be used the clock

from the CLK pin.

B3

<Test> Alarm test for the verify check

Write B7 = 1 to the data at the CTL (Address 71^H) memory

area.

The alarm will be set at the next power-on or after a power-on

reset.

B7

*

To cancel the alarm, write B7 = 0 to the memory again.

DS04–29135–1E

31

MB42M001

11) Used to adjust the linearity of the output voltage (Optional function for channel A only)

LTC (Linearity: Channel A output linearity adjustment)

LTC is normally not used.

<Option> Adjusts the linearity of the output voltage of channel A.

Address

A first order linear temperature gradient is used as the gain

temperature dependence for all channels.

• When LTC is not used: Set A1 = 0 and A2 = 0. [Normal state]

• Use the A2, A1 and A0 settings to select the correction curve.

• The adjustment amount can be adjusted in 15 steps using the B3,

B2, B1 and B0 bits.

Channel A

28H

1

Bit setting

7

6

5

4

3

2

0

M

A2 A1 A0 B3 B2 B1 B0

Inclination

characteristics

Inclination

characteristics

A2 A1 A0

• N (Decimal) ← (B3, B2, B1, B0)

• Correction characteristics

selection ← A2, A1 and A0

• M (MOD function ON/OFF bit) ← M

0

1

0

LTC OFF

0

1

LTC OFF

Note : See the “12) Channel A output

voltage monitor test (Optional

function for channel A only)”.

RD

RU

Input

Default setting

7

6

5

4

0

3

0

2

0

1

0

LD

1

0

1

0

1

0

1

LU

LTC and MOD function are not used.

CU

CD

When using the LTC function, current dissipation may increase by

20 µA (VDD = 3 V) or so, depending on the settings.

Adjustment step amount may not be uniform.

The zero point may shift depending on the register settings.

In this case, adjust the offset again.

• Setting the adjustment amount

Measure the deviation from an ideal straight line at an arbitrary

point and use the B3, B2, B1 and B0 bits to adjust the correction

amount.

For example, when the zero point of the output pin (VOUTx) is 0.5

× VDD and the full scale point is defined in terms of the potential

difference from the zero point, the full-scale voltage is

0.5 × VDD.Also, in terms of the FLT2A pin voltage, it is approx.

0.6V (0.5 × VDD /7).

α

Input

α

Input

32

DS04–29135–1E

MB42M001

12) Channel A output voltage monitor test (Optional function for channel A only)

MOD (Modulation: Channel A output monitor)

The MOD function is not normally used.

<Option> Monitor the output voltage of channel A multiplied

by k.

• ON/OFF setting of the MOD function

Address

The MOD function can multiply the output voltage of channel

A by k and output it from channel B or C.

Channels B and C

28^H

• ON/OFF setting of the MOD function

• When the MOD function is not used: M = 0 (Set bit 7 of

the LTC register to “0”)

Bit setting

Only bit7 of the LTC register is used

7

6

5

4

3

2

1

0

• When the MOD function is used: M = 1 (Set bit 7 of the

LTC register to “1”)

M

• M ← Sets the MOD function ON or OFF.

• When the output is adjusted to “+” inclination M = 1, F = 0,

Nx = 1 to 15

• Adjustment amount setting

Address

VOUT_B = VOUT_B + (VOUT_A × NB × Approx. 1%)

VOUT_C = VOUT_C + (VOUT_A × N^C× Approx. 1%)

Channels B and C

20^H

• When the output is adjusted to “-” inclination M = 1, F = 1,

Nx = 1 to 15

Bit setting

VOUT_B = VOUT_B - (VOUT_A × N^B× Approx. 1%)

VOUT_C = VOUT_C - (VOUT_A × NC × Approx. 1%)

7

6

5

4

3

2

1

0

C3 C2 C1 C0 B3 B2 B1 B0

• NB (Decimal) ← (B3, B2, B1 and B0)

• NC (Decimal) ← (C3,C2,C1 and C0)

Notes: • The bit setting should be M = 0 (bit 7 of the LTC

register) as the MOD function is normally not used.

• When using the MOD function, current

• Inclination selection

Address

dissipation may increase by 20 µA (VDD = 3 V) or

so, depending on the settings.

• Note that this covers multiple addresses.

• The adjustment step amount may not be uniform.

Channels B and C 2D^H, 2EH

Bit setting

Only bit 7 of the VOF2B and VOF2C

registers are used

7

F

6

5

4

3

2

1

0

• F ← Selects the inclination.

Note : Bits other than B7 are for the VOF2

register.

DS04–29135–1E

33

MB42M001

■ DESCRIPTION OF THE SERIAL INTERFACE

This document defines read and write operations as described below.

• Write : Data is transmitted by an external device and received by this IC.

• Read : Data is transmitted by this IC and received by an external device.

1. Serial interface connection

External devices can access the registers and flash memory inside the IC via the serial interface.

Control the CLK (clock), DIN (data input), DOUT (data out) and CS (chip select) pins and use serial

handshaking to transmit data one byte (8 bits) at a time.

Inside the IC

CMOS input

CLK

DIN

CMOS input

Tri-state

DOUT

CS

CMOS input

3-pin control can be achieved by connecting from the DOUT pin to the DIN pin with a resistor of

approximately 5 kΩ inserted between them.

Note: The SD pin should be set to “L” when using the serial interface.

When in the shutdown state, the DIN, CLK and CS pins should be open or set to the “L” level.

2. Serial interface “Data valid timing”

When writing, latch DIN on the rising edge of CLK.

When reading, read DOUT on the rising edge of CLK.

CLK

DIN

CLK

DOUT

Data

held changed

readable undefined

Write operation

Read operation

34

DS04–29135–1E

MB42M001

3. Serial interface “Starting/terminating communication mode”

• Starting communication

To communicate with the IC, set the CS signal to “H” and then wait for the DOUT output to become “L”.

Communication will start in synchronization with CLK when CLK is input (rising edge) after the DOUT output

goes to “L”.

Disable

communication

Enable

communication

Communication

mode

Ignore data

CLK

DIN

DOUT

L

H

Z

CS

If communication is enabled

If communication is disabled

• When DOUT signal is “H”

DOUT goes to “H” if the sequence circuit inside the IC is operating.

1) If a sequence triggered by a power-on reset is in operation

It takes around 14 ms from the power-on reset to the end of the sequence operation inside the IC.

2) If data was written to flash memory

It takes around 53 ms for the writing of 8 bytes to flash memory to end.

• Terminating communication

To terminate the communication, change the CS signal from “H” to “L”.

On detecting the CS signal changing from H → L, the IC executes the sequence operation specified by the

communication, such as writing to flash memory.

DS04–29135–1E

35

MB42M001

4. Serial interface “Communication format”

• Communication format

The period during which CS is High will be counted as one frame.

Communication during a frame consists of one address byte and one command byte followed by either

eight bytes or one byte of data.

address

command

data0 to data7

CLK

DIN

to

DOUT

CS

to

• Communication bit string

The basic unit for the address, command and data is one byte. Bytes are transmitted/received starting from

the most significant bit.

The most significant bit in the bit string (MSB) is B7 and the least significant bit (LSB) is B0.

MSB

LSB

B7

B6

B5

B4

B3

B2

B1

B0

Example) When transferring 8 bytes

address

command

data 0

data 1

data 2 to 6

data 7

G H

E F

I

J K L M N O P

S T U V W X Y Z

A B

C D

bit No.

7 6 5 4 3 2 1 0

BFH

C0H

C1H

C2H

to

C7^H

C8H

A B C D E F G H

address

I

J K L M N O P

S T U V W X Y Z

• Address:

Set a 1-byte address value that points to an area that can be accessed by the user.

1) Register - User area : 10^Hto 2FH

2) Register - For test mode (TMR register) : 54H

3) Flash memory - User area : 70H to B7H

• Command

The command value specifies whether the operation is a read or write.

1) To write to a register or flash memory : 80^H

2) To read from a register or flash memory : 00H

Note: For normal use, commands other than 80H or 00H must not be set.

Setting commands other than 80^Hor 00H can result in malfunction or damage to other memory areas.

36

DS04–29135–1E

MB42M001

• Data (data)

Data is transmitted/received in fixed data length per address (8 bytes or 1 byte).

The 8th byte is the CRC code.

Note: A CRC check is only performed for addresses between 60^Hto A7H and D0H to FFH.

Address values and data lengths that can be specified by the user

Specifiable address values

Data length

Register User area

10H

54^H

70^H

90H

18H

⎯

20H

⎯

28H

⎯

8

1

8

Register For test mode

Flash memory user area 1

Flash memory user area 2

78H

98H

80H

A0H

88H

A8H

⎯

B0H

• CRC coding formula

CRC code must be appended every 8 bytes when writing to flash memory.

Each frame has a total of 8 bytes, consisting of 7 bytes of data and 1 byte of CRC code.

• CRC coding formula - Calculated based on the previous 7 bytes of data.

Generating polynomial X⁸+X²+X+1 (1 0000 0111)

• Alarm function

1) Alarm detection output

The alarm function outputs “CRC error” and “verify error” to the ALARM pin.

The voltage level of the ALARM pin is normally Low but goes High in the event of an error.

2) Alarm detection timing

The alarm function only operates when data is automatically transferred from the memory area to the

register area at power-on or power-on reset.

Alarm detection will not function even when a CRC or verify error is generated while the memory or

register is being accessed from the external serial interface.

Once the alarm output becomes High, it cannot revert to Low level unless the power is turned off and on

again or a power-on reset is performed.

3) CRC

• The CRC code is only checked for addresses marked with “CRC” in the flash memory area on the

memory map (60^Hto A7H and D0H to FFH).

• The serial interface cannot write to a CRC-capable address in flash memory if the CRC values do not

match.In this case, the write sequence will terminate immediately and the DOUT output will revert to

“L” within 1ms of CS recovery.

Read operations are possible regardless of the CRC values.

• A CRC check is performed when data is automatically transferred from the memory area (CRC-capable

address) to the register area at power-on or power-on reset; and an alarm is output if the calculated

CRC values do not match.

4) Verify

A verify check is performed by comparing the data in memory (transfer source) with the data in the

register (transfer destination) when data is automatically transferred from the memory area to the register

area at power-on or power-on reset; and an alarm is output if these data do not match.

5) If the alarm does not disappear

The alarm will disappear when data “00” is written to all CRC-capable addresses in the flash memory

area (60^Hto A7H, D0H to FFH).

DS04–29135–1E

37

MB42M001

• Communication example

38

DS04–29135–1E

MB42M001

■ HOW TO CREATE SETTING DATA

1. Example procedure for creating setting data

Use a PC or microcontroller to save data from flash memory to an

external device via the serial interface.

1:Save the data in flash

memory to an external

device

Use the serial interface to set the TMR register to switch to register

access mode (transmit “54^H80H A0H” from the serial interface).

2:Enter the mode in

which each register

can be accessed.

• Set the data in each register from the serial interface.Adjust to

the optimal data by measuring the analog voltage value.

• Use a PC or microcontroller to save the data in the register area

(10^Hto 2FH) to an external device.

3:Adjust the data in each

register

• Set the same data as the data in the register area (10^Hto 2FH) to

the user area of the flash memory area (70H to 8FH) from the

serial interface. (It is also possible to only write those addresses

that have been changed)

4:Write data to flash

memory

Note: The VDD_M voltage must be set to 5 V when writing.

• When the IC restarts after completing this procedure, it will

operate with the new setting.

5:Restart

Note: Data is transferred automatically from flash memory (70^Hto

8FH) to the register area (10H to 2FH) by power-on or power-

on reset.

DS04–29135–1E

39

MB42M001

2. Conditions for accessing setting data

Access condition table: Conditions for accessing the user registers and flash memory

Command

VDD VDD_M Permitted Address Values

Value

Data

Length

Remarks

2.7 V

to

5.5 V

Write

Read

Write

Read

Write

VDD

10H 18H 20H 28H

Read disabled

⎯

80H

8

Register User

area

2.7 V

to

5.5 V

00H or

54H

⎯

1

A0^Honly

for data

TMR register

Read disabled

2.7 V

to

5.5 V

2.7 V

to

5.5 V

2.7 V

to

5.5 V

2.7 V

to

5 V

VDD

5 V

70H 78H 80H 88H

70^H78H 80H 88H

⎯

80H

00H

80H

00H

8

Flash memory

user area 1

Read

Write

Read

90H 98H A0H A8H B0H

Flash memory

user area 2

VDD

5.5 V

(1) Power supply voltages (VDD, VDD_M)

The VDD_M voltage must be set to 5 V when writing to a flash memory area.

The data in flash memory may become corrupted if it is written with a VDD_M voltage of other than 5 V.

Other than when writing to a flash memory area, the power supply voltage is VDD = VDD_M = 2.7 V to 5.5 V.

Note:Flashmemoryshouldpreferablybewrittentoatthepowersupplyvoltageof5.0Vandatroomtemperature.

(2) Address value

Only those address values shown in the access condition table can be specified.

Specifying address values other than those shown in the access condition table can result in malfunction

or damage to other memory areas.

(3) Data length (No. of bytes of data)

Use the data length specified in the access condition table.

Using a data length other than that shown in the access condition table can result in malfunction or damage

to other memory areas.

(4) Command value

Specify a command value permitted by the combination of the address and read/write in the access

condition table.

Specifying a command value other than those shown in the access condition table can result in malfunction

or damage to other memory areas.

(5) Precautions when writing to the flash memory

It is prohibited to set the SD pin to “H” or perform serial interface communications while data is being written

to flash memory.

Operating such as communications during data writing can result in malfunction or damage to other

memory areas.

Note : DOUT goes to “H” from when the data write is started until it is finished.

(6) CRC code

The 8th byte of transmitted or received data is the CRC code.

The serial interface cannot write to CRC-capable addresses in flash memory (60^Hto A7H, D0H to FFH) if the

CRC values do not match.In this case, the write sequence terminates immediately and the DOUT output

reverts to “L” within 1 ms of CS recovery.

40

DS04–29135–1E

MB42M001

■ POWER-ON AND SHUTDOWN FUNCTIONS

The power supply current is shut down by inputting a digital logic signal (High VDD, Low = 0 V) to the SD pin.

1. Power-on

1) When controlling the SD pin after VDD power-on

• The serial interface input pins (CS, CLK and DIN) must be open circuit or 0 V.

• The power supply voltage must be 2.7 V or higher when switching the SD pin to the normal state

(High→Low).

The IC will malfunction if the SD pin is switched to the normal state (High→Low) at a voltage lower than

2.7 V.

• The SD pin can be switched to shutdown state (High→Low) regardless of the power supply voltage

(Shutdown state when SD = High; Normal state when SD = Low).

2) When using the SD pin shorted to GND

• When the power supply turns on, ensure that the transition time from 2.2 V to 2.7 V is less than 1ms.

The IC may malfunction if it takes longer.

• If the power supply is slow to turn on, control the SD pin separately and switch from High to Low after

the power supply voltage has reached over 2.7 V.

VDD [V]

2.7 V

2.2 V

t

Ton ≤ 1 ms

2. Operation startup wait time

The following describes the process flow and wait times for the analog circuit to come into operation after a

power-on or while recovering from a shutdown.

• Power-on (VDD>2.7 V)

• Recover from shutdown

A power-on reset is invoked at power-on or when recovering

Power-on reset

from shutdown.

After a power-on reset, the adjustment data is copied

Data transfer from flash

automatically from flash memory to the registers. The transfer

memory to the registers

takes approx. 7 ms.

It takes some time for the analog circuit to become stable.This

Wait time for analog circuit

stabilization wait time will vary depending on the LPF filter

operation to stabilize

(capacitance of the FLTxx pin).

Example) If the wait time until the analog circuit becomes

stable is longer than 10ms, then an operation wait

time of 17 ms or longer is required.

DS04–29135–1E

41

MB42M001

3. Operation start wait time for the serial interface

The following describes the process flow and wait times for the analog circuit to come into operation after a

power-on or while recovering from a shutdown.

4. Operation modes specified by the SD pin and serial interface input pins

The “DIN, CLK and CS” pins should be Low or open circuit while in shutdown state (SD = High).

The table below shows the states invoked by the DIN and CS pin logic levels while in shutdown state (SD =

High).

SD DIN CLK CS

Normal state

L

*

Note: A power-on reset is invoked at power-on.

Shutdown

Normal

operation

H

L

Note: A power-on reset is invoked after recovering from shutdown.

Current dissipation can be lowered by temporarily halting the

analog circuits while maintaining the register values.

1) Starts in normal operating mode and invokes a power-on reset

when the power is turned on.

2) When switched to power-save mode, set DIN to High beforehand

and then set SD to High to avoid a power-on reset.

3) When recovering from power-save mode, maintain DIN to High

and set SD to Low to avoid a power-on reset.

Power-save

mode

H

L

Note: The serial interface cannot access registers or memory in

power-save mode.

H

L

H

Normal operation

<Test>

Pause clock

H

This termporarily stops the clock in the IC.

Note: The pause function for the IC internal clock can be used to connect multiple MB42M001s and sensor

elements.

42

DS04–29135–1E

MB42M001

■ APPLICATION CIRCUIT EXAMPLE

Connection example for a 3ch capacitive sensor (1)

CFLTx = 10 nF to 100 nF

Sensor-C

24 23 22 21 20 19 18

VOUT_A

VOUT_B

VOUT_C

VDD

SIN1C

SIN2C

AGND2

SIN1A

SIN2A

DGND

SIN1B

SIN2B

25

26

17

16

VDD

15

14

13

12

11

10

27

28

29

30

31

32

Sensor-A

Sensor-B

AGND1

VREF

VFA

Package:

BCC-32

C^VDD

CVREF

C^VFA

SD

GND

VDD

VDD_M

9

1

2

3

4

5

6

7

8

VDD or 5 V

CVREF :1 µF

C^VFA:1 µF

C^VDD:1 µF

Serial interface

Note : About VDD_M

VDD_M should normally be at the same potential as VDD.

VDD_M should be 5.0V when writing to the non-volatile memory in the IC.

DS04–29135–1E

43

MB42M001

Connection example for a 3ch capacitive sensor (2)

This example shows the operation with a minimum configuration.

1) Use with the VDD and VDD_M power supply pins connected together.This is necessary to set VDD = 5.0

V when writing to the non-volatile memory inside the IC.

2) The serial interface does not need to be connected permanently as it is only used when creating

adjustment data or when writing to non-volatile memory.

3) Although the filter capacitance is determined by factors such as the response frequency and noise

tolerance, it is also possible to use one capacitance for each channel.

4) Although sensors with a pair capacitance are desirable, capacitive sensors with other than a pair

capacitance can be supported, depending on the value of the capacitance. The following diagram shows

an example where a pair capacitance sensor is connected to Ch.A, a single capacitance sensor to Ch.B,

and a single capacitance sensor and capacitor (with fixed capacitance value) to Ch.C.

CFLT2 = 10 nF to 100 nF

Sensor-C

24 23 22 21 20 19 18

VOUT_A

VOUT_B

VOUT_C

VDD

SIN1C

SIN2C

AGND2

SIN1A

SIN2A

DGND

SIN1B

SIN2B

25

26

17

16

GND

C^VDD

15

14

13

12

11

10

27

28

29

30

31

32

Sensor-A

Sensor-B

VDD

AGND1

VREF

VFA

Package:

BCC-32

CVREF

C^VFA

SD

VDD_M

9

1

2

3

4

5

6

7

8

CVREF :1 µF

C^VFA:1 µF

C^VDD:1 µF

44

DS04–29135–1E

MB42M001

Connection example for a 3ch capacitive sensor (3)

The IC should be designed to guard the area between SIN_COM wiring pattern and sensor connection pin

with the GND pattern and the wiring SIN_COM should be lined as short as possible.

The following diagram shows an indicative wiring pattern. The actual pattern should be based on the

positions of the sensor and IC.

C

FLTx = 10 nF to 100 nF

Sensor-C

Sensor-A

Sensor-B

VOUT_A

VOUT_B

VOUT_C

VDD

24 23 22 21 20 19 18

SIN1C

SIN2C

AGND2

SIN1A

SIN2A

DGND

SIN1B

SIN2B

25

17

16

26

27

28

29

30

31

32

VDD

15

14

13

12

11

10

AGND1

Package:

BCC-32

C

VDD

VREF

VFA

SD

C

VREF

C

VFA

GND

VDD

VDD_M

9

1

2

3

4

5

6

7

8

C

VREF :1 µF

VFA :1 µF

VDD :1 µF

Serial interface

DS04–29135–1E

45

MB42M001

Connection example for a 1ch capacitive sensor

CFLT2 = 10 nF to 100 nF

20

VOUT_A

VOUT_B

VOUT_C

VDD

24 23 22 21

19 18

SIN1C

SIN2C

AGND2

SIN1A

SIN2A

DGND

SIN1B

SIN2B

25

26

17

16

VDD

15

14

13

12

11

10

27

28

29

30

31

32

Sensor-A

AGND1

Package:

BCC-32

C^VDD

VREF

VFA

SD

CVREF

CVFA

GND

VDD

5 V

VDD_M

9

1

2

3

4

5

6

7

8

CVREF :1 µF

C^VFA:1 µF

C^VDD:1 µF

Serial interface

Notes : • If using other than a pair capacitance sensor, leave one of the SINxx pins open circuit.

• Connect C^SRVto FLT1C when using the SRV function.

46

DS04–29135–1E

MB42M001

Connection example for a 1ch capacitive sensor

When using the CV amplifier in C mode, the wiring pattern of SIN_COM should preferably be guarded from

SIN1A and SIN2A by the GND pattern.

The following diagram shows an indicative wiring pattern. The actual pattern should be based on the

positions of the sensor and IC.

CFLT2 = 10 nF to 100 nF

20

VOUT_A

VOUT_B

VOUT_C

VDD

24 23 22 21

19 18

SIN1C

SIN2C

AGND2

SIN1A

SIN2A

DGND

SIN1B

SIN2B

25

26

17

16

VDD

15

14

13

12

11

10

27

28

29

30

31

32

Sensor-A

AGND1

VREF

VFA

Package:

BCC-32

C^VDD

CVREF

CVFA

SD

GND

VDD_M

9

1

2

3

4

5

6

7

8

C^VREF:1 µF

C^VFA:1 µF

C^VDD:1 µF

DS04–29135–1E

47

MB42M001

• Application example

• Use with sensor elements that output a 3ch static capacitance change

Acceleration sensor, inclination sensor, fall detection, and vibration detection

• Use with sensor elements that output a 1ch static capacitance change

Pressure sensor

• Use with other sensor elements that output a change in static capacitance

Micro-capacitance detection circuit, etc.

• Static capacitance change detection and DC differential amplifier

DC differential amplifier with wide input range

48

DS04–29135–1E

MB42M001

■ PRECAUTIONS FOR USING THIS DEVICE

• Never use settings that exceed the maximum rated conditions, otherwise the LSI may be destroyed.

Also, it is recommended that recommended operating conditions be observed in normal use. Exceeding

recommended operating conditions may adversely affect LSI reliability.

• Inserting the IC backwards or with the incorrect orientation can damage the LSI.

• Mount the IC in the socket (or board) in the correct orientation indicated by the index mark on the IC

package.

Although this device contains an anti-static element to prevent electrostatic breakdown and the circuit

design has improved electrostatic immunity, observe the following precautions when handling the device.

(1) When storing and transporting the device, keep it in a container that has anti-static protection or is made

of conductive material.

(2) Before handling the device, confirm that the work personnel, jigs and tools have been discharged

(grounded). Use a conductive sheet on the workbench.

(3) Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ inserted in series between

body and ground.

(4) Before fitting the device into or removing it from the socket, turn the power supply off.

(5) When handling (such as transporting) a board on which the device is mounted, protect the leads with a

conductive sheet.

• Recommended operating conditions are values within which normal LSI operation is warranted.

Standard electrical characteristics are warranted within the range of recommended operating conditions

and within the listed conditions for each parameter.

Operation outside these ranges may adversely affect LSI reliability.

• Printed circuit board ground lines should be set up with consideration for common impedance.

■ ORDERING INFORMATION

Part number

MB42M001PV

Package

32-pin plastic BCC

(LCC-32P-M08)

DS04–29135–1E

49

MB42M001

■ PACKAGE DIMENSIONS

Lead pitch

0.50 mm

5.00 mm ×× 5.00 mm

Plastic mold

32-pin plastic BCC

Package width ×

package length

Sealing method

Mounting height

0.80 mm MAX

(LCC-32P-M08)

32-pin plastic BCC

(LCC-32P-M08)

ꢁ.20(.165)TYP

0.50(.020)TYP

0.50 0.10

5.00 0.10(.1ꢀ7 .00ꢁ)

0.80(.031)MAX

(Mount height)

(.020 .00ꢁ)

25

17

25

ꢁ.20(.165)

TYP

3.00(.118) ꢁ.15(.163)

5.00 0.10

(.1ꢀ7 .00ꢁ)

REF

INDEX AREA

0.50(.020)

TYP

0.50 0.10

(.020 .00ꢁ)

"A"

"B"

"C"

0.075 0.025

(.003 .001)

(Stand off)

1

ꢀ

1

3.00(.118)REF

ꢁ.15(.163)REF

Details of "A" part

Details of "B" part

C0.2(.008)

Details of "C" part

0.05(.002)

0.1ꢁ(.006)

MIN

0.ꢁ0 0.06

(.016 .002)

0.ꢁ5 0.06

(.018 .002)

0.ꢁ5 0.06

(.018 .002)

0.30 0.06

0.ꢁ5 0.06

(.012 .002)

(.018 .002)

C

2001 FUJITSU LIMITED C32060S-c-3-2

Dimensions in mm (inches)

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

Note: About wafer delivery

Delivery can be arranged depending on the number of wafers purchased and the terms and condition

of purchase.

50

DS04–29135–1E

MB42M001

MEMO

DS04–29135–1E

51

MB42M001

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Japan

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incor-

porating the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or

any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other

right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property

rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages

arising in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-

current levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations

of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department


型号：	MB42M001PV
厂家：	FUJITSU
描述：	Analog Circuit, 1 Func, LCC-20
文件：	总52页 (文件大小：2780K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB42M001PV [FUJITSU]

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