MB811L323229-12WFKT [FUJITSU]
Synchronous DRAM, 1MX32, 9ns, CMOS, WAFER-88;
| 型号： | MB811L323229-12WFKT |
| 厂家： | 
FUJITSU |
| 描述： | Synchronous DRAM, 1MX32, 9ns, CMOS, WAFER-88 时钟 动态存储器 内存集成电路 |
| 文件： | 总45页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11410-2E
MEMORY
CMOS
2 × 512K × 32-BIT
SINGLE DATA RATE I/F FCRAMTM
Consumer/Embedded Application Specific Memory for SiP
MB811L323229-12/18
■ DESCRIPTION
The Fujitsu MB811L323229 is a Single Data Rate Interface Fast Cycle Random Access Memory (FCRAM*)
containing 33,554,432 memory cells accessible in a 32-bit format. The MB811L323229 features a fully synchro-
nous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence.
The MB811L323229 is utilized using Fujitsu advanced FCRAM core technology and designed for low power
consumption and low voltage operation than regular synchronous DRAM (SDRAM).
The MB811L323229 is dedicated for SiP (System in a package), and ideally suited for various embedded/
consumer applications including digital AVs and image processing where a large band width and low power
consumption memory is needed.
*: FCRAM is a trademark of Fujitsu Limited, Japan.
■ PRODUCT LINE
Parameter
MB811L323229-12
81 MHz Max
2 - 2 - 2 clk Min
12 ns Min
MB811L323229-18
54 MHz Max
2 - 2 - 2 clk Min
18 ns Min
Clock Frequency
CL - tRCD - tRP
CL = 2
CL = 2
CL = 2
Burst Mode Cycle Time
Access Time from Clock
Operating Current
9 ns Max
9 ns Max
120mA Max
1 mA Max
80mA Max
Power Down Mode Current (ICC2PS)
Self Refresh Current (ICC6)
1 mA Max
2.5 mA Max
2.5 mA Max
MB811L323229-12/18
■ FEATURES
• VCCQ: +3.3V Supply ±0.3V tolerance or +2.5V Supply ±0.2V tolerance
• VDD: +2.5 V Supply ±0.2 V tolerance
• LVCMOS compatible I/O interface
• 2 K refresh cycles every 32 ms
• Two bank operation (512 K word × 32 bit × 2 bank)
• Burst read/write operation and burst read/single write operation capability
• Programmable burst type and burst length
Burst type : Sequential Mode, Interleave Mode
Burst length : BL = 1, 2, 4, 8, full column (256)
• CAS latency = 2
• Auto-and Self-refresh
• CKE power down mode
• Byte control with DQM0 to DQM3
2
MB811L323229-12/18
■ PAD LAYOUT
PADNo.88
BME
VSS
VDD
DQ24
DQ23
VSSQ
VCCQ
DQ25
DQ22
DQ26
DQ21
DQ27
DQ20
DQ28
DQ19
DQ29
DQ18
DQ30
DQ17
VCCQ
VSSQ
DQ31
DQ16
VSSI
VSS
VDDI
VDD
DQM3
DQM2
DSE
A3
A2
A4
A1
A5
A0
A6
A10/AP
A7
VSS
VDD
A8
BA
A9
CKE
CSB
CLK
RASB
CASB
WEB
DQM1
DQM0
VSSI
VSS
VDDI
VDD
DQ8
DQ7
VCCQ
VSSQ
DQ9
DQ6
DQ10
DQ5
DQ11
DQ4
DQ12
DQ3
DQ13
DQ2
DQ14
DQ1
VSSQ
VCCQ
DQ15
DQ0
VSS
VDD
PADNo.1
3
MB811L323229-12/18
■ PAD DESCRIPTIONS
Symbol
Function
VCCQ, VDD, VDDI
DQ0 to DQ31
VSS, VSSQ, VSSI
—
Supply Voltage
Data I/O
Ground
Don’t Bond
WE(WEB)
CAS(CASB)
RAS(RASB)
CS(CSB)
BA
Write Enable
Column Address Strobe
Row Address Strobe
Chip Select
Bank Select (Bank Address)
Auto Precharge Enable
AP
Row: A0 to A10
Column: A0 to A7
A0 to A10
Address Input
CKE
CLK
Clock Enable
Clock Input
DQM0 to DQM3
DSE
Data Input /Output Mask
Disable (apply VSS except DISABLE mode)
BME
Burn in Mode Entry (apply VSS except Burn in mode)
4
MB811L323229-12/18
■ BLOCK DIAGRAM
MB811L323229 BLOCK DIAGRAM
To each block
CLK
CLOCK
BUFFER
CKE
BANK-1
BANK-0
RAS
CAS
WE
CONTROL
SIGNAL
LATCH
CS
RAS
CAS
WE
COMMAND
DECODER
FCRAM
CORE
(2,048 × 256 × 32)
DSE
BME
MODE
REGISTER
ROW
ADDR.
A0 ~ A9,
A10/AP
ADDRESS
BUFFER/
BA
REGISTER
COL.
COLUMN
ADDRESS
COUNTER
ADDR.
I/O
DQM0 ~
DQM3
I/O DATA
BUFFER/
REGISTER
DQ0 ~
DQ31
VCCQ
VDD
VDDI
VSS
VSSQ
VSSI
5
MB811L323229-12/18
■ FUNCTIONAL TRUTH TABLE
1. Command Truth Table
CKE
A9
to
A8
A7
to
A0
Com-
A10
(AP)
Function
mand
CS RAS CAS WE BA
n-1
n
Device Deselect *1
No Operation *1
DESL
NOP
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
V
V
V
V
V
V
X
X
X
X
X
L
X
X
X
X
X
X
X
V
X
X
V
X
X
X
V
V
V
V
V
X
X
V
Burst Stop *2
BST
Read *3
READ
READA
WRIT
WRITA
ACTV
PRE
H
H
L
Read with Auto-precharge *3
Write *3
L
H
L
L
Write with Auto-precharge *3
Bank Active *4
L
L
H
V
L
H
H
H
L
H
L
Precharge Single Bank
Precharge All Banks
Mode Register Set *5, *6
L
PALL
MRS
L
L
H
X
L
L
V = Valid, L = Logic Low, H = Logic High, X = either L or H,
n = state at current clock cycle, n−1 = state at 1 clock cycle before n.
*1 : NOP and DESL commands have the same effect on the part. The both commands have the device hold the
internal operation.
*2 : BST command is effective for all burst length (BL = 1, 2, 4, 8, full column (256) ) .
*3 : READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has been
activated (ACTV command). Refer to “■ STATE DIAGRAM (Simplified for Single Bank Operation State
Diagram).”
*4: ACTVcommandshouldonlybeissuedaftercorrespondingbankhasbeenprecharged(PREorPALLcommand).
*5 : Required after power up. Refer to “18. Power-Up Initialization” in “■ FUNCTIONAL DESCRIPTION.”
*6 : MRS command should only be issued after all banks have been precharged (PRE or PALL command). Refer
to “■ STATE DIAGRAM (Simplified for Single Bank Operation State Diagram) .”
Notes : • All commands assume no CSUS command on previous rising edge of clock.
• All commands are assumed to be valid state transitions.
• All inputs are latched on the rising edge of clock.
6
MB811L323229-12/18
2. DQM Truth Table
Function
CKE
DQMi *1,*2
Command
n-1
H
n
X
X
Data Input/Output Enable
Data Input/Output Disable
ENBi *1
MASKi *1
L
H
H
V = Valid, L = Logic Low, H = Logic High, X = either L or H,
n = state at current clock cycle, n−1 = state at 1 clock cycle before n.
*1 : i = 0, 1, 2, 3
*2 : DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, DQM2 for DQ16 to DQ23, DQM3 for DQ24 to DQ31
Notes : • All commands assume no CSUS command on previous rising edge of clock.
• All commands are assumed to be valid state transitions.
• All inputs are latched on the rising edge of the clock.
3. CKE Truth Table
CKE
A9
to
A0
Current
State
Com-
mand
A10
(AP)
Function
CS RAS CAS WE BA
n-1
n
Bank Active Clock Suspend Mode Entry *1
CSUS
H
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any
Clock Suspend Continue *1
Clock
Suspend
Clock Suspend Mode Exit
L
H
X
X
X
X
X
X
X
Idle
Idle
Auto-refresh Command *2
Self-refresh Entry *2, *3
REF
H
H
L
H
L
L
L
L
L
L
L
H
H
H
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SELF
H
H
L
L
H
X
H
X
H
X
H
X
H
X
H
X
Self Refresh Self-refresh Exit *4
Power Down Entry *3
SELFX
PD
L
H
L
H
H
L
Idle
L
H
L
H
H
Power Down Power Down Exit
L
H
V = Valid, L = Logic Low, H = Logic High, X = either L or H,
n = state at current clock cycle, n−1 = state at 1 clock cycle before n.
*1 : The CSUS command requires that at least one bank is active. Refer to “■ STATE DIAGRAM (Simplified for
Single Bank Operation State Diagram.”
NOP or DSEL commands should only be issued after CSUS and PRE (or PALL) commands asserted at the
same time.
*2 : REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL
command). Refer to “■ STATE DIAGRAM (Simplified for Single Bank Operation State Diagram) .”
*3 : SELF and PD commands should only be issued after the last read data have been appeared on DQ.
*4 : CKE should be held high within one tRC period after tCKSP.
Notes : • All commands assume no CSUS command on previous rising edge of clock.
• All commands are assumed to be valid state transitions.
• All inputs are latched on the rising edge of the clock.
7
MB811L323229-12/18
4. Operation Command Table (Applicable to single bank)
Current
CS RAS CAS WE
Addr
Command
Function
State
H
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
BST
NOP
NOP
NOP
H
L
BA, CA, AP READ/READA Illegal *1
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal *1
Idle
H
H
L
H
L
ACTV
Bank Active after tRCD
NOP
L
PRE/PALL
REF/SELF
L
H
Auto-refresh or Self-refresh *2, *5
Mode Register Set
(Idle after tRSC) *2, *6
L
L
L
L
MODE
MRS
H
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
BST
NOP
NOP
NOP
H
L
BA, CA, AP READ/READA Start Read; Determine AP
L
BA, CA, AP
BA, RA
WRIT/WRITA Start Write; Determine AP
Bank Active
H
H
ACTV
Illegal *1
Start Precharge;
Determine Precharge Type
L
L
H
L
BA, AP
PRE/PALL
L
L
L
L
L
L
H
L
X
REF/SELF
MRS
Illegal
Illegal
MODE
(Continued)
8
MB811L323229-12/18
Current
State
CS RAS CAS WE
Addr
Command
Function
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
BST
Continue Burst to End → Bank Active
Continue Burst to End → Bank Active
Burst Stop → Bank Active
Terminate Burst, New Read;
Determine AP
L
H
L
H
BA, CA, AP READ/READA
Terminate Burst, Start Write;
Determine AP *3
Read
L
L
L
H
L
L
L
H
H
L
H
L
BA, CA, AP
BA, RA
WRIT/WRITA
ACTV
Illegal *1
Terminate Burst, Start Precharge →
Idle; Determine Precharge Type
BA, AP
PRE/PALL
L
L
L
L
L
L
H
L
X
REF/SELF
MRS
Illegal
Illegal
MODE
Continue Burst to End →
Write Recovery
H
X
X
X
X
DESL
Continue Burst to End →
Write Recovery
L
L
L
H
H
H
H
H
L
H
L
X
X
NOP
BST
Burst Stop → Bank Active
Terminate Burst, Start Read;
Determine AP *3
H
BA, CA, AP READ/READA
Write
Terminate Burst, New Write;
Determine AP
L
L
L
H
L
L
L
H
H
L
H
L
BA, CA, AP
BA, RA
WRIT/WRITA
ACTV
Illegal *1
Terminate Burst, Start Precharge;
Determine Precharge Type
BA, AP
PRE/PALL
L
L
L
L
L
L
H
L
X
REF/SELF
MRS
Illegal
MODE
Illegal
(Continued)
9
MB811L323229-12/18
Current
State
CS RAS CAS WE
Addr
Command
Function
Continue Burst to End →
Precharge → Idle
H
L
X
H
X
H
X
H
X
DESL
Continue Burst to End →
Precharge → Idle
X
X
NOP
BST
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
Illegal
Read with
Auto-
precharge
BA, CA, AP READ/READA Illegal *1
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal *1
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal *1
Illegal *1
Illegal
L
L
H
L
L
L
MODE
Illegal
Continue Burst to End →
Precharge → Idle
H
L
X
H
X
H
X
H
X
DESL
Continue Burst to End →
Precharge → Idle
X
X
NOP
BST
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
Illegal
Write with
Auto-
precharge
BA, CA, AP READ/READA Illegal *1
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal *1
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal *1
Illegal *1
Illegal
L
L
H
L
L
L
MODE
Illegal
(Continued)
10
MB811L323229-12/18
Current
State
CS RAS CAS WE
Addr
Command
Function
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
NOP
BST
Idle after tRP
Idle after tRP
Idle after tRP
H
L
BA, CA, AP READ/READA Illegal *1
Pre-
charging
L
BA, CA, AP
WRIT/WRITA Illegal *1
H
H
L
H
L
BA, RA
ACTV
PRE/PALL
REF/SELF
MRS
Illegal *1
L
BA, AP
PALL may affect other bank *4
Illegal
L
H
L
X
L
L
MODE
Illegal
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL
Bank Active after tRCD
Bank Active after tRCD
Bank Active after tRCD
NOP
BST
H
L
BA, CA, AP READ/READA Illegal *1
Bank
Activating
L
BA, CA, AP
BA, RA
BA, AP
X
WRIT/WRITA Illegal *1
H
H
L
H
L
ACTV
PRE/PALL
REF/SELF
MRS
Illegal *1
Illegal *1
Illegal
L
L
H
L
L
L
MODE
Illegal
(Continued)
11
MB811L323229-12/18
(Continued)
Current
CS RAS CAS WE
State
Addr
Command
Function
H
L
X
H
X
H
X
X
X
X
DESL
Idle after tRC
Idle after tRC
NOP/BST
READ/READA/
WRIT/WRITA
L
L
L
H
L
L
L
H
L
X
X
X
X
X
X
Illegal
Illegal
Illegal
Refreshing
ACTV/
PRE/PALL
REF/SELF/
MRS
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
BST
Idle after tRSC
Idle after tRSC
Illegal
Mode
Register
Setting
READ/READA/
WRIT/WRITA
L
L
H
L
L
X
X
X
X
Illegal
Illegal
ACTV/PRE/
PALL/REF/
SELF/MRS
X
ABBREVIATIONS:
L = Logic Low, H = Logic High, X = either L or H
RA = Row Address BA = Bank Address
CA = Column Address AP = Auto Precharge
*1 : Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state of that
bank.
*2 : Illegal if any bank is not idle.
*3 : Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to “11. READ Interrupted by WRITE (Example @ CL = 2, BL = ≥ 4) and 12. WRITE to READ Timing
(Example @CL = 2, BL = 4) ” in “■ TIMING DIAGRAMS.”
*4 : NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP).
*5 : SELF command should only be issued after the last read data have been appeared on DQ.
*6 : MRS command should only be issued on condition that all DQ are in High-Z.
Notes : • All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle.
Illegal means don’t used command. If used, power up sequence be asserted after power shout down.
• All commands assume no CSUS command on previous rising edge of clock.
• All commands are assumed to be valid state transitions.
• All inputs are latched on the rising edge of the clock.
• All entries in “4. Operation Command Table” assume that the CKE was High during the proceeding clock
cycle and the current clock cycle.
• Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up
sequence will be asserted after power shut down.
12
MB811L323229-12/18
5. Command Truth Table for CKE
CKE
Current
State
CS RAS CAS WE
Addr
Function
n-1
n
H
X
X
H
X
X
X
X
X
X
X
X
Invalid
Exit Self-refresh
(Self-refresh Recovery → Idle after tRC)
L
L
H
H
Exit Self-refresh
(Self-refresh Recovery → Idle after tRC)
L
H
H
H
X
Self-
refresh
L
L
H
H
H
L
L
L
H
H
L
H
L
L
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Illegal
Illegal
L
L
X
X
X
X
H
H
L
Illegal
L
X
X
H
L
X
X
X
H
H
H
L
Maintain Self-refresh
Invalid
L
X
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
Idle after tRC
Idle after tRC
Illegal
Self-
refresh
Recovery
L
L
X
X
X
X
X
X
H
X
X
X
Illegal
L
X
X
X
X
X
H
X
X
L
Illegal
X
X
X
H
L
X
X
X
X
H
X
L
Illegal
Illegal *
X
H
H
L
Invalid
Exit Power Down Mode → Idle
L
Power
Down
L
X
L
Maintain Power Down Mode
L
H
H
Illegal
L
L
H
Illegal
(Continued)
13
MB811L323229-12/18
(Continued)
CKE
Current State
CS RAS CAS WE
Addr
Function
n-1
n
Bank Active,
Bank
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Refer to “Operation Command Table”.
Activating,
Read/Write,
All Banks idle ,
Refreshing,
Precharging
Refer to “Operation Command Table”.
Start Clock Suspend next cycle
H
L
L
X
Invalid
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Invalid
Clock
Suspend
Exit Clock Suspend next cycle
Maintain Clock Suspend
Invalid
L
L
X
H
L
Any State
Other Than
Listed Above
H
H
Refer to “Operation Command Table”.
Illegal
V = Valid, L = Logic Low, H = Logic High, X = either L or H,
n = state at current clock cycle, n−1 = state at 1 clock cycle before n.
* : CKE should be held High for tRC period after tCKSP.
Notes : • All entries in “5. Command Truth Table for CKE” are specified at CKE(n) state and CKE input from
CKE(n–1) to CKE(n) state must satisfy corresponding set up and hold time for CKE.
• All commands assume no CSUS command on previous rising edge of clock.
• All commands are assumed to be valid state transitions.
• All inputs are latched on the rising edge of the clock.
14
MB811L323229-12/18
■ FUNCTIONAL DESCRIPTION
1. SDR I/F FCRAM Basic Function
Three major differences between this SDR I/F FCRAMs and conventional DRAMs are: synchronized operation,
burst mode, and mode register.
The synchronized operation is the fundamental difference. SDR I/F FCRAM uses a clock input for the syn-
chronization, while the DRAM is basically asynchronous memory although it has been using two clocks, RAS
and CAS. Each operation of DRAM is determined by their timing phase differences while each operation of SDR
I/F FCRAM is determined by commands and all operations are referenced to a positive clock edge. “BASIC
TIMING FOR CONVENTIONAL DRAM VS SDR I/F CRAM” shows the basic timing diagram differences between
SDR I/F FCRAMs and DRAMs.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a
column address for the first access is set, following addresses are automatically generated by the internal column
address counter.
The mode register is to justify the SDR I/F FCRAM operation and function into desired system conditions.
“■ MODE REGISTER TABLE” shows how SDR I/F FCRAM can be configured for system requirement by mode
register programming.
The program to the mode register should be executed after all banks are precharged.
2. FCRAMTM
MB811L323229 utilizes FCRAM core technology. The FCRAM is an acronym for Fast Cycle Random Access
Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
3. Clock Input (CLK) and Clock Enable (CKE)
All input and output signals of SDR I/F FCRAM use register type buffers. CLK is used as a trigger for the register
and internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated
by the a rising edge of CLK. CKE is a high active clock enable signal. CKE controls the internal clock generator.
CKE is latched by a rising edge of CLK. CKE should become High level on the previous clock cycle when a
basic command is issued. When CKE = Low is latched at a clock input during active cycle, the next clock will
be internally masked. During idle state (all banks have been precharged), the Power Down mode (standby) is
entered with CKE = Low and this will make extremely low standby current.
4. Chip Select (CS)
CS enables all commands inputs, RAS, CAS, WE, and address input. When CS is High, command signals are
negated but internal operation such as burst cycle will not be suspended. If such a control isn’t needed, CS can
be tied to ground level.
5. Command Input (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDR I/F FCRAM operation, such as Row
address strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at
a rising edge of the CLK determines SDR I/F FCRAM operation. Refer to “■ FUNCTIONAL TRUTH TABLE.”
6. Address Input (A0 to A10)
Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of
nineteen address input signals are required to decode such a matrix. SDR I/F FCRAM adopts an address
multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV), eleven Row
addresses are initially latched and the remainder of eight Column addresses are then latched by a Column
address strobe command of either a Read command (READ or READA) or Write command (WRIT or WRITA).
7. Bank Select (BA)
This SDR I/F FCRAM has two banks and each bank is organized as 512 K words by 32-bit.
Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT
or WRITA), and precharge command (PRE).
15
MB811L323229-12/18
8. Data Input and Output (DQ0 to DQ31)
Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input:
tRAC ; from the bank active command when tRCD (Min) is satisfied. (This parameter is reference only.)
tCAC ; from the read command when tRCD is greater than tRCD (Min). (This parameter is reference only.)
tAC ; from the previous clock edge when output data is valid.
The polarity of the output data is identical to that of the input data. Data is valid between access time (determined
by the three conditions above) and the next positive clock edge (tOH).
Refer to “■ AC CHARACTERISTICS.”
9. Data I/O Mask (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and
when DQM0 to DQM3 = High is latched by a clock, input is masked at the same clock and output will be masked
at the second clock later while internal burst counter will increment by one or will go to the next stage depending
on burst type. DQM0, DQM1, DQM2 and DQM3 control DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23 and DQ24 to DQ31,
respectively.
10. Burst Mode Operation and Burst Type
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row
address and by automatic strobing column address. Access time and cycle time of Burst mode is specified as
tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which
defines burst type and burst count length of 1, 2, 4, 8 bits of boundary or full column. In order to terminate or to
move from the current burst mode to the next stage while the remaining burst count is more than 1, the following
combinations will be required:
Current Stage
Next Stage
Method (Assert the following command)
Read Command
Burst Read
Burst Read
1st Step
2nd Step
Mask Command (Normally 3 clock cycles)
Write Command after OWD
Write Command
Burst Read
Burst Write
Burst Write
Burst Write
Burst Read
Burst Write
Burst Write
Burst Read
Precharge
Precharge
Read Command
Precharge Command
Precharge Command
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. But only the
sequential mode is usable to the full column burst. The sequential mode is an incremental decoding scheme
within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address
until reaching the end of boundary address and then wraps round to least significant address (= 0). The interleave
mode is a scrambled decoding scheme for A0 and A2. If the first access of column address is even (0), the next
address will be odd (1), or vice-versa.
16
MB811L323229-12/18
Starting Column
Address
Burst
Length
Sequential Mode
Interleave Mode
A2
X
X
X
X
X
X
0
A1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 – 1
0 – 1
2
4
1 – 0
1 – 0
0 – 1 – 2 – 3
1 – 2 – 3 – 0
2 – 3 – 0 – 1
3 – 0 – 1 – 2
0 – 1 – 2 – 3
1 – 0 – 3 – 2
2 – 3 – 0 – 1
3 – 2 – 1 – 0
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
1 – 2 – 3 – 4 – 5 – 6 – 7 – 0
2 – 3 – 4 – 5 – 6 – 7 – 0 – 1
3 – 4 – 5 – 6 – 7 – 0 – 1 – 2
4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
5 – 6 – 7 – 0 – 1 – 2 – 3 – 4
6 – 7 – 0 – 1 – 2 – 3 – 4 – 5
7 – 0 – 1 – 2 – 3 – 4 – 5 – 6
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
1 – 0 – 3 – 2 – 5 – 4 – 7 – 6
2 – 3 – 0 – 1 – 6 – 7 – 4 – 5
3 – 2 – 1 – 0 – 7 – 6 – 5 – 4
4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
5 – 4 – 7 – 6 – 1 – 0 – 3 – 2
6 – 7 – 4 – 5 – 2 – 3 – 0 – 1
7 – 6 – 5 – 4 – 3 – 2 – 1 – 0
0
0
0
8
1
1
1
1
11. Full Column Burst and Burst Stop Command (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full
column burst mode is repeatedly access to the same column. If burst mode reaches end of column address,
then it wraps around to first column address (= 0) and continues to count until interrupted by the news read
(READ) /write (WRIT), precharge (PRE), or burst stop (BST) command. The selection of Auto-precharge option
is illegal during the full column burst operation except write command at BURST READ & SINGLE WRITE mode.
The BST command is applicable to terminate the burst operation. If the BST command is asserted during the
burst mode, its operation is terminated immediately and the internal state moves to Bank Active.
When read mode is interrupted by BST command, the output will be in High-Z.
For the detail rule, please refer to “8. READ Interrupted by Burst Stop (Example @ CL = 2, BL = Full Column) ”
in “■ TIMING DIAGRAMS.”
When write mode is interrupted by BST command, the data to be applied at the same time with BST command
will be ignored.
12. Burst READ & Single WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this
mode, burst read operation does not be affected by this mode.
17
MB811L323229-12/18
13. Precharge and Precharge Option (PRE, PALL)
SDR I/F FCRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations.
Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge
command (PRE). With the Precharge command, SDR I/F FCRAM will automatically be in standby state after
precharge time (tRP).
The precharged bank is selected by combination of AP and BAwhen Precharge command is asserted. If AP =
High, all banks are precharged regardless of BA (PALL). If AP = Low, a bank to be selected by BA is precharged
(PRE).
Theauto-prechargeentersprechargemodeattheendofburstmodeofreadorwritewithoutPrechargecommand
assertion.
This auto precharge is entered by AP = High when a read or write command is asserted. Refer to “■ FUNC-
TIONAL TRUTH TABLE.”
14. Auto-Refresh (REF)
Auto-refresh uses the internal refresh address counter. SDR I/F FCRAM Auto-refresh command (REF) generates
Precharge command internally. All banks of SDR I/F FCRAM should be precharged prior to the Auto-refresh
command. The Auto-refresh command should also be asserted every 15.6 µs or a total 2048 refresh commands
within 32 ms period.
15. Self-Refresh Entry (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue
the refresh function until cancelled by SELFX.
Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once SDR
I/F FCRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or low
level state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained.
SELF command should only be issued after last read data has been appeared on DQ.
Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within
2 ms prior to the self-refresh mode entry.
16. Self-Refresh Exit (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No Operation command
(NOP) or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High
within one tRC period after tCKSP. Refer to “16. Self-Refresh Entry and Exit Timing” in “■ TIMING DIAGRAMS” for
the detail.
It is recommended to assert an Auto-refresh command just after tRC period to avoid the violation of refresh period.
Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within
2 ms after the self-refresh exit.
17. Mode Register Set (MRS)
The mode register of SDR I/F FCRAM provides a variety of different operations. The register consists of four
operation fields; Burst Length, Burst Type, CAS latency, and Operation Code. Refer to “■ MODE REGISTER
TABLE.”
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the
address line. Once a mode register is programmed, the contents of the register will be held until re-programmed
by another MRS command (or part loses power). MRS command should only be issued on condition that all DQ
is in High-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDR I/F FCRAM. Refer to “18. Power-Up Initialization”.
18
MB811L323229-12/18
18. Power-Up Initialization
SDR I/F FCRAM internal condition after power-up will be undefined. It is required to follow the following Power
On Sequence to execute read or write operation.
1. Apply power (VDD and VDDI should be applied before or in parallel with VCCQ)and start clock. Attempt to
maintain either NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 µs.
3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
4. Assert minimum of 2 Auto-refresh command (REF).
5. Program the mode register by Mode Register Set command (MRS).
In addition, it is recommended DQM and CKE to track VDD to insure that output is High-Z state. The Mode Register
Set command (MRS) can be set before 2 Auto-refresh command (REF). It is possible to execute 5, after 4.
19. Disable
When DSE PAD is applied high level, SDR I/F FCRAM entries DISABLE mode. This command entry doesn’t
require clock. In DISABLE mode, SDR I/F FCRAM current consumption is less than ICC2PS and output is High-
Z. Any command isn’t accepted in this mode. To exit DISABLE mode, apply Low level to DSE PAD.
20. Burn IN
When BME PAD is applied High level, SDR I/F FCRAM entries BURN IN mode. In BURN IN mode, self refresh
function is asserted internally. This command doesn’t require clock. Any command isn’t accepted in this mode.
To exit BURN IN mode, apply Low level to BME PAD.
19
MB811L323229-12/18
BASIC TIMING FOR CONVENTIONAL DRAM VS SDR I/F FCRAM
<SDR I/F FCRAM>
Read/Write
Active
Precharge
CLK
H
H
H
CKE
tSI
tHI
CS
RAS
CAS
H : Read
WE
L : Write
Address
BA
RA
BA
AP (A10)
BA
CA
CAS Latency = 2
DQ0 to DQ31
Burst Length = 4
<Conventional DRAM>
Row Address Select
Columm Address Select
Precharge
RAS
CAS
DQ0 to DQ31
20
MB811L323229-12/18
■ STATE DIAGRAM (Simplified for Single Bank Operation State Diagram)
MRS
SELF
MODE
REGISTER
SET
SELF
REFRESH
SELFX
IDLE
REF
CKE
CKE\
(PD)
AUTO
REFRESH
POWER
DOWN
BANK
ACTIVE
SUSPEND
CKE\ (CSUS)
BANK
ACTIVE
CKE
BST
BST
READ
READ
WRIT
WRIT
READA
READ
WRITA
CKE
CKE
READ
SUSPEND
WRITE
SUSPEND
READ
WRITE
WRIT
CKE\ (CSUS)
WRITA
CKE\ (CSUS)
READA
WRITA
READA
CKE
CKE
READ WITH
AUTO
PRECHARGE
WRITE WITH
AUTO
PRECHARGE
WRITE
SUSPEND
READ
SUSPEND
PRE
or
PRE
or
CKE\ (CSUS)
CKE\ (CSUS)
PALL
PALL
PRE or PALL
POWER
ON
PRECHARGE
POWER
APPLIED
DEFINITION OF ALLOWS
Manual
Input
Automatic
Sequence
Note : CKE\ means CKE goes Low-level from High-level.
21
MB811L323229-12/18
■ BANK OPERATION COMMAND TABLE
• Minimum Clock Latency or Delay Time for 1 Bank Operation
*4
*4
Second
command
(same
bank)
First
command
MRS
tRSC
tRSC
tRSC
tRAS
tRSC
tRAS
tRSC
tRSC
tRSC
1
ACTV
READ
tRCD
tRCD
tRCD
tRCD
5
5
4
4
*
*
*
*
1
1
1
1
1
1
1
4
4
2
*1, *2
BL
+
*
*
*
*2, *7
BL
+
BL
+
BL
+
BL
+
BL
+
READA
WRIT
tRP
tRP
tRP
tRP
tRP
tRP
4
4
*
*
tWR
tWR
1
1
tDPL
tDPL
1
2
4
4
2
2
*
*
*
*
*
BL-1
+
BL-1
+
BL-1
+
BL-1
+
BL-1
+
BL-1
+
WRITA
tDAL
tDAL
tDAL
tDAL
tDAL
tDAL
4
2
*2, *3
*
*
*2, *6
PRE
PALL
REF
tRP
tRP
tRP
tRC
tRC
1
1
1
tRP
tRP
tRC
tRC
tRP
1
1
3
6
*
*
tRP
tRC
tRC
1
tRP
tRC
tRC
tRC
tRC
tRC
tRC
tRC
tRC
SELFX
*1 : If tRP(Min) ≤ CL×tCK, minimum latency is a sum of (BL+CL)×tCK.
*2 : Assume all banks are in Idle state.
*3 : Assume output is in High-Z state.
*4 : Assume tRAS(Min) is satisfied.
*5 : Assume no I/O conflict.
*6 : Assume after the last data have been appeared on DQ.
*7 : If tRP(Min) ≤ (CL-1)×tCK, minimum latency is a sum of (BL+CL-1)×tCK.
Illegal Command
22
MB811L323229-12/18
• Minimum Clock Latency or Delay Time for Multi Bank Operation
*5
*5, *6
*5
*5, *6
Second
command
(same
bank)
First
command
MRS
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
1
2
7
7
7
7
7
*
*
*
*
*
*6, *7
1
*
ACTV
READ
READA
WRIT
tRRD
1
1
1
1
tRAS
*2, *4
1
*
*
*
*
10
10
6
6
1
1
1
1
1
1
1
*1, *2
BL+
tRP
*2, *4
1
*
*
*6, *10
1
*6, *10
1
*
*
*
*2, *9
BL+
tRP
6
6
6
6
2
1
1
1
BL+
tRP
BL+
tRP
*2, *4
1
*
*
6
6
1
1
1
1
1
tDPL
1
2
6
6
6
6
6
6
2
2
*
*2, *4
1
*
*
*
*
*
*
*
*
BL-1
+
BL-1
+
BL-1
+
BL-1
+
WRITA
1
1
1
1
1
tDAL
tDAL
tDAL
tDAL
7
7
7
7
7
2
*2, *3
tRP
*2, *4
1
*
*
*
*
*6, *7
1
*
*
*2, *8
tRP
PRE
PALL
REF
1
1
1
1
1
tRP
tRP
tRC
tRC
1
1
3
8
*
*
tRP
tRC
tRC
tRP
tRC
tRC
1
1
tRP
tRC
tRC
tRC
tRC
tRC
tRC
tRC
tRC
SELFX
*1 : If tRP(Min) ≤ CL×tCK, minimum latency is a sum of (BL+CL)×tCK.
*2 : Assume bank of the object is in Idle sate.
*3 : Assume output is in High-Z sate.
*4 : tRRD(Min) of other bank (second command will be asserted) is satisfied.
*5 : Assume other bank is in active, read or write state.
*6 : Assume tRAS(Min) is satisfied.
*7 : Assume other banks are not in READA/WRITA state.
*8 : Assume after the last data have been appeared on DQ.
*9 : If tRP(Min) ≤ (CL-1)×tCK, minimum latency is a sum of (BL+CL-1)×tCK.
*10 : Assume no I/O conflict.
Illegal Command
23
MB811L323229-12/18
■ MODE REGISTER TABLE
MODE REGISTER SET
BA A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 ADDRESS
*3
*3
Op-
code
MODE
REGISTER
0 or 1
0
0
CL
BT
BL
CAS Latency
Burst Length
A5
A6
A4
A2
A1
A0
BT = 0
BT = 1 *2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
Reserved
2
4
8
8
Reserved
Reserved
Reserved
Full Column
Reserved
Reserved
Reserved
Reserved
A9
Op-code
Burst Read & Burst Write
A3
Burst Type
0
1
0
1
Sequential (Wrap round, Binary-up)
Interleave (Wrap round, Binary-up)
*1
Burst Read & Single Write
*1 : When A9 = 1, burst length at Write is always one regardless of BL value.
*2 : BL = 1 and Full Column are not applicable to the interleave mode.
*3 : A7 = 1 and A8 = 1 are reserved for vender test.
24
MB811L323229-12/18
■ ABSOLUTE MAXIMUM RATINGS (See WARNING)
Rating
Unit
Parameter
Symbol
Min
–0.5
–0.5
–0.5
–50
—
Max
+4.6
+3.6
+4.6
+50
Voltage of VCCQ Supply Relative to VSS
Voltage of VDD Supply Relative to VSS
Voltage at Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
VCCQ
VDD, VDDI
VIN, VOUT
IOUT
V
V
V
mA
W
°C
PD
1.0
Storage Temperature
TSTG
–55
+125
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Value
Parameter
Symbol
Unit
Min
3.0
2.3
2.3
0
Typ
3.3
2.5
2.5
0
Max
3.3V I/O
2.5V I/O
3.6
V
V
VCCQ
2.7
Supply Voltage
VDD, VDDI
VSS, VSSQ, VSSI
2.7
0
V
V
3.3V I/O
2.5V I/O
2.4
2.0
–0.5
0
—
VCCQ + 0.5
VCCQ + 0.5
0.4
V
Input High Voltage *1
VIH
—
V
Input Low Voltage *2
Ambient Temperature
VIL
—
V
TA
—
70
°C
*1 : Overshoot limit: VIH (Max)
*2 : Undershoot limit: VIL (Min)
= 4.6V for pulse width ≤ 5 ns acceptable,
= VSS -1.5V for pulse width ≤ 5 ns acceptable,
pulse width measured at 50% of pulse ampli-
pulse width measured at 50% of pulse amplitude.
Pulse width ≤ 5 ns
4.6 V
VIH
VIL (Max)
VIL
50% of pulse amplitude
VIH
50% of pulse amplitude
VIH (Min)
Pulse width ≤ 5 ns
-1.5 V
VIL
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
25
MB811L323229-12/18
■ CAPACITANCE
(TA = +25°C, f = 1 MHz)
Value
Typ
—
Parameter
Symbol
Unit
Max
Min
1.5
1.5
2.0
Input Capacitance, Except for CLK
Input Capacitance for CLK
CIN1
CIN2
CI/O
5.0
4.0
6.0
pF
pF
pF
—
I/O Capacitance (DQ0 to DQ31)
—
26
MB811L323229-12/18
■ DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
Value
Parameter
Symbol
Condition
Unit
V
Min
Max
3.3V I/O IOH = –2 mA
2.4
—
Output High Voltage
Output Low Voltage
VOH(DC)
2.5V I/O IOH = –0.5 mA
3.3V I/O IOL = 2 mA
2.0
—
—
V
0.4
0.4
V
VOL(DC)
2.5V I/O IOL = 0.5 mA
—
V
0 V ≤ VIN ≤ VCCQ;
All other pins not under
test = 0 V
Input Leakage Current (Any Input ex-
cept for DSE,BME)
ILI
–5
–5
5
+5
+5
20
µA
µA
kΩ
VIN = 0 V
All other pins not under
test = 0V
Input Leakage Current
(DSE,BME)
ILIPD
Input Pull Down Resistance
(DSE, BME)
RPD
0 V ≤ VIN ≤ VCCQ;
High impedance
Output Leakage Current
ILO
–5
—
+5
µA
Burst Length = 1,
tCK = Min, tRC = Min,
One bank active,
MB811L323229-12
Operating Current
(Average Power
120
80
Output pin open,
ICC1
mA
Adrress changed up to
1 - time during tRC (Min),
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
Supply Current)
MB811L323229-18
(Continued)
27
MB811L323229-12/18
Value
Max
Parameter
Symbol
Condition
CKE = VIL,
Unit
Min
All banks idle,
tCK = Min,
ICC2P
—
2
1
mA
Power down mode,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
CKE = VIL,
All banks idle,
CLK = VIH or VIL,
Power down mode,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
ICC2PS
—
—
—
mA
mA
mA
Power Supply
Current
(Precharge
CKE = VIH,
All banks idle, tCK = Min,
NOP commands only,
Input signals (except to
CMD) are changed 1 time
during 2 clocks,
12
8
Standby Current)
MB811L323229-12
MB811L323229-18
ICC2N
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
CKE = VIH,
All banks idle,
CLK = VIH or VIL,
Input signal are stable,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
ICC2NS
2
(Continued)
28
MB811L323229-12/18
(Continued)
Value
Parameter
Symbol
Condition
Unit
Min
Max
CKE = VIL,
Any bank active,
tCK = Min,
ICC3P
—
2
mA
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
CKE = VIL,
Any bank active,
CLK = VIH or VIL,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
ICC3PS
—
—
1
mA
mA
CKE = VIH,
Any bank active,
tCK = Min,
NOP commands only,
Input signals (except to
CMD) are changed 1 time
during 2 clocks,
Power Supply
Current
MB811L323229-12
37.5
25
(Active Standby
Current)
ICC3N
MB811L323229-18
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
CKE = VIH,
Any bank active,
CLK = VIH or VIL,
Input signals are stable,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
ICC3NS
—
—
2
mA
mA
tCK = Min,
Burst Length = 4,
Output pin open,
All-banks active,
Gapless data output,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
MB811L323229-12
MB811L323229-18
143
95
Average Power
Supply Current
(Burst mode Cur-
rent)
ICC4
Auto-refresh;
tCK = Min,
tRC = Min,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
Average Power
Supply Current
(Refresh Current
#1)
MB811L323229-12
MB811L323229-18
150
100
ICC5
—
—
mA
mA
Self-refresh;
tCK = Min,
CKE ≤ 0.2 V,
0 V ≤ VIN ≤ VIL Max,
VIH Min ≤ VIN ≤ VCCQ
Average Power Supply Current
(Refresh Current #2)
ICC6
2.5
Notes : • All voltages are referenced to VSS.
• DC characteristics are measured after following the 18. Power-Up Initialization procedure in
“■ FUNCTIONAL DESCRIPTION.”
• ICC depends on the output termination or load condition, clock cycle rate, signal clocking rate.
The specified values are obtained with the output open and no termination register.
29
MB811L323229-12/18
■ AC CHARACTERISTICS
(1) AC Characteristics
(At recommended operating conditions unless otherwise noted.)
MB811L323229-12 MB811L323229-18
Parameter
Symbol
Unit
Min
Max
—
—
—
—
—
9
Min
Max
—
—
—
—
—
9
Clock Period
CL = 2
tCK2
tCH
tCL
12
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock High Time
tCK x 0.3
tCK x 0.4
Clock Low Time
tCK x 0.3
tCK x 0.4
Input Setup Time
tSI
3
1.5
—
0
4
1.5
—
0
Input Hold Time
tHI
Access Time from Clock (tCK =Min) *2,*3,*4 CL = 2
Output in Low-Z *2
tAC2
tLZ
—
9
—
9
Output in High-Z *2,*5
Output Hold Time *2,*4
CL = 2
CL = 2
tHZ2
tOH
2
2
2
—
2
—
Time between Auto-Refresh command
interval *1
tREFI
—
15.6
—
15.6
µs
Time between Refresh
Transition Time
tREF
—
32
10
—
32
10
ms
ns
tT
0.5
0.5
CKE Setup Time for Power Down Exit
Time *2
tCKSP
3
—
4
—
ns
*1 : This value is for reference only.
*2 : If input signal transition time (tT) is longer than 1 ns; [(tT/2) – 0.5] ns should be added to tAC (Max), tHZ (Max),
and tCKSP (Min) spec values, [(tT/2) – 0.5] ns should be subtracted from tLZ (Min), tHZ (Min), and tOH (Min) spec
values, and (tT – 1.0) ns should be added to tCH (Min), tCL (Min), tSI (Min), and tHI (Min) spec values.
*3 : tAC also specifies the access time at burst mode.
*4 : tAC and tOH are measured under OUTPUT LOAD CIRCUIT shown in “OUTPUT LOAD CIRCUIT”.
*5 : Specified where output buffer is no longer driven.
Notes : • AC characteristics are measured after following the POWER-UP INITIALIZATION procedure. (See “18.
Power-Up Initialization in ■ FUNCTIONAL DESCRIPTION.)
• AC characteristics assume tT = 1 ns, 10 pF of capacitive load and 50 Ω of terminated load.
• 1.4 V is the reference level for 3.3 V I/O for measuring timing of input signals. 1.2 V is the reference level
for 2.5 V I/O for measuring timing of input signals. Transition times are measured between VIH (Min) and
VIL (Max).
30
MB811L323229-12/18
(2) Base Values for Clock Count/Latency
Parameter
MB811L323229-12
MB811L323229-18
Symbol
Unit
Min
72
24
48
24
18
24
12
Max
—
Min
108
36
Max
—
RAS Cycle Time *
t
RC
ns
ns
ns
ns
ns
ns
ns
RAS Precharge Time
tRP
tRAS
tRCD
tWR
—
—
RAS Active Time
110000
—
72
110000
—
RAS to CAS Delay Time
Write Recovery Time
36
—
18
—
RAS to RAS Bank Active Delay Time
Data-in to Precharge Lead Time
tRRD
tDPL
—
36
—
—
18
—
Data-in to Active/Refresh Com-
mand Period
CL=2
tDAL2
1 cyc + tRP
24
—
—
1 cyc + tRP
36
—
—
ns
ns
Mode Resister Set Cycle Time
tRSC
* : Actual clock count of tRC ( RC) will be sum of clock count of tRAS ( RAS) and tRP ( RP).
(3) CLOCK COUNT FORMULA
Base Value
Clock Period
Clock cycle ≥
(Round up a whole number)
Note : All base values are measured from the clock edge at the command input to the clock edge for the next
command input. All clock counts are calculated by a simple formula: clock count equals base value divided
by clock period (round off to a whole number).
31
MB811L323229-12/18
(4) LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Symbol MB811L323229-12 MB811L323229-18 Unit
Parameter
CKE to Clock Disable
CKE
1
2
0
2
0
2
2
1
1
2
0
2
0
2
2
1
1
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
DQM to Output in High-Z
DQZ
DQM to Input Data Delay
DQD
OWD
DWD
ROH2
BSH2
CCD
CBD
Last Output to Write Command Delay
Write Command to Input Data Delay
Precharge to Output in High-Z Delay
Burst Stop Command to Output in High-Z Delay
CAS to CAS Delay (Min)
CAS Bank Delay (Min)
1
OUTPUT LOAD CIRCUIT
R1 = 50 Ω
Output
1.4 V (3.3 V I/O)
1.2 V (2.5 V I/O)
CL = 10 pF
Note:Byaddingappropriatecorrelationfactorstothetestconditions, tAC andtOH measured
when the Output is coupled to the Output Load Circuit are within specifications.
32
MB811L323229-12/18
(5) Timing Diagram, Setup, Hold and Delay Time
tCK2
tCH
tCL
2.4 V (3.3 V I/O)
2.0 V (2.5 V I/O)
1.4 V (3.3 V I/O)
1.2 V (2.5 V I/O)
CLK
0.4 V
tSI
tHI
2.4 V (3.3 V I/O)
Input
2.0 V (2.5 V I/O)
1.4 V (3.3 V I/O)
1.2 V (2.5 V I/O)
VALID
(Control, Addr. & Data)
0.4 V
tAC2
tHZ2
tLZ
tOH
2.4 V (3.3 V I/O)
2.0 V (2.5 V I/O)
1.4 V (3.3 V I/O)
1.2 V (2.5 V I/O)
VALID
Output
0.4 V
Notes : • Reference level of input signal is 1.4 V for LVCMOS (3.3V I/O),1.2V for LVCMOS (2.5V I/O).
• Access time is measured at 1.4 V for LVCMOS (3.3V I/O),1.2V for LVCMOS (2.5V I/O).
• AC characteristics are also measured in this condition.
(6) Timing Diagram, Delay Time for Power Down Exit
H or L
CLK
tCKSP (Min)
1 clock (Min)
CKE
H or L
NOP
NOP
ACTV
Command
33
MB811L323229-12/18
(7) Timing Diagram, Pulse Width
CLK
tRC, tRP, tRAS, tRCD, tWR, tREF,
tDPL, tDAL, tRSC, tRRD, tCKSP
Input
COMMAND
(Control)
COMMAND
Invalid Data
Notes : • These parameters are a limit value of the rising edge of the clock from one command input
to next input. tCKSP is the latency value from the rising edge of CKE.
• Measurement reference voltage is 1.4 V (3.3V I/O) or 1.2V (2.5V I/O).
(8) Timing Diagram, Access Time
CLK
READ
Command
tAC2
tAC2
tAC2
(CAS Latency-1) × tCK
DQ
(Output)
Q (Valid)
Q (Valid)
Q (Valid)
34
MB811L323229-12/18
■ TIMING DIAGRAMS
1. Clock Enable - READ and WRITE Suspend (@ BL = 4)
CSUS Command
CSUS Command
CLK
CKE
*1
*1
CKE
CKE
(1 clock)
(1 clock)
*2
*2
CLE
(Internal)
*2
*2
DQ
(Read)
Q1
D1
Q2 (NO CHANGE)
Q3 (NO CHANGE)
Q4
D4
*3
*3
DQ
(Write)
NOT
NOT
D2
D3
WRITTEN
WRITTEN
*1 : The latency of CKE ( CKE) is one clock.
*2 : During read mode, burst counter will not be increased or decreased at the next clock of CSUS
command. Output data remain the same data.0
*3 : During the write mode, data at the next clock of CSUS command is ignored.
2. Clock Enable - Power Down Entry and Exit
CLK
tCKSP (Min)
1 clock (Min)
CKE
*1
*3
*3
*4
Command
NOP
PD (NOP)*2
NOP
NOP
ACTV
H or L
tREF (Max)
*1 : Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.
*2 : Precharge command can be posted in conjunction with CKE after the last read data have been
appeared on DQ.
*3 : It is recommended to apply NOP command in conjunction with CKE.
*4 : The ACTV command can be latched after tCKSP (Min) + 1 clock (Min).
35
MB811L323229-12/18
3. Column Address to Column Address Input Delay
CLK
RAS
CCD
tRCD (Min)
(1 clock)
CCD
CCD
CCD
CAS
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Address
Note : CAS to CAS delay can be one or more clock period.
4. Different Bank Address Input Delay
CLK
tRRD (Min)
RAS
CBD
(1 clock)
tRCD (Min) or more
CBD
CAS
tRCD (Min)
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Address
BA
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Note : CAS Bank delay can be one or more clock period.
36
MB811L323229-12/18
5. DQM0 to DQM3 - Input Mask and Output Disable (@ BL = 4)
CLK
DQM
(@ Read)
DQZ2 (2 clocks)
Q2
DQ
(@ Read)
High-Z
Q1
Q4
End of burst
DQM
(@ Write)
DQD (same clock)
DQ
(@ Write)
D1
D3
D4
MASKED
End of burst
6. Precharge Timing (Applied to The Same Bank)
CLK
tRAS (Min)
Command
ACTV
PRE
Note : PRECHARGE means ’PRE’ or ’PALL’.
37
MB811L323229-12/18
7. READ Interrupted by Precharge (Example @ CL = 2, BL = 4)
CLK
PRECHARGE
Command
ROH2 (2 clolcks)
High-Z
Q1
DQ
PRECHARGE
Command
ROH2 (2 clolcks)
Q2
High-Z
DQ
Q1
Command
DQ
PRECHARGE
ROH2 (2 clolcks)
Q3
High-Z
Q1
Q2
Command
DQ
PRECHARGE
No effect (end of burst)
Q3 Q4
Q1
Q2
Notes : • In case of CL = 2, the ROH2 is 2 clocks.
• PRECHARGE means ’PRE’ or ’PALL’.
38
MB811L323229-12/18
8. READ Interrupted by Burst Stop (Example @ CL = 2, BL = Full Column)
CLK
BST
Qn
Command
DQ
BSH2 (2 clocks)
High-Z
Qn − 2
Qn − 1
Qn + 1
9. WRITE Interrupted by Burst Stop (Example @ BL = 2)
CLK
Command
DQ0
COMMAND
BST
LAST
DATA-IN
Masked
by BST
39
MB811L323229-12/18
10. WRITE Interrupted by Precharge (Example @ CL = 2)
CLK
WRIT
PRECHARGE
ACTV
Command
tDPL (Min)
tRP (Min)
MASKED
by Precharge
LAST
DATA-IN
DQ
DATA-IN
Note : • The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied.
• PRECHARGE means ’PRE’ or ’PALL’.
11. READ Interrupted by WRITE (Example @ CL = 2, BL = ≥ 4)
CLK
OWD (2 clocks)
Command
DQM
READ
WRIT
*1
*2
*3
DQZ (2 clocks)
DWD (same clock)
Q1
D1
D2
DQ
Masked
*1 : The first DQM makes high-impedance state High-Z between last output and first input data.
*2 : The second DQM makes internal output data mask to avoid bus contention.
*3 : The third DQM also makes internal output data mask. If burst read ends (final data output) at or after
the second clock of burst write, this third DQM is required to avoid internal bus contention.
40
MB811L323229-12/18
12. WRITE to READ Timing (Example @ CL = 2, BL = 4)
CLK
tWR (Min)
WRIT
READ
Command
DQM
(CL − 1) × tCK2
tAC2 (Max)
D3
DQ
D1
D2
Q1
Q2
Q3
Masked
by READ
Notes : • Read command should be issued after tWR of final data input is satisfied.
• The write data after the READ command is masked by the READ command.
13. READ with Auto-Precharge (Example @ CL = 2, BL = 2 Applied to Same Bank)
CLK
tRAS (Min)
READA
tRP (Min)
Command
DQM
NOP or DESL
ACTV
ACTV
*1
2 clocks
(same value as BL)
*2
BL + tRP (Min)
DQ
Q1
Q2
*1 : Precharge at read with Auto-precharge command (READA) is started from number of clocks
that is the same as Burst Length (BL) after the READA command is asserted.
*2 : The next ACTV command should be issued after BL + tRP (Min) from READA command.
41
MB811L323229-12/18
14. WRITE with Auto-Precharge (Example @ CL = 2, BL = 2 Applied to Same Bank)
tRAS (Min)
CLK
CL + 1 *1
tDAL2 (Min)
*2
BL + tRP (Min)
NOP or DESL
WRITA
ACTV
ACTV
Command
DQM
D1
D2
DQ
*1 : Precharge at write with Auto-precharge is started after CL - 1 from the end of burst.
*2 : The next command should be issued after BL+ tRP (Min) at CL = 2 from WRITA command.
Notes: • Even if the final data is masked by DQM, the precharge does not start the clock of final data input.
• Once auto precharge command is asserted, no new command within the same bank can be issued.
• Auto-precharge command doesn’t affect at full column burst operation except Burst READ & Single
Write.
15. Auto-Refresh Timing
CLK
*1
*3
*3
*3
*3
Command *4
Command
REF
NOP
NOP
NOP
REF
NOP
tRC (Min)
tRC (Min)
*2
*2
H or L
BA
H or L
BA
*1 : All banks should be precharged prior to the first Auto-refresh command (REF).
*2 : Bank select is ignored at REF command. The refresh address and bank select are selected by internal
refresh counter.
*3 : Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode.
*4 : Any activation command such as ACTV or MRS command other than REF command should be asserted
after tRC from the last REF command.
42
MB811L323229-12/18
16. Self-Refresh Entry and Exit Timing
CLK
tCKSP (Min)
tSI (Min)
CKE
*6
tRC (Min)*5
SELF *2
NOP *1
H or L
Command
NOP *3
SELFX
NOP *4
Command
*1 : The precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh
Entry command (SELF).
*2 : SELF command should be issued only after the last read data has been appeared on DQ.
*3 : The Self-refresh Exit command (SELFX) is latched after tCKSP (Min). It is recommended to apply NOP
command in conjunction with CKE.
*4 : Either NOP or DESL command can be used during tRC period.
*5 : CKE should be held high within one tRC period after tCKSP.
*6 : CKE level should be held less than 0.2 V during self-refresh mode.
17. Mode Register Set Timing
CLK
tRSC (Min)
MRS
NOP or DESL
ACTV
Command
Address
ROW
ADDRESS
MODE
Note : The Mode Register Set command (MRS) should only be asserted after all banks have been
precharged and DQ is in High-Z.
43
MB811L323229-12/18
■ ORDERING INFORMATION
Part number
Configuration
Shipping form
wafer
Remarks
MB811L323229-12WFKT
MB811L323229-18WFKT
524,288 word × 32 bit × 2 bank
524,288 word × 32 bit × 2 bank
wafer
44
MB811L323229-12/18
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0205
FUJITSU LIMITED Printed in Japan
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