MB81N261647A-22FN [FUJITSU]
DDR DRAM, 16MX16, 0.85ns, CMOS, PDSO66;
| 型号： | MB81N261647A-22FN |
| 厂家： | 
FUJITSU |
| 描述： | DDR DRAM, 16MX16, 0.85ns, CMOS, PDSO66 时钟 动态存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总50页 (文件大小：1020K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
AE1E
MEMORY
CMOS
256M BIT
DOUBLE DATA RATE FCRAM™
MB81N26847A/261647A-22/-24/-30
CMOS 4-BANK x 67,108,864 BIT
Fast Cycle Random Access Memory
with Double Data Rate
■ DESCRIPTION
The Fujitsu MB81N26847A/261647A is a CMOS Fast Cycle Random Access Memory (FCRAM) containing
268,435,456 memory cells accessible in an 8-bit or 16-bit format. The MB81N26847A/261647A features a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81N26847A/261647A is designed to
reduce the complexity of using a standard Dynamic RAM (DRAM) which requires many control signal timing
constraints. The MB81N26847A/261647A uses Double Data Rate (DDR) where data bandwidth is twice of fast
speed compared with regular SDRAMs.
The MB81N26847A/261647A is designed using Fujitsu advanced FCRAM Core Technology.
The MB81N26847A/261647A is ideally suited for Enterprise Servers, Network Systems, Hardware Accelerators,
Buffers, and other applications where large memory density and high effective bandwidth are required and where
a simple interface is needed.
The MB81N26847A/261647A adopts CMOS I/O interface circuitry, 2.5 V Half-strength SSTL-2 interface, which
is capable of extremely fast data transfer of quality.
■ PRODUCT LINE
MB81N26847A (x8) / MB81N261647A (x16)
Parameter
-22
-24
-30
CL = 3
CL = 2
154 MHz max
133 MHz max
22.5 ns max
30 ns min
143 MHz max
125 MHz max
24.0 ns max
32 ns min
133 MHz max
100 MHz max
30.0 ns max
40 ns min
Clock Frequency
Random Access Time
Random Address Cycle Time
DQS Access Time From Clock
Operating Current (IDD1S)
Power Down Current (IDD2P)
+/– 0.85 ns max
170 mA max
2 mA max
+/– 0.9 ns max
165 mA max
2 mA max
+/– 1.0 ns max
150 mA max
2 mA max
Notice: FCRAM is a trademark of Fujitsu Limited, Japan.
(AE1E) 1
MB81N26847A/261647A-22/-24/-30 Preliminary
■ FEATURES
• Double Data Rate
• Variable Write Length Control per Byte
• Distributed Auto-refresh cycle in 7.8 µs
• 2.5 V CMOS I/O comply with SSTL_2
(Half Strength Driver)
• Bi-directional Data Strobe Signal
• Four independent bank operation
• Burst read/write operation
• Programmable burst type, burst length, and
CAS latency
• VDD:
+2.5V Supply ± 0.2V tolerance
• VDDQ: +2.5V Supply ± 0.2V tolerance
■ PACKAGE
Plastic TSOP(II) Package
(FPT-66P-M01)
(Normal Bend)
Package and Ordering Information
– 66-pin plastic (400 mil) TSOP-II, order as MB81N26847A/261647A-××FN
2 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ PIN ASSIGNMENTS AND DESCRIPTIONS #1
Fig. 1 – MB81N26847A PIN ASSIGNMENTS
66-Pin TSOP(II)
(TOP VIEW)
VDD
DQ0
VDDQ
NC2
DQ1
VSSQ
NC2
DQ2
VDDQ
NC2
DQ3
VSSQ
NC2
NC1
VDDQ
NC2
NC1
VDD
VSS
66
65
64
63
62
61
60
1
DQ7
VSSQ
NC2
DQ6
VDDQ
NC2
DQ5
VSSQ
NC2
DQ4
VDDQ
NC2
NC1
VSSQ
DQS
NC1
VREF
VSS
2
3
4
5
6
7
8
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NC1
NC2
A14
NC2
CLK
CLK
PD
A13
FN
CS
NC1
A12
NC1
BA0
BA1
A10
A11
A9
39
38
37
36
35
34
A8
A0
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
Pin Number
Symbol
Function
1, 3, 9, 15, 18, 33, 55, 61
2, 5, 8, 11, 56, 59, 62, 65
6, 12, 34, 48, 52, 58, 64, 66
VDD, VDDQ
Supply Voltage
Data I/O
DQ0 to DQ7
VSS, VSSQ
Ground
• Upper: A0 to A14
• Lower: A0 to A7
21, 22, 28, 29, 30, 31, 32, 35, 36, 37, 38, 39, 40, 41, 42
A0 to A14
Address Input
23
FN
CS
Function Select
Chip Select
24
26, 27
BA1, BA0
PD
Bank Address
Power Down
44
45
CLK
CLK
VREF
Clock Input
46
Clock Input
49
51
Input Reference Voltage
Data Strobe
DQS
NC1
NC2
14, 17, 19, 25, 43, 50, 53
4, 7, 10, 13, 16, 20, 47, 54, 57, 60, 63
No Connection
No Connection (Left Open)
(AE1E) 3
MB81N26847A/261647A-22/-24/-30 Preliminary
■ PIN ASSIGNMENTS AND DESCRIPTIONS #2
Fig. 2 – MB81N261647A PIN ASSIGNMENTS
66-Pin TSOP(II)
(TOP VIEW)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC1
VDDQ
LDQS
NC1
VDD
VSS
66
65
64
63
62
61
60
1
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC1
VSSQ
UDQS
NC1
VREF
VSS
2
3
4
5
6
7
8
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NC1
NC2
A14
NC2
CLK
CLK
PD
A13
FN
CS
NC1
A12
NC1
BA0
BA1
A10
A11
A9
39
38
37
36
35
34
A8
A0
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
Pin Number
Symbol
Function
1, 3, 9, 15, 18, 33, 55, 61
VDD, VDDQ
Supply Voltage
Data I/O
• Upper: DQ8 to DQ15
• Lower: DQ0 to DQ7
2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65
6, 12, 34, 48, 52, 58, 64, 66
DQ0 to DQ15
VSS, VSSQ
Ground
• Upper: A0 to A14
• Lower: A0 to A6
21, 22, 28, 29, 30, 31, 32, 35, 36, 37, 38, 39, 40, 41, 42
A0 to A14
Address Input
23
FN
CS
Function Select
Chip Select
24
26, 27
BA1, BA0
PD
Bank Address
44
Power Down
45
CLK
Clock Input
46
CLK
Clock Input
49
VREF
Input Reference Voltage
Lower Byte Data Strobe
Upper Byte Data Strobe
No Connection
16
LDQS
UDQS
NC1
51
14, 17, 19, 25, 43, 50, 53
20, 47
NC2
No Connection (Left Open)
4 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ BLOCK DIAGRAM #1
Fig. 3 – MB81N26847A BLOCK DIAGRAM
CLK
CLOCK
To each block
CLK
PD
BUFFER
Bank-3
Bank-2
Enable
Bank-1
Bank-0
CS
CONTROL
SIGNAL
LATCH
CS
FN
R/W
COMMAND
DECODER
DRAM
CORE
MODE
REGISTER
(8M x 8)
ADDRESS
23
A0 to A14
BA0,BA1
ADDRESS
BUFFER/
REGISTER
BURST
ACCESS
COUNTER
BURST
ADDRESS
2
I/O
I/O DATA
BUFFER/
REGISTER
&
DQ0
to
DQ7
DQS
DQS
GENERA-
TOR
8
VDD
Clock Buffer
DLL
VREF
VSS / VSSQ
VDDQ, VSSQ
(AE1E) 5
MB81N26847A/261647A-22/-24/-30 Preliminary
■ BLOCK DIAGRAM #2
Fig. 4 – MB81N261647A BLOCK DIAGRAM
CLK
CLOCK
To each block
CLK
PD
BUFFER
Bank-3
Bank-2
Enable
Bank-1
Bank-0
CS
CONTROL
SIGNAL
LATCH
CS
FN
R/W
COMMAND
DECODER
DRAM
CORE
MODE
REGISTER
(4M x 16)
ADDRESS
22
A0 to A14
BA0,BA1
ADDRESS
BUFFER/
REGISTER
BURST
ACCESS
COUNTER
BURST
ADDRESS
DQ0
to
DQ7
2
I/O
I/O DATA
BUFFER/
REGISTER
&
LDQS
DQ8
to
DQ15
DQS
GENERA-
TOR
16
VDD
Clock Buffer
DLL
UDQS
VREF
VSS / VSSQ
VDDQ, VSSQ
6 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ FUNCTION TRUTH TABLE Note *1
COMMAND TRUTH TABLE Note *2, and *3
1st Command
Function
Device Deselect
Notes
Symbol
DESL
RDA
CS
H
FN
X
BA1-0
X
A14-0
X
Read (with Auto-close)
Write (with Auto-close)
*4
*4
L
H
BA
BA
UA
UA
WRA
L
L
2nd Command (1 clock after from RDA or WRA command)
Function
Notes
x16
Symbol
LAL
CS
H
H
L
FN
X
BA1-0 A14-13
A12-11
A10-8
X
A7
A6-0
LA
LA
X
X
X
X
V
V
V
X
L
V
X
X
L
X
LA
X
Lower Address Latch
*5
x8
*6
*6, *7
LAL
X
X
Auto-refresh
REF
X
X
Mode Register Set
MRS
L
X
L
V
V
Notes: *1. L = Logic Low, H = Logic High, X = either L or H, V = Valid (Specified Value), Hi-Z = High Impedance,
UA = Upper Address, LA = Lower Address
*2. All commands are assumed to be valid state transitions.
*3. All inputs for command are latched on the cross point of clock input where CLK goes to High.
*4. RDA and WRA commands should only be issued to the back in standby state.
Refer to Figure 5, STATE DIAGRAM, in page 9.
*5. LAL command is the same command state as DESL and used at both Read and Write operation.
A14 to A11 are only used for Variable Write Length control at Write operation.
Refer to READ and WRITE command table below.
*6. Required at Power-up Initialization.
REF and MRS command should only be issued if all banks are in standby state.
*7. Refer to MODE REGISTER TABLE.
READ COMMAND TABLE
Command
RDA (First)
CS
L
FN
H
BA1
BA1
X
BA0
BA0
X
A14 to A8
A7
UA
X
A6 to A0
UA
UA
X
x16
x8
H
X
LA
LAL (2nd)
H
X
X
X
X
LA
LA
WRITE COMMAND TABLE
Command
CS
L
FN BA1 BA0
A14
A13
A12
UA
A11
A10-8
UA
X
A7
UA
X
A6 to A0
UA
WRA (First)
L
X
X
BA1 BA0
UA
UA
UA
x16
x8
H
X
X
X
X
LVW0 LVW1 UVW0 UVW1
VW0 VW1
LA
LAL (2nd)
H
X
X
X
LA
LA
(AE1E) 7
MB81N26847A/261647A-22/-24/-30 Preliminary
■ FUNCTION TRUTH TABLE (continued)
VW TRUTH TABLE (Effective during Write mode) Note 8
Function
Write All Words
Notes
VW0
L
VW1
X
BL=2
BL=4
Write First One Word
Reserved
H
X
*9
L
L
Write All Words
H
L
Write First Two Words
Write First One Word
L
H
H
H
*8. LVW and UVW controls DQ0-7 and DQ8-15, respectively. Unless specifically noted, VW represents both
LVW and UVW in later descriptions.
*9. Must not be used
PD TRUTH TABLE
Power Down Table
*11
DQ
PD
Current
State
Function
Power Down Entry
Notes Command
CS FN BA1 BA0
A14-0
(n-1) (n)
Standby
PDEN
—
H
L
L
L
H
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Power Down Power Down Continue
Power Down Power Down Exit
PDEX
L
H
L
Active
Self-refresh Entry
*10
REF
—
H
L
Self-refresh Self-refresh Continue
Self-refresh Self-refresh Exit
Read / Write Illegal
L
X
H
X
SELFX
—
L
H
L
H
other than
Illegal
other than
above
H
L
any
above
*10. PD can be brought to Low within tFPDL from REF command for Self-refresh entry.
*11. PD has asynchronous OE function but its AC parameters wil not be guaranteed.
8 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ STATE DIAGRAM
Fig. 5 – STATE DIAGRAM (Simplified for Single Bank Operation)
AUTO
REFRESH
PD = L
MODE
REGISTER
SELF-
REFREESH
SELFX
PD = H
REF
MRS
WRA
RDA
DESL
(Standby)
ACTIVE
ACTIVE
LAL
LAL
PDEN
PDEX
POWER
DOWN
WRITE
READ
SymbolDefinitions:
One Time State
Command Input
Automatic Sequence
(AE1E) 9
MB81N26847A/261647A-22/-24/-30 Preliminary
■ FUNCTIONAL DESCRIPTION
FCRAMTM
The FCRAM is an acronym of Fast Cycle Random Access Memory and provides very fast random cycle time. The
FCRAM also provides low latency and low power consumption than regular DRAMs.
DDR, Double Data Rate Function
The regular SDRAM read and write cycle have only used the rising edge of external clock input. When clock signal
goes to High from Low at the read mode, the read out data will be available at every rising clock edge after the
specified latency up to burst length. The MB81N26847A/261647A DDR FCRAM features a twice of data transfer
rate within the same clock period by transferring data at every rising and falling clock edge.
CLOCK (CLK, CLK)
The MB81N26847A/261647A adopts differential clock scheme. CLK is a master clock and its rising edge is used
to latch all command and address inputs. CLK is a complementary clock input.
The MB81N26847A/261647A implements Delay Locked Loop (DLL) circuit. This internal DLL tracks the signal cross
point between CLK and CLK and generate some clock cycle delay for the output buffer control at Read mode.
The internal DLL circuit requires some Lock-on time for the stable delay time generation. In order to stabilize the
delay, a constant stable clock input for lLOCK period is required during the Power-up initialization and a constant stable
clock input for lLOCK period is also required after Self-refresh exit as specified lLOCK prior to RDA command.
POWER DOWN (PD)
PD is a synchronous input signal and enables low power mode; Power Down and Self-refresh mode.
The Power Down mode is entered when PD is brought to Low while all banks are in idle state and exited when it
return to High.
PD must be brought to Low within the timing between tFPDL(min) and tFPDL(max) to Self-refresh mode.
When PD is bourght to Low after lPDV, FCRAM perform Auto-refresh and enter Power Down mode.
During the Power Down and Self-refresh mode, both CLK and CLK are disabled after specified time.
PD does not have a Clock Suspend function unlike CKE pin of regular SDRAMs, and it is illegal to bring PD into
Low if any read or write operation is being performed. For the detail, refer to STATE DIAGRAM.
It is recommended to maintain PD to be Low until VDD gets in the specified operating range in order to assure the
power-up initialization.
CHIP SELECT (CS) and FUNCTION SELECT (FN)
Unlike regular SDRAMs’ command input signals, the MB81N26847A/261647A has only two control signals; CS
and FN.
Each operation is determined by two consecutive command input. Refer to FUNCTION TRUTH TABLE in page 7.
10 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ FUNCTIONAL DESCRIPTION (continued)
BANK ADDRESS (BA0, BA1)
The MB81N26847A/261647A has four internal banks. Bank selection by BA occurs at Read (RDA) or Write (WRA)
command.
ADDRESS INPUTS (A0 to A14)
Address input selects an arbitrary location of each memory cell matrix within each bank. MB81N26847A/261647A
adopts an address multiplexer in order to reduce the pin count of the address lines. At either RDA or WRA command,
fifteen Upper addresses are initially latched as well as two bank addresses and the remainder of Lower addresses
are then latched by an LAL command. Refer to FUNCTIONAL TRUTH TABLE.
DATA STROBE (DQS)
DQSis a bi-directional signal and used as data strobe. During Read operation, DQS provides the read data strobe
signal that is intended to use input data strobe signal at the receiver circuit of the controller(s). It turns Low before
first data is coming out and toggle High to Low or Low to High till end of burst read. Refer to the timing diagrams.
The CAS Latency is specified to the first Low to High transition of this DQS output.
During the write operation, DQS is used to latch corresponding byte of write data signals. As well as the behavior
of read data strobe, the first rising edge of DQS input latches first input data and following falling edge of DQS signal
latches second input data. This sequence shall be continued till end of burst count. Therefore, DQS must be provided
from the driver circuit of the controller that drives write data.
Note that DQS input signal should not be tristated from High at the end of write mode, and LDQS and UDQS of
MB81N261647 are for Lower Byte Data (DQ0-7) and Upper Byte Data (DQ8-15), respectively.
DATA INPUTS AND OUTPUTS (DQn)
Input data is latched by DQS input signal and written into memory at the clock following the write command input.
Output data is obtained together with DQS output signals at programmed read CAS latency.
The polarity of the output data is identical to that of the input. Data is valid from DQS output signal transition (tQSQ)
till next transition as specified in Data Valid Time from DQS (tQSQV).
READ (RDA) and LOWER ADDRESS LATCH (LAL)
The MB81N26847A/261647A adopts two consecutive command input scheme. The read or write operation is
determined at first RDA or WRA command input from Standby state of the bank to be accessed.
Refer to Figure 5, STATE DIAGRAM in page 9.
The read mode is entered when RDA command is asserted with Bank Address and Upper Address input and LAL
command with Lower Address input must be followed at next clock input. The output data is then valid after
programmed CAS Latency (CL) from a clock at LAL command till end of burst. The read mode is automatically
exited after lRC, Random Cycle Latency.
Refer to FUNCTION TRUTH TABLE.
(AE1E) 11
MB81N26847A/261647A-22/-24/-30 Preliminary
■ FUNCTIONAL DESCRIPTION (continued)
WRITE (WRA), LOWER ADDRESS LATCH (LAL) and VERIABLE WRITE LENGTH
The write mode is entered and exited as the same manner as read mode. The input data store is started at the
rising edge of DQS input from CL-1 till end of burst count. Refer to FUNCTION TRUTH TABLE.
The MB81N26847A/261647A write operation has a feature of “on-the-fly” Variable Write Length (VW) at every LAL
command input following WRA command.
Unlike Data Mask (DM) of regular DDR SDRAM, VW does not provide random data mask capability and the VW
controls the burst counter for the write burst and its burst length is set by a combination of two control addresses,
VW0 and VW1, and programmed Burst Length condition. Refer to VW TRUTH TABLE in page 8.
The data in masked address location remain unchanged.
Note that the DQS signal input must be continued till end of burst length set by Burst Length (BL) at standard mode
register field regardless of actual write burst count set by VW.
During read cycle, the VW field is inactive and does not have any effect on read operation.
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access and MB81N26847A/261647A read and write operations are burst
oriented. The burst mode is implemented by keeping the same addresses and by automatic strobing least significant
addresses in every single clock edge till programmed burst length (BL). Access time from clock of burst mode is
specified as tAC. The internal lower address counter operation is determined by a mode register which defines burst
type (BT) and burst count length(BL) of 2 or 4 bits of boundary.
The burst type can be selected eithersequentialor interleave mode. The sequential modeisanincrementaldecoding
scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address
until reaching the end of boundary address and then wraps round to the least significant address(= 0). The interleave
mode is a scrambled decoding scheme for A0 to A1 of Lower Address depending on the burst length. If the first
access of lower address is even (0), the next address will be odd (1), or vice-versa.
BURST ORDER
Starting Lower Address
Burst Length
Sequential
Interleave
A1
—
—
A0
0
0 – 1
0 – 1
2
1
1 – 0
1 – 0
0
0 – 1 – 2 – 3
1 – 2 – 3 – 0
2 – 3 – 0 – 1
3 – 0 – 1 – 2
0 – 1 – 2 – 3
1 – 0 – 3 – 2
2 – 3 – 0 – 1
3 – 2 – 1 – 0
0
1
1
4
0
1
12 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ FUNCTIONAL DESCRIPTION (continued)
MODE REGISTER SET (MRS)
The mode register provides a variety of different operations as specified above and can be programmed MRS
command following RDA command input if all banks are in standby state. Note that the read operation initiated by
RDA command is cancelled if MRS command is asserted at next clock input from RDA command instead of LAL
command required for read operation.
The MB81N26847A/261647A has two registers; Standard and Extended mode register. The Standard mode register
has four operation fields; Burst Length, Burst Type, CAS Latency, and Test Mode (This Test Mode must not be used.)
The Extended mode register has two fields; DLL Enable and Output Driver Strength.
Refer to MODE REGISTER TABLE in page 15.
These two registers are selected by BA0 at MRS command entry and each field is also set by the address line at
MRS command as well. Once those fields are programmed, the contents will be held until re-programmed by another
MRS command (or part loses power). MRS command should only be issued on condition that all banks are in idle
state and all outputs are in High-Z. The condition of the mode register is undefined after the power-up stage and it
is required to set each field after initialization.
Refer to POWER-UP INITIALIZATION below.
AUTO-REFRESH (REF)
The memory core of MB81N26847A/261647A is the same as conventional DRAM’s capacitor cell and requires
refresh operation to maintain the data written into the cell. The Auto-refresh mode is entered by REF command
following to WRA command. REF command should only be issued under condition that all banks are in idle state
and all outputs are in High-Z. Note that the write operation initiated by WRA command is cancelled if REF command
is asserted at next clock input from WRA command instead of LAL command required for write operation.
The Auto-refresh command should also be issued within every 7.8 µs period. In case of burst refresh operation,
more than 8 consecutive auto-refresh should not be performed within 400ns as average of 8 refresh. In other words,
at least 3.2 µs (8 times 400ns) must be waited for next 8 consecutive refresh operation.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the
refresh operation until cancelled by SELFX.
The Self-refresh mode is entered by applying an REF command (that is following WRA command) in conjunction
with PD = Low (SELF) or PD to bring LOW within the timing between tFPDL (min) and tFPDL (max) from REF command.
However when PD is brought to Low after lPDV, FCRAM perform Auto-refresh and enter Power Down mode. Note
that actual Self-refresh mode will be entered after Auto-refresh operation. The DESL command must be kept for at
least lREFC period and clock input must also be kept for at least lCKD period. Once MB81N26847A/261647A enters
the self-refresh mode, all inputs except for PD can be either logic high or low level state and outputs will be in a
High-Z state. During Self-refresh mode, PD = Low should be maintained. SELF command should only be issued
under condition that all banks are in idle state and all outputs are in High-Z.
SELF-REFRESH EXIT (SELFX)
To exit Self-refresh mode, PD must brought to High for at least 2 clock cycles together with DESL condition.
Refer to Timing Diagram for the detail procedure. It is recommended to issue at least one Auto-refresh command
just after the lREFC period to avoid the violation of refresh period.
WARNING:A stable clock for lLOCK period with a constant duty cycle must be supplied prior to applying any command
other than Auto-refresh command to insure the DLL is locked against the latest device conditions.
(AE1E) 13
MB81N26847A/261647A-22/-24/-30 Preliminary
■ FUNCTIONAL DESCRIPTION (continued)
POWER-UP INITIALIZATION
The MB81N26847A/261647A internal condition at and after power-up will be undefined. Since MB81N26847A/
261647A does not have designated reset function, following procedure must be followed in order to initialize internal
state machine, DLL, and forcing DRAM to be a standby state.
1. Apply VDD before or the same time as VDDQ and attempt to maintain PD to be equal or less than 0.2V before
power supply injection.
2. Apply VDDQ before or same time as VREF.
3. Apply VREF.
4. Start clock after all power supplies reached in a specified operating range and maintain stable condition for
a minimum of 200µs.
5. Maintain stable power and clock, apply DESL command with either A8 = Low or A7 = High and take PD to
High state.
6. Keep CS = High and set either or both BA = Low. (note *1)
7. Set CS = Low with BA[1−0] = A[14−8] = High, A7 = Low for two clocks (MRS command with Reset Address)
8. Set CS = High and maintain same address input for a minimum of 4 clocks.
9. Keep CS = High and change one or more address input within BA[1−0] to A[14−7] and maintain them for a minimum
of 4 clocks.
10. Set Extended mode register to enable DLL. (note *2)
11. Set Standard mode register. (note *2)
12. Issue Auto-refresh commands twice or more. (note *2)
13. Issue Write command to all four banks after minimum lLOCK clocks from Extended mode register programming.
(note *3)
14. Ready for normal operation.
Notes: *1. The reset/initialization after Power-up can be also performed if the procedure from step 6 to step 12
are issued. Refer to RESET CONDITION below.
*2. These steps can be issued in random order. For example, Auto-refresh command can be issued prior
to Extended mode register programming of step 10.
*3. Order of bank address can be arbitrarily but must be write to all banks before normal operation.
RESET CONDITION
Clock
n-13:1 *1
n
Command
DESL
RDA
CS
H
L
FN
X
BA1
X or L
X
BA0
L or X
X
A14-9
A8
L or X
X
A7
A6-0
X
X
X or H
H
X
X
H
X
L
L
X
n+1
MRS
L
H
H
H
X
n+2:5
n+6
DESL
DESL
DESL
H
H
H
X
H
H
H
H
X
X
Note *2
Note *3
X
n+7:10
X
X
Notes: *1. DESL condition must be maintained at least 12 clocks.
*2. At least one address bit must be flipped from previous state.
*3. Same address input conditions at n+6 state must be maintained at least 4 clocks.
14 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ MODE REGISTER TABLE
STANDARD MODE REGISTER
ADDRESS
BA1 BA0 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
STANDARD MODE
REGISTER
0*1 0*1
0
TM
CL
BT
BL
A2
A1
A0
Burst Length (BL)
RESERVED
2
A6
A5
0
A4
X
0
CAS Latency (CL)
0
0
0
1
RESERVED *2
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
1
2
4
1
1
3
RESERVED
RESERVED
X
X
RESERVED
A3
Burst Type (BT)
A7
0
Test Mode (TM)
0
1
Sequential (Wrap round, Binary up)
Interleave (Wrap round)
Regular Mode (Default)
1
Test Mode (supplier specific mode) *3
EXTENDED MODE REGISTER *1
ADDRESS
BA1 BA0 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
EXTENDED MODE
REGISTER
0*1 1*1
RESERVED *4
OD DE
A1
0
Output Driver Strength (OD)
A0
DLL Enable (DE)
Standard Strength *5
RESERVED *5
DLL Enable *6
0
1
1
DLL Disable
Notes: *1. A combination of BA1 = BA0 = 0 (Low) selects Standard mode register,
a combination of BA1 = 0 and BA0 = 1 (High) selects Extended mode register, and
a combination of BA1 = BA0 = 1 can only be used at RESET operation.
*2. The RESERVED field in Standard mode register must not be used.
*3. Must not be used. A7 = 1 should only be used at power-up initialization and RESET.
*4. The RESERVED field in Extended mode register must be set as 0.
*5. A1 of Extended mode register must always be set at 0.
*6. Must be set at power-up initialization.
(AE1E) 15
MB81N26847A/261647A-22/-24/-30 Preliminary
■ ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter
Supply Voltage
Symbol
VDD, VDDQ
VREF
Value
–0.3 to +3.6
–0.3 to +3.6
–0.3 to VDDQ + 0.3
–0.3 to VDDQ + 0.3
±50
Unit
V
Input Reference Voltage
Input Voltage
V
VIN
V
Output Voltage
VOUT
V
Output Short Circuit Current
Storage Temperature
Operating Temperature
Soldering Temperature(10s)
IOUT
mA
°C
°C
°C
TSTG
–55 to +150
0 to +70
TOPR
TSOLDER
260
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter
Notes Symbol
Min.
2.3
Typ.
2.5
Max.
2.7
Unit
V
VDD
Supply Voltage
VDDQ
2.3
VDD
VDD
V
Input Reference Voltage
*3
*5
VREF
VDDQ/2 * 96%
VDDQ/2 VDDQ/2 * 104%
VDDQ + 0.2
V
Single Ended DC Input High Level
VIH(DC)
VREF + 0.2
V
Single Ended DC Input Low Level
Single Ended AC Input High Level
Single Ended AC Input Low Level
Differential Clock DC Input Level
*5
*6
*6
VIL(DC)
VIH(AC)
VIL(AC)
VICK(DC)
–0.1
VREF + 0.35
–0.1
—
—
—
—
VREF – 0.2
VDDQ + 0.2
VREF – 0.35
VDDQ + 0.1
V
V
V
V
–0.1
Differential DC Input
Differential Level
*7
*7
VID(DC)
VID(AC)
VX(AC)
0.4
0.7
—
—
—
VDDQ + 0.2
VDDQ + 0.2
VDDQ/2 + 0.2
V
V
V
Differential AC Input
Differential Level
Differential AC Input Cross
Point Level
*8
*4
VDDQ/2 – 0.2
Differential AC Input Signal Offset Level
Ambient Temperature
VISO(AC)
TA
VDDQ/2 – 0.2
0
—
—
VDDQ/2 + 0.2
70
V
°C
16 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ RECOMMENDED OPERATING CONDITIONS(Continued)
Notes: *1. Overshoot greater than the VIH(AC) maximum limit is VDD + 0.9V for pulse width < 5 ns. Refer to Figure 6.
*2. Undershoot greater than the VIL(AC) minimum limit is VSS – 0.9V for pulse width < 5 ns. Refer to Figure 7.
*3. VREF is expected to track variations in the DC level of VDDQ of the transmitting device.
Peak-to-Peak noise level on VREF may not exceed +/- 2% of the supplied DC value.
*4. VISO means {VICK(CLK) + VICK(CLK)} / 2. Refer to Figure 8.
*5. VIH(DC) and VIL(DC) are levels to maintain the current logic state.
*6. VIN(AC) and VIL(AC) are levels to change to the new logic state.
*7. VID is magnitude of the difference between CLK input level and CLK input level.
*8. The value of VX(AC) is expected to equal VDDQ/2 of the transmitting device.
*9. In case of external termination, VTT (Termination Voltage) must be within a range of VREF(DC) +/- 0.04V.
Overshoot and Undershoot Definition
Fig. 6 – Overshoot Definition
Fig. 7 – Undershoot Definition
VDD + 0.9V
VIH
Pulse width ≤ 5 ns
50% of pulse amplitude
VIL(max)
VIH
VIL
VIH(min)
50% of pulse amplitude
Pulse width
≤ 5 ns
VIL
-0.9V
Differential Input Signal Definition
Fig. 8 – Differential Input Signal Offset Voltage (For Clock Input)
CLK
VX
VID(AC)
CLK
VICK (CLK)
VICK (CLK)
VSS
|VID(AC)|
0V Differential
VISO
VSS
VISO (max.)
VISO (min.)
(AE1E) 17
MB81N26847A/261647A-22/-24/-30 Preliminary
■ CAPACITANCE
(TA = 25°C, f = 1 MHz)
Parameter
Clock Pin Capacitance
Symbol
CIN1
Min.
2.5
2.5
4.0
—
Typ.
—
Max.
Unit
pF
4.0
4.0
6.0
1.5
6.0
Input Pin Capacitance
I/O Pin Capacitance
NC1 Pin Capacitance
NC2 Pin Capacitance *
CIN2
—
pF
CI/O
—
pF
CNC1
CNC2
—
pF
4.0
—
pF
Note:*The NC2 pins have additional capacitance for adjustment of adjacent pin capacitance. The NC2 pins have
power and Ground clamp.
18 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
Note *1,*2
Value
Parameter
Symbol
Condition
Unit
Min.
Max.
VDDQ = 2.3V for min, 2.7V for max
VOH = VDDQ-0.4V
Output Source Current
IOH
IOL
ILI
-10.0
—
mA
mA
µA
VDDQ = 2.3V for min, 2.7V for max
VOL = +0.4V
Output Sink Current
10.0
-5
—
5
0 V < VIN < VDDQ;
All other pins not under test = 0 V
Input Leakage Current (any input)
0 V < VOUT < VDDQ;
Data out disabled
Output Leakage Current
VREF Current
ILO
-5
-5
—
5
5
µA
µA
IREF
tCK = min, lRC = min, Burst Length = 4,
One bank active, Read/Write
command cycling,
-22
170
Operating Current
(Average Power Supply
-24
-30
-22
-24
-30
IDD1S
Address change up to 2 times during
minimum lRC,
0 V < VIN < VIL(AC) (max),
VIH(AC) (min) < VIN < VDDQ
—
—
—
—
—
165
150
45
mA
mA
Current)
*3,*4
PD = VIH, tCK = min
All banks idle,
DESL commands only, Other input
signals are changed one time during
four clock inputs,
0 V < VIN < VIL(AC) (max),
VIH(AC) (min) < VIN < VDDQ
Standby Current
*3
IDD2N
40
35
PD = VIL(AC), tCK = min
All banks idle,
0 V < VIN < VDDQ
Power Down Current
IDD2P
IDD5
IDD6
—
2
mA
mA
mA
*3
Auto-refresh;
-22
-24
-30
—
—
—
65
60
55
tCK = min, lREFC = min, tREFI = min,
Address change up to 2 times during
minimum lREFC,
0 V < VIN < VIL(AC) (max),
VIH(AC) (min) < VIN < VDDQ
Auto-refresh Current
(Average Power Supply
Current)
*3
Self-refresh;
PD = 0.2V,
0 V < VIN < VDDQ
Self-refresh Current
(Average Power Supply Current)
—
3
Notes: *1. All voltages referenced to VSS.
*2. DC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
*3. IDD depends on the output termination or load conditions, clock cycle rate, and number of address and
command change within certain period.
*4. The specified values are obtained with the output open.
(AE1E) 19
MB81N26847A/261647A-22/-24/-30 Preliminary
■ AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.) Note *1,*2,*3
AC PARAMETERS
− 22
Max.
− 24
Max.
− 30
Max.
Parameter
Notes
Symbol
Unit
Min.
6.5
Min.
7.0
Min.
7.5
CL = 3
CL = 2
10.0
10.0
10.0
10.0
10.0
10.5
ns
ns
Clock Period
tCK
7.5
8.0
10.0
Input Setup Time (Except for
LDQS/UDQS and Data)
*4
tIS
1.0
1.0
2.2
—
—
—
1.2
1.2
2.6
—
—
—
1.6
1.6
3.4
—
—
—
ns
ns
ns
Input Hold Time (Except for
LDQS/UDQS and Data)
*4
*4
tIH
Command and Address Input
Pulse Width (each device)
tIPW
Data Input Setup Time
Data Input Hold Time
*5
*5
tDS
tDH
0.6
0.6
—
—
0.6
0.6
1.9
0
—
—
0.8
0.8
2.3
0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Input Pulse Width
DQS First Input Setup Time
*5
tDIPW
1.9
—
—
—
*4,*6
tDSPRES
CL = 3
0
—
—
—
1.5
—
1.5
1.6
1.5
1.6
-0.9
-0.56
-0.9
-0.9
-0.9
—
—
1.6
2.0
1.6
2.0
-1.0
-0.64
-1.0
-1.0
-1.0
—
—
DQS Input Falling Edge to
Clock Setup Time
*5 tDSS
CL = 2
CL = 3
CL = 2
1.5
—
—
—
1.5
—
—
—
DQS Last Low Input
(Postamble) Hold Time
*4 tDSPSTH
*4,*7
1.5
—
—
—
DQS Access Time from CLK
Data Output skew from DQS
Data Access Time from CLK
Data Output in Low-Z
tCKQS
tQSQ
tAC
tLZ
tOH
tHZ
-0.85
-0.52
-0.85
-0.85
-0.85
—
0.85
0.52
0.85
—
0.9
0.56
0.9
—
1.0
0.64
1.0
—
*5
*4,*7
*4,*7,*8
*4,*7
Data Output Valid Time
Data Output in High-Z
0.85
0.85
0.9
0.9
1.0
1.0
*4,*7,*9
DQS Output in Low-Z
(Preamble Setup Time)
*4,*7,*8
*4,*7,*9
tQSLZ
-0.85
—
-0.9
—
-1.0
—
ns
DQS Output in High-Z
tQSHZ
-0.85
0
0.85
—
-0.9
0
0.9
—
-1.0
0
1.0
—
ns
ns
Last Output to PD High Hold Time
PD Low Input Window for
tQPDH
*4,*10
tFPDL
-0.5*tCK 10.0 -0.5*tCK 10.0 -0.5*tCK 10.0
ns
Self-refresh Entry
Power Down Exit Time
Auto-refresh Interval
Pause Time after Power-up
Input Transition Time
*4
*11
*12
*13
tPDEX
tREFI
tPAUSE
tT
2.0
0.4
200
0.2
—
7.8
—
2.0
0.4
200
0.2
—
7.8
—
3.0
0.4
200
0.2
—
7.8
—
ns
µs
µs
ns
1.0
1.0
1.0
20 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ AC CHARACTERISTICS (continued)
AC PARAMETERS (FREQUENCY DEPENDANT) Note *10
Parameter
Clock High Time
Notes
*4
Symbol
tCH
Min.
Max.
—
Unit
ns
0.45 * tCK
0.45 * tCK
0.75 * tCK
Clock Low Time
*4
tCL
—
ns
DQS Low to High Setup Time
*4,*14
tDQSS
1.25 * tCK
ns
DQS First Low Input Pulse Width
(Input Preamble Pulse Width)
*6
*4,*6
*5
tDSPRE
tDSPREH
tDSP
0.4 * tCK
0.25 * tCK
0.45 * tCK
0.45 * tCK
– 0.25 * tCK
—
—
ns
ns
ns
ns
ns
DQS First Low Input Hold Time
(Input Preamble Hold Time)
DQS High or Low Input Pulse Width
[Not applicable to last Postamble]
0.55 * tCK
—
DQS Last Low Input (Postamble)
Pulse Width
*5,*15
tDSPST
tDSSK
LDQS to UDQS Input Skew
[Applicable to MB81N261647A only]
*5
*4
0.25 * tCK
DQS Preamble Pulse Width
DQS Pulse Width
tQSPRE
tQSP
0.9 * tCK – 0.2
0.4 * tCK – 0.2
0.4 * tCK – 0.4
1.1 * tCK + 0.2
ns
ns
ns
—
—
Data Output Valid Time from DQS
tQSQV
(AE1E) 21
MB81N26847A/261647A-22/-24/-30 Preliminary
■ AC CHARACTERISTICS (continued)
LATENCY
(The latency values on these parameters are fixed regardless of clock period.)
Parameter
Note
Symbol
CL = 3
BL = 2
BL = 4
Unit
5
4
5
4
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Random Read/Write Cycle Time (minimum)
[Applicable to same bank]
lRC
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
1
1
RDA or WRA to LAL Command Input Delay
[Applicable to same bank]
lRCD
lRAS
lRBD
lRWD
lWRD
1
1
4
4
LAL to RDA or WRA Command Input Delay (minimum)
[Applicable to same bank]
3
3
2
2
Random Bank Access Delay (minimum)
[Applicable to other bank]
2
2
2
3
LAL following RDA to WRA Delay Time (minimum)
[Applicable to other bank]
2
3
1
1
LAL following WRA to RDA Delay Time (minimum)
[Applicable to other bank]
*15
1
1
PD Low to Input Inactive
PD High to Input Active
lPD
lPDA
1
1
1
1
CL = 3
4
4
Power Down mode valid from REF command
Auto-refresh Cycle Time (minimum)
lPDV
lREFC
lRSC
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
3
3
15
12
5
15
12
5
Mode Register Set Cycle Time (minimum)
*16
4
4
REF Command to Clock Input Disable
at Self-refresh Entry (minimum)
lCKD
16
16
tCK
tCK < 8ns
200
300
200
300
tCK
tCK
DLL Lock-on Time (Applicable to RDA command)
lLOCK
tCK < 10.5 ns
22 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ AC CHARACTERISTICS (continued)
Notes: *1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure and stable
clock input with constant clock period and with 50% duty cycle.
*2. Access Times assume input slew rate of 1ns/volt between VREF+0.35V to VREF-0.35V, where VREF is
VDDQ/2, with parallel termination load conditions. Refer to AC TEST LOAD CIRCUIT in page 23.
*3. VREF = 1.25V is a typical reference level for measuring timing of input signals.
Transition times are measured between VIH (min) and VIL (max) unless otherwise noted.
Refer to AC TEST CONDITIONS in page 23.
*4. This parameter is measured from the cross point of CLK and CLK input.
*5. This parameter is measured from signal transition point of DQS input crossing VREF level.
*6. Not applicable if consecutive write operation within lRBD (min) is performed.
*7. This parameter depends on the clock jitters.
*8. Low-Z (Low Impedance State) is specified and measured at VDDQ / 2 +/- 200mV from steady state.
*9. High-Z is specified where output buffer is no longer driven.
*10. If the result of nominal calculation with regard to tCK contains more than one decimal place, the result
should be rounded up to the nearest decimal place.
e.g., if tCK=6.5ns and formula is 0.5*tCK, the result is rounded up to 3.3ns.
*11. The tREFI (max) is applicable for equally distributed refresh method.
The tREFI (min) is applicable for burst refresh method. In such case, more than 8 consecutive auto-
refresh operation should not be performed within 400ns as average of 8 refresh. In other words, at least
3.2 µs (8 times 400ns) must be waited for next 8 consecutive refresh operation.
*12. Specified when the clock input is started on the condition of the stable supply voltage
*13. Defined as the transition time between VIH(AC) (min) and VIL(AC) (max).
*14. More than 2 signal edge of DQS should not be input within 1 clock (tCK) cycle.
*15. The maximum value is not a device limit and is a reference value when minimum lWRD at BL=4 is applied.
*16. The lRSC is 5 clock cycles before CL programming during power-up sequence.
(AE1E) 23
MB81N26847A/261647A-22/-24/-30 Preliminary
■ AC CHARACTERISTICS (continued)
Fig. 9 – AC TEST LOAD CIRCUIT
VTT
Output
measurement
point
RT = 50 Ω
Output
Z0 = 50 Ω
VDDQ
VDDQ
VREF
VREF
0.5 × VDDQ
CL = 30 pF
Device
Under Test
VSS
Note: AC characteristics are measured in this condition. This load circuit is not applicable for DC Test.
AC TEST CONDITIONS
Parameters
Symbol
VIH
Value
VREF + 0.35
VREF – 0.35
VDDQ/2
VDDQ/2
VREF
Unit
V
Input High Level
Input Low Level
VIL
V
Input Reference Level
Output Timing Measurement Reference Level
Termination Voltage
VREF
VOTR
VTT
V
V
V
Input Peak to Peak Swing Level
Differential Input Level
Differential Input Reference Level
Input Slew Rate
VSWING
VID(AC)
Vr
1.0
V
1.5
V
Vx(AC)
V
SLEW
1.0
V/ns
Fig. 10 – AC TEST TIMING SETUP
VDDQ
VIH (AC) min.
VREF
VSWING
VIL (AC) max.
VSS
∆T
∆T
Note: SLEW is measured between VREF+0.35V to VREF–0.35V in a ∆T period.
24 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ AC CHARACTERISTICS (continued)
Fig. 11 – AC TIMING of CLK & CLK
tCK
tCL
tCH
CLK
CLK
VX
VID(AC)
Note: Reference level for AC timings of clock are the cross point of CLK and CLK as specified in VX.
Fig. 12 – AC TIMING of Command Input & Address
tCK
CLK
CLK
VX(AC)
tIS
tIH
tIS
tIH
Input
VIH (AC)
VIL (AC)
(Controls &
Addresses)
Input Valid
Input Valid
VREF
tIPW
tIPW
Note: The cross point of CLK and CLK (VX) is used for command and address input.
The reference level of single ended input is VREF.
Fig. 13 – AC TIMING of Write Mode (Data Strobe and Write Data Input)
tCK
tCK
CLK
CLK
tIS
tIH
VIH (AC)
VIL (AC)
Input
(Controls &
Addresses)
tDSS
tDSP
tDSS
LAL (after WRA)
VREF
tDQSS
tDSP
tDQSS
tDSPSTH
tDSPST
tDSPREH
tDSPRE
tDSP
tDSPRES
VREF
DQS Input
(@BL=4)
VREF
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Data Input
Input Valid
Input Valid
Input Valid
Input Valid
tDIPW
tDIPW
tDIPW
tDIPW
Note: The above timing on DQS and Data input assume CL=2 and BL=4.
The definition point of tDQSS, tDSPRES and tDSPREH at CL=3 shift one clock later from above example.
(AE1E) 25
MB81N26847A/261647A-22/-24/-30 Preliminary
■ AC CHARACTERISTICS (continued)
Fig. 14 – AC TIMING of Write Mode (Data Strobe and Write Data Input)
tCK
tCK
CLK
CLK
tIS
tIH
VIH (AC)
VIL (AC)
Input
(Controls &
Addresses)
LAL (after WRA)
VREF
tDSS
tDSPSTH
tDSPST
tDQSS
tDSPREH
tDSPRE
tDSP
tDSPRES
VREF
LDQS Input
(@BL=2)
VREF
tDS
tDH
tDS
tDH
Data Input
(DQ0 to DQ7)
Input Valid
Input Valid
tDIPW
tDIPW
tDSS
tDSSK
tDSSK
tDSP
tDQSS
tDSPSTH
tDSPST
tDSPREH
tDSPRES
VREF
UDQS Input
(@BL=2)
tDSPRE
VREF
tDS
tDH
tDS
tDH
Data Input
(DQ8 to DQ15)
Input Valid
Input Valid
tDIPW
tDIPW
Note: The above timing on DQS and Data input assume CL=2 and BL=2.
The definition point of tDQSS, tDSPRES and tDSPREH at CL=3 shift one clock later from above example.
26 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ AC CHARACTERISTICS (continued)
Fig. 15 – AC TIMING of Read Mode (Clock to DQS Output Delay Time)
tCK
tCK
CLK
CLK
VX
tCKQS
(min)
tCKQS
(min)
tCKQS
(min)
tCKQS
(min)
tQSLZ
(min)
tQSHZ
tQSPRE
tCKQS
tCKQS
tCKQS
tCKQS
(max)
(max)
(max)
(max)
DQS Output
(@BL=4)
VTT
VTT - 0.2 V
tQSP
tQSP
tQSP
Note: DQS Access time (tQSCK) is measured from the cross point of clock (VX) and VREF.
The tQSHZ specification is defined at where output buffer is no longer driven.
The starting point of DQS in Low-Z (tQSHZ specification) is CL-1.
Fig. 16 – AC TIMING of Read Mode (Clock to Data Output Delay Time)
tCK
tCK
CLK
CLK
VX
tAC
tOH
(min)
tAC
tAC
tAC
(tmLiZn)
(min)
(min)
(min)
(min)
tOH
(max)
tAC
tAC
tAC
tAC
(max)
(max)
(max)
(max)
tHZ
DQ Data
Output
(@BL=4)
VTT + 0.2 V
VTT - 0.2 V
VTT
(max)
Note: Access time (tAC) is measured from the cross point of clock (VX) and VREF.
The tHZ specification is defined at where output buffer is no longer driven.
Fig. 17 – AC TIMING of Read Mode (DQS Output to Data Output Delay Time)
DQS Output
(@BL=4)
VREF
tQSQ
(min)
tQSQ
(min)
tQSQ
(min)
tQSQ
(min)
tQSQ
(max)
tQSQ
(max)
tQSQ
(max)
tQSQ
(max)
DQ Data
Output
(@BL=4)
VTT + 0.2 V
VTT - 0.2 V
VTT
tQSQV
tQSQV
tQSQV
tQSQV
Note: DQS Output Edge to Data Output Edge Skew Time (tQSQ) is measured from VREF to VREF.
Data Output Valid Time from DQS (tQSQV) is specified from valid DQS transition crossing VREF to end of data valid.
(AE1E) 27
MB81N26847A/261647A-22/-24/-30 Preliminary
■ AC CHARACTERISTICS (continued)
Fig. 18 – AC TIMING of Power Down
lRC (min), tREFI (max)
PD
VREF
tIH
tPDEX
lPDA
tIS
lPD
CLK
CLK
RDA /
WRA
Command
DQ
DESL
DESL
Don’t Care
DESL
DESL
tQPDH
Q
Q
Last Output
Note: The above timing is for Power Down mode as a reference of PD input condition.
The setup and hold time of PD High to Low input must comply with tIS and tIH condition for both Power
Down and Self-refresh entry.
When is brought to High from Low, tPDEX is applied as a setup time against clock input.
Fig. 19 – AC TIMING of Pulse Width and Latency
CLK
CLK
VX
VX
tREFI, tPAUSE, lxxx (all latencies)
Input
(Controls &
Addresses)
Command
Command
Note: All parameters listed above are measured from the cross point at rising edge of the CLK and falling
edge of CLK of one command input to next command input.
28 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS
TIMING DIAGRAM – 1 : READ @ CL=3
(Single Bank Access)
CLK
CLK
lRC = 5 clocks (minimum) *1
DESL
RDA
LAL
RDA
LAL
DESL
Command
lRCD *2
lRAS
DQ
(Output)
@BL = 4
Hi-Z
Hi-Z
Hi-Z
Q1 Q2 Q3 Q4
Q1 Q2
CL=3
CL=3
DQS
(Output)
@BL = 4
Hi-Z
DQ
(Output)
@BL = 2
Hi-Z
Hi-Z
Hi-Z
Q1 Q2
Q1 Q2
CL=3
CL=3
DQS
(Output)
@BL = 2
Hi-Z
Notes: *1 The random cycle time lRC is 5 clocks regardless of burst length when CL =3.
*2 The lRCD must be 1 clock.
(AE1E) 29
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 2 : READ @ CL=2
(Single Bank Access)
CLK
CLK
lRC = 4 clocks (minimum) *1
DESL
RDA
LAL
RDA
LAL
DESL
Command
lRCD *2
lRAS
DQ
(Output)
@BL = 4
Hi-Z
Hi-Z
Hi-Z
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
CL=2
CL=2
DQS
(Output)
@BL = 4
Hi-Z
DQ
(Output)
@BL = 2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Q1 Q2
Q1 Q2
CL=2
CL=2
DQS
(Output)
@BL = 2
Notes: *1 The random cycle time lRC is 4 clocks regardless of burst length when CL=2.
*2 The lRCD must be 1 clock.
30 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 3 : WRITE @ CL=3
(Single Bank Access)
CLK
CLK
lRC = 5 clocks (minimum) *1
DESL
WRA
LAL
WRA
LAL
DESL
Command
lRCD *2
lRAS
DQ
(Input)
Don’t Care
Don’t Care
D1 D2 D3 D4
D1 D2 D3 D4
@BL = 4
WL=2 *3
WL=2
Invalid
DQS
(Input)
Invalid
@BL = 4
DQ
(Input)
@BL = 2
Don’t Care
Invalid
Don’t Care
WL=2
Don’t Care
D1 D2
D1 D2
WL=2
DQS
(Input)
Invalid
@BL = 2
Notes: *1 The random cycle time lRC is 5 clocks regardless of burst length when CL=3.
*2 The lRCD must be 1 clock.
*3 The Write Data Latency (WL) is 2 clocks typical when CL=3.
(AE1E) 31
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 4 : WRITE @ CL=2
(Single Bank Access)
CLK
CLK
lRC = 4 clocks (minimum) *1
DESL
WRA
LAL
WRA
LAL
DESL
Command
lRCD *2
lRAS
DQ
(Input)
Don’t Care
Don’t Care
D1 D2 D3 D4
D1 D2 D3 D4
@BL = 4
WL=1 *3
WL=1
DQS
(Input)
Invalid
Invalid
@BL = 4
DQ
(Input)
@BL = 2
Don’t Care
Invalid
Don’t Care
Don’t Care
D1 D2
D1 D2
WL=1
WL=1
DQS
(Input)
Invalid
@BL = 2
Notes: *1 The random cycle time lRC is 4 clocks regardless of burst length when CL=2.
*2 The lRCD must be 1 clock.
*3 The Write Data Latency (WL) is 1 clock typical when CL=2.
32 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 5 : READ and WRITE @ CL=3
(Single Bank Access)
CLK
CLK
lRC = 5 clocks (minimum) *1
DESL
lRC = 5 clocks (minimum)
DESL
RDA
LAL
WRA
LAL
RDA
Command
lRCD *2
lRAS
Hi-Z
Hi-Z
Hi-Z
DQ
@BL = 4
Q1 Q2 Q3 Q4
D1 D2 D3 D4
CL=3
WL=2
Hi-Z
DQS
@BL = 4
Low
Input
Hi-Z
Hi-Z
Hi-Z
DQ
@BL = 2
Q1 Q2
D1 D2
CL=3
WL=2
Hi-Z
High-Z
DQS
@BL = 2
Low
Input
Notes: *1 The random cycle time lRC is 5 clocks regardless of burst length when CL =3.
*2 The lRCD must be 1 clock.
(AE1E) 33
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 6 : READ and WRITE @ CL=2
(Single Bank Access)
CLK
CLK
lRC = 4 clocks (minimum) *1
lRC = 4 clocks (minimum)
DESL
RDA
LAL
WRA
LAL
DESL
RDA
LAL
Command
lRCD *2
lRAS
Hi-Z
Hi-Z
DQ
@BL = 4
Q1 Q2 Q3 Q4
D1 D2 D3 D4
CL=2
WL=1
High-Z
DQS
@BL = 4
Low
Input
Hi-Z
Hi-Z
Hi-Z
DQ
@BL = 2
Q1 Q2
D1 D2
CL=2
WL=1
Hi-Z
High-Z
DQS
@BL = 2
Low
Input
Notes: *1 The random cycle time lRC is 4 clocks regardless of burst length when CL=2.
*2 The lRCD must be 1 clock.
34 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 7 : READ @ CL=3
(Multiple Bank Access)
CLK
CLK
lRBD = 2 clocks
(minimum) *1
lRC *2
DESL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
Command
lRCD *2
Bank
Bank 3
X
Bank 0
X
X
Bank 1
X
Bank 0
X
Bank 2
Address
Bank 3 Data
Bank 0 Data
Bank 1 Data
Q1 Q2
DQ
(Output)
@BL = 4
Hi-Z
Hi-Z
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CL=3
DQS
(Output)
@BL = 4
Bank 3 Data
Q1 Q2
Bank 0 Data
Q1 Q2
Bank 1 Data
Q1 Q2
DQ
(Output)
@BL = 2
Hi-Z
Hi-Z
CL=3
DQS
(Output)
@BL = 2
Notes: *1 The random bank access delay lRBD is 2 clocks minimum.
*2 Both lRC and lRCD must be satisfied for the same bank.
(AE1E) 35
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 8 : READ @ CL=2
(Multiple Bank Access)
CLK
CLK
lRBD = 2 clocks
(minimum) *1
lRC *2
RDA
RDA
LAL
RDA
LAL
RDA
LAL
LAL
RDA
LAL
DESL
Command
lRCD *2
Bank
Bank 3
X
Bank 0
X
Bank 1
X
Bank 0
X
X
Bank 2
Address
Bank 3 Data
Bank 0 Data
Bank 1 Data
Bank 0 Data
DQ
(Output)
@BL = 4
Hi-Z
Hi-Z
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
CL=2
DQS
(Output)
@BL = 4
Bank 3 Data
Q1 Q2
Bank 0 Data
Q1 Q2
Bank 1 Data
Q1 Q2
Bank 0 Data
Q1 Q2
DQ
(Output)
@BL = 2
Hi-Z
Hi-Z
CL=2
DQS
(Output)
@BL = 2
Notes: *1 The random bank access delay lRBD is 2 clocks minimum.
*2 Both lRC and lRCD must be satisfied for the same bank.
36 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 9 : WRITE @ CL=3
(Multiple Bank Access)
CLK
CLK
lRBD = 2 clocks
lRC *2
(minimum) *1
WRA
WRA
Bank 3
LAL
WRA
LAL
DESL
WRA
LAL
WRA
LAL
DESL
Command
lRCD *2
Bank
Address
X
Bank 0
X
Bank 1
X
Bank 0
X
X
Bank 2
X
Bank 3 Data
Bank 0 Data
Bank 1 Data
DQ
(Input)
@BL = 4
Don’t Care
Invalid
D1 D2 D3 D4 D1 D2 D3 D4
D1 D2 D3 D4 D1
WL=2
DQS
(Input)
@BL = 4
Bank 3 Data
D1 D2
Bank 0 Data
D1 D2
Bank 1 Data
D1 D2
Bank 0 Data
DQ
(Input)
@BL = 2
Don’t Care
Invalid
D1
WL=2
DQS
(Input)
@BL = 2
Notes: *1 The random bank access delay lRBD is 2 clocks minimum.
*2 Both lRC and lRCD must be satisfied for the same bank.
(AE1E) 37
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 10 : WRITE @ CL=2
(Multiple Bank Access)
CLK
CLK
lRBD = 2 clocks
(minimum) *1
lRC *2
WRA
WRA
LAL
WRA
Bank 3
LAL
WRA
LAL
LAL
WRA
LAL
DESL
Command
lRCD *2
Bank
Address
X
Bank 0
X
Bank 1
X
Bank 0
X
X
Bank 2
Bank 3 Data
Bank 0 Data
Bank 1 Data
Bank 0 Data
DQ
(Input)
@BL = 4
Don’t Care
Invalid
D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4
WL=1
DQS
(Input)
@BL = 4
Bank 3 Data
Bank 0 Data
D1 D2
Bank 1 Data
D1 D2
Bank 0 Data
D1 D2
DQ
(Input)
@BL = 2
Don’t Care
Invalid
D1 D2
WL=1
DQS
(Input)
@BL = 2
Notes: *1 The random bank access delay lRBD is 2 clocks minimum.
*2 Both lRC and lRCD must be satisfied for the same bank.
38 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 11 : READ and WRITE @ BL=4
(Multiple Bank Access)
CLK
CLK
lRCD
lRCD
lRCD
DESL
RDA
LAL
WRA
LAL
RDA
LAL
DESL
Command
lRWD = 3 clocks (minimum) *1
lWRD = 1 clocks (minimum) *2
Bank 2
Bank
Address
X
Bank 0
X
Bank 1
X
X (Don’t Care)
X (Don’t Care)
Hi-Z
Hi-Z
DQ
@CL = 3
Q1 Q2 Q3 Q4
D1 D2 D3 D4
CL=3
WL=2
CL=3
DQS
@CL = 3
Low Input
after Hi-Z
*2, *3
Hi-Z
Hi-Z
DQ
@CL = 2
Q1 Q2
Q1 Q2
D3 D4
D1 D2 D3 D4
CL=2
WL=1
CL=2
DQS
@CL = 2
Low Input
after Hi-Z
*2, *3
Notes: *1 The read to write delay for different bank, lRWD is 3 clocks minimum at BL=4 regardless of CL.
*2 The lWRD can be 1 clock if maximum tDSPST can be met.
*3 Low to Low input and output conflict is allowed if maximum tDSPST can be met.
(AE1E) 39
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 12 : READ and WRITE @ BL=2
(Multiple Bank Access)
CLK
CLK
lRCD
lRCD
lRCD
RDA
LAL
DESL
WRA
LAL
RDA
LAL
DESL
Command
lRWD = 2 clocks (minimum) *1
lWRD = 1 clocks (minimum)
Bank
Address
X
Bank 2
Bank 0
X
Bank 1
X
X
X (Don’t Care)
Hi-Z
Hi-Z
DQ
@CL = 3
Q1 Q2
Q1 Q2
D1 D2
CL=3
WL=2
CL=3
DQS
@CL = 3
Low Input
after Hi-Z
Hi-Z
Hi-Z
DQ
@CL = 2
Q1 Q2
Q1 Q2
D1 D2
CL=2
WL=1
CL=2
DQS
@CL = 2
Low Input
after Hi-Z
Notes: *1 The read to write delay for different bank, lRWD is 2 clocks minimum at BL=2 regardless of CL.
40 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 13 : WRITE with VW
(Example at Single Bank Access with CL=2)
CLK
CLK
lRC = 4 clocks (minimum)
DESL
WRA
UA
LAL
WRA
LAL
DESL
Command
lRCD
lRAS
Address
@BL=4
LA +
VW=2
LA +
VW=1
Don’t Care
UA
Don’t Care
Last two data are masked.
D1 D2 D3 D4
Last three data are masked.
DQ
(Input)
@BL = 4
Don’t Care
Invalid
Don’t Care
D1 D2 D3 D4
WL=1
WL=1
DQS
(Input)
Invalid
@BL = 4
*1
*1
Address
@BL=2
LA +
VW=All
LA +
VW=1
Don’t Care
UA
UA
Don’t Care
All data are written.
D1 D2
Last one data is masked.
D1 D2
DQ
(Input)
@BL = 2
Don’t Care
Don’t Care
Invalid
Don’t Care
WL=1
WL=1
DQS
(Input)
Invalid
@BL = 2
*1
Dn
Dn
Valid Data Input
Masked Data
Notes: *1 DQS Inputmustbe continued till end ofburstcounteven ifsome oflater data is masked.
(AE1E) 41
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 14 : MODE REGISTER SET
(Example at BL=4 with CL=2)
CLK
CLK
lRC = 4 clocks (minimum)
lRSC = 4 clocks (minimum) *1
RDA or
WRA
2nd
command
RDA
LAL
DESL
RDA *2
MRS
Valid
DESL
Command
Address
lRCD
lRAS
lRCD
*3
BA,UA
LA
Don’t Care
BA,UA
Don’t Care
DQ
(Output)
@BL = 4
Hi-Z
Hi-Z
Q1 Q2 Q3 Q4
CL=2
DQS
(Output)
@BL = 4
Notes: *1 The minimum mode register set cycle time lRSC is the same as minimum lRC.
Read command (RDA+LAL) should be asserted after lLOCK at the initialization sequence.
*2 All banks must be in idle state or lRC of last open bank must be satisfied.
*3 The address information will be ignored when MRS command is asserted at next cycle.
42 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 15 : POWER DOWN
(Example at BL=2 with CL=2)
CLK
CLK
tIH
tIS
lRC (min), tREFI (max) *1
*3
PD
tQPDH
lPD *2
tPDEX
lPDA *2
RDA or
WRA
RDA
LAL
DESL
Command
DESL
Don’t Care
Don’t Care
DQ
(Output)
@BL = 2
Hi-Z
Hi-Z
Q1 Q2
CL=2
DQS
(Output)
@BL = 2
Notes: *1 PD should be brought to High within tREFI (max) to maintain the data written into cell.
*2 The PD to input enable/disable latency is 1 clock.
*3 All banks must be in idle state and tQPDH from last read data output must be satisfied.
TIMING DIAGRAM – 16 : AUTO-REFRESH
(Example at BL=4 with CL=2)
CLK
CLK
lRC (minimum)
DESL
lRCD
lREFC (minimum)
DESL
RDA or
WRA
RDA
LAL
WRA *1
REF *2
Command
DESL
DQ
(Output)
@BL = 4
Hi-Z
Hi-Z
Q1 Q2 Q3 Q4
CL=2
DQS
(Output)
@BL = 4
Notes: *1 All banks must be in idle state or lRC of last open bank must be satisfied.
*2 The write operation will be cancelled when REF command is asserted.
(AE1E) 43
MB81N26847A/261647A-22/-24/-30 Preliminary
■ TIMING DIAGRAMS (Continued)
TIMING DIAGRAM – 17 : SELF-REFRESH ENTRY
(Example at CL=2)
*3
CLK
CLK
lCKD = 16clocks (minimum) *1
tFPDL(min)
tFPDL(max)
lPD=1 cycle *4
PD
lPDV *5
WRA
REF
Hi-Z
Command
DQ, DQS
DESL
DESL
Don’t Care
lREFC (minimum) *2
tQPDH
Notes: *1 Clock input should be continued at least 16 clocks from REF command even though PD is brought
to Low for Self-refresh entry.
*2 DESL command must be asserted during lREFC period.
*3 Clock can be disabled after lCKD period from REF command when PD is brought to Low for Self-refresh.
*4 lPD is defined from the first clock rising edge after PD is brought to Low.
*5 PD must be brought to Low within the timing between tFPDL (min) and tFPDL (max) to Self-refresh mode.
When PD is brought to Low after lPDV, FCRAM perform Auto-refresh and enter Power Down mode.
44 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
TIMING DIAGRAM －18 : SELF-REFRESH EXIT
*5
CLK
CLK
tPDEX
lLOCK (minimum) *4
PD
lREFC (min) *1
lRCD
lREFC (min)
DESL
WRA*2
Command *3
RDA *4
LAL
Command
DQ, DQS
Don’t Care
DESL *1
REF*2
Hi-Z
Notes: *1 DESL command must be asserted during lREFC period after PD is brought to High.
*2 One REF command should be asserted just after Self-refresh exit before any other operation.
*3 Any command other than read command can be issued after Auto-refresh period.
*4 Read command (RDA + LAL) can be issued after lLOCK period.
*5 Clock should be stable prior to PD = High if clock input is suspended during Self-refresh.
(AE1E) 45
TIMING DIAGRAM － 19 : POWER-UP INITIALIZATION and RESET
CLK
CLK
High
PD
4 clocks (min)
1 clock
1 clock
5 clocks (min)
lRCD
RDA or
WRA
2nd
Command
Command
BA[1:0]
A[14:7]
DESL
RDA
MRS
DESL
(Maintail DESL command.)
Note *3
Note *4
X
X
X
1 *1
Key-1 *1
X
Key-2 *2
Valid
Valid
BA1 orBA0 =0
Valid
Valid
Valid
Valid
A8=0 or A7=1
Key-2 *2
A[6:0]
X
X
X
X
X
X
X
X
X
Don’t Care (X)
Hi-Z
DQ, DQS
Notes: *1 BA[1:0] and A[14:8] must be High (1) and A7 must be Low (0), and those value must be maintained for 4 clocks.
*2 At least one address must be flipped and maintained at least 5 clocks.
*3 DESL condition must be maintained for 12 clocks when RESET is being performed.
*4 Ready for normal operation after RESET or start MRS programming and Auto-refresh at Power-up Initialization.
MB81N26847A/261647A-22/-24/-30 Preliminary
■ PACKAGE DIMENSIONS (TENTATIVE)
*: Resin protrusion. (Each side: 0.15 (.006) MAX)
66-pin plastic TSOP (II)
(FPT-66P-M01)
66
34
Details of "A" part
0.25(.010)
0°~8°
INDEX
0.45/0.75
(.018/.030)
1
33
LEAD No.
*22.22±0.10(.875±.004)
11.76±0.20(.463±.008)
1.15±0.05(.045±.002)
(Mounting height)
10.16±0.10(.400±.004)
0.145 +–00..0035
.006 –+..000012
"A"
0.65(.026)
TYP
0.24 –+00..0078
0.10±0.05(.004±.002)
(Stand off)
M
0.13(.005)
0.10(.004)
.009 –+..000033
20.80(.819)REF
Dimensions in mm (inches)
(AE1E) 47
MB81N26847A/261647A-22/-24/-30 Preliminary
MEMO
48 (AE1E)
MB81N26847A/261647A-22/-24/-30 Preliminary
MEMO
(AE1E) 49
MB81N26847A/261647A-22/-24/-30 Preliminary
FUJITSU LIMITED
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F0105
FUJITSU LIMITED Printed in Japan
50 (AE1E)
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